Amrita Vishwa Vidyapeetham

Amrita School of Engineering, Bengaluru Campus

Department of ECE
End Semester Examination August 2021
19EAC111 – Digital Circuits and Systems
B. Tech.- II Semester EAC
Time: 90 Minutes Max Marks- 50

CO Course Outcomes
CO1 Understand the basics of Boolean logic, number system and codes for representing Boolean
variables
CO2 Develop Boolean equations and truth tables for synthesis using different logic gates and
optimize the Boolean function using different minimization methods
CO3 Analysis and Synthesis of multiple output function and its optimization

CO4 Design of various combinational circuits.

CO5 Understanding various sequential circuit elements and its conversions

CO6 Develop various synchronous sequential circuits and analyze

Answer all the Questions

1. A combinational circuit which is used to convert few inputs to many outputs is called as ______
[CO4]
[1M]
2. 1:32 size De-Multiplexer is equivalent to ........size of Decoder. [C04]
[1M]
3. How many flip-flops are required to build a counter that counts from 0 to 4095? [CO5]
[1M]
4. The output Q0Q1Q2Q3Q4 of a 5-bit Ring counter on the 5th clock pulse is _________. (Assume Q0
being the LSB and initial state as 01000). [CO5]
[1M]
5. An asynchronous 3-bit down counter changes its count from 3 onwards down to 4. How many
clock cycles are required to have this change? [CO5]
[1M]
6. For a 5-bit Johnson Counter, if the present count Q0Q1Q2Q3Q4 = 10000. What must be the count
on Q0Q1Q2Q3Q4 in the previous clock cycle? (Assume Q0 as LSB bit). [CO5]
[1M]

7. A Finite State Machine is said to be Moore state machine, if ___________________ [CO6]

[1M]
8. Moore state machine has ___________ states than in Mealy state machine. [CO6]
[1M]

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9. Why in Moore state machine more logic is required to decode the outputs. [CO6]
[2M]
10. Determine the decimal values of the following unsigned numbers:
a. (1101001011)2 [CO1]
b. (CD93)16 [3M]

11. Find the minimum-cost SOP forms for the function:

f (x1, x2, x3, x4) = m(2, 4, 6, 9,11,12,13)+ D(1, 3, 8, 14). Implement the minimum-cost function
using only NAND gates. [CO2]
[3M]
12. Implement A circuit with two outputs has to implement the following functions:
f (a, b, c, d) = ПM (1,3,8,10,12,13,15). D (2,11)
g (a, b, c, d) = ПM (2,5,4,,10,11). D (3,9)
Assume that the input variables are available in both uncomplemented and complemented forms at free
of cost.
i) Obtain the minimum cost POS for f when designed separately and find its cost. [CO3]
ii) Obtain the minimum cost POS for g when designed separately and find its cost. [8M]
iii) Find the total cost when f and g are designed separately.
iv) Draw a combined circuit for f and g. Obtain the total cost when f and g are designed together.

13. Design an efficient digital circuit for the following operation using Adder/Subtractor unit. Assume
the variables are 8 bit binary numbers. [CO4]
D =12A  2B [6M]

14. Convert a positive edge triggered PQ flip flop to T flip flop where PQ flip-flop’s characteristic table is
defined as follows: [CO5]
Case 1: PQ = 00 flip flop remains same as previous state, [4M]
Case 2: PQ = 01 results in reset state,
Case 3: PQ = 10 results in set state,
Case 4: PQ = 11 changes to complement of previous state.
The resultant circuit of the conversion shows P input connection as ______ and Q input connection as
________.

15. Consider a 4-bit Serial-in-parallel-out right-shift shift register. The input bit stream applied to shift
register is 101101(MSB bit is first serial input bit). Write the content of shift register Q 3Q2Q1Q0 for 4
consecutive clock cycles if the initial content of shift register is 0111. (Assume Q3 is the output of flip-
flop in which serial input is applied).
(Note: Start with the initial content and write the content Q3Q2Q1Q0 for 4 consecutive clock cycles
separated by comma). [CO5]
[4M]

16. Consider a 3-bit synchronous counter designed with positive edge triggered T flip flops. The counter
has 3-bit output Q0Q1Q2 where Q0 is LSB bit and Q2 is MSB bit. The T input of first flip-flop (providing
output Q0) is always high. The T input of second flip-flop is connected to Q0 and T input of third flip-
flop is connected to Q1. Write the count sequence Q0Q1Q2 for the mentioned counter. Assume initially
Q0Q1Q2 = 011. [CO5]
[4M]

17. Consider a circuit where D flip-flop’s output ‘QD’ is connected to the input of T flip-flop. The output
of this circuit is observed from the ‘QT’ output of the T flip-flop. What is the sequence of output
observed on the ‘QT’ output of the T flip-flop for the four consecutives clock cycles, if the input
sequence applied on D is (assume one bit in one clock cycle) ‘1’, ‘1’, ‘0’, and ‘0’. Assume both flip-
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 flops as positive edge triggered and with same clock signal. Assume the output of both the flip-flop
“QDQT” = “00” initially.
(Note: Write the answer in (D T QT) format for mentioned 4 clock cycles. Use comma to indicate your
answer for different clock cycles.) [CO4]
[4M]

18. Consider a negative edge triggered T flip-flop with input T and output Q and Q’. Consider a primary
input D and T = D XOR Q. If the input sequence applied on D is (assume one bit in one clock cycle)
‘1’, ‘1’, ‘0’, and ‘0, then find the output sequence observed on output Q for these 4 clock cycles.
Assume initially Q = 0 Please provide your answer only in the format shown below.
(Note: Write the answer in (D T Q) format for mentioned 4 clock cycles. Use comma to indicate
your answer for different clock cycles.) [CO4]
[4M]

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