MCA I SEMESTER

COMPUTER ORGANIZATION AND ARCHITECTURE

UNIT –I
(SYLLABUS Unit I)

Number Systems: Binary, Octal, Hexa decimal numbers, base conversion, addition,
subtraction of binary numbers, one's and two's complements, positive and negative numbers,
character codes ASCII, EBCDIC etc. Computer Arithmetic: Addition and Subtraction,
Multiplication and Division algorithms, Floating-point Arithmetic Operations, Decimal
arithmetic operations. Structure of Computers: Computer types, Functional units, Basic
operational concepts, Von- Neumann Architecture, Bus Structures, Software, Performance,
Multiprocessors and Multicomputer, Digital Logic Circuits: Logic gates, Boolean algebra, Map
Simplification. Combinational Circuits: Half Adder, Full Adder, flip flops,
Sequentialcircuits:Shiftregisters,Counters,IntegratedCircuits,Mux,Demux,Encoder,Decoder,Data
Representation: Fixed and Floating point,Error detection and correction codes.

NUMBER SYSTEMS
Number system is a basis for counting varies items. Modern computers communicate
and operate with binary numbers which use only the digits 0 &1. Basic number system used by
humans is Decimal number system. For Ex: Let us consider decimal number 18. This number is
represented in binary as 10010.

• To define any number system we have to specify Base of the number system such as 2,8,10
or 16.
• The base decides the total number of digits available in that number system.
• First digit in the number system is always zero and last digit in the number system is always
base-1.
Binary number system: The binary number has a radix of 2. As r = 2, only two digits are
needed, and these are 0 and 1. In binary system weight is expressed as power of 2.
Decimal Number system The decimal system has ten symbols: 0,1,2,3,4,5,6,7,8,9. In other
words, it has a base of 10.
Octal Number System Digital systems operate only on binary numbers. Since binary numbers
are often very long, two shorthand notations, octal and hexadecimal, are used for representing
large binary numbers. Octal systems use a base or radix of 8. It uses first eight digits of decimal

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number system. Thus it has digits from 0 to 7.
Hexa Decimal Number System The hexadecimal numbering system has a base of 16. There
are 16 symbols. The decimal digits 0 to 9 are used as the first ten digits as in the decimal system,
followed by the letters A, B, C, D, E and F, which represent the values 10, 11,12,13,14 and 15
respectively.

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 Complements:

In digital computers to simplify the subtraction operation & for logical manipulation
complements are used.

There are two types of complements used in each radix system.

i) The radix complement or r’s complement

ii) ii) The diminished radix complement or (r-1)’s complement
Representation of signed no.s binary arithmetic in computers:
• Two ways of rep signed no.s
1. Sign Magnitude form
2. Complemented form
• Two complimented forms
1. 1‘s compliment form
2. 2‘s compliment form
Advantage of performing subtraction by the compliment method is reduction in the
hardware.( instead of addition & subtraction only adding ckt‘s are needed.)

i.e, subtraction is also performed by adders only.

Instead of subtracting one no. from other the compliment of the subtrahend is added
to minuend. In sign magnitude form, an additional bit called the sign bit is placed in
front of the no. If the sign bit is 0, the no. is +ve, If it is a 1, the no is _ve.

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Representation of signed no.s using 2’s or 1’s complement method:
If the no. is +ve, the magnitude is rep in its true binary form & a sign bit 0 is placed in front of
the MSB.I f the no is _ve , the magnitude is rep in its 2‘s or 1‘s compliment form &a sign bit 1 is
placed in front of the MSB.

Signed binary numbers:

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 2’s compliment Arithmetic:

• The 2‘s comp system is used to rep –ve no.s using modulus arithmetic . The word
length of a computer is fixed. i.e, if a 4 bit no. is added to another 4 bit no . the result
will be only of 4 bits. Carry if any , from the fourth bit will overflow called the Modulus
arithmetic. Ex:1100+1111=1011

•In the 2‘s compl subtraction, add the 2‘s comp of the subtrahend to the minuend . If
there is a carry out , ignore it , look at the sign bit I,e, MSB of the sum term .If the MSB
is a 0, the result is positive.& it is in true binary form. If the MSB is a ` ( carry in or no
carry at all) the result is negative.& is in its 2‘s comp form. Take its 2‘s comp to find its
magnitude in binary.

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Binary codes

Binary codes are codes which are represented in binary system with modification from
the original ones.

Weighted Binary codes

Non Weighted Codes

Weighted binary codes are those which obey the positional weighting principles, each
position of the number represents a specific weight. The binary counting sequence is
an example.

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Non weighted codes

Non weighted codes are codes that are not positionally weighted. That is, each position within the
binary number is not assigned a fixed value. Ex: Excess-3 code

Excess-3 Code

Excess-3 is a non weighted code used to express decimal numbers. The code derives its name from
the fact that each binary code is the corresponding 8421 code plus 0011(3).

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Gray Code

The gray code belongs to a class of codes called minimum change codes, in
which only one bit in the code changes when moving from one code to the next.
The Gray code is non-weighted code, as the position of bit does not contain any
weight. The gray code is a reflective digital code which has the special property that
any two subsequent numbers codes differ by only one bit. This is also called a unit-
distance code. In digital Gray code has got a special place

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 Error – Detecting codes:

When binary data is transmitted & processed,it is susceptible to noise that

can alter or distort its contents. The 1‘s may get changed to 0‘s & 1‘s .because digital systems must
be accurate to the digit, error can pose a problem. Several schemes have been devised to detect
the occurrence of a single bit error in a binary word, so that whenever such an error occurs the
concerned binary word can be corrected & retransmitted.

Parity: The simplest techniques for detecting errors is that of adding an extra bit known as parity
bit to each word being transmitted.Two types of parity: Oddparity, evenparity forodd parity, the
parity bit is set to a ‗0‘ or a ‗1‘ at the transmitter such that the total no. of 1 bit in the word
including the parity bit is an odd no.For even parity, the parity bit is set to a ‗0‘ or a ‗1‘ at the
transmitter such that the parity bit is an even no.

When the digit data is received . a parity checking circuit generates an error signal if the total no
of 1‘s is even in an odd parity system or odd in an even parity system. This parity check can always
detect a single bit error but cannot detect 2 or more errors with in the same word.Odd parity is
used more often than even parity does not detect the situation. Where all 0‘s are created by a
short ckt or some other fault condition.

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The circuit consists of one XOR and one XNOR gate

The message and the odd parity bits are transmitted to the destination when they are
applied to a parity checker.

An error has occurred during the transmission if the parity of the four bits received is even
since the binary information transmitted was originally odd.The output of the parity
checker would be 1 when an error occurs.

Binary Arithmetic
Binary Addition Rules
Binary addition is performed in the same manner as decimal addition. However, since
binary number system has only two digits, the addition table for binary arithmetic is
very simple consisting of only four entries. The complete table for binary addition is
given below.

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Binary Addition Table

In Binary Number Addition carry-overs are performed in the same manner as in

Decimal Addition. Since 1 is the largest digit in the Binary Number System, any sum
greater than 1 requires that a digit to be carried over. For instance,

The sum of 10 plus 10 binary numbers requires the addition of two 1's in the second
position. Since 1 + 1 = 0 plus a carry of 1 therefore the sum of 10 + 10 is 100 in Binary
System.

By the repeated use of the above rules any two binary numbers can be added together by
adding two bits at a time.

Binary Subtraction Rules

The principles of decimal subtraction can as well be applied to subtraction of numbers
in other cases. It consists of two steps, which are repeated for each column of the
numbers.

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 • The first step is to determine if it is necessary to borrow. If the subtrahend (the lower
digit) is larger than the minuend (the upper digit), it is necessary to borrow from the column to
the left. It is also important to note here that the valued borrowed depends upon the base of
the number.
• The second step is simply to subtract the lower value from the upper value. The
complete table for binary subtraction is given below.

Binary Subtraction Table

Binary Multiplication Rules

Multiplication in the binary system also follows the same general rules as decimal multiplication.
However, learning the binary multiplication is a trivial task because the table for binary
multiplication is very short, with only four entries instead of the 100 necessary for decimal
multiplication. The complete table for binary multiplication is given below.

Binary Multiplication Table

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Binary Division

Binary division is again very simple. As in the decimal system (or in any other number
system), division by 0 is meaningless. Hence, the complete table for binary division is
given below.

The division process is performed in a manner similar to decimal division. The rules for
binary division are:

1. Start from the left of the dividend.

2. Perform a series of subtraction in which the divisor is subtracted from the
dividend.

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3.If subtraction is possible, put a 1 in the quotient and subtract the divisor from the corresponding
digits of dividend.

4.If subtraction is not possible (divisor is greater than remainder), record a 0 in the quotient.

5.Bring down the next digit to add to the remainder digits. Proceed as before in a manner similar to
long division.

Step 1: Divisor greater than 100, so put 0 in quotient.

Step 2: Add digit from dividend to group used above.
Step 3: Subtraction possible so put 1 in the quotient.
Step 4: Remainder from subtraction plus digit from dividend
Step 5: Divisor greater, so put 0 in quotient.
Step 6: Add digit from dividend to group.
Step 7: Subtraction possible, so put 1 in quotient.
Subtraction by 2’s Complement

The operation is carried out by means of the following steps:

(i) At first, 2’s complement of the subtrahend is found.

(ii) Then it is added to the minuend.

(iii) If the final carry over of the sum is 1, it is dropped and the result is positive.

(iv) If there is no carry over, the two’s complement of the sum will be the result and it is negative.

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(i) 110110 - 10110

Solution:

The numbers of bits in the subtrahend is 5 while that of minuend is 6. We make the
number of bits in the subtrahend equal to that of minuend by taking a `0’ in the sixth
place of the subtrahend.

Now, 2’s complement of 010110 is (101101 + 1) i.e.101010. Adding this with the
minuend.

1 10110 Minuend

1 01010 2’s complement of subtrahend

Carry over 1 1 00000 Result of addition

After dropping the carry over we get the result of subtraction to be 100000.

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 Digital Logic Gates

Boolean functions are expressed in terms of AND, OR, and NOT operations, it is easier to
implement a Boolean function with these type of gates.

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 K MAP

A K-map provides a systematic method for simplifying Boolean expressions and, if

properly used, will produce the simplest SOP or POS expression possible, known as the
minimum expression.

It’s similar to truth table; instead of being organized (i/p and o/p) into columns and
rows, the K-map is an array of cells in which each cell represents a binary value of the
input variables.

The cells are arranged in a way so that simplification of a given expression is simply a
matter of properly grouping the cells.

K-maps can be used for expressions with 2, 3, 4, and 5 variables.

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 NOTE:PRACTICE MORE PROBLEMS OF K MAP

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 COMBINATIONAL CIRCUITS

Combinational Logic

• Logic circuits for digital systems may be combinational or sequential.

• A combinational circuit consists of input variables, logic gates, and output variables.

For n input variables,there are 2n possible combinations of binary input variables .For
each possible input Combination ,there is one and only one possible output combination.A
combinational circuit can be described by m Boolean functions one for each output variables.Usually
the input s comes from flip-flops and outputs goto flip-flops.

Half Adder:

A Half Adder is a combinational circuit with two binary inputs (augends and addend bits and
two binary outputs (sum and carry bits.) It adds the two inputs (A and B) and produces the sum (S)
and the carry (C) bits. It is an arithmetic operation of addition of two single bit words.

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 The Sum(S) bit and the carry (C) bit, according to the rules of binary addition, the
sum (S) is the X-OR of A and B ( It represents the LSB of the sum). Therefore,

The carry (C) is the AND of A and B (it is 0 unless both the inputs are 1).Therefore,
C=AB

A half-adder can be realized by using one X-OR gate and one AND gate

The Full Adder:

A Full-adder is a combinational circuit that adds two bits and a carry and
outputs a sum bit and a carry bit. To add two binary numbers, each having two or
more bits, the LSBs can be added by using a half-adder. The carry resulted from the
addition of the LSBs is carried over to the next significant column and added to the
two bits in that column. So, in the second and higher columns, the two data bits of
that column and the carry bit generated from the addition in the previous column
need to be added.

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 The full-adder adds the bits A and B and the carry from the previous column
called the carry-in Cin and outputs the sum bit S and the carry bit called the carry-
out Cout . The variable S gives the value of the least significant bit of the sum. The
variable Cout gives the output carry.The eight rows under the input variables
designate all possible combinations of 1s and 0s that these variables may have. The
1s and 0s for the output variables are determined from the arithmetic sum of the
input bits. When all the bits are 0s , the output is 0. The S output is equal to 1 when
only 1 input is equal to 1 or when all the inputs are equal to 1. The Cout has a carry
of 1 if two or three inputs are equal to 1.

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 Sequential Circuits
The following figure shows the block diagram of sequential circuit.

This sequential circuit contains a set of inputs and output(s).

The output(s) of sequential circuit depends not only on the combination of present
inputs but also on the previous output(s). Previous output is nothing but the present
state. Therefore, sequential circuits contain combinational circuits along with
memory (storage) elements. Some sequential circuits may not contain combinational
circuits, but only memory elements.

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 Flip-Flops

A flip-flop is a storage element based on the gated latch principle

It can have its output state changed only on the edge of the controlling clocksignal

SR Flip-Flop

SR flip-flop operates with only positive clock transitions or negative clock transitions

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EXCITATION TABLE

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EXCITATION TABLE OF JK and T Flipflop

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 Decoder

Decoder is a combinational circuit that has „n‟ input lines and maximum of 2n output lines. One of these
outputs will be active High based on the combination of inputs present, when the decoder is enabled.
That means decoder detects a particular code. The outputs of the decoder are nothing but the min
termsof „n‟ input variables (lines), when it is enabled.

2 to 4 Decoder:

Let 2 to 4 Decoder has two inputs A1 & A0 and four outputs D3, D2, D1 & D0. The block diagram of 2 to
4 decoder is shown in the following figure.

2 to 4 NAND gate decoder

If enable, E is zero, then all the outputs of decoder will be equal to zero

3 to 8 line Decoder

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 Encoder:

An Encoder is a combinational circuit that performs the reverse operation

of Decoder. It has maximum of 2n input lines and „n‟ output lines. It will produce a
binary code equivalent to the input, which is active High. Therefore, the encoder
encodes 2n input lines with „n‟ bits. It is optional to represent the enable signal in
encoders.

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 Multiplexer

Multiplexer is a combinational circuit that has maximum of 2n data inputs, „n‟

selection lines and single output line. One of these data inputs will be connected to the output
based on the values of selection lines. Since there are „n‟ selection lines, there will be 2n possible
combinations of zeros and ones. So, each combination will select only one data input.

4x1 Multiplexer:

4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one
output Y. The block diagram of 4x1 Multiplexer is shown in the following figure.

One of these 4 inputs will be connected to the output based on the combination of
inputs present at these two selection lines. Truth table of 4x1 Multiplexer is shown below

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 From Truth table, we can directly write the Boolean function for output,

Y as Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I2Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I2 We
can implement this Boolean function using Inverters, AND gates & OR gate.

The circuit diagram of 4x1 multiplexer is shown in the following figure

shift register:

If the register is capable of shifting bits either towards right hand side or
towards left hand side is known as shift register. An „N‟ bit shift register contains „N‟
flip-flops. Following are the four types of shift registers based on applying inputs and
accessing of outputs.

The shift register, which allows serial input and produces serial output is
known as Serial In – Serial Out (SISO) shift register. The block diagram of 3-bit SISO shift
register is shown in the following figure.

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 This block diagram consists of three D flip-flops, which are cascaded. That means, output
of one D flip-flop is connected as the input of next D flip-flop.

All these flip-flops are synchronous with each other since, the same clock signal is applied
to each one.

In this shift register, we can send the bits serially from the input of left most D flip-flop.
Hence, this input is also called as serial input.

For every positive edge triggering of clock signal, the data shifts from one stage to the
next. So, we can receive the bits serially from the output of right most D flip-flop. Hence, this output
is also called as serial output.

BIDIRECTIONAL SHIFT REGISTER WITH PARALLEL LOAD

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 • When S1 S0 = 10, input 2 of the MUX is selected.. The serial input SI is transferred
into the leftmost bit (i.e. MSB) in this case. SHIFT RIGHT

• Finally, when S1 S0 = 11, input 3 of thWhen S1 S0 = 00, input 0 of the MUX is selected.
This forms a path from the output of the FF into its own input, which causes the same
value to be loaded in the D FF when a clock pulse is applied. This results in the NO
CHANGE operation.

• When S1 S0 = 01, input 1 of the MUX is selected. The serial input SI is transferred
into the rightmost bit in this case. SHIFT LEFT

• e MUX is selected. On this input, the binary information on the parallel input line Di
is transferred into the FF, resulting in PARALLEL LOAD operation.

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 DESIGN STATE DIAGRAM

• Derive the State equation

• Derive the state table from state equations
• State table

• Similar to truth table

• Left side-Present and Input state

• Right side-Outputs and Next state

• If M flipflops then no of present state=M

• If N inputs then no of inputs=N

• No of rows=2^(M+N)

State Diagram

Rep by binary states (present states).

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 NOTE:Practice more problems

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