Register No: 20BLC1123 Name: Jaswanth Sai K R

Date:12/08/21 Exp 2: Study and Verification of HALF-ADDER,

HALF-SUBTRACTOR, FULL-ADDER, FULL-SUBTRACTOR.

Aim : Verify the truth table for HALF-ADDER, HALF-SUBTRACTOR, FULL-

ADDER, FULL-SUBTRACTOR.
Software Required: Logic Gate Simulator.

PROCEDURE:
1. Place the USERINPUT blocks in the workspace of the Logic Gate
Simulator according to the number of inputs required for the Boolean
expressions
2. Place the required gates in the workspace and connect the USERINPUT
blocks to the gates
3. Place the USEROUTPUT block near the gate and connect them
4. Switch the inputs from ON to OFF and vice versa and verify the truth
table.
Acquire the Boolean expressions and verify the truth table of the HALF-ADDER,
HALF-SUBTRACTOR, FULL-ADDER, FULL-SUBTRACTOR.
5. LOGIC DIAGRAMS:
1) HALF ADDER:
Register No: 20BLC1123 Name: Jaswanth Sai K R

2) HALF SUBTRACTOR:

3) FULL ADDER:

4) FULL SUBTRACTOR:
Register No: 20BLC1123 Name: Jaswanth Sai K R

OUTPUT AND TRUTH TABLE:

1) HALF ADDER:

A B SUM CARRY
0 0 0 0

2)

A B SUM CARRY
0 1 1 0

3)

A B SUM CARRY
Register No: 20BLC1123 Name: Jaswanth Sai K R

1 0 1 0

A B SUM CARRY
1 1 0 0

2) HALF SUBTRACTOR:

A B DIFFERENCE BORROW
0 0 0 0
Register No: 20BLC1123 Name: Jaswanth Sai K R

0 1 1 1

1 0 1 0

1 1 0 0

3) FULL ADDER:

A B CIN SUM CARRY

Register No: 20BLC1123 Name: Jaswanth Sai K R

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1
Register No: 20BLC1123 Name: Jaswanth Sai K R

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1
Register No: 20BLC1123 Name: Jaswanth Sai K R

4) FULL SUBTRACTOR:

A B Bi DIFFERENC BORRO
n E W
0 0 0 0 0
Register No: 20BLC1123 Name: Jaswanth Sai K R

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0
Register No: 20BLC1123 Name: Jaswanth Sai K R

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1
Register No: 20BLC1123 Name: Jaswanth Sai K R

RESULT:
The circuits of the HALF-ADDER, HALF-SUBTRACTOR, FULL-ADDER, FULL-
SUBTRACTOR are designed and the truth tables of the gates are verified.