Begins 

at: 10:30 AM, Wednesday, August 8th

2018 ARDC India
Red Track, Session 2
Highly Accelerated Life Testing
A Next Generation Testing Tool Towards 
Quality & Reliability Assurance for Complex Electronics 
Hardware Systems
Mustaq Basha1, B Sajidha Thabassum2, Anand 
Dambal3 and KS Suryaprakash4
MUSTAQ  BASHA, Sc ‘E’
Certified Reliability Engineer (ASQ)
LRDE,DRDO
Ministry of Defence (MOD) 
CV Raman Nagar
Bangalore ‐93
mustaq.basha@lrde.drdo.com
 PRESENTATION SLIDES
The following presentation was delivered at the:

Applied Reliability and Durability Conference, India

August 8 - 10, 2018: Chennai, India
http://www.ardconference.com

The Applied Reliability and Durability Conference (ARDC) is intended to be a forum for reliability, maintainability and
durability practitioners within industry and government to discuss their success stories and lessons learned regarding
the application of reliability and durability techniques to meet real world challenges. Each year, the ARDC issues an
open "Call for Presentations" at http://www.ardconference.com and the presentations delivered at the Conference are
selected on the basis of the presentation proposals received.

Although the ARDC may edit the presentation materials as needed to make them ready to print, the content of the
presentation is solely the responsibility of the author. Publication of these presentation materials in the ARDC
Proceedings does not imply that the information and methods described in the presentation have been verified or
endorsed by the ARDC and/or its organizers.

The publication of these materials in the ARDC presentation format is

Copyright © 2018 International Applied Reliability Symposium LLC, All Rights Reserved.
Content

 Introduction to HALT/HASS
 Design of test fixtures for HALT/HASS Test
 Case Study– HALT of TRMs
 Challenges faced during HALT
 HASS Profile release for Production screening
 Benefits of HALT/HASS

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 2

 HALT
Highly Accelerated Life
Test
A process used during the
design stage of a product
that provides a stringent
environment to force
design and process
maturity.
Mustaq  Basha, LRDE, DRDO
HASS
Highly Accelerated Stress
Screen
A process used in
manufacturing, to
HALT Knowledge allow discovery of
process changes and
prevent products with
latent defects from
getting into the field.
Red Track Session 2 Slide Number: 3
 Old Paradigm New Paradigm

 Test to verify conformance to 
 Stress to measure design 
Specifications
margin
 Repair field returns
 Treat field failures as 
 Extended “Burn‐in” opportunities for process 
 Ship to specifications = OK improvement
 HALT/HASA

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 4

There Are Two Causes For Product
Failure

• DESIGN
Specifically lack of design margin

• MANUFACTURING PROCESS
Variability of process, including your upstream
suppliers processes

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 5

HALT – What Is It?
 Design Tool (Used in Design Stage):

 Owned by engineering

 A method to quickly expose weak links of the designs

 Perform Root Cause Failure Analysis and Corrective Action

 Tool with a different purpose:

 Not a Design Verification Test or Qualification Test

 Goal is to find defects and correct them

 Can Not equate results to product LIFE or predict a MTBF!!

 Does not replace, but complements Existing Testing

 Different goal – Different method – Different equipment

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 6
HALT Fundamentals

 HALT is not a test you pass or fail, it is a 
process tool for the design engineers.
 There are no pre‐established limits – the 
product determines the limits.
 Stress to failure.
 For optimum results, monitor product during 
stressing.

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 7

Should I Design to HALT Limits?

Absolutely NOT!

 Design for Normal Limits.

 Let HALT tell you where the weak
links are.
 Use information found in HALT in the
design phase itself to eliminate the
weak links ahead of time.

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 8

Percentage Environmental Failure
contribution
Altitude2%
Others 1%

Corrosion 2%

Humidity 5%

Combined Vibration &

Temperature
VIBRATION 15%
50%

Temperature 25%

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 9

HALT, How It Works

Start low and step up the

stress, testing the product
during the stressing

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 10

HALT, How It Works

Gradually increase
stress level until a
failure occurs

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 11

HALT, How It Works

Analyze
the failure

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 12

HALT, How It Works

Make
temporary
improvements
Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 13
HALT, How It Works
Increase
stress and
start
process
over

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 14

HALT, How It Works

Fundamental
Technological
Limit

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 15

 HALT Diagram
Lower Lower Upper Upper
Destruct Operating Product Operating Destruct
Limit Limit
Operating
Specs Limit Limit
Operating
Margin Margin
Destruct Margin Destruct Margin

Precipitation Screen
Detection Screen

Stress

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 16

 HALT Diagram Sequence
Upper Destructive
Limit

Upper Operating
Limit Upper
Destructive
Upper Operating Margin Margin
Upper Specification
Limit HALT Vibration Stress

Upper Product
Specification
HALT Temp Stress
Proof of Screen
Product
(HASS) Product
Specification
Specification(DVT).

Lower product
Specification

Lower Specification Lower Operating Margin

Limit Lower
Destructive
Lower Operating Margin
Limit
Lower Destruction
Limit

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 17

 HALT / HASS TYPICAL TEST 

SEQUENCE

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 18

 Step Stress Process

• Cold

• Hot

• Rapid Thermal

• Vibration

• Combined
Environment
Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 19
 Thermal Stress

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 20

 Pseudo Random Vibration System

• Excites six axes, 3 linear & 3 rotational

• Broadband (10 Hz to 10 KHz) random vibration

Note: Repetitive shock system used for HALT are equipped with multiple pneumatic actuators that
randomly strikes from the bottom of the semi rigid table, This system stimulates the product at
much wider range of frequencies than those used in DVT, simulating all 6DOF vibrations. This will
rapidly drive poor solder joint or weak mechanical connection to failure.
Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 21
 Vibration Step Stress

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 22

Combined HALT Environment

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 23

Typical HALT Approach

• After HALT is completed..

• Formal Test Report is prepared

• HALT data is used to plan HASS procedure

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 24

 HASS – Highly
Accelerated Stress
Screen

Sec 3
Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 25
 HALT Diagram

Lower Lower Upper Upper

Destruct Operating Product Operating Destruct
Limit Limit
Operating
Specs Limit Limit
Operating
Margin Margin
Destruct Margin Destruct Margin

Precipitation Screen
Detection Screen

• Temperature - 80% of DLs

Stress
• Vibration - 50% of DL

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 26

Developing a HASS Profile

• The 80/50 Rule

– 80% of the Temperature Limits found in
HALT, and 50% of the Vibration Limits
found in HALT
• The 10oC Rule
– Maintain minimum of 10oC from Limits

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 27

 HASS TEST PROCESS
Proof-of-Screen (POS)
• 2 to 4 new samples
• 10 to 50 (X) times the proposed production
HASS
• Must not have fatigue failure or visible damage
• If workmanship latent defect found, may be
repaired and used to complete POS, but using a
new sample would be better if time allows
• The units used for the POS are not to be shipped
but may be used for in-house testing

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 28

 Temperature (C) / Vibration (Grms)

-50
-30
-10
10
30
50
70
90
0:00
0:20
0:40
1:00
1:20
1:40
2:00
2:20
2:40
3:00
3:20
3:40
4:00
4:20

Mustaq  Basha, LRDE, DRDO
4:40
5:00
5:20
5:40

Temp Setpoint
6:00
6:20
6:40
7:00
7:20
7:40
8:00
8:20
8:40
9:00

Time
9:20
9:40
10:00
10:20
10:40

Red Track
11:00
PROOF OF SCREEN (POS)

11:20
11:40
12:00
12:20
HASS Development Product Life Valuation - 15 Runs

12:40
13:00
13:20
13:40
14:00
Session 2
14:20
Vib Setpoint

14:40
15:00
15:20
15:40
16:00
16:20
16:40
17:00
17:20
17:40
Slide Number: 29
A Typical Single HASS Profile

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 30

 HALT/HASS Testing of X-QTRMs
1:4 way 
power 
divider Height = 5 mm
Circulator
76 mm HPA

LPF

Radiating Elements
FPGA
65.8 mm

DC/Control
Signal 
Connector

Core Chip HPF
Limiter

Layout of X-QTRM Lid cover open: X-QTRM

 The Transmit/Receive Modules (T/R Modules) are the basic building blocks for Active Array Antennas

 Four numbers of T/R Modules is housed in a single package called as the Quad-TRM or Q-TRM.

 Q-TRM may be called QTRM-X (in X -Band) and integrated with 1:4 ways RF power combiners.

 Q-TRM should be controlled by QTRM Controller (FPGA based controller).

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 31

 PC check during HALT Test

PRE-ET IN-SET POET

Sl.
Test Parameter (Pre -environmental (During (Post -
No.
test) Test) environmental test)
DC and link Test
1 √ -- √
(Power Consumption)
2 Peak Transmit Output Power √ √ √

3 Pulse rise/fall time and Droop √ -- √

4 Receive Noise Figure √ √ √
5 Receive path gain √ √ √
Phase shifter in both Tx & Rx √ -- √
6 and attenuator states in Rx
mode (Prime states)
7 Input /output Return Loss √ -- √
BIT Test
8 (Temp, Volt and power √ -- √
monitoring)

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 32

 Flow Chart of HALT and HASS – X QTRMs
during Development and Certification phase

Step I (Sample-I) Step II (Sample –II, III)

Equipment  HASS on two 
Design Units(II & III)

HALT Passed
Conduct LQT on  Clear Sample III
Step Stress for integration
of the sample

Establish
UOL & UDL / 
LOL & LDL Complete QT on
Sample II

Define
HASS Limits

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 33

 Flow Chart of HALT and HASS Test during 
Development and Certification phase – X QTRMs
POS on another Unit Step III (Sample IV)
Perform HASS Cycle(Combined temp & vibration 
test)

Carry out 20 HASS cycles

Test  Fail Tailor the 

Pass/ Fail HASS limits

Pass
Final Destructive HALT

Check for UOL & UDL/
LOL & LDL limits

Are limits Y
Finalize the HASS levels
same?

N Production Clearance
Redefine HASS levels Based on the new 
limits HASS on each unit of production

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 34

HALT/HASS Sequence X QTRMs

Conduct HALT &

Define UDL,UOL & Define HASS Limit
LDL LOL

Sample I

Conduct HASS Conduct QT on II &

on both the get field Trial on III
samples

Sample II &III

Conduct HALT &

Conduct & Confirm
Redefine UDL,UOL &
HASS limits LDL LOL

Sample IV

Redefine HASS Limit Production clearance

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 35

HALT Test: Dummy Modules with bare
PCB enclosed

X Band QTRM Mechanical Enclosure and 8 layer bare PCB - HALT

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 36
 Challenges Faced – HALT Test
Material characterization
• Hot Product Specification = 65°C
• Upper Screening Limits = 75°C
• Upper Operating Limit = 85°C
• Upper Design Limits = 90°C

Crack

Observation after Hot Step test

•Upper Product Specification = 15grms

•Upper Screening Limits = 17.3grms
•Upper Operating Limit = 20grms
•Vibration ramp rate = 10grms/min

Mechanical Housing of QTRM Top cover Fixture simulating end configuration

lid opens after Vibration (HALT) Test made: HALT vibration test pass
Observation after Vibration Test
Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 37
 HALT Test Setup – X QTRMs

Accelerometer

8 QTRM Plank with one QTRM & Remaining Dummy modules

OROS 36 DAQ H/W

• Frequency Bandwidth = 10-10 KHz for CH-1 & CH-2
• Sampling Frequency = 25 KHz (Nyquist Criteria)
FFT Setting:
• Range = 10 KHz
• No. of Lines = 1601
• Resolution = 6.25Hz

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 38

 HALT Stages – X QTRMs
Cold Temperature • Lower Temp working limits = - 40°C
Stepped Process • Lower Temp Screening Limits= - 50°C
• Lower Temp Operating Limit = - 55°C
• Lower Temp Design Limits = - 60°C

Hot Temperature • Upper Temp working limits = 65°C

Stepped Process • Upper Temp Screening Limits = 75°C
• Upper Temp Operating Limit = 85°C
• Upper Temp Design Limit = 90°C

Vibration Stepped • Vibration working limits = 15grms

Process • Vibration Screening Limits = 17grms
• Vibration Operating Limit = 20grms

Combined HALT • Upper Operating Limits = 85°C

Cycle • Lower Operating Limits = - 55°C
• Vibration Operating Limits = 20grms
• Number of Cycles = Seven

Define
HASS Limits
Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 39
Proof of Screening (POS)
This process demonstrate that the chosen HASS screen
profile does not take out much life out of the equipment and
sufficient life is left in them to survive the normal lifetime of
field use. Also it shows that the chosen HASS screen is
effective in finding out the latent defects in the product.

After completion of the HALT tests as per approved test

plan, the POS shall be carried out on new set of QTRMs as
defined in the following steps: -

Step 1: Perform a POS on new set of QTRMs with

combined temperature and Vibration limits as per
the HASS screening profile and record the results.
Verify that there is no hard failure during the test.

Step 2: Number of Cycles for POS is 15 defect free cycles,

after POS the unit will be yellow banded and all
production deliverable modules will undergo HASS
on fresh units

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 40

 HASS – X QTRMs
HASS Profile – X QTRMs
•Upper Screening Limits = 75°C
•Lower Screening Limits = - 50°C
•Vibration Screening Limit = 17grms

HASS Cycle consist of Three Thermal cycles (Passive), fourth cycle electrically
energized and last cycle combined Temperature, vibration & electrically energized
(HASS=4 Hours & ESS=5 Days)
Achievements:
 HASS replaced by ESS for production screening.
 Total Qty- 8000 numbers of production QTRMs are 100% HASS screened for
projects like AESA, QRSAM, ADFCR(Atulya) Radars, resulting in accomplishing the
quality requirements without compromising the project time schedules.
Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 41
Benefits of HALT/HASS
 Quickly discover design & process flaws.
 Evaluate & improve design margins.
 Eliminate design & process problems before release to
manufacturing.
 Quickly detect shifts in manufacturing processes.
 Reduce production time and cost.
 Decrease field service & warranty costs.
 Reduce infant mortality rate at product introduction.
 Reduces filed failures & Increases product reliability
BOTTOM LINE -
Higher profits and delighted customers

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 42

 HALT/HASS Test Team

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 43

References
[1] Ross, S.M. Stochastic Processes, New York, John Weilly & Son, 
1983.
[2] A. Biroloni, Reliability Engineering Theory & practice SIE Edition.
[3]Ebeling, CE., An Introduction to Reliability & Maintainability 
Engineering, New York, John Weilly & Son, 1994.
[4] MIL_STD‐217 FN2, Reliability Prediction of Electrical and 
electronic components.
[5] IPC 9592A Requirements for power conversion devices   
for the computer and telecommunication industries.
[6] MIL‐STD‐756B, Reliability modeling and Prediction.
[7] Provisional Airworthiness CEMILAC Directive 
No.09/2007(HALT/HASS).

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 44

Typhoon 4.0
This system is designed specifically for the task of
performing Highly Accelerated Stress Screening (HASS)
and HALT on large products.

Typhoon 4.0
WORK SPACE UPPER TABLE POSITION
53.8”w x 54”d x 34.6”h (1366 x 1372 x 879mm)
LOWER TABLE POSITION
53.8”w x 54”d x 53.6”h (1366 x 1372 x 1362mm)

OUTER 69.2”w x 78.8”d x 103.9”h (1759 x 2003 x 2640mm)

DIMENSIONS
TEMPERATURE +200°C TO -100°C
RANGE +250°C TO -100°C
THERMAL RAMP 70°C - 100°C/min average
RATE
TABLE SIZE 48” x 48” (1220 x 1220mm)

ACCELERATION 5 - 75 gRMS (Bare Table)

TABLE CAPACITY 600 lbs (272kg) Recommended

POWER 380V, 400V, 440V, 480V

REQUIREMENTS 3Φ
50/60Hz,
100A (Service Rating)

ACTUATORS 12 Lubricant free

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 45

Author: MUSTAQ BASHA, Scientist E , DRDO

MUSTAQ BASHA received his B.E Degree in Mechanical Engineering from

Vijayanagar College of Engineering (Gulbarga University) Bellary with a
Distinction and Joined DRDO in June 2002 as Scientist B and posted to
LRDE Lab. Initially he was in Mechanical Engineering Division looking after
design and fabrication of Radar hardware structures and environmental test
fixtures etc., in 2007 he got internally transferred to Dynamic testing group of
Radar Integration Test Engineering Division (RITED) which exclusively works
on dynamic testing for all the three services requirements. He is currently
holding Scientist ‘E’ grade (Senior Scientist) and also Heading RAMS
(Reliability) Group of LRDE. He is the only scientist in LRDE who was
successfully qualified as Certified Reliability Engineer from American Society
of Quality in 2016. He has around 15 plus years of experience in this field of
environmental testing. His main area of work involves Dynamic testing,
Quality assurance, Quality control and RAMS analysis of the Radar system
design, developed by LRDE for all the three services. He has published
more than 20 national and international papers in IEEE conference in the
field of dynamic/climatic testing, Field data acquisition, reliability
demonstration and accelerated life testing.
Today he is here in this conference to deliver a talk on “Highly Accelerated
Life Testing Next generation tool towards quality & reliability assurance for
complex electronic systems”.

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 46

Co-Authors Details
B Sajidha Thabassum received her B.E Degree in Electronics Engineering from Vijayanagar
College of Engineering (Gulbarga University) Bellary with a Distinction and M. Tech from
VTU. Currently she is working as Assistant Professor in Dr AIT, College, B’lore. Her main area
of work involves evaluation of Radar systems and antenna design.

ANAND DAMBAL is heading Quality & Reliability Assurance Group of LRDE, currently
scientist 'G' and PD‐Active Phased Array Radars at Electronics Radar and Development
Establishment, DRDO, Bangalore. He has been with the Establishment as a researcher for
over 25 years in the R&D projects of radar systems. His area of interest includes radar
signal processing, radar system Design and Analysis.

KS Surya Prakash, Sc 'G' is Divisional Officer Radar Integration Testing Evaluation Division
(RITED) of LRDE. Received his BE degree in Mechanical from Karnataka University, Dharwad
and M. Tech in Machine Design from IIT Madras. Since 1983 he has been with Electronics &
Radar Development Establishment [LRDE]. He is involved in design and development of
Akash Radar Hardware, Airborne surveillance Platform (ASP), 3D Surveillance radars and
AESA Radar.

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 47

 Question / Discussion

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 48

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 49
Design Challenges faced during HALT– X QTRMs

Version I :
 100µF charge storage ceramic type capacitor was used and this component is not recommended for
airborne application got it replaced with tantalum type.
 LDO(Low drop output voltage regulator) Part number 6806 become obsolence which is used to give 2V
supply to LNA got replaced by TI.
Version II:
 Tantalum capacitor with TI LDO has overshoot in drain pulse of PA limit which was 8V but exceed up to
10.5V, it has cross the limit due to this some resistor, capacitors are change along with it N channel
MOSFET which is added to increase standby raise time to overcome over shoot issues.
 Recovery time of LNA was coming to 1sec, for this problem of ON to OFF additional connection is
made from ground pad pin to the external ground i.e., heat sink (base of LNA) with this change recovery
has become <100µsec
 .FPGA already has an oscillator for timing/clock etc., but an additional oscillator is added with TCXO is
added from RAKON device, this is standby mechanism to counter jitter issues arises in FPGA oscillator,
this all changes got implemented in Ver III.
Version III:
 In rush current issue for short duration while switching ON 8V supply from external source, notice
module drawing up to 5A current against few milliamps, once it get stabilise it draws 300milliamps, to
address this issue MOSFET driver is replaced from MAXIM device to MICREL device. This replacement
of MOSFET drivers will wont allow PA to switch ON during transition period , once full 8V achieved then
only PA will be ON, with this modification version-IV was released.
Version IV: Was released with all the above changes and successfully qualified HALT/QTP test.

Coating Issues: Electroless nickel plating(conductive) plating was required were the nano-D connector get soldered to
the cover of the lid earlier the coating thickness was 20% used got to 10% and this added extra area for
bonding of lid cover.
Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 50
Electroless Nickel Plating
Electroless nickel is a term used to describe plating of a
nickel-phosphorus coating onto a suitable substrate by
chemical reduction. Unlike electroplated coatings,
electroless nickel is applied without an externally
applied electric current. Instead, the coating is deposited
onto a part's surface by reducing nickel ions to metallic
nickel with sodium hypophosphite. This chemical
process avoids many of the problems associated with
most metallic coatings and provides deposits with many
unique characteristics. As applied, electroless nickel
coatings are uniform, hard, relatively brittle,
lubrious, easily solderable and highly corrosion
resistant. They can be precipitation hardened to very
high levels through the use of low temperature
treatments, producing wear resistance equal to that of
commercial hard chrome coatings. This combination
makes the coating well suited for many severe
applications and often allows it to be used in place of
more expensive or less readily available alloys.

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 51

 LAYOUT OF X-BAND QTRM

76 mm

1:4 way 
power 
divider
Circulator
HPA
LPF

FPGA Radiating 
Plank side Elements’ 
65.8 mm
side

DC/Control
Signal 
Connector
Core Chip HPF
Limiter
Height = 5 mm

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 52

 Reliability Prediction of X-Band Single QTRM
Parts Stress Method (PSM)

Note: The MTBF and Failure rate calculation as per MIL-HDBK-217FN2, for the X-Band Quad Transmit Receive
Module on Airborne Inhabited Fighter Aircraft(AIF) condition at +65°C by assuming continuous operation
with 100% duty cycle.

SYSTEM FAILURE RATE   λ= λ1 + λ2 +‐ ‐ ‐ ‐ ‐ + λ13= 26.7367fpmh

SYSTEM MTBF = 37401.71Hrs

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 53

MTBF of the QTRM over Temperature

Operating
MTBF(Hrs)
Temperature
+65 38189
+30 57753
0 74779
-20 87099
-40 100794

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 54

 MTBF of QTRM with Other Platform Environment

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 55

 Vibration Data Acquisition during HALT – X QTRMs
2
1 Start Stop

60E+00 Data acquisition in Frequency Domain 
40E+00
for frequency bandwidth of 10‐10KHz 
20E+00
for 10Grms input stress on Channel‐1 
Sensor on QTRM
Acceleration (g)

-20E+00

-40E+00

-60E+00

0 1 2 3 4 5 6 7
Time (s)

2
1 Start Stop

80E+00 Data acquisition in Frequency Domain for 
60E+00
frequency bandwidth of 10‐10KHz for 
40E+00
15Grms input stress on Channel‐1 Sensor 
20E+00

on QTRM
Acceleration (g)

-20E+00

-40E+00

-60E+00

-80E+00

1:47:53 PM 1:48:00 PM 1:48:10 PM 1:48:20 PM 1:48:30 PM 1:48:40 PM 1:48:50 PM 1:49:00 PM 1:49:10 PM

11/30/2015

Start 1
2 Stop

Data acquisition in Frequency Domain 
80E+00

60E+00

for frequency bandwidth of 10‐10KHz 
40E+00

for  17.0 grms input stress on 
20E+00

Channel‐1 Sensor on QTRM
Acceleration (g)

-20E+00

-40E+00

-60E+00

-80E+00

1:57:41 PM 1:58:00 PM 1:58:30 PM 1:59:00 PM 1:59:28 PM

11/30/2015 11/30/2015

Mustaq  Basha, LRDE, DRDO Red Track Session 2 Slide Number: 56