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UNIT-I: 8086 ARCHITECTURE: Main features, pin diagram/description,

8086 microprocessor family, 8086 internal architecture, bus interfacing unit,
execution unit, interrupts and interrupt responses, 8086 system timing,
minimum mode and maximum mode configuration.
A HISTORICAL BACKGROUND:
The idea of computing system is not new-it has been around long before
modern electrical and electronic devices were developed. Babylonians invented
the calculating device Abacus, the first mechanical calculator. The Abacus,
which used strings of beads to perform calculations .It was used extensively and
is still in use today. It was not improved until 1642. The mathematician Blaise
Pascal invented a calculator in 1642 that was constructed of gears and wheels.
The motor –driven adding machines were came after the advent of electric
motors in 1800’s.These are all based on the mechanical calculator developed by
Pascal.
In the early 1870s, Bomar introduced the first small hand –held
electronic calculator. In 1889, Herman Hollerith developed the punched card
for storing data. In 1896, Hellerith formed a company called the Tabulating
Machine Company, which developed a line of machines that was used
punched cards for tabulation. After a number of mergers, the Tabulating
Machine Company was formed into International Business machines
Corporation, now it is referred more commonly as IBM. The punched cards
used in computer systems are often called Hollerith cards.
The first Electronic calculating machine was invented by Konrad Zuse
(German) in 1941.It has recently been discovered that the first electronic
computer was placed into operation in 1943.This first electronic computing
system, which used Vacuum tubes, was invented by Alan Turing .It was a
fixed program computer system, today which is often called a special- purpose
computer.
The first general –purpose programmable electronic computer system was
developed in 1946 at the University of Pennsylvania. The first modern
computer was called the ENIAC (Electronics Numerical Integrator and
Calculator).The ENIAC was a huge machine, containing over 17,000 vacuum
tubes and over 500 miles of wires. This machine weighted over 30 tons, yet
performed only about 1, 00,000 operations per second. Another problem with
the ENIAC was the life of the vacuum tube components, which required
frequent maintenance.
fter development of Transistors in 1948 at Bell Labs and invention of
the Integrated Circuits in 1958 by Jack Kilby of Texas Instruments, the Intel
Corporation introduced the first Microprocessor 4004 in 1971.The device that
started the Microprocessor revolution that continues today at an ever-
accelerating pace.

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1.0 MICROPROCESSOR:-- an electronic device that includes arithmetic

,logical , and control circuitry needed to function as a digital computer's CPU.
Microprocessors are integrated circuits because it has an in built CPU on single
chip using LSI/VLSI Technology.
Since Microprocessors is a small in size compared to the CPU and it‘s
processing time is in microseconds hence name as Microprocessor

1.1 MICROPROCESSOR BASED SYSTEM OR MICROCOMPUTER:--

The microprocessor based system consists of microprocessor as CPU,

semiconductor memories like EPROM and RAM, Input device ,out put device
and interfacing devices .The memories, input device, output device and
interfacing devices are called PERIPHERALS .In this system microprocessor is
the MASTER and all other peripherals are SLAVES.

The buses are group of lines that carries data ,address or control signals.
The CPU has multiplexed lines. i.e same line is used to carry different signals
(i.e both data and address) are called system bus. All the slaves in the system
are connected to the same system bus. At any time instant communication takes
place between the master and one of the slaves. the processor selects a slave by
sending an address. When a slave selected it comes to the normal logic and
communicate with the processor.
CPU:- The cpu of 8086 is capable in performing ARITHEMATIC &
LOGICAL and making decision during program execution. this can be divided
in to three sections as arithmetic/logic unit (ALU),register unit and control unit.
Input :- the input unit is required to get data and instructions in binary form
from the outside to the microprocessor.(EX-Keyboard, video unit, a card reader,
a/d converters etc…)
Output:-- The output unit transfer the processed data from the microprocessor
to the out put devices such as LED, CRT’s, VEDIO MONITER,PRINTERS
etc……..
Memory:- Memory devices stores the program and data, and provides that
information to the microprocessor whenever necessary.

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1.2 DEVELOPMENT OF MICROPROCESSORS (μP):

Intel introduced its first 4-bit microprocessor 4004 in 1971.The 4004
instruction set contained only 45 instructions. It execute instructions at the slow
rate of 50 Kilo-instructions per second(KIPS).This was slow when compared to
the 100,000 instructions executed per second by the ENIAC computer
in1946.The 4-bit microprocessor is used in early video game systems and small
microprocessor based control systems. Intel released 4040(4-bit)
microprocessor, an updated version of the earlier 4004.The 4040
microprocessor operated at a higher speed, although it lacked improvements in
word width and memory size.
In 1972 Intel Corporation released 8-bit microprocessor 8008, which is
an extended version of 4-bit microprocessor. The 8008 microprocessor is used
in more advanced systems because it has an expanded memory size (16KB)
and contained a additional instructions(48) .It executes 5,00,000 instructions per
second. But it is some what small memory size, slow speed and instruction set
limited its usefulness. These microprocessors could not survive as general
purpose microprocessors due to their design and performance limitations. The
launch of the first general purpose 8-bit microprocessor 8080 in 1974 by Intel
is considered to be the first major stepping stone towards the development of
advanced microprocessors. It executes the instruction s10 times faster than the
8008.Also the 8080 was compatible with TTL, where as the 8008 was not
directly compatible. This made interfacing much easier and less expensive. The
memory size of 8080 is 64KB.
In 1977 Intel Corporation introduced an updated version of the 8080
microprocessor –the 8085.This was to be the last 8-bit general purpose
microprocessor developed by Intel. The 8085 executed software at a higher
speed. It executes 769230 instructions per second. The main advantages of 8085
were its internal clock generator, internal system controller and higher clock
frequency.
The main limitations of the 8-bit microprocessor were their low speed,
low memory addressing capability, limited number of general purpose registers
and a less powerful instruction set. All these limitations of the 8-bit
microprocessors pushed the designers to build more powerful processors in
terms of advanced architecture, more processing capability, larger memory
addressing capability and a more powerful instruction set. The 8086 was a result
of such development design efforts.
In the family of 16-bit microprocessors, Intel’s 8086 were the first one
to be launched in 1978.The introduction of the 16-bit microprocessor was a
result of the increasing demand for more powerful and high speed
computational resources. The 8086 microprocessor has a much powerful
instruction set along with the architectural developments which imparts
substantial programming flexibility and improvement in speed over the 8-bit
microprocessors. A year or so later Intel released the 8088 microprocessor. It is
also a 16-bit microprocessor. The memory size of the 8086/8088 processor is
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1MB,which was 16 times more memory than 8085.One another feature found in
8086 was a small 6-byte instruction queue, that prefetched a few instructions
before they were executed. Note that these types of microprocessors were called
CISC (Complex Instruction Set Computers) because of the number and
complexity of instructions. The popularity of the Intel family was ensured in
1981, when IBM Corporation decided to use the 8088 microprocessor in its
Personal Computer.
In 1983, Intel introduced the 80286 microprocessor; an updated version
of 8086.It is also a 16-bit microprocessor. It was almost identical to the 8086
and 8088, except memory size. The memory size of 80286 is 16MB.
In 1986, Intel released 80386 microprocessor keeping in mind faster
microprocessor speeds, more memory size and wider data paths. It is 32-bit
microprocessor. So, it contained 32-bit data bus. The memory size is 4GB (32-
bit address bus). Some of the advanced processors developed by Intel
Corporation are 80486, Pentium, PentiumII, PentiumII Xeaon, Pentium III,
Pentium-4, etc.

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1.3 FEATURES OF 8086 MICROPROCESSOR:

Intel released its first 16-bit microprocessor 8086 in 1978.The Intel 8086 is a
16-bit processor ,which is fabricated using HMOS technology and it has 40 pins
,packaged in DIP .
 The 8086 is a 16-bit microprocessor. The term 16-bit means that its
arithmetic logic unit, internal registers and most of its instructions are
designed to work with 16-bit binary words.
 The 8086 has a 16-bit data bus, so it can read data from or write data to
memory and ports either 16 bits or 8 bits at a time. The 8088, however
has an 8-bit data bus, so it can only read data from or write data to
memory and ports 8 bits at a time.
 The 8086 has a 20-bit address bus, so it can directly access 220 or 10,
48,576 (1MB) memory locations. Each of the 10, 48,576 (1MB) memory
locations is byte wide. Therefore, a 16-bit word is stored in two
consecutive memory locations. The 8088 also has a 20-bit address bus, so
it can also address 220 memory locations.
 The 8086 can generate 16-bit I/O address, hence it can access
216=65536 I/O ports.
 The 8086 provides fourteen 16-bit registers.
 The 8086 has multiplexed address and data bus which reduces the
number of pins needed, but does slow down the transfer of data.
 The 8086 requires clock with a 33% duty cycle to provide optimized
internal timing.
 The 8086 microprocessor available in three clock rates: 5 MHz (8086), 8
MHz (8086-2) and 10 MHz (8086-1).
 The Intel 8086 is designed to operate in two modes: minimum mode and
maximum mode.
 Minimum mode: When only one 8086 CPU is to be used in a
microcomputer system, the 8086 is used in the minimum mode of
operation.
 Maximum mode: More than one processor (multiprocessor) is used in the
system, the 8086 is used in the maximum mode of operation.
 An interesting feature of the 8086 is that it fetches up to 6 instruction
bytes from memory and queue stores them in order to speed up
instruction execution.
 It requires +5V single power supply.

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1.4 INTERNAL ARCHITECTURE OF 8086:-

 8086 developed by Intel was the first 16bit microprocessor and designed
using HMOS technology, and packs approximately 29000 transistors in a
chip.
 The based on their functionality complete architecture of 8086 can be
divided into 2 parts.
1. Bus interfacing unit(B.I.U)
2. Execution unit(E.U)

BUS INTERFACING UNIT: The bus interfacing unit in 8086 provides the
interface to the outside world. The BIU in responsible for all memory access
and I/O access by the 8086. And BIU communicates with devices outside the
microprocessors like fetches instructions from memory, reads data from ports
and memory, and writes data to ports and memory. It contains the following
blocks:
 Instruction Byte Queue
 Segment Registers
 Adder (Physical Address Generation)
 Instruction Pointer
THE QUEUE: To speed up program execution, the BIU fetches six instruction
bytes ahead of time from the memory. The BIU stores these perfected bytes in a
first-in-first-out register set called a queue. When the EU is ready for its next
instruction, it simply reads the instruction byte for the instruction from the
queue in the BIU. This is much faster than sending out an address to the system
memory and waiting for memory to send back the next instruction byte or bytes.
The process is analogous to the way a bricklayer’s assistant fetches bricks
ahead of time and keeps a queue of bricks lined up so that the brick layer can
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just reach out and grab a brick when necessary. Except in the cases of JMP and
CALL instructions, where the queue must be damped and then reloaded starting
from a new address. So, the queue operates on the principle first in first out
(FIFO).So that the execution unit gets the instructions for execution in the order
they are fetched. This prefetch-and-queue scheme greatly speeds up processing.
Fetches the next instruction while the current instruction executes is called
pipelining.
Instruction pointer:( IP) is a 16-bit register, Instruction pointer points(store the
adders) to be fetched and executed next instruction .
Segment Pointer or Segment Registers:- Most of the registers contain
data/instruction offsets within 64 KB memory segment. There are four different
64 KB segments for instructions, stack, data and extra data. To specify where in
1 MB of processor memory these 4 segments are located the processor uses four
segment registers:
Code segment (CS) is a 16-bit register containing address of 64 KB segment
with processor instructions. The processor uses CS segment for all accesses to
instructions referenced by instruction pointer (IP) register.
Stack segment (SS) is a 16-bit register containing address of 64KB segment
with program stack. It holds the stack information hence stack is a portion of
memory set aside to store address and data when the program is processed.
Data segment (DS) is a 16-bit register containing address of 64KB segment
with program data. By default, the processor assumes that all data referenced by
general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the
data segment.
Extra segment (ES) is a 16-bit register containing address of 64KB segment,
usually with program data. By default, the processor assumes that the DI
register references the ES segment in string manipulation instructions.
EXECUTION UNIT(E.U):-The execution unit is responsible for executing the
instruction fetched by the BIU it performs four kinds of operations .
These are fetching, decode, execute and write operation
The functional parts of EU:-
 General purpose registers
 Pointer and index registers
 Arithmetic and logic unit (ALU)
 Flag register
 Control unit.

General purpose registers:- All general registers of the 8086 microprocessor

can be used for arithmetic and logic operations. The general registers are.
Accumulator(AX): register consists of 2 8-bit registers AL and AH, which can
be combined together and used as a 16-bit register AX. Accumulator can be
used for I/O operations, ALU and string manipulation.

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Base register(BX) consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX. BL in this case contains the
low-order byte of the word, and BH contains the high-order byte. BX register
usually contains a data pointer used for based, based indexed or register indirect
addressing.
Count register(CX) consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX. When combined, CL
register contains the low-order byte of the word, and CH contains the high-order
byte. Count register can be used in Loop, shift/rotate instructions and as a
counter in string manipulation,
Data register(DX) consists of two 8-bit registers DL and DH, which can be
combined together and used as a 16-bit register DX. When combined, DL
register contains the low-order byte of the word, and DH contains the high-
order byte. Data register can be used as a port number in I/O
operations. In integer 32-bit multiply and divide instruction the DX register
contains high-order word of the initial or resulting number
Pointer and index registers:- 8086 has two pointer registers (SP,BP),these
are used for storing the offset-address of data elements that are stored in stack.
It has two index registers (SI,DI). These are used in array processing and
string operations.
Stack Pointer (SP) is a 16-bit register and it pointing (storing address) to the
top stack.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP
register is usually used for based, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and
register indirect addressing, as well as a source data address in string
manipulation instructions. Thus this register is useful in accessing contiguous
memory locations.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based
indexed and register indirect addressing, as well as a destination data address in
string manipulation instructions.
Flags is a 16-bit register containing 9 1-bit flags:

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A flag is a flip-flop which indicates some condition produced by the execution

of an instruction .flags are of two types, there are status flag and contr
The six status flags are Zero(Z),Sign(S),Parity(P),Carry(C), Auxiliary Carry
(AC) and Over flow(O).flags. the three control flags are
Direction(D),Interrupt(I),and Trap(T) flags.
 Overflow Flag (OF) - set if the result is too large positive number, or is
too small negative number to fit into destination operand.
 Direction Flag (DF) - if set then string manipulation instructions will
auto-decrement index registers. If cleared then the index registers will be
auto-incremented.
 Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.
 Single-step Flag (TF) - if set then single-step interrupt will occur after the
next instruction.
 Sign Flag (SF) - set if the most significant bit of the result is set.(+ or -)
indicats.
 Zero Flag (ZF) - set if the result is zero.
 Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits
0-3 in the AL register.
 Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order
byte of the result is even.
 Carry Flag (CF) - set if there was a carry from or borrow to the most
significant bit during last result calculation.
1.5 MEMORY ORGANIZATION
Segmentation is the process in which the main memory of the computer is
divided into different segments and each segment has its own base address. It is
basically used to enhance the speed of execution of the computer system, so that
processor is able to fetch and execute the data from the memory easily and fast.
Need for Segmentation –
The Bus Interface Unit (BIU) contains four 16 bit special purpose registers
(mentioned below) called as Segment Registers.
 Code segment register (CS): is used for addressing memory location in the
code segment of the memory, where the executable program is stored.
 Data segment register (DS): points to the data segment of the memory
where the data is stored.
 Extra Segment Register (ES): also refers to a segment in the memory
which is another data segment in the memory.
 Stack Segment Register (SS): is used for addressing stack segment of the
memory. The stack segment is that segment of memory which is used to
store stack data.
The number of address lines in 8086 is 20, 8086 BIU will send 20bit address, so
as to access one of the 1MB memory locations. The four segment registers
actually contain the upper 16 bits of the starting addresses of the four memory
segments of 64 KB each with which the 8086 is working at that instant of time.
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A segment is a logical unit of memory that may be up to 64 kilobytes long.

Each segment is made up of contiguous memory locations. It is independent,
separately addressable unit. Starting address will always be changing. It will not
be fixed.
Note that the 8086 does not work the whole 1MB memory at any given time.
However it works only with four 64KB segments within the whole 1MB
memory.
Bellow is the one way of positioning four 64 kilobyte segments within the 1M
byte memory space of an 8086.

Types Of Segmentation –
1. Overlapping Segment – A segment starts at a particular address and its
maximum size can go up to 64kilobytes. But if another segment starts along this
64kilobytes location of the first segment, then the two are said to
be Overlapping Segment.
2. Non-Overlapped Segment – A segment starts at a particular address and its
maximum size can go up to 64kilobytes. But if another segment starts before
this 64kilobytes location of the first segment, then the two segments are said to
be Non-Overlapped Segment.
Advantages of the Segmentation The main advantages of segmentation are as
follows:
 It provides a powerful memory management mechanism.
 Data related or stack related operations can be performed in different
segments.
 Code related operation can be done in separate code segments.
 It allows to processes to easily share data.
 It allows to extend the address ability of the processor, i.e. segmentation
allows the use of 16 bit registers to give an addressing capability of 1
Megabytes. Without segmentation, it would require 20 bit registers.
 It is possible to enhance the memory size of code data or stack segments
beyond 64 KB by allotting more than one segment for each area.

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1.6 PIN DIAGRAM/DESCRIPTION:

 Pin(1 &20):- The 8086 is a 40 pin DIP (Dual Inline Package) in that
these are two ground pis
 Pin 40(Vcc): The 8086 is a 40 pin DIP require a single +5v power
supply.
 AD0 to AD15(Pin no: 2 to 16 & 39): These are the time multiplexed
memory I/O address and data lines. Address remains on the lines during
T1 state, while the data is available on the data bus during T2, T3, Tw
and T4. i.e., provision for relocation is done. to be time
 NMI (NON-MASKABLE INTERRUPT)(pin 17): This is a edge
triggered input and hardware interrupt pin which causes Type 2 interrupt.
Whenever an external device activates this pin the microprocessor will
interrupt the present program execution and execute the interrupt service
routine. And it can’t mask-able with any instruction.
 INTR(Interrupt)(pin 18): This is a level triggered input and hardware
interrupt pin . This interrupt is mask-able (Enable by some instruction i.e
STI (set interrupt flag) & CLI(clear interrupt flag)),and is non vectored.
 CLK(pin 19): for timing purpose microprocessor needs a clock .the 8086
comes in different clock speeds, with no change in internal architecture.
8086-1 works at 10MHz
8086-2 works at 8MHz
8086 works at 5MHz
 RESET(pin 21) causes the processor to immediately terminate its present
activity. The signal must be active HIGH for at least four clock cycles. It
restarts execution
Code segment contents will be FFFFH
IP registers contents 0000H
DS,ES,SS will be initialized to 0000H
Flag registers contents 0000H
also the processor gets into disable interrupt state(Except NMI).

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 READY(pin 22):-READY is the acknowledgement from the addressed

memory or I/O device that it will complete the data transfer.
 TEST(pin 23):- This input is examined by a ‘WAIT’ instruction . in the
TEST i/p goes low ,execution will continue else ,the processor remains in
an idle state. the input is synchronized internally during each clock cycle
on leading edge of clock.
 RD(pin 32): when ever microprocessor needs to get information from a
memory location or an I/O port it activated RD pin .it is an active low
signal.
 MN/MX(pin 33): MINIMUM/MAXIMUM: indicates what mode the
processor is to operate in. The two modes are present Minimum and
Maximum modes. When MN/MX pin is connected to +5v it will act as
minimum mode, and when MN/MX pin is connected to GND activated in
maximum mode.
 BHE/s7(pin 34): BHE stands for bus high enable . this signal is used to
indicate the transfer of data over D15-D8 and is used to drive chip select
of odd address memory bank or peripherals .s7 is not currently used.

 A16/s3, A17/s4, A18/s5, A19/s6(pin‘s- 38 to 35): These are the time

multiplexed address and status lines. During T1 these are the most
significant address lines for memory operations. During I/O operations,
these lines are low. During memory or I/O operations, status information
is available on those lines for T2, T3, Tw and T4. S3 and s4 indicate
segment register to be used for accessing data . and s5 indicate the value
of the interrupt enable flag bit . s6 not used
S4 S3 Segment register
0 0 Extra segment
0 1 Stack segment
1 0 Code segment
1 1 Data segment
 PIN DESCRIPTION FOR MINIMUM MODE: when only one 8086
CPU is to be used in a microcomputer system ,the 8086 is used in
minimum mode .for this MN/MX pin connect to +5v.
1. INTA(pin 24): INTA stands for interrupt acknowledgment. it is
response for INTR , it is active low signal.
2. ALE(pin 25): (address latch enable) this o/p signal indicates the
availability of the valid address on address / data lines. And is
connected to latch enable I/P.

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3. DT/R(pin 27): (data transmit and receive) when it is high data is

transmitted through transreceivers and if it is low data is received
through transreceivers.
4. DEN(pin 26)(data enable): this signal indicates availability of
valid data over the address / data lines. it is used to enable the
transreceivers. To separate the data from the multiplexed address/data
signals.
5. M/IO (pin 28) : Differentiate between the Memory and I/O
operation. A LOW on this pin indicated I/O operation and a HIGH
indicated a Memory Operation.
6. WR(pin 29): the WR pin is an active low output pin. Whenever
the microprocessor needs to write information to a memory location
or an I/O port it activates the WR pin.
7. HOLD(pin 31) : The 8086 has a pin called HOLD. This pin is
used by external devices to gain control of the busses.
8. HLDA(pin 30) :When the HOLD signal is activated by an external
device, the 8086 stops executing instructions and stops using the
busses. This would allow external devices to control the information
on the
 PIN DESCRIPTION FOR MAXIMUM MODE:- in multi processor
system it operates in maximum mode. When connected MN/MX pin to
gnd.
1. QS0 and QS1(pin 24 & 25): these lines give information about
the status of the code pre fetch queue.

2.Status signals (S0,S1,S2)(pin 26 to 28):this signal represent type

of operation being carried out by the processor.

3.LOCK(pin 29). This output pin indicates that other system bus
master will be prevented from gaining the system bus, while the
LOCK signal is low. The LOCK signal is activated by the ‘LOCK’
prefix instruction and remains active until the completion of the
next instruction. When the CPU is executing a critical instruction
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which requires the system bus, the LOCK prefix instruction ensures
that other processors connected in the system will not gain the
control of the bus.
4.RQ0/GT0 and RQ1/GT1(pin 30 & 31)
/grant) these pins are used by other local bus master in maximum
mode to force the processor to release the local bus at the end of the
processor‘s current bus cycle. Each of the pin is pin is bi-
directional.
Q)What is the use of operating 8086 in minimum mode? Explain.

 In a minimum mode 8086 system, the microprocessor 8086 is

operated in minimum mode by strapping its MN//MX pin to logic 1.
 In this mode, all the control signals are given out by the
microprocessor chip itself. There is a single microprocessor in the
minimum mode system.
 The remaining components in the system are latches, Tran receivers,
clock generator, memory and I/O devices. Some type of chip
selection logic may be required for selecting memory or I/O devices,
depending upon the address map of the system.
 Latches are generally buffered output D-type flip-flops like 74LS373
or 8282. They are used for separating the valid address from the
multiplexed address/data signals and are controlled by the ALE signal
generated by 8086.
 Transreceivers are the bidirectional buffers and some times they are
called as data amplifiers. They are required to separate the valid data
from the time multiplexed address/data signals.
 They are controlled by two signals namely, DEN and DT/R.
 The DEN signal indicates the direction of data, i.e. from or to the
processor. The system contains memory for the monitor and users
program storage.

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 Usually, EPROM is used for monitor storage, while RAM for user’s
program storage. A system may contain I/O devices.
Q)What is the use of operating 8086 in maximum mode? Expain?

MAXIMUM MODE 8086 SYSTEM:

 Maximum mode is one of the two hardware modes available to the
Intel 8086 and 8088 processors (CPU).Maximum mode is for large
applications such as multiprocessing. The mode is hard-wired into
the circuit and cannot be changed by software.
 The Bus controller is introduced here due to the support of
multiprocessor environment of Maximum mode. The decoder is
used to select desired memory chips. The remaining components of
this circuit are similar to 8088 minimum mode circuit, as shown in
figure. Note that the bank high enable signal is used to control the
access of even or odd memory banks of 8086 system.
 The status codes (S0, S1, S2) of the CPU is used by the bus
controller to activate maximum mode memory control signals:
These codes are important for multiprocessor environment,
supported by Maximum mode

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1.7 BUS CYCLES AND TIMING DIAGRAMS:

The BIU initiates all external operations which are also called bus activity . the
external bus activity are repetitions of certain operations . the basic operations
performed by the CPU bus are called bus cycles. these are classified in to .
1. Memory read cycle(four T-states)
2. Memory write cycle(four T-states)
3. I/O read cycle(four T-states)
4. I/O write cycle(four T-states)
5. Interrupt acknowledgement cycle(eight T-states)
The processor takes a definite time to perform a bus cycle. The time taken to
perform a bus cycle at specified in terms of T-states.
1.7.1 MINIMUM MODE 8086 SYSTEM TIMING DIAGRAMS:-

MN/MX
pin to +5v power supply.
 In this mode all the control signals are given out by 8086 it self. Control
signals are memory or I/O read ,write , ALE ,DEN and DT/R.
 There is a single microprocessor in the minimum mode is called
MASTER, the remaining components in the system are Latch,
Tranreceivers, Clock generator, memory and I/O devices are SLAVES.
 The Latches are generally buffered output (like D-Flip flop).used for
separating the valid address from the multiplexed address/data signals
and are controlled by ALE signal generated by 8086 CPU.
 Tranreceiver are the bi-directional buffers some time called as data
amplifiers. They are controlled by two signals namely DEN(data
enable),DT/R(data transmit /receive) generated by 8086 CPU.
 Usually EPROMS are used for program (O.S) storage, while RAM for
users data storage. A system may contain I/O devices for communication
with processor as well as some special purpose I/O devices.
Timing Diagrams for Memory-Read bus-cycle of 8086 system
 During T1 or the 1st clock pulse, the read bus cycle starts and valid
address is latched together with setting minimum and maximum mode,
input output or memory interface, data transmit and receive mode of
buffer IC.
 During T2 , the Read control signals are issued and data enable signal is
asserted. Note that during this state the READY signal is also checked to
insert wait status, if needed
 During T3 , the data from the memory is read by sampling the data bus at
the end of T3
 During T4 , all bus signals are deactivated in preparation for the next
clock cycle.

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Timing Diagrams for Memory-Write bus-cycle of 8086 system

 During T1 or the 1st clock pulse, the write bus cycle starts and valid
address is latched together with setting minimum and maximum mode,
input output or memory interface, data transmit and receive mode of
buffer IC.
 During T2 , the Write control signals are issued and data enable signal
is asserted. Note that during this state the READY signal is also checked
to insert wait status, if needed
 During T3&T4 , the data to the memory is write by sampling the data bus
at the end of T4
 During T4 , all bus signals are deactivated in preparation for the next
clock cycle.

1.7.2 MAXIMUM MODE 8086 SYSTEM TIMING DIAGRAMS:

ground(vss)
 In multi processor system it operate in maximum mode , in that more than
one microprocessor is used for master . Remaining Latch, Memory
devices (ROM & RAM)and I/O devices are slaves.
 In ths mode the processor drives the status signals S2,S1,S0.another chip
(IC8288)called bus controller drives the control signals using status
information. those control signals are RD and WR(for memory and I/O
devices), DEN,DT/R ALE , etc..
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 The outputs of the bus controller are the Control Signals, namely DEN,
DT/R*, IORC*, IOWTC*, MWTC*, MRDC*, ALE etc
 The pins in 8086 are RQ0/GT0 ,RQ1/GT1 and LOCK are used for
multi processing purpose. When other master requires a bus 8086 will
suspend the process and grant the system bus to the other master.
Timing Diagrams for Memory-Read bus-cycle of 8086 system
 During T1 or the 1st clock pulse, the master sets status signals on
s0,s1,s2 according that signals bus controller will generate control
signals .the read bus cycle starts and valid address is latched together
with setting minimum and maximum mode, input output or memory
interface, data transmit and receive mode of buffer IC.
 During T2 , the Read control signals are issued and data enable signal is
asserted. Note that during this state the READY signal is also checked to
insert wait status, if needed
 During T3 , the data from the memory is read by sampling the data bus at
the end of T3
 During T4 , all bus signals are deactivated in preparation for the next
clock cycle.

Timing Diagrams for Memory-Write bus-cycle of 8086 system

 During T1 or the 1st clock pulse, the master sets status signals on
s0,s1,s2 according that signals bus controller will generate control
signals .the write bus cycle starts and valid address is latched together
with setting minimum and maximum mode, input output or memory
interface, data transmit and receive mode of buffer IC.
 During T2 , the Write control signals are issued and data enable signal
is asserted. Note that during this state the READY signal is also checked
to insert wait status, if needed
 During T3&T4 , the data to the memory is write by sampling the data bus
at the end of T4
 During T4 , all bus signals are deactivated in preparation for the next
clock cycle
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

COMPARISON BETWEEN MINIMUM AND MAXIMUM MODES
Maximum Mode
When MN/MX(bar) is Low 8086 is in
Maximum Mode
In Maximum Mode 8086 generates
QS1,QS0,S0(bar) ,S1(bar) ,S2(bar),
LOCK(bar),RQ(bar)/GT1(bar),
RQ(bar)/GT0(bar),
So clearly there are multiple
microprocessors in the system
Where in maximum mode interfacing,
master/slave and multiplexing and
several such control signals are required
In maximum mode a bus controller is
required to produce control signals. This
bus controller produces
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Minimum Mode
When MN/MX(bar) is High 8086 is in
Maximum Mode
In Minimum Mode 8086 generates
INTA(bar),ALE,DEN(bar),M/IO(bar),
HLDA, HOLD and WR(bar) control
signals
There is only one processor in the
system
In minimum mode no interfacing or
master/slave signal is required.
In maximum mode direct RD WR signals
can be used. No bus controller required.
A simple de-multiplexing would do the
job of producing the control signals. The
de-multiplexer produces MEMRD,
MEMWR, IORD, IOWR control signals
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1.8 INTERRUPT: An interrupt is signal or an event which response to E.U

will terminates the execution of main program and transfers the E.U to Interrupt
Service Routine (ISR).That signal is called Interrupt.
1.9 SOURCES OF INTERRUPT: An 8086 interrupt can come from any one
of three sources. One source is an external signal applied to the nonmaskable
interrupt (NMI) input pin or to the interrupt (INTR) ·input pin. An interrupt
caused by a signal applied to one of these inputs is referred to as hardware
interrupt.
A second source of an interrupt is execution of the Interrupt instruction,
INT. This is referred to as a software interrupt. The third source of an interrupt
is some error condition produced in the 8086 by the execution of an instruction.
An example of this is the divide-by-zero interrupt. If you attempt to divide an
operand by zero, the 8086 will automatically interrupt the currently executing
program.
1.10 INTERRUPT CYCLE or INTERRUPT SERVICE MECHANISUM:
 It decrements the stack pointer by 2 and pushes the flag register on the
stack.
 It disables the 8086 INTR interrupt input by clearing the interrupt flag
(IF) in the flag register.
 It resets the trap flag (TF) in the flag register.
 It decrements the stack pointer by 2-and pushes the current code segment
register contents on the stack.
 It decrements the stack pointer again by 2 and pushes the current
instruction
pointer contents on the stack.
 CPU Fetches ISR address from interrupt vector table and jump to the start
of the procedure you wrote to respond to the interrupt.

 After completing ISR (IRET) It increments the stack pointer by 2 and

pops current instruction pointer contents on the stack.
 It increments the stack pointer by 2-and pops the current code segment
register contents on the stack.
 It increments the stack pointer by 2 and pushes the flag register on the
stack.
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1.11:TYPES OF INTERRUPTS:There are two types of Interrupts in 8086.

They are: (i)Hardware Interrupts and
(ii)Software Interrupts
(i) HARDWARE INTERRUPTS (External Interrupts). The Intel
microprocessors support hardware interrupts through:
 Two pins that allow interrupt requests, INTR and NMI
 One pin that acknowledges, INTA, the interrupt requested on INTR.
INTR:-
 INTR is a maskable hardware interrupt. The interrupt can be
enabled/disabled using STI/CLI instructions or using more complicated
method of updating the FLAGS register with the help of the POPF
instruction.
 INTR is level triggered interrupt.
 The INTR interrupt is activated by an I/O port, then the microprocessor
first completes the current execution and sends ‘0’ on INTA pin twice.
The first ‘0’ means INTA informs the external device to get ready and
during the second ‘0’ the microprocessor receives the 8 bit, say X, from
the programmable interrupt controller.
These actions are taken by the microprocessor −
 First completes the current instruction.
 Activates INTA output and receives the interrupt type, say X.
 Flag register value, CS value of the return address and IP value of the
return address are pushed on to the stack.
 IP value is loaded from the contents of word location X × 4
 CS is loaded from the contents of the next word location.
 Interrupt flag and trap flag is reset to 0
NMI:-
 NMI is a non-maskable interrupt. Interrupt is processed in the same way
as the INTR interrupt. Interrupt type of the NMI is 2, i.e. the address of
the NMI processing routine is stored in location 0008h. This interrupt has
higher priority than the maskable interrupt.
 NMI is edge triggered interrupt
When this interrupt is activated, these actions take place −
 Completes the current instruction that is in progress.
 Pushes the Flag register values on to the stack.
 Pushes the CS (code segment) value and IP (instruction pointer) value of
the return address on to the stack.
 IP is loaded from the contents of the word location 00008H.
 CS is loaded from the contents of the next word location 0000AH.
 Interrupt flag and trap flag are reset to 0.

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(ii) SOFTWARE INTERRUPTS (Internal Interrupts and Instructions)

.Software interrupts can be caused by:
 INT instruction - breakpoint interrupt. This is a type 3 interrupt.
 INT <interrupt number> instruction - any one interrupt from available
256 interrupts.
 INTO instruction - interrupt on overflow
 Single-step interrupt - generated if the TF flag is set. This is a type 1
interrupt. When the CPU processes this interrupt it clears TF flag before
calling the interrupt processing routine.
 Processor exceptions: Divide Error (Type 0), Unused Opcode (type 6)
and Escape opcode (type 7).
 Software interrupt processing is the same as for the hardware interrupts.
 Ex: INT n (Software Instructions)
 Control is provided through:
IF and TF flag bits
IRET and IRETD
Its execution includes the following steps −
 Flag register value is pushed on to the stack.
 CS value of the return address and IP value of the return address are
pushed on to the stack.
 IP is loaded from the contents of the word location ‘type number’ × 4
 CS is loaded from the contents of the next word location.
 Interrupt Flag and Trap Flag are reset to 0
INTERRUPT VECTOR TABLE:
Software interrupts related vector address can be stored in interrupt
vector table. For each interrupt there is 32 bit(4-Bytes) allocated space that is
16-bit for code segment and 16-bit for instruction pointer.
It shows how the 256 interrupt vectors are arranged in the table in
memory. Note that the instruction pointer value is put in as the low word of the
vector, and the code segment register is put in as the high Word of the vector.
Each doubleword interrupt vector is identified by a number from 0 to 255. Intel
calls this number the type of the interrupt.

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The lowest five types are dedicated to specific interrupts, such as the
divide-by-zero interrupt, the single step interrupt and the nonmaskable interrupt.
Later in this chapter we explain the operation of these interrupts in detail.
Interrupt types 5 to 31 are reserved by Intel for use in more complex
microprocessors such as the 80286, 80386, and 80486. In a later chapter we
discuss some of these interrupt types. The upper 224 interrupt types, from 32 to
255, are available for you to use for hardware or software interrupts.
(a) Type 0 interrupt (or Divide-by-zero interrupt)
If the quotient resulting from a DIV (divide) instruction or an IDIV
(integer divide) instruction is too large such that it cannot be accommodated in
the destination register, a divide error occurs. Then 8086 perform a Type 0
interrupt. This then passes the control to a service subroutine at addresses
corresponding to IP0 and CS0 at 0000 H and 0002 H respectively in the pointer
table.
(b) Type 1 interrupt (Single Step interrupt)
The single step interrupt will be enabled only if the trap flag (TF) bit is
set (= 1). The TF bit can be set/reset by software.Single step control is used for
debugging in assembly language. In this mode the processor executes one
instruction and then stops. The contents of various registers and memory
locations can be examined. If the results are found to be ok, then a command
can be inserted for execution of the next instruction. Trap flag cannot be set
directly. This is done by pushing the flags on the stack, changes are made and
then they are popped.
(c) Type 2 interrupt (non-maskable NMI interrupt)
Type 2 interrupt is the non-maskable NMI interrupt and is used for some
emergency situations like power failure. When power fails, an external circuit
detects this and sends an interrupt signal via NMI pin of 8086. The DC supply
remains on for atleast 50 ms via capacitor banks so that the program and data

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remaining in RAM locations can be saved, which were being executed at the
time of power failure.
(d) Type 3 interrupt (break point interrupt)
Type 3 interrupt is a break point interrupt. The program runs up to the
break point when the interrupt occurs. This is achieved by inserting INT 3 at the
point the break is desired. The ISS corresponding to Type 3 interrupt saves the
register contents in the stack and can also be displayed on CRT and the control
is returned to the user. This is used as a software debugging tool, like single
stepping method.
(e) Type 4 interrupt (overflow interrupt)
The software instruction INTO (interrupt on overflow) is inserted in a
program immediately after an arithmetic operation is performed. Insertion of
INTO implements a Type 4 interrupt. When the signed result of an arithmetic
operation on two signed numbers is too large to be stored in the destination
register or else in a memory location, an overflow occurs and the OF (overflow
flag) is set. This initiates INT4 instruction and the program control moves over
to the starting address of the ISS, which corresponds to IP4 and CS4. These two
are stored at address locations 0010 H and 0012 H respectively.
1.12 MEMORY ADDRESSING MECHANISM:
The 8086 based system will have two sets of memory ic‘s one set for even bank
another set for odd bank. The data lines D0-D7 are connected to even bank and
the data lines D8 –D15 are connected to odd bank. The even bank and odd bank
are selected by using control signals ‗BHE‘ and ‗A‘. The memory banks are
selected when these signals are low. Any memory location in the memory is
selected by the address line A1 to A19.
Accessing a Byte-data in a 8086-based Memory System(LOW BANK):
 The two bank memory module of 8086 based storage system requires
one bus-cycle to read/write a data-byte.
 To access a Byte of data in Low-bank, valid address is provided via
address pins A1 to A19 together with A0=’0’ and BHE=’1’.

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Accessing a Byte-data in a 8086 System (HIGH BANK):

 Similarly to access a Byte of data in High-bank, valid address in pins
A1 to A19, A0=’1’ and BHE=’0’ are required to access the data
through D8 to D15 of the data-bus.
 These signals disable the Low bank and enable the High bank to
transfer (in/out) data through D8 to D15 of the data-bus.

Accessing a Alighted Word-data in a 8086 System(EVEN BOUNDARY):

 For even-addressed (aligned) words, only one bus-cycle is needed to
access the word, as both low and high banks are activated at the same
time using A0=’0’ and BHE=’0’
 Note that during this bus-cycle, all 16-bit data is transferred via D0 to
D15 of the data bus.

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Accessing a Unaligned Word-data in a 8086 System(ODD- BOUNDARY):

 For odd-addressed (unaligned) words (with odd P.A of the LSB), two
bus-cycles are required to access the Word-data.
 During the 1st bus-cycle, odd addressed LSB of the word is accessed
from the High-memory -bank via D8 to D15 of data bus
 During 2nd bus-cycle, P.A. is auto-incremented to access the even
address MSB of the word from the Low bank via D0 to D7.
 Note that A0 and BHE signals are reset (violet) accordingly to enable the
required memory bank.

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