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MICROPROCESSORS AND ITS APPLICATIONS
NOTES
UNIT I
THE 8086 PROCESSOR - SOFTWARE ASPECTS

1.1 INTRODUCTION
Microprocessor is a multipurpose, programmable, clock-driven, register-base,

electronic device that reads binary instructions from a storage device called memory, accepts
binary data as input and processes data according to those instructions, and provides
results as output. A typical programmable machine can be represented with four components:
microprocessor, memory, input and output. These four components work together or interact
with each other to perform a given task; thus they comprise a system. The physical
components of this system are called hardware. A set of instructions written for the
microprocessor to perform a task is called a program. A group of programs is called
software.
The microprocessors applications are classified primarily in two categories:

reprogrammable systems and embedded systems. In reprogrammable systems, such as
microcomputers, the microprocessor is used for computing and data processing, a Personal
Computer (PC) is a typical illustration. In an embedded system, the microprocessor is a
part of a final product and is not available for reprogramming to the end user.
The microprocessor operates in binary digits, 0 and 1, also known as bits. Bit is an
abbreviation for the term binary digit. These digits are represented in terms of electrical
voltages.
Each microprocessor recognizes and processes a group of bits called the word, and
microprocessors are classified according to their word length. The fact that the
microprocessor is programmable means it can be instructed to perform given tasks within
its capability. The instructions are entered or stored in a storage device called memory,
which can be read by the microprocessor.
Memory is like the pages of a notebook with space for a fixed number of binary
numbers on each line. However, these pages are generally made of semiconductor material.
Typically, each line is an 8-bit register that can store eight binary bits, and several of these
1 ANNA UNIVERSITY CHENNAI

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register are arranged in a sequence called memory. These registers are always grouped in
NOTES powers of two. The user writes the necessary instructions and data in memory through an
input device and asks the microprocessor to perform the given task and find an answer.
The answer is generally displayed at an output device or stored in memory.
The user can enter (or feed) instructions and data into memory through devices such
as keyboard or simple switches. The microprocessor reads the instruction from memory
and process the data according to those instructions. The result can be displayed by a
device such as seven segment LEDs or printed by a printer. These devices are called
output devices.
1.2 LEARNING OBJECTIVES

 To study the evolution of the microprocessor
 To study the architecture of 8086 microprocessor
 To learn the addressing modes, instruction set and assembler directives
 To under the concept of interrupt and interrupt service routine
1.3 EVOLUTION OF THE MICROPROCESSOR
First microprocessor of Intel was the 4004, in 1971, it was a 4-bit processor. The
4004 took the integrated circuit one step further by locating all the components of a computer
on a chip. It evolved from a development effort for a calculator chip set. The 4004
microprocessor was the central component in a four-chip set, called the 4004 Family:
4001 – 2,048-bit ROM, a 4002 – 320-bit RAM, and a 4003 – 10-bit I/O shift register.
The 4004 had 45 instructions, using only 2,300 transistors in a 16-pin DIP. It was fabricated
with the then-current state-of-the-art P-channel MOSFET technology that only allowed it
to execute instructions at the slow rate of 50 KIPs(kilo instruction per seconds). It ran at
a clock rate of 740kHz (eight clock cycles per CPU cycle of 10.8 microseconds)—the
original goal was 1MHz, to allow it to compute BCD arithmetic. The 4-bit microprocessor
debuted in early video game systems and small microprocessor based control systems.
The main problems with early microprocessor were its speed, word width, and memory
size.
Next, in 1972 was the 4040, which was an enhanced version of the 4004, with an
additional 14 instructions, 8K program space, and interrupt abilities (including shadows of
the first 8 registers). The 4040 operated at a higher speed, although it lacked improvements
in word width and memory size. In the same year, the 8008 was introduced. It had a 14-
bit PC. The 8008 was intended as a terminal controller and was quite similar to the 4040.
The 8008 increased the 4004’s word length from four to eight bits, and doubled the volume
of information that could be processed. The 8008 addressed an expanded memory size
(16K bytes) and contained additional instructions (48) that provided an opportunity for its
application in more advanced systems.

In April 1974, 8080, the successor to 8008 was introduced. It was the first device
with the speed and power to make the microprocessor an important tool for the designer. NOTES
It quickly became accepted as the standard 8-bit processor. The 8080 also addressed
four times more memory (64K bytes) than the 8008 (16K bytes). These improvements
are responsible for ushering in the era of the 8080 and the continuing saga of the
microprocessor. The use of 8080 in personal computers and small business computers
was initiated in 1975 by MITS’s Altair microcomputer.
About six months after Intel released the 8080 microprocessor, Motorola Corporation
introduced its MC6800 microprocessor. The floodgates opened and the 8080 and, to a
lesser degree, the MC6800-ushered in the age of the microprocessor. Soon, other
companies began to introduce their own versions of the 8-bit microprocessor.
In 1977, Intel Corporation introduced an updated version of the 8080-the 8085.

This was to be the last 8-bit, general-purpose microprocessor developed by Intel. Although
only slightly more advanced than an 8080 microprocessor, the 8085 executed software at
an even higher speed. The main advantages of the 8085 were its internal clock generator,
internal system controller, and higher clock frequency. This higher level of component
integration reduced the 8085’s cost and increased its usefulness, Intel has managed to sell
well over 100 million copies of the 8085 microprocessor, its most successful 8-bit, general-
purpose microprocessor. Another company that sold 500 million 8-bit microprocessors is
Zilog Corporation, which produced the Z-80 microprocessor. The Z-80 is machine language
code-compatible with the 8085, which means that there are over 700 million
microprocessors that execute 8085/Z-80 compatible code!
In 1978, Intel released the 8086 microprocessor; a year or so later, it released the
8088. Both devices are 16-bit microprocessors, which executed instructions in as little as
400 ns (2.5 MIPs, or 2.5 millions of instructions per second). This represented a major
improvement over the execution speed of the 8085. In addition, the 8086 and 8088
addressed 1M bytes of memory, which was 16 times more memory than the 8085. (A 1M
byte memory contains 1024K byte-sized memory locations, or 1,048,576 bytes.) This
higher execution speed and larger memory size allowed the 8086 and 8088 to replace
smaller minicomputers in many applications. It is said that the personal computer revolution
did not really start until the 8088 processor was created. This chip became the most
ubiquitous in the computer industry when IBM chose it for its first PC.
In 1982, the 80286 (also known as 286) was next and was the first Intel processor
that could run all the software written for its predecessor, the 8088. The clock speed of the
80286 was increased, so it executed some instructions in as little as 250 ns (4.0 MIPs)
with the original release 8.0 MHz version. Many novices were introduced to desktop
computing with a “286 machine” and it became the dominant chip of its time. It contained
130,000 transistors.

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Applications began to demand faster microprocessor speeds, more memory, and

NOTES wider data paths. This led to the arrival of the 80386 in 1986, by Intel Corporation. The
80386 represented a major overhaul of the 16-bit 8086-80286 architecture. The 80386
was Intel’s first practical 32-bit microprocessor that contained a 32-bit data bus and 32-
bit memory address. A 4G byte memory can store an astounding 1,000,000 typewritten,
double-spaced pages ofASCII text data. The 80386 was available in few modified versions
such as the 80386sX, which addressed 16M bytes of memory through a 16-bit data and
25-bit address bus.
The MC68000 was the first 32-bit microprocessor introduced by Motorola in early
1980s. This was followed by higher levels of functionality on the microprocessor chip in
the MC68000 series. For example, MC68020, introduced later, had 3 times as many
transistors, was about three times as big, and was significantly faster. Motorola 68000 was
one of the second generation systems that were developed in 1973. It was known for its
graphics capabilities. The Motorola 88000 (originally named the 78000) is a 32-bit
processor, one of the first load-store CPUs based on Harvard Architecture.
The 486 (80486) generation of chips really advanced the point-and-click revolution.
It was also the first chip to offer a built-in math coprocessor, which gave the central processor
the ability to do complex math calculations. The 486 had more than a million transistors. In
1993, when Intel lost a bid to trademark the 586, to protect its brand from being copied
by other companies, it coined the name Pentium for its next generation of chips and there
began the Pentium series—Pentium Classic, Pentium II, III and currently, 4.
The Pentium, introduced in 1993, was similar to the 80386 and 80486
microprocessors. The two introductory versions of the Pentium operated with a clocking
frequency of 60 MHz and 66 MHz, and a speed of 110 MIPs, with a higher-frequency
100 MHz one and one-half clocked version that operated at 150 MIPs. Pentium pro
processor contains 21 million transistors, 3 integer units, as well as a floating-point unit to
increase the performance of most software. Pentium pro microprocessor is optimized to
efficiently execute 32-bit code and is used in servers.
1.4 8086 ARCHITECTURE:
The introduction of the 16-bit processor was a result of the increasing demand for
more powerful and high-speed computational resources. 8086 has a 20-bit address bus
can access up to 220 memory locations (1 MB). Frequency range of 8086 is 6-10 MHz.
The 8086 has a much more powerful instruction set along with architectural developments
which imparts substantial programming flexibility and improvement in speed over the 8-bit
microprocessors.
The internal functions of the 8086 processor are partitioned logically into two processing
units. The first is the Bus Interface Unit (BIU) and the second is the Execution Unit (EU) as
shown in the Figure 1.4.1.

MEMORY
INTERFACE NOTES
BIU C-BUS
C-BUS
 6
5
INSTRUCTION
4 STREAM
3 BYTE
B-BUS
2 QUEUE
1
ES
CS
SS
DS
IP
CONTROL
SYSTEM
EU A-BUS
AH AL
BH BL
CH CL ARITHMETIC
DH DL
LOGIC UNIT
SP
BP
SI
DI OPERANDS
FLAGS
Figure1.4.1 Architecture of 8086
Functions of the two blocks BIU and EU are:
 The BIU performs all bus operations such as instruction fetching, reading and
writing operands for memory and calculating the addresses of the memory
operands. The instruction bytes are transferred to the instruction queue.
 EU decodes the instruction fetched by the BIU, executes the instructions and
generates the appropriate control signals.
 Both units operate asynchronously to give the 8086 an overlapping instruction

fetch and execution mechanism that is called as Pipelining. This results in efficient
use of the system bus and system performance.
 BIU contains Instruction queue, Segment registers, Instruction pointer, Address

adder.
 EU contains Control circuitry, Instruction decoder, ALU, General data registers,

Pointer and Index register, Flag register.
The execution unit consists of general data registers such as 16-bit AX, BX, CX and
DX and pointers like SP (Stack Pointer), BP (Base Pointer) and finally index registers
such as source index and destination index registers.

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Register Organization of 8086

NOTES
8086 has a powerful set of registers known as general data registers, segment registers
and pointers and index registers. All of them are 16 bit registers.
Most of the registers contain data/instruction offsets within 64KB memory segment.
There are four different 64KB segments for instructions, stack, data and extra data. To
specify where in 1MB of processor memory these 4 segments are located the 8086
microprocessor uses four segment registers:
Code segment (CS) is a 16-bit register containing address of 64KB segment with
processor instructions. The processor uses CS segment for all accesses to instructions
referenced by instruction pointer (IP) register.
Stack segment (SS) is a 16-bit register containing address of 64KB segment with program
stack. By default, the processor assumes that all data referenced by the stack pointer (SP)
and base pointer (BP) registers are located in the stack segment.
Data segment (DS) is a 16-bit register containing address of 64KB segment with program
data. By default, the processor assumes that all data referenced by general registers (AX,
BX, CX, DX) and index register (SI, DI) is located in the data segment.
Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually
with program data. By default, the processor assumes that the DI register references the
ES segment in string manipulation instructions.
General data registers are 16-bit AX, BX, CX and DX and pointers like SP (Stack
Pointer), BP (Base Pointer) and finally index registers such as source index and destination
index registers. All general registers of the 8086 microprocessor can be used for arithmetic
and logic operations. The general registers are:
Accumulator register consists of 2 8-bit registers AL and AH, which can be combined
together and used as a 16-bit register AX. AL in this case contains the low-order byte of
the word, and AH contains the high-order byte. Accumulator can be used for I/O operations
and string manipulation.
Base register consists of 2 8-bit registers BL and BH, which can be combined together
and used as a 16-bit register BX. BL in this case contains the low-order byte of the word,
and BH contains the high-order byte. BX register usually contains a data pointer used for
based, based indexed or register indirect addressing.
Count register consists of 2 8-bit registers CL and CH, which can be combined together
and used as a 16-bit register CX. When combined, CL register contains the low-order
byte of the word, and CH contains the high-order byte. Count register can be used as a
counter in string manipulation and shift/rotate instructions.

Data register consists of 2 8-bit registers DL and DH, which can be combined together
and used as a 16-bit register DX. When combined, DL register contains the low-order NOTES
byte of the word, and DH contains the high-order byte. Data register can be used as a port
number in I/O operations. In integer 32-bit multiply and divide instruction the DX register
contains high-order word of the initial or resulting number.
The following registers are both general and index registers:
Stack Pointer (SP) is a 16-bit register pointing to program stack.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is
usually used for based, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register
indirect addressing, as well as a source data address in string manipulation instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and
register indirect addressing, as well as a destination data address in string manipulation
instructions.
Other registers:
Instruction Pointer (IP) is a 16-bit register.
Flags is a 16-bit register containing 9 1-bit flags as shown in figure 1.4.2.
The 8086 flags are divided into the conditional flags, which reflect the result of the
previous operation involving the ALU, and the control flags, which control the execution of
special functions.
O-Flag I-Flag S-Flag
D-Flag T-Flag Z-Flag A-Flag P-Flag C-Flag
15 0
Direction Trap Zero Parity
Overflow Interrupt Sign Auxilliary Carry

Carry
Figure 1.4.2 Flags of 8086

Conditional flags are:
 Overflow Flag (OF) - set if the result is too large positive number, or is too small
negative number to fit into destination operand.
 Sign Flag (SF) - set if the most significant bit of the result is set.
 Zero Flag (ZF) - set if the result is zero.

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 Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in
NOTES the AL register.
 Parity Flag (PF) - set if parity (the number of “1” bits) in the low-order byte of the
result is even.
 Carry Flag (CF) - set if there was a carry from or borrow to the most significant
bit during last result calculation.
 Control flags are:
 Direction Flag (DF) - if set then string manipulation instructions will auto-decrement
index registers. If cleared then the index registers will be auto-incremented.
 Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.
 Trap Flag (TF) - if set then single-step interrupt will occur after the next instruction.
To provide flexible base addressing and indexing, a data address may be formed by
adding together a combination of the BX or BP register contents, SI or DI register contents,
and a displacement. The result of such an address computation is called an effective
address (EA) or offset. [The Intel manuals tend to use the term “effective address” when
discussing the machine language and the term “offset” when discussing the assembler
language. The word “displacement” is used to indicate a quantity that is added to the
contents of a register(s) to form an EA.] The final data address, however, is determined by
the EA and the appropriate data segment (DS), extra segment (ES), or stack segment
(SS) register.
The segment group consists of the CS, SS, DS, and ES registers. As indicated above,
the registers that can be used for addressing, the BX, IP, SP, BP, SI, and DI registers, are
only 16 bits wide and, therefore, an effective address has only 16 bits. On the other hand,
the address carried by the address bus is called the physical address it must contain 20
bits. The extra 4 bits are obtained by adding the effective address to the contents of one of
the segment registers. The addition is carried out by appending four 0 bits to the right of the
number in the segment register before the addition is made; thus a 20-bit result is produced.
As an example, if (CS) = 323A and (IP) = 341B, then the next instruction will be fetched
from 357BB.
The advantages of using segment registers are that they:

1. Allow the memory capacity to be 1 megabyte even though the addresses associated
with the individual instructions are only 16 bits wide.
2. Allow the instruction, data, or stack portion of a program to be more than 64K
bytes long by using more than one code, data, or stack segment
3. Facilitate the use of separate memory areas for a program, its data, and the stack.
4. Permit a program and/or its data to be put into different areas of memory each
time the program is executed.

Have you Understand?
Q1.4.a Discuss about the BIU and EU in the 8086 architecture.
NOTES
Q1.4.b What are the various types of registers present in 8086?
Q1.4.c What are the advantages of segmentation in 8086?
Q1.4.d How is the address of the next instruction determined in 8086?
Q1.4.e List the uses of the conditional and control flags in the flag register.
1.5 MACHINE LANGUAGE INSTRUCTIONS

An instruction is divided into groups of bits, or fields, with one field called the operation
code (or op code) indicating what the computer is to do and the other fields, called the
operands indicating the information needed by the instruction in carrying out its task. An
operand may contain a datum, at least part of the address of a datum, an indirect pointer to
a datum, or other information pertaining to the data to be acted on by the instruction.
Instructions may contain several operands, but the more operands and the longer
these operands are, the more memory space they will occupy and the more time it will take
to transfer each instruction into the CPU. In order to minimize the total number of bits in an
instruction, most instructions, particularly those for 16-bit computers are limited to one or
two operands with at least one operand in a two-operand instruction involving a register.
Because the memory and/or I/O spaces are relatively large, memory and I/O addresses
require several hits, but because the number of registers is small, it takes only a few bits to
specify a register. Therefore, one means of conserving instruction bits is to use registers as
much as possible. The two-operand limitation does reduce the flexibility of many instructions,
but normally the extra flexibility is not really needed.
For example, an addition instruction, which involves the two numbers being added
and the result, is reduced to two operands by putting the sum into the location that contained
the addend. This means that the addend is lost, but this is usually not important. If it is
important the addend could be duplicated (by also storing it elsewhere) before the addition
is executed.
1.5.1 Addressing Modes
The way in which an operand is specified is called its addressing mode. The addressing
modes for the 8086 instructions are typical and are discussed below. They are broken into
two categories, those for data and those for branch addresses. Figure 1.5.1 graphically
shows how the operands are determined for the various data-related addressing modes.
These modes are:
Immediate—The datum is either 8 bits or 16 bits long and is part of the instruction.
Direct—The 16-bit effective address of the datum is part of the instruction.
Register—The datum is in the register that is specified by the instruction.

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For a 16-bit operand, a register may be AX. BX, CX, DX, SI. DI, SP, or BP, and for
NOTES an 8-bit operand a register may be AL. AH, BL, BH. CL. CK. DL, or DH.
Register Indirect—The effective address of the datum is in the base register BX or an

index register that is specified by the instruction, i.e.,
BX 
 
EA   DI  
 SI  
 
Register Relative—The effective address is the sum of an 8- or 16-bit displacement

and the contents of a base register or an index register. i.e.,
BX 
 BP   8 bit displaceme nt 
   
EA     (sign extended ) 
 SI   16  bit displaceme nt 
 DI    
Based Indexed—The effective address is the sum of a base register and an index
register. both of which are specified by the instruction. i.e..
BX  SI  
EA     
BP   DI 
Relative Based Indexed—The effective address is the sum of an 8- or 16-bit

displacement and a based indexed address, i.e.,
8 bit displaceme nt 
BX  SI    
EA       (sign extended ) 
BP   DI 16  bit displaceme nt 
 
Example,
If (BX) = 0158 (DI) = 10A5 Displacement = 1B57 (DS) = 2100 and DS is

used as the segment register, then the effective and physical addresses produced by these
quantities and the various addressing modes would be
(i) Direct: EA = 1B57

Physical address lB57 + 21000 = 22B57
(ii) Register: No effective address—datum is in specified register.
(iii) Register indirect assuming register BX:
EA = 0158
Physical address = 0158 + 21000 = 21158

(iv) Register relative assuming register BX:
EA = 0l58 t lB57 = 1CAF
NOTES
Physical address = ICAF + 21000 = 22CAF
(v) Based indexed assuming registers BX and Dl:
EA= 0158 + 10A5 1IFD
Physical address = 1IFD + 21000 221FD
(vi) Relative based indexed assuming BX and DI:
EA= 0158 + 10A5 + 1B57 = 2D54
Physical address = 2D54 + 21000 = 23D54
Instruction
Datum
(a) Immediate
Instruction Memory
EA* Datum
(b) Direct
Instruction Register
Register Datum
(c) Register
Instruction Register Memory

Register EA* Datum
(d) Register indirect
Instruction
Register Displacement
Memory
EA*
+ Datum
Register
Address
(e) Register relative
Instruction Register
Base reg. Index reg. Index
Memory
EA*
+ Datum
Register
Base add.
(f) Based indexed
Instruction
Base reg. Index reg. Displacement
Register Memory
EA*
Index + Datum
Register
Base addr.
(g) Relative based indexed
Figure 1.5.1 Data Related addressing Mode

The addressing modes for indicating branch addresses are graphically defined in
Figure1.5.2 and are:

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Intrasegment Direct—The effective branch address is the sum of an 8- or 16-bit

NOTES displacement and the current contents of IP. When the displacement is 8 bits long, it is
referred to as a short jump. Intrasegment direct addressing is what most computer books
refer to as relative addressing because the displacement is computed “relative” to the IP. It
may be used with either conditional or unconditional branching, but a conditional branch
instruction can have only an 8-bit displacement.
Intrasegment Indirect—The effective branch address is the contents of a register or
memory location that is accessed using any of the above data-related addressing modes
except the immediate mode. The contents of IP are replaced by the effective branch address.
This addressing mode may be used only in unconditional branch instructions.
Intersegment Direct—Replaces the contents of IP with part of the instruction and the
contents of CS with another part of the instruction. The purpose of this addressing mode is
to provide a means of branching from one code segment to another.
Intersegment Indirect—Replaces the contents of IP and CS with the contents of two
consecutive words in memory that are referenced using any of the above data-related
addressing modes except the immediate and register modes.
Instruction
Displacement
+ EA = effective branch address

IP
(a) Intrasegment direct

Register
Effective branch address

Instruction
EA* computed
according to or Memory
Addressing mode
addressing mode
Effective branch address
(b) Intrasegment direct
Instruction CS
Offset Segment
IP
(c) Intrasegment direct

Two consecutive
words in memory
Instruction
EA* computed
Addressing mode according to Branch address offset
addressing mode
Segment address
(d) Intrasegment direct
Figure 1.5.2 Branch Related Addressing Mode

Note that the physical branch address is the new contents of IP plus the contents of
CS multiplied by 1610 an intersegment branch must be unconditional. To demonstrate how NOTES
indirect branching works with some of the data-related addressing modes, suppose that
(BX) = 1256 (SI) = 528F Displacement = 20A1
Then:
(i) With direct addressing the effective branch address is the contents of
20A1 + (DS) x 1610
(ii) With register relative addressing assuming register BX, the effective branch
address is the contents of:
1256 + 20A1 + (DS) x 1610
(iii) With based indexed addressing assuming registers BX and SI, the effective
branch address is the contents of:
1256 + 528F + (DS) X 1610
1.5.2 INSTRUCTION SET OF 8086/8088
The 8086/8088 instructions are categorised into the following main types. This section
explains the function of each of the instructions with suitable examples wherever necessary.
(I) Data Copy / Transfer Instructions This type of instructions are used to transfer
data from source operand to destination operand. All the store, move, load,
exchange, input and output instructions belong to this category.
(ii) Arithmetic and Logical Instructions All the instructions performing arithmetic,
logical, increment, decrement, compare and scan instructions belong to this
category.
(iii) Branch Instructions These instructions transfer control of execution to the
specified address. All the call, jump, interrupt and return instructions belong to this
class.
(iv) Loop Instructions If these instructions have REP prefix with CX used as count
register, they can be used to implement unconditional and conditional loops. The
LOOP, LOOPNX, and LOOPZ instructions belong to this category. These are
useful to implement different loop structures.
(v) Machine Control Instructions These instructions control the machine status.
NOP, HLT, WAIT and LOCK instructions belong to this class.
(vi) Flag Manipulation Instructions All the instructions which directly affect the flag
register, come under this group of instructions. Instructions like CLD, STD, CLI,
STI, etc. belong to this category of instructions.
(vii)Shift and Rotate Instructions These instructions involve the bitwise shifting or
rotation in either direction with or without a count in CX.

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(viii)String Instructions These instructions involve various string manipulation

NOTES operations like load, move, scan, compare, store, etc. These instructions are only
to be operated upon the strings.
1.5.2.1 Data Copy / Transfer Instructions

MOV : Move This data transfer instruction transfers data from one register/memory
location to another register/memory location. The source may be any one of the segment
registers or other general or special purpose registers or a memory location and, another
register or memory location may act as destination.
However, in case of immediate addressing mode, a segment register cannot be a

destination register. In other words, direct loading of the segment registers with immediate
data is not permitted. To load the segment registers with immediate data, one will have to
load any general purpose register with the data and then it will have to be moved to that
particular segment register. The following example instructions explain the fact.
Example Load DS with 5000H.

1. MOV DS, 5000H; Not permitted (invalid)
Thus to transfer an immediate data into the segment register, the correct procedure is
given below.
2. MOV AX, 5000H
MOV DS, AX
It may be noted, here, that both the source and destination operands cannot be memory
locations (Except for string instructions). Other MOV instruction examples are given below
with the corresponding addressing modes.
3. MOV AX, 5000H; Immediate
4. MOV AX, BX; Register
5. MOV AX, [SI]; Indiect
6. MOV AX, [2000H]; Direct
7. MOV AX, 50H [BX]; Based relative, 50H Displacement
PUSH : Push to Stack This instruction pushes the contents of the specified register/
memory location on to the stack. The stack pointer is decremented by 2, after each execution
of the instruction. The actual current stack-top is always occupied by the previously pushed
data. Hence, the push operation decrements SP by two and then stores the two byte
contents of the operand onto the stack. The higher byte is pushed first and then the lower
byte. Thus out of the two decremented stack addressed the higher byte occupies the
higher address and the lower byte occupies the lower address. The examples of these
instructions are as follows :

Example
1. PUSH AX
NOTES
2. PUSH DS
3. PUSH [5000H] ; Content of location 5000H and 5001H in DS are
; pushed onto the stack.
POP : Pop from Stack This instruction when executed, loads the specified register/memory
location with the contents of the memory location of which the address is formed using the
current stack segment and stack pointer as usual. The stack pointer is incremented by 2.
The POP instruction serves exactly opposite to the PUSH instruction.
The examples of these instructions are as shown :
Example
1. POP AX
2. POP DS
3. POP [5000H];
XCHG : Exchange This instruction exchanges the contents of the specified source
and destination operands, which may be registers or one of them may be a memory location.
However, exchange of data contents of two memory locations is not permitted. The examples
are as shown :
Example
1. XCHG [5000H], AX ; This instruction exchanges data between AX and a
memory location [5000H] in the data segment.
2. XCHG BX ; This instruction exchanges data between AX and BX.
IN : Input the port This instruction is used for reading an input port. The address of
the input port may be specified in the instruction directly or indirectly. AL and AX are the
allowed destinations for 8 and 16-bit input operations. DX is the only register (implicit)
which is allowed to carry the port address. The examples are given as shown :
Example
1. IN AL, 0300H ; This instruction reads data from an 8-bit port
; whose address is 0300H and stores it in AL.
2. IN AX ; This instruction reads data from a 16-bit port
; whose address is in DX (implicit) and stores it
; in AX.
OUT : Output to the port : This instruction is used for writing to an output port. The
address of the output port may be specified in the instruction directly or implicitly in DX.
Contents of AX or AL are transferred to a directly or indirectly addressed port after

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execution of this instruction. The data to an odd addressed port is transferred on D8-D15
NOTES while that to an even addressed port is transferred on D0-D7. The registers AL and AX are
the allowed source operands for 8-bit and 16-bit operations respectively. The examples
are given as shown :
Example
1. OUT 0300H, AL ; This sends data available in AL to a port whose
; address is 0330H.
2. OUT AX ; This sends data available in AX to a port whose
; address is specified implicitly in DX.
XLAT : Translate This translate instruction is used for finding out the codes in case of
code conversion problems, using look up table technique. We will explain this instruction
with the aid of the following example.
Suppose, a hexadecimal key pad having 16 keys from 0 to F is interfaced with 8086
using 8255. Whenever a key is pressed, the code of that key (0 to F) is returned in AL.
For displaying the number corresponding to the pressed key on the 7-segment display
device, it is required that the 7-segment code corresponding to the key pressed is found
out and sent to the display port. This translation from the code of the key pressed to the
corresponding 7-segment code is performed using XLAT instruction.
For this purpose, one is required to prepare a look up table of codes, starting from an
offset say 2000H, and store the 7-segment codes for 0 to F at the locations 2000H to
200FH sequentially. For executing the XLAT instruction, the code of the pressed key
obtained from the keyboard (i.e the code to be translated) is moved in AL and the base
address of the look up table containing the 7-segment codes is kept in BX. After execution
of the XLAT instruction, the 7-segement code corresponding to the pressed key is returned
in AL, replacing the key code which was in AL prior to the execution of the XLAT instruction.
To find out the exact address of the 7-segment code from the base address of look up
table, the content of AL is added to BX internally, and the contents of the address pointed
to by this new content of BX in DS are transferred to AL. The following sequence of
instructions, perform the task.
Example
MOV AX, SEG TABLE ; Address of the segment containing look-up-table
MOV DS, AX ; is transferred in DS.
MOV AL, CODE ; Code of the pressed key is transferred in AL.

MOV BX, OFFSET TABLE ; Offset of the code look-up-table in BX.
XLAT ; Find the equivalent code and store in AL.

LEA : Load Effective Address The load effective address instruction loads the offset
of an operand in the specified register. This instruction is more useful for assembly language NOTES
rather than for machine language. Suppose, in an assembly language program, a label
ADR is used. The instruction LEA BX, ADR loads the offset of the label ADR in BX.
LDS/LES : Load Pointer to DE/ES The instruction, Load DS/ES with pointer, loads
the DS or ES register and the specified destination register in the instruction with the
content of memory location specified as source in the instruction. The example of the
operation is shown below.
LDS BX, 5000H/LES BX, 5000H
15 8 7 0 7 0
BX YY XX XX 5000
YY 5001
DS/ES nn mm mm 5002
nn 5003
LDS/LES Instruction Execution

LAHF : Load AH from Lower Byte of Flag This instruction loads the AH register with
the lower byte of the flag register. This instruction may be used to observe the status of all
the condition code flags (except over flow) at a time.
SAHF : Store AH to Lower Byte of Flag Register This instruction sets or resets the
condition code flags (except overflow) in the lower byte of the flag register depending
upon the corresponding bit positions in AH. If a bit in AH is 1, the flag corresponding to the
bit position is set, else it is reset.
PUSHF : Push Flags to Stack The push flag instruction pushes the flag register on to
the stack; first the upper byte and then the lower byte will be pushed on to the stack. The
SP is decremented by 2, for each push operation. The general operation of this instruction
is similar to the PUSH operation.
POPF : Pop Flags from Stack The pop flags instruction loads the flag register completely
(both bytes) from the word contents of the memory location currently addressed by SP
and SS. The SP is incremented by 2 for each pop operation.
1.5.2.2 Arithmetic Instructions

These instructions usually perform the arithmetic operations, like addition, subtraction,
multiplication and division along with the respective ASCII and decimal adjust instructions.
The increment and decrement operations also belong to this type of instructions. The 8086/

DMC 1932
8088 instructions falling under this category are discussed below in significant details. The
NOTES arithmetic instructions affect all the condition code flags. The operands are either the registers
or memory locations or immediate data depending upon the addressing mode.
ADD : Add This instruction adds an immediate data or contents of a memory location
specified in the instruction or a register (source) to the contents of another register
(destination) or memory location. The result is in the destination operand. However, both
the source and destination operands cannot be memory operands. That means memory to
memory addition is not possible. Also the contents of the segment registers cannot be
added using this instruction. All the condition code flags are affected, depending upon the
result. The examples of this instruction are given along with the corresponding modes.
Example
1. ADD AX, 0100H Immediate
2. ADD AX, BX Register
3. ADD AX, [SI] Register Indirect
4. ADD AX, [5000H] Direct
5. ADD [5000H], 0100H Immediate
6. ADD 0100H Destination AX (implicit)
ADC : Add with Carry This instruction performs the same operation as ADD instruction,
but adds the carry flag bit (which may be set as a result of the previous calculations) to the
result. All the condition code flags are affected by this instruction. The examples of this
instruction along with the modes are as follows :
Example
1. ADC 0100H Immediate
2. ADC AX, BX Register
3. ADC AX, [SI] Register Indirect
4. ADC AX, [5000H] Direct
5. ADC [5000H], 0100H Immediate
INC : Increment This instruction increments the contents of the specified register or
memory location by 1. All the condition code flags are affected except the carry flag CF.
This instruction adds 1 to the contents of the operand. Immediate data cannot be operand
of this instruction. The examples of this instruction are as follows:
Example
1. INC AX Immediate
2. INC [BX] Register Indirect
3. INC [5000H] Direct

DEC : Decrement The decrement instruction subtracts 1 from the contents of the
specified register or memory location. All the condition code flags except carry flag are NOTES
affected depending upon the result. Immediate data cannot be operand of the instruction.
The examples of this instruction are as follows:
Example
1. DEC AX Register
2. DEC [5000H] Direct
SUB : Subtract The subtract instruction subtracts the source operand from the destination
operand and the result is left in the destination operand. Source operand may be a register,
memory location or immediate data and the destination operand may be a register or a
memory location, but source and destination operands both must not be memory operands.
Destination operand can not be an immediate data. All the condition code flags are affected
by this instruction. The examples of this instruction along with the addressing modes are as
follows:
Example
1. SUB 0100H Immediate [destintion AX]
2. SUB AX, BX Register
3. SUB AX, [5000H] Direct
4. SUB [5000H], 0100 Immediate
SBB : Subtract with Borrow The subtract with borrow instruction subtracts the source
operand and the borrow flag (CF) which may reflect the result of the previous calculations,
from the destination operand. Subtraction with borrow, here means subtracting 1 from the
subtraction obtained by SUB, if carry (borrow) flag is set.
The result is stored in the destination operand. All the flags are affected (Condition
code) by this instruction. The examples of this instruction are as follows:
Example
1. SBB 0100H Immediate [destintion AX]
2. SBB AX, BX Register
3. SBB AX, [5000H] Direct
4. SBB [5000H], 0100 Immediate
CMP : Compare This instruction compares the source operand, which may be a
register or an immediate data or a memory location, with a destination operand that may
be a register or a memory location. For comparison, it subtracts the source operand from
the destination operand but does not store the result anywhere. The flags are affected
depending upon the result of the subtraction. If both of the operands are equal, zero flag is

DMC 1932
set. If the source operand is greater than the destination operand, carry flag is set or else,
NOTES carry flag is reset. The examples of this instruction are as follows:
Example
1. CMP 0100H Immediate
2. CMP 0100 Immediate [AX implicit]
3. CMP [5000H], 0100H Direct
4. CMP BX, [SI] Register indirect
5. CMP BX, CD Register
AAA : ASCII Adjust After Addition The AAA instruction is executed after an ADD
instruction that adds two ASCII coded operands to give a byte of result in AL. The ADD
instruction converts the resulting contents of AL to unpacked decimal digits. After the
addition, the ADD instruction examines the lower 4 bits of AL to check whether it contains
a valid BCD number in the range 0 to 9. If it is between 0 to 9 and AF is zero, AAA sets
the 4 high order bits of AL to 0. The AH must be cleared before addition. If the lower digit
of AL is between 0 to 9 and AF is set, 06 is added to AL. The upper 4 bits of AL are
cleared and AH is incremented by one.
If the value in the lower nibble of AL is greater than 9 then the AL is incremented by
06, AH is incremented by 1, the AF and CF flags are set to 1, and the higher 4 bits of AL
are cleared to 0. The remaining flags are unaffected. The AH is modified as sum of previous
contents (usually 00) and the carry from the adjustment. This instruction does not give
exact ASCII codes of the sum, but they can be obtained by adding 3030H to AX.
1. AL 5 7 -- Before to AAA
AL 0 7 -- After AAA execution
2. AL 5 A
-- Previous to AAA
AH 0 0
A > 9, hence A + 6 = 1010 + 0110

= 10000 B
= 10 H
AX
0 0 5 A - Previous to AAA
AX
01 0 0 - After AAA execution
ASCII Adjust After Addition Instruction

AAS : ASCII Adjust AL After Subtraction AAS instruction corrects the result in AL
register after subtracting two unpacked ASCII operands. The result is in unpacked decimal NOTES
format. If the lower 4 bits of AL register are greater than 9 or if the AF flag is 1, the AL is
decremented by 6 and AH register is decremented by 1, the CF and AF are set to 1.
Otherwise, the CF and AF are set to 0, the result needs no correction. As a result, the
upper nibble of AL is 00 and the lower nibble may be any number from 0 to 9. The
procedure is similar to the AAA instruction. AH is modified as difference of the previous
contents (usually zero) of AH and the borrow for adjustment.
AAM : ASCII Adjust for Multiplication This instruction, after execution, converts the
product available in AL into unpacked BCD format. This follows a multiplication instruction.
The lower byte of result (unpacked) remains in AL and the higher byte of result remains in
AH. The example given below explains execution of the instruction. Suppose, a product is
available in AL, say AL = 5D. AAM instruction will form unpacked BCD result in AX. DH
is greater than 9, so add 6 (0110) to it D+6 = 13H. LSD of 13H is the lower unpacked
byte for the result. Increment AH by 1, 5+1 = 6 will be the upper unpacked byte of the
result. Thus after the execution, AH = 06 and AL = 03.
AAD : ASCII Adjust for Division Though the names of these two instructions (AAM
and AAD) appear to be similar, there is a lot of difference between their functions. The
AAD instruction converts two unpacked BCD digits in AH and AL to the equivalent binary
number in AL. This adjustment must be made before dividing the two unpacked BCD
digits in AX by an unpacked BCD byte. PF, SF, ZF are modified while AF, CF, OF are
undefined, after the execution of the instruction AAD. The example explains the execution
of the instruction. In the instruction sequence, this instruction appears before DIV instruction
unlike AAM appears after MUL. Let AX contain 0508 unpacked BCD for 58 decimal,
and DH contain 02H.
Example
AX 5 8
AAD result in AL 05 3A 58D = 3A H in AL
The result of AAD execution will give the hexadecimal number 3A in AL and 00 in
AH. Note that 3A is the hexadecimal equivalent of 58 (decimal). Now, instruction DIV
DH may be executed. So rather than ASCII adjust for division, it is ASCII adjust before
division. All the ASCII adjust instructions are also called as unpacked BCD arithmetic
instructions. Now, we will consider the two instructions related to packed BCD arithmetic.
DAA : Decimal Adjust Accumulator This instruction is used to convert the result of the
addition of two packed BCD numbers to a valid BCD number. The result has to be only in
AL. If the lower nibble is greater than 9, after addition or if AF is set, it will add 06 to the
lower nibble in AL. After adding 06 in the lower nibble of AL, if the upper nibble of AL is

DMC 1932
greater than 9 or if carry flag is set, DAA instruction adds 60H to AL. The examples given
NOTES below explain the instruction.
Example
(i) AL = 53 CL = 29
ADD AL, CL ; AL  (AL) + (CL)
; AL  53 + 29
; AL  7C
; AL  7C + 06 (as C>9)
; AL  82
(ii) AL = 73 CL = 29
ADD AL, CL ; AL  AL + CL
; AL  73 + 29
; AL  9C
; AL  02 and CF = 1
AL = 73
+
CL = 29
9C
+6
A2
+60
CF = 1 0 2 in AL
The instruction DAA affects AF, CF, PF, and ZF flags. The OF is undefined.
DAS : Decimal Adjust After Subtraction This instruction converts the result of
subtraction of two packed BCD numbers to a valid BCD number. The subtraction has to
be in AL only. If the lower nibble of AL is greater than 9, this instruction will subtract 06
from lower nibble of AL. If the result of subtraction sets the carry flag or if upper nibble is
greater than 9, it subtracts 60H from AL. This instruction modifies the AF, CF, SF, PF and
ZF flags. The OF is undefined after DAS instruction. The examples are as follows:
Example
(i) AL = 75 BH = 46
SUB AL, BH ; AL  2 F = (AL) - (BH)

; AF  1
DAS ; AL  2 9 (as F > 9, F - 6 = 9)
NOTES
(ii) AL = 38 CH = 61
SUB AL, CH ; AL  D 7 CF = 1 (borrow)
; AL  7 7 (as D > 9, D - 6 = 7)
; CF = 1 (borrow)
NEG : Negate The negate instruction forms 2’s complement of the specified destination
in the instruction. For obtaining 2’s complement, it subtracts the contents of destination
from zero. The result is stored back in the destination operand which may be a register or
a memory location. If OF is set, it indicates that the operation could not be completed
successfully. This instruction affects all the condition code flags.
MUL : Unsigned Multiplication Byte or Word This instruction multiplies an unsigned

byte or word by the contents of AL. The unsigned byte or word may be in any one of the
general purpose registers or memory locations. The most significant word of the result is
stored in DX, while the least significant word of the result is stored in AX. All the flags are
modified depending upon the result. The example instructions are as shown. Immediate
operand is not allowed in this instruction. If the most significant byte or word of the result
is ‘0’ CF and OF both will be set.
Example
(i) MUL BH ; (AX)  (AL) + (BH)
(ii) MUL CX ; (DX) (AX)  (AX) + (CX)
(iii) MUL WORD PTR [SI]; (DX) (AX)  (AX) + ([SI])
IMUL : Signed Multiplication This instruction multiplies a signed byte in source operand
by a signed byte in AL or signed word in source operand by signed word in AX. The
source can be a general purpose register, memory operand, index register or base register,
but it cannot be an immediate data. In case of 32-bit results, the higher order word (MSW)
is stored in DX and the lower order word is stored in AX. The AF, PF, SF, and ZF flags
are undefined after IMUL. If AH and DX contain parts of 16 and 32-bit result respectively,
CF and OF both will be set. The AL and AX are the implicit operands in case of 8 bits and
16 bits multiplications respectively. The unused higher bits of the result are filled by sign bit
and CF, AF are cleared. The example instructions are given as follows:
Example
1. IMUL BH
2. IMUL CX
3. IMUL [SI]

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CBW : Convert Signed Byte to Word This instruction converts a signed byte to a
NOTES signed word. In other words, it copies the sign bit of a byte to be converted to all the bits
in the higher byte of the result word. The byte to be converted must be in AL. The result
will be in AX. It does not affect any flag.
CWD : Convert Signed Word to Double Word This instruction copies the sign bit of
AX to all the bits of the DX register. This operation is to be done before signed division. It
does not affect any flag.
DIV : Unsigned Division This instruction performs unsigned division. It divides an unsigned
word or double word by a 16-bit or 8-bit operand. The dividend must be in AX for 16-bit
operation and divisor may be specified using any one of the addressing modes except
immediate. The result will be in AL (quotient) while AH will contain the remainder. If the
result is too big to fit in AL, type 0 (divide by zero) interrupt is generated. In case of a
double word dividend (32-bit), the higher word should be in DX and lower word should
be in AX. The divisor may be specified as already explained. The quotient and the remainder,
in this case, will be in AX and DX respectively. This instruction does not affect any flag.
IDIV : Signed Division This instruction performs the same operation as the DIV
instruction, but with signed operands. The results are stored similarly as in case of DIV
instruction in both cases of word and double word divisions. The results will also be signed
numbers. The operands are also specified in the same way as DIV instruction. Divide by 0
interrupt is generated, if the result is too big to fit in AX (16-bit dividend operation) or AX
and DX (32-bit dividend operation). All the flags are undefined after IDIV instruction.
1.5.2.3 Logical Instructions

These types of instructions are used for carrying out the bit by bit shift, rotate, or
basic logical operations. All the condition code flags are affected depending upon the
result. Basic logical operations available with 8086 instruction set are AND, OR, NOT,
and XOR. The instruction for each of these operations are discussed as follows.
AND : Logical AND This instruction bit by bit ANDs the source operand that may be
an immediate, a register or a memory location to the destination operand that may be a
register or a memory location. The result is stored in the destination operand. At least one
of the operands should be a register or a memory operand. Both the operands cannot be
memory locations or immediate operands. An immediate operand cannot be a destination
operand. The examples of this instruction are as follows:
Example
1. AND AX, 0008H
2. AND AX, BX
3. AND AX, [5000H]
4. AND [5000H], DX

If the content of AX is 3F0FH, the first example instruction will carry out the operation as
given below. The result 3F9FH will be stored in the AX register. NOTES
0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 = 3F0F H [AX]
                AND
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = 0008 H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = 0008 H [AX]
The result 0008H will be in AX.

OR : Logical OR The OR instruction carries out the OR operation in the same way as
described in case of the AND operation. The limitations on source and destination operands
are also the same as in case of AND operation. The examples are as follows:
Example
1. OR AX, 0098H
2. OR AX, BX
3. OR AX, [5000H]
4. OR [5000H], 0008H
The contents of AX are say 3F0FH, then the first example instruction will be carried out as
given below.
0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 = 3F0F H
                OR
0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 = 0098 H
0 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 = 3F9F H
Thus the result 3F9FH will be stored in the AX register.
NOT : Logical Invert The NOT instruction compliments (inverts) the contents of an
operand register or a memory location, bit by bit. The examples are as follows :
Example
1. NOT AX
2. NOT [5000H]
If the content of AX is 200FH, the first example instruction will be executed as shown.

DMC 1932
NOTES AX = 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1
invert                
1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0
Result
in AX = D F F 0
The result DFF0H will be stored in the destination register AX.

XOR : Logical Exclusive OR The XOR operation is again carried out in a similar way
to the AND or OR operation. The constraints on the operands are also similar. The XOR
operation gives a high output, when the 2 input bits are dissimilar. Otherwise, the output is
zero. The example instructions are as follows:
Example
1. XOR AX, 0098H
2. XOR AX, BX
3. XOR AX, [5000H]
If the content of AX is 3F0FH, then the first example instruction will be executed as
explained. The result 3F97H will be stored in AX.
AX = 3F0FH = 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1
XOR     
0098H = 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0
AX = RESULT = 0 0 1 1 1 1 1 1 1 0 0 1 0 1 1 1
= 3F97H
TEST : Logical Compare Instruction The TEST instruction performs a bit by bit
logical AND operation on the two operands. Each bit of the result is then set to 1, if the
corresponding bits of both operands are 1, else the result is reset to 0. The result of this
anding operating is not available for further use, but flags are affected. The affected flags
are OF, CF, SF, ZF and PF. The operands may be registers, memory or immediate data.
The examples of this instruction are as follows:
Example
1. TEST AX, BX
2. TEST [0500], 06H
3. TEST [BX] [DI], CX
SHL/SAL : Shift logical/Arithmetic Left These instructions shift the operand word or
byte bit by bit to the left and insert zeros in the newly introduced least significant bits. In

case of all the SHIFT and ROTATE instructions, the count is either 1 or specified by
register CL. The operand may reside in a register or a memory location but cannot be an NOTES
immediate data. All flags are affected depending upon the result. Figure 1.5.3 explains the
execution of this instruction. It is to noted here that the shift operation is through carry flag.
BIT POSITIONS CF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPERAND 1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 1
SHL RESULT 1st 1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 1 0

inserted
nd
SHL RESULT 2 0 1 0 1 1 0 0 1 0 1 0 0 1 0 1 0 0
inserted
Figure 1.5.3 Execution of SHL/SAL Instruction

SHR : Shift Logical Right This instruction performs bit-wise right shifts on the operand
word or byte that may reside in a register or a memory location, by the specified count in
the instruction and inserts zeros in the shifted positions. The result is stored in the destination
operand. Figure 1.5.4 explains execution of this instruction. This instruction shifts the operand
through carry flag.
BIT POSITIONS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CF
OPERAND 1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 1
Count = 1 0 1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 1
inserted
Count = 2 0 0 1 0 1 0 1 1 0 0 1 0 1 0 0 1 0
inserted
Figure 1.5.4 Execution of SHR Instruction

SAR : Shift Arithmetic Right This instruction performs right shift on the operand word
or byte, that may be a register or a memory location by the specified count in the instruction
and inserts the most significant bit of the operand in the newly inserted positions. The result
is stored in the destination operand. Figure 1.5.5 explains execution of the instruction. All
the condition code flags are affected. This shift operation shifts the operand through carry
flag.
BIT POSITIONS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CF
OPERAND 1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 1
Count = 1 1 1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 1
inserted MSB = 1
Count = 2 1 1 1 0 1 0 1 1 0 0 1 0 1 0 0 1 0
inserted MSB = 1
Figure 1.5.5 Execution of SAR Instruction

DMC 1932
Immediate operand is not allowed in any of the shift instructions.

NOTES
ROR : Rotate Right without Carry This instruction rotates the contents of the destination
operand to the right (bit-wise) either by one or by the count specified in CL, excluding
carry. The least significant bit is pushed into the carry flag and simultaneously it is transferred
to the most significant bit position at each operation. The remaining bits are shifted right in
the specified positions. The PF, SF and ZF flags are left unchanged by the rotate operation.
The operand may be a register or a memory location but it cannot be an immediate operand.
Figure 1.5.6 explains the operation. The destination operand may be a register (except a
segment register) or a memory location.
BIT POSITIONS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CF
OPERAND 1 0 1 0 1 1 1 1 0 1 0 1 1 1 0 1 x
Count = 1 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 0 1
Count = 2 0 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 0
Figure 1.5.6 Execution of ROR Instruction
ROL : Rotate Left without Carry This instruction rotates the contents of the destination
operand to the left by the specified count (bit-wise) excluding carry. The most significant
bit i pushed into the carry flag as well as the least significant bit position at each operation.
The remaining bits are shifted left subsequently by the specified count positions. The PF,
SF, and ZG flags are left unchanged by this rotate operation. The operand may be a
register or a memory location. Figure1.5.7 explains the operation.
BIT POSITIONS CF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPERAND 1 0 1 0 1 1 1 1 0 1 0 1 1 1 0 1
SHL RESULT 1st 1 0 1 0 1 1 1 1 0 1 0 1 1 1 0 1 1
SHL RESULT 2nd 0 1 0 1 1 1 1 1 0 1 1 1 1 0 1 1 0
Figure 1.5.7 Execution of ROL Instruction
RCR : Rotate Right through Carry This instruction rotates the contents (bit-wise) of
the destination operand right by the specified count through carry flag (CF). For each
operation, the carry flag is pushed into the MSB of the operand, and the LSB is pushed
into carry flag. The remaining bits are shifted right by the specified count positions. The SF,
PF, ZF are left unchanged. The operand may be a register or a memory location. Figure
.5.8 explains the operation.

BIT POSITIONS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CF NOTES

(arbitrary)
OPERAND 1 0 1 0 1 1 1 1 0 1 0 1 1 1 1 0 0
Count = 1 0 1 0 1 0 1 1 1 1 0 1 0 1 1 1 0 1
Figure 1.5.8 Execution of RCR Instruction
RCL : Rotate Left through Carry This instruction rotates the contents (bit-wise) of the
destination operand left by the specified count through the carry flag (CF). For each
operation, the carry flag is pushed into the LSB, and the MSB is pushed into carry flag.
The remaining bits are shifted left by the specified positions. The SF, PF, ZF are left
unchanged. The operand may be a register or a memory location. Figure 1.5.9 explains
the operation.
BIT POSITIONS CF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(arbitrary)
OPERAND 0 1 0 0 1 1 1 0 1 1 0 1 1 0 1 0 1
Count = 1 1 0 0 1 1 1 0 1 1 0 1 1 0 1 0 1 0
Figure 1.5.9 Execution of RCL Instruction
1.5.2.4 String Manipulation Instructions
A series of data bytes or words available in memory at consecutive locations, to be

referred to collectively or individually, are called as byte strings or word strings. For example,
a string of characters may be located in consecutive memory locations, where each character
may be represented by its ASCII equivalent. For referring to a string, two parameters are
required,
(a) starting or end address of the string and
(b) length of the string.
The length of a string is usually stored as count in CX register. The pointers and
counters may be modified at each iteration, till the required condition for proceeding further
is satisfied. On the other hand, the 8086 supports a set of more powerful instructions for
string manipulations. The incrementing or decrementing of the pointer, in case of 8086
string instructions, depends upon the direction flag (DF) status. If it is a byte string operation,
the index registers are updated by one. On the other hand, if it is a word string operation,
the index registers are updated by two. The counter in both the cases, is decremented by
one.

DMC 1932
REP : Repeat Instruction Prefix This instruction is used as a prefix to other instructions.
NOTES The instruction to which the REP prefix is provided, is executed repeatedly until the CX
register becomes zero (at each iteration CX is automatically decremented by one). When
CX becomes zero, the execution proceeds to the next instruction in sequence. There are
two more options of the REP instruction. The first is REPE/REPZ, i.e. repeat operation
while equal/zero. The second is REPNE/REPNZ allows for repeating the operation while
not equal/not zero. These options are used for CMPS, SCAS instructions only, as instruction
prefixes.
MOVSB/MOVSW : Move String Byte or String Word Suppose a string of bytes,

stored in a set of consecutive memory locations is to be moved to another set of destination
locations. The starting byte of the source string is located in the memory location whose
address may be computed using SI (source index) and DS (data segment) contents. The
starting address of the destination locations where this string has to be relocated is given by
DI (destination index) and ES (extra segment) contents. The starting address of the source
string is 10H*DS+[SI], while the starting address of the destination string is 10H*ES+[DI].
The MOVSB/MOVSW instruction thus, moves a string of bytes/words pointed to by DS:
SI pair (source) to the memory location pointed to by ES:DIU pair (destination). The REP
instruction prefix is used with MOVS instruction to repeat it by a value given in the counter
(CX). The length of the byte string or word string must be stored in CX register. No flags
are affected by this instruction.
After the MOVS instruction is executed once, the index registers are automatically
updated and CX isely or individually, are called as byte strings or word strings. For example,
a string of characters may be locted, in case of all the string manipulation instructions. The
following string of instructions explain the execution of the MOVS instruction.
Example
MOV AX, 5000H ; Source segment address is 5000H
MOV DS, AX ; Load it to DS.
MOV AX, 6000H ; Destination segment address is 6000H
MOV ES, AX ; Load it to ES.
MOV CX, OFFH ; Move length of the string to counter register CX.
MOV SI, 1000H ; Source index address 1000H is moved to SI.
MOV DI, 2000H ; Destination index address 2000H is moved to DI.
CLD ; Clear DF, i.e. set auto increment mode.
REP MOVSB ; Move OFFH string bytes from source address to destination.
CMPS : Compare String Byte of String Word The CMPS instruction can be used to
compare two strings of bytes or words. The length of the string must be stored in the

register CX. If both the byte or word strings are equal, zero flag is set. The flags are
affected in the same way as CMP instruction. The DS:SI and ES:DI point to the two NOTES
strings. The REP instruction prefix is used to repeat the operation till CX (counter) becomes
zero or the condition specified by the REP prefix is false.
The following string of instructions, explain the instruction. The comparison of the
string starts from initial byte or word of the string, after each comparison the index registers
are updated depending upon the direction flag and the counter is decremented. This byte
by byte or word by word comparison continues till a mismatch is found. When, a mismatch
is found, the carry and zero flags are modified appropriately and the execution proceeds
further.
Example
MOV AX, SEG1 ; Segment address of STRING1, i.e. SEG1 is
moved to AX.
MOV DS, AX ; Load it to DS.
MOV AX, SEG2 ; Segment address of STRING2, i.e. SEG2 is
moved to AX.
MOV SI, OFFSET STRING 1 ; Offset of STRING1 is moved to SI.
MOV DI, OFFSET STRING 2 ; Offset of STRING2 is moved to DI.
MOV CD, 010H ; Length of the string is moved to CD.
CLD ; Clear DF, i.e. set auto increment mode.
REPE CMPSW ; Compare 010H words of STRING1 and
; STRING2, while they are equal, if a mismatch
is found,
; modify the flags and proceed with further
execution.
If both strings are completely equal, i.e., CX becomes zero, the ZF is set, otherwise,
ZF is reset.
SCAS : Scan String Byte or String Word This instruction scans a string of bytes or
words for an operand byte or word specified in the register AL or AX. The string is
pointed to by ES:DI register pair. The length of the string is stored in CX. The DF controls
the mode for scanning of the string as stated in case of MOVSB instruction. Whenever a
match to the specified operand, is found in the string, execution stops and the zero flag is
set. If no match is found, the zero flag is reset. The REPNE prefix is used with the SCAS
instruction. The pointers and counters are updated automatically, till a match is found. The
following string instruction elaborates the use of SCAS instruction.

DMC 1932
Example
NOTES MOV AX, SEG ; Segment address of the string, i.e. SEG is moved to AX.
MOV DI, OFFSET ; String offset i.e. OFFSET
MOV CX, 010H ; Length of the string is moved to CX.
MOV AX, WORD ; The word to be scanned for, i.e. WORD is in AL.
CLD ; Clear DF.
REPNE SCASW ; Scan the 010H bytes of the string, till a match to
; WORD is found.
This string of instructions finds out, if it contains WORD. If the WORD is found in the
word string, before CX becomes zero, the ZF is set, otherwise the ZF is reset. The scanning
will continue till a match is found. Once a match is found the execution of the programme
proceeds further.
LODS : Load String Byte or String Word The LODS instruction loads the AL/AX
register by the content of a string pointed to by DS:SI register pair. The SI is modified
automatically depending upon DF. If it is a byte transfer (LODSB), the SI is modified by
one and if it is a word transfer (LODSW), the SI is modified by two. No other flags are
affected by this instruction.
STOS : Store String Byte or String Word The STOS instruction stores the AL/AX
register contents to a location in the string pointed by ES:DI register pair. The DI is modified
accordingly. No flags are affected by this instruction.
The direction flag controls the string instruction execution. The source index SI and
destination index DI are modified after each iteration automatically. If DF = 1, then the
execution follows auto decrement mode. In this mode, SI and DI are decremented
automatically after each iteration (by 1 or 2 depending upon byte or word operations).
Hence, in autodecrementing mode, the strings are referred to by their ending addresses. If
DF = 0, then the execution follows autoincrement mode. In this mode, SI and DI are
incremented automatically (by 1 or 2 depending upon byte or word operation) after each
iteration, hence the strings, in this case, are referred to by their starting addresses. Chapter
3 on assembly language programming explains the use of some of these instructions in
assembly language programs.
1.5.2.5 Control Transfer of Branching Instructions
The control transfer instructions transfer the flow of execution of the program to a
new address specified in the instruction directly or indirectly. When this type of instruction
is executed, the CS and IP registers get loaded with new values of CS and IP corresponding

to the location where the flow of execution is going to be transferred. Depending upon the
addressing modes, the CS may or may not be modified. This type of instructions are NOTES
classified in two types :
Unconditional Control Transfer (Branch) Instructions In case of unconditional control
transfer instructions, the execution control is transferred to the specified location independent
of any status or condition. The CS and IP are unconditionally modified to the new CS and
IP.
Conditional Control Transfer (Branch) Instructions In the conditional control transfer
instructions, the control is transferred to the specified location provided the result of the
previous operation satisfies a particular condition, otherwise, the execution continues in
normal low sequence. The results of the previous operations are replicated by condition
code flags.
In other words, using this type of instruction the control will be transferred to a particular
specified location, if a particular flag satisfies the condition.
1.5.2.6 Unconditional Branch Instruction
CALL : Unconditional Call This instruction is used to call a subroutine from a main
program. In case of assembly language programming, the term procedure is used
interchangeably with subroutine. The address of the procedure may be specified directly
or indirectly depending upon the addressing mode. There are again two types of procedures
depending upon whether it is available in the same segment (Near CALL, i.e +32
displacement) or in an other segment (Far CALL, i.e anywhere outside the segment). The
modes for them are respectively called as intrasegment and intersegment addressing modes.
This instruction comes under unconditional branch instructions and can be described as
shown with the coding formats. On execution, this instruction stores the incremented IP
(i.e. address of the next instruction) and CS onto the stack along with the flags and loads
the CS and IP registers, respectively, with the segment and offset addresses of the procedure
to be called.
D7 D0 D7 D0 D7 D0
Direct Near OPCODE DISP.LB DISP.HB
D7 D0 D7 D0
Indirect Near OPCODE OPCODE
D7 D0 D7 D0 D7 D0 D7 D0 D7 D0
Direct Far OPCODE LB HB LB HB
OFFSET SEGMENT
D7 D0 D7 D0
Indirect Far OPCODE OPCODE

DMC 1932
RET : Return from the Procedure At each CALL instruction, the IP and CS of the
NOTES next instruction is pushed onto stack, before the control is transferred to the procedure. At
the end of the procedures, the RET instruction must be executed. When it is executed, the
previously stored content of IP and CS along with flags are retrieved into the CS, IP and
flag registers from the stack and the execution of the main program continues further. The
procedure may be a near or a far procedure. In case of a FAR procedure, the current
contents of SP points to IP and CS at the time of return. While in case of a NEAR procedure,
it points to only IP. Depending upon the type of procedure and the SP contents, the RET
instruction is of four types.
1. Return within segment
2. Return within segment adding 16-bit immediate displacement to the SP contents.
3. Return intersegment
4. Return intersegment adding 16-bit immediate displacement to the SP contents.
INT N : Interrupt Type N In the interrupt structure of 8086/8088, 256 interrupts are
defined corresponding to the types from 00H to FFH. When an INT N instruction is
executed, the TYPE byte N is multiplied by 4 and the contents of IP and CS of the
interrupt service routine will be taken from the hexadecimal multiplication (Nx4) as offset
address and 0000 as segment address. In other words, the multiplication of type N by 4
(offset) points to a memory block in 0000 segment, which contains the IP and CS values
of the interrupt service routine. For the execution of this instruction, the IF must be enabled.
Example
Thus the instruction INT 20H will find out the address of the interrupt service routine as
follows :
INT 20H
Type* 4 = 20 * 4 = 80H
Pointer to IP and CS of the ISR is 0000 : 0080 H
INTO : Interrupt on Overflow This is executed, when the overflow flag OF is set. The
new contents of IP and CS are taken from the address 0000:0000 as explained in INT
type instruction. This is equivalent to a Type 4 interrupt instruction.
JMP : Unconditional Jump This instruction unconditionally transfers the control of

execution to the specified address using an 8-bit or 16-bit displacement (intrasegment
relative, short or long) or CS : IP (intersegment director far). No flags are affected by this
instruction. Corresponding to the three methods of specifying jump addresses, the JUMP
instruction has the following three formats.

JUMP DISP 8-bit Intrasegment, relative, near jump NOTES

JUMP DISP 16-bit (LB) DISP 16-bit (UB) Intrasegment, relative, Far jump
JUMP IP(LB) IP(UB) CS(LB) CS(UB) Intersegment, direct, jump
RET : Return from ISR When an interrupt service routine is to be called, before
transferring control to it, the IP, CS and flag register are stored on the stack to indicate the
location from where the execution is to be continued, after the ISR is executed. So, at the
end of each ISR, when IRET is executed, the values of IP, CS and flags are retrieved from
the stack to continue the execution of the main program. The stack is modified accordingly.
LOOP : Loop Unconditionally This instruction executes the part of the program from
the label or address specified in the instruction up to the loop instruction, CX number or
times. The following sequence explains the execution. At each iteration, CX is determined
automatically. In other words, this instruction implements DECREMENT COUNTER
and JUMP IF NOT ZERO structure.
Example
MOV CX, 0005 ; NUMBER OF TIMES IN CX
MOV BX, OFF7H ; DATA TO BX
LABEL 1 : MOV AX, CODE1
OR BX, AX
AND DX, AX
LOOP LABEL
The execution proceeds in sequence, after the loop is executed, CX number of times.
If CX is already 00H, the execution continues sequentially. No flags are affected by this
instruction.
1.5.2.7 Conditional Branch Instructions
When these instructions are executed, they transfer execution control to the address
specified relatively in the instruction, provided the condition implicit in the opcode is satisfied,
otherwise, the execution continues sequentially. The conditions, here, means the status of
condition code flags. These type of instructions do not affect any flag. The address has to
be specified in the instruction relatively in terms of displacement which must lie within -
80H to 7FH (or - 128 to 127) bytes from the address of the branch instruction.
In other words, only short jumps can be implemented using conditional branch
instructions. A label may represent the displacement, if it lies within the above specified
range. The different 8086/8088 conditional branch instructions and their operations are
listed in Table 1.5.1.

DMC 1932
Table 1.5.1 Conditional Branch Instructions

NOTES Mnemonic Displacement Operation
1 JZ/JE Label Transfer execution control to address ‘Label’, if ZF=1.
2 JNZ/JNE Label Transfer execution control to address ‘Label’, if ZF=0.
3 JS Label Transfer execution control to address ‘Label’, if SF=1.
4 JNS Label Transfer execution control to address ‘Label’, if SF=0.
5 JO Label Transfer execution control to address ‘Label’, if OF=1.
6 JNO Label Transfer execution control to address ‘Label’, if OF=0.
7 JP/JPE Label Transfer execution control to address ‘Label’, if PF=1.
8 JNP Label Transfer execution control to address ‘Label’, if PF=0.
9 JB/JNAE/JC Label Transfer execution control to address ‘Label’, if CF=1.
10 JNB/JAE/JNC Label Transfer execution control to address ‘Label’, if CF=0.
11 JBE/JNA Label Transfer execution control to address ‘Label’, if CF=1
or ZF=1.
12 JNBEJA Label Transfer execution control to address ‘Label’, if CF=0
or ZF=0.
13 JL/JNGE Label Transfer execution control to address ‘Label’, if neither
SF=1 nor OF=1.
14 JNL/JGE Label Transfer execution control to address ‘Label’, if neither
SF=0 nor OF=0.
15 JLE/JNC Label Transfer execution control to address ‘Label’, if neither
ZF=1 or neither SF nor OF is 1.
16 JNLE/JE Label Transfer execution control to address ‘Label’, if neither
ZF=0 or atleast any one of SF and OF is 1 (Both SF &
OF are not 0).
The last four instructions are used in case of decisions based on signed binary number
operations, while the remaining instructions can be used for unsigned binary operations.
The terms above and below are generally used for unsigned numbers, while the terms less
and greater are used for signed numbers. A conditional jump instruction, that does not
check status flags for condition testing, is given as follows:
JCXZ ‘LABEL’ TRANSFER EXECUTION CONTROL TO
ADDRESS ‘LABEL’, IF CX=0.
The conditional LOOP instructions are given in Table 1.5.2 with their meanings. These
instructions may be used for implementing structures like DO_WHILE, REPEAT_UNTIL,
etc.

Table 1.5.2 Conditional Loop Instructions
NOTES
Mnemonic Displacement Operation
1 LOOPZ/LOOPE Label Loop through a sequence of instructions
from ‘Label’ while ZF = 1 and CX  0.
2 LOOPNZ/LOOPENE Label Loop through a sequence of instructions
from ‘Label’ while ZF = 0 and CX  0.
This ideas about all these instructions will be more clear with programming practice.
1.5.2.8 Flag Manipulation and Processor Control Instructions
These instructions control the functioning of the available hardware inside the processor
chip. These are categorized into two types; (a) flag manipulation instructions and (b) machine
control instructions. The flag manipulation instructions directly modify some of the flags of
8086. The machine control instructions control the bus usage and execution. The flag
manipulation instructions and their functions are as follows:
CLC - Clear carry flag
CMC - Complement carry flag
STC - Set carry flag
CLD - Clear direction flag
STD - Set direction flag
CLI - Clear interrupt flag
STI - Set interrupt flag
These instructions modify the carry (CF), direction (DF) and interrupt (IF) flags directly.
The DF and IF, which may be modified using the flag manipulation instructions, further
control the processor operation; like interrupt respondes and autoincrement or
autodecrement modes. Thus the respective instructions may also be called as machine or
processor control instructions. The other flags can be modified using POPF and SAHF
instructions, which are termed as data transfer instructions, in this text. No direct instructions,
are available for modifying the status flags except carry flag.
The machine control instructions supported by 8086 and 8088 are listed as follows
along with their functions. These machine control instructions do not require any operand.
WAIT - Wait for Test input pin to go low
HLT - Halt the processor
NOP - No operation
ESC - Escape to external device like NDP (numeric co-processor)
LOCK - Bus lock instruction prefix.

DMC 1932
After executing the HLT instruction, the processor enters the halt state. The two ways
NOTES to pull it out of the halt state are to reset the processor or to interrupt it. When NOP
instruction is executed, the processor does not perform any operation till 4 clock cycles,
except incrementing the IP by one. It then continues with further execution after 4 clock
cycles. ESC instruction when executed, frees the bus for an external master like a
coprocessor or peripheral devices. The LOCK prefix may appear with another instruction.
When it is executed, the bus access is not allowed for another master till the lock prefixed
instruction is executed completely. This instruction is used in case of programming for
multiprocessor systems. The WAIT instruction when executed, holds the operation of
processor with the current status till the logic level on the TEST pin goes low. The processor
goes on inserting WAIT states in the instruction cycle, till the TEST pin goes low. Once the
TEST pin goes low, it continues further execution.
1.5.3 Assembler Directives And Operators
The main advantage of machine language programming is that the memory control is
directly in the hands of the programmer, so, that, he may be able to manage the memory of
the system more efficiently. On the other hand, the disadvantage are more prominent. The
programming, coding and resource management technique are tedious. The programmer
has to take care of all these functions hence the chances of human errors are more. The
programs are difficult to understand unless one has a thorough technical knowledge of the
processor architecture and instruction set.
The assembly language programming is simpler as compared to the machine language
programming. The instruction mnemonics are directly written in the assembly language
programs. The programs are now more readable to users than the machine language
programs. The main improvement in assembly language over machine language is that the
address values and the constants can be identified by labels. If the labels are suggestive,
then certainly the program will become more understandable, and each time the programmer
will not have to remember the different constants and the addresses at which they are
stored, throughout the programs. The labels may help to identify the addresses and constants.
Due to this facility, the tedious byte handling and manipulations are got rid of. Similarly,
now different logical segments and routines may be assigned with the labels rather than the
different addresses. The memory control feature of machine language programming is left
unchanged by providing storage define facilities in assembly language programming. The
documentation facility which was not possible with machine language programming is now
available in assembly language.
An assembler is a program used to convert an assembly language program into the
equivalent machine code modules which may further be converted to executable codes.
The assembler decides the address of each label and substitutes the values for each of the
constants and variables. It then forms the machine code for the mnemonics and data in the
assembly language program. While doing these things, the assembler may find out syntax

errors. The logical errors or other programming errors are not found out by the assembler.
For completing all these tasks, an assembler needs some hints from the programmer. i.e. NOTES
the required storage for a particular constant or a variable, logical names of the segments,
types of the different routines and modules, end of file, etc. These types of hints are given
to the assembler using some predefined alphabetical strings called assembler directives.
Assembler directives help the assembler to correctly understand the assembly language
programs to prepare the codes.
Another type of hint which helps the assembler to assign a particular constant with a
label or initialise particular memory locations or labels with constants is called an operator.
Rather, the operators perform the arithmetic and logical tasks unlike directives that just
direct the assembler to correctly interpret the program to code it appropriately. The following
directives are commonly used in the assembly language programming practice using Microsoft
Macro Assembler or Turbo Assembler. The directives and operators are discussed here.
DB : Define Byte The DB directive is used to reserve byte or bytes of memory

locations in the available memory. While preparing the EXE file, this directive directs the
assembler to allocate the specified number of memory bytes to the said data type that may
be a constant, variable, string, etc. Another option of this directive also intialises the reserved
memory bytes with the ASCII codes of the characters specified as a string. The following
examples show how the DB directive is used for different purposes.
Example
RANKS DB 01H, 02H, 03H, 04H
This statement directs the assembler to reserve four memory locations for a list named
RANKS and initialise them with the above specified four values.
MESSAGE DB ‘GOOD MORNING
This makes the assembler reserve the number of bytes of memory equal to the number
of characters in the string named MESSAGE and initialise those locations by the ASCII
equivalent of these characters.
VALUE DB 50H
This statement directs the assembler to reserve 50H memory bytes and leave them initialised
for the variable named VALUE.
DW : Define Word The DW directive serves the same purposes as the DB directive, but
it now makes the assembler reserve the number of memory words (16-bit) instead of
bytes. Some examples are given to explain this directive.

DMC 1932
Example
NOTES
WORDS DW 1234H, 4567H, 78ABH, 045CH
This makes the assembler reserve four words in memory (8 bytes), and initialize the
words with the specified values in the statements. During initialisation, the lower bytes are
stored at the lower memory addresses, while the upper bytes are stored at the higher
addresses. Another option of the DW directive is explained with the DUP operator.
WDATA DW 5 DUP (6666H)
This statement reserves five words. i.e. 10-bytes of memory for a word lable WDATA
and initialises all the word locations with 6666H.
DQ : Define Quadword This directive is used to direct the assembler to reserve 4

words (8 bytes) of memory for the specified variable and may initialise it with the specified
values.
DT : Define Ten Bytes The DT directive directs the assembler to define the specified
variable requiring 10-bytes for its storage and initialise the 10-bytes with the specified
values. The directive may be used in case of variables facing heavy numerical calculations,
generally processed by numerical processors.
ASSUME : Assume Logical Segment Name The ASSUME directive is used to inform
the assemble, the names of the logical segments to be assumed for different segments used
in the program. In the assembly language program, each segment is given a name. For
example, the code segment may be given the name CODE, data segment may be given the
name DATA etc. The statement ASSUME CS : CODE directs the assembler that the
machine codes are available in a segment named CODE, and hence the CS register is to
be loaded with the address (segment) allotted by the operating system for the label CODE,
while loading. Similarly, ASSUME DS : DATA indicates to the assembler that the data
items related to the program, are available in a logical segment named DATA, and the DS
register is to be initialized by the segment address value decide by the operating system for
the data segment, while loading. It then considers the segment DATA as a default data
segment for each memory operation, related to the data and the segment CODE as a
source segment for the machine codes of the program. The ASSUME statement is a must
at the starting of each assembly language program, without which a message ‘CODE/
DATA EMITTED WITHOUT SEGMENT” may be issued by an assembler.
END : END of Program The END directive marks the end of an assembly language
program. When the assembler comes across this END directive, it ignores the source lines
available later on. Hence, it should be ensured that the END statement should be the last
statement in the file and should not appear in between. Also, no useful program statement
should lie in the file, after the END statement.

ENDP : END of Procedure In assembly language programming, the subroutines are
called procedures. Thus, procedures may be independent program modules which return NOTES
particular results or values to the calling programs. The ENDP directive is used to indicate
the end of a procedure. A procedure is usually assigned a name, i.e. label. To mark the end
of a particular procedure, the name of the procedure, i.e. label may appear as a prefix with
the directive ENDP. The statements, appearing in the same module but after the NEDP
directive, are neglected from that procedure. The structure given below explains the use of
ENDP.
PROCEDURE STAR
.
.
.
STAR ENDP
ENDS : END of Segment This directive marks the end of a logical segment. The logical
segments are assigned with the names using the ASSUME directive. The names appear
with the ENDS directive as prefixes to mark the end of those particular segments. Whatever
are the contents of the segments, they should appear in the program before ENDS. Any
statement appearing after ENDS will be neglected from the segment. The structure shown
below explains the fact more clearly.
DATA SEGMENT
.
.
.
DATA ENDS
ASSUME CS : CODE, DS : DATA
CODE SEGMENT
.
.
.
CODE ENDS
END
The above structure represents a simple program containing two segments named
DATA and CODE. The data related to the program must lie between the DATA SEGMENT
and DATA ENDS statements. Similarly, all the executable instructions must lie between
CODE SEGMENT and CODE ENDS statements.

DMC 1932
EVEN : Align on Even Memory Address The assembler, while starting the assembling
NOTES procedure of any program, initialises a location and goes on updating it, as the assembly
proceeds. It goes on assigning the available addresses, i.e. the contents of the location
counter, sequentially to the program variables, constants and modules as per their
requirements, in the sequence in which they appear in the program. The EVEN directive
updates the location counter to the next even address, if the current location counter contents
are not even, and assigns the following routine or variable or constant to that address. The
structure given below explains the directive.
EVEN
PROCEDURE ROOT
.
.
.
ROOT ENDP
The above structure shows a procedure ROOT that is to be aligned at an even address.
The assembler will start assembling the main program calling ROOT. When the assembler
comes across the directive EVEN, it checks the contents of the location counter. If it is
odd, it is updated to the next even value and then the ROOT procedure is assigned to that
address, i.e. the updated contents of the location counter. If the content of the location
counter already even, then the ROOT procedure will be assigned with the same address.
EQU : Equate The directive EQU is used to assign a label with a value or a symbol. The
use of this directive is just to reduce the recurrence of the numerical values or constants in
a program code. The recurring value is assigned with a label, and that label is used in place
of that numerical value, throughout the program. While assembling, whenever the assembler
comes across the label, it substitutes the numerical value for that label and finds out the
equivalent code. Using the EQU directive, even an instruction mnemonic can be assigned
with a label, and the label can then be used in the program in place of that mnemonic.
Suppose, a numerical constant appears in a program ten times. If that constant is to be
changed at a later time, one will have to make all these ten corrections. This may lead to
human errors, because it is possible that a human programmer may miss one of those
corrections. This will result in the generation of wrong codes. If the EQU directive is used
to assign the value with a label that can be used in place of each recurrence of that constant,
only one change in the EQU statement will give the correct and modified code. The examples
given below show the syntax.
Example
LABEL EQU 0550H
ADDITION EQU ADD

The first statement assigns the constant 500H with the label LABEL, while the second
statement assigns another label ADDITION with mnemonic ADD. NOTES
EXTRN : External and PUBLIC : Public The directive EXTRN informs the assembler
that the names, procedures and labels declared after this directive have already been defined
in some other assembly language modules. While in the other module, where the names,
procedures and labels actually appear, they must be declared public, using the PUBLIC
directive. If one wants to call a procedure FACTORIAL appearing in MODULE1 from
MODULE2; in MODULE1, it must be declared PUBLIC using the statement PUBLIC
FACTORIAL and in module 2, it must be declared external using the declaration EXTRN
FACTORIAL. The statement of declaration EXTRN must be accompanied by the
SEGMENT and ENDS directives of the MODULE 1, before it is called in MODULE 2.
Thus the MODULE 1 and MODULE 2 must have the following declarations.
MODULE 1 SEGMENT
PUBLIC FACTORIAL FAR
MODULE 1 ENDS
MODULE 2 SEGMENT
EXTRN FACTORIAL FAR
MODULE 2 ENDS
GROUP : Group the Related Segments The directive is used to form logical groups
of segments with similar purpose of type. This directive is used to inform the assembler to
form a logical group of the following segment names. The assembler passes an information
to the linker/loader to form the code such that the group declared segments or operands
must lie within a 64Kbyte memory segment. Thus all such segments and labels can be
addressed using the same segment base.
PROGRAM GROUP CODE, DATA, STACK
The above statement directs the loader/linker to prepare an EXE file such that CODE,
DATA and STACK segment must lie within a 64Kbyte memory segment that is named as
PROGRAM. Now, for the ASSUME statement, one can use the label PROGRAM rather
than CODE, DATA and STACK as shown.
ASSUME CS : PROGRAM, DS : PROGAM, SS : PROGRAM.
LABEL : Label The Label directive is used to assign a name to the current content of
the location counter. At the start of the assembly process, the assembler initialises a location
counter to keep track of memory locations assigned to the program. As the program
assembly proceeds, the contents of the location are updated. During the assembly process,
whenever the assembler comes across the LABEL directive, it assigns the declared label
with the current contents of the location counter. The type of the label must be specified,
i.e. whether it is a NEAR or a FAR label, BYTE or WORD label, etc.
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A LABEL directive may be used to make a FAR jump as shown below. A FAR jump
NOTES cannot be made at a normal label with a colon. The label CONTINUE can be used for a
FAR jump, if the program contains the following statement.
CONTINUE LABEL FAR
The LABEL directive can be used to refer to the data segment along with the data
type, byte or word as shown.
DATA SEGMENT
DATAS DB 50H DUP (?)
DATA-LAST LABEL BYTE FAR
DATA ENDS
After reserving 50H locations for DATAS, the next location will be assigned a label DATA-
LAST and its type will be byte and far.
LENGTH : Byte Length of a Label This directive is not available in MASM. This is
used to refer to the length of a data array or a string.
MOV CX, LENGTH ARRAY
This statement, when assembled, will substitute the length of the array ARRAY in bytes, in
the instruction.
LOCAL The labels, variables, constants or procedures declared LOCAL in a module

are to be used only by that module. At a later time, some other module may declare a
particular data type LOCAL, which is previously declared LOCAL by an other module or
modules. Thus the same label may serve different purposes for different modules of a
program. With a single declaration statement, a number of variables can be declared local,
as shown.
LOCAL a, b, DATA, ARRAY, ROUTINE
NAME : Logical Name of a Module The NAME directive is used to assign a name to
an assembly language program module. The module, may now be referred to by its declared
name. The names, if selected to be suggestive, may point out the functions of the different
modules and hence may help in the documentations.
OFFSET : Offset of a Label When the assembler comes across the OFFSET operator
along with a label, it first computes the 16-bit displacement (also called as offset
interchangeably) of the particular label, and replaces the string ‘OFFSET LABEL’ by the
computed displacement. This operator is used with arrays, strings, labels, and procedures
to decide their offsets on their default segments. The segment may also be decided by
another operator of similar type, viz, SEG. Its most common use is in the case of the

indirect, indexed, based indexed or other addressing techniques of similar types, used to
refer to the memory indirectly. The examples of this operator are as follows: NOTES
Example
CODE SEGMENT
MOV SI, OFFSET LIST
CODE ENDS
DATA SEGMENT
LIST DB 10H
DATA ENDS
ORG : Origin The ORG directive directs the assembler to start the memory allotment
for the particular segment, block or code from the declared address in the ORG statement.
While starting the assembly process for a module, the assembler initialises a location counter
to keep track of the allotted addresses for the module. If the ORG statement is not written
in the program, the location counter is initialised to 0000. If an ORG 200H statement is
present at the starting of the code segment of that module, then the code will start from
200H address in code segment. In other words, the location counter will get initialised to
the address 0200H instead of 0000H. Thus, the code for different modules and segments
can be located in the available memory as required by the programmer. The ORG directive
can even be used with data segments similarly.
PROC : Procedure The PROC directive marks the starts of a named procedure in the
statement. Also, the types NEAR or FAR specify the type of the procedure, i.e whether it
is to be called by the main program located within 64K of physical memory or not. For
example, the statement RESULT PROC NEAR marks the start of a routine RESULT,
which is to be called by a program located in the same segment of memory. The FAR
directive is used for the procedures to be called by the programs located in different
segments of memory. The example statements are as follows:
Example
RESULT PROC NEAR
ROUTINE PROC FAR
PTR : Pointer The pointer operator is used to declare the type of a label, variable or
memory operand. The operator PTR is prefixed by either BYTE or WORD. If the prefix
is BYTE, then the particular label, variable or memory operand is treated as an 8-bit
quantity, while of WORD is the prefix, then it is treated as a 16-bit quantity. In other
words, the PTR operator is used to specify the data type - byte or word. The examples of
the PTR operator are as follows:

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Example
NOTES MOV AL, BYTE PTR [SI] - Moves content of memory location
addressed by SI (8-bit) to AL
INC BYTE PTR [BX] - Increments byte contents of memory
location addressed by BX
MOV BX, WORD PTR [2000H] - Moves 16-bit content of memory
location 2000H to BX, i.e. [2000H] to BL
[2001H] to BH
INC WORD PTR [3000H] - Increments word contents of memory
location 3000H considering contents
of 3000H (lower byte) and 3001H
(higher byte) as a 16-bit number
In case of JMP instructions, the PTR operator is used to specify the type of the jump,
i.e. near or far, as explained in the examples given below.
JMP WORD PTR [BX] - NEAR Jump
JMP WORD PTR [BX] - FAR Jump
PUBLIC As already discussed, the PUBLIC directive is used along with the EXTRN
directive. This informs the assembler that the labels, variables, constants, or procedures
declared PUBLIC may be accessed by other assembly modules to form their codes, but
while using the PUBLIC declared labels, variables, constants or procedures the user must
declare them externals using the EXTRN directive. On the other hand, the data types
declared EXTRN in a module of the program, may be declared PUBLIC in at least any
one of the other modules of the same program. (Refer to the explanation on EXTRN
directive to get the clear idea of PUBLIC.)
SEG : Segment of a Label The SEG operator is used to decide the segment address of
the label, variable, or procedure and substitutes the segment base address in place of
‘SEG label’. The example given below explain the use of SEG operator.
Example
MOV AX, SEG ARRAY ; This statement moves the segment address of
MOV DS, AX ; ARRAY in which it is appearing, to register
AX and then to DS.
SEGMENT : Logical Segment The SEGMENT directive marks the starting of a

logical segment. The started segment is also assigned a name, i.e. label, by this statement.
The SEGMENT and ENDS directive must bracket each logical segment of a program. In
some cases, the segment may be assigned a type like PUBLIC (i.e. can be used by other

modules of the program while linking) or GLOBAL (can be accessed by any other
modules). The program structure given below explains the use of the SEGMENT directive. NOTES
EXE. CODE SEGMENT GLOBAL ;Start of segment named EXE.CODE,
; that can be accessed by any other module.
EXE. CODE ENDS ; END of EXE.CODE logical segment.
SHORT The SHORT operator indicates to the assembler that only one byte is required
to code the displacement for a jump (i.e. displacement is within -128 to +127 bytes from
the address of the byte next to the jump opcode). This method of specifying the jump
address saves the memory. Otherwise, the assembler may reserve two bytes for the
displacement. The syntax of the statement is as given below.
JMP SHORT LABEL
TYPE The TYPE operator directs the assembler to decide the data type of the specified
label and replaces the ‘TYPE label’ by the decided data type. For the word type variable,
the data type is 2, for double word type, it is 4, and for byte type, it is 1. Suppose, the
STRING is a word array. The instruction MOV AX, TYPE STRING moves the value
0002H in AX.
GLOBEL The labels, variables, constants or procedures declared GLOBAL may be

used by other modules of the program. Once a variable is declared GLOBAL, it can be
used by any module in the program. The following statement declares the procedure
ROUTINE as a global label.
ROUTINE PROC GLOBAL
Have you Understand Questions?

Q1.5.a How is intersegment indirect addressing mode calculated?
Q1.5.b Give the differences between instruction set and directives of 8086.
Q1.5.c Discuss about the string manipulation instructions.
Q1.5.d Discuss about the value returning attributes.
Q.1.5.e Describe each assembler directive and operator, with an example.
1.6 Assembly Language Example Programs
In the previous section, we studied the complete instruction set of 8086/88 and the
assembler directives. In this section, we will study some programs which elucidate the use
of instructions, directives and some other facilities that are available in assembly language
programming. If one writes an assembly language program and tries to code it, in the first
attempt, the chances are rare that there is no error. Rather, errors in programming depend
upon the skill of the Programmer. A lot of practice is needed to obtain skills in assembly

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language programming as compared to high level languages. So, to obtain a command on

NOTES assembly language one should write and execute a number of assembly programs, besides
studying the example programs given in this text.
Before starting the explanation of the written programs, we have to explain one more
important point, that is about the DOS function calls available under INT 21H instruction.
DOS is an operating system, which is a program that stands between a bare computer
system hardware and a user. It acts as a user interface with the available computer hardware
resources. It also manages the hardware resources of the computer system. In the Disk
Operating System, the hardware resources of the computer system like memory, keyboard,
CRT display, hard disk, and floppy disk drives can be handled with the help of the instruction
INT 21H.
The routines required to refer to these resources are written as interrupt service routines
for 21H interrupt. Under this interrupt, the specific resource is selected depending upon
the value in AH register. For example, if AH contains 09H, then CRT display is to be used
for displaying a message or it, AH contain 0AH, then the keyboard is to be accessed.
These interrupts are called ‘function calls’ and the value in AH is called ‘function value’. In
short, the purpose of ‘function calls’ under INT 21 H is to be decided by the ‘function
value’ that is in AH. Some function values also control the software operations of the
machine. Note that there are a number of interrupt functions in DOS, but INT 21H is used
more frequently. The readers may find other interrupts of DOS and BIOS from the respective
technical references.
In this section, a few example programs are presented.
Program 1.6.1 Write a program for addition of two numbers.
Solution The following program adds two 16-bit operands. There are various methods
of specifying operands depending upon the addressing modes that the programmer wants
to use. Accordingly, there may be different program listing to achieve a single programming
goal. A skilled programmer uses a simple logic and implements it by using a minimum
number of instructions. Let us now try to explain the following program.
ASSUME CS : CODE, DS : DATA
DATA SEGMENT
OPR1 DW 1234H ; 1st operand
OPR 2 DW 0002H ; 2nd operand
RESULT DW 01 DUP(?); A word of memory reserved for result
DATA ENDS
CODE SEGMENT

START: MOV AX, DATA ; Initialize data segment
MOV DS, AX ;
NOTES
MOV AX, OPR1 ; Take 1st operand in AX.
MOV BX, OPR2 ; Take 2nd operand in BX.
CLC ; Clear previous carry if any.
ADD AX, BX ; Add BX to AX.
MOV DI, OFFSET RESULT ; Take offset of RESULT in DI.
MOV [DI], AX ; Store the result at memory address in DI.
MOV AH, 4CH ; Return to DOS prompt.
INT 21H
CODE ENDS ; CODE segment ends.
END START ; Program ends
Program 1.6.1 Listings
How to Write an Assembly Language Program
The first step in writing an assembly language program is to define and study the
problem. After studying the problem, decide the logical modules required for the program.
From the statement of the program one may guess that some data may be required for the
program or the result of the program that is to be stored in memory. Hence the program
will need a logical space called DATA segment. Invariably CODE segment is a part of a
program containing the actual instruction sequence to be executed. If the stack facility is to
be used in the program, it will require the STACK segment. The EXTRA segment may be
used as an additional destination data segment. Note that the use of all these logical segments
is not compulsory except for the CODE segment. Some programs may require DATA and
CODE segments, while the others may also contain STACK and EXTRA. For example,
Program 1.6.1 requires only DATA and CODE segment.
The first line of the program containing ‘ASSUME’ directive declares that the label
CODE is to be used as a logical name for CODE segment and the label DATA is to be
used for DATA segment. These labels CODE and DATA are reserved by MASM for
these purposes only. They should not be used as general labels. Once this statement is
written in the program, CODE refers to the code segment and DATA refers to data segment
throughout the program. If you want to change it in a program you will have to write
another ASSUME statement in the program.
The second statement DATA SEGMENT marks the starting of a logical data space
DATA. Inside DATA segment, OPR1 is the first operand. The directive DW defines OPR1
as a word operand of value 1234H and OPR2 as a word operand of value 0002H. The

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third DW directive reserves 01H words of memory for storing the result of the program
NOTES and leaves it undefined due to the directive DUP(?). The statement DATA ENDS marks
the end of the DATA segment. Thus the logical space DATA contains OPR1, OPR2 and
RESULT. These labels OPR1, OPR2 and RESULT will be allotted physical memory
locations whenever the logical SEGMENT DATA is allocated memory or loaded in the
memory of a computer as explained in the previous topic of relocation. The assembler
calculates that the above data segment requires 6 bytes, i.e 2 bytes each for OPR1, OPR2
and RESULT.
The code segment in the above program starts with the statement CODE SEGMENT.
The code segment as already explained is a logical segment space containing the instructions.
The label STARTS marks the starting point of the execution sequence. The ASSUME
statement just informs the assembler that label CODE is used for the code segment and the
label DATA is used for the DATA segment. It does not actually put the address corresponding
to CODE in code segment register (CS) and address corresponding to DATA in the data
segment register (DS). This procedure of putting the actual segment address values into
the corresponding segment registers is called as segment register initialisation. A programmer
has to carry out these initializations for DS, SS and ES using instructions, while the CS is
automatically initialised by the loader at the time of loading the EXE file into the memory
for actual execution. The first two instructions in the program are for data segment
initialization. Note that, no segment register in 8086 can be loaded with immediate segment
address value, instead the address value should be first loaded into any one of the general
purpose registers and then the contents of the general purpose register can be transferred
to any of the segment registers DS, ES and SS. Also one should note that CS cannot be
loaded at all. Its contents can be changed by using a long jump instruction, a call instruction
or an interrupt instruction.
For each of the segments DS, ES and SS, the programmer will have to carry out
initialization if they are used in the program, while CS is automatically initialized by the
loader program at the time of loading and execution. Then the two instructions move the
two operands OPR1 and OPR2 in AX and BX respectively. Carry is cleared before
addition operation (optional in this program). The ADD instruction will add BX into AX
and store the result in AX. The instruction used to store the result in RESULT uses different
addressing mode than the used for taking OPR1 into AX. The indexed addressing mode is
used to store the result of addition in memory locations labeled RESULT. The instruction
MOV DI, OFFSET RESULT stores the offset of the label RESULT into DI register. Next
instruction stores the result available in AX into the address pointed to by DI, i.e address
of the RESULT. A lot has been already discussed about the function calls under INT 21H.
The function value 4CH is for returning to the DOS prompt. If instead of these one writes
HLT instruction there will not be any difference in program execution except that the computer
will hang as the processor goes to HLT state, and the user will not be able to examine the

result. In that case, for further operation, one will have to reset the computer and boot it
again. To avoid this resetting of the computer every time you run the program and enable NOTES
one to check the result, it is better to use the function call 4CH at the end of each program
so that after executing the program, the computer returns back to DOS prompt. The
statement CODE ENDS marks the end of the CODE segment. The statement END START
marks the end of the procedure that started with the label START. At the end of each file,
the END statement is a must.
Until now we have discussed every line of Program 1.6.1 in significant details. As we
have already said, the program contains two logical segments CODE and DATA, but it is
not at all necessary that all the programs must contain the two segments. A programmer
may use a single segment to cover up data as well as instructions. The following listings
explain the fact.
ASSUME CS : CODE
CODE SEGMENT
OPR1 DW 1234H
OPR2 DW 0002H
RESULT DW 01 DUP(?)
START : MOV AX, CODE
MOV DS, AX
MOV AX, OPR1
MOV BX, OPR2
CLC
ADD AX, BX
MOV DI, OFFSET RESULT
MOV [DI] , AX
MOV AH, 4CH
INT 21H
CODE ENDS
END START
Program 1.6.1 Alternative listing for program 1.6.1
For this program, we have discussed all clauses and clones in details. For all the
following programs, we will not explain the common things like forming segments using
directives and operators, etc. Instead, just the logic of the program will be explained. The
use of proper syntax of the 8086/8088 assembler MASM is self explanatory. The comments
may help the reader in getting the ideas regarding the logic of the program.

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Program 1.6.2 Write a program for the addition of a series of 8-bit numbers. The series
NOTES contains 100 (numbers)
Solution In the first program, we have implemented the addition of two numbers. In this
program, we show the addition of 100 (D) numbers. Initially, the resulting sum of the first
two numbers will be stored. To this sum, the third number will be added. This procedure
will be repeated till all the numbers in the series are added. A conditional jump instruction
will be used to implement the counter checking logic. The comments explain the purpose
of each instruction.
ASSUME CS: CODE, DS : DATA
DATA SEGMENT ; Data segment starts
NUMLIST DB 52H, 23H, ; List of byte numbers
COUNT EQU 100D ; Number of bytes to be added
RESULT DW 01H DUP(?) ; One word is reserved for result.
DATA ENDS ; Data segment ends
CODE SEGMENT ; Code segment starts at relative
ORG 200H ; address 0200H in code segment.
START : MOV AX, DATA ; Initialize data segment.
MOV DS, AX
MOV CX, COUNT ; Number of bytes to be added in CX.
XOR AX, AX ; Clear AX and CF.
XOR BX, BX ; Clear BH for converting the byte to word
MOV SI, OFFSET NUMLIST ; Point to the first number in the list.
AGAIN : MOV BL, [SI] ; Take the first number in BL, BH is zero
ADD AX, BX ; Add AX with BX.
INC SI ; Increment pointer to the byte list.
DEC CX ; Decrement counter.
JNZ AGAIN ; If all numbers are added, point to result.
MOV DI, OFFSET RESULT ; destination and store it.
MOV [DI], AX
MOV AH, 4CH ; Return to DOS.
INT 21H
CODE ENDS
AND START

Program 1.6.2 Listing
NOTES
The use of statement ORG 200H in this program is not compulsory. We have used
this statement here just to explain the way to use it. It will not affect the result at all.
Whenever the program is loaded into the memory whatever is the address assigned for
CODE, the executable code starts at the offset address 0200H due to the above statement.
Similar to DW, the directive DB reserves space for the list of 8-bit numbers in the series.
The procedure for entering the program, coding and execution has already been explained.
The result of addition will be stored in the memory locations allotted to the label RESULT.
Program 1.6.3 A program to find out the largest number from a given unordered array of
8-bit numbers, stored in the locations starting from a known address.
Solution Compare the ith number of the series with the (i+1)th number using CMP
instruction. It will set the flags appropriately, depending upon whether the ith number or the
(i+1)th number is greater. If the ith number is greater than (i+1), leave it in AX (any register
may be used). Otherwise, load the (i+1)th number in AX, replacing the ith number in AX.
The procedure is repeated till all the members in the array have been compared.
ASSUME CS: CODE, DS : DATA
DATA SEGMENT ; Data segment starts
LIST DB 52H, 23H, 56H, 45H, ; List of byte numbers
COUNT EQU 0F ; Number of bytes in the list
LARGEST DB 01H DUP(?) ; One byte is reserved for the largest number.
DATA ENDS ; Data segment ends
CODE SEGMENT ; Code segment starts.
START : MOV AX, DATA ; Initialize data segment.
MOV DS, AX
MOV SI, OFFSET LIST
MOV CL, COUNT ; Number of bytes in CL.
MOV AL, [SI] ; Take the first number in AL.
AGAIN: CMP AL, [SI+1] ; and compare it with the next number.
JNL NEXT
MOV AL, [SI]
NEXT: INC SI ; Increment pointer to the byte list.
DEC CL ; Decrement counter.
JNZ AGAIN ; If all numbers are compared, point to result.
MOV SI, OFFSET LARGEST; destination and store it.
MOV [SI], AL
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MOV AH, 4CH ; Return to DOS.

NOTES INT 21H
CODE ENDS
END START
Program 1.6.4 Modify the Program 1.6.3 for a series of words.
Solution The logic is similar to the previous program written for a series of byte numbers.
The program is directly written as follows without any comment leaving it to the reader to
find out the use of each instruction and directive used.
ASSUME CS : CODE , DS : DATA
DATA SEGMENT
LIST DW 1234H, 2354H, 0056H, 045AH,
COUNT EQU 0F
LARGEST DW 01H DUP (?)
DATA ENDS
CODE SEGMENT
START : MOV AX, CODE
MOV DS, AX
MOV SI, OFFSET LIST
MOV CL, COUNT
MOV AX, [SI]
AGAIN: CMP AX, [SI+2]
JNL NEXT
MOV AX, [SI+2]
NEXT: INC SI
INC SI
DEC CL
JNZ AGAIN
MOV SI, OFFSET LARGEST
MOV [SI], AX
MOV AH, 4CH
INT 21H
CODE ENDS
END START

NOTES
Program 1.6.5 A program to find out the number of even and odd numbers from a given
series of 16-bit hexadecimal numbers.
Solution The simplest logic to decide whether a binary number is even or odd, is to check
the least significant bit of the number. If the bit is zero, the number is even, otherwise it is
odd. Check the LSB by rotating the number through carry flag, and increment even or odd
number counter.
DATA SEGMENT
LIST DW 2357H, 0A579H, 0C322H, 0C91EH, 0C000H, 0957H
COUNT EQU 006H
DATA ENDS
CODE SEGMENT
START : XOR BX, BX
XOR DX, DX
MOV AX, DATA
MOV DS, AX
MOV CL, COUNT
MOV SI, OFFSET LIST
AGAIN: MOV AX, [SI]
ROR AX, 01
JC ODD
INC BX
JMP NEXT
ODD: INC DX
NEXT: ADD SI, 02
DEC CL
JNZ AGAIN
MOV AH, 4CH
INT 21H
CODE ENDS
END START

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NOTES
Program 1.6.6 Write a program to find out the number of positive numbers and negative
numbers from a given series of signed numbers.
Solution Take the ith number in any of the registers. Rotate it left through carry. The status
of carry flag, i.e. the most significant bit of the number will give the information about the
sign of the number. If CF is 1, the number is negative; otherwise, it is positive.
DATA SEGMENT
LIST DW 2579H, 0A500H, 0C009H, 0159H, 0B900H
COUNT EQU 05H
DATA ENDS
CODE SEGMENT
START : XOR BX, BX
XOR DX, DX
MOV AX, DATA
MOV DS, AX
MOV CL, COUNT
MOV SI, OFFSET LIST
AGAIN: MOV AX, [SI]
SHL AX, 01
JC NEG
INC BX
JMP NEXT
NEG: INC DX
NEXT: ADD SI, 02
DEC CL
JNZ AGAIN
MOV AH, 4CH
INT 21H
CODE ENDS
END START

NOTES
The logic of Program 1.6.6 is similar to that of Program 1.6.5, hence comments are
not given in Program 1.6.6 except for a few important ones.
Program 1.6.7 Write a program to move a string of data words from offset 2000H offset
3000H the length of the string is 0FH.
Solution To write this program, we will use an important facility, available in the 8086
instruction set, i.e. move string byte/word instruction. We will also study the flexibility
imparted by this instructions to the 8086 assembly language program. Let us first write the
Program 3.7 for 8085, assuming that the string is available at location 2000H and is to be
moved at 3000H.
LXI I, 2000H
LXI D, 3000H
MVI C, 0FH
AGAIN: MOV A, M
STAX D
INX H
INX D
DCR C
JNZ AGAIN
HLT
An 8085 Program for Program 1.6.7
Now assuming DS is suitably set, let us write the sequence for 8086. At first using the
index registers, the program can be written as given.
MOV SI, 2000H
MOV DI, 3000H
MOV CX, 0FH
AGAIN: MOV AX [SI]
MOV [DI], AX
INC SI
INC DI
DEC CX
JNZ AGAIN
HLT
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An 8086 Program for Program 1.6.7

NOTES
Comparing the above listing for 8085 and 8086 we may infer that every instruction in
8085 listing is replaced by an equivalent instruction of 8086. The above 8086 listing is
absolutely correct but it is not efficient. Let us try to write the listings for the same purpose
using the string instruction. Due to the assembler directives and the syntax, one may feel
that the program is lengthy, though it eliminates four instructions for a MOVSW instruction.
DATA SEGMENT
SOURCESTRT EQU 2000H
DESTSTRT EQU 3000H
COUNT EQU 0FH
DATA ENDS
CODE SEGMENT
START : MOV AX, DATA
MOV DS, AX
MOV ES, AX
MOV SI, SOURCESTRT
MOV DI, DESTSTRT
MOV CD, COUNT
CLD
REP MOVSW
MOV AH, 4CH
INT 21H
CODE ENDS
END START
Program 1.6.7
An 8086 Program listing for Program 1.6.7 using String instruction.
Compare the above two 8086 listings. Both contain ten instructions. However, in
case of the second program, the instruction for the initialisation of segment register and
DOS interrupt are additional while the first one neither contains initialisation of any segment
registers nor does it contain the DOS interrupt instruction. We can say that the first program
uses 9 instructions, while the second one uses only 5 for implementing the same algorithm.

This program and the related discussions are aimed at explaining the importance of
the string instructions and the method to use them. NOTES
Program 1.6.8 Write an assembly language program to arrange a given series of
hexadecimal bytes in ascending order.
Solution There exist a large number of sorting algorithms. The algorithm used here is
called bubble sorting. The method of sorting is explained as follows. To start with, the first
number of the series is compared with the second one. If the first number is greater than
second, exchange their positions in the series otherwise leave the positions unchanged.
Then, compare the second number in the recent form of the series with third and repeat the
exchange part that you have carried out for the first and the second number, and for all the
remaining numbers of the series. Repeat this procedure for the complete series (n-1) times.
After (n-1) iterations, you will get the largest number at the end of the series, where n is the
length of the series. Again start from the first address of the series. Repeat the same procedure
right from the first element to the last element. After (n-2) iterations you will get the second
highest number at the last but one place in the series. Continue this till the complete series
is arranged in ascending order. Let the series be as given :
53, 25, 19, 02 n=4
25, 53, 19, 02 1st operation
25, 19, 53, 02 2nd operation
25, 19, 02, 53 3rd operation
largest no.  4 - 1 = 3 operations
19, 25, 02, 53 1st operation
19, 02, 25, 53 2nd operation
2nd largest no.  4 - 2 = 2 operations
02, 19, 25, 53 1st operation
3rd largest no.  4 - 3 = 1 operations
Instead of taking a variable count for the external loop in the program like (n-1), (n-2), (n-
3).......,etc. It is better to take the count (n-1) all the time for simplicity. The resulting
program is given as shown.

DMC 1932

NOTES DATA SEGMENT
LIST DW 53H, 25H, 19H, 02H
COUNT EQU 04
DATA ENDS
CODE SEGMENT
MOV DS, AX
MOV DX, COUNT-1
AGAIN0: MOV CX, DX
MOV SI, OFFSET LIST
AGAIN1: MOV AX, [SI]
CMP AX, [SI+2]
JL PR1
XCHG [SI+2], AX
XCHG [SI], AX
PR1: ADD SI, 01
LOOP AGAIN 1
DEC DX
JNZ AGAIN0
MOV AH, 4CH
INT 21H
CODE ENDS
END START
With a similar approach, the reader may write a program to arrange the string in
descending order. Just instead of the JL instruction in the above program, one will have to
use a JG instruction.
Program 1.6.9 Write a program to perform a one byte BCD addition.
Solution It is assumed that the operands are in BCD form, but the CPU considers it
hexadecimal and accordingly performs addition. Consider the following example for
addition. Carry is set to be zero.

9 2 NOTES
+ 5 9
E B Actual result after addition considering hex. operands
1 0 1 1
+ 0 1 1 0 AS 0BH (LSD of addition) > 09, add 06 to it.
10 0 0 1 Least significant nibble of result (neglect the auxiliary carry)
 AF is set to 1
0110 is added to most significant nibble of the result if it is greater than 9 or AF is set.
1 Carry from previous digit (AF)

E  1 1 1 0
+ 0 1 1 0
CF is set to 1 0 1 0 1 next significant nibble of result
Result CF Most significant Least significant digit

1 5 1

DATA SEGMENT
OPR 1 EQU 92H
OPR 2 EQU 52H
RESULT DB 02 DUP (00)
DATA ENDS
CODE SEGMENT
MOV DS, AX
MOV BL, OPR1
XOR AL, AL
MOV AL, OPR2
ADD AL, BL
DAA

DMC 1932
MOV RESULT, AL
NOTES JNC MSB0
INC [RESULT +1]
MSB0: MOV AH, 4CH
INT 21H
CODE ENDS
END START
In this program, the instruction DAA is used after ADD. Similarly, DAS can be used
after SUB instruction. The reader may try to write a program for BCD subtraction for
practice.
Program 1.6.10 Write a program that performs addition, subtraction, multiplication and
division of the given operands. Perform BCD operation for addition and subtraction.
Solution Here we have directly given the routine for Program 1.6.10.
DATA SEGMENT
OPR 1 EQU 98H
OPR 2 EQU 49H
SUM DW 01 DUP (00)
SUBT DW 01 DUP (00)
PROD DW 01 DUP (00)
DIVS DW 01 DUP (00)
DATA ENDS
CODE SEGMENT
MOV DS, AX
MOV BL, OPR2
XOR AL, AL
MOV AL, OPR1
ADD AL, BL
DAA
MOV BYTE PTR SUM, AL

JNC MSB0
INC [SUM+1]
NOTES
MSB0: XOR AL, AL
MOV AL, OPR1
SUB AL, BL
DAS
MOV BYTE PTR SUBT, AL
JNB MSB1
INC [SBT+1]
MSB1: XOR AL, AL
MOV AL, OPR1
MUL BL
MOV WORD PTR PROD, AX
XOR AH, AH
MOV AL, OPR1
DIV BL
MOV WORD PTR DIVS, AX
MOV AH, 4CH
INT 21H
CODE ENDS
END START
1.7 INTERRUPTS AND INTERRUPT ROUTINES
It is sometimes necessary to have the computer automatically execute one of a

collection of special routines whenever certain conditions exist within a program or the
computer system. The action that prompts the execution of one of these routines is called
an interrupt and the routine that is executed is called an interrupt routine. There are two
general classes of interrupts and associated routines. There are the internal interrupts that
are initiated by the state of the CPU or by an instruction, and the external interrupts that are
caused by a signal being sent to the CPU from elsewhere in the computer system. Typical
internal interrupts are those caused by a division by zero or a special instruction and typical
external interrupts are caused by the need of an I/O device to be-serviced by the CPU.

DMC 1932
An interrupt routine is similar to a procedure in that it may be branched to from any other
NOTES program and a return branch is made to that program after the interrupt routine has executed.
The interrupt routine must be written so that, except for the lapse in time, the interrupted
program will proceed just as if nothing had happened. This means that the PSW and the
registers used by the routine must be saved and restored and the return must be made to
the instruction following the last instruction executed before the interrupt. An interrupt
routine is unlike a procedure in that, instead of being linked to a particular program, it is
sometimes put in a fixed place (absolutely located) in memory. Because it is not linked to
other segments, it can use only common areas that are absolutely located to communicate
with other programs. Because some kinds of interrupts are initiated by external events,
they occur at random points in the interrupted program. For such interrupts, no parameters
or parameter addresses can be passed to the interrupt routine, Instead, data communication
must be made through variables that are directly accessible by both routines.
00000
8086 New (IP) 4*N Interrupt

pointer for
New (CS) 4*N+2 TYPE = N
IP
CS
~
~ ~
~
PSW
(SS)
Old (IP) New top of stack

Old (CS)
Old (PSW)
Figure1.7.1 Use of a stack to dynamically provide storage during recursive calls
Regardless of the type of interrupt, the actions that result from an interrupt are the
same and are known as the interrupt sequence. The interrupt sequence for the 8086 is
shown in Figure1.7.1 . Some kinds of interrupts are controlled by the IF and TF flags and
in those cases these flags must be properly set or the interrupt action is blocked. If the
conditions for an interrupt are met and the necessary flags are set, the instruction that is
currently executing is completed and the interrupt sequence proceeds by pushing the current
contents of the PSW, CS, and IP onto the stack, inputting the new contents of IP and CS
from a double word whose address is determined by the type of interrupt, and Clearing
the IF and TF flags. The new contents of the IP and CS determine the beginning address

of the interrupt routine to be executed. After the interrupt has been executed the return is
made to the interrupted program by an instruction that pops the IP, CS, and PSW from the NOTES
stack.
The double word containing the new contents of IP and CS is called an interrupt
pointer (or vector). Each interrupt type is given a number between 0 and 255, inclusive,
and the address of the interrupt pointer is found by multiplying the type by 4. If the type is
9, then the interrupt pointer will be in bytes 00024 through 00027. Since it takes 4 bytes to
store a double word, the interrupt pointers may occupy the first 1024 bytes of memory
and these bytes should never be used for other purposes. Some of the 256 interrupt types
may be reserved by the operating system and may be initialized when the computer system
is first brought up Users may tailor the other interrupt types according to their particular
applications.
The kinds of interrupts and their designated types are summarized in Figure1.7.2 by
illustrating the layout of their pointers within memory. Only the first five types have explicit
definitions; the other types may be used by interrupt instructions or external interrupts.
From the figure it is seen that the type associated with a division error interrupt is 0.
Therefore, if a division by 0 is attempted. the computer will push the Current contents of
the PSW, CS and IP onto the stack fill the IP and CS registers from addresses 00000 and
00002 and continue executing at the address indicated by the new contents of IP and CS.
A division error interrupt occurs any time a DIV or IDIV instruction is executed with the
quotient exceeding the range regardless of the IF and TF settings.
The type 1 interrupt is the single-step trap and is the only interrupt controlled by the
TF flag. If the TF flag is enabled an interrupt will occur at the end of the next instruction that
will cause a branch to the location indicated by the contents of 00004 through 00007.
Because the TF flag is cleared by the interrupt sequence, interrupts will not occur after the
instructions in the interrupt routine, but because the original PSW (including the enabled
TF flag) is restored by the return, an interrupt will occur immediately after the instruction
following the return. Therefore, an interrupt will take place after each instruction in the
interrupted program as long as the TF flag is set. The single-step trap is used primarily for
debugging by having the interrupt routine print out the contents of the pertinent registers
and memory locations after the execution of each instruction. This gives the programmer a
snapshot of this program after each instruction is executed.
The TF flag can be enabled by pushing the PSW onto the stack, ORing the top of the
stack with 0100, and then popping the stack. It can be disabled by similarly ANDing the
PSW with FEFF.

DMC 1932
The type 2 interrupt is the non-maskable external interrupt. It is the only external
NOTES interrupt that can occur regardless of the IF flag setting. The instruction IRET is used to
return from an interrupt routine.
Contents Address
Pointer New (IP) for type 0 00000
for Reserved for divide error
type 0 New (CS) for type 0
Pointer New (IP) for type 1 00004

for Reserved for single step
trap - TF must be set
Pointer 00008
for Reserved for nonmaskab
type 2
interrupt
Pointer 0000C
for Reserved for one-byte
type 3
interrupt instruction, IN
Pointer 00010
for
type 4
INTO instruction
Pointer 00014
for
type 5
Pointer 00018
for
type 6
0001C
Pointer New (IP) for type N 4*N

for
type N New (CS) for type N
4*N + 4
Pointer New (IP) for type 255 003FC

for
00400
Figure 1.7.2 Layout of Interrupt Pointers

Q1.6.a Discuss about the BIU and EU in the 8086 architecture?
Q1.6.b What are the various types of registers present in 8086?
Q1.6c What are the advantages of segmentation in 8086?
Q1.6d Give the difference between the control flag and conditional flag?

Summary
 We have presented the internal architecture of 8086.
NOTES
 The functional details of the architecture like, register set, flags and segment memory
organization are also discussed in significant details.
 Further the addressing modes available in 8086 are discussed in significant details
with necessary examples.
 Aimed at introducing the readers with the instruction set of 8086 and the most
commonly used assembler directives and operators.
 To start with, the available instruction set is explained in detail.
 With an overview of assembler operation, we have initiated the discussion of
assembly language programming.
 The interrupt and interrupt routines are also discussed in detail.
Exercises
1.1 Draw and discuss the internal block diagram of 8086.
1.2 What do you mean by pipelined architecture? How is it implemented in 8086?
1.3 Explain the concept of segmented memory? What are its advantages?
1.4 Explain the physical address formation in 8086.
1.5 Draw the register organisation of 8086 and explain typical applications of each
register.
1.6 Draw and discuss flag register of 8086 in brief.
1.7 What do you mean by addressing modes? What are the different addressing
modes supported by 8086? Explain each of them with suitable examples.
1.8 Explain the addressing modes for control transfer instructions.
1.9 What are the different instruction types of 8086?
1.10Which instructions of 8086 can be used for look up table manipulations?
1.11What is the difference between the respective shift and rotate instructionss?
1.12How will you enter the single step mode of 8086?
1.13What is LOCK prefix? What is its use?
1.14What is REP prefix? What is its use?
*****

DMC 1932
NOTES

NOTES
UNIT II
8086 SYSTEM DESIGN

2.1 INTRODUCTION
A set of conductors used for communicating information between the components in

a computer system is called a bus. If a bus connects two minor components within a major
component it is called an internal bus. When a bus connects two major components, such
as a CPU and an interface, it is called an external bus. Because an internal bus is ordinarily
internal to an IC device and its construction is dependent on the device, the exact construction
of these buses is of little interest to us. External buses, on the other hand, have common
characteristics that must be understood when designing the overall architecture of a computer
system. Some system may include more than one external bus, others contain only one bus
which is referred to as the system bus, and it is the basic structure of system buses, particularly
those in 8086 and 8088 based systems that is discussed in this chapter.
 To study the signals of 8086 processor

 To have knowledge about both the minimum and maximum mode configuration
 To understand system bus timing for various modes and signals
2.3 BASIC 8086/8088 CONFIGURATIONS
In order to adapt to as many situations as possible both the 8086 and 8088 have
been given two modes of operation the minimum mode and the maximum mode. The
minimum mode is used for a small system with a single processor a system in which the
8086/8088 generates all the necessary bus control signals directly (thereby minimizing the
required bus control logic). The maximum mode is for medium-size to large systems, which
often include two or more processors. In the maximum mode, the 8086/8088 encodes the
basic bus control signals into 3 status bits, and uses the remaining control pins to provide
the additional information that is needed to support a multiprocessor configuration.

DMC 1932
NOTES MAX
MODE
MIN
MODE
MAX
MODE
MIN
MODE
GND 1 40 VCC
GND 1 40 VCC
AD14 2 39 AD15
AD14 2 39 AD15
AD13 3 38 A16/S3
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD10 6 35 A19/S6 (HIGH)
AD9 7 34 SSO
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD8 8 33 MN/MX
AD7 9 32 RD
AD7 9 32 RD
AD6 10 8086 31 HOLD (RQ/GTO )
AD6 10 8086 31 RQ/GTO (HOLD)
CPU HLDA (RQ/GT1)
CPU AD5 11 30
AD5 11 30 RQ/GT1 (HLDA)
AD4 12 29 WR (LOCK)
AD4 12 29 LOCK (WR)
AD3 13 28 I0/M (S2)
AD3 13 28 S2 (M/IO)
AD2 14 27 DT/IR (S1)
AD2 14 27 S1 (DT/IR)
AD1 15 26 DEN (S0)
AD1 15 26 S0 (DEN)
AD0 16 ALE (QS0)
25
AD0 16 25 QS0 (ALE)
NMI 17 24 INTA (QS1)
NMI 17 24 QS1 (INTA)
INTR 18 23 TEST
INTR 18 23 TEST
CLK 19 22 READY
CLK 19 22 READY
GND 20 21 RESET
GND 20 21 RESET
(a) 8086 pin diagram

(a) 8086 pin diagram
Figure 2.3.1 Pin configuration of 8086 and 8088
The Pin diagrams for the 8086 and 8088 and the pin definitions that are common to
both modes are given in Fig 2.3.1. Pin 33 (MN/MX) determines the configuration option
When it is strapped to ground the processor is to be used in a maximum mode configuration
and when it is strapped to +5 V it is to be operated in its minimum mode. Both processors
multiplex the address and data signals and both have 20 address pins with address and
status signals being multiplexed on the 4 most significant address pins. However, because
the 8088 can only transfer 8 bits of data at a time, only eight of its pins are used for data,
as opposed to 16 for the 8086. Except for pins 28 and 34 the two processors have the
same control pin definitions. Pin 28 differs only in the minimum mode. For the 8088 this
minimum mode signal is inverted from that of the 8086, so that the 8088 is compatible with
the Intel 8085 microcomputer chip. Table 2.3.1 gives the pin description details of 8086.

Table 2.3.1 Pin Description details
NOTES
Symbol Pin No. Type Name and Function
Ad15-AD0 2-16, 39 I/O ADDRESS DATA BUS: These lines constitute the time
multiplexed memory/IO address (T1), and data (T 2,T3,T4) bus.
A0 is analogous to BHE for the lower byte of the data bus, pins
D7-D0. It is LOW during T1 when a byte is to be transferred on
the lower portion one line missing to the lower half would
normally us A0 to condition chip select functions. (See
(See BHE) . These lines are active HIGH and float to 3-state
off during interrupt acknowledge and local bus “hold
acknowledge”
A19/S6, 35-36 O ADDRESS/STATUS: During T1 these are the four most
A18/S5, significant address lines for memory operations. During I/O
A17/S4, operations these lines are LOW. During memory and I/O
A16/S3, operations, status information is available on these lines during
(T2,T3,T4). The status of the interrupt enable FLAG bit (S5) is
updated at he beginning of each CLK cycle. A17/ S4 and A16/ S3
are encoded as shown.
This information indicates which relocation register is presently
being used for data accessing.
These lines float to 3-state OFF during local bus “hold
acknowledge”.
A17/S4 A16/S3 Characteristics
0(LOW) 0 Alternate Data

0 1 State
1(HIGH) 0 Code or None
1 1 Data
S8 is 0
(LOW)
BHE / S 7 34 O BUS HIGHs ENABLE/STATUS: During T1 the bus

high enable signal ( BHE ) should be used to enable
data onto the most significant half of the data bus, pins
D15- D8, Eight-bit oriented devices tied to the upper
half of the bus would normally use BHE to condition
chip select functions, BHE is LOW during T1 for
read, write and interrupt acknowledge cycles when a
byte is to be transferred on the high portion of the bus.
The S7 status information is available during T2, T3,
and T4. The signal is active LOW floats to 3-state OFF
in “hold” It is LOW during T1 for the first interrupt
acknowledge cycle,
BHE A0 Characteristics
0 0 Whole word
0 1 Upper byte from/to add address
1 0 Lower byte from/to even address
1 1 None
RD 32 O READ: Read strobe indicates that the processor is
performing a memory or l/O read cycle, depending on
the state of the S2 pin. This signal is used to read
devices which reside on the 8086 local bus RD is
active LOW during T2, T3 and Tw of any read cycle,
and is guaranteed to remain HIGH in T2 until the 8086
local bus has floated. This signal floats to 3-state OFF
in “hold acknowledge”.

DMC 1932
NOTES Symbol Pin

No.
Type Name and Function
READY 22 l READY: Is the acknowledgement from the addressed memory or

I/O device that it will complete the data transfer. The READY
signal from memory /IO is synchronized by the 8284A Clock
Generator to form READY. This signal is active HIGH. The
8086 REDY input is not synchronized. Correct operation is not
guaranteed if the setup and hold times are not met.
INTR 18 l INTERUPT REQUEST: Is a level triggered input which is
sampled during the last clock cycle of each instruction to
determine if the processor should enter into an inter into an
interrupt acknowledge operation. A subroutine is vectored to via
an interrupt vector lookup table located in system memory. It can
be internally masked by software resetting the interrupt enable
bit. INTR is internally synchronized. This signal is active HIGH.
TEST 23 1 TEST : Input is examined by the “Wait” instruction. If the
TEST input is LOW execution continues, otherwise the
processor waits in an “idle” state. This input is synchronized
internally during each clock cycle on the leading edge of CLK.
NMI 17 1 NON-MASKABLE INTERPUT: an edge triggered input which
causes a type 2 interrupt. A subroutine is vectored to via an
interrupt vector lookup table located in system memory. NMI is
not maskable internally by software. A transition from LOW to
HIGH initiates the interrupt at the end of the current instruction.
This input is internally synchronized.
RESET 21 1 RESET: causes the processor to immediately terminate its
present activity. The signal must be active HIGH for at least four
clock cycles. It restarts execution, as described in the instruction
set description, when RESET returns LOW. RESET is internally
synchronized.
CLK 19 1 CLOCK: provides the basic timing for the processor and bus
controller. It is asymmetric with a 33% duty cycle to provide
optimized internal timing.
Vcc 40 Vcc: +5V power supply pin
GND 1.20 GROUND
MN/ MX 33 1 MINIMUM/MAXIMUM: indicates what mode the processor is
to operate in. The two modes are discussed in the following
section.
On the 8086, pin 34 (BHE) designates whether or not at least 1 byte of a transfer is
to be made on AD15 through AD8. A0 on this pin indicates that the more significant data
lines are to be used; otherwise, only AD7 through AD0 are used. Together the BHE and
A0 signals indicate to the interfaces connected to the bus how the data are to appear on
the bus. The four possible combinations are defined as follows:

Operation BHE A0 Data pins used

NOTES
Write/read a word at an even address 0 0 AD15-AD0
Write/read a byte at even address 1 0 AD7-AD0
Writers/read a byte at an odd address 0 1 Ad15-AD8
Write/read a word at an odd address 0 1 AD15-AD8 (First bus cycle: puts the
least significant data byte
on a AD15-AD8
1 0 AD7-AD0 (Next bus cycle: puts the
most significant data byte on
AD7-AD0)
where 0 is low and 1 is high
Because, on the 8088, only AD7—AD0 can transfer data, this pin is not needed to
indicate the upper or lower half of the data bus and is free to provide status information.
Pins 1 and 20 are grounded. Pins 2 through 16 and 39 (AD 15—AD0) hold the address
needed for the transfer during the first part of the bus cycle, and are free to transfer the
data during the remaining part of the cycle.
Pins 17 and 18 (NMI and INTR) are for interrupt requests. Pin 19 (CLK) is for
supplying the clock signal that synchronizes the activity within the CPU. Pin 21 (RESET) is
for inputting a system reset signal. Most systems include a line that goes to all system
components and a pulse is automatically sent over this line when the system is turned on, or
the reset pulse can be manually generated by a switch that allows the operator to reinitialize
the system. A 1 on the reset line causes the components to go to their “turn on” state. For
the processor this state is having the PSW. IP, DS, SS, ES, and instruction queue cleared
and CS set to FFFF. With (IP) = 0000 and (CS) = FFFF the processor will begin executing
at FFFFO. Normally, this location would be in a read-only section of memory and would
contain a JMP instruction to a program for initializing the system and loading the application
software or operating system. Such a program is referred to as a bootstrap loader.
Pin 22 (READY) is for inputting an acknowledge from a memory or I/O interface

that input data will be put on the data bus or output data will be accepted from the data bus
within the next clock cycle. In either case, the CPU and its bus control logic can complete
the current bus cycle after the next clock cycle. Pin 23 (TEST) is used in conjunction with
the WAIT instruction and is employed primarily in, multiprocessing situations. Pins 24
through 31 are mode dependent and are considered later. Pin 32 (RD) indicates that an
input operation is to be performed and, in minimum mode, is used along with pin 28 which
distinguishes a memory transfer from an 1/0 transfer, and pin 29, which indicates an output
operation, to determine the type of transfer.

DMC 1932
During the first part of a bus cycle pins 35—38 (AD19/S6—AD16/S3) output the 4
NOTES high-order bits of the address, and during the remaining part of the cycle they output status
information. Status bits S3 and S4 indicate the segment register that is being used to generate
the address and bit S5 reflects the contents of the IF flag. S6 is always held at 0 and
indicates that an 8086/8088 is controlling the system bus.
Pin 40 (VCC) receives the supply voltage, which must be +5 V ± 10%. Systems
based on an 8086 or 8088 are ordinarily designed so that only a TTL compatible + 5-V
supply voltage and ground are needed, thus simplifying the design of the power supply.
2.4 MINIMUM MODE
A processor is in minimum mode when its MN/MX pin is strapped to +5 V. The

definitions for pins 24 through 31 for the minimum mode are given in Table 8-3.
Table 2.4.1 Pin definition for minimum mode

28 O STATUS LINE: logically equivalent to S2. In the maximum mode.
M / IO
It is used to distinguish a memory access from an I/O access.
M / IO becomes valid in the T4 preceding a bus cycle and remains
valid until the final T4 of the cycle (M = HIGH, IO = LOW, M / IO
floats to 3-sate OFF In local bus “hold acknowledge”
WR 29 O WRITE: Indicates that the processor is performing a write memory
or write I/O cycle, depending on the state of the M / IO signal.
WR is active for T2, T3 and TW of any write cycle. It is active
LOW, and floats to 3-stats to OFF in local bus “hold acknowledge”
INTA 24 O INTA : is used as a read strobe for interrupt acknowledge cycles. It
is active LOW during T2, T 3 and T W of each interrupt acknowledge
cycle.
ALE 25 O ADDRESS LATCH ENABLE: Provided by the Processor to latch
the address into the 8282/8283 address latch. It is a High pulse active
during T1 of any bus cycle. Note that ALE is never floated.
27 O DATA TRANSMIT/RECEIVE: needed in minimum system that
DT / R
desires to use an 8286/8287 data bus transceiver. It is used to control
the direction of data flow through the transceiver. Logically
DT / R is equivalent to S1 in the maximum mode, and its timing
is the same as for M / IO . (T = High, R = LOW.) This signal floats
to 3-state OFF in local bus “hold acknowledge”.
DEN 26 O DATA ENABLE: provided as an output enable for the 8286/8287 in
DEN is active LOW
a minimum system which uses the transceiver
during each memory and I/O access and for INTA cycles. For a
read or INTA CYCLE It is active from the middle of T 2 until the
middle of T4, while for a write cycle it is active from the beginning
of T2 until the middle of T 4 DEN floats to 3. state OFF in local
bus “hold acknowledge”.

HOLD HLDA 31, 30 I/O HOLD: Indicates that another master is requesting a local bus
“hold” To be acknowledged, HOLD must be active HIGH. The NOTES
processor receiving the “hold” request will issue HLDA (HIGH) as
an acknowledgement in the middle of a T4 or T1 clock cycle.
Simultaneous with the issuance of HLDA the processor will float the
local bus and control lines, After HOLD is detected as being LOW,
the processor will LOWer the HLDA, and when the processor needs
to run another cycle, it will again drive the local bus and control
lines. Hold acknowledge (HLDA) and HOLD have internal pull–up
resistors.
The same rules as for RQ / GT apply regarding when the local bus
will be released.
HOLD is not an asynchronous input. External synchronization
should be provided if the system cannot otherwise guarantee the
setup time.
A typical minimum mode configuration is shown in Figure 2.4.1.
Clock
(8284A)
CLK RESET
READY BHE
MN/MX +5 V
ALE Address
latches
BHE (3 8282s)
A19-A16 Address bus
AD15-AD0
8086
Transceivers
(2 8286s) Data bus
optional
DEN
DT/R
M/IO
WR
RD
HOLD
HLDA Control bus
INTR
INTS
READY
RESET
Figure 2.4.1 Minimum Mode System

DMC 1932
The address must be latched since it is available only during the first part of the bus
NOTES cycle. To signal that the address is ready to be latched a 1 is put on pin 25, the address
latch enable (ALE) pin. Typically, the latching is accomplished using Intel 8282s, as shown
in Figure 2.4.2. Because 8282 is an 8-bit latch, two of them are needed for a 16-bit
address and three are needed if a full 20-bit address is used. In an 8086 system, BHE
would also have to be latched. For a small 8088 system that has only 64k bytes of memory,
only two 8282s would be required. A signal on the STB pin latches the bits applied to the
input data lines DI7—DI0. Therefore, STB is connected to the 8086’s ALE pin and DI7—
DI0 are attached to eight of the address lines. An active low signal on the OE enables the
latch’s outputs DO7—DO0 and a 1 at this pin forces the outputs into their high-impedance
state. in an 8086/8088 single-processor system that does not include a DMA controller
this pin is grounded.
ALE
AD0 DI0 DO0

AD1 DI1 DO1
AD2 DI2 DO2

AD3 DI3 DO3
8086 8282
AD4 DI4 DO4
AD5 DI5 DO5

AD6 DI6 DO6
AD7 DI7 DO7
OE STB
Data
AD8 DI0 DO0
AD9 DI1 DO1 Address
8282
AD15 D17 DO7
OE STB
Data
A16
A17
A18
8282
A19
BHE BHE
OE STB
Figure 2.4.2 Application of 8282 Latch
If a system includes several interfaces, then drivers and receivers, which may not be
needed on small, single-board systems, will be required for the data lines. The Intel IC

device for implementing the transceiver (driver/receiver) block shown in Figure 2.4.3 is
the 8286 transceiver device. The 8286 contains 16 tri-state elements, eight receivers, and NOTES
eight drivers. Therefore, only one 8286 is needed to service all of the data lines for an
8088, but two are required in an 8086 system. Figure 2.4.3 shows how 8286s are connected
into a system and a logic diagram of one of its cells. The 8286 is symmetric with respect to
its two sets of data pins, either the pins A7—A0 can be the inputs and B7—B0 the
outputs. or vice versa.
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Two are required for
an 8086 system
8088
A0 B0
8286
A1 B1
A2 B2
A3 B3
Data bus
A4 B4
A5 B5
A6 B6
A7 B7
DEN OE T
DT/R
Figure 2.4.3 Application of 8286
The output enable (OE) pin determines whether or not data are allowed to pass
through the 8286 and the transmit (T) pin controls the direction of the data flow. When OE
= 1, data are not transmitted through the 8286 in either direction. If it is 0, then T causes
A7—A0 to be the inputs and T = 0 results in B7—B0 being the inputs. In an 8086/8088-
based system the OE pin would be connected to the DEN pin, which is active low whenever
the processor is performing an I/O operation. The A7-A0 pins are connected to the
appropriate address/data lines and the T pin is tied to the processor’s DT/R pin. Thus,

DMC 1932
when the processor is outputting the data flow is from A7—A0 to B7—B0, and when it is
NOTES inputting the flow is in the other direction. The processor floats the DEN and DT/R pins in
response to a bus request on the HOLD pin.
Sometimes a system bus is designed so that the address and/or data signals are inverted.
Therefore, the 8282 and 8286 both have companion chips that are the same as the 8282
and 8286 except that they cause an inversion between their inputs and outputs. The
companion for the 8282 is the 8283 and the companion for the 8286 is the 8287.
The third component, other than the processor, that appears in Figure 2.4.1 is an
8284A clock generator. In addition to supplying a train of pulses at a constant frequency it
synchronizes ready (RDY) signals, which indicate an interface is ready to complete a
transfer, and reset (RES) signals, which initialize the system, with the clock pulses. Although
these two signals may be sent at any time, the 8284A will not reflect them in its READY
and RESET outputs until the trailing edge of the clock pulse in which they are received.
All three of the devices considered above, the 8282, 8286, and 8284A, require only
+ 5-V supply voltages. Their inputs and outputs are TTL compatible and, therefore, the
devices are compatible with each other and with the 8086 and 8088. In a minimum system
the control lines do not need to be passed through transceivers, but can be used directly.
The M/IO, RD. and WR lines specify the type of transfer according to the following table:
M/IO RD WR
0 0 1 I/O read
0 1 0 I/O write
1 0 1 Memory read
1 1 0 Memory write
where 0 is low and 1 is high.
2.5 MAXIMUM MODE

A processor is in maximum mode when its MN/MX pin is grounded. The maximum
mode definitions of pins 24 through 31 are given in Table 2.5.1 and a typical maximum
mode configuration is shown in Figure 2.5.1. It is clear from Figure 2.5.1 that the main
difference between minimum and maximum mode configurations is the need for additional
circuitry to translate the control signals. This circuitry is for converting the status bits S0,
S1, and S2 into the I/O and memory transfer signals needed to direct data transfers, and
for controlling the 8282 latches and 8286 transceivers. It is normally implemented with an
Intel 8288 bus controller. Also included in the system is an interrupt priority management
device; however, its presence is optional.
The S0, S1, and S2 status bits specify the type of transfer that is to be carried out and
when used with an 8288 bus controller they obviate the need for the M/IO, WR, INTA.
ALE, DT/R. and DEN signals that are output over pins 24 through 29 when the processor
is operating in minimum mode. Except for the case S1 S0 = 1, S2 = 0 indicates a transfer

between an I/O interface and the CPU and S2 = 1 implies a memory transfer. The S1 bit
specifies whether an input or output is to be performed. From the status the 8288 is able to NOTES
originate the address latch enable signal to the 8282s, the enable and direction signals to
the 8286 transceivers, and the interrupt acknowledge signal to the interrupt controller.
Table 2.5.1 Pin description of Maximum mode Signals
Symbol Pin Type Name and Function

No.
QS1, QS0 24,25 O QUEUE STATUS: The queue status us valid during the CLK
cycle, after which the queue operation is performed.
QS1 and QS0 provide status to allow external of the internal
8086 instruction queue.
QS1 QS0 Characteristics
0(LOW)1 0 No Operation
0 1 First Byte of Op- Code from Queue
1 (HIGH) 0 Empty the Queue
1 1 Subsequent Byte from Queue
S 2 , S1 , S 0 26-28 0 STATUS: active during T4, T1 and T2 and is returned

to the passive state (1,1,1) during T3 or during TW
when READY is HIGH. This status is used by is
8288 Bus controller to generate all memory and I/O
access control signals. Any change by S 2 , S1 or S0
during T4 is used to indicate the beginning of a bus
cycle, and the return to the passive state in T3 or TW
is used to indicate the end of a bus cycle
Symbol Pin Type Name and Function

No.
26-28 0 These singles float to 3-state off in “hold
S 2 , S1 , S0 acknowledged”. These status lines are encoded as
Continued  shown
S S Characteristics
2 1 S0
0(LOW) 0 0 Interrupt
0 0 1 Acknowledge
0 1 0 Read I/O Port
0 1 1 Write I/O Port
1(HIGH) 0 0 Halt
1 0 1 Code Access
1 1 0 Read Memory
1 1 1 Write Memory
Passive

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30,31 I/O REQUEST/ GRANT: Pins are used bus other local bus masters
NOTES RQ / GT0
to force the processor to release the local bus at the end of the
RQ / GT1 processor’s current bus cycle. Each pin is bidirectional with
RQ / GT0 having higher priority than RQ / GT1 ,
RQ / GT pins have internal pull-up resistors and may be left
unconnected. The request/ grant sequence is as follows (see
Page 2-24):
1. A pulse of 1 CLK wide from another local bus master
indicates a local bus request (“hold”) to the 8086 (pu1se
1).
2. During a T4 or T1, clock cycle, a pulse 1 CLK wide from
the 8086 to the requesting master (pulse 2), indicates that
the 8086 has allowed the local bus to float and that it will
enter the “hold” acknowledge” state at the next CLK. The
CPU’s bus interface unit is disconnected logically from
the local bus during “hold” acknowledge”
3. A pulse 1 CLK wide from the requesting master indicates
to the 8086 (pulse 3) that the “hold” request is about to
end and that the 8086 can reclaim the local bus at the next
CLK.
Each master- master exchange of the local bus is a sequence of

3 pulses. There must be one dead CLK cycle after each bus
exchange. Pulses are active LOW.
I the request is made while the CPU is performing a memory
cycle. It will release the local bus during T4 of the cycle when
at the following conditions are met.
1. Request occurs on or before T2.
2. Current cycle is not the low the low byte of a word (on an
odd address).
3. Current cycle is not the first acknowledge of an interrupt
acknowledge sequence.
4. A locked instruction is not currently executing.
If the local bus is idle when the request is made the two
possible events will follow:
1. Local bus will be released during the next clock.
A memory cycle will start within 3 clocks. Now the four rules
for a currently active memory cycle apply with condition
number 1 already satisfied.
29 O LOCK : Output indicates that other system bus masters are not
LOCK
gain control of the system bus while LOCK is active LOW. The
LOCK signal is activated by the “LOCK” prefix instruction and
remains active until the completion of the next instruction. This
signal is active LOW, and floats to 3- state OFF in “hold”
acknowledge”.
The QS0 and QS1 pins are to allow the system external to the processor to interrogate
the status of the processor instruction queue so that it can determine which instruction it is
currently executing and the LOCK pin indicates that an instruction with a LOCK prefix is
being executed and the bus is not to be used by another potential master. These pins are
needed only in multiprocessor systems and, along with the LOCK prefix.

NOTES
8284A
Clock
READY
RESET
CLK
RESET
OE
READY
Latches
MN/MX 8282s
BHE
BHE
A19-A16 Address bus
AD15-AD0
STB
8086/8088
Transceivers
8286s Data bus
OE
Bus controller
8288
Control bus
S0 INTR
S1
Interrupt requests
S2
Interrupt
acknowledge
INTR Priority interrupt

controller
RQ/GT0 8259A
RQ/GT1 and associated logic
Figure 2.5.1 Maximum mode configuration
The HOLD and HLDA pins become the RQ/GT0 and RQ/GT1 pins. Both bus
requests and bus grants can be given through each of these pins. They are exactly the same
except that if requests are seen on both pins at the same time, then the one on RQ/GT0 is
given higher priority. A request consists of a negative pulse arriving before the start of the
current bus cycle.
The grant is a negative pulse that is issued at the beginning of the current bus cycle provided
that:
1. The previous bus transfer was not the low byte of a word to or from an odd
address if the CPU is an 8086. For an 8088, regardless of the address alignment,
the grant signal will not be sent until the second byte of a word reference is accessed,

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2. The first pulse of an interrupt acknowledgment did not occur during the previous
NOTES bus cycle.
3. An instruction with a LOCK prefix is not being executed. If condition 1 or 2 is not
met, then the grant will not be given until the next bus cycle, and if condition 3 is not
met, the grant will wait until the locked instruction is completed. In response to the
grant the three-state pins are put in their high- impedance state and the next bus
cycle will be given to the requesting master. The processor will be effectively
disconnected from the system bus until the master sends a second pulse to the
processor through the RQ/GT pin.
An expanded view of a maximum mode system which shows only the connections to
an 8288 is given in Figure 2.5.2. The S0, S1, and S2 pins are for receiving the corresponding
status bits from the processor. The ALE, DT/R, and DEN pins provide the same outputs
that are sent by the processor when it is in minimum mode (except that DEN is inverted
from DEN). The CLK input permits the bus controller activity to be synchronized with that
of the processor. In a single-processor system AEN and lOB are normally grounded and
a I is applied to CEN. The meaning of the MCE/PDEN output depends on the mode,
which is determined by the signal applied to JOB: When JOB is grounded it assumes its
master cascade enable (MCE) meaning and can be used to control cascaded 8259As. In
the event that + 5 V is connected to IOB, the peripheral data enable (PDEN) meaning,
which is used in multiple-bus configurations, is assumed.
The remaining pins given in Figure 2.5.2 have the following definitions:
INTA—Issues the two interrupt acknowledgment pulses to a priority interrupt controller
or an interrupting device when S0 = S1 = S2 = 0
IORC (I/O Read Command)—Instructs an I/O interface to put the data contained in the
addressed port on the data bus.
IOWC (I/O Write Command)—Instructs an I/O interface to accept the data on the data
bus and put the data into the addressed port.
MRDC (Memory Read Command)—Instructs the memory to put the contents of the
addressed location on the data bus.
MWTC (Memory Write Command)—Instructs the memory to accept the data on the
data bus and put the data into the addressed memory location
These signals are active low and are output during the middle portion of a bus cycle.
Clearly, only one of them will be issued during any given bus cycle.

STB
Latches
8282s (3)
NOTES
If there is no
8259A,
Clock this is an
8284A Transceivers
inverter
8286s(2)
OE
T
DT/R MRDC
DEN
ALE
8086/8088 MWTC
CLK control
S0 S0 Bus bus
S1 S1 controller IORC
8288
S2 S2
AEN
IOB IOWC
+5 V CEN INTA MCE/PDEN
Priority interrupt
controller
8259A
Figure2.5.2 Connection to an 8288 bus controller
This gives slow interfaces an extra clock cycle to prepare to input the data as with the
other 8086 supporting devices, the 8288 requires a +5-V supply voltage and has TTL-
compatible inputs and outputs.
2.6 SYSTEM BUS TIMING
Until now we have vaguely referred to the first part, middle part, and last part of the
bus cycle. It is the objective of this section to put the discussion of timing on a more precise
footing. The length of a bus cycle in an 8086/8088 system is four clock cycles, denoted T1
through T4, plus an indeterminate number of wait state clock cycles, denoted TW, If the bus
is to be inactive after the completion of a bus cycle, then the gap between successive
cycles is filled with idle state clock cycles represented by T1, Wait states are inserted
between T3 and T4 when a memory or I/O interface is not able to respond quickly enough
during a transfer. A typical succession of bus cycles is given in Figure 2.6.1.

DMC 1932
NOTES Wait states while waiting for memory

or I/O interface to respond
T1 T2 T3 T4 T5 T1 T2 T3 T4 T1 T1 T1 T2 T3 Tw Tw T4 T1 T1
Idle states between

bus cycles
Figure 2.6.1 Typical sequence of Bus Cycles
ONE BUS CYCLE

T1 T2 T3 T4
CLK
A19/S6-A16/S3 STATUS OUT

ADDRESS, BHE OUT
AND BHE / S7
AD15-AD0 ADDRESS OUT DATA IN
ALE
M/IO LOW = I/O READ, HIGH = MEMORY READ
RD
DT/R
DEN
(a) Input
Figure 2.6.2a Minimum Mode Bus Timing Diagram (input)

T1
ONE BUS CYCLE
T2 T3 T4
NOTES
CLK
A19/S6-A16/S3 STATUS OUT

ADDRESS, BHE OUT
AND BHE / S7
AD15-AD 0 ADDRESS OUT DATA OUT
ALE
M/IO LOW = I/O READ, HIGH = MEMORY READ
WR
DT/R
DEN
(b) Output
Figure 2.6.2b Minimum Mode Bus Timing Diagram (output)
The timing diagrams for 8086 minimum mode input and output transfers that require
no wait states are shown in Figure 2.6.2. When the state of the processor is such that it is
ready to initiate a bus cycle it applies a pulse to the ALE pin during T1. Before the trailing
edge of the ALE signal the address, BHE, M/IO, DEN, and DT/R signals should be
stable, with DEN = 1 and DT/R = 0 for an input and DT/R = 1 for an output. At the trailing
edge of the ALE signal the 8282s latch the address. During T2, the address is dropped and
S3 through S7 are output on AD16/S3—AD19/S6 and BHE/S7, and DEN is lowered to
enable the 8286 transceivers. If an input is being conducted, RD is activated low during T2
and AD15—ADO enters a high-impedance state in preparation for input. If the memory
or I/O interface can perform the transfer immediately, there are no wait states and the data
are put on the bus during T3. After the input data are accepted by the processor, RD is
raised to 1 at the beginning of T4 and, upon detecting this transition, the memory or I/O
interface will drop its data signals. For an output, the processor applies the WR = 0 signal
and then the data during T2, and in T4 WR is raised and the data signals are dropped. For
either an input or output, DEN is raised during T4 to disable the transceivers and the M/IO
signal is set according to the next transfer at this time or during a subsequent T1 state.
The bus timing has been designed so that the memory or I/O interface involved in a
transfer can control when data are to he placed on or taken from the bus by the interface.
This is done by having the interface send a READY signal to the processor (perhaps via an

DMC 1932
8284A) when it has made data available or accepted data. If a READY signal has not
NOTES been received by the processor by the beginning of T3, then one or more Tw states will be
inserted between T3 and T4 until a READY has been received. The bus activity during Tw
is the same as during T3. A signal applied to an RDY input of an 8284A will cause a
READY output to the processor at the trailing edge of the current clock cycle; therefore,
if a wait state is to be avoided, an RDY input must be received before the beginning of the
T3 clock cycle.
The timing diagram for an interrupt acknowledge is shown in Figure 2.6.3. If an

interrupt request has been recognized during the previous bus cycle and an instruction has
just been completed, then a negative pulse will be applied to INTA during the current bus
cycle and the next bus cycle. Each of these pulses will extend from T2 to T4. Upon receiving
the second pulse, the interface accepting the acknowledgment will put the interrupt type on
AD7—ADO, which are floated the rest of the time during the two bus cycles. The type
will be available from T2 to T4.
Idle states, typically 3, are needed

on an 8086 system, but not on
an 8088 system
T1 T2 T3 T4 T1 T1 T1 T1 T2 T3 T4
ALE
INTA
Interrupt
AD7-AD0 type
Figure 2.6.3 Interrupt Acknowledge
Figure 2.6.4 shows the timing of a bus request and bus grant in a minimum mode
system. The HOLD pin is tested at the leading edge of each clock pulse. If a HOLD signal
is received by the processor before T4 or during a T1 state, then the CPU activates HLDA
and the succeeding bus cycles will be given to the requesting master until that master drops
its request. The lowered request is detected at the rising edge of the next clock cycle and
the HLDA signal is dropped at the trailing edge of that clock cycle. While HLDA is 1, all
of the processor’s three-state outputs are put in their high-impedance state. Instructions
already in the instruction queue will continue to he executed until one of them requires the
use of the bus. The instruction MOV AX,BX could execute completely, but MOV
AX,NUMBER would only execute until it is necessary to bring in data from the location
NUMBER.

T4ORT1 NOTES
CLK
HOLD
HLDA
Figure 2.6.4 Bus Request and Bus Grant Timing on a Minimum Mode
System
The timing diagrams for input and output transfers on a maximum mode system are
given in Figure 2.6.5. The S0, S1, and S2 bits are set just prior to the beginning of the bus
cycle. Upon detecting a change from the passive S0 = S1= S2 =1 state, the 8288 bus
controller will output a pulse on its ALE pin and apply the appropriate signal to its DT/R
pin during T1. In T2, the 8288 will set DEN = 1, thus enabling the transceivers, and, for an
input, will activate either MRDC or IORC. These signals will he maintained until T4. For
an_output. the AMWC or AIOWC is activated from T2 to T4 and the MWTC or IOWC
is activated from T3 to T4. The status bits S0, S1, and S2 will remain active until T3 and will
become passive (all is) during T3 and T4. As with the minimum mode, if the READY input
is not activated before the beginning of T3 wait states will he inserted between T3 and T4.
One bus cycle

T1 T2 T3 T4
CLK
S2-S0 S2-S0 S2-S0 Inactive

BHE, A19-A16
Address/status Float
and BHE/S7 S7-S3
Address/data A15-A0
(AD15-AD0)
Data in D15-D0
* ALE
* MRDC or IORC
* DT/R
* DEN
(a) Input

DMC 1932
NOTES T1
One bus cycle
T2 T3 T4
CLK
S2-S0 S2-S0 S2-S0 Inactive

BHE, A19-A16
Address/status Float
S7-S3
and BHE/S7
Address/data A15-A0 Data out D15-D0

(AD15-AD0)
* ALE
* AMWC or AIOWC
* MWTC or IOWC
* DEN
* 8288 bus controller outputs
(b) Output
Figure2.6.5 Timing Diagram for a maximum mode system
T4 or T1
CLK
RQ/GT
Master requests CPU grants bus Master releases
bus access to coprocessor bus
Figure 2.6.6 Timing Diagram for Maximum mode Bus requests and
grants RQ/GT
Interrupt acknowledgment signals are the same as in the minimum mode case except
that a 0 is applied to the LOCK pin from T2 of the first bus cycle to T2 of the second bus
cycle. Bus requests and grants are handled differently however and the timing on an RQ/
GT pin is shown in Fig 2.6.6. A request/grant/release is accomplished by a sequence of
three pulses. The RQ/GT pins are examined at the rising edge of each clock pulse and if a
request is detected (and the necessary conditions discussed previously are met), the
processor will apply a grant pulse to the RQ/GT immediately following the next T4 or T1
state. When the requesting master receives this pulse it seizes control of the bus. This
master may control the bus for only one bus cycle or for several bus cycles. When it is
ready to relinquish the bus it will send the processor the release pulse over the same line
that it made its request. As noted before. RQ/GT0 and RQ/GT1 are the same except that
RO/ GTO has higher priority.

SUMMARY
NOTES
 The signals of 8086 are discussed in detail.
 Minimum mode configuration of 8086 is discussed with supportive diagrams
 Maximum mode configuration of 8086 is discussed with supportive diagrams
 General bus cycle operations have been described with the help of timing diagrams.
EXERCISES
2.1 Explain the function of the following signals of 8086.
(I) ALE (ii) DT / R (iii) DEN (iv) LOCK

(v) TEST (vi) MN / MX (vii) BHE (viii) M / IO
(ix) RESET (x) QS0 (xi) READY (xii) NMI
(xiii) INTR (xiv) HOLD (xv) HLDA
2.2 Draw and discuss a typical minimum mode 8086 system.
2.3 Draw and discuss a typical maximum mode 8086 system. What is the use of a bus
controller in maximum mode?
2.4 What are the functions of the clock generator IC 8224, in the 8086/8088 systems?
2.5 Draw and discuss the Bus Request and Bus Grant timing diagrams of 8086 in
minimum mode.
2.6 Draw and discuss the Bus Request and Bus Grant timing diagram of 8086 in
maximum mode?
*****

DMC 1932
NOTES

NOTES
UNIT III
INTERFACING CONCEPTS
3.1 INTRODUCTION
In the previous chapters we have presented the architecture, instruction set, and the
art of programming, signals of 8086, minimum mode and maximum mode configurations
with 8086. In this chapter the general peripheral devices and their interfacing techniques
with the microprocessor 8086/8088 are discussed. In the minimal working system
configuration of the general microprocessor, we consider a keyboard, display system,
memory system and I/O ports along with the CPU. In general, all these devices are called
peripheral devices. There are also some additional dedicated peripheral devices like
programmable interrupt controller, direct memory access controller, etc. All these dedicated
peripheral are studied in this chapter. The microprocessor may be seen as the heart of the
system, while all the peripheral circuits including memory system are built around the
microprocessor. Since a processor without memory is not meaningful, memory may also
be considered as an integral part of a microprocessor system.
Most of the peripheral devices are designed and interfaced with a CPU either to
enable it to communicate with the user or an external processor and to easy the circuit
operation so that the microprocessor works more efficiently. The use of special purpose
peripheral integrated devices simplifies both – the hardware circuits and the software
considerably. Each of these special purpose devices need a typical sequence of instruction
to make it work. This instruction sequence appropriately initializes the peripheral makes it
work under the control of microprocessor. Thus each dedicated peripheral device needs
suitable initialization. However memory, unlike the peripheral device, does not need any
initialization and doesn’t directly participate in the process of communication between the
CPU and the user. In this chapter, we present interfacing technique of memory, I/O ports
and few other peripherals.
 To understand the basic memory and I/O interfacing concepts

 To study how parallel devices communicate with microprocessor via parallel
communication interface
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 Also, to understand how serial devices communicate with microprocessor via serial
NOTES communication interface
 To study about the timer and it various modes of operation
 To know about how keyboard and display is interfaced with the processor
 To understand how direct memory access is done with the help of DMA controller.
3.3 MEMORY INTERFACING
In this section we will consider the interfacing of memory with 8086/8088. The
semiconductor memories are organized as two dimensional arrays of memory locations
for eg, 4K x 8 or 4K byte memory contain 4096 locations, where each location contains
8 bit data and only one of the 4096 locations can be selected at a time. Once a location is
selected all the bits in it are accessible using a group of conductors called data bus.
Obviously, for addressing 4K bytes of memory, 12 address lines are required. In general,
to address a memory location out of N memory location, we will require atleast n bits of
address, i.e. n addressing lines where n= Log2N. Thus if the microprocessor has n address
lines, then it is to address at the most N locations of memory, where 2n=N. However, if out
of N locations only P memory are to be interfaced, then the least significant p address line
out of the available n lines can be directly connected from the microprocessor to the
memory chip while the remaining of n-p higher order address lines may be used for address
decoding. The memory address depends upon the hardware circuit used for decoding the
chip select (CS). The output of the decoding circuit is connected with the CS pin of the
memory chip.
The general procedure for of static memory interfacing with 8086 is as follows
1. Arrange the available memory chips so as to obtain 16-bit data bus width. The
upper 8-bit bank is called ‘odd address memory bank’ and the lower 8-bit bank
is called ‘even address memory bank’.
2. Connect available memory address lines of memory chips with those of the
microprocessor and also connect the memory RD and WR inputs to the
corresponding processor control signals. Connect the 16-bit data bus of the memory
bank with that of the microprocessor 8086.
3. The remaining address lined of the microprocessor, BHE and A0 are used for
decoding the required chip select signals for the odd and even memory banks.
The CS of memory is derived from the O/P of the decoding circuit.
3.3.1 Interfacing I/O ports
I/O ports are the devices through which the microprocessor communicates with other
devices or external data source/destinations.
Steps in interfacing I/O devices:

The following steps are performed to interface a general I/O device with CPU
NOTES
1. Connect the data bus of the microprocessor system with the data bus of I/O port.
2. Derive a device address pulse by decoding the required address of the device and
use it as the chip select of the device.
3. Use a suitable control signal, i.e. IORD and/or IOWR to carry out the device
operations, i.e. connect IORD to RD input of the device if it is an input device,
otherwise connect IOWR to WR input of the device. In some cases the RD or
WR control signals or combined with the device address pulse to generate the
device select pulse.
3.3.2 Methods of interfacing I/O devices
There are two methods of interfacing general I/O devices.
(i) I/O mapped

(ii) Memory mapped
The principal distinction in the two approaches is that I?O mapped interfacings the
devices are viewed as distinct I/O devices and or addressed accordingly While in memory
mapped scheme, the devices are viewed as memory locations and are addressed like
wise. In I/O mapped interfacing, all the available address lines of a microprocessor ay not
be used for interfacing devices. The processor 8086 has 20 address lines. The I/O mapped
scheme may use at the most 16 address lines A0-A15 or even 8 address lines for address
decoding. The unused higher order address lines are logic 0, while addressing the device.
An I/O mapped device requires the use of IN and OUT instructions for accessing them.
The I/O mapped method requires less hardware of decoding, as less number of address
lines are used. In case of 8086, a maximum of 64K input and 64Koutput devices or 32K
input and 32K word output devices can be interfaced. In addition to address and data
bus, to address an input devices, we require the IORD signals and to address an output
device, we use IOWR signal for the respective operation. The IOWR and IORD
signals are used for I/O mapped interfacing.
In memory-mapped interfacing, all the available address lines are used for address
decoding. Thus each memory-mapped I/O devices with 8086 has a 20 bit address, i.e.
8086 can have as many as 1M memory-mapped Input and as many byte output device.
Practically this is impossible, as memory mapped I/O device consume that addresses in
the memory map of the CPU. 1M byte devices will require the complete 1M byte of the
memory map and nothing will be left as program memory. Also the memory locations and
the memory mapped devices cannot have common addresses. The MRDC and MRTC
signals are used for interfacing in memory mapped I/O scheme. All the applicable data
transfer instructions can be used to communicate with memory mapped I/O devices.

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However, I/O operations are much more sluggish compared to the memory operations
NOTES which are faster. Moreover, complex decoding hardware is required in this case since all
address lines are used for decoding. In case of 8086 systems, the memory mapped method
is seldom is used. Hence all the peripheral devices in most of the practical systems are
essentially I/O mapped devices.
3.4 PROGRAMMABLE PERIPHERAL INTERFACE – 8255A
The Intel 8255A is a general purpose programmable I/O device which is designed for
use with all Intel and most other microprocessors. . Its function is that of a general purpose
I/O component to interface peripheral equipment to the microprocessor system bus. It
provides 24 I/O pins which may be individually programmed in 2 groups of 12, each of
these groups contain a subgroup of eight I/O lines called as 8-bit port and another subgroup
of four I/O lines or a 4-bit port. Thus Group A contains 8-bit port A along with a 4-bit port
C upper. The port A lines are identified by symbols PA0 – PA7 while the port C lines are
identified as PC4 - PC7. Similarly, Group B contains an 8-bit port B, containing lines PB0 -
PB7 and a 4-bit port C with lower bits PC0 - PC3. All of these ports can function
independently either as input or as output ports. This can be achieved by programming the
bits of an internal register of 8255 called as control word register (CWR).
The internal block diagram and the pin configuration of 8255A are shown in figure
3.4.1a and 3.4.1b.
Figure 3.4.1a Internal block diagram of 8255A

NOTES
Figure 3.4.1b Pin Configuration of 8255A
3.4.1 8255A Functional Description
Data Bus Buffer
It is 3-state bidirectional 8-bit buffer used to interface the 8255A to the system data bus.
Data is transmitted or received by the buffer upon execution of input or output instructions
by the processor. Control words and status information are also transferred through the
data bus buffer.
Read/Write and Control Logic
The function of this block is to manage all of the internal and external transfers of both
Data and Control or Status words. It accepts inputs from the processor’s address and
control busses and in turn, issues commands to both of the control groups, group A and
group B controls The control word contains information such as “mode”, “bit set”, “bit
reset”, etc., that initializes the functional configuration of the 82C55A. Each of the Control
blocks (Group A and Group B) accepts “commands” from the Read/Write Control Logic,
receives “control words” from the internal data bus and issues the proper commands to its
associated ports.
Control Group A - Port A and Port C upper (PC7 - PC4)
Control Group B - Port B and Port C lower (PC3 - PC0)
The control word register can be both written and read. Figure 3.4.2 shows the control
word format. The modes for Port A and Port B can be separately defined, while Port C is
divided into two portions as required by the Port A and Port B definitions. Modes may be

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combined so that their functional definition can be “tailored” to almost any I/O structure.
NOTES For instance; Group B can be programmed in Mode 0 to monitor simple switch closings
or display computational results, Group A could be programmed in Mode 1 to monitor a
keyboard or tape reader on an interrupt-driven basis.
Ports A, B, and C
The 8255A contains three 8-bit ports (A, B, and C). Port A contains one 8-bit data
output latch/buffer and one 8-bit input latch/buffer. Both “pull-up” and “pull-down” bus
hold devices are present on Port A. In Port B, one 8-bit data input/output latch/buffer and
only “pull-up” bus hold devices is present on Port B.
Port C contains one 8-bit data output latch/buffer and one 8-bit data input buffer (no latch
for input). This port can be divided into two 4-bit ports under the mode control. Each 4-
bit port contains a 4-bit latch and it can be used for the control signal outputs and status
signal inputs in conjunction with ports A and B. Only “pull-up” bus hold devices are present
on Port C.
Figure 3.4.2 Control Word Format for 8255
3.4.2 Modes of operation of 8255
There are two basic modes of operation of 8255, I/O mode and Bit Set-Reset more
(BSR). In I/O mode, the 8255 ports work as programmable I/O ports, while in BSR
mode only port C can be used to set or reset its individual port bits. Under the I/O mode
of operation further there are three modes of operation of 8255, mode 0, mode1 and
mode 2

BSR mode:
NOTES
In this mode, any of the 8-bits of port C can be set or reset depending on D0 of the
control word. The bit to be set or reset is selected by bit select flags D3, D2 and D1 of the
CWR. The CWR format is shown in Figure 3.4.3 .
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
BIT SET / RESET

x x x 1 - SET
0 - RESET
DON'T
CARE
BIT SELECT
0 1 2 3 4 5 6 7
0 10 1 0 10 18
0 0 11 00 118
0 0 0 0 1 1 1 1 8
BIT SET / RESET FLAG

0 - ACTIVE
Figure 3.4.3 BSR mode Control Word Register Format

I/O modes :
(i) Mode 0 (Basic I/O mode):
This mode provides simple input and output capability using each of the three ports.
Data can be simply read from and written to the input and output ports respectively, after
appropriate initialization in the control word.
The salient features of this mode are as listed below:
1. Two 8-bit ports (port A and port B) and two 4-bit ports (port C upper and lower)
are available. The two 4-bit ports can be used as a third 8-bit port.
2. Any port can be used as an input or output port.
3. Output ports are latched. Input ports are not latched.
(ii) Mode 1 (Strobed Input/Output)
This functional configuration provides a means for transferring I/O data to or from a
specified port in conjunction with strobes or “handshaking” signals. In mode 1, Port A and
Port B use the lines on Port C to generate or accept these “handshaking” signals.
Two Groups (Group A and Group B): Each group contains one 8-bit data port and
one 4-bit control/data port. The 8-bit data port can be either input or output both inputs
and outputs are latched. The 4-bit port is used for control and status of the 8-bit data port.

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Input Control Signal Definition: Figure 3.4.4 show the input configuration of mode1
NOTES where port A and port B acts as input ports and figure 3.4.5 shows the timing diagram for
this mode.
STB (Strobe Input). A “low” on this input loads data into the input latch.
IBF (Input Buffer Full) : A “high” on this output indicates that the data has been loaded into
the input latch; in essence, an acknowledgement. IBF is set by STB input being low and is
reset by the rising edge of the RD input.
INTR (Interrupt Request): A “high” on this output can be used to interrupt the CPU when
an input device is requesting service. INTR is set by the STB is a “high”, IBF is a “high”
and INTE is a “high”. It is reset by the falling edge of RD. This procedure allows an input
device to request service from the CPU by simply strobing its data into the port.
INTE A: Controlled by bit set/reset of PC4.
INTE B: Controlled by bit set/reset of PC2.
Figure3.4.4 Mode 1 Group A and B Input
Figure:3.4.5 Timing diagram of Mode 1Strobed data Input

Output Control Signal Definition: Figure 3.4.6 show the output configuration of mode1
where port A and port B acts as output ports and figure 3.4.7 shows the timing diagram for NOTES
this mode.
OBF (Output Buffer Full): The OBF output will go “low” to indicate that the CPU has
written data out to the specified port. The OBF will be set by the rising edge of the WR
input and reset by ACK Input being low.
ACK (Acknowledge Input): A “low” on this input informs the 8255A that the data from
Port A or Port B has been accepted. In essence, a response from the peripheral device
indicating that it has received the data.
INTR (Interrupt Request): A “high” on this output can be used to interrupt the CPU when
an output device has accepted data transmitted by the CPU.
INTR is set when ACK is a “high”, OBF is a “high” and INTE is a “high”. It is reset by the
falling edge of WR.
INTE A: Controlled by bit set/reset of PC6.
INTE B: Controlled by bit set/reset of PC2
Figure3.4.6 Mode 1 Group A and B Output

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NOTES
Figure: 3.4.7 Timing diagram of Mode 1Strobed data output
(iii) MODE 2 (Strobed Bidirectional Bus I/O).
This functional configuration provides a means for communicating with a peripheral

device or structure on a single 8-bit bus for both transmitting and receiving data (bidirectional
bus I/O). “Handshaking” signals are provided to maintain proper bus flow discipline in a
similar manner to MODE 1. Interrupt generation and enable/disable functions are also
available.
Used in Group A only. One 8-bit, bi-directional bus port (Port A) and a 5-bit control port
(Port C). Both inputs and outputs are latched. The 5-bit control port (Port C) is used for
control and status for the 8-bit, bi-directional bus port (Port A). Figure 3.4.5 shows the
mode2 bidirectional data transfer.
Bidirectional Bus I/O Control Signal Definition INTR (Interrupt Request) - A high on this
output can be used to interrupt the CPU for input or output operations.
Figure: 3.4.8 Mode 2 Bidirectional data transfer

NOTES
Q3.4.a What is the purpose of parallel interface device?
Q3.4.b What are the various modes of 8255?
Q3.4c How handshaking signals are used in mode1 and mode2?
3.5 PROGRAMMABLE COMMUNICATION INTERFACE (USART) - 8251
Intel 8251A is a universal synchronous asynchronous receiver and transmitter

compatible with Intel’s processors. This may be programmed to operate in any of the
serial communication modes built into it. This chip converts the parallel data into a serial
stream of bits suitable for serial transmission. It is also able to receive a serial stream of bits
and convert it into parallel data bytes to be read by a microprocessor.
3.5.1 Architecture And Signal Description Of 8251
The architecture block diagram of 8251A is shown in figure 3.5.1. The data bus
buffer interfaces the internal bus of the circuit with the system bus. The read write control
logic controls the operation of the peripheral depending upon the operations imitated by
the CPU. This unit also selects one of the two internal addresses those are control address
and data address based on C/D signal. The modem control unit handles the modem
handshake signals to coordinate the communication between the modem and the USART.
The transmit control unit transmits the data byte received by the data buffer from the CPU
for further serial communication. The receiver control unit converts the received serial data
from the serial devices into parallel data and sends it to the data buffer of the CPU. This
unit also detects a break in the data string while the 8251 is in asynchronous mode.

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NOTES
Transmit
Data Bus
Buffer TXD
Buffer (P-S)
D7-D0
RESET
TXRDY
CLK Transmit
Read/Write TXE
C/D Control
Control TXC
RD
Logic
Internal Bus Line

WR
CS
DSR
Receive
DTR Modem Buffer RXD
CTS Control
(S-P)
RTS
RXRDY
Receive RXC
Control
SYNDET/BD
Figure 3.5.1 Architecture block diagram of 8251A
Figure3.5.2: Pin Configuration of 8251A

The pin configuration of 8251A is shown in figure3.5.2. The following text describes
the signal description pf 8251A. NOTES
D0 to D7 (l/O terminal) - This is bidirectional data bus which receives control words
and transmits data from the CPU and sends status words and received data to CPU.
RESET (Input terminal) - A “High” on this input forces the 8251A into “reset status.”
The device waits for the writing of “mode instruction”.
CLK (Input terminal) - CLK signal is used to generate internal device timing. CLK
signal is independent of RXC or TXC. However, the frequency of CLK must be greater
than 30 times the RXC and TXC at Synchronous mode and Asynchronous “x1” mode,
and must be greater than 5 times at Asynchronous “x16” and “x64” mode.
WR (Input terminal) - This is the “active low” input terminal which receives a signal
for writing the data to be transmitted and control words from the CPU into the 8251A.
RD (Input terminal) - This is the “active low” input terminal which receives a signal for
reading receive data and status words from the 8251A.
C/D (Input terminal) - This is an input terminal which receives a signal for selecting
data or command words and status words when the 8251A is accessed by the CPU.
If C/D = low, data will be accessed.
If C/D = high, command word or status word will be accessed.
CS (Input terminal) - This is the “active low” input terminal which selects the 8251A
at low level when the CPU accesses.
TXD (output terminal) - This is an output terminal for transmitting data from which
serial-converted data is sent out. The device is in “mark status” (high level) after resetting
or during a status when transmit is disabled. It is also possible to set the device in “break
status” (low level) by a command.
TXRDY (output terminal) - This is an output terminal which indicates that the 8251A
is ready to accept a transmitted data character. But the terminal is always at low level if
CTS = high or the device was set in “TX disable status” by a command.
Note: TXRDY status word indicates that transmit data character is receivable,
regardless of CTS. If the CPU writes a data character, TXRDY will be reset by the
leading edge or WR signal.
TXEMPTY (Output terminal) - This is an output terminal which indicates that the
8251A has transmitted all the characters and had no data character.

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In “synchronous mode,” the terminal is at high level, if transmit data characters are no
NOTES longer remaining and sync characters are automatically transmitted. If the CPU writes a
data character, TXEMPTY will be reset by the leading edge of WR signal.
Note: As the transmitter is disabled by setting CTS “High” or command, data written
before disable will be sent out. Then TXD and TXEMPTY will be “High”. Even if a data
is written after disable, that data is not sent out and TXE will be “High”. After the transmitter
is enabled, it sent out.
TXC (Input terminal): This is a clock input signal which determines the transfer speed
of transmitted data. In “synchronous mode,” the baud rate will be the same as the frequency
of TXC. In “asynchronous mode”, it is possible to select the baud rate factor by mode
instruction. It can be 1, 1/16 or 1/64 the TXC. The falling edge of TXC sifts the serial data
out of the 8251A.
RXD (input terminal): This is a terminal which receives serial data.
RXRDY (Output terminal): This is a terminal which indicates that the 8251A contains a
character that is ready to READ. If the CPU reads a data character, RXRDY will be reset
by the leading edge of RD signal. Unless the CPU reads a data character before the next
one is received completely, the preceding data will be lost. In such a case, an overrun
error flag status word will be set.
RXC (Input terminal): This is a clock input signal which determines the transfer speed
of received data. In “synchronous mode,” the baud rate is the same as the frequency of
RXC. In “asynchronous mode,” it is possible to select the baud rate factor by mode
instruction. It can be 1, 1/16, 1/64 the RXC
SYNDET/BD (Input or output terminal): This is a terminal whose function changes

according to mode. In “internal synchronous mode.” this terminal is at high level, if sync
characters are received and synchronized. If a status word is read, the terminal will be
reset.
In “external synchronous mode, “this is an input terminal. A “High” on this input forces
the 8251A to start receiving data characters. In “asynchronous mode,” this is an output
terminal which generates “high level” output upon the detection of a “break” character if
receiver data contains a “low-level” space between the stop bits of two continuous
characters. The terminal will be reset, if RXD is at high level. After Reset is active, the
terminal will be output at low level.
DSR (Input terminal): This is an input port for MODEM interface. The input status of
the terminal can be recognized by the CPU reading status words.

DTR (Output terminal): This is an output port for MODEM interface. It is possible to
set the status of DTR by a command. NOTES
CTS (Input terminal): This is an input terminal for MODEM interface which is used
for controlling a transmit circuit. The terminal controls data transmission if the device is set
in “TX Enable” status by a command. Data is transmittable if the terminal is at low level.
RTS (Output terminal): This is an output port for MODEM interface. It is possible to
set the status RTS by a command.
There are two types of control word.
1. Mode instruction (setting of function)

2. Command (setting of operation)
Mode Instruction
Mode instruction is used for setting the function of the 8251A. Mode instruction will
be in “wait for write” at either internal reset or external reset. That is, the writing of a
control word after resetting will be recognized as a “mode instruction.” Mode Instruction
of 8251 is shown in figure 3.5.3.
Items set by mode instruction are as follows:
 Synchronous/asynchronous mode
 Stop bit length (asynchronous mode)
 Character length
 Parity bit
 Baud rate factor (asynchronous mode)
 Internal/external synchronization (synchronous mode)
 Number of synchronous characters (Synchronous mode)

DMC 1932
NOTES D7
S1
D6
S1
D5
EP
D4
PEN
D3
L2
D2
L1
D1
B2
D0
B1
Baud Rate Factor
0 1 0 1
0 0 1 1
Refer to
Fig. 3 1x 16 x 64 x
SYNC
Charactor Length
0 1 0 1
0 0 1 1
5 bits 6 bits 7 bits 8 bits
Parity Check
0 1 0 1
0 0 1 1
odd Even
Disable parity Disable Parity
Stop bit Length

0 1 0 1
0 0 1 1
Inhabit 1 bit 1.5 bits 2 bits
Figure 3.5.3 Mode Instruction Format of 8251 (Asynchronous)
The bit configuration of mode instruction is shown in Figures 3.5.3 and 3.5.4.
Figure 3.5.4 Mode Instruction Format of 8251 (Synchronous)

In the case of synchronous mode, it is necessary to write one-or two byte sync
characters. If sync characters were written, a function will be set because the writing of NOTES
sync characters constitutes part of mode instruction.
Command
Command is used for setting the operation of the 8251A and the command instruction
format of 8251 is shown in figure 3.5.4. It is possible to write a command whenever
necessary after writing a mode instruction and sync characters. Items to be set by command
are as follows:
 Transmit Enable/Disable
 Receive Enable/Disable
 DTR, RTS Output of data.
 Resetting of error flag.
 Sending to break characters
 Internal resetting
 Hunt mode (synchronous mode)
The bit configuration of a command is shown in Figure 3.5.5

D7 D6 D5 D4 D3 D2 D1 D0
EH IR RTS ER SBRK RXE DTR TXEN
1 ... Transmit Enable

0 ... Disable
DTR
1 DTR = 0
0 DTR = 1
1 ... Recieve Enable

0 ... Disable
1 ... Sent Break Charactor

0 ... Normal Operation
1 ... Reset Error Flag

RTS
1 RTS = 0
0 RTS = 1
1 ... Internal Reset

1 ... Hunt Mode (Note)

Figure 3.5.5 Command Instruction Format of 8251

DMC 1932

NOTES
Q3.5.aWhat is the purpose of serial interface device?
Q3.5.b How synchronous and asynchronous communication is done using 8251?
Q3.5.c What are the differences between mode instructions and command instructions?
Q3.5d How data is converted from parallel to serial and serial to parallel?
3.6 PROGRAMMABLE INTERVAL TIMER/COUNTER - 8254
The Intel 8254 is a high-performance counter/timer which is designed to solve the

timing control problems common in microcomputer system design. It provides three
independent 16-bit counters and all modes are software programmable. Six programmable
timer modes allow the 8254 to be used as an event counter, elapsed time indicator,
programmable one-shot, and in many other applications. The 8254 is available in 24-pin
DIP and 28-pin plastic leaded chip carrier (PLCC) packages.
3.6.1 Functional Description
The 8254 is a programmable interval timer/counter designed for use with Intel
microcomputer systems. The 8254 solves one of the most common problems in any
microcomputer system, the generation of accurate time delays under software control. In-
stead of setting up timing loops in software, the programmer configures the 8254 to match
his requirements and programs one of the counters for the de sired delay. After the desired
delay, the 82C54 will interrupt the CPU. Software overhead is minimal and variable length
delays can easily be accommodated.
Some of the other counter/timer functions common to microcomputers which can be

implemented with the 8254 are:
 Real time clock
 Even counter
 Digital one-shot
 Programmable rate generator
 Square wave generator
 Binary rate multiplier
 Complex waveform generator
 Complex motor controller
The block diagram and the pin configuration of 8254 is shown in figure 3.6.1a and

CLK 0
NOTES
DATA
D1-D0 8 BUS COUNTER
GATE 0
BUFFER 0
OUT 0
INTERNAL BUS
RD
CLK 1
WR READ /
WRITE COUNTER
1 GATE 1
A0 LOGIC
A1 OUT 1
CS
CLK 2
CONTROL
WORD COUNTER
2 GATE 2
REGISTER
OUT 2
Figure 3.6.1a Block Diagram
D7 1 24 Vcc
D6 2 23 WR
D5 3 22 RD
D4 4 21 CS
D3 5 20 A1
D2 6 19 A0
82C54
D1 7 18 CLK 2
D0 8 17 OUT 2
CLK 0 9 16 GATE 2
OUT 0 10 15 CLK 1
GATE 0 11 14
13 GATE 1
GND 12 13 OUT 1
Figure 3.6.1 b Pin Configuration
DATA BUS BUFFER
This 3-state, bi-directional, 8-bit buffer is used to interface the 8254 to the system
bus.

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READ/WRITE LOGIC
NOTES
The Read/Write Logic accepts inputs from the system bus and generates control
signals for the other functional blocks of the 8254. A1 and A0 select one of the three
counters or the Control Word Register to be read from/written into. A “low” on the RD
input tells the 8254 that the CPU is reading one of the counters. A “low” on the WR input
tells the 8254 that the CPU is writing either a Control Word or an initial count. Both RD
and WR are qualified by CS; RD and WR are ignored unless the 8254 has been selected
by holding CS low.
COUNTER 0, COUNTER 1, COUNTER 2
These three functional blocks are identical in operation, so only a single counter will
be described. The internal block diagram of a single counter is shown in Figure 3.6.2.
INTERNAL BUS
CONTROL STATUS
WORD LATCH
REGISTER
CRM CRL
STATUS
REGISTER
CONTROL CE
LOAD
OLM OLL
GATE n
CLX n OUT n
Figure 3.6.2 Internal block diagram of a counter
The counters are fully independent. Each counter may operate in a different Mode.
The Control Word Register is shown in the figure3.6.3; it is not part of the counter itself,
but its contents determine how the counter operates.
The status register, when latched, contains the current contents of the Control Word
Register and status of the output and null count flag. The actual counter is labeled CE (for
“Counting Element”). It is a 16-bit pre-settable synchronous down counter.
OLM and OLL are two 8-bit latches. OL stands for “Output Latch”; the subscripts
M and L stand for “Most significant byte” and “Least significant byte” respectively. Both
are normally referred to as one unit and called just OL. These latches normally “follow” the
CE, but if a suitable Counter Latch Command is sent to the 8254, the latches “latch” the
present count until read by the CPU and then return to “following” the CE. One latch at a

time is enabled by the counter’s Control Logic to drive the internal bus. This is how the 16-
bit Counter communicates over the 8-bit internal bus. Note that the CE itself cannot be NOTES
read; whenever you read the count, it is the OL that is being read.
Similarly, there are two 8-bit registers called CRM and CRL (for “Count Register”).
Both are normally referred to as one unit and called just CR. When a new count is written
to the Counter, the count is stored in the CR and later transferred to the CE. The Control
Logic allows one register at a time to be loaded from the internal bus. Both bytes are
transferred to the CE simultaneously. CRM and CRL are cleared when the Counter is
programmed. In this way, if the Counter has been programmed for one byte counts (either
most significant byte only or least significant byte only) the other byte will be zero.
Note that the CE cannot be written into; whenever a count is written, it is written into
the CR. The Control Logic is also shown in the diagram. CLK n, GATE n, and OUT n are
all connected to the outside world through the Control Logic.
OPERATIONAL DESCRIPTION
After power-up, the state of the 8254 is undefined. The Mode, count value, and
output of all Counters are undefined. How each Counter operates is determined when it is
programmed. Each Counter must be programmed before it can be used. Unused counters
need not be programmed.
3.6.2 PROGRAMMING THE 8254
Counters are programmed by writing a Control Word and then an initial count. The
control word format is shown in Figure 3.6.3. All Control Words are written into the
Control Word Register, which is selected when A1, A0 = 11. The Control Word itself
specifies which Counter is being programmed. By contrast, initial counts are written into
the Counters, not the Control Word Register. The A1, A0 inputs are used to select the
Counter to be written into. The format of the initial count is determined by the Control
Word used.

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Control Word Format

NOTES A 1 , A 0  11; CS  0; RD  1 WR  0
D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 RW1 RW0 M2 M1 M0 BCD
Sc-Select Counter: M-MODE:

SC1 SC0 M2 M1 M0
0 0 Select Counter 0
0 0 0 Mode 0
0 1 Select Counter 1
1 0 Select Counter 1 0 0 1 Mode 1
1 1 Read-Back Command X 0 Mode 2
(See Read Operations)
X 1 1 Mode 3
1 0 0 Mode 4
1 0 1 Mode 5
RW-Read/Write:
RW1 RW0
0 0 Counter latch Command (See BCD:
Read Operations)
0 1 Read/write least significant byte only 0 Binary counter 16
bits
1 0 Read /write most significant byte only 1 Binary coded
decimal (BCD)
Counter (4 decades)
1 1 Read/write least significant byte first,
then most significant byte
Figure 3.6.3 Control Word Format
Write Operations
The programming procedure for the 8254 is very flexible. Only two conventions need to
be remembered:
1) For each Counter, the Control Word must be written before the initial count is
written.
2) The initial count must follow the count format specified in the Control Word (least
significant byte only, most significant byte only, or least significant byte and then
most significant byte).
Since the Control Word Register and the three Counters have separate addresses
(selected by the A1, A0 inputs), and each Control Word specifies the Counter it applies to
(SC0, SC1 bits), no special instruction sequence is required.
Read Operations
It is often desirable to read the value of a Counter without disturbing the count in
progress. This is easily done in the 8254. There are three possible methods for reading the
counters: a simple read operation, the Counter Latch Command, and the Read-Back
Command.

The first method is to perform a simple read operation. To read the Counter, which is
selected with the A1, A0 inputs, the CLK input of the selected Counter must be inhibited NOTES
by using either the GATE input or external logic. Other-wise, the count may be in the
process of changing when it is read, giving an undefined result.
COUNTER LATCH COMMAND
The second method uses the “Counter Latch Command” that is shown in figure 3.6.4.
Like a Control Word, this command is written to the Control Word Register, which is
selected when A1,A0 = 11. Also like a Control Word, the SC0, SC1 bits select one of the
three Counters, but two other bits, D5 and D4, distinguish this command from a Control
Word.
A1 , A 0  11; CS  0; RD  1 WR  0
D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 0 0 X X X X
SC1, SC0- specify counter to be latched
SC1 SC0 Counter
0 0 0
0 1 1
1 0 2
1 1 Read-Back Command
D5, D4-00 designates Counter Latch Command
X-don’t care
Note:
Don’t care bits (X) should be 0 to insure compatibility
With future Intel products
Figure 3.6.4. Counter Latching Command Format
The selected Counter’s output latch (OL) latches the count at the time the Counter
Latch Command is received. This count is held in the latch until it is read by the CPU (or
until the Counter is reprogrammed). The count is then unlatched automatically and the OL
returns to “following” the counting element (CE). This allows reading the contents of the
Counters “on the fly” without affecting counting in progress. Multiple Counter Latch
Commands may be used to latch more than one Counter. Each latched Counter’s OL
holds its count until it is read. Counter Latch Commands do not affect the programmed
Mode of the Counter in any way.

DMC 1932
If a Counter is latched and then, some time later, latched again before the count is
NOTES read, the second Counter Latch Command is ignored. The count read will be the count at
the time the first Counter Latch Command was issued. With either method, the count must
be read according to the programmed format; specifically, if the Counter is programmed
for two byte counts, two bytes must be read. The two bytes do not have to be read one
right after the other; read or write or programming operations of other Counters may be
inserted between them.
READ-BACK COMMAND
The third method uses the Read-Back command, the format is shown in figure 3.6.5.
This command allows the user to check the count value, programmed Mode, and current
state of the OUT pin and Null Count flag of the selected counter(s).
The command is written into the Control Word Register. The command applies to the
counters selected by setting their corresponding bits D3,D2,D1 = 1.
A0, A1  11 CS  0 RD  1 WR  0
D7 D6 D5 D4 D3 D2 D1 D0
1 1 CNT 2 CNT 1 CNT 0 0
COUNT STATUS
D5 : 0 = Latch count of selected counter (s)

D4 : 0 = Latch status of selected counter (s)
D3 : 1 = Select counter 2
D2 : 1 = Selector counter 1
D1 : 1 = Selector counter 0
D0 : Reserved for future expansion; must be 0
Figure 3.6.5 Read Back Command
The read-back command may be used to latch multiple counter output latches (OL)
by setting the COUNT bit D5=0 and selecting the desired counter(s). This single command
is functionally equivalent to several counter latch commands, one for each counter latched.
Each counter’s latched count is held until it is read (or the counter is reprogrammed). That
counter is automatically unlatched when read, but other counters remain latched until they
are read. If multiple count read-back commands are issued to the same counter without
reading the count, all but the first are ignored; i.e., the count which will be read is the count
at the time the first read-back command was issued.
The read-back command may also be used to latch status information of selected
counter(s) by setting STATUS bit D4=0. Status must be latched to be read; status of a
counter is accessed by a read from that counter. The status byte is shown in figure 3.6.6.
The counter status format is shown in Figure. Bits D5 through D0 contain the counter’s
programmed Mode exactly as written in the last Mode Control Word. OUTPUT bit D7

contains the current state of the OUT pin. This allows the user to monitor the counter’s
output via software, possibly eliminating some hardware from a system. NOTES
D7 D6 D5 D4 D3 D2 D1 D0
NULL
OUTPUT RW1 RW0 M2 M1 M0 BCD
COUNT
D7 1 = Out Pin is 1
0= Out Pin is 0
D6 : 1 = Null count
0= Count available for reading
D5-D0 Counter Programmed Mode (See Figure 7)
Figure 3.6.6. Status Byte
NULL COUNT bit D6 indicates when the last count written to the counter register
(CR) has been loaded into the counting element (CE). The exact time this happens depends
on the Mode of the counter and is described in the Mode Definitions, but until the count is
loaded into the counting element (CE), it can’t be read from the counter. If the count is
latched or read before this time, the count value will not reflect the new count just written.
Mode Definitions
The following are defined for use in describing the operation of the 82C54.
CLK PULSE: a rising edge, then a falling edge, in that order, of a Counter’s CLK input.
TRIGGER: a rising edge of a Counter’s GATE input.
COUNTER LOADING: the transfer of a count from the CR to the CE
MODE 0: INTERRUPT ON TERMINAL COUNT
Mode 0 is typically used for event counting. After the Control Word is written, OUT is
initially low, and will remain low until the Counter reaches zero. OUT then goes high and
remains high until a new count or a new Mode 0 Control Word is written into the Counter.
The timing diagram of mode 0 is shown in figure 3.6.7.

DMC 1932
NOTES WR
CW-10 LSB=4
CLK
GATE
OUT
0 0 0 0 0 FF FF
N N N N
4 3 2 1 0 FF FF
CW-10 LSB=3
WR
CLK
GATE
OUT
0 0 0 0 0 0 FF
N N N N
3 2 2 2 1 0 FF
CW-10 LSB=3 LSB=2
WR
CLK
GATE
OUT
0 0 0 0 0 0 FF
N N N N
3 2 1 2 1 0 FF
Figure : 3.6.7 Mode 0
GATE = 1 enables counting; GATE = 0 disables counting. GATE has no effect on

OUT.
After the Control Word and initial count are written to a Counter, the initial count will be
loaded on the next CLK pulse. This CLK pulse does not decrement the count, so for an
initial count of N, OUT does not go high until N + 1 CLK pulses after the initial count is
written. If a new count is written to the Counter, it will be loaded on the next CLK pulse
and counting will continue from the new count. If a two-byte count is written, the following
happens:
1) Writing the first byte does not disable counting. OUT is set low immediately (no
clock pulse required).
2) Writing the second byte allows the new count to be loaded on the next CLK pulse.
3) When there is a count in progress, writing a new LSB before the counter has
counted down to 0 and rolled over to FFFFh, WILL stop the counter. However,
if the LSB is loaded AFTER the counter has rolled over to FFFFh, so that an
MSB now exists in the counter, then the counter WILL NOT stop.
This allows the counting sequence to be synchronized by software. Again, OUT does
not go high until N + 1 CLK pulses after the new count of N is written. NOTES
If an initial count is written while GATE = 0, it will still be loaded on the next CLK
pulse. When GATE goes high, OUT will go high N CLK pulses later; no CLK pulse is
needed to load the Counter as this has already been done.
NOTE: The following conventions apply to all mode timing diagrams:
1. Counters are programmed for binary (not BCD) counting and for Reading/Writing
least significant byte (LSB) only.
2. The counter is always selected (CS always low).
3. CW stands for “Control Word”; CW e 10 means a control word of 10, hex is
written to the counter.
4. LSB stands for “Least Significant Byte” of count.
5. Numbers below diagrams are count values.
6. The lower number is the least significant byte. The upper number is the most
significant byte. Since the counter is programmed to Read/Write LSB only, the
most significant byte cannot be read. N stands for an undefined count. Vertical
lines show transitions between count values.
MODE 1: HARDWARE RETRIGGERABLE ONE-SHOT
OUT will be initially high. OUT will go low on the CLK pulse following a trigger to
begin the one-shot pulse, and will remain low until the Counter reaches zero. OUT will
then go high and remain high until the CLK pulse after the next trigger. The timing diagram
of mode 1 is shown in figure 3.6.8.
After writing the Control Word and initial count, the Counter is armed. A trigger
results in loading the Counter and setting OUT low on the next CLK pulse, thus starting
the one-shot pulse. An initial count of N will result in a one-shot pulse N CLK cycles in
duration. The one-shot is re-triggerable, hence OUT will remain low for N CLK pulses
after any trigger. The one-shot pulse can be repeated without rewriting the same count into
the counter. GATE has no effect on OUT.
If a new count is written to the Counter during a one- shot pulse, the current one-shot
is not affected unless the Counter is retriggered. In that case, the Counter is loaded with
the new count and the one-shot pulse continues until the new count expires.

DMC 1932
NOTES WR
CW=12 LSB=3
CLK
GATE
OUT
0 0 0 0 FF 0 0
N N N N N
3 2 1 0 FF 3 2
CW=12 LSB=3
WR
CLK
GATE
OUT
0 0 0 0 0 0 0
N N N N N
3 2 1 3 2 1 0
CW=12 LSB=2 LSB=4
WR
CLK
GATE
OUT
0 0 0 FF FF 0 0
N N N N N
2 1 0 FF FF 4 3
Figure 3.6.8 Mode 1
MODE 2: RATE GENERATOR

This Mode functions like a divide-by-N counter. It is typically used to generate a
Real Time Clock interrupt. OUT will initially be high. When the initial count has decremented
to 1, OUT goes low for one CLK pulse. OUT then goes high again, the Counter reloads
the initial count and the process is repeated. The timing diagram of mode 2 is shown in
figure 3.6.9.
Mode 2 is periodic; the same sequence is repeated indefinitely. For an initial count of
N, the sequence repeats every N CLK cycles. GATE = 1 enables counting; GATE = 0

disables counting. If GATE goes low during an output pulse, OUT is set high immediately.
A trigger reloads the Counter with the initial count on the next CLK pulse; OUT goes low NOTES
N CLK pulses after the trigger. Thus the GATE input can be used to synchronize the
Counter.
After writing a Control Word and initial count, the Counter will be loaded on the next
CLK pulse. OUT goes low N CLK Pulses after the initial count is written. This allows the
Counter to be synchronized by software also.
Writing a new count while counting does not affect the current counting sequence. If
a trigger is received after writing a new count but before the end of the current period, the
Counter will be loaded with the new count on the next CLK pulse and counting will continue
from the new count. Otherwise, the new count will be loaded at the end of the current
counting cycle. In mode 2, a COUNT of 1 is illegal.
CW-14 LSB=3
WR
CLK
GATE
OUT
0 0 0 0 0 0 0
N N N N
3 2 1 3 2 1 3
CW-14 LSB=3
WR
CLK
GATE
OUT
0 0 0 0 0 0 0
N N N N
3 2 2 3 2 1 3
CW-14 LSB=4 LSB=5

WR
CLK
GATE
OUT
0 0 0 0 0 0 0
N N N N
4 3 2 1 5 4 3
Figure 3.6.9 Mode 2
MODE 3: SQUARE WAVE MODE
Mode 3 is typically used for Baud rate generation. Mode 3 is similar to Mode 2
except for the duty cycle of OUT. OUT will initially be high. When half the initial count has
expired, OUT goes low for the remainder of the count. Mode 3 is periodic; the sequence
above is repeated indefinitely. An initial count of N results in a square wave with a period
of N CLK cycles. The timing diagram of mode 3 is shown in figure 3.6.10.

DMC 1932
GATE = 1 enables counting; GATE e 0 disables counting. If GATE goes low while
NOTES OUT is low, OUT is set high immediately; no CLK pulse is required. A trigger reloads the
Counter with the initial count on the next CLK pulse. Thus the GATE input can be used to
synchronize the Counter.
CLK pulse. This allows the Counter to be synchronized by software also. Writing a new
count while counting does not affect the current counting sequence. If a trigger is received
after writing a new count but before the end of the current half-cycle of the square wave,
the Counter will be loaded with the new count on the next CLK pulse and counting will
continue from the new count. Otherwise, the new count will be loaded at the end of the
current half-cycle.
Mode 3 is implemented as follows:
Even counts: OUT is initially high. The initial count is loaded on one CLK pulse and
then is decremented by two on succeeding CLK pulses. When the count expires OUT
changes value and the Counter is reloaded with the initial count. The above process is
repeated indefinitely.
Odd counts: OUT is initially high. The initial count minus one (an even number) is
loaded on one CLK pulse and then is decremented by two on succeeding CLK pulses.
One CLK pulse after the count expires, OUT goes low and the Counter is reloaded with
the initial count minus one. Succeeding CLK pulses decrement the count by two. When
the count expires, OUT goes high again and the Counter is reloaded with the initial count
minus one. The above process is repeated indefinitely. So for odd counts, OUT will be
high for (N + 1)/2 counts and low for (N -1)/2 counts.

CW=16 LSB=4
WR NOTES
CLK
GATE
OUT
0 0 0 0 0 0 0 0 0 0
N N N N
4 2 4 2 4 2 4 2 4 2
CW=16 LSB=5
WR
CLK
GATE
OUT
0 0 0 0 0 0 0 0 0 0
N N N N
4 2 0 4 2 4 2 0 4 2
CW=16 LSB=4
WR
CLK
GATE
OUT
0 0 0 0 0 0 0 0 0 0
N N N N
4 2 4 2 2 2 4 2 4 2
Figure 3.6.10 Mode 3

MODE 4: SOFTWARE TRIGGERED STROBE
OUT will be initially high. When the initial count expires, OUT will go low for one
CLK pulse and then go high again. The counting sequence is “triggered” by writing the
initial count. GATE = 1 enables counting; GATE = 0 disables counting. GATE has no effect
on OUT. The timing diagram of mode 4 is shown in figure 3.6.11.
CLK pulse. This CLK pulse does not decrement the count, so for an initial count of N,
OUT does not strobe low until N + 1 CLK pulses after the initial count is written.
If a new count is written during counting, it will be loaded on the next CLK pulse and
counting will continue from the new count. If a two-byte count is written, the following
happens:
1) Writing the first byte has no effect on counting.

2) Writing the second byte allows the new count to be loaded on the next CLK
pulse.

DMC 1932
This allows the sequence to be “retriggered” by software. OUT strobes low Na1
NOTES CLK pulses after the new count of N is written.
CW=18 LSB=3
WR
CLK
GATE
OUT
0 0 0 0 FF FF FF
N N N N
3 2 1 0 FF FF F0
CW=18 LSB=3
WR
CLK
GATE
OUT
0 0 0 0 0 0 FF
N N N N
3 3 3 2 1 0 FF
LSB=3 LSB=2
WR
CLK
GATE
OUT
0 0 0 0 0 0 FF
N N N N
3 2 1 2 1 0 FF
MODE 5: HARDWARE TRIGGERED STROBE (RETRIGGERABLE)
OUT will initially be high. Counting is triggered by a rising edge of GATE. When the
initial count has expired, OUT will go low for one CLK pulse and then go high again. The
timing diagram of mode 5 is shown in figure 3.6.12.
After writing the Control Word and initial count, the counter will not be loaded until
the CLK pulse after a trigger. This CLK pulse does not decrement the count, so for an
initial count of N, OUT does not strobe low until Na1 CLK pulses after a trigger. A trigger

results in the Counter being loaded with the initial count on the next CLK pulse. The
counting sequence is retriggerable. OUT will not strobe low for N a 1 CLK pulses after NOTES
any trigger. GATE has no effect on OUT.
If a new count is written during counting, the current counting sequence will not be
affected. If a trigger occurs after the new count is written but before the current count
expires, the Counter will be loaded with the new count on the next CLK pulse and counting
will continue from there.
CW=18 LSB=3
WR
CLK
GATE
OUT
0 0 0 0 FF FF FF
N N N N N FF FF F0
3 2 1 0
CW=18 LSB=3
WR
CLK
GATE
OUT
0 0 0 0 0 0 FF
N N N N
3 3 3 2 1 0 FF
CW=18 LSB=3 LSB=2

WR
CLK
GATE
OUT
0 0 0 0 0 0 FF
N N N N
3 2 1 2 1 0 FF

DMC 1932

NOTES Q3.6.a List some applications of timer chip?
Q3.6.b How a counter works?
Q3.6.c How the counter values can be read?
Q3.6d What are the various modes of 8254 timer?
3.7 PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE - 8279
The Intel 8279 is a general purpose programmable keyboard and display I/O interface
device designed for use with Intel® microprocessors. The keyboard portion can provide
a scanned interface to a 64-contact key matrix. The keyboard portion will also interface to an
array of sensors or a strobed interface keyboard, such as the hall effect and ferrite variety. Key
depressions can be 2-key lockout or N-key rollover. Keyboard entries are debounced and
strobed in an 8-character FIFO. If more than 8 characters are entered, overrun status is
set. Key entries set the interrupt output line to the CPU.
The display portion provides a scanned display interface for LED, incandescent,
and other popular display technologies. Both numeric and alphanumeric segment displays
may be used as well as simple indicators. The 8279 has 16x8 display RAM which can be
organized into dual 16x4. The RAM can be loaded or interrogated by the CPU. Both right
entry, calculator and left entry typewriter display formats are possible. Both read and write
of the display RAM can be done with auto-increment of the display RAM address.
3.7.1 Hardware Description
The 8279 is packaged in a 40 pin DIP as shown in figure 3.7.1.
RL2 1 40 Vcc
RL3 2 39 RL1
CLK 3 38 RL0
IRO 4 37 CNTL/STB
RL4 5 36 SHIFT
RL5 6 35 SL3
RL6 7 34 SL2
RL7 8 33 SL1
RESET 9 32 SL0
8279
AD 10 31 OUT B0
WR 11 30 OUT B1
DB0 12 29 OUT B2
DB1 13 28 OUT B3
DB2 14 27 OUT A0
DB3 15 26 OUT A1
DB4 16 25 OUT A2
DB5 17 24 OUT A3
DB6 18 23 BD
DB7 19 22 CS
Vss 20 21 A0
Figure 3.7.1 Pin Configuration of 8279

The table is the functional description of each pin.
NOTES
Table 3.7.1 Functional description of each pin of 8279
Symbol Pin Name and Function
No.
DB0-DB7 19-12 BI-DIRECTIONAL DATA BUS: All data and
commands between the CPU and the 8279 are transmitted
on these lines.
CLK 3 CLOCK: Clock from system used to generate internal
timing.
RESET 9 RESET: A high signal on this pin resets the 8279. After
being reset the 8279 is placed in the following mode: 1)16
8-bit character display—left entry. 2) Encoded scan
keyboard—2 key lockout. Along with this the program
clock prescaler is set to 31.
CS 22 CHIP SELECT: A low on this pin enables the interface
functions to receive or transmit.
Ao 21 BUFFER ADDRESS: A high on this line indicates the
signals in or out are interpreted as a command or status. A
low indicates that they are data.
RD.WR 10-11 INPUT/OUTPUT READ AND WRITE: These signals
enable the data buffers to either send data to the external
bus or receive it from the external bus.
IRQ 4 INTERRUPT REQUEST: In a keyboard mode, the
interrupt line is high when there is data in the FIFO/Sensor
RAM. The interrupt line goes low with each FIFO/Sensor
RAM read and returns high if there is still information in
the RAM. In a sensor mode, the interrupt line goes high
whenever a change in a sensor is detected.
Vss, Vcc 20,40 GROUND AND POWER SUPPLY PINS.
SL0-SL3 32-35 SCAN LINES: Scan lines which are used to scan the key
switch or sensor matrix and the display digits. These lines
can be either encoded (1 of 16) or decoded (1 of 4).
RL0-RL7 38, 39, RETURN LINE: Return line inputs which are connected
1,2,5- to the scan lines through the keys or sensor switches. They
8 have active internal pullups to keep them high until a
switch closure pulls one low. They also serve as an 8-bit
input in the Strobed Input mode.
SHIFT 36 SHIFT: The shift input status is stored along with the key
position on key closure in the Scanned Keyboard modes. It
has an active internal pullup to keep it high until a switch
closure pulls it low.

DMC 1932
NOTES CNTL/STB 37 CONTROL/STROBED INPUT MODE: For keyboard

modes this line is used as a control input and stored like
status on a key closure. The line is also the strobe line that
enters the data into the FIFO in the Strobed Input mode.
(Rising Edge). It has an active internal pullup to keep it
high until a switch closure pulls it low.
OUT AQ- 27-24 OUTPUTS: These two ports are the outputs for the 16 x
OUT A3 31-28 4 display refresh registers. The data from these outputs is
OUT Bo- synchronized to the scan lines (SLo-SL3) for multiplexed
OUT B3 digit displays. The two 4 bit ports may be blanked
independently. These two ports may also be considered as
one 8-bit port.
BD 23 BLANK DISPLAY: This output is used to blank the
display during digit switching or by a display blanking
command.
Since data input and display are an integral part of many microprocessor designs,
the system designer needs an interface that can control these functions without placing a
large load on the CPU. The 8279 provides this function for 8-bit microprocessors.
The 8279 has two sections: keyboard and display. The keyboard section can
interface to regular typewriter style keyboards or random toggle or thumb switches.
The display section drives alphanumeric displays or a bank of indicator lights. Thus the
CPU is relieved from scanning the keyboard or refreshing the display.
The 8279 is designed to directly connect to the microprocessor bus. The CPU can
program all operating modes for the 8279. These modes include:
Input Modes
 Scanned Keyboard—with encoded (8x8 key keyboard) or decoded (4x8 key
keyboard) scan lines. A key depression generates a 6-bit encod-ing of key position.
Position and shift and control status are stored in the FIFO. Keys are automatically
debounced with 2-key lockout or N-key rollover.
 Scanned Sensor Matrix—with encoded (8x8 matrix switches) or decoded (4x8
matrix switches) scan lines. Key status (open or closed) stored in RAM addressable
by CPU.
 Strobed Input—Data on return lines during control line strobe is transferred
to FIFO.
Output Modes
 8 or 16 character multiplexed displays that can be organized as dual 4-bit or single

8-bit

 Right entry or left entry display formats.
 Other features of the 8279 include:
NOTES
 Mode programming from the CPU.
 Clock Prescaler
 Interrupt output to signal CPU when there is keyboard or sensor data available.
 An 8 byte FIFO to store keyboard information.
 16 byte internal Display RAM for display refresh. This RAM can also be read
by the CPU.
3.7.3 Principles Of Operation
The following is a description of the major elements of the 8279 programmable

keyboard/display interface device. The block diagram of 8279 is shown in figure3.7.2
KEYBOARD CNTL / STB
DEBOUNCE
AND RETURN
SHIFT
IRQ FiFO/SENSOR RAM
CONTROL RL0~RL7
STATUS
CIRCUIT
8
8X8
A0 FIFO /
SENSOR SCAN
CS I/O RAM
SL0-3
COUNTER
RD CONTROL 4
INTERNALBUS
WR
TIMING
CONTROL AND
TIMING CONTROL
DB0-7 DATA BUS REGISTERS BD
CIRCUIT
BUFFER
RESET
CLK
16 X 8 OUTB0-3
DISPLAY DISPLAY
RAM COUNTER OUTA0-3
8
DISPLAY
ADDRESS
REGISTERS
Figure3.7.2 Block Diagram of 8279
3.7.3.1 I/O Control and Data Buffers
The I/O control section uses the CS, Ao, RD and WR lines to control data flow to
and from the various internal registers and buffers. A0 is one means the information is a
command or status. A0 logic is zero means the information is data. RD and WR determine
the direction of data flow through the Data Buffers. The Data Buffers are bi-directional
buffers that connect the internal bus to the external bus.

DMC 1932
3.7.3.2 Control and Timing Registers and Timing Control

NOTES
These registers store the keyboard and display modes and other operating conditions
programmed by the CPU. The modes are programmed by presenting the proper
command ^n_the data lines with Ao = 1 and then sending a WR. The command is latched
on the rising edge of WR. The command is then decoded and the appropriate function is
set. The timing control contains the basic timing counter chain. The first counter is a + N
prescaler that can be programmed to yield an internal frequency of 100 kHz which gives a
5.1 ms keyboard scan time and a 10.3 ms debounce time. The other counters divide
down the basic internal frequency to provide the proper key scan, row scan, keyboard
matrix scan, and display scan times.
3.7.3.3 Scan Counter
The scan counter has two modes. In the encoded mode, the counter provides a
binary count that must be externally decoded to provide the scan lines for the keyboard
and display. In the decoded mode, the scan counter decodes the least significant 2 bits and
provides a decoded 1 of 4 scan. Note that when the keyboard is in decoded scan, so is
the display. This means that only the first 4 characters in the Display RAM are displayed.
In the encoded mode, the scan lines are active high outputs. In the decoded mode, the
scan lines are active low outputs.
3.7.3.4 Return Buffers and Keyboard Debounce and Control
The 8 return lines are buffered and latched by the Return Buffers. In the keyboard
mode, these lines are scanned, looking for key closures in that row. If the debounce circuit
detects a closed switch, it waits about 10 ms to check if the switch remains closed. If it does,
the address of the switch in the matrix plus the status of SHIFT and CONTROL are
transferred to the FIFO. In the scanned Sensor Matrix modes, the contents of the return
lines is directly transferred to the corresponding row of the Sensor RAM (FIFO) each key scan
time. In Strobed Input mode, the contents of the return lines are transferred to the FIFO
on the rising edge of the CNTL/STB line pulse.
3.7.3.5 FIFO/Sensor RAM and Status
This block is a dual function 8x8 RAM. In Keyboard or Strobed Input modes, it is a
FIFO. Each new entry is written into successive RAM positions and each is then read in order
of entry. FIFO status keeps track of the number of characters in the FIFO and whether it is
full or empty. Too many reads or writes will be recognized as an error. The status can
be read by an RD with CS low and Ao high. The status logic also provides an IRQ signal when
the FIFO is not empty. In Scanned Sensor Matrix mode, the memory is a Sensor RAM.
Each row of the Sensor RAM is loaded with the status of the corresponding row of sensor in
the sensor matrix. In this mode, IRQ is high if a change in a sensor is detected.

3.7.3.6. Display Address Registers and Display RAM
NOTES
The Display Address Registers hold the address of the word currently being written
or read by the CPU and the two 4-bit nibbles being displayed. The read/ write addresses
are programmed by CPU command. They also can be set to auto increment after each
read or write. The Display RAM can be directly read by the CPU after the correct mode
and address is set. The addresses for the A and B nibbles are automatically updated by the
8279 to match data entry by the CPU. The A and B nibbles can be entered
independently or as one word, according to the mode that is set by the CPU. Data
entry to the display can be set to either left or right entry.
3.7.4 Software Operation
8279 Commands
The following commands program the 8279 operating modes. The commands are
sent on the Data Bus with CS low and Ao high and are loaded to the 8279 on the rising edge
of WR.
Keyboard/Display Mode Set

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 D D K K K
Display Mode
0 0 8 x 8 bit character display-Left entry 0 0 0 Encoded scan keyboard-2-key Lockout
0 1 16 x 8 bit character display-Left entry 0 0 1 Decoded scan keyboard-2-key Lockout
1 1 8 x 8 bit character display-Right entry 0 1 0 Encoded scan Keyboard-N-key Rollover
16 x 8 bit character display-Right entry Decoded scan keyboard-N-Key

1 1 0 1 1
Rollover
1 0 0 Encoded scan Sensor Matrix
Default after Reset
1 0 1 Decoded scan Sensor Matrix
1 1 0 Strobed Input, Encoded Display Scan
1 1 1 Strobed Input, Decoded Display Scan
Program Clock
0 0 1 P P P P P
All timing and multiplexing signals for the 8279 are generated by an internal prescaler.
This prescaler divides the external clock (pin 3) by a programmable integer. Bits PPPPP
determine the value of this integer which ranges from 2 to 31. Choosing a divisor that
yields 100 kHz will give the specified scan and debounce times. For instance, if Pin 3 of

DMC 1932
the 8279 is being clocked by a 2 MHz signal, PPPPP should be set to 10100 to divide the
NOTES clock by 20 to yield the proper 100 kHz operating frequency.
Read FIFO/Sensor RAM

0 1 0 AI X A A A
The CPU sets the 8279 for a read of the FIFO/Sensor RAM by first writing this
command. In the Scan Keyboard Mode, the Auto-Increment flag (Al) and the RAM
address bits (AAA) are irrelevant. The 8279 will automatically drive the data bus for each
subsequent read (Ao = 0) in the same sequence in which the data first entered the FIFO.
All subsequent reads will be from the FIFO until another command is issued.
In the Sensor Matrix Mode, the RAM address bits AAA select one of the 8 rows
of the Sensor RAM. If the Al flag is set (Al = 1), each successive read will be from the
subsequent row of the sensor RAM.
Read Display RAM

0 1 1 Al A A A A
The CPU sets up the 8279 for a read of the Display RAM by first writing this command.
The address bits AAAAselect one of the 16 rows of the Display RAM. If the Al flag is set (A1
= 1), this row address will be incremented after each following read or write to the Display
RAM. Since the same counter is used for both reading and writing, this command sets
the next read or write address and the sense of the Auto-Increment mode for both
operations.
Write Display RAM

1 0 0 Al A A A A
The CPU sets up the 8279 for a write to the Display RAM by first writing this command.
After writing the command with Ao = 1, all subsequent writes with AQ = 0 will be to the
Display RAM. The addressing and Auto-Increment functions are identical to those for
the Read Display RAM. However, this command does not affect the source of
subsequent Data Reads; the CPU will read from whichever RAM (Display of FIFO/
Sensor) which was last specified. If, indeed, the Display RAM was last specified, the
Write Display RAM will, nevertheless, change the next Read location.

Display Write Inhibit/Blanking
NOTES
1 0 1 X IWA IWB BLA BLB
The IW Bits can be used to mask nibble A and nibble B in applications requiring
separate 4-bit display ports. By setting the IW flag (IW = 1) for one of the ports, the
port becomes marked so that entries to the Display RAM from the CPU do not affect
that port. Thus, if each nibble is input to a BCD decoder, the CPU may write a digit to the
Display RAM without affecting the other digit being displayed. It is important to note
that bit Bo corresponds to bit Do on the CPU bus, and that bit A3 corresponds to bit D7.
If the user wishes to blank the display, the BL flags are available for each nibble. The
last Clear command issued determines the code to be used as a “blank.” This code
defaults to all zeros after a reset. Note that both BL flags must be set to blank a display
formatted with a single 8-bit port.
Clear

1 1 0 CD CD CD CF CA
The CD bits are available in this command to clear all rows of the Display RAM to
a selectable blanking code as follows:
During the time the Display RAM is being cleared (~ 160 /us), it may not be written
to. The most significant bit of the FIFO status word is set during this time. When the
Display RAM becomes available again, it automatically resets.
If the CF bit is asserted (CF = 1), the FIFO status is cleared and the interrupt output
line is reset. Also, the Sensor RAM pointer is set to row 0.
CA, the Clear All bit, has the combined effect of CD and CF; it uses the CD clearing
code on the Display RAM and also clears FIFO status. Furthermore, it resynchronizes
the internal timing chain.

DMC 1932
End Interrupt/Error Mode Set

NOTES DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 1 1 E X X X X
For the sensor matrix modes this command lowers the IRQ line and enables
further writing into RAM. (The IRQ line would have been raised upon the detection of
a change in a sensor value. This would have also inhibited further writing into the RAM
until reset).
For the N-key rollover mode—if the E bit is pro-grammed to “1” the chip will
operate in the special Error mode.
Status Word
X: don’t care
DU S/E 0 U F N N N
Number of characters in FIFO

FIFO Full
Error-Underrun
Error-Overrun
Sensor Closure/Error Flag for
Multiple Closures
Display unavailable 05
Figure 3.7.4 Status Word Format of 8279

The status word contains the FIFO status, error, and display unavailable signals as shown
in figure 3.7.4. This word is read by the CPU when Ao is high and CS and RD” are low. See
Interface Considerations for more detail on status word.
Data Read
Data is read when Ao, CS and RD are all low. The source of the data is specified
by the Read FIFO or Read Display commands. The trailing edge of RD will cause the
address of the RAM being read to be incremented if the Auto-Increment flag is set. FIFO
reads always increment (if no error occurs) independent of Al.
Data Write
Data that is written with Ao, CS and WR low is always written to the Display
RAM. The address is specified by the latest Read Display or Write Display command.
Auto-Incrementing on the rising edge of WR occurs if Al is set by the latest display
command.
3.7.5 Interface Considerations
Scanned Keyboard Mode, 2-Key Lockout
There are three possible combinations of conditions that can occur during debounce
scanning. When a key is depressed, the debounce logic is set. Other depressed keys

are looked for during the next two scans. If none are encountered, it is a single key
depression and the key position is entered into the FIFO along with the status of CNTL NOTES
and SHIFT lines. If the FIFO was empty, IRQ will be set to signal the CPU that there is an
entry in the FIFO. If the FIFO was full, the key will not be entered and the error flag
will be set. If another closed switch is encountered, no entry to the FIFO can occur.
If all other keys are released before the one, then it will be entered to the FIFO. If this
key is released before any other, it will be entirely ignored. A key is entered to the
FIFO only once per depression, no matter how many keys were pressed along with it
or in what order they were released. If two keys are depressed within the debounce cycle,
it is a simultaneous depression. Neither key will be recognized until one key remains
depressed alone. The last key will be treated as a single key depression.
Scanned Keyboard Mode, N-Key Rollover
With N-key Rollover each key depression is treated independently from all others.
When a key is depressed, the debounce circuit waits 2 keyboard scans and then
checks to see if the key is still down. If it is , the key is entered into the FIFO. Any number of
keys can be depressed and another can be recognized and entered into the FIFO. If a
simultaneous depression occurs, the keys are recognized and entered according to the
order the keyboard scan found them.
Scanned Keyboard—Special Error Modes
For N-key rollover mode the user can program a special error mode. This is
done by the “End Interrupt/Error Mode Set” command. The debounce cycle and
key-validity check are as in normal N-key mode. If during a single debounce cycle,
two keys are found depressed, this is considered a simultaneous multiple depression,
and sets an error flag. This flag will prevent any further writing into the FIFO and will set
interrupt (if not yet set). The error flag could be read in this mode by reading the FIFO
STATUS word. (See “FIFO STATUS” for further details.) The error flag is reset by
sending the normal CLEAR command with CF = 1.
Sensor Matrix Mode
In Sensor Matrix mode, the debounce logic is inhibited. The status of the sensor
switch is inputted directly to the Sensor RAM. In this way the Sensor RAM keeps an
image of the state of the switches in the sensor matrix. Although debouncing is not provided,
this mode has the advantage that the CPU knows how long the sensor was closed and
when it was released. A keyboard mode can only indicate a validated closure. To make
the software easier, the designer should functionally group the sensors by row since this
is the format in which the CPU will read them.
The IRQ line goes high if any sensor value change is detected at the end of a sensor
matrix scan. The IRQ line is cleared by the first data read operation if the Auto-Increment
flag is set to zero, or by the End Interrupt command if the Auto-Increment flag is set to
one.
DMC 1932

NOTES Q3.7.a What are the principle operations of 8279 ?
Q3.7.b What is a debouncing circuit?
Q3.7.c What are the various input and output modes of 8279?
Q3.7d Discuss the various command word of 8279?
3.8 PROGRAMMABLE INTERRUPT CONTROLLER - 8259
The Intel 8259A Programmable Interrupt Controller handles up to eight vectored

priority interrupts for the CPU. It is cascadable for up to 64 vectored priority interrupts
without additional circuitry. It is packaged in a 28-pin DIP, uses NMOS technology and
requires a single 5V supply. Figure 3.8.1a and b shows the block diagram and pin
configuration of 8259.
INTA INT
DATA CONTROL LOGIC

D1 -D0 BUS
BUFFER
IR0
RD IR1
READ/
WR IN INTERRUPT IR2
WRITE
LOGIC SERVICE PRIORITY REQUEST IR3
REG RESOLVER REG IR4
A0 (ISR) (IRA)
IR5
IR6
CS IR7
CAS 0 INTERRUPT MASK REG

CASCADE (IMR)
CAS 1 BUFFER/
COMPARATOR
CAS 2
SP,EN INTERNAL
Figure 3.8.1a Block Diagram of 8259

DIP NOTES
CS 1 28 Vcc
WR 2 27 A0
RD 3 26 INTA
D7 4 25 IR7
D6 5 24 IR6
D5 6 23 IR5
D4 7 22 IR4
8259A
D3 8 21 IR3
D2 9 20 IR2
D1 10 19 IR1
D0 11 18 IR0
CAS 0 12 17 INT
CAS 1 13 16 SP,EN
GND 14 15 CAS 2
Figure 3.8.1b Pin Configuration of 8259
Interrupts in Microcomputer Systems
Microcomputer system design requires that I/O devices such as keyboards, displays,
sensors and other components receive servicing in a an efficient manner so that large
amounts of the total system tasks can be assumed by the microcomputer with little or no
effect on throughput.
The most common method of servicing such devices is the Polled approach. This is
where the processor must test each device in sequence and in effect “ask” each one if it
needs servicing. It is easy to see that a large portion of the main program is looping through
this continuous polling cycle and that such a method would have a serious detrimental
effect on system throughput, thus limiting the tasks that could be assumed by the
microcomputer and reducing the cost effectiveness of using such devices.
A more desirable method would be one that would allow the microprocessor to be
executing its main program and only stop to service peripheral devices when it is told to do
so by the device itself. In effect, the method would provide an external asynchronous input
that would inform the processor that it should complete whatever instruction that is currently
being executed and fetch a new routine that will service the requesting device. Once this

DMC 1932
servicing is complete, however, the processor would resume exactly where it left off. This
NOTES method is called Interrupt. It is easy to see that system throughput would drastically increase,
and thus more tasks could be assumed by the microcomputer to further enhance its cost
effectiveness.
Table3.8.1 : Pin Description of 8259

Symbol Pin No. Type Name and Function
Vcc 28 l SUPPLY: +5V Supply
GND 14 l GROUND
CS 1 1 CHIP SELECT: A low on this pin enables RD and WR
communication between the CPU and the 8259A, INTA
functions are independent of CS.
WR 2 l WRITE: A low on this pin when CS is low enables the
8259A to accept command words from the CPU.
RD 3 1 READ: A low on this pin when CS is low enable the 8259A
to release status onto the data bus for the CPU.
D7-D0 4-11 I/O BIDIRECTIONAL DATA BUS: Control, Status and
interrupt-vector information is transferred via this bus.
CAS0-CAS2 12,13,15 I/O CASCADE LINES: The CAS lines form a private 8259A
bus to control a multiple 8259A structure. These pins are
outputs for a master 8259A and inputs for a slave 8259A.
SP / EN 16 I/O SLAVE PROGRAM/ENABLE BUFFER: This is a dual
function pin. When in the Buffered Mode it can be used as
an output to control buffer transceivers (EN). When not in
the buffered mode it is used as an input to designate a
master (SP = 1) or slave (SP = 0).
INT 17 O INTERRUPT: This pin goes high whenever a valid
interrupt request is asserted. It is used to interrupt the CPU,
thus it is connected to the CPU’s interrupt pin.
IR0-IR7 18-25 1 INTERRUPT REQUESTS: Asynchronous inputs. An
interrupt request is executed by raising an IR input (low to
high), and holding it high until it is acknowledged (Edge
Triggered Mode), or just by a high level on an IR input
(Level Triggered Mode).
26 l INTERRUPT ACKNOWLEDGE: This pin is used to
INTA
enable 8259A interrupt-vector data onto the data bus by a
sequence of interrupt acknowledge pulses issued by the
CPU.
A0 27 1 AO ADDRESS LINE: This pin acts in conjunction with
the CS , WR , and RD Pins. It is used by the 8259A to
decipher various Command words the CPU writes and
status the CPU wishes to read. It is typically connected to
the CPU A0 address line (A1 for 8086, 8088).
The Programmable Interrupt Controller (PIC) functions as an overall manager in an

Interrupt-Driven system environment. It accepts requests from the peripheral equipment,
determines which of the incoming requests is of the highest importance (priority), ascertains
whether the incoming request has a higher priority value than the level currently being
serviced, and issues an interrupt to the CPU based on this determination. Each peripheral
device or structure usually has a special program or “routine” that is associated with its
specific functional or operational requirements; this is referred to as a “service routine”.
The PIC, after issuing an Interrupt to the CPU, must somehow input information into the
CPU that can “point” the Program Counter to the service routine associated with the

requesting device. This “pointer” is an address in a vectoring table and will often be referred
to, in this document, as vectoring data. NOTES
The 8259A is a device specifically designed for use in real time, interrupt driven
microcomputer systems. It manages eight levels or requests and has built-in features for
expandability to other 8259A’s (up to 64 levels). It is programmed by the system’s software
as an I/O peripheral. A selection of priority modes is available to the programmer so that
the manner in which the requests are processed by the 8259A can be configured to match
his system requirements.
The priority modes can be changed or reconfigured dynamically at any time during the
main program. This means that, the complete interrupt structure can be defined as required,
based on the total system environment.
INTERRUPT REQUEST REGISTER (IRR) AND IN-SERVICE REGISTER
(ISR)
The interrupts at the IR input lines are handled by two registers in cascade, the Interrupt
Request Register (IRR) and the In-Service (ISR). The IRR is used to store all the interrupt
levels which are requesting service; and the ISR is used to store all the interrupt levels
which are being serviced.
PRIORITY RESOLVER
This logic block determines the priorities of the bits set in the IRR. The highest priority
is selected and strobed into the corresponding bit of the ISR during INTA pulse.
INTERRUPT MASK REGISTER (IMR)
The IMR stores the bits which mask the interrupt lines to be masked. The IMR
operates on the IRR. Masking of a higher priority input will not affect the interrupt request
lines of lower quality.
INT (INTERRUPT)
This output goes directly to the CPU interrupt input. The VOH level on this line is
designed to be fully compatible with the 8080A, 8085A and 8086 input levels.
INTA (INTERRUPT ACKNOWLEDGE)
INTA pulses will cause the 8259A to release vectoring information onto the data bus.
The format of this data depends on the system mode (mPM) of the 8259A.
DATA BUS BUFFER
This 3-state, bidirectional 8-bit buffer is used to interface the 8259A to the system
Data Bus. Control words and status information are transferred through the Data Bus
Buffer.

DMC 1932
READ/WRITE CONTROL LOGIC

NOTES
The function of this block is to accept OUTput commands from the CPU. It contains
the Initialization Command Word (ICW) registers and Operation Command Word (OCW)
registers which store the various control formats for device operation. This function block
also allows the status of the 8259A to be transferred onto the Data Bus.
CS (CHIP SELECT)
A LOW on this input enables the 8259A. No reading or writing of the chip will occur
unless the device is selected.
WR (WRITE)
A LOW on this input enables the CPU to write control words (ICWs and OCWs) to
the 8259A.
RD (READ)
A LOW on this input enables the 8259A to send the status of the Interrupt Request
Register (IRR), In Service Register (ISR), the Interrupt Mask Register (IMR), or the
Interrupt level onto the Data Bus.
A0
This input signal is used in conjunction with WR and RD signals to write commands
into the various command registers, as well as reading the various status registers of the
chip. This line can be tied directly to one of the address lines.
THE CASCADE BUFFER/COMPARATOR
This function block stores and compares the IDs of all 8259A’s used in the system.
The associated three I/O pins (CAS0-2) are outputs when the 8259A is used as a master
and are inputs when the 8259A is used as a slave. As a master, the 8259A sends the ID of
the interrupting slave device onto the CAS0-2 lines. The slave thus selected will send its
preprogrammed subroutine address onto the Data Bus during the next one or two
consecutive INTA pulses.
INTERRUPT SEQUENCE
The powerful features of the 8259A in a microcomputer system are its programmability
and the interrupt routine addressing capability. The latter allows direct or indirect jumping
to the specific interrupt routine requested without any polling of the interrupting devices.
The normal sequence of events during an interrupt depends on the type of CPU being
used.

The events occur as follows in an 8085 system:
1. One or more of the INTERRUPT REQUEST lines (IR7-0) are raised high, setting
NOTES
the corresponding IRR bit(s).
2. The 8259A evaluates these requests, and sends an INT to the CPU, if appropriate.
3. The CPU acknowledges the INT and responds with an INTA pulse.
4. Upon receiving an INTA from the CPU group, the highest priority ISR bit is set,
and the corresponding IRR bit is reset. The 8259A will also release a CALL
instruction code (11001101) onto the 8-bit Data Bus through its D7-0 pins.
5. This CALL instruction will initiate two more INTA pulses to be sent to the 8259A
from the CPU group.
6. These two INTA pulses allow the 8259A to release its preprogrammed subroutine
address onto the Data Bus. The lower 8-bit address is released at the first INTA
pulse and the higher 8-bit address is released at the second INTA pulse.
7. This completes the 3-byte CALL instruction released by the 8259A. In the AEOI
mode the ISR bit is reset at the end of the third INTA pulse. Otherwise, the ISR
bit remains set until an appropriate EOI command is issued at the end of the
interrupt sequence.
The events occurring in an 8086 system are the same until step 4.
1. Upon receiving an INTA from the CPU group, the highest priority ISR bit is set
and the corresponding IRR bit is reset. The 8259A does not drive the Data Bus
during this cycle.
2. The 8086 will initiate a second INTA pulse. During this pulse, the 8259A releases
an 8-bit pointer onto the Data Bus where it is read by the CPU.
3. This completes the interrupt cycle. In the AEOI mode the ISR bit is reset at the
end of the second INTA pulse. Otherwise, the ISR bit remains set until an
appropriate EOI command is issued at the end of the interrupt subroutine.
If no interrupt request is present at step 4 of either sequence (i.e., the request was too
short in duration) the 8259A will issue an interrupt level 7. Both the vectoring bytes and the
CAS lines will look like an interrupt level 7 was requested. When the 8259A PIC receives
an interrupt, INT becomes active and an interrupt acknowledge cycle is started. If a higher
priority interrupt occurs between the two INTA pulses, the INT line goes inactive
immediately after the second INTA pulse. After an unspecified amount of time the INT line
is activated again to signify the higher priority interrupt waiting for service. This inactive
time is not specified and can vary between parts. The designer should be aware of this
consideration when designing a system which uses the 8259A. It is recommended that
proper asynchronous design techniques be followed.
This sequence is timed by three INTA pulses. During the first INTA pulse the CALL
opcode is enabled onto the data bus. During the second INTA pulse the lower address of
the appropriate service routine is enabled onto the data bus. When Interval = 4 bits A5-

DMC 1932
A7 are programmed, while A0-A4 are automatically inserted by the 8259A. When Interval
NOTES = 8 only A6 and A7 are programmed, while A0-A5 are automatically inserted. During the
third INTA pulse the higher address of the appropriate service routine, which was
programmed as byte 2 of the initialization sequence (A8-A15), is enabled onto the bus.
3.8.2 Programming The 8259A
The 8259A accepts two types of command words generated by the CPU:
1. Initialization Command Words (ICWs): Before normal operation can begin, each
8259A in the system must be brought to a starting point - by a sequence of 2 to 4
bytes timed by WR pulses.
2. Operation Command Words (OCWs): These are the command words which
command the 8259A to operate in various interrupt modes. These modes are:
a. Fully nested mode
b. Rotating priority mode
c. Special mask mode
d. Polled mode
The OCWs can be written into the 8259A anytime after initialization.
INITIALIZATION COMMAND WORDS (ICWS)
Whenever a command is issued with A0 = 0 and D4 = 1, this is interpreted as

Initialization Command Word 1 (ICW1). The format of initialization command words are
shown in figure 3.8.2. ICW1 starts the initialization sequence during which the following
automatically occur.
a. The edge sense circuit is reset, which means that following initialization, an interrupt
request (IR) input must make a low-to-high transition to generate an interrupt.
b. The Interrupt Mask Register is cleared.
c. IR7 input is assigned priority 7.
d. The slave mode address is set to 7.
e. Special Mask Mode is cleared and Status Read is set to IRR.
f. If IC4 = 0, then all functions selected in ICW4 are set to zero. (Non-Buffered
mode*, no AutoEOI, MCS-80, 85 system).
Initialization Command Words 1 and 2 (ICW1, ICW2)
A5-A15: Page starting address of service routines. In an MCS 80/85 system, the 8
request levels will generate CALLs to 8 locations equally spaced in memory. These can be
programmed to be spaced at intervals of 4 or 8 memory locations, thus the 8 routines will
occupy a page of 32 or 64 bytes, respectively.

The address format is 2 bytes long (A0-A15). When the routine interval is 4, A0-A4
are automatically inserted by the 8259A, while A5-A15 are programmed externally. When NOTES
the routine interval is 8, A0-A5 are automatically inserted by the 8259A, while A6-A15
are programmed externally.
The 8-byte interval will maintain compatibility with current software, while the 4-byte
interval is best for a compact jump table. In an 8086 system A15-A11 are inserted in the
five most significant bits of the vectoring byte and the 8259A sets the three least significant
bits according to the interrupt level. A10-A5 is ignored and ADI (Address interval) has no
effect.
LTIM: If LTIM = 1, then the 8259A will operate in the level interrupt mode. Edge
detect logic on the interrupt inputs will be disabled.
ADI: CALL address interval. ADI = 1 then interval e 4; ADI = 0 then interval = 8.
SNGL: Single. Means that this is the only 8259A in the system. If SNGL = 1 no
ICW3 will be issued.
IC4: If this bit is set -ICW4 has to be read. If ICW4 is not needed, set IC4 = 0.
Initialization Command Word 3 (ICW3)
This word is read only when there is more than one 8259A in the system and cascading
is used, in which case SNGL = 0. It will load the 8-bit slave register.
The functions of this register are:

a. In the master mode (either when SP = 1, or in buffered mode when M/S = 1 in
ICW4) a “1” is set for each slave in the system. The master then will release byte
1 of the call sequence (for MCS- 80/85 system) and will enable the corresponding
slave to release bytes 2 and 3 (for 8086 only byte 2) through the cascade lines.
b. In the slave mode (either when SP = 0, or if BUF = 1 and M/S = 0 in ICW4) bits
2-0 identify the slave. The slave compares its cascade input with these bits and, if
they are equal, bytes 2 and 3 of the call sequence (or just byte 2 for 8086) are
released by it on the Data Bus.
Initialization Command Word 4 (ICW4)
SFNM: If SFNM =1 the special fully nested mode is programmed.
BUF: If BUF = 1 the buffered mode is programmed. In buffered mode SP/EN becomes
an enable output and the master/slave determination is by M/S.
M/S: If buffered mode is selected: M/S = 1 means the 8259A is programmed to be a

master, M/S = 0 means the 8259A is programmed to be a slave. If BUF = 0, M/S has no
function.

DMC 1932
AEOI: If AEOI = 1 the automatic end of interrupt mode is programmed. mPM:

NOTES Microprocessor mode: mPM = 0 sets the 8259A for MCS-80, 85 system operation,
mPM = 1 sets the 8259A for 8086 system operation.
A0 D7 D6 D5 D4 D3 D2 D1 D0
0 A7 A6 A5 1 LTIM ADI SNGL IC4

1 ICW4 NEEDED
0. NO ICW4 NEEDED
1 = SINGLE
0 = CASCADE MODE
CALL ADDRESS INTERVAL

1 = INTERVAL OF 4
0 = INTERVAL OF 8
1 = LEVEL TRIGGERED MODE

0 = EDGE TRIGGERED MODE
A7-A5 of INTERRUPT
VECTOR ADDRESS
(MCS-80/85 MODE ONLY)
Figure 3.8.2a Initialization Command Word 1

A0 D7 D6 D5 D4 D3 D2 D1 D0
A15 A14 A13 A12 A11
1 A10 A9 A8
T7 T6 T5 T4 T3
A15 -A8 OF INTERRUPT

VECTOR ADDRESS
(MCS80/85 MODE)
T7-T3 OF INTERRUPT
VECTOR ADDRESS
(8086/8088 MODE)
Figure 3.8.2b Initialization Command Word 2
A0 D7 D6 D5 D4 D3 D2 D1 D0
1 S7 S6 S5 S4 S3 S2 S1 S0
1 = IR INPUT HAS A SLAVE

0 = IR INPUT DOES NOT HAVE
A SLAVE
Figure 3.8.2c Initialization Command Word 3 - Master

A0 D7 D6 D5 D4 D3 D2 D1 D0
NOTES
1 0 0 0 0 0 ID2 ID1 ID0
SLAVE ID
0 1 2 3 4 5 6 7
0 1 0 1 0 1 0 1
0 0 1 1 0 0 1 1
0 0 0 0 1 1 1 1
Figure 3.8.2 Initialization Command Word 3 - Slave
A0 D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 SFNM BUF M/S AEOI µPM
1 = 8086/8088 MODE
0 = MCS-80/85 MODE
1 = AUTO EOI
0 = NORMAL EOI
0 x - NON BUFFERED MODE

1 0 - BUFFERED MODE/SLAVE
1 1 - BUFFERED MODE/MASTER
1 = SPECIAL FULLY NESTED

MODE
0 = NOT SPECIAL FULLY
NESTED MODE
Figure 3.8.2 Initialization Command Word 4
OPERATION COMMAND WORDS (OCWS)
After the Initialization Command Words (ICWs) are programmed into the 8259A,
the chip is ready to accept interrupt requests at its input lines. However, during the 8259A
operation, a selection of algorithms can command the 8259A to operate in various modes
through the Operation Command Words (OCWs). The formats of the Operational
Command Word is shown in figure 3.8.3.
Operation Control Word 1 (OCW1)
OCW1 sets and clears the mask bits in the interrupt Mask Register (IMR). M7-M0
represent the eight mask bits. M = 1 indicates the channel is masked (inhibited), M = 0
indicates the channel is enabled.

DMC 1932
NOTES A0 D7 D6 D5 D4 D3 D2 D1 D0
1 M7 M5 M5 M4 M3 M2 M1 M0
INTERRUPT MASK
1 = MASK SET
0 = MASK RESET
Figure 3.8.3a Operational Command Word 1
R, SL, EOI-These three bits control the Rotate and End of Interrupt modes and
combinations of the two. A chart of these combinations can be found on the Operation
Command Word Format. L2,L1,L0-These bits determine the interrupt level acted upon
when the SL bit is active.
A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 1 P AR RIS
Figure 3.8.3b Operational Command Word 2
ESMM-Enable Special Mask Mode. When this bit is set to 1 it enables the SMM bit
to set or reset the Special Mask Mode. When ESMM = 0 the SMM bit becomes a “don’t
care”.

SMM-Special Mask Mode. If ESMM = 1 and SMM = 1 the 8259A will enter Special
Mask Mode. If ESMM =1 and SMM = 0 the 8259A will revert to normal mask mode. NOTES
When ESMM = 0, SMM has no effect.
Figure 3.8.3c Operational Command Word 3

Fully Nested Mode
This mode is entered after initialization unless another mode is programmed. The
interrupt requests are ordered in priority from 0 through 7 (0 highest). When an interrupt is
acknowledged the highest priority request is determined and its vector placed on the bus.
Additionally, a bit of the Interrupt Service register (ISO-7) is set. This bit remains set until
the microprocessor issues an End of Interrupt (EOI) command immediately before returning
from the service routine, or if AEOI (Automatic End of Interrupt) bit is set, until the trailing
edge of the last INTA. While the IS bit is set, all further interrupts of the same or lower
priority are inhibited, while higher levels will generate an interrupt (which will be
acknowledged only if the microprocessor internal Interrupt enable flip-flop has been re-
enabled through software). After the initialization sequence, IR0 has the highest priority
and IR7 the lowest. Priorities can be changed, as will be explained, in the rotating priority
mode.
End of Interrupt (EOI)
The In Service (IS) bit can be reset either automatically following the trailing edge of
the last in sequence INTA pulse (when AEOI bit in ICW1 is set) or by a command word
that must be issued to the 8259A before returning from a service routine (EOI command).
An EOI command must be issued twice if in the Cascade mode, once for the master and
once for the corresponding slave.
DMC 1932
There are two forms of EOI command: Specific and Non-Specific. When the 8259A
NOTES is operated in modes which preserves the fully nested structure, it can determine which IS
bit to reset on EOI. When a Non-Specific EOI command is issued the 8259A will
automatically reset the highest IS bit of those that are set, since in the fully nested mode the
highest IS level was necessarily the last level acknowledged and serviced. A non-specific
EOI can be issued with OCW2 (EOI = 1, SL = 0, R = 0).
When a mode is used which may disturb the fully nested structure, the 8259A may no
longer be able to determine the last level acknowledged. In this case a Specific End of
Interrupt must be issued which includes as part of the command the IS level to be reset. A
specific EOI can be issued with OCW2 (EOI = 1, SL = 1, R = 0, and L0-L2 is the binary
level of the IS bit to be reset). It should be noted that an IS bit that is masked by an IMR
bit will not be cleared by a non-specific EOI if the 8259A is in the Special Mask Mode.
Automatic End of Interrupt (AEOI) Mode

If AEOI = 1 in ICW4, then the 8259A will operate in AEOI mode continuously until
reprogrammed by ICW4. In this mode the 8259A will automatically perform a non-specific
EOI operation at the trailing edge of the last interrupt acknowledge pulse (third pulse in
MCS-80/85, second in 8086). Note that from a system standpoint, this mode should be
used only when a nested multilevel interrupt structure is not required within a single 8259A.
The AEOI mode can only be used in a master 8259A and not a slave. 8259As with a
copyright date of 1985 or later will operate in the AEOI mode as a master or a slave.
Automatic Rotation (Equal Priority Devices)
In some applications there are a number of interrupting devices of equal priority. In
this mode a device, after being serviced, receives the lowest priority, so a device requesting
an interrupt will have to wait, in the worst case until each of 7 other devices are serviced at
most once.
Specific Rotation (Specific Priority)
The programmer can change priorities by programming the bottom priority and thus
fixing all other priorities; i.e., if IR5 is programmed as the bottom priority device, then IR6
will have the highest one.
The Set Priority command is issued in OCW2 where: R = 1, SL = 1, L0-L2 is the
binary priority level code of the bottom priority device. Observe that in this mode internal
status is updated by software control during OCW2. However, it is independent of the
End of Interrupt (EOI) command (also executed by OCW2). Priority changes can be
executed during an EOI command by using the Rotate on Specific EOI command in OCW2
(R =1, SL = 1, EOI = 1 and LO-L2 = IR level to receive bottom priority)

Interrupt Masks
NOTES
Each Interrupt Request input can be masked individually by the Interrupt Mask
Register (IMR) programmed through OCW1. Each bit in the IMR masks one interrupt
channel if it is set (1). Bit 0 masks IR0, Bit 1 masks IR1 and so forth. Masking an IR
channel does not affect the other channels operation.
Special Mask Mode
Some applications may require an interrupt service routine to dynamically alter the
system priority structure during its execution under software control. For example, the
routine may wish to inhibit lower priority requests for a portion of its execution but enable
some of them for another portion.
The difficulty here is that if an Interrupt Request is acknowledged and an End of Interrupt
command did not reset its IS bit (i.e., while executing a service routine), the 8259A would
have inhibited all lower priority requests with no easy way for the routine to enable them.
That is where the Special Mask Mode comes in. In the special Mask Mode, when a mask
bit is set in OCW1, it inhibits further interrupts at that level and enables interrupts from all
other levels (lower as well as higher) that are not masked. Thus, any interrupts may be
selectively enabled by loading the mask register.
The special Mask Mode is set by OWC3 where:
SSMM = 1, SMM = 1, and cleared where SSMM = 1, SMM = 0.
Poll Command
In Poll mode the INT output functions as it normally does. The microprocessor should
ignore this output. This can be accomplished either by not connecting the INT output or by
masking interrupts within the microprocessor, thereby disabling its interrupt input. Service
to devices is achieved by software using a Poll command. The Poll command is issued by
setting P = ‘1” in OCW3. The 8259A treats the next RD pulse to the 8259A (i.e., RD = 0,
CS = 0) as an interrupt acknowledge, sets the appropriate IS bit if there is a request, and
reads the priority level. Interrupt is frozen from WR to RD.
Q3.8.aWhat is the functions of various registers present in 8259?
Q3.8.b What are the sequences of operation that take place when a request arrives?
Q3.8.c Discuss the various initialization and operational command word?

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3.9 DMA CONTROLLER - 8257

NOTES
The Intel 8257 is a 4-channel direct memory access (DMA) controller. It is specifically
designed to simplify the transfer of data at high speeds for the Intel microcomputer
systems. Its primary function is to generate, upon a peripheral request, a sequential
memory address which will allow the peripheral to read or write data directly to or from
memory. Acquisition of the system bus is accomplished via the CPU’s hold function.
The 8257 has priority logic that resolves the peripherals requests and issues a
composite hold request to the CPU. It maintains the DMA cycle count for each channel
and outputs a control signal to notify the peripheral that the programmed number of DMA
cycles is complete. Other output control signals simplify sectored data transfers. The
8257 represents a significant savings in component count for DMA-based
microcomputer systems and greatly simplifies the transfer of data at high speed between
peripherals and memories.
The 8257 is a programmable, Direct Memory Access (DMA) device which, when
coupled with a single lntel 8212 I/O port device, provides a complete four-channel DMA
controller for use in Intel® microcomputer systems. Alter being initialized by software, the
8257 can transfer a block of data, containing up to 16,384 bytes, between memory and a
peripheral device directly, without further intervention required of the CPU. Upon receiving
a DMA transfer request from an enabled peripheral, the 8257:
1. Acquires control of the system bus.
2. Acknowledges that requesting peripheral which is connected to the highest priority
channel.
3. Outputs the least significant eight bits of the memory address onto system address
lines Ao-A7. outputs the most significant eight bits of the memory address to the
8212 110 port via. the data bus (the 8212 places these address bits on lines
A8.A15), and
4. Generates the appropriate memory and I/O read/write control signals that cause
the peripheral to receive or deposit a data byte directly from or to the addressed
location in memory.
The 8257 will retain control of the system bus and repeal the transfer sequence, as
long as a peripheral maintains its DMA request. Thus, the 8257 can transfer a block of
data to/from a high speed peripheral (e.g.. a sector of data on a floppy disk) in a single
“burst”. When the specified number of data bytes have been transferred, the 8257 activates
its Terminal Count (TC) output, informing the CPU that the operation is complete.
The 8257 offers three different modes of operation:
(1) DMA read, which causes data to be transferred from memory to a peripheral
(2) DMA write, which causes data to be transferred from a peripheral to memory

(3) DMA verify, which does not actually involve the transfer of data. When an 8257
channel is in the DMA verify mode, it will respond the same as described for transfer NOTES
operations, except that no memory or I/O read/write control signals will be generated,
thus preventing the transfer of data. The 8257, however, will gain control of the system bus
and will acknowledge the peripheral’s DMA request for each DMA cycle. The peripheral
can use these acknowledge signals to enable an internal access of each byte of a data
block ri order to execute some verification procedure, such as the accumulation of a CRC
(Cyclic Redundancy Code) checkword. For example, a block of DMA verify cycles might
follow a block of DMA read cycles (memory to peripheral) to allow the peripheral to
verify its newly acquired data.
3.9.1 Block Diagram Description
The block diagram and pin configuration of DMA controller is shown in figures 3.9.1
and 3.9.2.
DMA Channels
The 8257 provides four separate DMA channels (labeled CH-O to CH-3). Each
channel includes two sixteen-bit registers: (1) a DMA address register, and (2) a terminal
count register. Both registers must be initialized before a channel is enabled. The DMA
address register is loaded with the address of the first memory location to be accessed.
The value loaded into the low-order 14-bits of the terminal count register specifies the
number of DMA cycles minus one before the Terminal Count (TC) output is activated. For
instance, a terminal count of 0 would cause the TC output to be active in the first DMA
cycle for that channel. In general, if N = the number of desired DMA cycles, load the value
N-i into the low-order 14-bits of the terminal count register. The most significant two bits
of the terminal count register specify the type of DMA operation for that channel. These
two bits are not modified during a DMA cycle, but can be changed between DMA blocks,
Each channel accepts a DMA Request (DROn) input and provides a DMA
Acknowledge (DACKn) output.

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NOTES
Figure 3.9.1 DMA Controller block diagram
Figure 3.9.2 DMA Pin Configuration diagram

(DRQ 0-DRQ 3)
NOTES
DMA Request: These are individual asynchronous channel request inputs used by the
peripherals to obtain a DMA cycle. If not in the rotating priority mode then DRQ 0 has the
highest priority and DRQ 3 has the lowest, A request can be generated by raising the
request line and holding it high until DMA acknowledge. For multiple DMA cycles (Burst
Mode) the request line is held high until the DMA acknowledge at the last cycle arrives.
(DACK 0- DACK 3)
DMA Acknowledge: An active low level on the acknowledge output informs the
peripheral connected to that channel that ii has been selected for a DMA cycle. The DACK
output acts as a “chip select” for the peripheral device requesting service. This line goes
active (low) and inactive (high) once for each byte transferred even if a burst of data is
being transferred.
Data Bus Buffer
This three-state. bi-directional. eight bit buffer interfaces the 8257 to the system data bus.
(D0-D7)
Data Bus Lines: These are bi-directional three-state lines. When the 8257 is being
programmed by the CPU. eight-bits of data for a DMA address register, a terminal count
register or the Mode Set register are received on the data bus. When the CPU reads a
DMA address register, a terminal count register or the Status register, the data is sent to
the CPU over the data bus. During DMA cycle5 (when the 8257 is the bus master, the
8257 will output the most significant eight-bits of the memory address (from one of the
DMA address registers) to the 8212 latch via the data bus. These address bits will be
transferred at the beginning of the DMA cycle; the bus will then be released to handle the
memory data transfer during the balance of the DMA cycle.
Read/Write Logic
When the CPU Is programming or reading one of the 8257’s registers (i.e., when the
8257 is a “slave” device on the system bus), the Read/Write Logic accepts the I/O Read
(IOR) or I/O Write (IOW) signal, decodes the least significant four address bits, (A0-
A3), and either writes the contents of the data bus into the addressed register (if IOW is
true) or places the contents of the addressed register onto the data bus (if IOR is true).
During DMA cycles (i.e., when the 8257 is the bus “master”), the Read/Write Logic
generates the I/O read and memory write (DMA write cycle) or I/O Write and memory
read (DMA read cycle) signals which control the data link with the peripheral that has
been granted the DMA cycle.

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Note that during DMA transfers Non-DMA I/O devices should be de-selected (disabled)
NOTES using “AEN” signal to inhibit I/O device decoding of the memory address as an erroneous
device address.
(I/OR)
I/O Read: An active-tow, bi-directional three-state line. In the “slave” mode, it is an

input which allows the 8-bit status register or the upper/tower byte of a 16-bit DMA
address register or terminal count register to be read. In the “master” mode, I/OR is a
control output which is used to access data from a peripheral during the DMA write cycle.
(I/OW)
I/O Write: An active-low, bi-directional three-state line. In the “slave’ mode, it is an

input which allows the contents of the data bus to be loaded into the 8-bit mode set
register or the upper/lower byte of a 16-bit DMA address register or terminal Count
register. In the “master” mode, I/OW is a control output which allows data to be output to
a peripheral during a DMA read cycle.
(CLK)
Clock Input: Generally from an Intel® 8224 Clock Generator device.
(RESET)
Reset: An asynchronous input (generally from an 8224 or 8085 device) which disables
all DMA channels by clearing the mode register and 3-states all control lines,
(A0-A3)
Address Lines: These least significant four address lines are bi-directional. In the
“slave” mode they are inputs which select one of the registers to be read or programmed.
In the “master” mode, they are outputs which constitute the least significant tour bits of the
16-bit memory address generated by the 8257.
(CS)
Chip Select: An active-low input which enables the I/O Read or I/O Write input when
the 8257 is being read or programmed in the “slave” mode. In the “master” mode, is
automatically disabled to prevent the chip from selecting itself while performing the DMA
function.
Control Logic
This block controls the sequence of operations during all DMA cycles by generating
the appropriate control signals and the 16-bit address that specifies the memory location
to be accessed.

(A4-A7)
NOTES
Address Lines: These four address lines are three-state outputs which constitute bits
4 through 7 of the 16-bit memory address generated by the 8257 during all DMA cycles.
(READY)
Ready: This asynchronous input is used to elongate the memory read and write cycles
in the 8257 with wait states if the selected memory requires longer cycles. READY must
conform to specified setup and hold times.
(HRQ)
Hold Request: This output requests control of the system bus. In systems with only
one 8257, HRQ will normally be applied to the HOLD input on the CPU. HRO must
conform to specified setup and hold times.
(HL.DA)
Hold Acknowledge: This input from the CPU indicates that the 8257 has acquired
control of the system bus.
(MEMR)
Memory Read: This active-low three-state output is used to read data from the
addressed memory location during DMA Read cycles.
(MEMR)
Memory Read: This active-low three-state output is used to read data from the
addressed memory location during DMA Read cycles.
(MEMW)
Memory Write: This active-low three-state output is used to write data into the
addressed memory location during DMA Write cycles.
(ADSTB)
Address Strobe: This output strobes the most significant byte of the memory address
into the 8212 device from the data bus.
(AEN)
Address Enable: This output is used to disable (float) the System Data Bus and the
System Control Bus. It may also be used to disable (float) the System Address Bus by use
of an enable on the Address Bus drivers in systems to inhibit non-DMA devices from
responding during DMA cycles. It may be further used to isolate the 8257 data bus from

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the System Data Bus to facilitate the transfer of the 8 most significant DMA address bits
NOTES over the 8257 data I/O pins without subjecting the System Data Bus to any timing constraints
for the transfer. When the 8257 is used in an I/O device structure (as opposed to memory
mapped), this AEN output should be used to disable the selection of an I/O device when
the DMA address is on the address bus. The I/O device selection should be determined
by the DMA acknowledge Outputs for the 4 channels.
(TC)
Terminal Count: This output notifies the currently selected peripheral that the present
DMA cycle should be the last cycle for this data block. If the TC STOP bit in the Mode
Set register is set, the selected channel will be automatically disabled at the end of that
DMA cycle. TC is activated when the 14-bit value in the selected channel’s terminal count
register equals zero. Recall that the low order 14-bits of the terminal count register should
be loaded with the values (n-I). where n = the desired number of the DMA cycles.
(MARK)
Modulo 128 Mark: This output notifies the selected peripheral that the current DMA
cycle is the 128th cycle since the previous MARK output. MARK always occurs at 128
(and all multiples of 128) cycles from the end of the data block. Only if the total number of
DMA cycles (n) is evenly devisable by 128 (and the terminal count register was loaded
with n-1). will MARK occur at 128 (and each succeeding multiple of 128) cycles from the
beginning of the data block.
3.9.2 Mode Set Register
When set the various bits in the Mode Set register enable each of the four DMA
channels, and allow four different options for the 8257 and the format for mode set register
is shown in figure 3.9.3.
7 6 5 4 3 2 1 0
Enables AUTOLOAD Enables DMA Channel 0

Enables TC STOP Enables DMA Channel 1
Enables EXTENDED WRITE Enables DMA Channel 2
Enables ROTATING PRIORITY Enables DMA Channel 3
Figure 3.9.3 Mode Set Register
The Mode Set register is normally programmed by the CPU alter the DMA address
registers) and terminal count register(s) are initialized. The Mode Set Register is cleared
by the RESET input, thus disabling all options, inhibiting all channels, and preventing bus
conflicts on power-up. A channel should not be left enabled unless its DMA address and

terminal count registers contain valid values; otherwise, an inadvertent DMA request (DRQn)
from a peripheral could initiate a DMA cycle that would destroy memory data. NOTES
The various options which can be enabled by bits in the Mode Set register are explained
below:
Rotating Priority Bit 4
In the Rotating Priority Mode, the priority of the channels has a circular sequence.
After each DMA cycle the priority of each channel changes. The channel which just had
been serviced will have the lowest priority.
Extended Write Bit 5
In the EXTENDED WRITE bit is set the duration of both the MEMW and I/OW
signals is extended by activating them earlier in the DMA cycle. Data transfers within
microcomputer systems proceed asynchronously to allow use of various types of memory
and I/O devices with different access times. If a device cannot be accessed within a specific
amount of time it returns a “not ready” indication to the 8257 that causes the 8257 to insert
one or more wait states in its internal sequencing. Some devices are fast enough to be
accessed without the use of wait states, but it they generate their READY response with
the leading edge of the I/OW or MEMW signal (which generally occurs late in the transfer
sequence), they would normally cause the 8257 to enter a wait state because it does not
receive READY in time. For systems with these types of devices, the Extended Write
option provides alternative timing for the I/O and memory write signals which allows the
devices to return an early READY and prevents the unnecessary occurrence of wait states
in the 8257, thus increasing system throughput.
TC Stop Bit6
If the TC STOP bit is set, a channel is disabled (i.e.. its enable bit is reset) after the
Terminal Count (TC) output goes true, thus automatically preventing further DMA operation
on that channel. The enable bit for that channel must be re-programmed to continue or
begin another DMA operation. If the TC STOP bit is not set, the occurrence of the TC
output has no effect on the channel enable bits. In this case, it is generally the responsibility
of the peripheral to cease DMA requests in order to terminate a DMA operation.
Auto Load Bit 7
The Auto Load mode permits Channel 2 to be used for repeat block or block chaining
operations, without immediate software intervention between blocks, Channel 2 registers
are initialized as usual for the first data block: Channel 3 registers, however, are used to
store the block re-initialization parameters (DMA starting address. terminal count and
DMA transfer mode). After the first block of DMA cycles 1 is executed by Channel 2 (i.e.,

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after the TC output goes true), the parameters Stored in the Channel 3 registers are
NOTES transferred to Channel 2 during an “update” cycle. Note that the TC STOP feature,
described above, has no effect on Channel 2 when the Auto Load bit is set.
If the Auto Load bit is set, the initial parameters for Channel 2 are automatically
duplicated in the Channel 3 registers when Channel 2 is programmed. This permits repeat
block operations to be set up with the programming of a single channel. Repeat block
operations can be used in applications such as CRT refreshing. Channels 2 and 3 can still
be loaded with separate values if Channel 2 is loaded before loading Channel 3. Note that
in the Auto Load mode, Channel 3 is still available to the user if the Channel 3 enable bit is
set, but use of this channel will change the values to be auto loaded into Channel 2 at
update time. All that is necessary to use the Auto Load feature for chaining operations is to
reload Channel 3 registers at the conclusion of each update cycle with the new parameters
far the next data block transfer.
Each time that the 8257 enters an update cycle, the update status register is set and
parameters in Channel 3 are transferred to Channel 2, non-destructively for channel3. The
actual re-initialization of Channel 2 occurs at the beginning of the next channel 2 DMA
cycle after the TC cycle. This will be the first DMA cycle of the new data block for channel
2. The update flag is cleared at the conclusion of this DMA cycle. For chaining operations
the update flag in the status register can be monitored by the CPU to determine when the
re-initialization process has been completed so that the next block parameters can be
safely loaded into Channel 3.
Status Register
The eight-bit status register indicates which channels have reached a terminal count
condition and includes the update flag described previously. The format of status register is
shown in figure 3.9.4.
7 6 5 4 3 2 1 0
0 0 0
TC STATUS FOR CHANNEL 0

UPDATE FLAG TC STATUS FOR CHANNEL 1
Figure 3.9.4 Status Register
The TC status bits are set when the Terminal Count (TC) output is activated for that
channel. These bits remain set until the status register is read or the 8257 is reset. The
UPDATE FLAG, however, is not affected by a status register read operation. The UPDATE
FLAG can be cleared by resetting the 8257. by changing to the non-auto load mode (i.e.,

by resetting the AUTO LOAD bit in the Mode Set register) or it can be left to clear itself
at the completion of the update cycle. The purpose of the UPDATE FLAG is to prevent NOTES
the CPU from inadvertently skipping a data block by overwriting a starting address or
terminal count in the Channel 3 registers before those parameters are properly auto-loaded
into Channel 2.
Q3.9.a Discuss about the read, write and verify operations of the DMA controller?
Q3.9.b Discuss about the DMA channels present in 8257?
Q3.9c Discuss about the mode set register?
Summary
 We have presented the peripheral devices and their interfacing circuits.
 To start with the interfacing of memories have been discussed briefly.
 The parallel programmable interface 8255 has been presented in significant details.
 The necessary functional details of 8254 have been discussed.
 Further the peripherals like programmable interrupt controller 8259A,
programmable keyboard/display controller 8279A, programmable communication
interface 8251A have been discussed along with the architecture, signal descriptions,
interfacing and programming examples.
 Thus, this chapter may provide an insight into the operations, programming and
interfacing of the dedicated peripherals.
EXERCISES
(i) OBJECTIVE TYPE QUESTIONS
3.1. In 8279 Strobed input mode, when the control line goes low, the data on return
lines is strobed in the ____ byte by byte.
a) FIFO b) FILO c) LIFO d) LILO.
3.2 The ___ bit in ICW1 indicates whether the 8259A is cascade mode or not.
a) LTIM=0 b) LTIM=1 c) SNGL=0 d) SNGL=1
3.3. In 8255, under the I/O mode of operation there are ____ modes and the following
features can be observed in ________ (mode).
i) A 5 bit control port is available.
ii) Three I/O lines are available at Port C.
a) 3, Mode2 b) 2, Mode 2 c) 4, Mode 3 d) 3, Mode 2

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3.4. In 8279, a scanned sensor matrix mode, if a sensor changes its state, the ___ line
NOTES goes ____ to interrupt the CPU.
a) CS, high b) A0, high c) IRQ, high d) STB, high
3.5. In 8279 Status Word, data is read when ________ pins are low, and write to the
display RAM with ____________ are low.
a) A0, CS, RD & A0, WR, CS. b) CS, WR, A0 & A0, CS, RD
c) A0, RD & WR, CS d) CS, RD & A0, CS.
3.6. In 8279, the keyboard entries are debounced and stored in an _________, that
is further accessed by the CPU to read the key codes.
a) 8-bit FIFO b) 8-byte FIFO c) 16 byte FIFO d) 16 bit FIFO
3.7. The 8279 normally provides a maximum of _____ seven segment display interface
with CPU.
a) 8 b) 16 c) 32 d) 18
(ii) QUESTIONS FOR LONG/SHORT ANSWERS

3.1 How does Port C of 8255 differ from ports A and B?
3.2 Explain different methods of parallel data transfer of 8255A
3.3 Explain the control word format of 8255 in I/O and BSR mode.
3.4 Explain the function of in-service register in 8259 programmable interrupt controller.
3.5 How many interrupts are possible with a single 8259?
3.6 With cascading mode of 8259 how many interrupts are possible?
3.7 How many 8259 ICs will be required for cascading mode?
3.8 What is the difference between polled command mode and vectored (interrupt
driven) command mode of 8259?
3.9 With block diagram describe the working of a DMA controller.
3.10.Explain the mode set register of 8279.
3.11.What are the 3 modes of operation of a keyboard interface chip 8279?
3.12.With a neat diagram explain the functional features of a 8279 keyboard interface
processor.
3.13.With a neat diagram explain the functional features of 8257 DMA controller.
3.14. Explain the following programmable counter modes of 8254
 Interrupt on terminal count
 Hardware retriggerable one-shot
 Rate generator

 Square wave mode
 Software-triggered strobe NOTES
 Hardware-triggered strobe (retriggerable)
3.15. What is the difference between software and hardware triggered modes of 8254?
3.16. List the applications of 8254.
3.17. What is read back command in 8254?
3.18. Explain control word format of 8251.
3.19.What are the applications of 8251.
3.20.Is write operation possible with status word register of 8251?
3.21.Define mode word register of 8251 for sync mode.
3.22. Define mode word register of 8251 for asynchronous mode.
3.23.What is USART?
3.24.What is the significance of BREAK DETECT signal in 8251?
3.25.What is over run error in 8251?
3.26.What is the significance of SYNC DETECT signal in 8251?

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NOTES

NOTES
UNIT IV
ADVANCED PROCESSORS
4.1 INTRODUCTION TO ADVANCED PROCESSORS
The Intel 80286 is an enhanced version of the earlier 8086/8088 microprocessor.

These are 16-bit processors that are upward compatible to 8086/8088. Even the hardware
is similar to the earlier versions. This unit provides the derails of the 80286 architecture.
The Intel 80386 is a full 32-bit version of the earlier 8086/8088 and 80286 16-bit
microprocessors and represents a major advancement in architecture. The 80486 is an
advanced version of 80386 that executes many of its instructions in a single clock period.
The 80486 also contains 8KB cache and an improved 80387 numeric coprocessor.
Pentium and Pentium Pro perform at better than twice the speed of the 80486. They
contain 16K cache and contain improved numeric coprocessors that operate five times
faster than in 80486.

 Detailed knowledge of the 80286 processor
 Architecture and features of 80286
 Register organization and different operating modes of 80286
 Architecture and features of 80386, 486 and Pentium processors
 Comparison between the various processors
4.3 INTEL 80286
The Intel 80286 processor is an advanced version of 8086 microprocessor. This

enhanced version of the 8086 includes a memory management unit through which the
80286 can address the virtual memory space of 1GB. It has 16-bit date bus, 24-bit non-
multiplexed bus and is packaged in a 68-pin ceramic pack. 80286 has 224 = 16M Byte of
physical memory accessibility.

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4.3.1 Internal Architecture

NOTES The block diagram of the internal architecture of the 80286 is shown in Figure 4.3.1.
This consists of four sections: The address unit (AU), the bus unit (BU) the Execution unit
(EU) and the Instruction unit (IU).
The bus unit (BU) performs all memory and I/O reads and writes, prefetches instruction
bytes, and controls transfer of data to and from processor extension devices such as the
80287 math coprocessor.
The instruction unit (IU) fully decodes up to three prefetched instructions and holds
them in a queue, where the execution unit can access them. This is an example of how
modern processors keep several instructions “in the pipeline” instead of waiting to finish
one instruction before fetching the next.
The execution unit (EU) uses its 16-bit ALU to execute instructions it receives from
the instruction unit. When operating in its real address mode, the 80286 register set is the
same as that of an 8086 except for the addition of a 16-bit machine status word (MSW)
register.
The address unit (AU) computes the physical addresses that will be sent out to memory
or I/O by the BU. The 80286 can operate in one of two memory address modes, real
address mode or protected virtual address mode. If the 80286 is operating in the real
address mode, the address unit computes addresses using a segment base and an offset
just as the 8086 does. The familiar CS, DS, SS, and ES registers are used to hold the
base addressed for the segments currently in use. The maximum physical address space in
this mode is 1 Mbyte, just as it is for the 8086.
Figure 4.3.1 Basic architecture of Intel 80286

A 68-pin package is usually used for the 80286 microprocessor. The 80286 as a 16-
bit data bus and a 24-bit non-multiplexed address bus. The 24-bit address bus allows the NOTES
processor to access 16 Mbytes of physical memory when operating in protected mode.
Memory hardware for the 80286 is set up as an odd bank and an even bank, just as it is
for the 8086. The even bank will be enabled when BHE is low. To access an aligned
word, both A0 and BHE will be low. External buffers are used on both the address and
the data bus.
From a control standpoint, the 80286 functions similar to an 8086 while the latter
operates in maximum mode. Status signals S0#, S1#, and M/IO# are decoded by an
external 8288 bus controller to produce the control bus, read, write, and interrupt-
acknowledge signals.
The HOLD, HLDA, INTR, INTA#, (NMI), READY#, and LOCK# and RESET
pins function basically the same as they do on an 8086. An external 82284-clock generator
is used to produce a clock signal for the 80286 and to synchronize RESET and READY#
signals.
The final four signal pins we need to discuss here are used to interface with processor
extensions such as the 80287-math coprocessor. The processor extension request
(PEREQ) input pin will be asserted by a coprocessor to tell the 80286 to perform a data
transfer to or from memory for it. When the 80286 gets around to perform the transfer, it
asserts the processor extension acknowledgement (PEACK#) signal to the coprocessor
to let it know the data transfer has started. The BUSY signal input on the 80286 functions
the same way as the TEST1# input does on the 8086. When the 80286 execute a WAIT
instruction, it will remain in a WAIT loop until it finds the BUSY# signal from the coprocessor
high. If a coprocessor finds some error during processing, it will assert the ERROR# input
of the 80286.
Figure 4.3.1 shows the address pins A23-A0, BUSY (active low), CAP, ERROR
(active low), PEREQ (active low), and PEACK (active low) are new or additional pins
that do not appear on the 8086. The BUSY (active low), ERROR (active low), PEREQ
(active low), and PEACK (active low) are used with the microprocessor extension or
coprocessor (eg. 80287). It must be noted that the TEST pin is now known as BUSY.
The address is 24bits wide to accommodate 16M bytes of physical memory. 80286 does
not contain multiplexed address/data bus.
4.3.2 Register Organization

The 80286 has a rich set of registers as shown in Figure 4.3.2. The bulk of data
manipulation is performed using the processor and co-processor register sets. Some
operations, such as storing an immediate quantity directly to memory, can occur without
involving any register, but generally the register set acts as a work-slate, while memory
corresponds to a huge filing system for storing the code and data.
DMC 1932
The 80286 has a total of fourteen registers of interest to application programmers.

NOTES Five additional registers are of interest to system programmers. The 80287 numeric co-
processor contains eight registers of interest to application programmers and five additional
registers of interest to system programmers.
AH AX AL Accumulator
16-bit
registers BH BX BL Base Index
AH AX AL CH CX CL Count
DH DX DL Data
8-bit 16-bit Stack Pointer
SP
names
BP Base Pointer
DI Destination Index
SI Source Index
IP Instruction Pointer
FLAGS Flags
CS Code
DS Data
ES Extra
SS Stack
Figure 4.3.2 Registers in 80286

80286 General Purpose Registers
Figure 4.3.2 names the eight general-purpose registers clearly. The general 80826
registers are each 16-bits wide. These general registers are quite flexible. For almost all
instructions, they are interchangeable in their ability to hold data operands. Any of these
eight registers may be used to hold 16-bit data, or may hold 8-bit data. Four registers, the
AX, DX, CX and BX registers, allow both 8-bit halves to be individually accessed for
some additional flexibility in handling byte data.
Five of the general-purpose registers may hold address quantities. These five address
registers, namely, BX, SI, DI, BP, and SP, can therefore be used when performing address
calculations.
80287 General Numeric Registers
The eight general-purpose registers in 80287 (R0 – R7) are 80-bit wide and hold
operands for arithmetic operations. They participate in register-register, register-memory,
and memory-register operations. They are dedicated to numeric processing.

80286 Segment Registers
NOTES
Segment registers are fundamental to addressing memory-resident operands. The
processor has four segment registers as shown in Figure 4.3.2, which determines addressable
segments at any given time. The four registers are: code segment (CS), stack segment
(SS), data segment (DS), and extra segment (ES). These registers endow all code and
data with good degree of relocatability, in real or protected mode. Since a segment register
is involved with every access to memory, all code and data are positioned relative to a
segment base address.
80286 Instruction Pointer
The Instruction Pointer (IP) is a 16-bit register and it holds an offset pointing to the
current instruction within the code segment. After completion of instruction, IP is incremented
to point at next sequential instruction. Depending on the number of bytes of instruction, IP
increments by 1 or more bytes. However, during JMP, CALL or INT instructions, the IP
does not advance sequentially.
80286 Flag Word
The Flag is a 16 bit register in 80286. It contains six single-bit flags indicating the
result of the most recent logical or arithmetic instruction. The results flag include a carry
flag, a parity flag, an Auxiliary carry flag, a zero flag, a sign flag and an overflow flag. It also
contains control flags to indicate current status of 80286 functions as shown in Figure
4.3.3.
15 0
- NT IOPL OF DF IF TF SF ZF - AF - PF - CF
(overflow flag ), NT (nested task ), and IOPL (input/output privilege level). Most of the
instructions that require the use of the ALU affect the flags. Remember that the flags allow
ALU instructions to be followed by conditional instructions.
The content/operations of each flag is as follows:
CF : Contains carry out of MSB of result

PF : Indicates if result has even party
AF : Contains carry out of bit 3 in AL
ZF : Indicates if result equals zero
SF : Indicates if result is negative
OF : Indicates that an overflow occured in result
IF : Enables/Disables interrupts
DF : Controls pointer updates during string operations
TF : Provide single-step capability for debugging
IOPL : Priority level of current task
NT : Indicates if current task is nested
Figure 4.3.3 Flag Register in 80286

DMC 1932
4.3.3 Modes of operation

NOTES
80286 can operate in two modes, namely, real and protected: Real Address Mode
and Protected Virtual Address mode.
i Real Address Mode: The ability to run an existing software base is the key to
commercial processor design. Therefore the existing 8086 code, even at the binary
object level can run unchanged on the 80286. The 80286 mode that provides binary
compatibility is the Real Address Mode.
In this mode, all programs addresses are physical or real addresses and 80286
addresses 1MB memory space and are virtually identical to the 8086. The real address
mode emulates a very high performance 8086 – two-and-a-half times the performance of
8086, running at exactly the same clock frequency or about three-and-a-half times the
performance of 8088, running at exactly the same clock frequency. The multiply-intensive
and the divide-intensive code will execute with five times the performance it exhibited on
an 8086.
In this mode, the CPU behaves functionally as an 8086 and none of the 286’s advanced
architectural features i.e., virtual memory, multitasking, or protection, is available. The
instruction set available is however, a superset of 8086 as shown in Figure 4.3.4.
Figure 4.3.4 also shows the program’s addresses are physical memory addresses,
just as in 8086. The datatypes understood by an 80286 in the Real modem are those
recognized by 8086 – signed and unsigned bytes, signed and unsigned words, 32-bit
pointers, 16-bit and 8-bit offsets. When an 80287 floating-point coprocessor is in place,
all 8087 numeric datatypes such as integers, floating-point and BCD are also available.
The 8086 operates in the Real Mode by default. Hence immediately after reset, it
executes code in Real Address Mode, and continues until software loads a particular code
into one of the processor’s new system registers.

ADDRESS SPACE NOTES

16 Mbyte Physical
1 Gigabyte per Task Virtual
1 Mbyte 1 Mbyte
Physical Physical
8086 80286 REAL

ADDRESS MODE
80286 PROTECTED,
VIRTUAL ADDRESS MODE
INSTRUCTION SET
EC
ROT TED M
6 P I N S T R U CT O
28 TE M IO
DE S
SY 0 S
HA N C E
8
N
EN O T H M
US E
EN S
6
8018
R
PL
TS
BASIC BASIC BASIC
SET SET SET
8086
80286 REAL
ADDRESS MODE
80286 PROTECTED,
VIRTUAL ADDRESS MODE
Figure 4.3.4 Relation of 8086, 80286 Real Mode and
80286 Protected Virtual Address Mode
(ii) Protected Virtual Address mode: The additional capabilities of the 80286, in addition
to running existing software, are available while operating the CPU in its fully featured
mode, namely the Protected Virtual Address Mode. This is the native mode of operation
for the 80286. It is possible to enable this protected mode and use all features of 80286,
under software control.
The Protection Enable bit (PE) in the Machine Status Word (MSW), a system register
in 80286, is used to control the mode of operation by software means. Once the Protected
mode of the 80286 is enabled, the next step is to do the same for its coprocessor, using
appropriate instruction, namely FSETPM.
Figure 4.3.5 shows the transition between the two operational modes of 80286 and
its coprocessor. It can be observed that the transition from Protected Mode back to Real
Mode is via hardware Reset.

DMC 1932
NOTES SYSTEM PROGRAM

SETS “PE” BIT = 1
POWER-ON REAL PROTECTED

MODE MODE
HARDWARE
RESET
(80286 PIN 29)
80286 MODE TRANSITIONS
SYSTEM PROGRAM
EXECUTIES “FSETPM”
POWER-ON REAL PROTECTED

MODE MODE*
HARDWARE *INSTRUCTION POINTER AND DATA

RESET OPERAND POINTER STORED IN VIRT-
(80287 PIN 35) UAL ADDRESS FORMAT (I.E. SELEC-
TOR: OFFSET). RATHER THAN AS
PHYSICAL ADDRESS
80287 MODE TRANSITIONS
Figure 4.3.5 Mode Transition for 80286 and 80287
The Protected Mode is a superset of the Real Mode, but with memory management
unit (MMU) enabled. In this mode, it addresses 16 MB memory space. If an 80286 is
operating in its protected virtual address mode, the address unit functions as a complete
MMU. In this address mode the 80286 uses all 24 address lines to access up to 16
Mbytes or physical memory. In protected mode it also provides up to a gigabyte of
virtual; memory using the descriptor table scheme.
When in Protected Mode, the MMU requires several address mapping tables to
exist in memory, which help in address translation. The memory-mapping tables hold
descriptive information which helps in multitasking and in protection operations.
Descriptors are special entries recognized by 80286 on-chip MMU in the Protected
Mode. These descriptors as shown in Figure 4.3.6, are references automatically to reach
the destinations of inter-segment JMP, CALL or INT instructions and Interrupt Service
Routines (ISRs).

7 0 7 0
NOTES
+7 INTEL RESERVED* +6
MUST BE SET TO O FOR COMPATIBILITY WITH IAPX 386.
ACCESS RIGHTS BYTE

+5 BASE +4
P DPL 1 TYPE A 23-16
+3 BASE 15-0 +2
+1 LIMIT 0
15-0
15 8 7 0
P = PRESENT
DPL = DESCRIPTOR PRIVILEGE LEVEL
TYPE = SEGMENT TYPE AND ACCESS INFORMATION
A = ACCESSED
SEGMENT DESCRIPTOR (8 BYTES). THE NECESSARY SEGMENT DESCRIPTORS

FOR YOUR SOFTWARE ARE AUTOMATICALLY GENERATED BY 80286 UTILITY
PROGRAMS.
Figure 4.3.6 A memory descriptor

The 80286 MMU views the descriptors as special datatypes and performs the
appropriate activity depending on the information content of the descriptor. , referring a
memory reference descriptor could perform a normal transfer of control, as JMP, CALL
etc. On the other hand, it is possible to cause 80286 toperform a task switch using a
special type descriptor.
Have you understood?

Q4.3.a What is the size of the physical and virtual memory in 80286?
Q4.3.b What is the size of the virtual memory that is addressed by 80286, when the
memory manager is in use?
Q4.3.c What are the differences or advancements in 80286 as compared to 8086?
Q4.3 d List the pins in 80286 that are used with a coprocessor.
Q4.3.e What can you say about the TEST pin in 8086 and BUSY pin in 80286?
Q4.3.f What are the functional blocks in the internal architecture of 80286?
Q4.3.g Give the role of each functional block namely, the address unit (AU), the bus unit
(BU) the Execution unit (EU) and the Instruction unit (IU), in 80286.
4.4 INTEL 80386 MICROPROCESSOR

The 80386 microprocessor is a full 32-bit version of 8086 and 80286 16-bit
microprocessors. 80386 features multitasking, memory management, virtual memory with
and without paging, software protection and a large memory system.

DMC 1932
The amount of physical memory addressable by 80386 is 4GB and virtual address
NOTES space is 64Terabyte. 80386 can switch between protected mode and real mode without
resetting the microprocessor. Switching from protected mode to real mode was a burden
since it required a hardware reset.
The 80386 has 32-bit general and offset registers, a 16-bit pre-fetch queue, 32-bit
address and data bus. It can operate in real, protected and virtual 8086 modes. It has i347
numerical coprocessor with IEEE standard 754-1985 for floating point arithmetic.
The performance improvement of the 80386 is primarily due to its expanded bus
width, prefetch queue, numeric coprocessor and generally improved instruction set.
80386 and Pentium support three operating modes: protected, real-address and
system management modes. Details of these are given in the section on Pentium.
4.4.1 80386 Architecture:
The internal architecture is divided into three parts: central processing unit (CPU),
memory management unit (MMU) and bus interface unit (BIU), as shown in Figure 4.4.1.
The CPU is further divided into Execution Unit (EU) and Instruction Unit (IU). EU has 8
general purpose and 8 special purpose registers which are either handling data or for
calculating offset addresses.
Address
Addressing Unit
(AU)
Bus Unit (BU)
Prefetch Queue
Execution Unit (EU) Data
ALU
Control Instruction Unit (IU)

Unit (CU)
Registers
Figure 4.4.1 Internal Block diagram of 80386
Figure 4.4.2 shows the details of the internal architecture of 80386 microprocessor.

PAGING UNIT
BUS CONTROL
NOTES
SEGMENTATION UNIT REQUEST
PRIORITIZER HOLD
INTR, NMI,
3-INPUT ADDER ERROR,
ADDER BUSY,
PHYSICAL ADDRESS BUS

EFFECTIVE ADDRESS BUS
RESET,
CONTROL
DESCRIPTOR HLDA
PAGE CACHE
REGISTER
LIMIT AND CONTROL AND

ATTRIBUTE ATTRIBUTE
LINER ADDRESS BUS

PLA PLA BE0# - BE3#
EFFECTIVE ADDRESS BUS
A0-A11
ADDRESS
DRIVER M/IO#, D/C#
BUS
W/R#, LOCK#,
CODE FETCH
PAGE FETCH
PIPELINE/ ADS#, NA#
INTERNAL CONTROL BUS BUS SIZE
CONTROL BS10 #, READY#
PROJECTION
TEST UNIT MUX /
TRANS- D0-D31
DISPLACEMENT
RECIVERS
PERFECTCHER/
LIMIT
CHECKER
BARREL INSTRUCTION
SHIFTER, DECODE AND DECODER
ADDER SEQUENCING
STATUS
FLAGS CODE
MULTIPLY/ STREAM 16 BYTE
DIVIDE CODE
3-DECODED
CONTROL INSTRUCTION
ROOM QUEUE
REGISTER FILE
ALU INSTRUCTION
CONTROL CONTROL INSTRUCTION PREFETCHER
ALU
PREDECODE
DEDICATED ALU BUS
Figure 4.4.2 Internal architecture of 80386
The Instruction unit decodes the opcode bytes received from the 16-byte instruction
code queue and arranges them in a 3- instruction decoded instruction queue. After decoding
them pass it to the control section for deriving the necessary control signals. The barrel
shifter increases the speed of all shift and rotate operations. The multiply / divide logic
implements the bit-shift-rotate algorithms to complete the operations in minimum time.
Even 32- bit multiplications can be executed within one microsecond by the multiply /
divide logic.
The Memory management unit consists of Segmentation unit and Paging unit.
Segmentation unit allows the use of two address components, viz. segment and offset for
relocability and sharing of code and data. Segmentation unit allows segments of size 4Gbytes
at max. The Paging unit organizes the physical memory in terms of pages of 4kbytes size
each. Paging unit works under the control of the segmentation unit, i.e. each segment is
further divided into pages. The virtual memory is also organizes in terms of segments and
pages by the memory management unit.
The Bus control unit has a prioritizer to resolve the priority of the various bus requests.
This controls the access of the bus. The address driver drives the bus enable and address
signal A0 – A31. The pipeline and dynamic bus sizing unit handle the related control signals.
The data buffers interface the internal data bus with the system bus.

DMC 1932
Instruction set upward compatible to its predecessors. New instructions deal with
NOTES protection mechanism, memory segmentation and paging MMU. The Memory Management
Unit (MMU) provides virtual memory, paging and four levels of protection. The concept
of paging enables it to organize available physical memory in terms of pages of 4K under
segmented memory.
Prefetch queue: helps in two ways: (i) The instruction fetch unit can read from the pre-
fetch queue faster then from memory. (ii) The pre-fetcher can do some work in parallel,
while the execution unit is doing some other task.
Address Bus
2X CLOCK CLK2 A2-A31
BE3# 32-BIT
32-BIT Data Bus BE2# BYTE ADDRESS
DATA D0 - D31 BE1# EN
Intel 386TM DX BE0#
Microprocessor
ADS# WR#
BUS NA# D/C#
CONTROL BS16# M/IO# BUS CYCLE DEFINITION
READY# LOCK#
HOLD PEREO
BUS
HLDA BUSY# COPROCESSOR SIGNALING
ARBITRATION
ERROR#
INTR
NMI Vcc
INTERRUPTS POWER CONNECTIONS
RESET GND
Figure 4.4.3 Block Diagram showing the Signals in 80386
4.4.2 80386 Register Organization:
The 80386 has eight 32-bit general purpose registers as shown in Figure 4.4.4, which
may be used as either 8 bit or 16 bit registers. A 32-bit register known as an extended
register, is represented by the register name with prefix E. Example: A 32 bit register
corresponding to AX is EAX, similarly BX is EBX etc. The 16 bit registers BP, SP, SI and
DI in 8086 are now available with their extended size of 32 bit and are names as EBP,
ESP, ESI and EDI. AX represents the lower 16 bit of the 32 bit register EAX. BP, SP, SI,
DI represents the lower 16 bit of their 32 bit counterparts, and can be used as independent
16 bit registers. The six segment registers available in 80386 are CS, SS, DS, ES, FS and
GS. The CS and SS are the code and the stack segment registers respectively, while DS,
ES, FS, GS are 4 data segment registers. A 16-bit instruction pointer (IP) is available
along with 32 bit counterpart EIP.
80386 has two additional data segment registers – FS and GS. 80386 has six segment
registers (i) One for current code segment (CS), (ii) One for current stack (SS) and (iii)
Four for general data segments (DS,ES,FS,GS).

Instruction Pointer
31 16 15 0
EFLAG Register
31 16 15 E0 NOTES
EIP IP EFLAG FLAG
General-Purpose Registers Segment Register

31 16 15 8 7 0
15 0
EAX AH AL CS
EBX BH BL SS
ECX CH CL DS
EDX DH DL ES
ESI SI FS
EDI DI GS
EBP BP
ESP SP
Figure 4.4.4 Register organization in 80386
Figure 4.4.5 shows the special purpose registers namely, Control, Debug and Test
registers in 80386. There are four control and four memory management registers for
protected mode, and eight Debug registers. These registers are useful in multitasking. The
debug registers are useful in locating errors in a given task.
4.4.2.1 Control Registers (CR0-CR3)
CR1 is left undefined. CR0 holds the status word machine (MSW) consisting of PE
(Protection Enable), MP (Math Present), EM (Emulate Co-processor), TS (Task
Switched), ET (Extension type) and PG ( Paging). CR2 is read-only which gives the last
32 bit address that caused page fault. CR3 is the Page Directory Base Register.
4.4.2.2 Debug Registers (DR0-DR7)
DR0-DR3 hold upto four linear address breakpoints. The addresses in registers are
compared with processors address generation logic on every instruction and if match is
found an exception 1 (debug fault) is generated. The debug address registers are effective
whether or not paging is enabled. DR4 and DR5 are undefined. DR6 and DR7 hold the
parameters for debugging, such as LEN: Break point length, BD: Break for debug register
access, BS: Break for single step, BT: Break for task switch, etc.
4.4.2.3 Test Registers (TR6 and TR7)
The test registers are used to perform confidence checking on the paging MMU’s
translation look aside buffer (TLB).By writing into this register one can initiate write directly
into 80386 TLB or perform a mock TLB lookup. TR6 is test command register and TR7
is test data register.

DMC 1932
NOTES TR
15
T S S Selector
0 31
T S S Base Address
0 19
T S S Limit
0
LDTR L D T S S Selector L D T Base Address L D T Limit

IDTR I D T Base Address I D T Limit
GDTR G D T Base Address G D T Limit
Control Registers Debug Registers

31 16 15 0 31 16 15 0
CR3 DR7
CR2 DR6
CR1 DR5
CR0 DR4
DR3
Test Registers
DR2
31 16 15 0
TR7 DR1
TR6 DR0
Figure 4.4.5 Special purpose registers in 80386
4.4.2.4 Memory Management Registers (Associated with Protection):
1. GDTR: Global Descriptor Table Register. 48 bit register.
2. IDTR: Interrupt Descriptor Table Register. 48 bit register.
3. LDTR: Local Descriptor Table Register. 16 bit register.
4. TR: Task Register. 16 bit register.
GDTR and LDTR points to the segment descriptor tables, namely, GDT and LDT.
IDTR points to the table of entry points for interrupt handlers. TR points to the information
needed by the processor to define the current task.
80386 provides a mechanism where by system programmer defines what each segment
will be. Definition includes starting address, its length, its intended use and other attributes.
A segment is described by a special structure called Segment descriptor. You can create
as many segment descriptors you want. The segment descriptors that you defined must be
grouped and placed one after another in continuous memory locations. This group
arrangement is known as descriptor table. Three types of descriptor tables.
ii GDTR: This register maintains list of most segments. It is a general purpose table of
descriptors. It may contain special system descriptor.
iii IDTR: This maintains list of Interrupt service routines.
iv Local Descriptor Table Register (LDTR): LDT is extension of GDT, but assigned to
individual task. LDT’s are created exactly like GDT’s and IDT’s. The LDTR refers to
special LDT in GDT. An LDT in GDT defines the base address and limit of another
descriptor table, i.e. an LDT. The GDT may contain any numbers of LDT descriptor.

Task State Segment (TSS): This is the context store. The task’s vital information is
stored when the task is not running. This information is used by 386 to restart the task. NOTES
TSS is not available to general user program.
Task Register (TR): This is a 16-bit processor register. It always holds the selector
for the current task. The old task state is saved in current TSS and the new TSS selector
is stored in task register.
Have you understood Questions?
Q4.4.a What are the functional blocks in the internal architecture of 80286?
Q4.4.b Give the role of each functional block namely, the address unit (AU), the
bus unit (BU) the Execution unit (EU) and the Instruction unit (IU), in 80286.
Q4.4.c Describe the registers in 80386.
Q4.4.d List the memory segments in 80386.
Q4.4.e What is multitasking and how does the 80386 architecture support
multitasking?
Q4.4.f Expand the following acronyms: TSS, IDT, GDT, LDTR, and IDTR.
4.5 INTEL 80486 MICROPROCESSOR
80486DX is the first CPU with an on chip floating-point unit. For fast execution of
complex instructions of xxx86 family, the 80486 has introduced five stage pipelines. Two
out of the five stages are used for decoding the complex instructions of xxx86 architecture.
This feature, which has been, used widely in RISC architectures results in very fast instruction
execution. The 80486 is also the first amongst the xxx86 processor to have an on-chip
cache. This 8Kbytes cache is a unified data and code cache and acts on physical addresses.
4.5.1 80486 Architecture
The 32-bit pipelined architecture of Intel’s 80486 is shown in Figure 4.5.1. The
internal architecture of 80486 can be broadly divided into three sections, namely bus
interface unit, execution and control unit and floating point unit.
The bus interface unit is mainly responsible for coordinating all the bus activities. The
address driver interfaces the internal 32-bit address output of cache unit with the system
bus. The data bus transreceivers interface the internal 32-bit data bus with the system bus.
The 48X80 write data buffer is a queue of four 80-bit registers, which hold the 80-bit data
to be written to the memory. The bus control and request sequences handles the signals
like ADS#, W/R#, D/C#, M/IO#, PCD, PWT, RDY#, LOCK#, PLOCK#, BOFF#,
A20M#, BREQ, HOLD, HLDA, RESET, INTR, NMI, FERR# and IGNNE# which
basically control the bus access and operations.

DMC 1932
The burst control signal BRDY# informs the processor that the burst is read. The
NOTES BLAST# output indicates to the external system that the previous burst cycle is over. The
bus size control signals BS16# and BS8# are used for dynamic bus sizing. The cache
control signals KEN#, FLUSH, AHOLD and EADS# control and maintain the in
coordination with the cache control unit. The parity generation and control unit maintain
the parity and carry out the related checks during the processor operation. The boundary
scan control unit, that is built in 50MHZ and advanced versions only, subject the processor
operation to boundary scan tests to ensure the correct operation of various components of
the circuit on the mother board, provided the TCK input is not tied high.
32-BIT DATA BUS
32-BIT DATA BUS

LINEAR ADDRESS BUS
BUS INTERFACE
PBO#
ADDRESS A2 - A31,
BARREL SEGMENTATION PB1# DRIVERS BEO# - BE3#
UNIT CACHE UNIT
SHIFTER PAGING
UNIT PHYSICAL
DESCRIPTOR ADDRESS
REGISTER FILE REGISTERS D0 - D31
BASE/ BK BYTE
DATA BUS
INDEX LIMIT AND TRANSLATION TRANSCEIVERS
CACHE
ALU BUS ATTRIBUTE LOOKASIDE
PLA BUFFER
BUS CONTROL CONTROL

120
MICRO-
INSTRUCTION DISPLACEMENT BUS
PREFETCHER
32-BYTE CODE
QUEUE
CONTROL
FLOATING DECODE
POINT CONTROL
UNIT UNIT
DECODED
INSTRUCTION
F.P. REGISTER PATH
FILE CONTROL
ROM
Figure 4.5.1 Intel 80486 Microprocessor 32-bit pipelined architecture
The prefetcher unit fetches the codes from the memory ahead of execution time and
arranges them in a 32-byte code queue. The instruction decoder gets the code from the
code queue and then decodes it sequentially. The output of the decoder drives the control
unit to derive the control signals required for the execution of the decoded instructions.
But prior to execution, the protection unit checks, if there is any violation of protection
norms. If any protection norm is violated, an appropriate exception is generated. The
control ROM stores a microprogram for deriving control signals for execution of different
instructions. The register bank and ALU are used for their conventional usages. The
barrel shifter helps in implementing the shift and rotate algorithms. The segmentation
unit, descriptor registers, paging unit, translation look aside buffer and limit and attribute
PLA work together to manage the virtual memory of the system and provide adequate
protection to the codes or data in the physical memory. The floating-point unit with its
register bank communicates with the bus interface unit under the control of memory
management unit, via its 64-bit internal data bus. The floating-point unit is responsible for
carrying out mathematical data processing at a higher speed as compared to the ALU,
with its built in floating-point algorithms.

The 80486 implements a 5-stage instruction pipeline: Prefetch, Decoding 1, Decoding
2, Execution, and Register write.The 80486 is not a RISC processor, since it must be SW NOTES
compatible with previous Intel processors.
4.5.2 Signal Descriptions of 80486
Timing Sigel CLK: This input provides the basic system timing for the operation of
80486.
Address Bus: A31- A2 These are the address lines of the microprocessor, and are
used for selecting memory I/O devices. However, for memory/IO addressing we also
need another set of signals known as byte enable signals BE0 – BE3. These active-low
byte enable signals (BE0# - BE3#) indicate which byte of the 32-bit data bus is active
during the read or write cycle.
Data Bus: D0-D31 This is bi-directional data bus with D0 as the least and D31 as the
most significant data bit.
Data Parity Group: The pins of this group of signals are extremely important, because
they are used to detect the parity during the memory read and write operations.
DP0-Dp3: These four data parity input/output pins are used for representing the
individual parity of 4bytes (32bits) of the data bus.
M/IO#: This output pin differentiates between memory and I/O operations.
D/C#: This output pin differentiates between data/control operations.
W/R#: This output pin differentiates between read and write bus cycle.
PLOCK#: This pseudo lock pin indicates that the current operation may require
more than one bus cycle for its completion. The bus is to be locked until then.
LOCK#: This output pin indicates that the current bus cycle is locked.
ADS#: The address status output pin indicates that a valid bus cycle definition and
addresses are currently available on the corresponding pins.
RDY#: This input pin acts as a ready signal for the current non-burst cycle.
BRDY# & BLAST#: refer Architecture of 80486
RESET: This input pin reset the processor, if its goes high
INTR: This is a maskable interrupt input that is controlled by the IF in the flag register
NMI: This is a non-maskable interrupt input, of type 2.

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BREQ: This active high output indicates that the 80486 has generated a bus request.
NOTES
HOLD: This pin acts a a local bus hold input, to be activated by another bus master
like DMA controller, to enable to gain the control of the system bus.
HLDA: This is an output that acknowledges the receipt of a valid HOLD request.
BOFF#: When a CPU requests the access of the bus, and if the bus is granted to it,
then the current bus master which is currently in charge of the bus will be asked to back off
or release the bus.
AHOLD: The address holds request input pin enables other bus masters to use the
80486 system bus during a cache invalidation cycle.
EADS#: The external address input signal indicates that a valid address for external
bus cycle is available on the address bus.
KEN#: The cache enable input pin is used to determine whether the current cycle is
cacheable or not.
FLUSH#: The cache flush input, if activated, clears the cache contents and validity
bits.
PCD, PWT: The page cache disables and page write-through output pins reflect the
status of the corresponding bits in page table or page directory entry.
FPU: Error Group
FERR: The FERR output pin is activated if the floating point unit reports any error.
IGNNE: If ignore numeric processor extension input pin is activated, the 80486
ignores the numeric processor errors and continues executing non-control floating-point
instructions.
BS8# and BS16#: The bus size-8 and bus size-16 inputs are used for the dynamic
bus sizing feature of 80486. These two pins enable 80486 to be interfaced with 8-bit or
16-bit devices though the CPU has a bus width of 32-bits.
A20M3: If this input pin is activated, the 80486 masks the physical address line A20
before carrying out any memory or cache cycle.
Test Access Port Group: This is a unique facility available in 80486, which enables it
to check the fault conditions of the other on-board components. This is invoked using the
JTAG instruction.
TCK: The test clock input provides the basic clock required by the boundary scan
feature.

TDI: The test data input is the serial input used to shift the JTAG instructions and data
into the component. NOTES
TDO: The test data output is the serial output pin used to shift the JTAG instruction
and data out of the component under test. The TDI and TDO are sampled or driven
during the SHIFT-IR and SHIFT-DR TAP controller states.
TMS: The test mode select input is decoded by the JTAG TAP ( tap access port) to
select the operation of this test logic.
Vcc: In all 24 pins are allocated for the power supply.
Vss: These act as return lines for the power supply. In all 28 pins are allocated for the
power supply return lines.
N/C: No connection pins are expected to be left open while connecting the 80486 in
the circuit.
Addressing Modes: The addressing modes supported by 80486 are exactly the same
as those of 80386.
Data types of 80486: The 80486 CPU supports a wide range of data types including
the floating-point data types, as listed briefly.
1. Signed/unsigned data type : 8-bit, 16-bit, 32-bit signed and unsigned integers are
supported by 80486 while the FPU supports 16-bit, 32-bit and 64-bit signed data.
2. Floating Point data types: Single precision, double precision, extended precision real
data are supported only by the FPU.
3. BCD Data types: Packed and unpacked BCD data types. The CPU supports 8-bit
packed and unpacked data types. The FPU supports 80-bit packed BCD data types.
4. String Data Types: String of bits, bytes, words and double words are supported by the
CPU. Each of the strings may contain upto 4Gbytes.
5. ASCII Data Types: The ASCII representation of the characters is supported by80486.
6. Pointer Data Types: 48-bit pointers containing 32-bit offset at the least significant bits
and 16-bit selector at the most significant bits are supported by the CPU. Also 32-bit
pointers containing 32bit offsets are supported by the CPU.
7. Little Endian and Big Endian data types: The 8086 family uses Little Endian data
format normally. This means for a data of size bigger than one byte, the least significant
byte is stored at the lowest memory address while the most significant byte is stored at
the highest memory address. A complete data is referred to by the lowest memory
address, i.e. the address of the least significant byte. The Big Endian format allows the
storage of data in the exactly opposite manner, i.e. the MSB is stored at the lowest
memory address, while the LSB is stored at highest memory address.

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Have you understood Questions?

NOTES Q4.5.a What is meant by RISC?
Q4.5.b What are the functions of (i) prefetcher, (ii) cache, (iii) instruction decode
unit and (iv) memory management unit, in 80486?
Q4.5.c Distinguish between little and big endian data types. Which one does 80486
support?
Q4.5.d Describe the pins associated with DMA in 80486.
Q4.5.e Which pin in 80486 helps to check the fault conditions of the other on-
board component?
4.6 INTEL PENTIUM PROCESSOR
The Pentium family of processors originated from the 80486 microprocessor and the
first Pentium processors were introduced in 1993. The term ‘’Pentium processor’’ refers
to a family of microprocessors that share a common architecture and instruction set. It runs
at a clock frequency of either 60 or 66 MHz and has 3.1 million transistors. The Pentium
(P54C) was released in 1994 and was the first to use a multiplier to give processor speeds
of 75, 90,100,120,133, 150, 166 and 200 MHz. The last version of the first member of
this sub-generation was the Pentium MMX (P55C) having 4.1 million transistors.
4.6.1 Pentium Architecture
Figure 4.6.1 shows the superscalar architecture of the Pentium processors and Figure
4.6.2 shows the internal architecture of Pentium.
Code Cache Branch Prediction

8 KB
Pre-fetch Buffer Pipelined Floating

Memory U Pipe V Pipe Point Unit
Interface
Integer ALU Integer ALU
Register Set
Multiplier
Adder
8 KB
Data Cache Divider
Figure 4.6.1 Superscalar Architecture of Pentium

NOTES
64 bit Data Bus 32 bit Address Bus Control Bus
Bus Interface Unit
I-Cache (8KB) TLB D-Cache (8KB) TLB
Brach Target Buffer Clock

Multiplier
Prefetch Buffer
Microcode
Fetch and Decode Unit
ROM
Dual Pipeline
Execution Unit
Control Unit
U-Pipeline V-Pipeline
Floating Point
Unit
ALU ALU
Advanced
Registers Programmable
Interrupt
Controller
Figure 4.6.2 Internal Architecture of the Pentium Processor
Some of the features of Pentium architecture are

 Superscalar Execution: The Intel486 processor can execute only one instruction at a
time. With superscalar execution, the Pentium processor can sometimes execute two
instructions simultaneously.
 Pipeline Architecture: Like the Intel486 processor, the Pentium processor executes
instructions in five stages. This staging, or pipelining, allows the processor to overlap
multiple instructions so that it takes less time to execute two instructions in a row.
Because of its superscalar architecture, the Pentium processor has two independent
processor pipelines.
o Pre-fetch/Fetch: Instructions are fetched from the instruction cache and aligned in
pre-fetch buffers for decoding.

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o Decode1: Instructions are decoded into the Pentium’s internal instruction format.
NOTES Branch prediction also takes place at this stage.
o Decode2: Same as above, and microcode ROM kicks in here, if necessary. Also,
address computations take place at this stage.
o Execute: The integer hardware executes the instruction.
o Write-back: The results of the computation are written back to the register file.
 Branch Target Buffer: The Pentium processor fetches the branch target instruction
before it executes the branch instruction.
 Dual 8-KB On-Chip Caches: The Pentium processor has two separate 8-kilobyte
(KB) caches on chip—one for instructions and one for data—which allows the Pentium
processor to fetch data and instructions from the cache simultaneously.
 Write-Back Cache: When data is modified; only the data in the cache is changed.
Memory data is changed only when the Pentium processor replaces the modified data
in the cache with a different set of data
 64-Bit Bus: With its 64-bit-wide external data bus the Pentium processor can handle
up to twice the data load of the Intel486 processor at the same clock frequency.
 Instruction Optimization: The Pentium processor has been optimized to run critical
instructions in fewer clock cycles than the Intel486 processor.
 Floating-Point Optimization: The Pentium processor executes individual instructions
faster through execution pipelining, which allows multiple floating-point instructions to
be executed at the same time.
 Pentium Extensions: The Pentium processor has fewer instruction set extensions than
the Intel486 processors. The Pentium processor also has a set of extensions for
multiprocessor (MP) operation. This makes a computer with multiple Pentium
processors possible.
Operating modes: The Pentium processor has two primary operating modes -
 Protected Mode - In this mode all instructions and architectural features are
available, providing the highest performance and capability. This is the recommended
mode that all new applications and operating systems should target.
 Real-Address Mode - This mode provides the programming environment of the
Intel 8086 processor, with a few extensions. Reset initialization places the processor
in real mode where, with a single instruction, it can switch to protected mode.
 System Management Mode - The Pentium microprocessor also provides support
for System Management Mode (SMM). SMM is a standard architectural feature
unique to all new Intel microprocessors, beginning with the Intel386 SL processor,
which provides an operating-system and application independent and transparent
mechanism to implement system power management and OEM differentiation
features. SMM is entered through activation of an external interrupt pin (SMI#),
which switches the CPU to a separate address space while saving the entire context
of the CPU. SMM-specific code may then be executed transparently. The operation
is reversed upon returning.

Figure 4.6.3 shows the transitions between the operating modes. Note, PE is in CR0
and VM is in EFLAGS. NOTES
Real-Address
Mode SMI#
Reset
or
Reset or PE=1 RSM
PE=0
SMI# System
Reset Protected Mode Management
RSM Mode
VM=0 VM=1
SMI#
Virtual-8086
Mode
RSM
Figure 4.6.3 Operating modes of Pentium processor

1. The Pentium processor fetches the branch target instruction before it executes the
branch instruction.
2. Caches: The Pentium processor has two separate 8-kilobyte (KB) caches on chip,
one for instructions and one for data. It allows the Pentium processor to fetch data and
instructions from the cache simultaneously.
 When data is modified, only the data in the cache is changed. Memory data is
changed only when the Pentium processor replaces the modified data in the cache
with a different set of data
3. Floating Point Unit: There are 8 general-purpose 80-bit Floating point registers.
Floating point unit has 8 stages of pipelining. First five are similar to integer unit. Since
the possibility of error is more in Floating Point unit (FPU) than in integer unit, additional
error checking stage is there in FPU.
4. The Pentium processor has been optimized to run critical instructions in fewer clock
cycles than the 80486 processor.
5. Upward code compatibility.
The most important enhancements over the 486 are the separate instruction and data
caches, the dual integer pipelines (the U-pipeline and the V-pipeline, as Intel calls them),
branch prediction using the branch target buffer (BTB), the pipelined floating-point unit,
and the 64-bit external data bus. Even-parity checking is implemented for the data bus and
the internal RAM arrays (caches and TLBs).

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Pentium is the first high-performance micro-processor to include a system management

NOTES mode. Pentium uses about 3 million transistors. The caches plus TLBs use only about 30%
of the die. In contrast to other superscalar designs, such as SuperSPARC, Pentium’s
integer data path is actually bigger than its FP data path. Intel estimates about 30% of the
transistors were devoted to compatibility with the x86 architecture. Much of this overhead
is probably in the microcode ROM, instruction decode and control unit, and the adders in
the two address generators, but there are other effects of the complex instruction set. For
example, the higher frequency of memory references in x86 programs compared to RISC
code led to the implementation of the dual-ac.
Pentium Pro: The Pentium Pro was designed around a the 6th generation P6 architecture,
which was optimized for 32 bit instructions and 32-bit operating systems such as Windows
NT and Linux. It was the first of the P6 family, which included the Pentium II, the Celeron
variants, and the Pentium III. It was aimed at the server market and the Pentium Pro did
not incorporate MMX technology. It was expensive to produce as it included the L2
cache on its substrate (but on a separate die) and had 5.5 million transistors at its core and
over 8 million in its L2 cache. Its core logic operated at 3.3Volts. The microprocessor was
still, however, chiefly CISC in design, and optimized for 32 bit operation. The chief features
of the Pentium Pro were:
 A partly integrated L2 cache of up to 512 KB (on a specially manufactured SRAM
separate die) that was connected via a dedicated ‘backside’ bus that ran at full
CPU speed.
 Three 12 staged pipelines
 Speculative execution of instructions
 Out-of-order completion of instructions
 40 renamed registers
 Dynamic branch prediction
 Multiprocessing with up to 4 Pentium Pros
 An increased bus size to 36 bits (from 32) to enable up to 64 Gb of memory to be
used.
Pentium II: The Pentium II incorporated many of the salient features of the Pentium Pro
and Pentium MMX; however, its physical package was based on the SECC/Slot 1 interface
and its 512 KB L2 cache ran at only half the processor internal clock rate. First generation
Pentium II Klamath CPUs operated at 233, 266, 300 and 333MHz with a FSB of 66MHz
and a core voltage of 2.8 Volts. In 1998, Intel introduced the Pentium II Deschutes that
operated at a speed of 350, 400 and 450 MHz with a 100 MHz, and later 66MHz, FSB
and at 2.0 Volts at the core. Its major improvements were:
 16 Kb L1 instruction and data caches

 L2 cache with non-proprietary commercially available SRAM
 Improved 16 bit capability through segment register caches
NOTES
 MMX unit.
 Standard Pentium II could only be used in dual multiprocessor configurations;
however, Pentium Xeon Processors had up to 2 MB of L2 cache and could be
used in multiprocessor configurations of up to 4 processors.
4.6.2 Pentium Register Organisation
The Pentium register set is the same as i386 including additional ones. Figure 4.6.4
shows the registers in the Pentium architecture.
There are 4 32-bit registers general-purpose registers: EAX, EBX, ECX and EDX,
which can be used as AX, BX, CX or DX, in 16-bit mode or as AH+AL, BH+BL,
CH+CL and DH+DL, in the 8-bit mode. The 32-bit memory pointers are EBP, ESI, EDI
and ESP while the 16-bit memory pointers are BP, SI, DI and SP. CS, SS, DS, ES, FS,
and GS are the 16-bit segment registers.
Instruction Pointer EFLAG Register
31 16 15 0 31 16 15 E0
EIP IP EFLAG FLAG
General-Purpose Registers
Segment Registers
31 16 15 8 7 0
15 0
EAX AH AL
CS
EBX BH BL
SS
ECX CH CL
DS
EDX DH DL
ES
ESI SI
FS
EDI DI
GS
EBP BP
ESP SP
15 0 31 0 19 0
TR TSS Selector TSS Base Address TSS Limit
LDTR LDTSS Selector LDT Base Address LDT Limit
IDTR IDT Base Address IDT Limit
GDTR GDT Base Address GDT Limit

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Control Registers Debug Registers

NOTES 31 16 15 0 31 16 15 0
CR4 DR7
CR3 DR6
CR2 DR5
CR1 DR4
CR0 DR3
DR2
Test Registers
31 16 15 0
DR1
TR12
DR0
TR7
TR6
Figure 4.6.4 Pentium Register Organisation

The 32-bit registers are named with prefix E, EAX, etc, and the least 16 bits 0-15 of
these registers can be accessed with names such as AX, SI Similarly the lower eight bits
(0-7) can be accessed with names such as AL & BL. The higher eight bits (8-15) with
names such as AH & BH. The instruction pointer EAP known as program counter(PC) in
8-bit microprocessor, is a 32-bit register to handle 32-bit memory addresses, and the
lower 16 bit segment IP is used for 16-bi memory address.
The flag register is a 32-bit register, however 14-bits are being used at present for 13
different tasks; these flags are upward compatible with those of the 8086 and 80286. The
comparison of the available flags in 16-bit and 32-bit microprocessor is may provide
some clues related to capabilities of these processors. The 8086 has 9 flags, the 80286
has 11 flags, and the 80286 has 13 flags. All of these flag registers include 6 flags related to
data conditions (sign SF, zero ZF, carry CF, auxiliary carry AF, overflow OF, and parity
PF) and three flags related to machine operations.(interrupts, Single-step and Strings).
The 80286 has two additional: I/O Privilege and Nested Task. The I/O Privilege uses two
bits in protected mode to determine which I/O instructions can be used, and the nested
task is used to show a link between two tasks.
The processor also includes control registers and system address registers, debug
and test registers for system and debugging operations. There are 5 Control Registers:
CR0-CR4. These are useful for Enabling protection mode, Turning the paging ON/OFF,
Controlling 4M/4K paging and Providing the Page Directory Base Address (CR3 register
is used with extended addressing). There are 8 32-bit debug registers. There are Test
registers.

Summary
NOTES
Table 1-2: Evolution of Intel’s Microprocessors (from the 8086 to the Pentium)
Product 8086 80286 80386 80486 Pentium

Year introduced 1978 1982 1985 1989 1992
Technology NMOS NMOS CMOS CMOS BICMOS
Clock rate (MHz) 3-10 10-16 16-33 25-33 60.66
Number of pins 40 68 132 168 273
Number of transistors 29,000 130,000 275,000 1.2 million 3.1 million
Physical memory IM 16M 4G 4G 4G
Virtual memory None IG 64T 64T 64T
Internal data bus 16 16 32 32 32
External data bus 16 16 32 32 64
Address bus 20 24 32 32 32
Data type (bits) 8.16 8.16 8,16,32 8,16,32 8,16,32
Textbooks
1 Barry B Brey, The Intel Microprocessors 8086/8088, 80186/80188, 80286,

80386, 80486, Pentium, PentiumPro Processor, Pentium II, Pentium III, Pentium
IV, Architecture, Programming and Interfacing”, 6th Edition Pearson Education /
prentice Hall Of India, 2002.
2 A K Ray and K M Bhurchandi, “Advanced Microprocessors and Peripherals –
Architecture, Programming and Interfacing”, Tata McGraw Hill, 2002 Reprint.

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NOTES

NOTES
UNIT V
BUILDING SYSTEMS
5.1 INTRODUCTION
The components inside the computer intercommunicate with each other in various
ways, and one among them is the use of ‘buses’. Most of the internal system components,
including the processor, cache, memory, expansion cards and storage devices, talk to
each other over one or more “buses”.
A bus is a channel over which information flows between two or more devices. A bus
normally has access points, or places into which a device can tap, to become part of the
bus, and devices on the bus can send to, and receive information from, other devices.
In industrial applications, main boards from personal computers are used as core
systems which require custom interfaces attached to one of the buses on the main board.
Hence many applications require the knowledge of the bus systems located within the
personal computer.
This chapter focuses on the system I/O (input/output) buses, also called expansion
buses. First the buses and their characteristics are discussed, and then the most common
types of I/O buses found on the PC are described with details on their features. The PCI
bus and the USB are then described in detail.
 To understand the concept of system buses

 To know the various bus characteristics
 To learn the basic PC buses
 To have a detailed knowledge of PCI bus and USB standard
5.3 BUS CONCEPTS
Based on the proximity to the processor, buses can be identified at different levels.
The various types of PC Buses (or PC Bus Hierarchy) are given below.

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5.3.1 Pc Buses
NOTES
 Processor Bus: This is the highest-level bus that the chipset uses to send information
to and from the processor.
 Cache Bus: Higher-level architectures, such as those used by the Pentium Pro
and Pentium II, employ a dedicated bus for accessing the system cache. This is
sometimes called a backside bus. Conventional processors using fifth-generation
motherboards and chipsets have the cache connected to the standard memory
bus.
 Memory Bus: This is a second-level system bus that connects the memory
subsystem to the chipset and the processor. In some systems the processor and
memory buses are the same.
 Local I/O Bus: This is a high-speed input/output bus used for connecting
performance-critical peripherals to the memory, chipset, and processor. For
example, video cards, disk storage devices, high-speed networks interfaces generally
use a bus of this kind. The two most common local I/O buses are the VESA Local
Bus (VLB) and the Peripheral Component Interconnect Bus (PCI).
 Standard I/O Bus: Connecting to the above three buses is the standard I/O bus,
used for slower peripherals (mice, modems, regular sound cards, low-speed
networking) and also for compatibility with older devices. On almost all modern
PCs this is the Industry Standard Architecture (ISA) bus.
The system chipset is the conductor that controls this orchestra of communication,
and ensures that every device in the system is talking properly to every other one.
Some newer PCs use an additional “bus” that is specifically designed for graphics
communications only. The word “bus” is in quotes because it isn’t actually a bus, it’s a port:
the Accelerated Graphics Port (AGP). The distinction between a bus and port is that a bus
is generally designed for multiple devices to share the medium, while a port is only for two
devices.
5.3.2 Data And Address Buses
Every bus is composed of the data bus, the address bus and the control bus. The data
bus lines carry the data being transferred while the address bus lines is the set of lines that
carry information about where in memory the data is to be transferred to or from, i.e., the
memory address. The control lines carry information that controls the bus functions, and
allow users of the bus to signal when data is available.
5.3.3 Bus Characteristics
(i) Bus Width: The width of a bus is specified as a number (i.e., the number of bits that it
can carry). The wider the bus, the more information can flow over the channel. The original

ISA bus on the IBM PC was 8 bits wide; the universal ISA bus used now is 16 bits. The
other I/O buses (including VLB and PCI) are 32 bits wide. The memory and processor NOTES
buses on Pentium and higher PCs are 64 bits wide.
The address bus width can be specified independently of the data bus width. The
width of the address bus dictates how many different memory locations that bus can transfer
information to or from.
(ii) Bus Speed: The speed of the bus reflects how many bits of information can be sent
across each wire each second. Most buses transmit one bit of data per line, per clock
cycle, although newer high-performance buses like AGP may actually move two bits of
data per clock cycle, doubling performance. Similarly, older buses like the ISA bus may
take two clock cycles to move one bit, halving performance.
(iii) Bus Bandwidth: Bandwidth, also called throughput, is the total amount of data that
can theoretically be transferred on the bus in a given unit of time. Most of the buses can run
at many different speeds; the speed listed is the one most commonly used for the bus type.
The Table 5.1 shows the width, speed and bandwidth of some common buses.
Bus Width Bus Speed Bus Bandwidth
(bits) (MHz) (MBytes/sec)
8-bit ISA 8 8.3 7.9
16-bit ISA 16 8.3 15.9
EISA 32 8.3 31.8
VLB 32 33 127.2
PCI 32 33 127.2
64-bit PCI 2.1 64 66 508.6
AGP 32 66 254.3
AGP (x2 mode) 32 66x2 508.6
AGP (x4 mode) 32 66x4 1,017.3
(iv) Bus Interfacing: On a system that has multiple buses, special circuitry must be provided
by the chipset to connect the buses and allow devices on one to talk to devices on the
other. This device is acing a bridge, is the bus interface. The most commonly found bridge
is the PCI-ISA bridge, which is part of the system chipset on a Pentium or Pentium Pro
PC. The PCI bus also has a bridge to the processor bus. These devices can be seen under
“System devices” in the Device Manager in Windows 95.
(v) Bus Mastering: On the higher-bandwidth buses, a great deal of information flows
through the channel every second, usually controlled by the processor. Alternately, special
devices called bus masters can take control of the bus and do the work themselves.
Currently most bus mastering in the PC world is done on the PCI bus; in addition,
support has been added for IDE/ATA hard disk drives to do bus mastering on PCI under
certain conditions.

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(vi) Plug-and-play interface is one that contains memory to hold configuration information
NOTES for the system.
Have you understood ?
Q5.3.a Distinguish between memory and IO buses.

Q5.3.b Distinguish between bus and port.
Q5.3.c What is AGP - a bus or a port – discuss.
Q5.3.d Describe the functions of data, address and control buses.
Q5.3.e What is (i) bus interfacing (ii) bus mastering?
Q5.3.f What is the need for knowing the operation of system buses?
5.4 BUS STANDARDS
Many applications require the knowledge of the buses and their architecture in order
to effectively communicate with the system components. The bus systems located within
the computer system forms the more essential ones. The hardware application systems,
especially, require custom interfaces attached to the bus systems on the main board of the
computer. In this unit, details of various system IO buses are provided.
5.4.1 System Io Buses
Some of the common system IO buses are
 Industry Standard Architecture (ISA) Bus

 Micro Channel Architecture (MCA) Bus
 Extended Industry Standard Architecture (EISA) Bus
 VESA Local Bus (VLB)
 PCI
 AGP
(i) Industry Standard Architecture (ISA) Bus: The original 8-bit ISA bus ran at 4.77MHz
- the same speed as the processor. It was improved over the years, and with the advent of
the IBM PC/AT using the Intel 80286 processor and 16-bit data bus it become the Industry
Standard Architecture bus in 1982. At this stage its speed increased to 6MHz and later to
8MHz.
The ISA bus specifies a 16-bit connection driven by an 8MHz clock. It has a theoretical
data transfer rate of up to 16 MBps. Functionally, this rate would reduce by a half to 8
MBps since one bus cycle is required for addressing and another bus cycle for the 16-bits
of data. In the real world it is capable of 5 MBps. ISA slots were mostly used for the
common 16 bit SoundBlaster compatible sound cards.

The ISA bus has two “faces” in the modern PC:
NOTES
 The internal ISA bus, which is used on the simple ports, like keyboard, diskette
drive, serial and parallel ports.
 And as external expansion bus, which can be connected with 16 bit ISA adapters.
Figure 5.1 shown how devised are connected using the ISA bus.
ISA bus
Controller
Internal External
units units
Diskette drive Adapter 1
Keyboard Adapter 2
COM 1 and 2 Adapter 3

LPT
Figure 5.1 Connecting devices using the ISA bus
With the improvements in the processor technology in terms of speed and wide data
paths, the ISA faced certain problems in coping up with these advancements. The ISA bus
could not transfer enough bits at a time. The bandwidth was very limited. As recently as the
late 1990s most ISA cards remained as 8-bit technology. IOs with 16-bit data paths such
as the hard disk controllers, graphics adapters and some network adapters - are constrained
by the low throughput levels of the ISA bus.
Further, the ISA bus lacks intelligence. This means that the CPU has to control the
data transfer across the bus. The CPU cannot start a new assignment, until the transfer is
completed. A typical example for this is, when the PC communicates with the floppy drive,
while the rest of the PC is waiting. Quite often the whole PC seems to be sleeping. That is
the result of a slow and unintelligent ISA bus.
(ii) Micro Channel Architecture (MCA) Bus: The MCA bus was IBM’s attempt to
replace the ISA bus, when the 80386DX was introduced in the mid-80s. The 80386DX
has 32-bit data bus and so the MCA is 32 bits wide, and offers several significant
improvements over ISA. (One of MCA’s disadvantages was rather poor DMA controller
circuitry.)
Features of the MCA bus:
* 32 Bit Bus Width: The MCA bus features a full 32 bit bus width, the same width as
the VESA and PCI local buses. It had far superior throughput to the ISA bus.

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* Bus Mastering: The MCA bus supported bus mastering adapters for greater
NOTES efficiency, including proper bus arbitration.
* Plug and Play: MCA automatically configured adapter cards, so there was no
need to fiddle with jumpers. This was eight years before Windows 95 brought PnP
into the mainstream!
Disadvantages: Although MCA had advanced features, it was not successful because
of two major reasons - (i) MCA was incompatible with ISA: this means ISA cards will not
work at all in an MCA system and the PC market is very sensitive to backwards-
compatibility issues and (ii) IBM made the MCA bus proprietary. These two factors,
combined with the increased cost of MCA systems, led to the demise of the MCA bus.
(iii) Extended Industry Standard Architecture (EISA) Bus: Unlike ISA, the EISA
bus never became an industry standard. EISA was developed by Compaq soon after the
IBM introduced the MCA bus.
Compaq avoided the two key mistakes that IBM made when they developed EISA.
First, they made it compatible with the ISA bus. Second, they opened the design to all
manufacturers instead of keeping it proprietary, by forming the non-profit EISA committee
to manage the design of the standard. EISA was similar to MCA both in terms of technology
and market acceptance: it had significant technical advantages over ISA, and it never
caught on with the PC-buying public.
Some of the key features of the EISA bus:
 ISA Compatibility: ISA cards will work in EISA slots.

 32 Bit Bus Width: Like MCA, the bus was expanded to 32 bits.
 Bus Mastering: The EISA bus supports bus mastering adapters for greater efficiency,
including proper bus arbitration.
 Plug and Play: EISA automatically configures adapter cards, similar to the Plug
and Play standards of modern systems.
EISA-based systems have today been mostly relegated to a specialty role; they are
sometimes found in network fileservers. The EISA bus is virtually non-existent on desktop
systems for several reasons. First, EISA-based systems tend to be much more expensive
than other types of systems. Second, there are few EISA-based cards available. Finally,
the performance of this bus is quite low compared to the popular local buses like the
VESA Local Bus and PCI.
(iv) VESA Local Bus (VLB): The VESA local bus was the first local bus to gain popularity
and was introduced in 1992. VESA stands for the Video Electronics Standards Association,
a standards group that was formed in the late eighties to address video-related issues in

personal computers. Indeed, the major reason for the development of VLB was to improve
video performance in PCs. NOTES
The VLB is a 32-bit bus - a direct extension of the 486 processor/memory bus. A
VLB slot is a 16-bit ISA slot with third and fourth slot connectors added on the end. The
VLB normally runs at 33 MHz, although higher speeds are possible on some systems.
Since it is an extension of the ISA bus, an ISA card can be used in a VLB slot, although it
makes sense to use the regular ISA slots first and leave the (small number of) VLB slots
open for VLB cards, which won’t work in an ISA slot of course. Use of a VLB video card
and I/O controller greatly increases system performance over an ISA-only system.
VLB was extremely popular with the use of the 486, but it died down with the
introduction of the Pentium along with the PCI local bus in 1994. Other reasons for the
unpopularity of the VLB are – (i) its design was strongly based on the 486 processor, and
adapting it to the Pentium caused a host of compatibility and other problems, (ii) the number
of cards that could be used on the bus was low (often only two or even one), and occasionally
there could be timing problems on the bus when more than one card was used, (iii) VLB
did not support bus mastering properly since there was no good arbitration scheme, and
(iv) VLB did not support Plug and Play.
Q5.4a What is the expansion of (i) ISA, (ii) MCA, (iii) EISA, (iv) PCI, (v) VESA?
Q5.4b What is the operating speed of (i) ISA (ii) MCA, (iii) EISA, (iv) PCI, (v) VESA?
Q5.4c What is meant by plug-and-play? Which of these buses support this feature – ISA,
EISA, MCA?
Q5.4d What are the disadvantages of the MCA that caused its unpopularity?
Q5.4e What are the reasons for the unpopularity of the VESA bus?
Q5.4f Is the ISA bus often used for memory expansion?
5.5 PERIPHERAL COMPONENT INTERCONNECT (PCI) LOCAL BUS
Currently the most popular local I/O bus is the Peripheral Component Interconnect
(PCI) bus. It was developed by Intel and introduced in 1993. It is geared specifically to
fifth and sixth generation systems.
PCI is a 32-bit bus that normally runs at a maximum of 33 MHz, just like it predecessor,
the VESA bus. The key to PCI’s advantages over its predecessor lies in the chipset that
controls it. The PCI bus is controlled by special circuitry in the chipset that is designed to
handle it, where the VLB was just an extension of the 486 processor bus. PCI is not tied
up to the 486 in this manner, and its chipset provides proper bus arbitration and control

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facilities, to enable PCI to do much more than VLB ever could. PCI is also used outside
NOTES the PC platform, providing a degree of universality and allowing manufacturers to save on
design costs.
The following sections provide more details on the functioning of the PCI bus in
various areas specifically,
 PCI Bus performance

 PCI bus speed setup
 PCI Expansion slots
 PCI bridge
 PCI internal interrupts
 PCI bus mastering
 PCI-IDE bus mastering
 PCI plug-n-play
5.5.1 Pci Bus Performance
The PCI bus provides superior performance to the VESA local bus. In fact, PCI is
the highest performance general I/O bus currently used on PCs, mainly the due to the
following factors:
 Burst Mode: The PCI bus can transfer information in a burst mode, where in
after an initial address is provided multiple sets of data can be transmitted in a row.
 Bus Mastering: PCI supports full bus mastering, which leads to improved
performance.
 High Bandwidth Options: The PCI bus specification version 2.1 calls for
expandability to 64 bits and 66 MHz speed; if implemented this would quadruple
bandwidth over the current design.
5.5.2 Pci Bus Speed Setup
The speed of the PCI bus can be set synchronously or asynchronously, depending
on the chipset and motherboard. In a synchronized setup (used by most PCs), the PCI bus
runs at half the memory bus speed; since the memory bus is usually 50, 60 or 66 MHz, the
PCI bus would run at 25, 30 or 33 MHz respectively. In an asynchronous setup the speed
of the PCI bus can be set independently of the memory bus speed. This is normally controlled
through jumpers on the motherboard, or BIOS settings.

5.5.3 Pci Expansion Slots
NOTES
The PCI bus offers more expansion slots than most VLB implementations. Most
PCI systems support 3 or 4 PCI slots. The PCI bus offers a great variety of expansion
cards compared to VLB. The most commonly found cards are video cards, SCSI host
adapters, and high-speed networking cards. Hard disk drives are also on the PCI bus but
are normally connected directly to the motherboard on a PCI system. However, it should
be noted that certain functions cannot be provided on the PCI bus. For example, serial
and parallel ports must remain on the ISA bus.
5.5.4 Pci Bridge
In a personal computer system, the microprocessor bus is separate and independent

of the PCI bus. The microprocessor connects to the PCI bus through the PCI bridge
which is an integrated circuit. This means that virtually any microprocessor can be interfaced
to the PCI bus as long as a PCI controller of bridge is designed for the system.
5.5.5 Pci Internal Interrupts
The PCI bus uses its own internal interrupt system for dealing with requests from the
cards on the bus. These interrupts, if needed by cards in the slots, are mapped to regular
interrupts, normally IRQ9 through IRQ12.
5.5.6 Pci Bus Mastering
The PCI bus is the first bus to popularize bus mastering. PCI supports full device
bus mastering, and provides bus arbitration facilities through the system chipset. PCI’s
design allows bus mastering of multiple devices on the bus simultaneously, with the arbitration
circuitry working to ensure that no device on the bus locks out any other device. At the
same time though, it allows any given device to use the full bus throughput if no other
device needs to transfer anything. In a way, the PCI bus acts like a tiny local area network
within the computer, in which multiple devices can each talk to each other, sharing a
communication channel that is managed by the chipset.
5.5.7 Pci Ide Bus Mastering
The PCI bus also allows to set up compatible IDE/ATA hard disk drives to be bus
masters. Under the correct conditions this can increase performance over the use of PIO
modes. When PCI bus mastering is used, IDE/ATA devices use DMA modes to transfer
data instead of PIO.
5.5.8 Pci Plug And Play
A PCI interface contains a series of registers located in a small memory device on

the PCI interface, that contains information about the board. The information in these
registers allows the computer to automatically configure the PCI card. This plug-and-play
feature has made the PCI bus, a very popular one.

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The PCI bus is part of the Plug and Play standard developed by Intel, with cooperation
NOTES from Microsoft and many other companies. PCI systems were the first to popularize the
use of Plug and Play. The PCI chipset circuitry handles the identification of cards and
works with the operating system and BIOS to automatically set resource allocations for
compatible peripheral cards.
5.5.9 Memory Interfacing Using Pci
PCI bus is most often used for interfacing IO components to the microprocessor.
Memory could be interfaced but it would only operate at a 33MHz rate with the Pentium,
which is half of the speed of the 66MHz resident local bus of the Pentium or Pentium Pro
system.
Q5.5.a What are the features of the PCI bus?
Q5.5.b What features of the ISA contribute to its performance?
Q5.5c What is the role of the PCI bridge?
Q5.5d How is a microprocessor interfaced to a PCI bus?
Q5.5.e Can memory be interfaced using the PCI bus?
5.6 UNIVERSAL SERIAL BUS (USB)
The USB interface or universal serial bus is one of the most used interfaces at this
moment to connect peripheral equipment to computers. The USB interface was developed
for connecting peripherals like printers and scanners to computers. Since the USB 2.0
release higher speed devices like external hard disks and even mobile phones, are equipped
with an USB interface. The USB interface itself is a standard, and any device can be
connected to a USB enabled computer that has the necessary driver and connector. The
USB has replaced the RS232 and parallel communications in a lot of situations.
5.6.1 Usb Versions
Version 0.7 of the USB interface definition was released in November 1994 and the
first actual definition of USB, USB 1.0 came out in January 1996. It was a combined
effort of some large players on the market such as Compaq, Intel, Microsoft and NEC,
to define a new general device interface for computers.
(i) USB 1.1: The original USB standard provides a fast Master/Slave interface using a
tiered star topology supporting up to 127 devices with up to 6 tiers (hubs). A PC
is normally the master or Host and each of the peripherals linked to it act as slaves
or Devices. One of the aims of the design was to minimise the complexity of the
Devices by doing as much operations in the Host as possible. Data transfer rates

are defined in the specification as –(i) Low Speed 1.5 Mbits/sec and (ii) Full
Speed 12 Mbits/sec and the maximum length of each cable section is 5 metres. NOTES
The USB specification allows each device to take up to 500mA of power (limited
to 100mA during startup).
(ii) USB 2.0: There are some minor variations from USB 1.1 within the USB 2.0
specification and since USB 2.0s inception most interfaces have been designed to
conform to the USB 2.0 standard. The 2.0 specification is a superset of 1.1 and
the major functional difference which is the addition of a High Speed 480 Mbits/
sec data transfer mode. Be warned, however, that the Spec does allow a product
(eg an interface chip) to say that it is “USB 2.0 compatible” without necessarily
implying that it implements the High Speed mode.
(iii) USB 3.0: Still at the design stage the 3.0 specification is due out in mid 2008 with
products hitting the shops in 2009. It is being designed to be backward compatible
with 2.0 and to add a Super Speed >4.8 Gbits/sec data transfer mode.
5.6.2 Usb Connectors
Although the USB interface itself is standard, and any device can be connected to a
USB enabled computer if the appropriate driver exists, problems may arise in finding the
right cable. This is because especially for smaller equipment like cameras different models
of USB connectors have been defined.
(i) USB A and B Connectors: Two USB connectors have been defined for basic use,
the USB A connector is to be used on devices which provide power (mostly computers),
and the USB B connector is to be used on devices which receive power like most peripheral
devices.
USB A connector USB B connector
For the USB A and B connectors specified in the USB 1.1 and USB 2.0 specification,
four pins are defined. Two pins are used for power and two pins are used for differential
data transmission. The pins for the power connection (pin 1 and 4) are slightly longer. This
is done on purpose in order to first connect the power supply when connecting a USB
device, and only afterwards establish the data connection. With this sequence the chance
that the driver or receiver ports of the data connection receive awkward and possible
dangerous voltages is lowered substantially. Table 5.1 gives the details of USB A and B
connectors.

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Table 5.1 Standard USB A and B connector pin names

NOTES
Pin Name Color Function
1 Vcc Red +5V supply voltage
2 D- White Data- signal line
3 D+ Green Data+ signal line
4 GND Black Supply ground
(ii) Mini USB A and B connectors: The USB A and B connectors were used with
devices like printers, modems and scanners. With the introduction of the faster
USB 2.0 faster and smaller devices like photo camera’s and mobile telephones,
could make use of USB. This required smaller connectors, namely the mini-
connectors – mini USB A and mini USB B. However, in practice the mini USB A
connector is not in use.
Mini USB A connector Mini USB B connector
Besides the size, the main difference between the standard USB A and B connectors
and the mini USB A and B versions is the extra pin which is called ID. In the mini connector
series this pin is normally not connected. It has been added for future enhancements of the
USB standard. Table 5.2 gives the details of mini USB A and B connectors.
Table 5.2 Mini USB A and B connector pin names

4 ID – not connected
(iii) Micro USB AB and B connectors: For smaller equipments like the cell phones,
smaller connectors, namely the micro USB connectors, very introduced in January 2007.
Although the micro USB connector is much thinner than its mini USB brother, it has been
especially designed for rough use and the connector is specified for at least 10000 connect/
disconnect cycles. One of the reasons is that with mobile devices like cell phones, PDA’s
and smartphones the number of mate cycles will be significantly higher than with static

equipment like printers and mice. Furthermore the micro USB connector is becoming the
de facto standard to charge mobile devices and its use will therefore be even more NOTES
widespread than of its mini USB counterpart.
The ability of a device to switch between the master and slave role is supported in the
USB 2.0 specification and is called USB On-The-Go or more often USB OTG. The
connectors used for this purpose are the mini USB AB and the micro USB AB. The mini
USB AB connector is now officially deprecated, but the micro USB AB connector is
replacing its place rapidly. In this micro USB AB connector the ID pin is used to signal the
master of slave function.
Micro USB AB connector Micro USB B connector
The pin numbering for the micro USB connectors is the same as for the mini USB
connectors. The only difference is that for the micro USB AB connector the ID pin now
has a function assigned to it. Table 5.3 gives the details of Micro USB AB and B connectors.
Table 5.3 Micro USB AB and B connector pin names

4 ID – not connected: works as B connector
connected to GND: works as A connector
5.6.3 Usb System Architecture
The USB System Architecture consists of the following main components:
 USB Host Computer

 One or more USB Devices
 A physical bus represented by the USB Cable that links the devices with the host
computer

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(i) USB Host: The main responsibility of the host computer is to control the communications
NOTES between the host system and USB devices. A typical host is shown in Figure 5.2.
Figure 5.2: USB Host Computer
The host computer contains two layers: a USB host controller hardware layer, and a
software layer, which includes USB device drivers for a wide range of USB devices such
as keyboards, mice, digital still cameras, scanners, mass storage devices etc. The drivers
convert data between the format that is used by the host computer and the format used by
the USB devices.
USB hardware layer is responsible for:
 Detecting the attachment and removal of USB devices

 Monitoring device status and collecting activity statistics
 Providing power to attached USB devices
 Managing control and data flow between the USB host and USB devices
 Checking the basic validity of bus transactions
 USB software layer is responsible for:
 Handling USB devices and their connectivity
 USB devices enumeration and configuration
 Loading appropriate device drivers
 Managing the power on the bus and bus bandwidth
 Managing the data transfer between the software and hardware
(ii) USB Devices: The USB Devices are peripherals that use the USB protocol for two
way communication with the host computer.
USB Flash Drive USB MP3 Player USB Image Still Camera USB Video Camera

The main responsibility of the USB Device is to provide the end user with various
specific functions, such as a keyboard, a data/fax modem device, a digital microphone, or NOTES
a video camera. For this reason the official USB Specification uses the term “function” to
refer to USB peripheral devices. To provide the user with additional attachment points to
connect more peripherals there is a special type of USB device called USB Hub.
7-port USB Hub
USB Hub is just a device with multiple USB ports for plugging in the USB devices
and other hubs. Internal root hub on the host controller and the external hubs are functionally
the same.
(iii) USB Cable: USB Cable is a cable to connect between host computer and USB
device.
USB cable: USB A - USB mini
The USB specification limits the maximum length of a standard USB cable between
full- and high-speed devices to 5 meters. For a low-speed device the limit is 3 meters. The
primary reason for USB cable’s length limit is the maximum allowed delay of a signal. In
practice, some USB devices may work with longer than specified cable. However, using a
longer cable lowers the signal quality provided by the USB bus below the specification
tolerance limit. This may prevent USB devices from working properly or even from working
at all. Using USB devices over a greater length require one or several USB hubs or USB
Active Extension Cable (USB Repeater Cable) that contains active electronics which
regenerate the USB signal for maximum reliability and performance over extended distances.
With powered USB hubs or USB active extension cables USB connections can be extended
to maximum theoretical distance of about 30 meters.
(iv) USB Host Controller: A USB Host Controller is the hardware either on the computer
motherboard or PCI card. It provides an interface for transferring streams of data between
the host computer and the USB devices. The host computer may have one or multiple
USB host controllers with different types of interface.
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(v) USB Host Controller Interface: A Host Controller Interface (HCI) is a register
NOTES level interface which allows host controller hardware to communicate with the operating
system of a host computer. There are three types of USB host controller interface:
 Open Host Controller Interface (OHCI)

 Universal Host Controller Interface (UHCI)
 Enhanced Host Controller Interface (EHCI)
Host controller interface standards are not defined in the USB specification itself.
5.6.4 Usb Protocol Basics
The USB protocol set up involves the host controller and the config flags.
(i) The host controller: This is the “master” of a series of devices and it controls all of
the devices below it according to one of the two USB topologies. In each topology,
the host controller will be the point on the USB network with no incoming wires.
(ii) The config flags: There are six of them: port, configuration, interface, vendor,
product, and release. Of these, the first one and the last three are the most important.
The port flag is a unique integer value which corresponds to the port number nearest
to the device. The uniqueness is guaranteed by the computer’s manufacturer, who
should ensure that no two devices share the same port as the one nearest to the
device. This is easy to accomplish, because each computer has a very large number
of ports. The last three flags are 16-bit values set by the manufacturer that can be
used by the host controller to nail down a specific device when the bus is searching
for drivers to mount; these numbers should also be unique as a set (i.e. no two
distinct products should ever have the exact same three numbers, though they may
share one or two.) As of yet, no plan exists for when the protocol runs out of
numbers, because no single manufacturer has come close to making 4.3 billion
distinct USB devices.
(iii) USB Topologies: Topology is the word used by the USB standard to refer to a
network setup. There are two basic topologies: the simpler star topology and the
more complex tier topology. Each of these has a host controller, as mentioned
above.
The simpler star topology is quite similar to a standard hub or a token-ring network;
the host controller is directly connected to all surrounding devices, with no wires running
back into the controller. In this structure, the host controller asks each device in turn for its
message. If the device has something to say, it says it, otherwise it gets passed by and must
wait until the host controller returns to ask it again. This setup is more useful in a situation
in which devices are of equal priority, because they all get equal time.

The more complex of the protocols is the tier topology, an illustration of which is
shown below. NOTES
Key: Hub
Device Root Tier
Tier 1
Tier 2
Tier 3
Tier 4
In such a setup, the host controller is the sole entity inhabiting the root tier. All other
devices chain from the root controller in a tree. When messages are sent, each tier has a
higher priority than the tier below it on sending something back to the host controller. Thus,
tier II may only send a message if no device in tier I has anything to say. Such a setup
would be more useful when some devices are more important than others; for example, a
keyboard would be in a relatively low tier because it cannot always be in use. A sample tier
topology is shown in Figure 5.3.
Tier 1
Tier 2
Tier 3
Tier 4
Tier 5
Tier 6
Tier 7
Figure 5.3: Example of the USB topology from the user’s point of view

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Figure Legend
NOTES
1. USB host with host controller
2. 2-port root hub integrated into the host controller
3. 4-port hub integrated into the keyboard (part of the compound device)
4. USB keyboard (part of the compound device)
5. USB keypad (part of the compound device)
6. 4-port hub (part of the 7-port hub)
7. 4-port hub (part of the 7-port hub)
8. USB mouse
9. USB flash drive
10. 4-port hub
11. 4-port hub
12. USB bluetooth adapter
(iv) Collision Detection in USB
In the case of either of the above setups, collisions are a non-issue. Due to what is
known as the “speak-when-spoken-to” protocol of USB, only one device may be sending
a message at any given time. Thus, in both the star topology and the tier topology, it is
impossible for multiple entities to be able to send messages that will conflict; regardless of
how much they might want to send a message at a given moment, each device must wait
for its turn.
The actual protocol controls collision detection by the use of interrupts.

5.6.5 The Usb Process
When the host powers up, it queries all of the devices connected to the bus and
assigns each one an address. This process is called enumeration — devices are also
enumerated when they connect to the bus. The host also finds out from each device what
type of data transfer it wishes to perform:
 Interrupt - A device like a mouse or a keyboard, which will be sending very little
data, would choose the interrupt mode.
 Bulk - A device like a printer, which receives data in one big packet, uses the
bulk transfer mode. A block of data is sent to the printer (in 64-byte chunks) and
verified to make sure it is correct.
 Isochronous - A streaming device (such as speakers) uses the isochronous mode.
Data streams between the device and the host in real-time, and there is no error
correction.
The host can also send commands or query parameters with control packets.
NOTES
As devices are enumerated, the host is keeping track of the total bandwidth that all of
the isochronous and interrupt devices are requesting. They can consume up to 90 percent
of the 480 Mbps of bandwidth that is available. After 90 percent is used up, the host
denies access to any other isochronous or interrupt devices. Control packets and packets
for bulk transfers use any bandwidth left over (at least 10 percent).
The Universal Serial Bus divides the available bandwidth into frames, and the host
controls the frames. Frames contain 1,500 bytes, and a new frame starts every millisecond.
During a frame, isochronous and interrupt devices get a slot so they are guaranteed the
bandwidth they need. Bulk and control transfers use whatever space is left. The technical
links at the end of the article contain lots of detail if you would like to learn more.
Q5.6.a What is meant by enumeration with respect to USB?
Q5.6.b Describe the USB’s star and tier topologies.
Q5.6.c Describe the config flags in USB.
Q5.6.d What are USB devices, give examples.
Q5.6.e What are the roles of the software and hardware layers in the USB host computer?
Q5.6.f Describe the different types of USB connectors.
Summary
 The unit discussed the concept of system buses

 The categories of buses were discussed
 Various bus characteristics were defined
 Popular system buses namely, ISA, MCA, EISA, VESA Local Bus, and AGP,
were discussed
 Details of PCI bus was described, including the Bus Performance, bus speed
setup, expansion Slots, PCI bridge, Internal Interrupts, Bus Mastering, Plug and
Play and Memory interfacing
 The architecture of the Universal Serial Bus (USB) was provided along with USB
versions, Connectors, Protocol Basics and The USB Process

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References
NOTES
1. System Buses: http://www.pcguide.com
2. Introduction to system buses: http://www.karbosguide.com/hardware/
module2c2.htm
3. USB: http://www.usb.org/home
4. USB Connectors: http://www.pctechguide.com/12Interfaces_USB.htm
5. USB Primer: http://ozark.hendrix.edu/~burch/cs/330/assn/assn5/Reed/
6. USB Architecture: http://www.usblyzer.com
7. USB architecture: Eli Journals at http://www.elementkjournals.com
Exercises
1. The system bus is made up of

(a) data bus (b) data bus and address bus
(c) data bus and control bus (d) data bus, control bus and address bus
2. Which of the following is NOT a bus standard ?
(a) EISA (b) VME (c) MCA (d) RS-232
3. Which of the following is not a USB connector type?
(a) AB (b) mini A (c) micro A (d) A
Short answers
1. Distinguish between memory and IO buses.

2. Distinguish between bus and port.
3. What is AGP - a bus or a port – discuss.
4. Describe the functions of data, address and control buses.
5. What is (i) bus interfacing (ii) bus mastering?
6. Describe the USB connectors that can be used with devices such as
a. Mobile phones
b. Digital cameras
c. Printers
7. What are the two bus topologies supported by the USB standard?
8. Is collision an issue with USB?

Long answers
NOTES
1. Describe the PC bus hierarchy.
2. Explain the characteristics of system buses.
3. List the features and explain the operations of the following buses
a. Industry Standard Architecture (ISA) Bus
b. Micro Channel Architecture (MCA) Bus
c. Extended Industry Standard Architecture (EISA) Bus
d. VESA Local Bus (VLB)
4. Describe the following bus standards in detail
a. Peripheral Component Interconnect (PCI)
b. Local Bus Universal Serial Bus (USB)
5. Describe the USB protocol operations.

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NOTES NOTES

NOTES NOTES

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NOTES NOTES

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MICROPROCESSORS AND ITS APPLICATIONS

THE 8086 PROCESSOR - SOFTWARE ASPECTS

Microprocessor is a multipurpose, programmable, clock-driven, register-base,

The microprocessors applications are classified primarily in two categories:

1 ANNA UNIVERSITY CHENNAI

1.2 LEARNING OBJECTIVES

1.3 EVOLUTION OF THE MICROPROCESSOR

2 ANNA UNIVERSITY CHENNAI

In 1977, Intel Corporation introduced an updated version of the 8080-the 8085.

3 ANNA UNIVERSITY CHENNAI

Applications began to demand faster microprocessor speeds, more memory, and

1.4 8086 ARCHITECTURE:

4 ANNA UNIVERSITY CHENNAI

Figure1.4.1 Architecture of 8086

Functions of the two blocks BIU and EU are:

 Both units operate asynchronously to give the 8086 an overlapping instruction

 BIU contains Instruction queue, Segment registers, Instruction pointer, Address

 EU contains Control circuitry, Instruction decoder, ALU, General data registers,

5 ANNA UNIVERSITY CHENNAI

Register Organization of 8086

6 ANNA UNIVERSITY CHENNAI

Instruction Pointer (IP) is a 16-bit register.

Flags is a 16-bit register containing 9 1-bit flags as shown in figure 1.4.2.

D-Flag T-Flag Z-Flag A-Flag P-Flag C-Flag

Direction Trap Zero Parity

Overflow Interrupt Sign Auxilliary Carry

Figure 1.4.2 Flags of 8086

7 ANNA UNIVERSITY CHENNAI

The advantages of using segment registers are that they:

8 ANNA UNIVERSITY CHENNAI

1.5 MACHINE LANGUAGE INSTRUCTIONS

1.5.1 Addressing Modes

9 ANNA UNIVERSITY CHENNAI

Register Indirect—The effective address of the datum is in the base register BX or an

Register Relative—The effective address is the sum of an 8- or 16-bit displacement

Relative Based Indexed—The effective address is the sum of an 8- or 16-bit

If (BX) = 0158 (DI) = 10A5 Displacement = 1B57 (DS) = 2100 and DS is

(i) Direct: EA = 1B57

10 ANNA UNIVERSITY CHENNAI

Instruction Register Memory

(d) Register indirect

(e) Register relative

(f) Based indexed

(g) Relative based indexed

Figure 1.5.1 Data Related addressing Mode

11 ANNA UNIVERSITY CHENNAI

Intrasegment Direct—The effective branch address is the sum of an 8- or 16-bit

+ EA = effective branch address

(a) Intrasegment direct

Effective branch address

(b) Intrasegment direct

(c) Intrasegment direct

(d) Intrasegment direct

Figure 1.5.2 Branch Related Addressing Mode

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(BX) = 1256 (SI) = 528F Displacement = 20A1

1.5.2 INSTRUCTION SET OF 8086/8088

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(viii)String Instructions These instructions involve various string manipulation

1.5.2.1 Data Copy / Transfer Instructions

However, in case of immediate addressing mode, a segment register cannot be a

Example Load DS with 5000H.

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