MP CBCS Notes

MICROPROCESSORS 15EC42
MODULE 1: 8086 PROCESSOR, INSTRUCTION SET OF 8086
Structure
1.0 Historical background

1.1 Objectives
1.2 8086 CPU Architecture
1.3 Addressing modes
1.4 Machine language instruction formats, Machine coding the program
1.5 Data transfer and arithmetic instructions
1.6 Control/Branch Instructions, Illustration with example programs
1.7 Outcomes
1.8 Questions/ answer
1.9 Further reading
1.0 HISTORICAL BACKGROUND:
The historical events leading to the development of microprocessors are outlined as follows:
The Mechanical age:
The computing system existed long before modern electrical and electronic devices were invented.
During 500 BC, the Babylonians invented the first mechanical calculator called Abacus. The abacus
which uses strings of beads to perform calculations was used by Babylonian priests to keep track of
their vast storehouses of grains. Abacus was in use until, Blaise Pascal, a mathematician, invented a
mechanical calculator constructed of gears and wheels during 1642. Each gear contained 10 teeth that,
when moved one complete resolution, advanced a second gear one place.
This is the same principle employed in a car‟s odometer mechanism and is the basis for all mechanical
calculators. The arrival of the first, practical geared, mechanical machines used to compute
information automatically dates to early 1800‟s, which is much earlier to the invention of electricity.
Only early pioneer of mechanical computing machinery was Charles Babbage. Babbage was
commissioned in 1823 by the astronomical society of Britain to produce a programmable computing
DEPT of ECE, ATMECE, MYSURU Page 1

machine. This machine was to generate navigational tables for the royal navy. He accepted the
challenge and began to create what he called as Analytical Engine. Analytical Engine was a
mechanical computer that could store 1000 20-digit decimal numbers and a variable program that
could modify the function of machine so it could perform various calculating tasks. Input to the
analytical engine was punched cards, which is an idea developed by Joseph Jaquard.
The development of analytical engine stopped because the machinists at that time were unable to
create around 50, 000 mechanical parts with enough precision.
The Electrical age:
The invention of electric motor by Michael Faraday during 1800‟s lead the way to the development of
motor-driven adding machines all based on the mechanical calculator developed by Blaise Pascal.
These electrically driven mechanical calculators were in use until the small hand-held electronic
calculator developed by Bomar was introduced in 1970‟s. Monroe is another person who introduced
electronic calculators, whose four-function models the size of cash register. In 1889, Herman Hollerith
developed the punched card for storing data, basically the idea was of Jaquard. He also developed a
mechanical machine, driven by one of the new electric motors that counted, sorted and collated
information stored on punched cards. The punched cards used in computer systems are often called
Hollerith cards, In honor of Herman Hollerith. The 12-bit code used on a punched card is called the
Hollerith code.
Electric motor driven mechanical machines dominated the computing world until the German inventor
konrad Zuse constructed the first electronic calculating machine, Z3 in the year 1941. Z3 was used in
aircraft and missile design during world war II for the German war effort.
In the year 1943, Allan Turing invented the first electronic computing system made of vacuum tubes,
which is called as Colossus. Colossus was not programmable; it was a fixed-program computer
system, called as special purpose computer.
The first general-purpose, programmable electronic computer system was developed in 1946 at the
University of Pennsylvania. This first modern computer was called the ENIAC (Electronics Numerical
Integrator And Calculator). The ENIAC was a huge machine, containing over 17,000 vacuum tubes
and over 500 miles of wires. This massive machine weighted over 30 tons, yet performed only about
100,000 operations per second. The ENIAC thrust the world into the age of electronic computers. The
ENIAC was programmed by rewriting its circuits – a process that took many workers several days to
accomplish. The workers changed the electrical connections on plug boards that looked like early

telephone switch boards. Another problem with the ENIAC was the life of the vacuum tube
components, which required frequent maintenance.
More advancement followed in the computer world with the development of the transistor in 1948 at
Bell labs followed by the invention of integrated circuit in 1958 by jack Kilby of Texas instruments.
The Microprocessor age:
With the invention of integrated circuit technology, Intel introduced the world‟s first microprocessor, a
4-bit Intel 4004 microprocessor. It addresses a mere 4096 4-bit wide memory locations. The 4004
instructions set contained only 45 instructions. It was fabricated with the P-channel MOSFET
technology that only allowed it to execute instructions at the slow rate of 50 KIPS. At first, the
applications abounded for this device, like video game systems and small microprocessor based
control systems. The main problem with this early microprocessors were its speed, word width and
memory size.
Later Intel introduced 4040, an updated version of 4004, which operated at higher speed, although it
lacked improvements in word width and memory size.
Intel Corporation released the 8008 an extended 8-bit version of 4004. The 8008 addressed an
expanded memory size (16 Kbytes) and contained additional instruction, totally 48 instructions, that
provided an opportunity for its application in more advanced systems.
Microprocessors were then used very extensively for many application developments. Many
companies like Intel, Motorola, Zilog and many more recognized the demanding requirement of
powerful microprocessors to the design world. In fulfilling this requirement many powerful
microprocessors were arrived to the market of which we study the Intel‟s contribution.
The Intel 8080 & 8085:
• 8080 address more memory and execute additional instructions, but it executed them 10 times
faster than 8008.
• The 8080 was compatible with TTL, whereas the 8008 was not directly compatible.
• The 8080 also addressed four times more memory (64 Kbytes) than the 8008 (16 Kbytes). Intel
corporation introduced 8085, an updated version of 8080. Although only slightly more advanced than
an 8080 microprocessor, the 8085 executed software at an higher speed. The main

advantages of the 8085 were its internal clock generator, internal system controller, and higher clock
frequency. This higher level of component integration reduced the 8085‟s cost and increased its
usefulness.
The 16-bit Microprocessor:
The Intel released 16-bit microprocessors 8086 & 8088, which executed instructions in as little as
400ns (2.5 MIPS). The 8086 & 8088 addressed 1 Mbytes of memory, which was 16 timers more
memory than the 8085. 8086/8088 have a small 6-byte instruction cache or queue that pre-fetched a
few instructions before they were executed, which leads to the faster processing. 8086/8088 has
multiply and divide instructions which were missing in 8085. These microprocessors are called as
CISC (Complex Instruction Set Computers) because of the number and complexity of the instructions.
The 16-bit microprocessor also provided more internal register storage space that the 8-bit
microprocessor. Applications such as spread sheets, word processors, spelling checkers, and computer-
based thesauruses on personal computers are few developed using 8086/8088 microprocessors.
The 80286 microprocessor:
Even the 1 Mbyte memory on 8086/8088 found limited for the advanced applications. This led
Intel to introduce the 80286 microprocessor. 80286 follow 8086‟s 16-bit architecture, except it can
address 16 Mbyte memory system. The instruction set was similar to 8086 except few instructions for
managing extra 15 Mbytes of memory. The clock speed of 80286 was increased, so it executed some
instructions in as little as 250 ns (4 MIPS).
The 32-bit Microprocessors:
The 80386 Microprocessor:
The 80386 is the Intel‟s first 32-bit microprocessor. The 80386 has 32-bit data bus and a 32-bit
memory addresses. The 80386 was available in a few modified versions such as 80386SX, 80386SL &
80386SLC, which vary in the amount of memory they address. Applications that require Graphical
User Interface (GUI) were using the 80386 microprocessors. Even applications which involve
floating-point numbers were using the 80386 microprocessors.
The 80386 included a memory management unit that allowed memory resources to be allocated and
managed by the operating system.

The 80486 Microprocessor:
The 80486 has 80386 like microprocessor, an 80387 like numeric co-processor, and an 8 Kbyte cache
memory integrated in it. Most of the instructions in 80486 can be executed in a single clock instead of
two clocks compared to 80386. the average speed improvement of instructions was about 50% over
the 80386 that operated at the same clock speed.
The Pentium Microprocessor:
The Pentium microprocessor was introduced late in 1993 with higher speeds compared to 80486. in
Pentium cache size was increased to 16 Kbytes from the 8K cache found in the basic version of 80486.
After Pentium, many versions were introduced, like Pentium Pro, Pentium II, Pentium III and Pentium
IV with higher capacities.
1.1 Objectives:
1. To learn basics of microprocessor and in detail about 8086

2. The course will provide knowledge about different set of instructions to build and program
microprocessor-based systems.
1.2 8086 CPU ARCHITECTURE
Register Organization of 8086
All the registers of 8086 are 16-bit registers. The general purpose registers can be used as either 8-
bit registers or 16-bit registers.
The register set of 8086 can be categorized into 4 different groups. The register organization of
8086 is shown in the figure.
AX AH AL SP
CS BP
BX BH BL
SS FLAGS/ SI
PSW
CX CH CL DS DI
DX ES IP
DH DL
General data registers Segment Pointers and index

Registers registers
Register organization of 8086

General Data Registers:
The registers AX, BX,CX and DX are the general purpose 16-bit registers.
AX is used as 16-bit accumulator. The lower 8-bit is designated as AL and higher 8-bit is designated
as AH. AL can be used as an 8-bit accumulator for 8-bit operation.
All data register can be used as either 16 bit or 8 bit. BX is a 16 bit register, but BL indicates the
lower 8-bit of BX and BH indicates the higher 8-bit of BX.
The register CX is used default counter in case of string and loop instructions.
The register BX is used as offset storage for forming physical address in case of certain addressing
modes.
DX register is a general purpose register which may be used as an implicit operand or destination in
case of a few instructions.
Segment Registers:
The 8086 architecture uses the concept of segmented memory. 8086 able to address to address a
memory capacity of 1 megabyte and it is byte organized. This 1 megabyte memory is divided into
16 logical segments. Each segment contains 64 kbytes of memory.
There are four segment register in 8086

 Code segment register (CS)
 Data segment register (DS)
 Extra segment register (ES)
 Stack segment register (SS)
Code segment register (CS): is used fro addressing memory location in the code segment of the
memory, where the executable program is stored.
Data segment register (DS): points to the data segment of the memory where the data is stored.
Extra Segment Register (ES) : also refers to a segment in the memory which is another data segment
in the memory.
Stack Segment Register (SS): is used fro addressing stack segment of the memory. The stack
segment is that segment of memory which is used to store stack data.
While addressing any location in the memory bank, the physical address is calculated from two
parts:
- The first is segment address, the segment registers contain 16-bit segment base addresses,
related to different segment.
- The second part is the offset value in that segment.
The advantage of this scheme is that in place of maintaining a 20-bit register for a physical address,
the processor just maintains two 16-bit registers which is within the memory capacity of the
machine.
Pointers and Index Registers.
The pointers contain offset within the particular segments.

- The pointer register IP contains offset within the code segment.

- The pointer register BP contains offset within the data segment.

- He pointer register SP contains offset within the stack segment.
The index registers are used as general purpose registers as well as for offset storage in case of
indexed, base indexed and relative base indexed addressing modes.
The register SI is used to store the offset of source data in data segment.
The register DI is used to store the offset of destination in data or extra segment.
The index registers are particularly useful for string manipulation.
Flag Register
The 8086 flag register contents indicate the results of computation in the ALU. It also contains some
flag bits to control the CPU operations.
8086 Architecture:
The 8086 architecture supports

- a 16-bit ALU.
- a set of 16 bit registers
- provides segmented memory addressing scheme
- a rich instruction set.
- Powerful interrupt structure
- Fetched instruction queue for overlapped fetching and execution step.
The internal block diagram units inside the 8086 microprocessor is shown in the figure.
FIG
The architecture of 8086 can be divided into two parts
(a) Bus Interface unit (BIU)

(b) Execution unit (EU)
The bus interface unit is responsible for physical address calculations and a predecoding instruction
byte queue ( 6 bytes long).
The bus interface unit makes the system bus signal available for external devices.
The 8086 addresses a segmented memory. The complete physical address which is 20-bits long is
generated using segment and offset registers, each 16-bits long.
Generating a physical address:
- The content of segment register (segment address) is shifted left bit-wise four times.
- The content of an offset register (offset address) is added to the result of the previous shift
operation.
These two operations together produce a 20-bit physical address.
For example, consider the segment address is 2010H and the offset address is 3535H.
The physical address is calculated as:

Segment Address 2010H 0010 0000 0001 0000
Shifted left by

4 bit positions 0010 0000 0001 0000 0000

+
offset address 0011 0101 0011 0101
---------------------------------------------------------------
physical address 0010 0011 0110 0011 0101
2 3 6 3 5
The segment address by the segment value 2010H can have offset value from 0000H to FFFFH
within it, ie. Maximum 64K locations may be accommodated in the segment.
The physical address range for this segment is from 20100H to 300FFH.
The segment register indicates the base address of a particular segment and CS, DS, SS and ES are
used to keep the segment address.
The offset indicates the distance of the required memory location in the segment from the base
address, and the offset may be the content of register IP, BP, SI, DI and SP.
Once the opcode is fetched and decoded, the external bus becomes free while the Execution Unit is
executing the instruction.
While the fetched instruction is executed internally, the external bus is used to fetch the machine
code of the next instruction and arrange it in a queue called as predecoded instruction byte queue.
This is a 6 byte long queue, works in first-in first-out policy.
While the opcode is fetched by the bus interface unit (BIU), the execution unit (EU) executes the
previously decoded instruction concurrently.
The execution unit contains.

- the register set of 8086 except segment registers and IF.
- a 16-bit ALU to perform arithmetic & logic operation
- 16-bit flag register reflects the results of execution by the ALU.
- the decoding units decodes the op-code bytes issued from the instruction byte queue.
- the timing and control unit generates the necessary control signals to execute the instruction
op-code received from the queue.
The execution unit may pass the results to the bus interface unit for storing them in memory.
Memory Segmentation:
The size of address bus of 8086 is 20 and is able to address 1 Mbytes ( 220 ) of physical memory.
The compete 1 Mbytes memory can be divided into 16 segments, each of 16 Kbytes size.
The addresses of the segment may be assigned as 0000H to F000H respectively.
The offset values are from 0000H to FFFFFH.
If the segmentation is done as per above mentioned way, the segments are called non-overlapping
segments.
In some cases segment may overlap also. Suppose a segment starts at a particular address and its
maximum size can go up to 64 Kbytes. But if another segment starts before this 64 Kbytes location
of the first segment, the two segments are said to be overlapping segment.

The area of memory from the start of the second segment to the possible end of the first segment is
called as overlapped segment.
Non-overlapping segments and overlapping segments are shown in the figure.

Fig
Non-Overlapping Segments
The main advantages of the segmented memory scheme are as follows:

a) Allows the memory capacity to be 1 Mbyte although the actual addresses to be handled are
of 16-bit size
b) Allows the placing of code data and stack portions of the same program in different parts
(segments) of memory, for data and code protection.
c) Permits a program and/ or its data to be put into different areas of memory each time
program is executed, ie, provision for relocation may be done.
Flag Register
A 16 flag register is used in 8086. It is divided into two parts .

(a) Condition code or status flags
(b) Machine control flags
The condition code flag register is the lower byte of the 16-bit flag register. The condition code flag
register is identical to 8085 flag register, with an additional overflow flag.
The control flag register is the higher byte of the flag register. It contains three flags namely
direction flag(D), interrupt flag (I) and trap flag (T).
The complete bit configuration of 8086 is shown in the figure.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X X X X 0 D I T S Z X AC X P X CY
S- Sign Flag : This flag is set, when the result of any computation is negative.
Z- Zero Flag: This flag is set, if the result of the computation or comparison performed by the
previous instruction is zero.
P- Parity Flag: This flag is set to 1, if the lower byte of the result contains even number of 1‟s.
C- Carry Flag: This flag is set, when there is a carry out of MSB in case of addition or a borrow in
case of subtraction.
T- Tarp Flag: If this flag is set, the processor enters the single step execution mode.
I- Interrupt Flag: If this flag is set, the maskable interrupt are recognized by the CPU, otherwise
they are ignored.
D- Direction Flag: This is used by string manipulation instructions. If this flag bit is „0‟, the string is
processed beginning from the lowest address to the highest address, i.e., auto incrementing
mode. Otherwise, the string is processed from the highest address towards the lowest address,
i.e., auto incrementing mode.

AC-Auxilary Carry Flag: This is set, if there is a carry from the lowest nibble, i.e, bit three during
addition, or borrow for the lowest nibble, i.e, bit three, during subtraction.
O- Over flow Flag: This flag is set, if an overflow occurs, i.e, if the result of a signed operation is
large enough to accommodate in a destination register. The result is of more than 7-bits in size
in case of 8-bit signed operation and more than 15-bits in size in case of 16-bit sign operations,
then the overflow will be set.
Signals of 8086
The 8086 is a 16-bit microprocessor. This microprocessor operate in single processor or

multiprocessor configurations to achieve high performance. The pin configuration of 8086 is shown
in the figure. Some of the pins serve a particular function in minimum mode (single processor
mode) and others function in maximum mode (multiprocessor mode).
FIG
Description of signals of 8086
AD7  AD0 The address/ data bus lines are the multiplexed address data bus and contain the
right most eight bit of memory address or data. The address and data bits are separated
by using ALE signal.
AD15  AD8 The address/data bus lines compose the upper multiplexed address/data bus. This lines
contain address bit A15  A8 or data bus D15  D8 . The address and data bits are
separated by using ALE signal.
A19 / S6  A18 / S3 The address/status bus bits are multiplexed to provide address signals A19  A16 and
also status bits S6  S3 . The address bits are separated from the status bits using
the ALE signals. The status bit S 6 is always a logic 0, bit S 5 indicates the
condition of the interrupt flag bit. The S 4 and S 3 combinedly indicate which
segment register is presently being used for memory access.
S4 S3 Funtion
0 0 Extra segment
0 1 Stack segment
1 0 Code or no segment
1 1 Data Segment
BHE / S7 The bus high enable (BHE) signal is used to indicate the transfer of data over the higher
order  D15  D8  data bus. It goes low for the data transfer over D15  D8 and is used to
derive chip select of odd address memory bank or peripherals.
BHE A0 Indication
0 0 Whole word
0 1 Upper byte from or to odd address
1 0 Lower byte from or to even address
1 1 None

RD : Read : whenever the read signal is at logic 0, the data bus receives the data from the
memory or  0 devices connected to the system
READY :This is the acknowledgement from the slow devices or memory that they have completed
the data transfer operation. This signal is active high.
INTR: Interrupt Request: Interrupt request is used to request a hardware interrupt of INTR is held
high when interrupt enable flag is set, the 8086 enters an interrupt acknowledgement cycle
after the current instruction has completed its execution.
TEST : This input is tested by “WAIT” instruction. If the TEST input goes low; execution will
continue. Else the processor remains in an idle state.
NMI- Non-maskable Interrupt: The non-maskable interrupt input is similar to INTR except that the
NMI interrupt does not check for interrupt enable flag is at logic 1, i.e, NMI is not maskable
internally by software. If NMI is activated, the interrupt input uses interrupt vector 2.
RESET: The reset input causes the microprocessor to reset itself. When 8086 reset, it restarts the
execution from memory location FFFF0H. The reset signal is active high and must be active
for at least four clock cycles.
CLK : Clock input: The clock input signal provides the basic timing input signal for processor and
bus control operation. It is asymmetric square wave with 33% duty cycle.
Vcc 5V power supply for the operation of the internal circuit
COND Ground for the internal circuit
MN / MX : The minimum/maximum mode signal to select the mode of operation either in minimum
or maximum mode configuration. Logic 1 indicates minimum mode.
Minimum mode Signals: The following signals are for minimum mode operation of 8086.
M / IO -Memory/IO M / I O signal selects either memory operation or  o operation. This line

indicates that the microprocessor address bus contains either a memory address or an  o
port address. Signal high at this pin indicates a memory operation. This line is logically
equivalent to S2 in maximum mode.
INTA - Interrupt acknowledge: The interrupt acknowledge signal is a response to the INTR input
signal. The INTA signal is normally used to gate the interrupt vector number onto the data
bus in response to an interrupt request.
ALE- Address Latch Enable: This output signal indicates the availability of valid address on the
address/data bus, and is connected to latch enable input of latches.
DT / R : Data transmit/Receive: This output signal is used to decide the direction of date flow
through the bi-directional buffer. DT / R  1 indicates transmitting and DT / R  0 indicates
receiving the data.
DEN Data Enable: Data bus enable signal indicates the availability of valid data over the
address/data lines.

HOLD: The hold input request a direct memory access(DMA). If the hold signal is at logic 1, the
micro process stops its normal execution and places its address, data and control bus at the
high impedance state.
HLDA: Hold acknowledgement indicates that 8086 has entered into the hold state.
Maximum mode signal: The following signals are for maximum mode operation of 8086.
S 2 , S1 , S 0 - Status lines: These are the status lines that reflect the type of operation being carried out
by the processor.
These status lines are encoded as follows
S2 S1 S0 Function
0 0 0 Interrupt Acknowledge
0 0 1 Read  o port
0 1 0 Write  o port
0 1 1 Halt
1 0 0 Code Access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 passive
LOCK : The lock output is used to lock peripherals off the system, ie, the other system bus masters
will be prevented from gaining the system bus.
QS1 and QS 0 - Queue status: The queue status bits shows the status of the internal instruction queue.
The encoding of these signals is as follows
QS1 QS 0 Function
0 0 No operation, queue is idle
0 1 First byte of opcode
1 0 Queue is empty
1 1 Subsequent byte of opcode
RQ / GT 1 and RQ / GT 0 - request/Grant: The request/grant pins are used by other local bus masters
to force the processor to release the local bus at the end of the processors current bus cycle.
These lines are bi-directional and are used to both request and grant a DMA operation.
RQ / GT 0 is having higher priority than RQ / GT 1
Physical Memory Organization
In an 8086 based system, the 1Mbyte memory is physically organized as odd bank and even bank,
each of 512kbytes, addressed in parallel by the processor.
Byte data with even address is transferred on D7  D0 and byte data with odd address is transferred
on D15  D8 .
The processor provides two enable signals, BHE and A0 for selecting of either even or odd or both
the banks.

FIG
BHE A0 Function are the
0 0 Whole word common signal line in 8086 as
0 1 Upper byte/ odd address
1 0 Lower byte/even address
1 1 none
If the address bus contains FFFFOH

If BHE  0 , then it reads the 16 bits data from memory location FFFFOH and FFFF1H .
If BHE  1 , it reads the 8 bits data from memory location FFFFOH
The block diagram of 8086 is as shown. This can be subdivided into two parts, namely the Bus
Interface Unit and Execution Unit. The Bus Interface Unit consists of segment registers, adder to
generate 20 bit address and instruction prefetch queue.
Once this address is sent out of BIU, the instruction and data bytes are fetched from memory and
they fill a First In First Out 6 byte queue.
Execution Unit: The execution unit consists of scratch pad registers such as 16-bit AX , BX, CX
and DX and pointers like SP (Stack Pointer), BP (Base Pointer) and finally index registers such as
source index and destination index register s. The 16-bit scratch pad registers can be split into two
8-bit registers. For example, AX can be split into AH and AL registers. The segment registers and
their default offsets are given below.

Segment Register Default Offset
CS IP (Instruction Pointer)
DS SI, DI
SS SP, BP
ES DI
The Arithmetic and Logic Unit adjacent to these registers perform all the operations. The results of
these operations can affect the condition flags.
Different registers and their operations are listed below:
Register Operations
AX Word multiply, Word divide, word I/O
AL Byte Multiply, Byte Divide, Byte I/O, translate, Decimal Arithmetic
AH Byte Multiply, Byte Divide
BX Translate
CX String Operations, Loops
CL Variable Shift and Rotate
DX Word Multiply, word Divide, Indirect I/O
8086/8088 MPU MEMORY

00000016
IP Instruction Pointer
CS Code Segment Register
Code Segment (64Kb)

DS Data Segment Register
SS Stack Segment Register
Data Segment (64Kb)

ES Extra Segment Register
AX AH AL
Stack Segment (64Kb)

BX BE BL
CX CE CL
Extra Segment (64Kb)

DX DH DL
SP Stack Pointer Register

FFFFF16
BP Break Pointer Register
SI Source Index Register
DI Destination Index Register
SR Status Register
Generation of 20-bit Physical Address:

8086 flag register format
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
U U U U 0F DF IF TF SF ZF U AF U PF U CF
U= UNDEFINED
CARRY FLAG – SET BY CARRY OUT OF MSB
PARITY FLAG – SET IF RESULT HAS EVEN PARITY

AUXILIARY CARRY FLAG FOR BCD
ZERO FLAG – SET IF RESULT = 0
SIGN FLAG = MSB OF RESULT

SINGLE STEP TRAP FLAG
INTERRUPT ENABLE FLAG
STRING DIRECTION FLAG

OVERFLOW FLAG
There are three internal buses, namely A bus, B bus and C bus, which interconnect the various
blocks inside 8086.
The execution of instruction in 8086 is as follows:
The microprocessor unit (MPU) sends out a 20-bit physical address to the memory and fetches the
first instruction of a program from the memory. Subsequent addresses are sent out and the queue is
filled upto 6 bytes. The instructions are decoded and further data (if necessary) are fetched from
memory. After the execution of the instruction, the results may go back to memory or to the output
peripheral devices as the case may be machine language.
1.3 Addressing modes
When 8086 executes an instruction, it performs the specified function on data. These data are called
its operands and may be part of the instruction, reside in one of the internal registers of the
microprocessor, stored at an address in memory or held at an I/O port, to access these different types
of operands, the 8086 is provided with various addressing modes (Data Addressing Modes).
Data Addressing Modes of 8086
The 8086 has 12 addressing modes. The various 8086 addressing modes can be classified into five
groups.
A. Addressing modes for accessing immediate and register data (register and immediate
modes).
B. Addressing modes for accessing data in memory (memory modes)
C. Addressing modes for accessing I/O ports (I/O modes)
D. Relative addressing mode
E. Implied addressing mode

8086 ADDRESSING MODES

A. Immediate addressing mode:
In this mode, 8 or 16 bit data can be specified as part of the instruction.
OP Code Immediate Operand
Example 1 : MOV CL, 03 H

Moves the 8 bit data 03 H into CL
Example 2 : MOV DX, 0525 H

Moves the 16 bit data 0525 H into DX
In the above two examples, the source operand is in immediate mode and the destination operand is
in register mode.
A constant such as “VALUE” can be defined by the assembler EQUATE directive such as
VALUE EQU 35H
Example : MOV BH, VALUE
Used to load 35 H into BH
Register addressing mode :
The operand to be accessed is specified as residing in an internal register of 8086. Fig. below shows
internal registers, any one can be used as a source or destination operand, however only the data
registers can be accessed as either a byte or word.
Operand sizes
Register
Byte (Reg 8) Word (Reg 16)
Accumulator AL, AH Ax
Base BL, BH Bx

Count CL, CH Cx
Data DL, DH Dx
Stack pointer - SP
Base pointer - BP
Source index - SI
Destination index - DI
Code Segment - CS
Data Segment - DS
Stack Segment - SS
Extra Segment - ES
Example 1 : MOV DX (Destination Register) , CX (Source Register)
Which moves 16 bit content of CS into DX.
Example 2 : MOV CL, DL
Moves 8 bit contents of DL into CL
MOV BX, CH is an illegal instruction.
* The register sizes must be the same.
B. Direct addressing mode :
The instruction Opcode is followed by an affective address, this effective address is directly used
as the 16 bit offset of the storage location of the operand from the location specified by the current
value in the selected segment register.
The default segment is always DS.

The 20 bit physical address of the operand in memory is normally obtained

as PA = DS : EA
But by using a segment override prefix (SOP) in the instruction, any of the four segment registers
can be referenced,
PA = CS
DS : Direct Address
SS
ES
The Execution Unit (EU) has direct access to all registers and data for register and immediate
operands. However the EU cannot directly access the memory operands. It must use the BIU, in
order to access memory operands.
In the direct addressing mode, the 16 bit effective address (EA) is taken directly from the
displacement field of the instruction.
Example 1 : MOV CX, START
If the 16 bit value assigned to the offset START by the programmer using an assembler pseudo
instruction such as DW is 0040 and [DS] = 3050.
Then BIU generates the 20 bit physical address 30540 H.
The content of 30540 is moved to CL
The content of 30541 is moved to CH
Example 2 : MOV CH, START
If [DS] = 3050 and START = 0040
8 bit content of memory location 30540 is moved to CH.

Example 3 : MOV START, BX
With [DS] = 3050, the value of START is 0040.
Physical address : 30540
MOV instruction moves (BL) and (BH) to locations 30540 and 30541 respectively.
Register indirect addressing mode :
The EA is specified in either pointer (BX) register or an index (SI or DI) register. The 20 bit
physical address is computed using DS and EA

Example : MOV [DI], BX

register indirect
If [DS] = 5004, [DI] = 0020, [Bx] = 2456 PA=50060.
The content of BX(2456) is moved to memory locations 50060 H and 50061 H.
CS
PA = DS BX
SS = SI
ES DI
Based addressing mode:
CS
PA = DS BX
SS : or + displacement
ES BP
when memory is accessed PA is computed from BX and DS when the stack is accessed PA is
computed from BP and SS.
Example : MOV AL, START [BX]
or
MOV AL, [START + BX] based

mode
EA : [START] + [BX]
PA : [DS] + [EA]
The 8 bit content of this memory location is moved to AL.
Indexed addressing mode:

CS
PA = DS SI
SS : or + 8 or 16bit displacement
ES DI

Example : MOV BH, START [SI]

PA : [SART] + [SI] + [DS]

The content of this memory is moved into BH.
Based Indexed addressing mode:

CS
PA = DS BX SI
SS : or +or + 8 or 16bit displacement
ES BP DI
Example : MOV ALPHA [SI] [BX], CL
If [BX] = 0200, ALPHA – 08, [SI] = 1000 H and [DS] = 3000
Physical address (PA) = 31208
8 bit content of CL is moved to 31208 memory address.
String addressing mode:
The string instructions automatically assume SI to point to the first byte or word of the source
operand and DI to point to the first byte or word of the destination operand. The contents of SI and
DI are automatically incremented (by clearing DF to 0 by CLD instruction) to point to the next
byte or word.
Example : MOV S BYTE
If [DF] = 0, [DS] = 2000 H, [SI] =

0500, [ES] = 4000, [DI] = 0300
Source address : 20500, assume it contains 38
PA : [DS] + [SI]
Destination address : [ES] + [DI] = 40300, assume it contains 45
After executing MOV S BYTE,
[40300] = 38

[SI] = 0501 incremented
[DI] = 0301
C. I/O mode (direct) :
Port number is an 8 bit immediate operand.
Example : OUT 05 H, AL
Outputs [AL] to 8 bit port 05 H

I/O mode (indirect):
The port number is taken from DX.
Example 1 : INAL, DX
If [DX] = 5040
8 bit content by port 5040 is moved into

AL. Example 2 : IN AX, DX
Inputs 8 bit content of ports 5040 and 5041 into AL and AH respectively.
D. Relative addressing mode:
Example : JNC START
If CY=O, then PC is loaded with current PC contents plus 8 bit signed value of START, otherwise
the next instruction is executed.
E. Implied addressing mode:
Instruction using this mode have no operands.
Example : CLC which clears carry flag to zero.
SINGLE INDEX DOUBLE INDEX

OR
BX
DI
OR
Explicit in the
BP
Encoded instruction
in the OR
instruction
SI

MICROPROCESSORS
15EC42
Assumed
unless
BX SI
over
ridden OR OR
by prefix
BP DI
+ EU
+ DISPLACEMENT +
CS 0000
OR
DS 0000
OR
SS 0000 BIU
OR
+ ES 0000
+
PHYSICAL ADDRESS

Special functions of general-purpose registers:
AX & DX registers:
In 8 bit multiplication, one of the operands must be in AL. The other operand can be a byte in
memory location or in another 8 bit register. The resulting 16 bit product is stored in AX, with AH
storing the MS byte.
In 16 bit multiplication, one of the operands must be in AX. The other operand can be a word in
memory location or in another 16 bit register. The resulting 32 bit product is stored in DX and
AX, with DX storing the MS word and AX storing the LS word.
BX register : In instructions where we need to specify in a general purpose register the 16 bit
effective address of a memory location, the register BX is used (register indirect).
CX register : In Loop Instructions, CX register will be always used as the implied counter.
In I/O instructions, the 8086 receives into or sends out data from AX or AL depending as a word
or byte operation. In these instructions the port address, if greater than FFH has to be given as the
contents of DX register.
Ex : IN AL, DX
DX register will have 16 bit address of the I/P device
Physical Address (PA) generation :
Generally Physical Address (20 Bit) = Segment Base Address (SBA)

+ Effective Address (EA)
Code Segment :
Physical Address (PA) = CS Base Address
+ Instruction Pointer (IP)
Data Segment (DS)
PA = DS Base Address + EA can be in BX or SI or DI
Stack Segment (SS)

PA + SS Base Address + EA can be SP or BP
Extra Segment (ES)
PA = ES Base Address + EA in DI
1.4 Machine language instruction formats
The 8086 instruction sizes vary from one to six bytes. The OP code occupies six bytes and it
defines the operation to be carried out by the instruction.
Register Direct bit (D) occupies one bit. It defines whether the register operand in byte 2 is the
source or destination operand.

D=1 Specifies that the register operand is the destination operand.
D=0 indicates that the register is a source operand.
Data size bit (W) defines whether the operation to be performed is an 8 bit or 16 bit data
W=0 indicates 8 bit operation
W=1 indicates 16 bit operation
Byte 3 Byte 4
7 2 1 0 7 6 5 4 3 2 10
Low Disp/ High Disp/

Opcode D W MOD REG R/M
DATA DATA
Byte 1 Byte 2 OR
DIRECT DIRECT
ADDRESS LOW ADDRESS HIGH
BYTE BYTE
Register Operand/Register to use EA
Calculation
Register Operand/Extension of opcode

Register mode/Memory mode

with displacement length
Word/byte operation
Direction is to register/from register
Operation code
The second byte of the instruction usually identifies whether one of the operands is in memory or
whether both are registers.
This byte contains 3 fields. These are the mode (MOD) field, the register (REG) field and the
Register/Memory (R/M) field.
MOD (2 bits) Interpretation
00 Memory mode with no displacement follows except for 16 bit

displacement when R/M=110
01 Memory mode with 8 bit displacement
10 Memory mode with 16 bit displacement

11 Register mode (no displacement)
Register field occupies 3 bits. It defines the register for the first operand which is specified as
source or destination by the D bit.
REG W=0 W=1
000 AL AX
001 CL CX
010 DL DX
011 BL BX
100 AH SP
101 CH BP
110 DH SI
111 BH DI
The R/M field occupies 3 bits. The R/M field along with the MOD field defines the second
operand as shown below.
MOD 11
R/M W=0 W=1
000 AL AX
001 CL CX
010 DL DX
011 BL BX
100 AH SP

101 CH BP
110 DH SI
111 BH DI
Effective Address Calculation
R/M MOD=00 MOD 01 MOD 10
000 (BX) + (SI) (BX)+(SI)+D8 (BX)+(SI)+D16
001 (BX)+(DI) (BX)+(DI)+D8 (BX)+(DI)+D16
010 (BP)+(SI) (BP)+(SI)+D8 (BP)+(SI)+D16
011 (BP)+(DI) (BP)+(DI)+D8 (BP)+(DI)+D10
100 (SI) (SI) + D8 (SI) + D16

101 (DI) (DI) + D8 (DI) + D16
110 Direct address (BP) + D8 (BP) + D16
111 (BX) (BX) + D8 (BX) + D16
In the above, encoding of the R/M field depends on how the mode field is set. If MOD=11 (register
to register mode), this R/M identifies the second register operand.
MOD selects memory mode, then R/M indicates how the effective address of the memory operand
is to be calculated. Bytes 3 through 6 of an instruction are optional fields that normally contain the
displacement value of a memory operand and / or the actual value of an immediate constant
operand.
Example 1 : MOV CH, BL
This instruction transfers 8 bit content of BL
Into CH
The 6 bit Opcode for this instruction is 1000102 D bit indicates whether the register specified by
the REG field of byte 2 is a source or destination operand.
D=0 indicates BL is a source operand.

W=0 byte operation
In byte 2, since the second operand is a register MOD field is 112.
The R/M field = 101 (CH)
Register (REG) field = 011 (BL)
Hence the machine code for MOV CH, BL is
10001000 11 011 101

Byte 1 Byte2
= 88DD16

Example 2 : SUB Bx, (DI)
This instruction subtracts the 16 bit content of memory location addressed by DI and DS from Bx.
The 6 bit Opcode for SUB is 0010102.
D=1 so that REG field of byte 2 is the destination operand. W=1 indicates 16 bit operation.
MOD = 00
REG = 011
R/M = 101
The machine code is 0010 1011 0001 1101
2 B 1 D
2B1D16
MOD / R/M Memory Mode (EA Calculation) Register Mode
00 01 10 W=0 W=1
000 (BX)+(SI) (BX)+(SI)+d8 (BX)+(SI)+d16 AL AX
001 (BX) + (DI) (BX)+(DI)+d8 (BX)+(DI)+d16 CL CX
010 (BP)+(SI) (BP)+(SI)+d8 (BP)+(SI)+d16 DL DX
011 (BP)+(DI) (BP)+(DI)+d8 (BP)+(DI)+d16 BL BX

100 (SI) (SI) + d8 (SI) + d16 AH SP
101 (DI) (DI) + d8 (DI) + d16 CH BP
110 d16 (BP) + d8 (BP) + d16 DH SI
111 (BX) (BX) + d8 (BX) + d16 BH DI
Summary of all addressing modes
Example 3 : Code for MOV 1234 (BP), DX

Here we have specify DX using REG field, the D bit must be 0, indicating the DX is the source
register. The REG field must be 010 to indicate DX register. The W bit must be 1 to indicate it is a
word operation. 1234 [BP] is specified using MOD value of 10 and R/M value of 110 and a
displacement of 1234H. The 4 byte code for this instruction would be 89 96 34 12H.
Opcode D W MOD REG R/M LB displacement HB displacement
100010 0 1 10 010 110 34H 12H
Example 4 : Code for MOV DS : 2345 [BP], DX
Here we have to specify DX using REG field. The D bit must be o, indicating that Dx is the source
register. The REG field must be 010 to indicate DX register. The w bit must be 1 to indicate it is a
word operation. 2345 [BP] is specified with MOD=10 and R/M = 110 and displacement = 2345 H.
Whenever BP is used to generate the Effective Address (EA), the default segment would be SS. In
this example, we want the segment register to be DS, we have to provide the segment override
prefix byte (SOP byte) to start with. The SOP byte is 001 SR 110, where SR value is provided as
per table shown below.

SR Segment register
00 ES
01 CS
10 SS
11 DS
To specify DS register, the SOP byte would be 001 11 110 = 3E H. Thus the 5 byte code for this
instruction would be 3E 89 96 45 23 H.
SOP Opcode D W MOD REG R/M LB disp. HD disp.
3EH 1000 10 0 1 10 010 110 45 23
Suppose we want to code MOV SS : 2345 (BP), DX. This generates only a 4 byte code, without
SOP byte, as SS is already the default segment register in this case.
1.5 DATA TRANSFER AND ARITHMETIC INSTRUCTIONS
Assembler instruction format, data transfer and arithmetic, branch type, loop, NOP & HALT, flag
manipulation, logical and shift and rotate instructions. Illustration of these instructions with
example programs, Directives and operators
Instruction Set
We only cover the small subset of the 8088 instruction set that is essential. In particular, we will
not mention various registers, addressing modes and instructions that could often provide faster
ways of doing things.A summary of the 80x86 protected-mode instruction set is available on the
course Web page and should be printed out if you don‟t have another reference.
Data Transfer

The MOV instruction is used to transfer 8 and 16-bit data to and from registers. Either the source
or destination has to be a register. The other operand can come from another register, from
memory, from immediate data (a value included in the instruction) or from a memory location
“pointed at” by register BX.
For example, if COUNT is the label of a memory location the following are possible assembly-
language instructions : ;
register: move contents of BX to AX
MOV AX,BX ; direct: move contents of AX to memory

MOV COUNT,AX ; immediate: load CX with the value
240 MOV CX,0F0H; memory: load CX with the value at
; address 240
MOV CX,[0F0H]; register indirect: move contents of AL

; to memory location in BX
MOV [BX],AL
Most 80x86 assemblers keep track of the type of each symbol and require a type “override” when
thesymbol is used in a different way. The OFFSET operator to convert a memory reference to a
16-bit value.
For example:
MOV BX,COUNT ; load the value at location COUNT

MOV BX,OFFSET COUNT ; load the offset of COUNT
16-bit registers can be pushed (the SP is first decremented by two and then the value stored at SP)
or popped (the value is restored from the memory at SP and then SP is incremented by 2). For
example:
PUSH AX ; push contents of

AX POP BX ; restore into BX

Arithmetic instruction:
Arithmetic/Logic
Arithmetic and logic instructions can be performed on byte and 16-bit values. The first operand
has to be a register and the result is stored in that register.
ADD BX,4;
increment BX by 4
; subtract 1 from AL
SUB AL,1
; increment BX
INC BX
; compare (subtract and set flags
; but without storing

result) CMP AX,[MAX]
; mask in LS 4 bits of
AL AND AL,0FH
; divide AX by two
SHR AX
; set MS bit of CX
OR CX,8000H
; clear AX
XOR AX,AX

1.6 CONTROL/BRANCH INSTRUCTIONS, illustration with example

programs
The LOOP Instruction
This instruction decrements the cx register and then branches to the target location if the cx
register does not contain zero. Since this instruction decrements cx then checks for zero, if cx
originally contained zero, any loop you create using the loop instruction will repeat 65,536 times.
If you do not want to execute the loop when cx contains zero, use jcxz to skip over the loop. There
is no “opposite” form of the loop instruction, and like the jcxz/jecxz instructions the range is
limited to ±128 bytes on all processors. If you want to extend the range of this instruction, you will
need to break it down into discrete components:
; “loop lbl” becomes:
dec cx
jne lbl
There is no loop instruction that decrements ecx and branches if not zero (there is a loope
instruction, but it does something else entirely). The reason is quite simple. As of the 80386,
Intel‟s designers stopped wholeheartedly supporting the loop instruction. Oh, it‟s there to ensure
compatibility with older code, but it turns out that the dec/jne instructions are actually faster on the
32 bit processors. Problems in the decoding of the instruction and the operation of the pipeline are
responsible for this strange turn of events. Although the loop instruction‟s name suggests that you
would normally create loops with it, keep in mind that all it is really doing is decrementing cx and
branching to the target address if cx does not contain zero after the decrement. You can use this
instruction anywhere you want to decrement cx and then check for a zero result, not just when
creating loops. Nonetheless, it is a very convenient instruction to use if you simply want to repeat a
sequence of instructions some number of times. For example, the following loop initializes a 256
element array of bytes to the values 1, 2, 3, ...
mov ecx, 255
ArrayLp: mov Array[ecx],

cl loop ArrayLp
mov Array[0], 0

The last instruction is necessary because the loop does not repeat when cx is zero.
Therefore, the last element of the array that this loop processes is Array[1], hence the last
instruction. The loop instruction does not affect any flags.
The LOOPE/LOOPZ Instruction
Loope/loopz (loop while equal/zero, they are synonyms for one another) will branch to the
target address if cx is not zero and the zero flag is set. This instruction is quite useful
The 80x86 Instruction Set after cmp or cmps instruction, and is marginally faster than the
comparable 80386/486 instructions if you use all the features of this instruction. However, this
instruction plays havoc with the pipeline and superscalar operation of the Pentium so you‟re
probably better off sticking with discrete instructions rather than using this instruction. This
instruction does the following:
cx := cx - 1
if ZeroFlag = 1 and cx ¹ 0, goto target The loope instruction falls through on one of two conditions.
Either the zero flag is clear or the instruction decremented cx to zero. By testing the zero flag after
the loop instruction (with a je or jne instruction, for example), you can determine the cause of
termination. This instruction is useful if you need to repeat a loop while some value is equal to
another, but there is a maximum number of iterations you want to allow. For example, the
following loop scans through an array looking for the first non-zero byte, but it does not scan
beyond the end of the array:
mov cx, 16 ;Max 16 array elements.
mov bx, -1 ;Index into the array (note next inc).

SearchLp: inc bx ;Move on to next array
element. cmp Array[bx], 0 ;See if this element is
zero. loope SearchLp ;Repeat if it is.
je AllZero ;Jump if all elements were zero.
Note that this instruction is not the opposite of loopnz/loopne. If you need to extend this jump
beyond ±128 bytes, you will need to synthesize this instruction using discrete instructions. For

example, if loope target is out of range, you would need to use an instruction sequence like the
following:
jne quit
dec cx
je Quit2
jmp Target
quit: dec cx ;loope decrements cx, even if

ZF=0. quit2:
The loope/loopz instruction does not affect any flags.
The LOOPNE/LOOPNZ Instruction
This instruction is just like the loope/loopz instruction in the previous section except
loopne/loopnz (loop while not equal/not zero) repeats while cx is not zero and the zero flag is
clear. The algorithm is
cx := cx - 1
if ZeroFlag = 0 and cx ¹ 0, goto target
You can determine if the loopne instruction terminated because cx was zero or if the zero flag was
set by testing the zero flag immediately after the loopne instruction. If the zero flag is clear at that
point, the loopne instruction fell through because it decremented cx to zero. Otherwise it fell
through because the zero flag was set.
This instruction is not the opposite of loope/loopz. If the target address is out of range,
you will need to use an instruction sequence like the following:
je quit
dec cx
je Quit2
jmp Target
quit: dec cx ;loopne decrements cx, even if ZF=1.

quit2:

You can use the loopne instruction to repeat some maximum number of times while waiting for
some other condition to be true. For example, you could scan through an array until you exhaust
the number of array elements or until you find a certain byte using a loop like the following:
mov cx, 16 ;Maximum # of array

elements. mov bx, -1 ;Index into array.
LoopWhlNot0: inc bx ;Move on to next array element.

cmp Array[bx],0 ;Does this element contain zero?
loopne LoopWhlNot0 ;Quit if it does, or more than 16 bytes.
Although the loope/loopz and loopne/loopnz instructions are slower than the individual instruction
from which they could be synthesized, there is one main use for these instruction forms where
speed is rarely important; indeed, being faster would make them less useful – timeout loops during
I/O operations. Suppose bit #7 of input port 379h contains a one if the device is busy and contains
a zero if the device is not busy. If you want to output
data to the port, you could use code like the

following: mov dx, 379h
WaitNotBusy: in al, dx ;Get port

test al, 80h ;See if bit #7 is one
jne WaitNotBusy ;Wait for “not busy”
The only problem with this loop is that it is conceivable that it would loop forever. In a real
system, a cable could come unplugged, someone could shut off the peripheral device, and any
number of other things could go wrong that would hang up the system.Robust programs usually
apply a timeout to a loop like this. If the device fails to become busy within some specified amount
of time, then the loop exits and raises an error condition. The following code will accomplish this:
mov dx, 379h ;Input port address
mov cx, 0 ;Loop 65,536 times and then quit.

WaitNotBusy: in al, dx ;Get data at port.
test al, 80h ;See if busy
loopne WaitNotBusy ;Repeat if busy and no time out.

jne TimedOut ;Branch if CX=0 because we timed out.

You could use the loope/loopz instruction if the bit were zero rather than
one. The loopne/loopnz instruction does not affect any flags.
Logical, Shift, Rotate and Bit Instructions
The 80x86 family provides five logical instructions, four rotate instructions, and three shift
instructions. The logical instructions are and, or, xor, test, and not; the rotates are ror,
rol, rcr, and rcl; the shift instructions are shl/sal, shr, and sar. The 80386 and later processors
provide an even richer set of operations. These are bt, bts, btr, btc, bsf, bsr, shld, shrd, and
theconditional set instructions (setcc). These instructions can manipulate bits, convert values, do
logical operations, pack and unpack data, and do arithmetic operations. The following sections
describe each of these instructions in detail.
1.7 OUTCOMES:
1. knowledge of basics of microprocessor and in detail about 8086

2. can build and program microprocessor based system
1.8 Questions/ Answers:
1. Draw a neat diagram of the internal architecture of 8086 and explain.

2. Write the position of each of the flags in PSW register. Write the salient features of each of
the flags briefly.
3. What are the addressing modes of 8086? Give an example of each of them.
1.9 Further Readings
1. Advanced Microprocessors and Peripherals - A.K. Ray and K.M. Bhurchandi, TMH, 3rd
Edition, 2012, ISBN 978-1-25-900613-5.

MODULE 2: INSTRUCTION SET OF 8086 (continued)
Structure
2.1 Objectives
2.2 Logical Instructions, String manipulation instructions
2.3 Flag manipulation and Processor control instructions
2.4 Illustration of these instructions with example programs
2.5 Assembler Directives and Operators
2.6 Assembly Language Programming and example programs
2.7 Outcomes
2.8 Questions / answer
2.9 Further reading
2.1 Objectives
1. To learn instruction set and addressing modes of 8086
2.2 Logical Instructions, String manipulation instructions
The Logical Instructions: AND, OR, XOR, and NOT
The 80x86 logical instructions operate on a bit-by-bit basis. Both eight, sixteen, and thirty-two bit
versions of each instruction exist. The and, not, or, and xor instructions do the following:
and dest, source ;dest := dest and source

or dest, source ;dest := dest or source
xor dest, source ;dest := dest xor source
not dest ;dest := not dest
The specific variations are

and reg, reg
and mem, reg

and reg, mem

and reg, immediate data

and mem, immediate data
and eax/ax/al, immediate data
or uses the same formats as AND

xor uses the same formats as
AND not register
not mem
Except not, these instructions affect the flags as follows:
• They clear the carry flag.
• They clear the overflow flag.
• They set the zero flag if the result is zero, they clear it otherwise.
• They copy the H.O. bit of the result into the sign flag.
• They set the parity flag according to the parity (number of one bits) in the
result.
• They scramble the auxiliary carry flag. The not instruction does not affect any flags. Testing the
zero flag after these instructions is particularly useful. The and instruction sets the zero flag if the
two operands do not have any ones in corresponding bit positions (since this would produce a zero
result); for example, if the source operand contained a single one bit, then the zero flag will be set
if the corresponding destination bit is zero, itwill be one otherwise. The or instruction will only set
the zero flag if both operands contain zero. The xor instruction will set the zero flag only if both
operands are equal. Noticethat the xor operation will produce a zero result if and only if the two
operands are equal. Many programmers commonly use this fact to clear a sixteen bit register to
zero since an instruction of the form
Xor reg16, reg16 is shorter than the comparable mov reg,0 instruction. Like the addition and
subtraction instructions, the and, or, and xor instructions provide special forms involving the
accumulator register and immediate data. These forms are shorter and sometimes faster than the

general “register, immediate” forms. Although one does not normally think of operating on signed
data with these instructions, the 80x86 does provide a special form of the “reg/mem, immediate”
instructions that sign extend a value in the range -128..+127 to sixteen or thirty-two bits, as
necessary.The instruction‟s operands must all be the same size. On pre-80386 processors theycan
be eight or sixteen bits. On 80386 and later processors, they may be 32 bits long as well. These
instructions compute the obvious bitwise logical operation on their operands, You can use the and
instruction to set selected bits to zero in the destination operand. This is known as masking out
data; see for more details. Likewise, you can use the or instruction to force certain bits to one in the
destination operand; see “Masking Operations
with the OR Instruction” on page 491 for the details. You can use these instructions,
along with the shift and rotate instructions described next, to pack and unpack data.
The Shift Instructions: SHL/SAL, SHR, SAR, SHLD, and SHRD
The 80x86 supports three different shift instructions (shl and sal are the same instruction): shl
(shift left), sal (shift arithmetic left), shr (shift right), and sar (shift arithmetic right). The 80386
and later processors provide two additional shifts: shld and shrd. The shift instructions move bits
around in a register or memory location. The general format for a shift instruction is
shl dest, count

sal dest, count
shr dest, count
sar dest, count
Dest is the value to shift and count specifies the number of bit positions to shift. For example, the
shl instruction shifts the bits in the destination operand to the left the number of bit positions
specified by the count operand. The shld and shrd instructions use the format:
shld dest, source, count

shrd dest, source, count
The specific forms for these instructions

are shl reg, 1
shl mem, 1

shl reg, imm (2)

shl mem, imm (2)
shl reg, cl
shl mem, cl
sal is a synonym for shl and uses the same

formats. shr uses the same formats as shl.
sar uses the same formats as shl.

shld reg, reg, imm (3)
shld mem, reg, imm

(3) shld reg, reg, cl (3)
shld mem, reg, cl (3)
shrd uses the same formats as shld.
2- This form is available on 80286 and later processors only.

3- This form is available on 80386 and later processors only.
For 8088 and 8086 CPUs, the number of bits to shift is either “1” or the value in cl. On 80286 and
later processors you can use an eight bit immediate constant. Of course, the value in cl or the
immediate constant should be less than or equal to the number of bits in the destination operand. It
would be a waste of time to shift left al by nine bits (eight would produce the same result, as you
will soon see). Algorithmically, you can think of the shift operations with a count other than one as
follows:
for temp := 1 to count

do shift dest, 1
There are minor differences in the way the shift instructions treat the overflow flag when the count
is not one, but you can ignore this most of the time. The shl, sal, shr, and sar instructions work on
eight, sixteen, and thirty-two bit operands. The shld and shrd instructions work on 16 and 32 bit
destination operands only.
SHL/SAL
The shl and sal mnemonics are synonyms. They represent the same instruction and

use identical binary encodings. These instructions move each bit in the destination operand
one bit position to the left the number of times specified by the count operand. Zeros
fill vacated positions at the L.O. bit; the H.O. bit shifts into the carry flag (see Figure
6.2). The shl/sal instruction sets the condition code bits as follows:
• If the shift count is zero, the shl instruction doesn‟t affect any flags.
• The carry flag contains the last bit shifted out of the H.O. bit of the operand.
• The overflow flag will contain one if the two H.O. bits were different
prior to a single bit shift. The overflow flag is undefined if the shift
count is not one.
• The zero flag will be one if the shift produces a zero result.
• The sign flag will contain the H.O. bit of the result.
• The parity flag will contain one if there are an even number of one bits in
the L.O. byte of the result.
• The A flag is always undefined after the shl/sal instruction.
The shift left instruction is especially useful for packing data. For example, suppose you have two
nibbles in al and ah that you want to combine. You could use the following
code to do this:
shl ah, 4 ;This form requires an 80286 or later

or al, ah ;Merge in H.O. four bits.
Of course, al must contain a value in the range 0..F for this code to work properly (the shift
left operation automatically clears the L.O. four bits of ah before the or instruction). If the H.O.
four bits of al are not zero before this operation, you can easily clear them with an and instruction:
shl ah, 4 ;Move L.O. bits to H.O. position.
and al, 0Fh ;Clear H.O. four bits.

or al, ah ;Merge the bits.

Since shifting an integer value to the left one position is equivalent to multiplying that value by
two, you can also use the shift left instruction for multiplication by powers of two:
shl ax, 1 ;Equivalent to AX*2

shl ax, 5 ;Equivlaent to AX*32
shl ax, 7 ;Equivalent to
AX*128 shl ax, 8 ;Equivalent
to AX*256 etc.
Note that shl ax, 8 is equivalent to the following two

instructions: mov ah, al
mov al, 0
The shl/sal instruction multiplies both signed and unsigned values by two for each shift. This
instruction sets the carry flag if the result does not fit in the destination operand (i.e., unsigned
overflow occurs). Likewise, this instruction sets the overflow flag if the signed result does not fit
in the destination operation. This occurs when you shift a zero into the H.O. bit of a negative
number or you shift a one into the H.O. bit of a non-negative number.
SAR
The sar instruction shifts all the bits in the destination operand to the right one bit, replicating the
H.O. bit (see Figure 6.3). The sar instruction sets the flag bits as follows:
• If the shift count is zero, the sar instruction doesn‟t affect any flags.
• The carry flag contains the last bit shifted out of the L.O. bit of the operand.
• The overflow flag will contain zero if the shift count is one. Overflow can
never occur with this instruction. However, if the count is not one, the
value of the overflow flag is undefined.

• The zero flag will be one if the shift produces a zero result.
• The sign flag will contain the H.O. bit of the result.
• The parity flag will contain one if there are an even number of one bits in
the L.O. byte of the result.
• The auxiliary carry flag is always undefined after the sar instruction.
The sar instruction‟s main purpose is to perform a signed division by some power of two. Each
shift to the right divides the value by two. Multiple right shifts divide the previous shifted result by
two, so multiple shifts produce the following results:
sar ax, 1 ;Signed division by 2 sar

ax, 2 ;Signed division by 4 sar ax,
3 ;Signed division by 8 sar ax, 4
;Signed division by 16 sar ax, 5
;Signed division by 256
There is a very important difference between the sar and idiv instructions. The idiv instruction
always truncates towards zero while sar truncates results toward the smaller result. For positive
results, an arithmetic shift right by one position produces the same result as an integer division by
two. However, if the quotient is negative, idiv truncates towards zero while sar truncates towards
negative infinity. The following examples demonstrate the difference:
mov ax, -15

cwd
mov bx, 2
idiv ;Produces -7
mov ax, -15
sar ax, 1 ;Produces -8
Keep this in mind if you use sar for integer division operations.

The sar ax, 8 instruction effectively copies ah into al and then sign extends al into ax. This is
because sar ax, 8 will shift ah down into al but leave a copy of ah‟s H.O. bit in all the bit positions
of ah. Indeed, you can use the sar instruction on 80286 and later processors to sign extend one
register into another. The following code sequences provide examples of this usage:
; Equivalent to
CBW: mov ah, al
sar ah, 7
Strings and String Handling Instructions
The 8086 microprocessor is equipped with special instructions to handle string operations. By
string we mean a series of data words or bytes that reside in consecutive memory locations. The
string instructions of the 8086 permit a programmer to implement operations such as to move data
from one block of memory to a block elsewhere in memory. A second type of operation that is
easily performed is to scan a string and data elements stored in memory looking for a specific
value. Other examples are to compare the elements and two strings together in order to determine
whether they are the same or different.
Move String : MOV SB, MOV SW:
An element of the string specified by the source index (SI) register with respect to the current data
segment (DS) register is moved to the location specified by the destination index (DI) register with
respect to the current extra segment (ES) register.
The move can be performed on a byte (MOV SB) or a word (MOV SW) of data. After the move is
complete, the contents of both SI & DI are automatically incremented or decremented by 1 for a
byte move and by 2 for a word move. Address pointers SI and DI increment or decrement depends
on how the direction flag DF is set.
Example : Block move program using the move string instruction
MOV AX, DATA SEG ADDR

MOV DS, AX
MOV ES, AX
MOV SI, BLK 1 ADDR
MOV DI, BLK 2 ADDR
MOV CK, N
CDF ; DF=0
NEXT : MOV SB
LOOP NEXT
HLT
Load and store strings : (LOD SB/LOD SW and STO SB/STO SW)
LOD SB: Loads a byte from a string in memory into AL. The address in SI is used relative to DS
to determine the address of the memory location of the string element.
(AL)  [(DS) +
(SI)] (SI)  (SI) +
1
LOD SW : The word string element at the physical address derived from DS and SI is to be
loaded into AX. SI is automatically incremented by 2.
(AX)  [(DS) + (SI)]
(SI)  (SI) + 2
STO SB : Stores a byte from AL into a string location in memory. This time the contents of ES
and DI are used to form the address of the storage location in memory

[(ES) + (DI)] 
(AL) (DI)  (DI) +
1
STO SW : [(ES) + (DI)]  (AX)

(DI)  (DI) + 2
Flags
Mnemonic Meaning Format Operation
affected
Move ((ES)+(DI))((DS)+(SI))
MOV
MOV SB String (SI)(SI) 1 None
SB
Byte (DI)  1
MOV SW Move MOV ((ES)+(DI))((DS)+(SI)) None
String SW ((ES)+(DI)+1)(DS)+(SI)+1)
Word (SI)  (SI) 2
(DI)  (DI) 2
LOD
LOD SB / Load SB/ (AL) or (AX) ((DS)+(SI))
None
LOD SW String LOD (SI)(SI) 1 or 2
SW
STOSB/ Store STOSB/ ((ES)+(DI))(AL) or (AX)
None
STOSW String STOSW (DI)  (DI) 71 or 2
Example : Clearing a block of memory with a STOSB operation.

MOV AX, 0
MOV DS, AX
MOV ES, AX
MOV DI, A000
MOV CX, OF
CDF

AGAIN : STO SB
LOOP NE AGAIN
NEXT : Clear A000 to A00F to 0016
Repeat String : REP
The basic string operations must be repeated to process arrays of data. This is done by inserting a
repeat prefix before the instruction that is to be repeated.
Prefix REP causes the basic string operation to be repeated until the contents of register CX
become equal to zero. Each time the instruction is executed, it causes CX to be tested for zero, if
CX is found to be nonzero it is decremented by 1 and the basic string operation is repeated.
Example : Clearing a block of memory by repeating STOSB
MOV AX, 0
MOV ES, AX
MOV DI, A000
MOV CX, OF
CDF
REP STOSB
NEXT:
The prefixes REPE and REPZ stand for same function. They are meant for use with the CMPS and
SCAS instructions. With REPE/REPZ the basic compare or scan operation can be repeated as long
as both the contents of CX are not equal to zero and zero flag is 1.
REPNE and REPNZ works similarly to REPE/REPZ except that now the operation is repeated as
long as CX0 and ZF=0. Comparison or scanning is to be performed as long as the string elements
are unequal (ZF=0) and the end of the string is not yet found (CX0).

MICROPROCESSORS
15EC42
Prefix Used with

MOVS
REP Meaning
STOS
CMPS Repeat while not end of
REPE/ REPZ
SCAS string CX0
CMPS
REPNE/REPNZ
SCAS CX0 & ZF=1
Example : CLD ; DF =0
CX0 & ZF=0
MOV AX, DATA SEGMENT ADDR
MOV DS, AX
MOV AX, EXTRA SEGMENT ADDR
MOV ES, AX
MOV CX, 20
MOV SI, OFFSET MASTER
MOV DI, OFFSET COPY
REP MOVSB

Moves a block of 32 consecutive bytes from the block of memory locations starting at offset
address MASTER with respect to the current data segment (DS) to a block of locations starting at
offset address copy with respect to the current extra segment (ES).
2.3 Flag manipulation and Processor control instructions
SI & DI addresses are either automatically incremented or decremented based on the setting of the
direction flag DF. When CLD (Clear Direction Flag) is executed DF=0 permits auto increment by
1.When STD (Set Direction Flag) is executed DF=1 permits auto decrement by 1.
Flags
Mnemonic Meaning Format Operation
affected
CLD Clear DF CLD (DF)  0 DF
STD Set DF STD (DF)  1 DF
1. LDS Instruction:
LDS register, memory (Loads register and DS with words from memory)
This instruction copies a word from two memory locations into the register specified in the
instruction. It then copies a word from the next two memory locations into the DS register. LDS is
useful for pointing SI and DS at the start of the string before using one of the string instructions.
LDS affects no flags.
Example 1 :LDS BX [1234]
Copy contents of memory at displacement 1234 in DS to BL. Contents of 1235H to BH. Copy
contents at displacement of 1236H and 1237H is DS to DS register.
Example 2 : LDS, SI String – Pointer
(SI)  [String Pointer]
(DS)  [String Pointer +2]

DS, SI now points at start and desired string
2. LEA Instruction :
Load Effective Address (LEA register, source)
This instruction determines the offset of the variable or memory location named as the source and
puts this offset in the indicated 16 bit register.
LEA will not affect the

flags. Examples :
LEA BX, PRICES
Load BX with offset and PRICES in DS
LEA BP, SS : STACK TOP
Load BP with offset of stack-top in SS
LEA CX, [BX] [DI]
Loads CX with EA : (BX) + (DI)
3. LES instruction :
LES register, memory
Example 1: LES BX, [789A H]

(BX)  [789A] in DS
(ES)  [789C] in DS
Example 2 : LES DI, [BX]
(DI)  [BX] in DS

(ES)  [BX+2] in DS
Macros
 Macros provide several powerful mechanisms useful for the development of generic
programs.
• A Macro is a group of instructions with a name.
• When a macro is invoked, the associated set of instructions is inserted in place in to the
source, replacing the macro name. This “macro expansion” is done by a Macro
Preprocessor and it happens before assembly. Thus the actual Assembler sees the
“expanded” source!
• We could consider the macro as shorthand for a piece of text; somewhat like a new pseudo-
code instruction.
Macros and Procedures:
 Macros are similar to procedures in some respects, yet are quite different in many other
respects.

 Procedure:

 Only one copy exists in memory. Thus memory consumed is less.

 “Called” when required;

 Execution time overhead is present because of the call and return instructions.

 Macro:

 When a macro is “invoked”, the corresponding text is “inserted” in to the source. Thus
multiple copies exist in the memory leading to greater space requirements.

 However, there is no execution overhead because there are no additional call and return
instructions. The code is in-place.
These concepts are illustrated in the following figure:

MACRO Definition:
A macro has a name. The body of the macro is defined between a pair of directives, MACRO
and ENDM. Two macros are defined in the example given below.
Examples of Macro Definitions:
; Definition of a Macro named PA2C
PA2CMACRO
PUSH AX
PUSH BX
PUSH CX
ENDM
; Another Macro named POPA2C is defined here
POPA2CMACRO
POP CX
POP BX
POP AX
ENDM

Examples of Macro usage:
The following examples illustrate the use of macros. We first show the source with macro
invocation and then show how the expanded source looks.
Program with macro invocations:
PA2C
MOV CX, DA1
MOV BX, DA2
ADD AX, BX
ADD AX, CX
MOV DA2, AX
POPA2C
When the Macro Preprocessor expands the macros in the above source, the expanded source
looks as shown below:
PUSH AX
PUSH BX
PUSH CX
MOV CX, DA1
MOV BX, DA2
ADD AX, BX
ADD AX, CX
MOV DA2, AX

POP CX
POP BX
POP AX
Note how the macro name is replaced by the associated set of instructions. Thus, macro name
does not appear in the expanded source code. In other words, the actual Assembler does not
“see” the macros. What gets assembled is the expanded source. This process is illustrated in the
following figure:
MACROS with Parameters:
Macros have several other interesting and powerful capabilities. One of these is the definition
and use of macros with parameters.
A macro can be defined with parameters. These are dummy parameters. When the macro is
invoked, we provide the actual parameters. During the macro expansion, the dummy
parameters are replaced by the corresponding actual parameters. The association between the
dummy and actual parameters is positional. Thus the first actual parameter is associated with the
first dummy parameter, the second actual parameter with the second dummy one and so on.
This is illustrated in the following example where a Macro named COPY is defined with two
parameters called A and B.
Example:
COPY MACRO A,B
PUSH AX

MOV AX, B
MOV A, AX
POP AX
ENDM
The macro is invoked in the following code with actual parameters as VAR1 and VAR2. Thus
during the macro expansion, the parameter A is replaced by VAR1 and the parameter B is
replaced by VAR2.
COPY VAR1, VAR2
The expanded code is:
PUSH AX
MOV AX, VAR2
MOV VAR1, AX
POP AX
Local Variables in a Macro:
• Assume that a macro definition includes a label RD1 as in the following example:
READ MACRO A
PUSH DX
RD1: MOV AH, 06
MOV DL, 0FFH
INT 21H

JE RD1 ;; No key, try again
MOV A, AL
POP DX
ENDM
• If READ macro is invoked more than once, as in
READ VAR1
READ VAR2
assembly error results!
• The problem is that the label RD1 appears in the expansion of READ VAR1 as well as in the
expansion of READ VAR2. Hence, the label RD1 appears in both the expansions. In other
words, the Assembler sees the label RD1 at two different places and this results in the
“Multiple Definition” error!
• SOLUTION: Define RD1 as a local variable in the macro.
READ MACRO A
LOCAL RD1
PUSH DX
RD1: MOV AH, 06
MOV DL, 0FFH
INT 21H
JE RD1 ;; No key, try again
MOV A, AL
POP DX

ENDM
• Now, in each invocation of READ, the label RD1 will be replaced, automatically, with a
unique label of the form ??xxxx ; where xxxx is a unique number generated by Assembler.
This eliminates the problem of multiple definitions in the expanded source.
• With the use of local variable as illustrated above,
READ VAR1
gets expanded as:
PUSH DX
??0000: MOV AH, 06
MOV DL, 0FFH
INT 21H
JE ??0000 ;; No key, try again
MOV VAR1, AL
POP DX
Subsequently, if we write
READ VAR2
it gets expanded as:
PUSH DX
??0001: MOV AH, 06
MOV DL, 0FFH
INT 21H

JE ??0001 ;; No key, try again
MOV VAR2, AL
POP DX
Note how each invocation of the READ macro gets expanded with a new and unique label,
generated automatically by the Assembler, in place of the local variable RD1. Further, note that
LOCAL directive must immediately follow the MACRO directive. Another feature to note is
that Comments in Macros are preceded by ;; (two semicolons) , and not as usual by ; (a single
semicolon).
File of Macros:
• We can place all the required Macros in a file of its own and then include the file into the
source.
• Example: Suppose the Macros are placed in D:\MYAPP\MYMAC.MAC

In the source file, we write
Advanced Features:
• Conditional Assembly
• REPEAT , WHILE, and FOR statements in MACROS
Conditional Assembly:
• A set of statements enclosed by IF and ENDIF are assembled if the condition stated with IF
is true; otherwise, the statements are not assembled; no code is generated.
• This is an Assembly time feature; not run-time behavior!
• Allows development of generic programs. From such a generic program, we can produce
specific source programs for specific application contexts.
• Example: Assume that our generic program has the following statements:

IF WIDT
WIDE DB 72
ELSE
WIDE DB 80
ENDIF
Now the assembly language program that is generated depends on the value of WIDT.
Assume the block is preceded by
WIDT EQU 1
Then the assembled code is:
WIDE DB 72
It is important to note that the Assembler sees a source file that has only the above
statement.
 Another case:
WIDT EQU 0
IF WIDT
WIDE DB 72
ELSE
WIDE DB 80
ENDIF
What gets assembled is: WIDE DB 80
 There are several other directives that can be used for Conditional Assembly as listed below:
IF If the expression is true

IFB If the argument is blank
IFNB If the argument is not blank
IFDEF If the label has been defined
IFNDEF If the label has not been defined
IFIDN If argument 1 equals argument 2
IFDIF If argument 1 does not equal argument 2
With each of the above constructs, the code that follows gets assembled only if the stated
condition is true.
REPEAT Statement:
This statement allows a block of code to be repeated the specified number of times. This avoids
repetitive typing and is much more elegant than Editor-level Copy-and-Paste operation.
Example:
REPEAT 3
INT 21H
INC DL
ENDM
The generated code would be 3 repetitions of the block of 2 statements enclosed within
REPEAT and ENDM as shown below:
INT 21H
INC DL
INT 21H
INC DL

INT 21H
INC DL

2.4 Illustration of these instructions with example programs
NUMBER FORMAT CONVERSION:
• Often Data available in one format needs to be converted in to some other format.
Examples:
 ASCII to Binary

 Binary to ASCII

 BCD to 7-Segment Code … … …

• Data Conversion may be based on
 Algorithm

 Look –Up Table
Converting from Binary to ASCII:
In many contexts, for example, when displaying a number on the screen, we must produce a
sequence of ASCII characters representing the number to be displayed. Thus the given number
must be converted to a string of equivalent ASCII characters.
• Example: Binary number: 0100 0011 = 43H = 67 D
To display this on the screen, we need to convert this binary number in to Two ASCII
characters, „6‟ and „7‟.
ASCII code for character „6‟ is 36H and
ASCII code for character „7‟ is 37H.
So, we need to produce 36H and 37H as output given 43H as input.

• Another Example: Binary number: 0000 0010 0100 0011 = 0243H = 579 D
To display this on the screen, we need Three ASCII characters, „5‟, „7‟ and
„9‟. ASCII code for character „5‟ is 35H,
ASCII code for character „7‟ is 37H, and
ASCII code for character „9‟ is 39H
So, we need to produce 35H, 37H and 39H as output given 0243H as input
Binary to ASCII Algorithm:
Example: Binary number: 0000 0010 0100 0011 = 579 D
• Divide 579 by 10 ; Quotient = 57 ; Remainder = 9 , Save 9
• Divide 57 by 10; Quotient = 5 ; Remainder = 7 , Save 7

• Divide 5 by 10; Quotient = 0 ; Remainder = 5 , Save 5
• Quotient = 0  Conversion Complete.
• Remainders saved in the order of 9, 7, and 5.
• Retrieve remainders in the order of 5, 7, and 9.
(As the order of retrieval is the reverse of the order of producing these digits, the most
convenient technique is to Save & Retrieve the digits using Stack)
• While retrieving, add 30H to convert the digit to ASCII code and then display it (or print it,
or save it…)
• Thus the algorithm is:
While the number is not equal to 0
Divide the number by 10;
Push the remainder digit on the stack;
Set number <- quotient

While stack not empty
Pop a digit from the stack
Add 30H to covert it to ASCII and display it
Return.
 This algorithm is implemented in the following program:
Binary to ASCII Program:

; Input : 16-Bit Binary Number in AX
; Output: Equivalent ASCII displayed on screen
.MODEL TINY
.CODE
.STARTUP
MOV AX, 2A5H ; Test value
CALL B2A ; Binary to ASCII and Display
.EXIT
B2A PROC NEAR
PUSH DX
PUSH CX
PUSH BX
MOV CX, 0 ; Count of ASCII digits, Initialized to 0
MOV BX, 10; Divisor is 10
B2A1: MOV DX, 0 ; Dividend in DX, AX. So set DX = 0
DIV BX ; Divide by 10
PUSH DX ; Save remainder digit on the stack
INC CX ; Increment digit count
OR AX, AX ; Conversion completed ? (Quotient, i.e AX = 0 ?)
JNZ B2A1 ; No, continue division
; Conversion is complete as quotient in AX = 0

; Count of remainder digits is in CX
B2A2: POP DX ; Retrieve remainder in DL

ADD DL, 30H ; Convert to ASCII
MOV AH, 06H ; Console Display Function
INT 21H ; DOS Service, display digit
LOOP B2A2 ; Repeat for all digits
; Clean up & Return. AX is destroyed
POP BX
POP CX
POP DX
RET
B2A ENDP
END
Another Method for Binary to ASCII Conversion:
• When the input number is less than 100, an alternative, simpler method exists.
• AAM (ASCII Adjust AX After Multiplication) instruction converts value in AX in to 2-

Digit Unpacked BCD and leaves it in AX.
• Example: AX = 0027H (39 Decimal)
Execute AAM ; Now, AX = 0309H ; This is Unpacked BCD.
• Now, add 3030H to AX to get 3339H ; This is Packed ASCII representation.
• Separate the two bytes (unpack) to get the two ASCII characters representing the given
number (33H and 39H).

• Works only when the number is less than 100 as the maximum unpacked BCD that we can
have in the AX register is 0909H only.
• The following program is developed based on this idea.
; Input : Binary Number in AL, Assumed <100
.MODEL TINY
.CODE
.STARTUP
MOV AL, 2AH ; Test value
.EXIT
B2A PROC NEAR
PUSH DX
MOV AH, 0 ; AX = Number
AAM ; AX = Unpacked BCD
ADD AX, 3030H ; Convert to ASCII

PUSH AX
; Now, unpack and display
MOV DL, AH ; First Digit

MOV AH, 06H ; Display Function
INT 21H ; Display first digit
POP AX ; Retrieve value
MOV DL, AL ; Second Digit
INT 21H ; Display second digit
POP DX
RET

B2A ENDP
END
Refinements:
• Suppose the input is: AL = 7H. What is displayed is 07
• Can we replace leading 0 with a blank so that the display looks better? Thus, instead of 07,
the display should be 7.
• Yes. We need to check if the first digit is 0. If so, display 20H (blank); else, display
the digit.
 We need to modify the previous program to incorporate this check for a leading 0.

 Old Code for displaying first digit:
MOV DL, AH ; First Digit

 Revised Code for displaying first digit:
ADD AH, 20H
CMP AH, 20H ; First Digit = 0?
JZ B2A1 ; Display blank (ASCII Code is 20H)
ADD AH, 10H ; Add 10H more to get the correct ASCII Code for the digit
B2A1: MOV DL , AH ; First Digit
MOV AH , 06H ; Display Function
 Incorporating this change, the program will be as shown below:
; Input : Binary Number in AL, Assumed <100
.MODEL TINY
.CODE

.STARTUP
MOV AL, 2AH ; Test value
.EXIT
B2A PROC NEAR
PUSH DX
MOV AH, 0 ; AX = Number
AAM ; AX = Unpacked BCD
ADD AX, 3030H ; Convert to ASCII
PUSH AX
; Now, unpack and display
ADD AH, 20H

CMP AH, 20H ; First Digit = 0?
JZB2A1 ; YES. So, display a blank (ASCII Code is 20H)
ADD AH, 10H ; No, we have already added 20H. Add 10H more
B2A1: MOV DL, AH ; First Digit itself if not 0 , Or Blank (if 0)
POP AX ; Retrieve value

MOV DL, AL ; Second Digit
INT 21H ; Display second digit
POP DX
RET
B2A ENDP
END
ASCII to Binary Algorithm:
In many contexts, for example, when reading a number from the key board, we get a sequence
of ASCII characters representing the number. This string of ASCII characters must be
converted to the equivalent number for further processing.
Example: Assume that ASCII character sequence „156‟ is the input.

• 3 characters, „1‟, „5‟, and „6‟; with codes as 31H, 35H, and 36H.
• Converted Binary Value must be:
0000 0000 1001 1100 = 009CH = 156 (decimal)
• Start with (Binary) Result = 0
• First ASCII digit 31H; Subtract 30H to get corresponding BCD digit 01H.
• Result = Result * 10 + Next BCD Digit Result

= 0 * 10 + 01 = 0000 0000 0000 0001
• Next ASCII digit 35H; Subtract 30H to get corresponding BCD digit 05H.

= 01 * 10 + 05 = 0000 0000 0000 1111
• Next ASCII digit 36H; Subtract 30H to get corresponding BCD digit 06H.

= 15 * 10 + 06 = 0000 0000 1001 1100
• ASCII digits exhausted. So, conversion is completed.
• Final Result = 0000 0000 1001 1100 = 009CH = 156 (decimal)
• Based on the above ideas, the following program implements the ASCII to Binary
Conversion.
; ASCII to Binary Program

; ASCII characters representing a number are read from key board.
; The first non-digit character (any character other than 0 through 9) typed
; signals the end of the number entry

; Result returned in AX, which is then stored in memory location TEMP.
; Result assumed not to exceed 16 bits!
; Program can be modified to accept larger numbers by implementing
; 32- bit addition.
.MODEL SMALL
.DATA
TEMP DW ?
.CODE
.STARTUP
CALL RDNUM
MOV TEMP, AX
.EXIT
RDNUM PROC NEAR
PUSH BX
PUSH CX
MOV CX, 10 ; Multiplier is 10
MOV BX, 0 ; Result initialized to 0
RDN1: MOV AH, 1 ; Read Key with Echo
INT 21H
; Check the character. If less than ‘0’ or greater than ‘9’ Number entry is over
CMP AL, ’0’

JB RDN2
CMP AL,’9’
JA RDN2
; Is digit. Update Result
SUB AL, 30H ; BCD Digit
PUSH AX
MOV AX, BX
MUL CX
MOV BX, AX ; Result = Result * 10
POP AX

MOV AH, 0 ; AX = Current Digit

ADD BX, AX ; Update Result
JMP RDN1 ; Repeat
; Non- digit. Clean Up and Return
RDN2: MOV AX, BX ; Result in AX
POP CX
POP BX
RET
RDNUM ENDP
END
Notes:
 The constant multiplier 10 is held in the register CX.


 In the procedure, RDNUM, the result is accumulated in the register BX and at the end,
it is moved in to register AX. The result in AX is moved, in the calling program, in to
the memory location TEMP.

 The BCD digit is in AL. AH is cleared to 0 so that the 16-bit value in AX represents the
correct value and thus can be added directly to the accumulating result in BX. This part
of the code must be changed to implement 32-bit addition if larger results are to be
supported.
Using Look – Up Tables for Data Conversion:
• Often, a look-up table simplifies data conversion.
• XLAT can be used if table has up to 256 byte-entries
• Value to be converted is used to index in to the table containing conversion values.
• As an example, we will demonstrate BCD to 7-Segment code conversion.
BCD to 7-Segment Code Conversion:
In many applications, we need to display BCD values on a 7-Segment display. The 7-Segment
display device, as the name suggests, has 7 segments which can be independently controlled to

be ON or OFF. Further, the device has a decimal point also that can be switched ON or OFF.
The 7 segments and the decimal point are controlled by 8 bits, with one bit controlling one
segment or the decimal point. The bit value required to switch on a segment depends on
whether the device is of a Common – Anode type or Common – Cathode type. Here, we are
assuming a Common – Anode type. Thus the segment will be ON if the corresponding
controlling bit is 1 and will be off if the bit is 0.
Based on the digit to be displayed, we must determine the segments that must be ON and the
ones that must be OFF. The bits controlling the segments that must be ON are set to 1 and the
bits controlling the segments that must be OFF are cleared to 0. The resulting bit pattern
determines the value of the 7-Segemnt code that must be output. This display structure is
shown in the following figure on the next page:
As an example of determining the display code corresponding to a given BCD digit, the
following figure shows the display of digit 3 and the determination of the corresponding 7-
Segment code:

Based on the above logic, the following FAR Procedure returns the 7-Segment code in the
AL register, corresponding to the BCD digit provided as input parameter in the AL register
before calling the procedure.
; BCD to 7-Segment Code Program
; Input: AL = BCD Digit
; Output: AL = 7-Segment code.
BT7SEG PROC FAR

PUSH BX
MOV BX, OFFSET TABLE
XLAT CS: TABLE
POP BX
RET
TABLE DB 3FH ; 0
DB 06H ; 1
DB 5BH ; 2
DB 4FH ; 3
DB 66H ; 4
DB 6DH ; 5
DB 7DH ; 6
DB 07H ; 7
DB 7FH ; 8
DB 6FH ; 9
BT7SEG ENDP
Notes:
• XLAT instruction does not normally contain an operand. Here we are using the operand
(TABLE). It is a dummy operand! It is being used here only to specify segment override.
XLAT uses DS by default. Here the table is in CS. So segment override is being specified.
• More examples are discussed in the Text Book.


2.7 OUTCOMES:
1. Complete knowledge of instruction set and addressing modes of 8086

2. Can work with coding of programs
1. Differentiate between the instructions AAA and DAA with examples.

2. Differentiate between the instructions ROR and RCR with examples.
1. Advanced Microprocessors and Peripherals - A.K. Ray and K.M. Bhurchandi, TMH, 3rd Edition,
2012, ISBN 978-1-25-900613-5.
DEPT. of ECE, ATMECE, MYSURU Page 82

MODULE 3: STACKS AND INTERRUPTS
Structure
3.0 Introduction to stack, Stack structure of 8086, Programming for Stack

3.1 Objectives
3.2 Interrupts and Interrupt Service routines
3.3 Interrupt cycle of 8086, NMI, INTR, Interrupt programming
3.4 Passing parameters to procedures, Macros, Timing and Delays
3.5 Outcomes
3.6 Questions/ answers
3.7 Further reading
MODULE 3.0 : Introduction to stack, Stack structure of 8086
The Stack, Stack Segment Register, and Stack Pointer The Stack During interrupt and subroutine
operations, the contents of specific internal registers of the 8086 may be overwritten. If these registers
contain data that are needed after the return, they should be PUSHed to a section of memory known as
the Stack. Here they may be maintained temporarily. At the completion of the service routine or
subroutine, these values are POPped off the stack in the reverse order of the PUSH, and the register
contents are restored with their original data. When an interrupt occurs, the 80x86 automatically PUSHes
the current flags, the value in CS, and the value in IP onto the stack. As part of the service routine for the
interrupt, the contents of other registers may be pushed onto the stack by executing PUSH instructions.
An example is the instruction PUSH SI. It causes the contents of the Source Index register to be PUSHed
onto the stack. At the end of the service routine, POP instructions can be included to restore the values
from the stack back into their corresponding internal registers. For example, POP SI causes the value at
the top of the stack to be popped back into the source index register. As indicated earlier, stack is
implemented in the memory of the 8086. It is a maximum of 64K bytes long and is organized as 32K

words. The lowest addressed byte in the current stack is pointed to by the contents of the stack segment
(SS) register. Any number of stacks may exist in an 8086. A new stack can be brought in by simply
changing the value in the SS register through software. For instance, executing the instruction MOV
SS,DX loads a new value from DX into SS. Even though many stacks can exist, only one can be active at
a time. Another register, the stack pointer (SP) contains an offset of the current top of the stack from the
value in SS. The address obtained from the contents of SS and SP is the physical address of the last
storage location in the stack to which data were PUSHed. This is known as the top of the stack. The value
in the stack pointer starts at 0FFFFh upon initialization of the 8086. Combining this value with the
current value in SS gives the highest addressed location in the stack: that is, the bottom of the stack.
Since data transfers to and from stack are always 16-bit words, it is important to configure the system
such that all stack locations are at even word boundaries. This minimizes the number of memory cycles
required to PUSH or POP data for the stack and minimizes the amount of time required to perform a
switch in program context. The 8086 PUSHes data and addresses to the stack one word at a time. Each
time a register value is to be PUSHed onto the top of the stack, the value in the stack pointer is first
decremented by 2 and then the contents of the register are written into memory. In this way, we see that
the stack grows down in memory from the bottom of the stack, which corresponds to the physical address
derived from SS and 0FFFFh toward the end of the stack, which corresponds to the physical address
obtained from SS and offset 000016. When a value is popped from the top of the stack, the reverse of this
sequence occurs. The physical address defined by SS and SP always points to the location of the last
value pushed onto the stack. Its contents are first popped off the stack and put into the specified register
within the 8086; then SP is incremented by 2. The top of the stack now corresponds to the previous value
pushed onto the stack. A few things that we must remember are: • We must make sure to create a Stack,
and make it large enough for any program that has a CALL or any program that will use the PUSH and
POP instructions.
The Stack, Stack Segment Register, and Stack Pointer

• PUSH all registers that contain data or addresses that we need after the RETurn
• When RETurn we must POP the registers in the reverse order of the PUSH
• We must POP each register that we PUSH
• If we PUSH before the CALL, we must after the RETurn (in the calling module or subroutine)
• If we PUSH after the CALL, we must POP before the RETurn (inside the subroutine)
PUSH Examples
PUSH AX – the contents of a 16-bit register
PUSH EBX - the contents of a 32-bit register
PUSHA (286 and higher) – Preserves all usable registers of 80286
PUSHAD (386 and higher) – Preserves all usable registers of 80386
There are corresponding POP instructions for each of the above examples. Execution of a PUSH
instruction causes the data corresponding to the operand to be pushed onto the top of the stack.
For instance, if the instruction is PUSH AX its execution results in the following:
SP <- SP - 1 ;SP is decremented
SS:SP <= AH ;AH is PUSHed on the Stack
SP <- SP - 1 ;SP is decremented
SS:SP <= AL ;AL is PUSHed on the Stack
This shows that the two bytes of AX are saved in the stack part of memory and the stack pointer is
decremented by 2 such that it points to the new top of the stack. On the other hand, if the instruction
is POP AX, its execution results in the following:
AL <- SS:SP ;AL is POPped from the Stack
SP <- SP + 1 ;SP is incremented
AH <= SS:SP ;AH is POPped from the Stack
SP <- SP + 1 ;SP is incremented
Let us assume we wish to write a program that CALLs a subroutine that will need all the general
purpose registers, and those registers contain data that we will need after the subroutine has
finished. We may preserve the contents of the registers using the PUSH instruction either by:
PUSHing before the CALL and POPping after the RETurn or
PUSHing after the CALL and POPping before the RETurn
Regardless of which method we use, we must POP in the reverse order of the PUSH. Consider the
following.
PUSH AX
PUSH BX
PUSH CX
PUSH DX
CALL SUB1
POP DX
POP CX
POP BX
POP AX
MODULE 3.1 : Objectives
1. To learn how interrupt service routines work in 8086 and also how to create time delays
MODULE 3.2 : Interrupts and Interrupt Service routines
Introduction
An interrupt is the method of processing the microprocessor by peripheral device. An interrupt is used to
cause a temporary halt in the execution of program. Microprocessor responds to the interrupt with an
interrupt service routine, which is short program or subroutine that instructs the microprocessor on how
to handle the interrupt. There are two basic type of interrupt, maskable and non-maskable, nonmaskable
interrupt requires an immediate response by microprocessor, it usually used for serious circumstances
like power failure. A maskable interrupt is an interrupt that the microprocessor can ignore depending
upon some predetermined upon some predetermined condition defined by status register. Interrupt can
divide to five groupe: 1. hardware interrupt 2. Non-maskable interrupt 3. Software interrupt 4. Internal
interrupt 5. Reset Hardware,software and internal interrupt are service on priority basis. each interrupt is
given a different priority level by assign it a type number. Type 0 identifies the highest-priority and type
255 identifies the lowest- priority interrupt. The 80x86 chips allow up to 256 vectored interrupts. This
means that you can have up to 256 different sources for an interrupt and the 80x86 will directly call the
service routine for that interrupt without any software processing. This is in contrast to nonvectored
interrupts that transfer control directly to a single interrupt service routine, regardless of the interrupt
source. The 80x86 provides a 256 entry interrupt vector table beginning at address 0:0 in memory. This is
a 1K table containing 256 4-byte entries. Each entry in this table contains a segmented address that points
at the interrupt service routine in memory. The lowest five types are dedicated to specific interrupts such
as the divide by zero interrupt and the non maskable interrupt. The next 27 interrupt types, from 5 to 31

are High priority 3 reserved by Intel for use in future microprocessors. The upper 224 interrupt types,
from32 to 255, are available to use for hardware and software interrupts.
When an interrupt occurs, regardless of source, the
80x86 does the following:
1. The CPU pushes the flags register onto the stack.
2. The CPU pushes a far return address (segment:offset) onto the stack, segment value first.
3. The CPU determines the cause of the interrupt (i.e., the interrupt number) and fetches the four byte
interrupt vector from address 0:vector*4.
4. The CPU transfers control to the routine specified by the interrupt vector table entry.
When the interrupt service routine wants to return control, it must execute an IRET (interrupt return)
instruction. The interrupt return pops the far return address and the flags off the stack. Note that
executing a far return is insufficient since that would leave the flags on the stack. 2. hardware interrupt
The primary sources of interrupts, however, are the PCs timer chip, keyboard, serial ports, parallel ports,
disk drives, CMOS real-time clock, mouse, sound cards, and other peripheral devices. These devices
connect to an Intel 8259A programmable interrupt controller (PIC) that prioritizes the interrupts and
interfaces with the 80x86 CPU. The 8259A chip adds considerable complexity to the software that
processes interrupts.
Programmable interrupt controller

The 8259A programmable interrupt controller chip accepts interrupts from up to eight different devices,
which shown in figure (2), If any one of the devices requests service, the 8259 will toggle an interrupt
output line (connected to the CPU) and pass a programmable interrupt vector to the CPU. You can
cascade ( show in figure(3))the device to support up to 64 devices by connecting nine 8259s together:
eight of the devices with eight inputs each whose outputs become the eight inputs of the ninth device. A
typical PC uses two of these devices to provide 15 interrupt inputs (seven on the master PIC with the
eight input coming from the slave PIC to process its eight inputs)7. The sections following this one will
describe the devices connected to each of those inputs, for now we will concentrate on what the 8259
does with those inputs. Nevertheless, for the sake of discussion, the following table lists the interrupt
sources on the PC.

NON-MASKABLE INTERRUPT (NMI)

The processor provides a single non-maskable interrupt pin (NMI) which has higher priority than the
maskable interrupt request pin (INTR). A typical use would be to activate a power failure routine. The
NMI is edgetriggered on a LOW-to-HIGH transition. The activation of this pin causes a type 2 interrupt.
NMI is required to have a duration in the HIGH state of greater than two CLK cycles, but is not required
to be synchronized to the clock. Any high-going transition of NMI is latched on-chip and will be serviced
at the end of the current instruction or between whole moves of a block-type instruction. Worst case
response to NMI would be for multiply, divide, and variable shift instructions. There is no specification
on the occurrence of the low-going edge; it may occur before, during, or after the servicing of NMI.
Another high-going edge triggers another response if it occurs after the start of the NMI procedure. The
signal must be free of logical spikes in general and be free of bounces on the low-going edge to avoid
triggering extraneous responses.
MASKABLE INTERRUPT
Whenever an external signal activates the INTR pin, the microprocessor will be interrupted only if
interrupts are enabled using set interrupt Flag instruction. If the interrupts are disabled using clear
interrupt Flag instruction, the microprocessor will not get interrupted even if INTR is activated. That is,
INTR can be masked. INTR is a non vectored interrupt, which means, the 8086 does not know where to
branch to service the interrupt. The 8086 has to be told by an external device like a Programmable
Interrupt controller regarding the branch. Whenever the INTR pin is activated by an I/O port, if Interrupts
are enabled and NMI is not active at that time, the microprocessor finishes the current instruction that is
being executed and gives out a „0‟ on INTA pin twice. When INTA pin goes low for the first time, it asks
the external device to get ready. In response to the second
INTA the microprocessor receives the 8 bit, say N, from a programmable Interrupt controller. The action
taken is as follows.
1. Complete the current instruction.
2. Activates INTA output, and receives type Number, say N
3. Flag register value, CS value of the return address & IP value of the return address are pushed on to the
stack.
4. IP value is loaded from contents of word location N x 4.
5. CS is loaded from contents of the next word location.
6. Interrupt Flag and trap Flag are reset to 0.

At the end of the ISS, there will be an IRET instruction. This performs popping off from the stack top to
IP, CS and Flag registers. Finally, the register values which are also saved on the stack at the start of ISS,
are restored from the stack and a return to the interrupted program takes place using the IRET instruction.
Software interrupt Instructions

There are instructions in 8086 which cause an interrupt. They are
 INT instructions with type number specified.
 INT 3, Break Point Interrupt instruction.
 INTO, Interrupt on overflow instruction.
These are instructions at the desired places in a program. When one of these instructions is executed a
branch to an ISS takes place. Because their execution results in a branch to an ISS, they are called
interrupts. Software Interrupt instructions can be used to test the working of the various Interrupt
handlers- For example, we can execute INTO instruction to execute type 0 ISS, without really having to
divide a number by 0. Similarly, we can execute INT 2 instruction to test NMI ISS.
INT-Interrupt Instruction with Type number Specified

The mnemonic for this is INT. It is a 2 byte instruction. The first byte provides the op-code and the
second byte the Interrupt type number. Op-code for this instruction is CDH
The execution of an INT instruction, say INTN, when N is the value in the range 00H to FFH, results in
the following:
1. Flag register value is pushed on to the stack.
2. CS value of the Return address and IP value of the Return address are push edon to the stack.
3. IP is loaded from the contents of the word location N x 4.
4. CS is loaded from the contents of the next word location.
5. Interrupt Flag and Trap Flag are reset to 0.
Thus a branch to the ISS take place. During the ISS, interrupt are disabled because the Interrupt flag is
reset to 0.At the end of the ISS, there will be an IRET instruction. Thus a return back to the interrupted
program takes place with Flag registers unchanged.
4.2. INT 3-Break Point Interrupt Instruction
When a break point is inserted, the system executes the instructions up to the breakpoint, and then goes to
the break point procedure. Unlike the single-Step feature which stops execution after each instruction, the
breakpoint feature executes all the instructions up to the inserted breakpoint and then stops execution.
The mnemonic for the instruction is INT3. It is a 1 byte instruction Op-code for this is CCH.

The execution of INT3 instruction results in the following.

1. Flag register value is pushed on to the Stack.
2. CS value of the return address and IP value of the return address are pushed onto the Stack.
3. IP is loaded from the contents of the word location 3x4 = 0000CH.
4. CS is loaded from the contents of the next word location.
5. Interrupt Flag and Trap Flag are reset to 0.
Thus a branch to the ISS takes place. During the ISS, interrupts are disabled because Interrupt flag is
reset to 0. At the end of the ISS, there will be an IRET instruction to return back to the interrupted
program. A break point interrupt service procedure usually saves all the register contents on the Stack.
Depending upon the system, it may then send the register contents to the CRTdisplay and wait for the
next command from the user.
4.3. INTO - Interrupt on overflow instruction
The 8086 overflow flag, OF, will be set if the signed result of an arithmetic operation on two signed
numbers is too large to be represented in the destination register or memory location. For example, if we
add the 8-bit signed number 01101100 and the 8- bit signed number 01010001, the signed result will be
10111101. This is correct if we add unsigned binary numbers, but it is not the correct signed result. There
are two ways to detect and respond to an overflow error in a program. One way is to put the jump if
overflow instruction, JO, immediately after the arithmetic instruction. If the overflow flag is Set,
execution will jump to the address specified in the JO instruction. At this address an error routine may be
put which respond to the overflow. The second way is to put them INTO instruction immediately after
the arithmetic Instruction in the program. The mnemonic for the instruction is INTO. It is a 1 byte
instruction. The op-code for this is CEH. It is a conditional interrupt instruction. Only if the overflow flag
is Set, a branch takes place to an interrupt handler whose interrupt type number is 4. If the overflow flag
is reset, the execution continues with the next instruction. The execution of INTO results in the
following.
1. Flag register values are pushed on to the Stack.
2. CS value of the return address and IP value of the return address and IP value of the return address are
pushed on to the stack.
3. IP is loaded from the contents of word location 4x4 = 00010H.
4. CS is loaded from the contents of next word location.
5. Interrupt flag and Trap flag are reset to 0.
Thus a branch to ISS takes place. During the ISS, interrupts are disabled. At the end of ISS, there will be
an IRET instruction, returning back to the interrupted program. Instructions in the ISS procedure perform
the desired response to the error condition.
MODULE 3.3 : Interrupt cycle of 8086, NMI, INTR, Interrupt programming
8086 INTERRUPTS: 8086 Interrupts and interrupt responses, Hardware interrupt applications, Software
interrupt applications, Interrupt examples
An interrupt is the method of accessing the MPU by a peripheral device. An interrupt is used to
cause a temporary halt in the execution of a program. The MPU responds to the interrupt with an
interrupt service routine, which is a short program or subroutine that instructs the MPU on how to handle
the interrupt. When the 8086 is executing a program, it can get interrupted because of one of the
following.
1. Due to an interrupt getting activated. This is called as hardware interrupt.

2. Due to an exceptional happening during an instruction execution, such as division of a number
by zero. This is generally termed as exceptions or Traps.
3.Due to the execution of an Interrupt instruction like "INT 21H". This is called a Software
interrupt. The action taken by the 8086 is similar for all the three cases, except for minor differences.
There are two basic types of interrupts, Maskable and non-maskable.
Nonmaskable interrupt requires an immediate response by the MPU. It is usually used for serious
circumstances like power failure. A maskable interrupt is an interrupt that the MPU can ignore depending
upon some predetermined condition defined by the status register. Interrupts are also prioritized to allow
for the case when more than one interrupt needs to be serviced at the same time.
Hardware interrupts of 8086

In a microcomputer system whenever an I/O port wants to communicate with themicroprocessor

urgently, it interrupts the microprocessor. In such a case, themicroprocessor completes the instruction it is
presently executing. Then, it saves theaddress of the next instruction on the stack top. Then it branches to
an Interrupt Service Subroutine (ISS), to service the interrupting I/O port. An ISS is also commonly
called as an Interrupt Handler . After completing the ISS, the processor returns to the original program,
making use of the return address that was saved on the stack top.In 8086 there are two interrupt pins.
They are NMI and INTR. NMI stands for non maskable interrupt. Whenever an external device activates
this pin, themicroprocessor will be interrupted. This signal cannot be masked. NMI is a vectored
Definition: The meaning of „interrupts‟ is to break the sequence of operation. While the CPU is
executing a program, on „interrupt‟ breaks the normal sequence of execution of
instructions, diverts its execution to some other program called Interrupt Service Routine (ISR).After
executing ISR , the control is transferred back again to the main program.I nterrupt processing is an
alternative to polling.
Need for Interrupt: Interrupts are particularly useful when interfacing I/O devices, that provide or require
data at relatively low data transfer rate.
Types of Interrupts: There are two types of Interrupts in 8086. They are: (i) Hardware Interrupts and
(ii)Software Interrupts
(i) Hardware Interrupts (External Interrupts). The Intel microprocessors support hardware interrupts
through:
Two pins that allow interrupt requests, INTR and NMI
One pin that acknowledges, INTA, the interrupt requested on INTR. INTR and NMI
INTR is a maskable hardware interrupt. The interrupt can be enabled / disabled

using STI/CLI instructions or using more complicated method of updating the
FLAGS register with the help of the POPF instruction.
When an interrupt occurs, the processor stores FLAGS register into stack, disables further interrupts,
fetches from the bus one byte representing interrupt type, and jumps to interrupt processing routine
address of which is stored in location 4 * <interrupt type>. Interrupt processing routine should return
with the IRET instruction.
NMI is a non-maskable interrupt. Interrupt is processed in the same way as the
INTR interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is stored in
location 0008h. This interrupt has higher priority than the maskable interrupt.
– Ex: NMI, INTR.
(ii) Software Interrupts (Internal Interrupts and Instructions) .Software interrupts can be caused by:
INT instruction - breakpoint interrupt. This is a type 3 interrupt.
INT <interrupt number> instruction - any one interrupt from available 256 interrupts.
INTO instruction - interrupt on overflow
Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt.
When the CPU processes this interrupt it clears TF flag before calling the
interrupt processing routine.
Processor exceptions: Divide Error (Type 0), Unused Opcode (type 6) and Escape opcode (type 7).
Software interrupt processing is the same as for the hardware interrupts. - Ex: INT n (Software
Instructions)
Control is provided through:

 IF and TF flag bits
 IRET and IRETD

3.4 Passing parameters to procedures, Macros, Timing and Delays
Writing and using procedures

• Avoid writing the same sequence of instruction again and again.
• Write it in a separate subprogram and call that subprogram whenever
necessary.
• For that CALL instruction is used.
•Stores the address of the next instruction to be executed after the CALL instruction to stack. This address is
called as the return address.

•RET at the end of the procedure, it copies this value from stack back to the instruction pointer (IP).
FIG. Chart for CALL and RET instruction




COUNTER AND TIME DELAYS

A counter is designed simply by loading appropriate number into one of the registers and using INR or
DNR instructions.
• Loop is established to update the count.
• Each count is checked to determine whether it has reached final number ;if not, the loop is repeated.
TIME DELAY
 Procedure used to design a specific delay.
 A register is loaded with a number , depending on time delay required and then the register is
decremented until it reaches zero by setting up a loop with conditional jump instruction.
3.5 OUTCOMES:
1. Can work with interrupt service routines and code the different interrupts in 8086 and also create
time delays
1. Explain the operation of the following DOS function using INT 21H interrupt.
2. Write a program that clears the screen (monitoring using MACRO HOME.
3. Describe the working of 8086 in minimum mode configuration with 8284 clock
generator
4. Explain the function of type 0 to type 4 interrupts of 8086 with interrupt vector table.
1. Microcomputer systems-The 8086 / 8088 Family – Y.C. Liu and G. A. Gibson, 2E PHI - 2003
2. The Intel Microprocessor, Architecture, Programming and Interfacing-Barry B. Brey, 6e,
Pearson Education / PHI, 2003

MODULE 4 (PART 1): 8086 Bus Configuration and Timings
Structure
4.0 Introduction
4.1 Objectives
4.2 Physical memory Organization, General Bus operation cycle
4.3 I/O addressing capability, Special processor activities
4.4 Minimum mode, Maximum Mode 8086 system and Timing diagrams
4.5 Outcomes
4.6 Questions/ answer
4.7 Further reading
MODULE 4.0: Introduction
There are two available modes of operation for the 8086/8088 microprocessors: minimum mode and
maximum mode. Minimum mode operation is obtained by connecting the mode selection pin to +5.0 V,
and maximum mode is selected by grounding this pin. Both modes enable different control structures for
the 8086/8088 microprocessors. The mode of operation provided by minimum mode is similar to that of
the 8085A, the most recent Intel 8-bit microprocessor. The maximum mode is unique and designed to be
used whenever a coprocessor exists in a system.
MODULE 4.1: Objectives
1. Study about minimum and maximum mode and bus interface.
MODULE 4.2: Physical memory Organization, General Bus operation cycle
8086 Memory Addressing

The 8086 memory address space can be viewed as a sequence of one million bytes in which any byte
may contain an 8-bit data element and any two consecutive bytes may contain a 16-bit data element.

There is no constraint on byte or word address boundaries. The address space is physically connected to
a 16-bit data bus by dividing the address space into two 8-bit banks of up to 512K bytes each.
One bank is connected to the lower half of the 16-bit data bus (D0 – D7) and contains even address
bytes. i.e., when A0 bit is low, the bank is selected. The other bank is connected to the upper half of the
data bus (D8 - D15) and contains odd address bytes. i.e., when A0 is high and BHE (Bus High Enable) is
low, the odd bank is selected. A specific byte within each bank is selected by address lines A1-A19.
Data can be accessed from the memory in four different ways. They are:
 8 - bit data from Lower (Even) address Bank.
 8 - bit data from Higher (Odd) address Bank.
 16 - bit data starting from Even Address.
 16 - bit data starting from Odd Address.
8-bit data from Even address Bank
To access memory bytes from Even address, information is transferred over the lower half of the data bus
(D0 - D7). The A0 is output LOW and BHE is output HIGH enabling only the even address bank. It is
illustrated in figure above.
Example: Consider loading a byte of data into CH register (higher order 8-bits of CX register) from the
memory location with an even address. The data will be accessed from the even bank via the (D0 - D7)
DATA BUS. Although this data is transferred into the 8086 over the lower 8-bit lines, the 8086
automatically redirects the data to the higher 8-bits of its internal 16bit data path and hence to the CH-
register. This capability allows bytes input - output transfer via the AL register to access I/O device
connected to either the upper half of the data bus or the lower half of the 16-bit data bus.
8-bit Data from Odd Address Bank
To access memory byte from an odd address information, is transferred over the higher half of the data
bus (D8 - D15). The BHE output low enables the upper memory bank. A0 is output high to disable the
lower memory bank
16-bit Data Access starting from Even - Address
16-bit data from an even address is accessed in a single bus cycle. Address lines A1 A19 select the
appropriate byte within each bank. A0 low and BHE low, enables both banks simultaneously.
16-bit Data Access starting from Odd Address
A 16-bits word located at an odd address (two consecutive bytes with the least significant byte at an odd
byte address) is accessed using two bus cycles. During the first bus cycle the lower byte (with the odd
address 0005.

During the second bus cycle, the upper byte (with the even address 0006H is accessed. During the first
bus cycle, A1 - A19 address bus specifies the address and A0 as 1 and BHE is low. Therefore the even
memory bank is disabled and odd memory bank is enabled.
During the second bus cycle, the address is incremented. Therefore A0 is zero and BHE is made high.
The even memory bank is enabled and the odd memory bank is disabled.
GENERAL BUS OPERATION
The 8086 has a combined address and data bus commonly referred to as a time multiplexed address and
data bus. The main reason behind multiplexing address and data over the same pins is the maximum
utilization of processor pins and it facilitates the use of 40 pin standard DIP package. The bus can be
demultiplexed using a few latches and transreceivers, whenever required. Basically, all the processor bus
cycles consist of at least four clock cycles. These are referred to as T1, T2, T3 and T4. The address is
transmitted by the processor during T1. It is present on the bus only for one cycle. During T2, i.e. the
next cycle, the bus is tristated foranging the direction of bus for the following data read cycle. The data
transfer takes place during T3 and T4.In case, an addressed device is slow and shows 'NOT READY'
status the wait states Tw are inserted between T3 and T4. These clock states during wait period are
called idle states (T),wait states (Tw) or inactive states. The processor uses these cycles for internal
housekeeping. The address latch enable (ALE) signal is emitted during T1 by the processor (minimum
mode) or the bus controller (maximum mode) depending upon the status of the MN MX input. The
negative edge of this ALE pulse is used to separate the address and the data or In maximum mode, the
status lines S0, Sl and S2 are used to indicate the type of operation.Status bits S3 to S7 are multiplexed
with higher order address bits and the BHE signal. Address is valid during T1 while the status bits S3 to
S7 are valid during T2 through T4.

MODULE 4.2: I/O addressing capability, Special processor activities
The 8086/8088 processor can address up to 64K byte I/O registers or 32K word registers. The I/O address
appears on the address lines A0 to A15 for one clock cycle (T1). It may then be latched using the ALE
signal. The upper address lines (A16 - A19) are at logic 0 level during the I/O operations.
The 16-bitregister DX is used as 16-bit I/O address pointer, with full capability to address up to 64K
devices. In memory mapped I/O interfacing, the I/O device addresses are treated as memory locations in
page 0, i.e. segment address 0000H.Even addressed bytes are transferred on D7-Do and odd addressed bytes
are transferred on D8-D15 lines
MODULE 4.3: Minimum mode, Maximum mode of 8086 system and Timing
diagrams
MINIMUM AND MAXIMUM MODES

The microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to logic 1.

 In this mode, all the control signals are given out by the microprocessor chip itself. There is a
single microprocessor in the minimum mode system.
 The remaining components in the system are latches, transreceivers, clock generator, memory
and I/O devices.
 Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. They are used for
separating the valid address from the multiplexed address/data signals and are controlled by the
ALE signal generated by 8086.
 Transreceivers are the bidirectional buffers and some times they are called as data amplifiers.
They are required to separate the valid data from the time multiplexed address/data signals. They
are controlled by two signals namely, DEN and DT/R.
 The DEN signal indicates the direction of data, i.e. from or to the processor.
 The system contains memory for the monitor and users program storage. Usually, EPROM are
used for monitor storage, while RAM for users program storage. A system may contain I/O
devices.

 The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized in
two parts, the first is the timing diagram for read cycle and the second is the timing diagram for
write cycle.
 The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and also M /
IO signal. During the negative going edge of this signal, the valid address is latched on the local
bus.
 The BHE and A0 signals address low, high or both bytes. From T1 to T4 , the M/IO signal
indicates a memory or I/O operation.
 At T2, the address is removed from the local bus and is sent to the output. The bus is then
tristated. The read (RD) control signal is also activated in T2.
 The read (RD) signal causes the address device to enable its data bus drivers. After RD goes low,
the valid data is available on the data bus.
 The addressed device will drive the READY line high. When the processor returns the read
signal to high level, the addressed device will again tristate its bus drivers.
 A write cycle also begins with the assertion of ALE and the emission of the address.
 The M/IO signal is again asserted to indicate a memory or I/O operation. In T2, after sending the
address in T1, the processor sends the data to be written to the addressed location.
 The data remains on the bus until middle of T4 state. The WR becomes active at the beginning of
T2 (unlike RD is somewhat delayed in T2 to provide time for floating).
 The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O word to be
read or write.
 The M/IO, RD and WR signals indicate the type of data transfer as specified in table below.

Hold Response sequence:

 The HOLD pin is checked at leading edge of each clock pulse. If it is received active by the
processor before T4 of the previous cycle or during T1 state of the current cycle, the CPU
activates HLDA in the next clock cycle and for succeeding bus cycles, the bus will be given to
another requesting master.
 The control of the bus is not regained by the processor until the requesting master does not drop
the HOLD pin low.
 When the request is dropped by the requesting master, the HLDA is dropped by the processor at
the trailing edge of the next clock.

Maximum Mode 8086 System

 In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.
 In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus
controller derives the control signal using this status information.
 In the maximum mode, there may be more than one microprocessor in the system configuration.
The components in the system are same as in the minimum mode system.
 The basic function of the bus controller chip IC8288, is to derive control signals like RD and WR
(for memory and I/O devices), DEN, DT/R, ALE etc. using the information by the processor on
the status lines.
 The bus controller chip has input lines S2, S1, S0 and CLK.
 These inputs to 8288 are driven by CPU.
 It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC and AIOWC.
The AEN, IOB and CEN pins are especially useful for multiprocessor systems.
 AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The significance of the
MCE/PDEN output depends upon the status of the IOB pin.
 INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or to an
interrupting device.

 IORC, IOWC are I/O read command and I/O write command signals respectively . These signals
enable an IO interface to read or write the data from or to the address port.
 The MRDC, MWTC are memory read command and memory write command signals
respectively and may be used as memory read or write signals.
 All these command signals instructs the memory to accept or send data from or to the bus.
 Here the only difference between in timing diagram between minimum mode and maximum
mode is the status signals used and the available control and advanced command signals.
 R0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will output a pulse as on the
ALE and apply a required signal to its DT / R pin during T1.
 In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will activate MRDC or
IORC. These signals are activated until T4.
 For an output, the AMWC or AIOWC is activated from T2 to T4 and MWTC or IOWC is
activated from T3 to T4.
 The status bit S0 to S2 remains active until T3 and become passive during T3 and T4.
 If reader input is not activated before T3, wait state will be inserted between T3 and T4.

4.4 Outcomes:
Generic Skills / Outcomes:

 To know how these bus interfacing can be done.
 How the different hardware can be interfaced with the microprocessors.
4.5 Questions / Answers

1. Explain minimum mode configuration of 8086 processor.

2. Explain maximum mode configuration of 8086 processor.
3. Explain the significance of following pins
____ ____ _ ____
(i)HOLD & HOLDA (II)BHE/S7 (iii) DEN, DT/R (iv) TEST.
5.Explain the significance of following pins
__ ___ ____ __ ___
(i) RQ/GT0 (ii) LOCK (iii) QSO-QS1 (iv) S2 –S0
1. Advanced Microprocessors and Peripherals - A.K. Ray and K.M. Bhurchandi, TMH, 3rd Edition, 2012,
ISBN 978-1-25-900613-5.

MODULE 4 (PART 2): Basic Peripherals and their Interfacing with 8086
(PART 1)
Structure
4.0 Introduction
4.1 Objectives
4.2 Static RAM Interfacing with 8086
4.3 Interfacing I/O ports, PIO 8255
4.4 Modes of operation – Mode-0 and BSR Mode
4.5 Interfacing Keyboard and 7-Segment digits using 8255
4.6 Outcomes
4.7 Questions/answer
4.8 Further reading
4.0 Introduction
Intel‟s 8279 is a general purpose Keyboard Display controller that simultaneously drives the display of a
system and interfaces a Keyboard with the CPU. The Keyboard Display interface scans the Keyboard to
identify if any key has been pressed and sends the code of the pressed key to the CPU. It also transmits the
data received from the CPU, to the display device. Both of these functions are performed by the controller
in repetitive fashion without involving the CPU. The Keyboard is interfaced either in the interrupt or the
polled mode.
4.1 Objectives
 Study of interfacing of processor with different types hardware components such as

keyboard and alphanumeric displays.
 Understanding Keyboard and Video Display, Data Conversions.

4.2 Static RAM Interfacing with 8086
Static RAM Interfacing

 The semiconductor RAM are broadly two types – static RAM and dynamic RAM.
 The semiconductor memories are organised as two dimensional arrays of memory locations.
 For example 4K * 8 or 4K byte memory contains 4096 locations, where each locations contains 8-
bit data and only one of the 4096 locations can be selected at a time. Once a location is selected
all the bits in it are accessible using a group of conductors called Data bus.
 For addressing the 4K bytes of memory, 12 address lines are required.
 In general to address a memory location out of N memory locations, we will require at least n bits
of address, i.e. n address lines where n = Log2 N.
 Thus if the microprocessor has n address lines, then it is able to address at the most N locations of
memory, where 2n=N. If out of N locations only P memory locations are to be interfaced, then the
least significant p address lines out of the available n lines can be directly connected from the
microprocessor to the memory chip while the remaining (n-p) higher order address lines may be
used for address decoding as inputs to the chip selection logic.
 The memory address depends upon the hardware circuit used for decoding the chip select (CS).
The output of the decoding circuit is connected with the CS pin of the memory chip.
 The general procedure of static memory interfacing with 8086 is briefly described as follows:
1. Arrange the available memory chip so as to obtain 16-bit data bus width. The upper 8-bit bank
is called as odd address memory bank and the lower 8-bit bank is called as even address
memory bank
2. Connect available memory address lines of memory chip with those of the microprocessor and
also connect the memory RD and WR inputs to the corresponding processor control signals.
Connect the 16-bit data bus of the memory bank with that of the microprocessor 8086.
3. The remaining address lines of the microprocessor, BHE and A0 are used for decoding the
required chip select signals for the odd and even memory banks. The CS of memory is derived
from the o/p of the decoding circuit.

As a good and efficient interfacing practice, the address map of the system should be continuous as far as
possible, i.e. there should not be no windows in the map and no fold back space should be allowed.
A memory location should have a single address corresponding to it, i.e. absolute decoding should be
preferred and minimum hardware should be used for decoding.
4.3 Interfacing I/O ports, PIO 8255

PIO 8255
 The parallel input-output port chip 8255 is also called as programmable peripheral input-output port.
The Intel‟s 8255 is designed for use with Intel‟s 8-bit, 16-bit and higher capability microprocessors.
It has 24 input/output lines which may be individually programmed in two groups of twelve lines
each, or three groups of eight lines.
 The two groups of I/O pins are named as Group A and Group B. Each of these two groups contains a
subgroup of eight I/O lines called as 8-bit port and another subgroup of four lines or a 4-bit port.
Thus Group A contains an 8-bit port A along with a 4-bit port. C upper.
 The port A lines are identified by symbols PA0-PA7 while the port C lines are identified as PC4-
PC7. Similarly, Group B contains an 8-bit port B, containing lines PB0-PB7 and a 4-bit port C with
lower bits PC0- PC3. The port C upper and port C lower can be used in combination as an 8-bit port
C.
 Both the port C are assigned the same address. Thus one may have either three 8-bit I/O ports or two
8-bit and two 4-bit ports from 8255. All of these ports can function independently either as input or

as output ports. This can be achieved by programming the bits of an internal register of 8255 called
as control word register (CWR).
 The internal block diagram and the pin configuration of 8255 are shown in fig.
 The 8-bit data bus buffer is controlled by the read/write control logic. The read/write control logic
manages all of the internal and external transfers of both data and control words.
 RD, WR, A1, A0 and RESET are the inputs provided by the microprocessor to the READ/ WRITE
control logic of 8255. The 8-bit, 3-state bidirectional buffer is used to interface the 8255 internal data
bus with the external system data bus.
 This buffer receives or transmits data upon the execution of input or output instructions by the
microprocessor. The control words or status information is also transferred through the buffer.
 The signal description of 8255 are briefly presented as follows :
o PA7-PA0: These are eight port A lines that acts as either latched output or buffered input
lines depending upon the control word loaded into the control word register.
o PC7-PC4 : Upper nibble of port C lines. They may act as either output latches or input
buffers lines. This port also can be used for generation of handshake lines in mode 1 or mode
2.
o PC3-PC0 : These are the lower port C lines, other details are the same as PC7-PC4 lines.
o PB0-PB7 : These are the eight port B lines which are used as latched output lines or buffered
input lines in the same way as port A.
o RD : This is the input line driven by the microprocessor and should be low to indicate read
operation to 8255.
o WR : This is an input line driven by the microprocessor. A low on this line indicates write
operation.
o CS : This is a chip select line. If this line goes low, it enables the 8255 to respond to RD and
WR signals, otherwise RD and WR signal are neglected.
o A1-A0 : These are the address input lines and are driven by the microprocessor. These lines
A1-A0 with RD, WR and CS from the following operations for 8255. These address lines are
used for addressing any one of the four registers, i.e. three ports and a control word register
as given in table below.
 In case of 8086 systems, if the 8255 is to be interfaced with lower order data bus, the A0 and A1 pins
of 8255 are connected with A1 and A2 respectively.
 D0-D7 : These are the data bus lines those carry data or control word to/from the microprocessor.
 RESET : A logic high on this line clears the control word register of 8255. All ports are set as input
ports by default after reset.
Block Diagram of 8255 (Architecture)

• It has a 40 pins of 4 groups.
1. Data bus buffer
2. Read Write control logic
3. Group A and Group B controls
4. Port A, B and C
• Data bus buffer: This is a tristate bidirectional buffer used to interface the 8255 to system databus. Data is
transmitted or received by the buffer on execution of input or output instruction by the CPU.
• Control word and status information are also transferred through this unit.
Read/Write control logic: This unit accepts control signals ( RD, WR ) and also inputs from address bus and
issues commands to individual group of control blocks ( Group A, Group B).
• It has the following pins.
a) CS – Chipselect : A low on this PIN enables the communication between CPU and 8255.

b) RD (Read) – A low on this pin enables the CPU to read the data in the ports or the status word through
data bus buffer.
WR ( Write ) : A low on this pin, the CPU can write data on to the ports or on to the control register through
the data bus buffer.
d) RESET: A high on this pin clears the control register and all ports are set to the input mode
e) A0 and A1 ( Address pins ): These pins in conjunction with RD and WR pins control the selection of one
of the 3 ports.
• Group A and Group B controls : These block receive control from the CPU and issues commands to their
respective ports.
Group A - PA and PCU ( PC7 –PC4)
• Group B - PCL ( PC3 – PC0)
• Control word register can only be written into no read operation of the CW register is allowed.
• a) Port A: This has an 8 bit latched/buffered O/P and 8 bit input latch. It can be programmed in 3 modes –
mode 0, mode 1, mode 2.
b) Port B: This has an 8 bit latched / buffered O/P and 8 bit input latch. It can be programmed in mode 0,
mode1.
c) Port C : This has an 8 bit latched input buffer and 8 bit out put latched/buffer. This port can be divided
into two 4 bit ports and can be used as control signals for port A and port B. it can be programmed in mode
0.
4.4 Modes of operation – Mode-0 and BSR Mode
Modes of Operation of 8255

• These are two basic modes of operation of 8255. I/O mode and Bit Set-Reset mode (BSR).
• In I/O mode, the 8255 ports work as programmable I/O ports, while in BSR mode only port C (PC0-PC7)
can be used to set or reset its individual port bits.
• Under the I/O mode of operation, further there are three modes of operation of 8255, so as to support
different types of applications, mode 0, mode 1 and mode 2.
• BSR Mode: In this mode any of the 8-bits of port C can be set or reset depending on D0 of the control word.
The bit to be set or reset is selected by bit select flags D3, D2 and D1 of the CWR as given in table.
• I/O Modes :

a) Mode 0 ( Basic I/O mode ): This mode is also called as basic input/output mode. This mode provides
simple input and output capabilities using each of the three ports. Data can be simply read from and
written to the input and output ports respectively, after appropriate initialisation.
• The salient features of this mode are as listed below:

1. Two 8-bit ports ( port A and port B )and two 4-bit ports (port C upper and lower ) are available. The
two 4-bit ports can be combinedly used as a third 8-bit port.
2. Any port can be used as an input or output port.
3. Output ports are latched. Input ports are not latched.
4. A maximum of four ports are available so that overall 16 I/O configuration are possible.
• All these modes can be selected by programming a register internal to 8255 known as CWR.

• The control word register has two formats. The first format is valid for I/O modes of operation, i.e.
modes 0, mode 1 and mode 2 while the second format is valid for bit set/reset (BSR) mode of operation.
These formats are shown in following fig.


b) Mode 1: (Strobed input/output mode ) In this mode the handshaking control the input and output
action of the specified port. Port C lines PC0-PC2, provide strobe or handshake lines for port B.
This group which includes port B and PC0-PC2 is called as group B for Strobed data input/output.
Port C lines PC3-PC5 provide strobe lines for port A. This group including port A and PC3-PC5
from group A. Thus port C is utilized for generating handshake signals. The salient features of
mode 1 are listed as follows:
1. Two groups – group A and group B are available for strobed data transfer.
2. Each group contains one 8-bit data I/O port and one 4-bit control/data port.
3. The 8-bit data port can be either used as input and output port. The inputs and outputs both are latched.
4. Out of 8-bit port C, PC0-PC2 are used to generate control signals for port B and PC3-PC5 are used to
generate control signals for port A. the lines PC6, PC7 may be used as independent data lines.
• The control signals for both the groups in input and output modes are explained as follows:
Input control signal definitions (mode 1):
• STB(Strobe input) – If this lines falls to logic low level, the data available at 8-bit input port is
loaded into input latches.

• IBF (Input buffer full) – If this signal rises to logic 1, it indicates that data has been loaded into
latches, i.e. it works as an acknowledgement. IBF is set by a low on STB and is reset by the rising
edge of RD input.
• INTR (Interrupt request) – This active high output signal can be used to interrupt the CPU
whenever an input device requests the service. INTR is set by a high STB pin and a high at IBF
pin. INTE is an internal flag that can be controlled by the bit set/reset mode of either PC4
(INTEA) or PC2 (INTEB) as shown in fig.
• INTR is reset by a falling edge of RD input. Thus an external input device can be request the
service of the processor by putting the data on the bus and sending the strobe signal.
Output control signal definitions (mode 1):
• OBF (Output buffer full) – This status signal, whenever falls to low, indicates that CPU has
written data to the specified output port. The OBF flip-flop will be set by a rising edge of WR
signal and reset by a low going edge at the ACK input.
• ACK (Acknowledge input) – ACK signal acts as an acknowledgement to be given by an output
device. ACK signal, whenever low, informs the CPU that the data transferred by the CPU to the
output device through the port is received by the output device.
• INTR (Interrupt request) – Thus an output signal that can be used to interrupt the CPU when an
output device acknowledges the data received from the CPU. INTR is set when ACK, OBF and
INTE are 1. It is reset by a falling edge on WR input. The INTEA and INTEB flags are controlled
by the bit set-reset mode of PC6 and PC2 respectively.
• Mode 2 (Strobed bidirectional I/O ): This mode of operation of 8255 is also called as strobed
bidirectional I/O. This mode of operation provides 8255 with additional features for
communicating with a peripheral device on an 8-bit data bus. Handshaking signals are provided to
maintain proper data flow and synchronization between the data transmitter and receiver. The
interrupt generation and other functions are similar to mode 1.
• In this mode, 8255 is a bidirectional 8-bit port with handshake signals. The RD and WR signals
decide whether the 8255 is going to operate as an input port or output port.
• The Salient features of Mode 2 of 8255 are listed as follows:
1. The single 8-bit port in group A is available.
2. The 8-bit port is bidirectional and additionally a 5-bit control port is available.
3. Three I/O lines are available at port C. ( PC2 – PC0 )
4. Inputs and outputs are both latched.

5. The 5-bit control port C (PC3-PC7) is used for generating / accepting handshake signals for the
8-bit data transfer on port A.
• Control signal definitions in mode 2:
• INTR – (Interrupt request) As in mode 1, this control signal is active high and is used to
interrupt the microprocessor to ask for transfer of the next data byte to/ from it. This signal is used
for input (read) as well as output (write) operations.
• Control Signals for Output operations:
• OBF (Output buffer full) – This signal, when falls to low level, indicates that the CPU has
written data to port A.
• ACK (Acknowledge) This control input, when falls to logic low level, acknowledges that the
previous data byte is received by the destination and next byte may be sent by the processor. This
signal enables the internal tristate buffers to send the next data byte on port A.
• INTE1 (A flag associated with OBF) This can be controlled by bit set/reset mode with PC6.
• Control signals for input operations:
• STB (Strobe input) A low on this line is used to strobe in the data into the input latches
of 8255.
• IBF (Input buffer full) When the data is loaded into input buffer, this signal rises to logic
„1‟. This can be used as an acknowledge that the data has been received by the receiver.
• Note: WR must occur before ACK and STB must be activated before RD.
4.5 Interfacing Keyboard and 7-Segment digits using 8255
Interfacing a Microprocessor to Keyboard

• When you press a key on your computer, you are activating a switch. There are many different ways of
making these switches. An overview of the construction and operation of some of the most common types.
1. Mechanical key switches: In mechanical-switch keys, two pieces of metal are pushed together when you
press the key. The actual switch elements are often made of a phosphor-bronze alloy with gold platting on
the contact areas. The key switch usually contains a spring to return the key to the nonpressed position and
perhaps a small piece of foam to help damp out bouncing.

• Some mechanical key switches now consist of a molded silicon dome with a small piece of conductive
rubber foam short two trace on the printed-circuit board to produce the key pressed signal.
• Mechanical switches are relatively inexpensive but they have several disadvantages. First, they suffer from
contact bounce. A pressed key may make and break contact several times before it makes solid contact.
• Second, the contacts may become oxidized or dirty with age so they no longer make a dependable
connection.
• Higher-quality mechanical switches typically have a rated life time of about 1 million keystrokes. The
silicone dome type typically last 25 million keystrokes.
2. Membrane key switches: These switches are really a special type of mechanical switches. They consist
of a three-layer plastic or rubber sandwich.
• The top layer has a conductive line of silver ink running under each key position. The bottom layer has a
conductive line of silver ink running under each column of keys.
• When u press a key, you push the top ink line through the hole to contact the bottom ink line.
• The advantages of membrane keyboards is that they can be made as very thin, sealed units.
• They are often used on cash registers in fast food restaurants. The lifetime of membrane keyboards varies
over a wide range.
3. Capacitive key switches: A capacitive keyswitch has two small metal plates on the printed circuit board
and another metal plate on the bottom of a piece of foam.
• When u press the key, the movable plate is pushed closer to fixed plate. This changes the capacitance
between the fixed plates. Sense amplifier circuitry detects this change in capacitance and produce a logic
level signal that indicates a key has been pressed.
• The big advantages of a capacitive switch is that it has no mechanical contacts to become oxidized or dirty.
• A small disadvantage is the specified circuitry needed todetect the change in capacitance.
• Capacitive keyswitches typically have a rated lifetime of about 20 million keystrokes.
4. Hall effect keyswitches: This is another type of switch which has no mechanical contact. It takes
advantage of the deflection of a moving charge by a magnetic field.
• A reference current is passed through a semiconductor crystal between two opposing faces. When a key is

pressed, the crystal is moved through a magnetic field which has its flux lines perpendicular to the direction
of current flow in the crystal.
• Moving the crystal through the magnetic field causes a small voltage to be developed between two of the
other opposing faces of the crystal.
• This voltage is amplified and used to indicate that a key has been pressed. Hall effect sensors are also used
to detect motion in many electrically controlled machines.
• Hall effect keyboards are more expensive because of the more complex switch mechanism, but they are
very dependable and have typically rated lifetime of 100 million or more keystrokes.
• In most keyboards, the keyswitches are connecting in a matrix of rows and columns, as shown in fig.
• We will use simple mechanical switches for our examples, but the principle is same for other type of
switches.
• Getting meaningful data from a keyboard, it requires the following three major tasks:
1. Detect a keypress.
2. Debounce the keypress.
3. Encode the keypress
• Three tasks can be done with hardware, software, or a combination of two, depending on the application.
1. Software Keyboard Interfacing:

• Circuit connection and algorithm : The following fig (a) shows how a hexadecimal keypad can be
connected to a couple of microcomputer ports so the three interfacing tasks can be done as part of a
program.
• The rows of the matrix are connected to four output port lines. The column lines of matrix are
connected to four input-port lines. To make the program simpler, the rowlines are also connected to
four input lines.
• When no keys are pressed, the column lines are held high by the pull-up resistor connected to +5V.
Pressing a key connects a row to a column. If a low is output on a row and
a key in that row is pressed, then the low will appear on the column which contains that key and can
be detected on the input port.
• If you know the row and column of the pressed key, you then know which key was pressed, and
you can convert this information into any code you want to represent that
key.
• The following flow chart for a procedure to detect, debounce and produce the hex code for a
pressed key.
• An easy way to detect if any key in the matrix is pressed is to output 0‟s to all rows and then check
the column to see if a pressed key has connected a low to a column.
• In the algorithm we first output lows to all the rows and check the columns over and over until the
column are all high. This is done before the previous key has been released before looking for the
next one. In the standard keyboard terminology, this is called two-key lockout.

• Once the columns are found to be all high, the programenters another loop, which waits until a low
appears on one of the columns, indicating that a key has been pressed. This second loop does the
detect task for us. A simple 20- ms delay procedure then does the debounce task.
• After the debounce time, another check is made to see if the key is still pressed. If the columns are
now all high, then no key is pressed and the initial detection was caused by a noise pulse or a light
brushing past a key. If any of the columns are still low, then the assumption is made that it
was a valid keypress.
• The final task is to determine the row and column of the pressed key and convert this row and
column information to the hex code for the pressed key. To get the row and column information, a
low is output to one row and the column are read. If none of the columns is low, the pressed key is
not in that row. So the low is rotated to the next row and the column are checked again. The process
is repeated until a low on a row produces a low on one of the column.
• The pressed key then is in the row which is low at that time.
• The connection fig shows the byte read in from the input port will contain a 4-bit code which
represents the row of the pressed key and a 4-bit code which represent the column of the pressed key.

• Error trapping: The concept of detecting some error condition such as “ no match found” is called
error trapping. Error trapping is a very important part of real programs. Even in simple programs,
think what might happen with no error trap if two keys in the same row were pressed at exactly at the
same time and a column code with two lows in it was produced.
• This code would not match any of the row-column codes in the table, so after all the values in the
table were checked, assigned register in program would be decremented from 0000H to FFFFH. The
compare decrement cycle would continue through 65,536 memory locations until, by change the
value in a memory location matched the row-column code. The contents of the lower byte register at
hat point would be passed back to the calling routine. The changes are 1 in 256 that would be the
correct value for one of the pressed keys. You should keep an error trap in a program whenever there
is a chance for it.
2. Keyboard Interfacing with Hardware: For the system where the CPU is too busy to be bothered doing
these tasks in software, an external device is used to do them.
• One of a MOS device which can be do this is the General Instruments AY5-2376 which can be
connected to the rows and columns of a keyboard switch matrix.
• The AY5-2376 independently detects a keypress by cycling a low down through the rows and
checking the columns. When it finds a key pressed, it waits a debounce time.
• If the key is still pressed after the debounce time, the AY5-2376 produces the 8-bit code for the
pressed key and send it out to microcomputer port on 8 parallel lines. The microcomputer knows that
a valid ASCII code is on the data lines, the AY5-2376 outputs a strobe pulse.
• The microcomputer can detect this strobe pulse and read in ASCII code on a polled basis or it can
detect the strobe pulse on an interrupt basis.
• With the interrupt method the microcomputer doesn‟t have to pay any attention to the keyboard
until it receives an interrupt signal.
• So this method uses very little of the microcomputer time. The AY5-2376 has a feature called two-
key rollover. This means that if two keys are pressed at nearly the same time, each key will be
detected, debounced and converted to ASCII.
• The ASCII code for the first key and a strobe signal for it will be sent out then the ASCII code for
the second key and a strobe signal for it will be sent out and compare this with two-key lockout.

Example
• Interface a 4 * 4 keyboard with 8086 using 8255 an write an ALP for detecting a key closure and
return the key code in AL. The debounce period for a key is 10ms. Use software debouncing
technique. DEBOUNCE is an available 10ms delay routine.
• Solution: Port A is used as output port for selecting a row of keys while Port B is used as an input
port for sensing a closed key. Thus the keyboard lines are selected one by one through port A and the
port B lines are polled continuously till a key closure is sensed. The routine DEBOUNCE is called
for key debouncing. The key code is depending upon the selected row and a low sensed column.

• The higher order lines of port A and port B are left unused. The address of port A and port B will
respectively 8000H and 8002H while address of CWR will be 8006H. The flow chart of the
complete program is as given. The control word for this problem will be 82H. Code segment CS is
used for storing the program code.
• Key Debounce : Whenever a mechanical push-button is pressed or released once, the mechanical
components of the key do not change the position smoothly, rather it generates a transient response.

• These transient variations may be interpreted as the multiple key pressure and responded accordingly by
the microprocessor system.
• To avoid this problem, two schemes are suggested: the first one utilizes a bistable multivibrator at the
output of the key to debounce .
• The other scheme suggests that the microprocessor should be made to wait for the transient period ( usually
10ms ), so that the transient response settles down and reaches a steady state.
Example
• A logic „0‟ will be read by the microprocessor when the key is pressed.
• In a number of high precision applications, a designer may have two options- the first is to have more than
one 8-bit port, read (write) the port one by one and then from the multibyte data, the second option allows
forming 16-bit ports using two 8-bit ports and use 16-bit read or write operations.

4.6 OUTCOMES:
 To write the relation relation regarding the component connectivity.

 How to use keyboard and video display and how to perform data conversions.
1. Interfacing eight 7-segment display using 8255 ppI with 8086. Write an
ALP to display 1,2,3,4,5,6,7,8 over the eight -7segment displays continuously .
2. Explain the control word format of 8255PPI . Explain with a block diagram how to interface
4X4 matrix keyboard with 8086 using 8255 PPI .
3. With necessary hardware & software, show the interface of 7 segment LED display to a 8086
processor.
4. Write an algorithm and program for an 8086 procedure to drive the stepper motor as one
rotation clockwise & anticlockwise for 360 degrees.
5. Interface 7-segment display through 8255 PPI with 8086 for BCD TO 7-segment display
using XLAT instruction.
2012,ISBN978-1-25-900613-5.

MODULE 5: Basic Peripherals and their Interfacing with 8086 (Part 2), INT
21H DOS Function calls, Other Architectures
Structure
5.0 Introduction
5.1 Objectives
5.2 Interfacing ADC-0808/0809, DAC-0800, Stepper Motor using 8255
5.3 Timer 8254 – Mode 0, 1, 2 & 3 and Interfacing programmes for these modes
5.4 INT 21H DOS Function calls - for handling Keyboard and Display
5.5 Architecture of 8088, Architecture of NDP 8087
5.6 Von-Neumann & Harvard CPU architecture, CISC & RISC CPU architecture
5.7 Outcomes
5.8 Questions /Answers
5.0 INTRODUCTION:
Intel‟s 8279 is a general purpose Keyboard Display controller that simultaneously drives the display of a
system and interfaces a Keyboard with the CPU. The Keyboard Display interface scans the Keyboard to
identify if any key has been pressed and sends the code of the pressed key to the CPU. It also transmits the
data received from the CPU, to the display device. Both of these functions are performed by the controller
in repetitive fashion without involving the CPU. The Keyboard is interfaced either in the interrupt or the
polled mode.
The 8086 microprocessor is basically an integer processing unit and works directly on a varietyof integer da
ta types. Many programs used in engineering, science, business, need to performmathematical operations lik
e logarithms of a number, square root of a number, sine of an angleetc. It may also be needed to perform co
mputations with very large numbers like 10+56, or verysmall numbers like 10-67.

5.1 OBJECTIVES:
 Study of interfacing of processor with different types hardware components such as

keyboard and alphanumeric displays.
 Understanding Keyboard and Video Display, Data Conversions.
 Study about Co-processor configuration, Pin-Outs and the Pin Functions, Clock
Generator, Bus Buffering and Latching.
 Understanding Bus Timings, Ready and Wait State, Minimum versus Maximum Mode.
Memory Devices.
5.2 Interfacing ADC-0808/0809, DAC-0800, Stepper Motor using 8255
Interfacing Analog to Digital Data Converters

• In most of the cases, the PIO 8255 is used for interfacing the analog to digital converters with
microprocessor.
• We have already studied 8255 interfacing with 8086 as an I/O port, in previous section. This section we
will only emphasize the interfacing techniques of analog to digital converters with 8255.
• The analog to digital converters is treaded as an input device by the microprocessor, that sends an
initialising signal to the ADC to start the analogy to digital data conversation process. The start of
conversation signal is a pulse of a specific duration. The process of analog to digital conversion is a slow
process, and the microprocessor has to wait for the digital data till the conversion is over. After the
conversion is over, the ADC sends end of conversion EOC signal to inform the microprocessor that the
conversion is over and the result is ready at the output buffer of the ADC. These tasks of issuing an SOC
pulse to ADC, reading EOC signal from the ADC and reading the digital output of the ADC are carried out
by the CPU using 8255 I/O ports.
The time taken by the ADC from the active edge of SOC pulse till the active edge of EOC signal is called as
the conversion delay of the ADC.
• It may range any where from a few microseconds in case of fast ADC to even a few hundred milliseconds
in case of slow ADCs
• The available ADC in the market use different conversion techniques for conversion of analog signal to
digitals.
Successive approximation techniques and dual slope integration techniques are the most popular techniques
used in the integrated ADC chip.
• General algorithm for ADC interfacing contains the following steps:
1. Ensure the stability of analog input, applied to the ADC.
2. Issue start of conversion pulse to ADC
3. Read end of conversion signal to mark the end of conversion processes.
4. Read digital data output of the ADC as equivalent digital output.
• Analog input voltage must be constant at the input of the ADC right from the start of conversion till the end
of the conversion to get correct results. This may be ensured by a sample and hold circuit which samples the
analog signal and holds it constant for a specific time duration. The microprocessor may issue a hold signal
to the sample and hold circuit.
• If the applied input changes before the complete conversion process is over, the digital equivalent of the
analog input calculated by the ADC may not be correct.
ADC 0808/0809 :
• The analog to digital converter chips 0808 and 0809 are 8- bit CMOS, successive approximation
converters. Thitechnique is one of the fast techniques for analog to digital conversion. The conversion delay
is 100μs at a clock frequency of 640 KHz, which is quite low as compared to other converters. These
converters do not need any external zero or full scale adjustments as they are already taken care of by
internal circuits. These converters internally have a 3:8 analog multiplexer so that at a time eight different
analog conversion by using address lines - ADD A, ADD B, ADD C. Using these address inputs,
multichannel data acquisition system can be designed using a single ADC. The CPU may drive these lines
using output port lines in case of multichannel applications. In case of single input applications, these may be
hardwired to select the proper input.
• There are unipolar analog to digital converters, i.e. they are able to convert only positive analog input
voltage to their digital equivalent. These chips do no contain any internal sample and hold circuit.

• If one needs a sample and hold circuit for the conversion of fast signal into equivalent digital quantities, it
has to be externally connected at each of the analog inputs.
• Vcc Supply pins +5V
• GND GND
• Vref + Reference voltage positive +5 Volts maximum.
• Vref_ Reference voltage negative 0Volts minimum.
• I/P0 –I/P7 Analog inputs
• ADD A,B,C Address lines for selecting analog inputs.
• O7 – O0 Digital 8-bit output with O7 MSB and O0 LSB
• SOC Start of conversion signal pin
• EOC End of conversion signal pin
• OE Output latch enable pin, if high enables output
• CLK Clock input for ADC


• Example: Interfacing ADC 0808 with 8086 using 8255 ports. Use port A of 8255 for transferring digital
data output of ADC to the CPU and port C for control signals. Assume that an analog input is present at I/P2
of the ADC and a clock input of suitable frequency is available for ADC.
• Solution: The analog input I/P2 is used and therefore address pins A,B,C should be 0,1,0 respectively to
select I/P2. The OE and ALE pins are already kept at +5V to select the ADC and enable the outputs. Port C
upper acts as the input port to receive the EOC signal while port C lower acts as the output port to send SOC
to the ADC.
• Port A acts as a 8-bit input data port to receive the digital data output from the ADC. The 8255 control
word is written as follows:
D7 D6 D5 D4 D3 D2 D1 D0
10011000
• The required ALP is as follows:
MOV AL, 98h ;initialise 8255 as
OUT CWR, AL ;discussed above.
MOV AL, 02h ;Select I/P2 as analog
OUT Port B, AL ;input.
MOV AL, 00h ;Give start of conversion
OUT Port C, AL ; pulse to the ADC
MOV AL, 01h
OUT Port C, AL
MOV AL, 00h
OUT Port C, AL
WAIT: IN AL, Port C ;Check for EOC by
RCR ; reading port C upper and
JNC WAIT ;rotating through carry.
IN AL, Port A ;If EOC, read digital equivalent in AL
HLT ;Stop.

Interfacing Digital To Analog Converters

INTERFACING DIGITAL TO ANALOG CONVERTERS: The digital to analog converters convert binary
number into their equivalent voltages. The DAC find applications in areas like digitally controlled gains,
motors speed controls, programmable gain amplifiers etc.
AD 7523 8-bit Multiplying DAC : This is a 16 pin DIP, multiplying digital to analog converter, containing
R-2R ladder for D-A conversion along with single pole double thrown NMOS switches to connect the
digital inputs to the ladder.

• The pin diagram of AD7523 is shown in fig the supply range is from +5V to +15V, while Vref may be any
where between -10V to +10V. The maximum analog output voltage will be any where between -10V to
+10V, when all the digital inputs are at logic high state.

• Usually a zener is connected between OUT1 and OUT2 to save the DAC from negative transients. An
operational amplifier is used as a current to voltage converter at the output of AD to convert the current out
put of AD to a proportional output voltage.
• It also offers additional drive capability to the DAC output. An external feedback resistor acts to control the
gain. One may not connect any external feedback resistor, if no gain control is required.
• EXAMPLE: Interfacing DAC AD7523 with an 8086 CPU running at 8MHZ and write an assembly
language program to generate a sawtooth waveform of period 1ms with Vmax 5V.
• Solution: Fig shows the interfacing circuit of AD 74523 with 8086 using 8255. program gives an ALP to
generate a sawtooth waveform using circuit.
ASSUME CS:CODE
CODE SEGMENT
START: MOV AL,80h ;make all ports output
OUT CW, AL
AGAIN: MOV AL,00h ;start voltage for ramp
BACK : OUT PA, AL
INC AL
CMP AL, 0FFh
JB BACK
JMP AGAIN
CODE ENDS
END START

• In the above program, port A is initialized as the output port for sending the digital data as input to DAC.
The ramp starts from the 0V (analog), hence AL starts with 00H. To increment the ramp, the content of AL
is increased during each execution of loop till it reaches F2H.
• After that the saw tooth wave again starts from 00H, i.e. 0V(analog) and the procedure is repeated. The
ramp period given by this program is precisely 1.000625 ms. Here the count F2H has been calculated by
dividing the required delay of 1ms by the time required for the execution of the loop once. The ramp slope
can be controlled by calling a controllable delay after the OUT instruction.
Another device often interfaced to a computer sys-tem is the stepper motor. A stepper motor is a digital
motor because it is moved in discrete steps as it traverses through 360°. A common stepper motor is
geared to move perhaps 15° per step in an inexpensive stepper motor, to 1° per step in a more costly,
high-precision stepper motor. In all cases, these steps are gained through many magnetic poles and/or
gearing.
If less power is required, one coil may be energized at a time, causing the motor to step at 45°, 135°,
225°, and 315°.Figure 5.6 shows a four-coil stepper motor that uses an armature with a single pole.
Notice that the stepper motor is shown four times with the armature (permanent magnetic) rotated to
four discrete places. This is accomplished by energizing the coils, as shown. This is an illustration of full
stepping. The stepper motor is driven by using NPN Darlington amplifier pairs to provide a large current
to each coil. A circuit that can drive this stepper motor is illustrated in Figure , with the four coils shown
in place. This circuit uses the 82C55 to provide it with the drive signals that are used to rotate the
armature of the motor in either the right-hand or left-hand direction.
Figure 5.6 Four Coil Stepper Motor
Figure 5.7 Interfacing Stepper Motor with 8255
A simple procedure that drives the motor (assuming that port A is programmed in mode 0 as an output
device) is listed in Example in both assembly language and as a function in C++. This subroutine is called,
with CX holding the number of steps and direction of the rotation. If CX is greater than 8000H, the motor
spins in the right-hand direction; if CX is less than 8000H, it spins in the left-hand direction. For example,
if the number of steps is 0003H, the motor moves in the left-hand direction three steps and if the number
of steps is 8003H, it moves three steps in the right-hand direction. The leftmost bit of CX is removed and the
remaining 15 bits contain the number of steps. Notice that the procedure uses a time delay (not illustrated)
that causes a l ms time delay. This time delay is required to allow the stepper-motor armature time to move
to its next position.
The current position is stored in memory location POS, which must be initialized with 33H, 66H,
0EEH, or 99H. This allows a simple ROR (step right) or ROL (step left) instruction to rotate the binary bit
pattern for the next step.
Stepper motors can also be operated in the half-step mode, which allows eight steps per sequence. This
is accomplished by using the full-step sequence described with a half step obtained by energizing one coil
interspersed between the full steps. Half-stepping allows the armature to be positioned at 0°, 90°, 180°, and
270°. The half-step position codes are 11H, 22H, 44H, and 88H. A complete sequence of eight steps
would be as follows: 11H, 33H, 22H, 66H, 44H, 0CCH, 88H, and 99H. This sequence could be either
output from a lookup table or generated with software.
.MODEL SMALL
.DATA
PA EQU 0DE00H
CW EQU 0DE03H
COUNT EQU 200

.CODE
MOV AX,@DATA
MOV DS,AX
MOV AL,80H
MOV DX,CW
OUT DX,AL
MOV CX,COUNT
MOV SI,05H
MOV DX,PA
MOV AL, 88H
AGAIN: OUT DX,AL
CALL DELAY
ROL AL,01H
LOOP AGAIN
DEC SI
JNZ AGAIN
MOV AH,4CH
INT 21H
DELAY PROC

PUSH CX
MOV BX,0055H
BACK1: MOV CX,0FFFFH
BACK: LOOP BACK
DEC BX
JNZ BACK1
POP CX
RET
DELAY ENDP
END
5.3 Timer 8254 – Mode 0, 1, 2 & 3 and Interfacing programmes for these
modes
The Intel 8254 is a counter/timer device designed to solve the common timing control problems in
microcomputer system design. It provides three independent 16-bit counters, each capable of handling
clock inputs up to 10 MHz. All modes are software programmable. The 8254 is a superset of the 8253.
The 8254 uses HMOS technology and comes in a 24-pin plastic or CERDIP package.

FUNCTIONAL DESCRIPTION
General
The 8254 is a programmable interval timer/counter designed for use with Intel microcomputer systems.
It is a general purpose, multi-timing element that can be treated as an array of I/O ports in the system
software.
The 8254 solves one of the most common problems in any microcomputer system, the generation of
accurate time delays under software control. Instead of setting up timing loops in software, the
programmer configures the 8254 to match his requirements and programs one of the counters for the
desired delay.
After the desired delay, the 8254 will interrupt the CPU. Software overhead is minimal and variable
length delays can easily be accommodated.
Some of the other counter/timer functions common
to microcomputers which can be implemented with the 8254 are:
# Real time clock
# Event-counter

# Digital one-shot
# Programmable rate generator
# Square wave generator
# Binary rate multiplier
# Complex waveform generator
# Complex motor controller
Block Diagram
DATA BUS BUFFER
This 3-state, bi-directional, 8-bit buffer is used to interface the 8254 to the system bus (see Figure 3).
READ/WRITE LOGIC
The Read/Write Logic accepts inputs from the system bus and generates control signals for the other
functional blocks of the 8254. A1 and A0 select one of the three counters or the Control Word Register to
be read from/written into. A ``low'' on the RD input tells the 8254 that the CPU is reading one of the
counters. A ``low'' on the WR input tells the 8254 that the CPU is writing either a Control Word or an
initial count. Both RD and WR are qualified by CS; RD and WR are ignored unless the 8254 has been
selected by holding CS low.
CONTROL WORD REGISTER

The Control Word Register (see Figure 4) is selected by the Read/Write Logic when A1,A0 e 11. If the
CPU then does a write operation to the 8254, the data is stored in the Control Word Register and is
interpreted as a Control Word used to define the operation of the Counters.
The Control Word Register can only be written to; status information is available with the Read-Back
Command.
COUNTER 0, COUNTER 1, COUNTER 2
These three functional blocks are identical in operation, so only a single Counter will be described. The
internal block diagram of a single counter is shown in Figure 5.
The Counters are fully independent. Each Counter may operate in a different Mode.
The Control Word Register is shown in the figure; it is not part of the Counter itself, but its contents
determine how the Counter operates.
The status register, shown in Figure 5, when latched, contains the current contents of the Control Word
Register and status of the output and null count flag. (See detailed explanation of the Read- Back
command.)
The actual counter is labelled CE (for ``Counting Element''). It is a 16-bit presettable synchronous down
counter. OLM and OLL are two 8-bit latches. OL stands for ``Output Latch''; the subscripts M and L
stand for ``Most significant byte'' and ``Least significant byte'' respectively. Both are normally referred to
as one unit and called just OL. These latches normally ``follow'' the CE, but if a suitable Counter Latch
Command is sent to the 8254, the latches ``latch'' the present count until read by the CPU and then return
to ``following'' the CE. One latch at a time is enabled by the counter's Control Logic to drive the internal
bus. This is how the 16-bit Counter communicates over the 8-bit internal bus. Note that the CE itself
cannot be read; whenever you read the count, it is the OL that is being read.
Similarly, there are two 8-bit registers called CRM and CRL (for ``Count Register''). Both are normally
referred to as one unit and called just CR. When a new count is written to the Counter, the count is stored
in the CR and later transferred to the CE. The Control Logic allows one register at a time to be loaded
from the internal bus. Both bytes are transferred to the CE simultaneously. CRM and CRL are cleared
when the Counter is programmed. In this way, if the Counter has been programmed for one byte counts
(either most significant byte only or least significant byte only) the other byte will be zero.
Note that the CE cannot be written into; whenever a count is written, it is written into the CR.
The Control Logic is also shown in the diagram. CLK n, GATE n, and OUT n are all connected to the
outside world through the Control Logic.
8254 SYSTEM INTERFACE

The 8254 is a component of the Intel Microcomputer Systems and interfaces in the same manner as all
other peripherals of the family. It is treated by the system's software as an array of peripheral I/O ports;
three are counters and the fourth is a control register for MODE programming.
Basically, the select inputs A0,A1 connect to the A0, A1 address bus signals of the CPU. The CS can be
derived directly from the address bus using a linear select method. Or it can be connected to the output of
a decoder, such as an Intel 8205 for larger systems.

OPERATIONAL DESCRIPTION
General
After power-up, the state of the 8254 is undefined. The Mode, count value, and output of all Counters are
undefined. How each Counter operates is determined when it is programmed. Each Counter must be
programmed before it can be used. Unused counters need not be programmed.
Programming the 8254
Counters are programmed by writing a Control Word and then an initial count. The Control Words are
written into the Control Word Register, which is selected when A1, A0 e 11. The Control Word itself
specifies which Counter is being programmed.

By contrast, initial counts are written into the Counters, not the Control Word Register. The A1,A0 inputs
are used to select the Counter to be written into. The format of the initial count is determined by the
Control Word used.
Write Operations
The programming procedure for the 8254 is very flexible. Only two conventions need to be remembered:
1) For each Counter, the Control Word must be written before the initial count is written.
2) The initial count must follow the count format specified in the Control Word (least significant byte
only, most significant byte only, or least significant byte and then most significant byte). Since the
Control Word Register and the three Counters have separate addresses (selected by the A1,A0 inputs),
and each Control Word specifies the Counter it applies to (SC0,SC1 bits), no special instruction sequence
is required. Any programming sequence that follows the conventions in Figure 7 is acceptable.
A new initial count may be written to a Counter at any time without affecting the Counter's programmed
Mode in any way. Counting will be affected as described in the Mode definitions. The new count must
follow the programmed count format.
If a Counter is programmed to read/write two-byte counts, the following precaution applies: A program
must not transfer control between writing the first and second byte to another routine which also writes
into that same Counter. Otherwise, the Counter will be loaded with an incorrect count.
Read Operations
It is often desirable to read the value of a Counter without disturbing the count in progress. This is easily
done in the 8254.

There are three possible methods for reading the counters: a simple read operation, the Counter Latch
Command, and the Read-Back Command. Each is explained below. The first method is to perform a
simple read operation. To read the Counter, which is selected with the A1, A0 inputs, the CLK input of
the selected Counter must be inhibited by using either the GATE input or external logic. Otherwise, the
count may be in the process of changing when it is read, giving an undefined result.
COUNTER LATCH COMMAND
The second method uses the ``Counter Latch Command''. Like a Control Word, this command is written
to the Control Word Register, which is selected when A1, A0 e 11. Also like a Control Word, the
SC0, SC1 bits select one of the three Counters, but two other bits, D5 and D4, distinguish this command
from a Control Word.
MODE 0: INTERRUPT ON TERMINAL COUNT
Mode 0 is typically used for event counting. After the Control Word is written, OUT is initially low, and
will remain low until the Counter reaches zero. OUT then goes high and remains high until a new count
or a new Mode 0 Control Word is written into the Counter. GATE e 1 enables counting; GATE e 0
disables counting. GATE has no effect on OUT.
After the Control Word and initial count are written to a Counter, the initial count will be loaded on the
next CLK pulse. This CLK pulse does not decrement the count, so for an initial count of N, OUT does
not go high until N a 1 CLK pulses after the initial count is written.
If a new count is written to the Counter, it will be loaded on the next CLK pulse and counting will
continue from the new count. If a two-byte count is written, the following happens:
1) Writing the first byte disables counting. OUT is set low immediately (no clock pulse required)
2) Writing the second byte allows the new count to be loaded on the next CLK pulse.
This allows the counting sequence to be synchronized by software. Again, OUT does not go high until
Na1 CLK pulses after the new count of N is written.
If an initial count is written while GATE e 0, it will still be loaded on the next CLK pulse. When GATE
goes high, OUT will go high N CLK pulses later; no CLK pulse is needed to load the Counter as this has
already been done.
MODE 1: HARDWARE RETRIGGERABLE
ONE-SHOT OUT will be initially high. OUT will go low on the CLK pulse following a trigger to begin
the one-shot pulse, and will remain low until the Counter reaches zero.
OUT will then go high and remain high until the CLK pulse after the next trigger.
After writing the Control Word and initial count, the Counter is armed. A trigger results in loading the
Counter and setting OUT low on the next CLK pulse, thus starting the one-shot pulse. An initial count of
N will result in a one-shot pulse N CLK cycles in duration. The one-shot is retriggerable, hence OUT will
remain low for N CLK pulses after any trigger. The one-shot pulse can be repeated without rewriting the
same count into the counter. GATE has no effect on OUT.
If a new count is written to the Counter during a oneshot pulse, the current one-shot is not affected unless
the counter is retriggered. In that case, the Counter is loaded with the new count and the oneshot pulse
continues until the new count expires.
MODE 2: RATE GENERATOR
This Mode functions like a divide-by-N counter. It is typically used to generate a Real Time Clock
interrupt. OUT will initially be high. When the initial count has decremented to 1, OUT goes low for one
CLK pulse. OUT then goes high again, the Counter reloads the initial count and the process is repeated.
Mode 2 is periodic; the same sequence is repeated indefinitely. For an initial count of N, the sequence
repeats every N CLK cycles. GATE e 1 enables counting; GATE e 0 disables counting. If GATE goes
low during an output pulse, OUT is set high immediately. A trigger reloads the Counter with the initial
count on the next CLK pulse; OUT goes low N CLK pulses after the trigger. Thus the GATE input can
be used to synchronize the Counter.
After writing a Control Word and initial count, the Counter will be loaded on the next CLK pulse. OUT
goes low N CLK Pulses after the initial count is written. This allows the Counter to be synchronized by
software also. Writing a new count while counting does not affect the current counting sequence. If a
trigger is received after writing a new count but before the end of the current period, the Counter will be
loaded with the new count on the next CLK pulse and counting will continue from the new count.
Otherwise, the new count will be loaded at the end of the current counting cycle. In mode 2, a COUNT of
1 is illegal.
MODE 3: SQUARE WAVE MODE
Mode 3 is typically used for Baud rate generation. Mode 3 is similar to Mode 2 except for the duty cycle
of OUT. OUT will initially be high. When half the initial count has expired, OUT goes low for the
remainder of the count. Mode 3 is periodic; the sequence above is repeated indefinitely. An initial count
of N results in a square wave with a period of N CLK cycles. GATE e 1 enables counting; GATE e 0
disables counting. If GATE goes low while OUT is low, OUT is set high immediately; no CLK pulse is

required. A trigger reloads the Counter with the initial count onthe next CLK pulse. Thus the GATE input
can be used to synchronize the Counter.
After writing a Control Word and initial count, the Counter will be loaded on the next CLK pulse. This
allows the Counter to be synchronized by software also. Writing a new count while counting does not
affect the current counting sequence. If a trigger is received after writing a new count but before the end
of the current half-cycle of the square wave, the
Counter will be loaded with the new count on the next CLK pulse and counting will continue from the
new count. Otherwise, the new count will be loaded at the end of the current half-cycle.
Mode 3 is implemented as follows:
Even counts: OUT is initially high. The initial count is loaded on one CLK pulse and then is
decremented by two on succeeding CLK pulses. When the count expires OUT changes value and the
Counter is reloaded with the initial count. The above process is repeated indefinitely.
Odd counts: OUT is initially high. The initial count minus one (an even number) is loaded on one CLK
pulse and then is decremented by two on succeeding CLK pulses. One CLK pulse after the count expires,
OUT goes low and the Counter is reloaded with the initial count minus one. Succeeding CLK pulses
decrement the count by two. When the count expires, OUT goes high again and the Counter is reloaded
with the initial count minus one. The above process is repeated indefinitely. So for odd counts, OUT will
be high for (N a 1)/2 counts and low for (N b 1)/2 counts.
MODE 4: SOFTWARE TRIGGERED STROBE
OUT will be initially high. When the initial count expires, OUT will go low for one CLK pulse and then
go high again. The counting sequence is ``triggered'' by writing the initial count.
GATE e 1 enables counting; GATE e 0 disables counting. GATE has no effect on OUT. After writing a
Control Word and initial count, the Counter will be loaded on the next CLK pulse. This CLK pulse does
not decrement the count, so for an initial count of N, OUT does not strobe low until N a 1 CLK pulses
after the initial count is written. If a new count is written during counting, it will be loaded on the next
CLK pulse and counting will continue from the new count. If a two-byte count is written, the following
happens:
1) Writing the first byte has no effect on counting.
2) Writing the second byte allows the new count to be loaded on the next CLK pulse.
This allows the sequence to be ``retriggered'' by software. OUT strobes low N a 1 CLK pulses after the
new count of N is written.
MODE 5: HARDWARE TRIGGERED STROBE

(RETRIGGERABLE)
OUT will initially be high. Counting is triggered by a rising edge of GATE. When the initial count has
expired, OUT will go low for one CLK pulse and then go high again.
After writing the Control Word and initial count, the counter will not be loaded until the CLK pulse after
a trigger. This CLK pulse does not decrement the count, so for an initial count of N, OUT does not strobe
low until N a 1 CLK pulses after a trigger.
A trigger results in the Counter being loaded with the initial count on the next CLK pulse. The counting
sequence is retriggerable. OUT will not strobe low for N a 1 CLK pulses after any trigger. GATE has no
effect on OUT.
If a new count is written during counting, the current counting sequence will not be affected. If a trigger
occurs after the new count is written but before the current count expires, the Counter will be loaded with
the new count on the next CLK pulse and counting will continue from there.
5.4 INT 21H DOS Function calls - for handling Keyboard and Display
INT 21h is provided by DOS. When MS-DOS is loaded into the computer, INT 21H can be invoked to
perform some extremely useful functions. These functions are commonly referred to as DOS INT 21H
function calls. Data input and output through the keyboard and monitor are the most commonly used
functions. Below are two examples that use DOS interrupts.
1. Display the message defined with variable DATA_ASC DB „the earth is but one country‟,‟$‟
MOV AH,09 ;option 9 to display string of data
MOV DX, OFFSET DATA_ASC ;DX= offset address of data
INT 21H ; invoke the interrupt
2. Inputting a single character, with echo.
MOV AH, 01 ;option 01 to input one character
INT 21H ;invoke the interrupt
1. Function Call 01: Read The Key Board
Input Parameter Ah = 01 Read A Character From Keyboard. Echo It On CRO Screen and Return The ASCII
Code Of The Key Pressed in Al Output Parameter: Al = ASCII Code Of Character
2. Function Call 02h: Display On CRT Screen

Input Parameter: Ah = 02
Dl = ASCII Character To Be Displayed On CRT Screen
3. Function Call 03: Read Character From Com1
Input Parameter: Ah = 03h
Function: Reads Data From Com Port
Output Parameter: Al = ASCII Code Of Character
4. Function Call 04: Write Character To Com1
Input Parameter: Ah = 04h Dl = ASCII Code Of Character To Be Transmitted
Function: Writes Data To Com Port
5.5 Architecture of 8088, Architecture of NDP 8087






















5.6 Von-Neumann & Harvard CPU architecture, CISC & RISC CPU
architecture
ARCHITECTURE
There are two basic architectures:
1) Harvard Architecture
2) Princeton Architecture(Von Neumann Architecture)

Princeton (Von Neumann) Instruction: Read a data byte from memory and store in the accumulator. (1)If
this instruction is executed in Princeton architecture then it is executed as follows.

The following cycles are required to execute the above instruction Cycle 1: read instruction (Instruction
Fetch cycle) Cycle 2: Read Data out from memory and store in accumulator.
Using Harvard Architecture
The execution above instruction will be done in the following cycles

Cycle 1: Complete the previous instructions and Read the present instruction. (Note: this will not be
done only for jump instruction as previous instruction .Because if jump is there, it flushes off the
instructions int the stack).
Cycle 2 : Execute , Read Data memory and store in Accumulator. Read next instruction. Advantage of
this architecture is that each instruction takes one instruction cycle.
Example: in PIC Microcontroller, of 4 MHz , it requires 4 clock cycles to execute one instruction cycle.
Hence, 1 million instructions could be executed in one second

5.7 OUTCOMES
 Convert between decimal data and signed integer, BCD, and floating-point data for use
by the arithmetic coprocessor
 Explain the operation of the 80X87 arithmetic coprocessor.
5.8 Questions /Answers
1. Draw the internal structure of 80X87 arithmetic coprocessor and explain.

2. Explain the different 8087 data types along with their format.
3. Explain how 8086 and 8087 co-execute in executing an instruction
2012, ISBN 978-1-25-900613-5.

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MICROPROCESSORS 15EC42

MODULE 1: 8086 PROCESSOR, INSTRUCTION SET OF 8086

1.0 Historical background

1.0 HISTORICAL BACKGROUND:

The Mechanical age:

DEPT of ECE, ATMECE, MYSURU Page 1

The Electrical age:

DEPT of ECE, ATMECE, MYSURU Page 2

The Microprocessor age:

DEPT of ECE, ATMECE, MYSURU Page 3

The 16-bit Microprocessor:

The 80286 microprocessor:

The 32-bit Microprocessors:

The 80386 Microprocessor:

DEPT of ECE, ATMECE, MYSURU Page 4

The 80486 Microprocessor:

The Pentium Microprocessor:

1. To learn basics of microprocessor and in detail about 8086

1.2 8086 CPU ARCHITECTURE

Register Organization of 8086

General data registers Segment Pointers and index

Register organization of 8086

DEPT of ECE, ATMECE, MYSURU Page 5

General Data Registers:

There are four segment register in 8086

Pointers and Index Registers.

The pointers contain offset within the particular segments.

DEPT of ECE, ATMECE, MYSURU Page 6

- The pointer register BP contains offset within the data segment.

The index registers are particularly useful for string manipulation.

The 8086 architecture supports

(a) Bus Interface unit (BIU)

Generating a physical address:

These two operations together produce a 20-bit physical address.

The physical address is calculated as:

DEPT of ECE, ATMECE, MYSURU Page 7

4 bit positions 0010 0000 0001 0000 0000

This is a 6 byte long queue, works in first-in first-out policy.

The execution unit contains.

The addresses of the segment may be assigned as 0000H to F000H respectively.

The offset values are from 0000H to FFFFFH.

DEPT of ECE, ATMECE, MYSURU Page 8

Non-overlapping segments and overlapping segments are shown in the figure.

The main advantages of the segmented memory scheme are as follows:

A 16 flag register is used in 8086. It is divided into two parts .

The complete bit configuration of 8086 is shown in the figure.

DEPT of ECE, ATMECE, MYSURU Page 9

The 8086 is a 16-bit microprocessor. This microprocessor operate in single processor or

Description of signals of 8086

DEPT of ECE, ATMECE, MYSURU Page 10

COND Ground for the internal circuit

M / IO -Memory/IO M / I O signal selects either memory operation or  o operation. This line

DEPT of ECE, ATMECE, MYSURU Page 11

These status lines are encoded as follows

Physical Memory Organization

DEPT of ECE, ATMECE, MYSURU Page 12

If the address bus contains FFFFOH

DEPT of ECE, ATMECE, MYSURU Page 13

Segment Register Default Offset

Different registers and their operations are listed below:

AX Word multiply, Word divide, word I/O

AL Byte Multiply, Byte Divide, Byte I/O, translate, Decimal Arithmetic

AH Byte Multiply, Byte Divide