ICA-ACCA 2018, October 17-19, 2018, Greater Concepción, Chile
Reduced Modified T-Type Topology for Cascaded
Multilevel Inverters
M. Ali Hosseinzadeh, M. Sarbanzadeh, E. Sarebanzadeh, M. Rivera and J. Muñoz
Abstract—Multilevel inverters are applied in medium-voltage
high power applications, nowadays. The drawback of multilevel
inverters is required for a high number of power electronics
devices to generate more voltage levels in order to reduce THD’s
magnitude. This paper presents a reduced T-type topology for
a cascaded multilevel inverter. The main advantages of the
proposed topology are reducing the switching elements and
the total blocking voltage for generating a high number of
levels. A comprehensive comparison is done with other similar
multilevel inverter topologies to show the superiority of the
reduced topology. The performance of the reduced multilevel
inverter is presented for a 61-levels cascaded topology.
Index Terms—T-type inverter; cascaded topology; multilevel
inverter; switching elements.
I. I NTRODUCTION
A multi-level inverter (MLI) is a power architecture which
generates an ac output level by considering several DC power
supplies [1]. This type of inverter uses lots of DC supplies and
semiconductor switches counts, to generate a large number
of voltage levels at the output. MLIs can be applied in high
power, high voltage applications because they share the voltage
on their switches [2].
In addition, MLIs have several advantages, among them
high power quality, lower total harmonic distortion (THD),
lower 𝑑𝑣/𝑑𝑡, etc. [3]. The conventional multilevel inverter
structures with industrial applications include neutral point
clamped (NPC) [4], flying capacitor (FC) [5], cascade H-
bridge (CHB) MLIs [6]. CHBs applied for various applica-
tions due to their simplified model can be categorized into
symmetrical and asymmetrical modes. In symmetrical (CHB)
the magnitude of all DC supplies are the same and in the
case of an asymmetrical (CHB), DC supply magnitudes are
incremented to accomplish required voltage level. CHB is
employed for medium and higher voltage levels whereas in
both NPC MLIs and FC MLIs structures voltage balancing
and sharing is challenging for higher voltage levels [7], [8].
In NPC and FC MLIs topologies, there are many flying
capacitors and diodes clamped to generate more levels [9],
[10]. The CHB structure includes the series connection of
several H-bridges. Three different methods are used to define
the value of DC supplies [11]. In [12] a symmetric cascaded
MLI structure is developed. The main problems of symmetric
cascaded converters are: the requirement of high number of
components to increase the levels because the magnitude of
M. Ali Hosseinzadeh, M. Sarbanzadeh, M. Rivera and J. Muñoz are
with the Faculty of Engineering, Universidad de Talca, Curico, Chile.
(e-mail: m.a hosseinzadeh@yahoo.com; maryam sarbanzadeh@yahoo.com;
marcoriv@utalca.cl; jamunoz@utalca.cl.
E. Sarebanzadeh is with the University of Tabriz, Tabriz, Iran. (e-mail:
el sarebanzade@yahoo.com; .
c
978-1-5386-5586-3/18/$31.00
2018 IEEE 1
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DC supplies are the same. To mitigate these drawbacks, several
topologies have been proposed in [13]–[15]. Despite the fact
that these topologies have novel topologies, the switch count
still stands high. Researchers are continuously making efforts
to develop novel structures [16].
Recapitulating the above remarks, in this paper, a reduced
modified T-type MLI is introduced. Next, a cascade connection
based on proposed structure is extended. To highlight the
capability of the presented structure, a deep comparative
analysis is presented among the proposed reduced module
and well known MLI structures to understand its benefits and
drawbacks. The simulation results are provided for the cascade
of two units to obtain 61 levels.
II. M ETHODOLOGY
A. Modified T-Type Inverter
Fig. 1(a) depicts a T-type Inverter. It generates two voltage
levels 𝑉2 and 𝑉1 +𝑉2 . Fig. 1(b) indicates a modified power cir-
cuit of a T-type inverter. This inverter uses four unidirectional
switches instead of a bidirectional switch between 𝑉1 and 𝑉2
in conventional T- connection inverter [17]. So, this circuit
can generate more levels compared to the conventional T-type
inverter so that generated level will have the following levels
𝑉1 , 𝑉2 and 𝑉1 + 𝑉2 . Considering Fig. 1, for generating more
voltage levels, two other switches have been placed in parallel
to switches of 𝑇1 and 𝑇2 (these switches produce positive and
negative voltage levels) and have been cascaded to two other
DC supplies. However, this inverter includes ten unidirectional
power and can generated 15 voltage levels with magnitudes
of 0, ±𝑉𝐷𝐶 , ±2𝑉𝐷𝐶 , ±3𝑉𝐷𝐶 , ±4𝑉𝐷𝐶 , ±5𝑉𝐷𝐶 , ±6𝑉𝐷𝐶 and
±7𝑉𝐷𝐶 in the output. Fig. 2 indicates the power circuit of this
structure. All the voltage levels of a modified T-type power
structure are provided in Table II. An interesting idea would
be to mix a half-inverter to a modified T-type inverter, to have
a new basic module inverter which generates more voltage
levels.
B. Proposed Module Structure
A new basic module is designed by back-to-back con-
nections with a modified T-type and half-bridge inverter
(BBTHB). That means, a half-bridge inverter is connected
from points A and B according to Fig. 2. The number of
DC supplies will be five and their magnitudes are different.
This idea gives a new structure for MLIs that creates more
number levels with lower components. The power circuit of
the proposed BBTHB module is indicated in Fig. 3, that can
produce 31 levels with 5 DC supplies and 12 power switches.
 ICA-ACCA 2018, October 17-19, 2018, Greater Concepción, Chile
2

TABLE I: Output Voltage Levels of 15-Level Modified T-Type

A
 Inverter
 V1
V1 S1
S1 S1 Output Voltage Levels S1 S2 S3 T1 T̄1 T2 T̄2
𝑉1 + 𝑉2 + 𝑉3 1 1 1 1 0 0 0
A 𝑉2 + 𝑉3 1 0 1 1 0 0 0
 𝑉1 + 𝑉3 1 1 0 1 0 0 0
 V2
V2 S3 𝑉3 1 0 0 1 0 0 0
S2 S2 𝑉1 + 𝑉2 1 1 1 0 1 0 0
S1 𝑉2 1 0 1 0 1 0 0
𝑉1 1 1 0 0 1 0 0
B 0 1 0 0 0 1 0 0
B −𝑉1 0 1 0 0 1 0 1
(b) −𝑉2 0 0 1 0 0 0 1
(a)
−𝑉1 − 𝑉2 0 1 1 1 1 0 1
Fig. 1: (a) Classical T-type converter; (b) modified T-type −𝑉3 1 0 0 0 0 1 0
−𝑉1 − 𝑉3 0 1 0 0 0 1 0
converter
−𝑉2 − 𝑉3 1 0 1 0 0 1 0
−𝑉1 − 𝑉2 − 𝑉3 0 1 1 0 0 1 0

D1
T2
negative levels by the switches 𝑆1 , 𝑆¯1 , 𝑆2 , 𝑆, ¯ respectively.

V 4 T2 V1
 To simplify, the voltage drop of switch conduction state is
S1 S1 S3 eliminated. To stay away of short-circuits of DC supplies, the
unidirectional switches 𝑆1 , 𝑆¯1 , 𝑆2 , 𝑆¯2 , 𝑆3 , 𝑆¯3 , 𝑆4 , 𝑆¯4 , 𝑇1 , 𝑇¯1 ,
B A 𝑇2 and 𝑇¯2 operate in an opposite mode.

V2 BBTH module produces nine levels when the DC supply
V 3 T1 S 2 S2 S3 magnitudes are all equal and if values are chosen differently

then the BBTH module generates higher voltage levels, we
consider their magnitudes as follows:
D2 T 1

𝑉1 = 1𝑉𝐷𝐶 (1)
Fig. 2: Modified T-type inverter. 𝑉2 = 2𝑉𝐷𝐶 (2)
𝑉3 = 4𝑉𝐷𝐶 (3)
This configuration can generate the negative levels without
𝑉4 = 𝑉5 = 8𝑉𝐷𝐶 (4)
H-bridge at the output. In this module two switch configura-
tions are used: unidirectional and bidirectional.
C. Total Blocking Voltage Calculation
The difference between these types of switches are the num-
ber of diodes and insulated gate bipolar transistors (IGBTs) In BBTH module, the equations of total blocking voltage
where unidirectional uses an IGBT and a reverse diode and (TBV) of the switches is obtained as follows:
the bidirectional uses two IGBTs and two reverse diodes. Table
I depicts the available commutation states for the modified T- 𝑇 𝐵𝑉 = 𝑉𝑆1 + 𝑉𝑆1
¯ + 𝑉𝑆2 + 𝑉𝑆2
¯ + 𝑉𝑆3 +
Type inverter module. This structure presents both positive and (5)
𝑉𝑆3
¯ + 𝑉𝑆4 + 𝑉𝑆4
¯ + 𝑉𝑇 1 + 𝑉𝑇¯ 1 + 𝑉𝑇 2 + 𝑉𝑇¯ 2

The blocking voltage on each switching device is:

D1 𝑉𝑆1 = 𝑉1 + 𝑉1 (6)
T 2
𝑉𝑆2 = 𝑉1 (7)


V 5 T2 V1 𝑉𝑆3 = 𝑉2 (8)
S4 S1 S1 S3
𝑉𝑆4 = 𝑉3 (9)

B V3 A
V2
 𝑉𝑇¯1 = 𝑉1 + 𝑉2 + 𝑉3 + 2𝑉4 (10)
S4 V 4 T1 S 2 S2 S3 𝑉𝑇 2 = 𝑉1 + 𝑉2 + 𝑉3 + 𝑉4 (11)

Considering the above equations and (1) to (5), 𝑇 𝐵𝑉 is
D2 T 1 defined as:
𝑇 𝐵𝑉 = 8(𝑉1 + 𝑉2 ) + 6(𝑉3 + 𝑉4 ) = 96𝑉𝐷𝐶 (12)
Fig. 3: BBTHB proposed structure.

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 ICA-ACCA 2018, October 17-19, 2018, Greater Concepción, Chile
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TABLE II: Output Voltage Levels of 31-Level BBTHB In-

verter D1,1
T 2,1

Output Voltage S1 S2 S3 S4 T1 T̄1 T2 T̄2 


V 5,1 T 2,1 V 1,1
+15𝑉𝐷𝐶 1 1 1 1 1 0 0 0
S 4,1 S 1,1 S 1,1 S 3,1
+14𝑉𝐷𝐶 1 0 1 1 1 0 0 1
+13𝑉𝐷𝐶 1 1 0 1 1 0 0 0 
V 3,1 A
+12𝑉𝐷𝐶 1 0 0 1 1 0 0 0 
V 2,1
+11𝑉𝐷𝐶 1 1 1 0 1 0 0 0
+10𝑉𝐷𝐶 1 0 1 0 1 0 0 0
S 4,1 V 4,1 T 1,1S 2,1 S 2,1 S 3,1

+9𝑉𝐷𝐶 1 1 0 0 1 0 0 0 vo,1
+8𝑉𝐷𝐶 1 0 0 0 1 0 0 0
+7𝑉𝐷𝐶 1 1 1 0 0 1 0 0 D 2,1 T 1,1
+6𝑉𝐷𝐶 1 0 1 1 0 1 0 0
+5𝑉𝐷𝐶 1 1 0 1 0 1 0 0
+4𝑉𝐷𝐶 1 0 0 1 0 1 0 0
D1,2
+3𝑉𝐷𝐶 1 1 1 0 0 1 0 0
T 2,2
+2𝑉𝐷𝐶 1 0 1 0 0 1 0 0
+1𝑉𝐷𝐶 1 1 0 0 0 1 0 0 

0 1 0 0 0 0 1 0 0 V 5,2 T 2,2 V 1,2
−1𝑉𝐷𝐶 0 1 0 1 0 0 0 1 S 4,2 S 1,2 S 1,2 S 3,2
−2𝑉𝐷𝐶 0 0 1 1 0 0 0 1 
V 3,2
−3𝑉𝐷𝐶 0 1 1 1 0 0 0 1 
−4𝑉𝐷𝐶 0 0 0 0 0 0 0 1 V 2,2
−5𝑉𝐷𝐶 0 1 0 0 0 0 0 1 S 4,2 V 4,2 T 1,2S 2,2 S 2,2 S 3,2
−6𝑉𝐷𝐶 0 0 1 0 0 0 0 1  vo
−7𝑉𝐷𝐶 0 1 1 0 0 0 0 1 v o ,2
−8𝑉𝐷𝐶 0 0 0 1 0 0 1 0 D 2,2 T 1,2
−9𝑉𝐷𝐶 0 1 0 1 0 0 1 0
−10𝑉𝐷𝐶 0 0 1 1 0 0 1 0
−11𝑉𝐷𝐶 0 1 1 1 0 0 1 0
−12𝑉𝐷𝐶 0 0 0 0 0 0 1 0 D1,n
−13𝑉𝐷𝐶 0 1 0 0 0 0 1 0 T 2,n

−14𝑉𝐷𝐶 0 0 1 0 0 0 1 0

−15𝑉𝐷𝐶 0 1 1 0 0 0 1 0 
V 5,n T 2,n V 1,n
S 4,n S 1,n S 1,n S 3,n

V 3,n

D. Proposed Extended Module V 2,n

To minimize the number of components, a cascaded struc-
ture is developed based on the cascaded connection of BBTH
module. Fig. 4 indicates the cascaded structure of BBTH
module with 𝑛 modules.
TABLE III: Equations of Extended Module
𝑛 number of module
No. Switches 12𝑛
No. IGBTs 12𝑛
No. Diodes 14𝑛
No. DC Sources ∑𝑛 5𝑛 ∑
𝑛
TBV 8 𝑗=1 (𝑉1𝑗 + 𝑉2𝑗 ) + 6 𝑗=1 (𝑉3𝑗 + 𝑉4𝑗 )
To maintain the modulatory, each module connected in
cascade is considered to be identical with constant number
of components. This will generate the maximum quantity of
levels from the cascaded connection with a constant number
of devices. The equations of the components and 𝑇 𝐵𝑉 for
the proposed configuration with 𝑛 modules in the cascade are
expressed in Table III.
III. C OMPARISON B ETWEEN MLI S TRUCTURES
To study the behaviour of the proposal, a comparison with
other cascaded MLIs [12]–[16] is presented in this section.
The comparison includes switches count, IGBTs count, DC
S 4,n V 4,n T1,nS 2,n S 2,n S 3,n

v o ,n
D 2,n T 1,n
B
Fig. 4: The cascade arrangement of proposed structure.
supplies count, the variety of DC supplies and TBV. In this
comparison, in the proposed structure three methods of a sym-
metrical and two asymmetrical states are used to determine the
magnitudes of DC supplies. Table V gives the operation modes
of the comparison structures presented in [11]–[16]. Fig. 5
presents a comparison among the proposed MLI structure and
others. Fig. 5(a) illustrates the plot of the variation of the
levels versus the switches count for the proposal and other
cascaded MLIs. It is evident, that, in comparison with other
structures with equal number of power devices, more levels
are obtained for the proposal when methods 𝑀 2 and 𝑀 3
are considered. For example, the proposed topology generates
more than fifty-levels with fourteen switches in 𝑀 3 and other
structures generates less than forty-levels. Fig. 5(b) displays
the variation between the quantity of levels and IGBTs count
for the proposed cascaded MLI and other cascaded MLIs. The
presented cascaded MLIs in [15], [16] require two IGBTs in

3
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 ICA-ACCA 2018, October 17-19, 2018, Greater Concepción, Chile
TABLE IV: Proposed Values of DC Supplies and other Parameters
Modes Mode I (M1)
Magnitudes
DC Supplies 𝑉1𝑗 = 𝑉2𝑗 = 𝑉3𝑗 = 𝑉4𝑗 = 𝑉5𝑗 = 𝑉𝐷𝐶
for 𝑗 = 1, 2, ⋅ ⋅ ⋅ , 𝑛
Maximum Output Voltage 4𝑛𝑉𝐷𝐶
Number of Levels 8𝑛 + 1
each switch because they use bidirectional switches in their
configurations. So, a comparison has been done among the
proposed cascaded MLI and other cascaded MLIs in terms
of the number of levels versus IGBTs count. As one can
see, the produced levels with the proposed cascaded MLI
is higher than other MLIs with the same IGBTs count. The
number of DC supplies is another important criterion in whilst
designing MLIs. The variation between the number of DC
supplies required among the proposed cascaded MLI and other
MLIs is illustrated in Fig. 5(c). As the reader can see from
this figure and considering 𝑀 3, the proposed MLI generates
a higher number of levels with the same number of DC
supplies compared to other cascaded MLIs. For example the
proposed topology generates more than fifty-level with four
power supplies in 𝑀 3 and other structures generates this levels
with five DC power supplies.
The variation of DC supply magnitudes is another important
component for comparison with respect to the increase of the
cost. Fig. 5(d) illustrates the plot of the variation between
𝑁𝑣𝑎𝑟𝑖𝑡𝑦 and the number of levels presented in MLIs structures.
As can be seen from Fig. 5(d), the proposed cascaded BBTHB
in the asymmetrical case, creates more levels with lower
𝑁𝑣𝑎𝑟𝑖𝑡𝑦 than other MLIs except for the presented MLIs in R6,
R8, and R11. This component is a drawback of the proposed
cascaded MLI. Fig. 5(e) illustrates the variation TBV and
the levels among the proposed MLI and other MLIs. The
TBV’s value is not the same for the two magnitudes methods
presented MLI in [14]. But for other structures, TBV factor is
the same in the rest of the presented MLIs. According to Fig.
5(e), the proposed cascaded structure has decreased the value
of the TBV compared to other MLIs for producing the same
number of levels.
Based on presented comparison between proposed cas-
caded structure and other MLIs structures, it is clear that
the proposed cascaded structure generates more voltage levels
with less number of components such as power switches,
IGBTs and drivers circuit. In additional, the proposed structure
reduced the magnitude of TBV than other MLIs.
IV. S IMULATION R ESULTS
To depict the behavior of the BBTHB module proposed in
this paper a 61-level inverter with a cascaded two BBMHB
module connection is simulated, in this paper. For this sim-
ulation, an R-L load is considered of 150Ω and 10𝑚𝐻 with
50𝐻𝑧 output frequency, respectively. In this simulation, for the
proposed MLI for production of the gate pulse of switches,
the fundamental frequency control switching is applied be-
cause this strategy works with the fundamental frequency that
decreases the switching losses.
4
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4
Mode II (M2) Mode III (M3)
𝑉1𝑗 = 𝑉𝐷𝐶 , 𝑉1𝑗 = 31𝑗−1 𝑉𝐷𝐶 ,
𝑉2𝑗 = 2𝑉𝐷𝐶 , 𝑉2𝑗 = 2(31𝑗−1 )𝑉𝐷𝐶 ,
𝑉3𝑗 = 4𝑉𝐷𝐶 , 𝑉3𝑗 = 4(31𝑗−1 )𝑉𝐷𝐶 ,
𝑉4𝑗 = 𝑉5𝑗 = 8𝑉𝐷𝐶 𝑉4𝑗 = 𝑉5𝑗 = 8(31𝑗−1 )𝑉𝐷𝐶
15𝑛𝑉𝐷𝐶 [(31𝑛 − 1)/2]𝑉𝐷𝐶
30𝑛 + 1 31𝑛
A 61-level cascaded topology used two series BBTHB mod-
ules. The number of DC supplies and semiconductor switches
are five and twelve for each module, respectively. The method
of 𝑀 2 is chosen for the magnitudes of DC supplies. So, these
magnitudes are 𝑉1,1 = 𝑉1,2 = 50𝑉 , 𝑉2,1 = 𝑉2,2 = 100𝑉 ,
𝑉3,1 = 𝑉3,2 = 200𝑉 , 𝑉4,1 = 𝑉4,2 = 𝑉5,1 = 𝑉5,2 = 400𝑉 .
The peak of the output voltage is 1500𝑉 having a voltage step
of 50𝑉 . Figs. 6(a) and (b) illustrate the load voltage curves
of each BBTHB module for the generation of 61-levels at the
output. Fig. 6(c) indicates 61-levels curve for the proposed
cascaded MLI. Fig. 6(d) shows the load current curve of the
proposed cascaded MLI. FFT of the load voltage and current
are indicated in Figs.6(e) and (f). As can seen from these
figures, THD values are 0.64% and 0.44% for the voltage and
current of the 61-leveld cascaded MLI proposed, respectively.
V. C ONCLUSION
A new module presented for the cascaded multilevel in-
verter that was called back-to-back modified T-type half-
bridge (BBTHB) was exposed in this paper. This configuration
generates a large number of voltage levels with lower switch-
ing devices count. In addition, a cascaded connection of the
configuration is introduced which increments the value of the
voltage levels. The merits of the proposed BBTHB module
is evaluated through various comparisons with other prior
art MLI structures. The results shown by simulations, have
demonstrated the improved capability of the suggested MLI
regarding reduced switching devices count and total blocking
voltage. The operation of a 61-level cascade connection of two
modules is evaluated under MATLAB/Simulink software.
ACKNOWLEDGMENT
The authors would like to thank the financial support of
FONDECYT Regular 1160690 and 1160806 Research Projects
as well as 14-INV-097.
R EFERENCES
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[2] M. Tariq, A. I. Maswood, C. J. Gajanayake and A. K. Gupta, ”Aircraft
batteries: current trend towards more electric aircraft,” in IET Electrical
Systems in Transportation, vol. 7, no. 2, pp. 93-103, 6 2017.
[3] F. Hahn, M. Andresen, G. Buticchi, M. Liserre, “Thermal analysis and
balancing for modular multilevel converters in HVDC applications,”
IEEE Trans. Power. Electron., vol. 33, no. 3, pp. 1985-1996, March.
2018.
[4] N. Sandeep, R.Y. Udaykumar, “Design and implementation of active
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 ICA-ACCA 2018, October 17-19, 2018, Greater Concepción, Chile
5

60 60
M3 M3
50 50
R6 R11 R6
40 R2 40 R2
R8 R8
Nlevel M2 R4 Nlevel R4
R9 M2 R9
M1, R 5 M1, R5, R10
20 20

10 10
0 R10 R11
0
R1, R 3 R7 R1, R 3 R7
10  10
0 2 4 6 Nswitch 10 12 14 16 0 2 4 6 NIGBT 10 12 14 16

(a) (b)

60 400
M3 R6 M3
R6 350
50 R2 R11
R4 300 R8
R8 R4
40 R11 250 M1, R1, R3, R5, R7, R10 R2
M2 R 7, R 9 Nlevel
Nlevel R2
M1, R 5 150 M2
20 100 R9

R1, R3, R5, R10 50

10
0
0  50
0 1 2 3 NDC 5 6 7 8 0 1 2 3 N var iety 5 6 7 8

(c) (d)

350
R7
300
R8
250
R4
TSV R9

150
100
50 R1, R 2, R3, R5, R6, R10, R11

0
M3, M2, M1
 50
0 10 20 30 40 Nlevel 60 70 80 90 100

(e)
Fig. 5: Comparative studies; (a) the switches count versus 𝑁𝐿 ; (b) the IGBTs count versus 𝑁𝐿 ; (c) DC supplies count versus
𝑁𝐿 ; (d) the variety of DC supplies (Nvariety) versus 𝑁𝐿 ; (e) 𝑇 𝐵𝑉 versus 𝑁𝐿 .

TABLE V: Comparison Requirements For The Presented Cascaded MLIs Based On Their Methods
Structures Methods N𝑠𝑤𝑖𝑡𝑐ℎ N𝐼𝐺𝐵𝑇 N𝐷𝐶 N𝑣𝑎𝑟𝑖𝑒𝑡𝑦 TBV(p.u)
CHB [11] R1 2(𝑁𝐿 − 1) 2(𝑁𝐿 − 1) 1 (𝑁𝐿 − 1)/2 2(𝑁𝐿 − 1)
(𝑁 +1) (𝑁 +1) (𝑁 +1) (𝑁 +1)
R2 4[log2 𝐿 −1] 4[log2 𝐿 −1] [log2 𝐿 ] − 1 [log2 𝐿 ] − 1 2(𝑁𝐿 − 1)
(BCMLI) [12] R3 2(𝑁𝐿 − 1) 2(𝑁𝐿 − 1) (𝑁𝐿 − 1)/2 1 2(𝑁𝐿 − 1)
R4 8 log𝑁
5
𝐿
8 log𝑁5
𝐿
2 log𝑁
5
𝐿
2 log𝑁5
𝐿
3(𝑁𝐿 − 1)
(DCHB) [13] R5 3(𝑁𝐿 − 1)/2 (𝑁𝐿 − 1)/2 (𝑁𝐿 − 1)/2 1 2(𝑁𝐿 − 1)
(𝑁 +1)/2 (𝑁 +1)/2 (𝑁 +1)/2 (𝑁 +1)/2
R6 6[log3 𝐿 ] 6[log3 𝐿 ] 2[log3 𝐿 ] log3 𝐿 2(𝑁𝐿 − 1)
(BUMLI) [14] R7 6(𝑁𝐿 − 1)/5] + 3 6(𝑁𝐿 − 1)/5] + 3 3(𝑁𝐿 − 1) + 3 1 (7𝑁𝐿 − 2)/2
(𝑁 +5) (𝑁 +5) (𝑁 +5) (𝑁 +5)
R8 5[log2 𝐿 ] − 9 5[log2 𝐿 ] − 9 3[log2 𝐿 ] − 8 [log2 𝐿 ] − 2 (10𝑁𝐿 − 9)/3
(E-Type) [15] R9 3(𝑁𝐿 − 1)/2 3(𝑁𝐿 − 1)/2 (𝑁𝐿 − 1)/3 (𝑁𝐿 − 1)/6 10(𝑁𝐿 − 1)/6
(BUMLC) [16] R10 5(𝑁𝐿 − 1)/4 3(𝑁𝐿 − 1)/2 (𝑁𝐿 − 1)/2 1 2(𝑁𝐿 − 1)
R11 10 log𝑁9
𝐿
12 log𝑁9
𝐿
4 log𝑁
9
𝐿
2 log𝑁9
𝐿
2(𝑁𝐿 − 1)

5
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 ICA-ACCA 2018, October 17-19, 2018, Greater Concepción, Chile
6

First unit output voltage (v) Second unit output voltage (v)
800 800
600 600
400 400
200 200
0 0
 200  200
 400  400
 600  600
 800  800
0 0.01 0.02 0.03 0.04 0.05 0 0.01 0.02 0.03 0.04 0.05

(a) (b)

Output voltage (v) Output current (A)

1500 10
8
1000 6
4
500 2
0 0
 2
 500  4
 1000  6
 8
 1500  10
0 0.01 0.02 0.03 0.04 0.05 0 0.01 0.02 0.03 0.04 0.05

(c) (d)

(e) (f)
Fig. 6: Simulation studies; (a) output voltage curve of first module; (b) output voltage curve of second module; (c); total output
voltage curve of the 61 level proposed cascaded MLI; (d) output current curve; (e) FFT of the voltage (THDv = 0.64%); f)
FFT of the current (THDi = 0.44%).

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