Chapter 4 Sequential Lo232323

Chapter 4
Sequential Logic Circuits

14 Hours
28Marks
4.1Introduction to Sequential Logic Circuit
Logic circuits discussed previously were combinational circuits. In those

circuits output depends only on the current input combination. But in sequential
logic circuits, output of circuit depends on current input as well as past
input or past output. For achieving this, sequential logic circuits contain
memory element for storing past input or past output.
Questions:
1. Give any four differences between combinational (or combinatorial) and
sequential logic circuit. [4M]
2. Differentiate between combinational logic and sequential logic system.
[4M]
4.2.1One-bit memory cell

Memory element just discussed above, stores data (generally one bit data
is stored per element). Snapshot of a memory is called a state. One-bit memory
cell is bi-stable. It means, it has two stable internal states. Flip-flop is common
implementation of bi-stable. Therefore flip flop is also referred as basic memory
cell.
One bit memory cell stores one bit data as 0 or 1. It can be implemented
using transistors, NAND gates or NOR gates.
Figure 4.1: One-bit memory cell using NAND gates
Table 4.1: Truth Table for One-bit memory cell (NAND implementation)
Input Output
S R
0 0 Race
(both 1)
0 1 0 1
1 0 1 0
1 1
4-1
Figure 4.2: One-bit memory cell using NOR gates
Table 4.2: Truth Table for One-bit memory cell (NOR implementation)
Input Output
S R
0 0
0 1 0 1
1 0 1 0
1 1 Race (both 0)
The above one-bit memory cell is also referred as SR flip flop or RS flip
flop. S input (Set) is used for setting the flip flop (i.e. to get output as 1). R input
(Reset) is used for resetting the flip flop (i.e. to get output as 0).
Questions:
3. Draw 1-bit memory cell using NAND gate. [2M]
4. Draw 1-bit memory cell using NOR gate. [2M]
5. Why a flip-flop is called a basic memory cell? [2M]
4.2.2Clock signal and Triggering Methods

Clock signal is a digital signal. Which is generally fed to every sequential
circuit. A sample clock signal is drawn below.
Level 1 (HIGH)
Positive Negative
Edge Edge
Level 0 (LOW)
Figure 4.3: Clock signal

Clock signal is a digital signal which has only two levels as level 0 and
level 1. Level 0 is also referred as LOW, FALSE, negative or OFFlevel. Level
1 is also referred as HIGH, TRUE, positive or ONlevel. The edge which
changes the level from level 0 to level 1 is referred as positive edge,rising
edge, leading edge or LOW-to-HIGH edge. The edge which changes the level
from level 1 to level 0 is referred as negative edge,falling edge, trailing edge
orHIGH-to-LOW edge.
4-2
Triggering is the process of activating the circuit for generating the
output. Triggering can be broadly classified in two categories as,
- Level triggering
- Edge triggering
In level triggering, the circuit is triggered at a level. There are two

types of level triggering. If circuit gets triggered at level 1 (i.e. Circuit generates
output at level 1 of clock signal), it is called level 1 triggering,HIGH level
triggering or positive level triggering. If circuit gets triggered at level 0 (i.e.
Circuit generates output at level 0 of clock signal), it is called level 0
triggering,LOW level triggering or negative level triggering.
In edge triggering, the circuit is triggered on an edge. There are two
types of edge triggering. If circuit gets triggered on positive edge (i.e. Circuit
generates output on rising edging of clock signal), it is called positive edge
triggering or rising edge triggering. If circuit gets triggered on negative
edge (i.e. Circuit generates output on falling edge of clock signal), it is called
negative edge triggering or falling edge triggering.
Questions:
1. Draw clock signal. Explain various triggering methods. [4M]
2. Name the types of triggering that can be used for clocking a flip flop. [2M]
3. Explain positive edge triggering and negative edge triggering. [4M]
4. Enlist triggering methods and explain one of them. [4M]
5. Describe different types of triggering methods for a flip-flop. [4M]
6. Explain the types of triggering methods. [4M]
4.3 Flip flops
Logic gate was the most basic building block of a combinational circuit. In
sequential circuit, flip-flop is the most basic building block.Flip flop is a bi-stable
circuit. It means, it has two stable internal states. Both the output states and
are stable. Circuit remains in a particular output state indefinitely until
something is done to change it.
Various types of flip-flops are
- SR Flip flop
- JK Flip flop
- T Flip flop
- D Flip flop
4.3.1SR Flip Flop or RS Flip Flop

Implementation of a SR flip flop using NAND gates is shown in figure 4.4.
Symbol of SR flip flop is shown in figure 4.5.
4-3
Figure 4.4: Implementation of SR Flip Flop using NAND gates
SR
Flip Flop
Figure 4.5: Symbol of SR Flip Flop
When S=0 and R=0

As S is 0 and R is 0, after inversion one input of both NAND gates is 1. So
outputs of these NAND gates are inversion of other inputs. So output of upper
NAND gate remains (as inversion of ) and output of lower NAND gate
remains (as inversion of ). So output remains unchanged.
When S=0 and R=1

As R is 1, after inversion one input of lower NAND gate is 0 which results
in generating output 1 for the lower NAND gate. i.e. becomes 1. As S is 0,
after inversion one input of upper NAND gate is 1. Other input of this NAND
gate is also 1 (as is 1). So the output of upper NAND gate i.e. becomes 0.
Both the outputs remain stable as 0 and 1.i.e. flip flop is reset.
When S=1 and R=0

As S is 1,after inversion one input of upper NAND gate is 0 which results
in generating output 1 for the upper NAND gate. i.e. becomes 1. As R is 0, after
inversion one input of lower NAND gate is 1. Other input of this NAND gate is
also 1 (as is 1). So the output of lower NAND gate i.e. becomes 0. Both the
outputs remain stable as 1 and 0.i.e. flip flop is set.
When S=1 and R=1

As S is 1 R is 1, after inversion one input of both NAND gates is 0. So
both the NAND gates try to generate output as 1, which is race between and
. This is forbidden state.
Truth table of SR flip flop is shown below.
4-4
Table 4.3: Truth Table for SR Flip Flop
Input Output
S R
0 0
0 1 0
1 0 1
1 1 Forbidden
4.3.1.1 Clocked SR Flip Flop

As discussed in 4.2.2, clock is fed to every sequential circuit. So, a
clocked SR flip flop can be implemented using NAND gates as shown below.
1
3
4
2
Figure 4.6: Implementation of clocked SR Flip Flop
Symbol of clocked SR flip flop is shown below. It is positive triggered SR

flip flop.
SR
Flip Flop
Figure 4.7: Symbol of clocked SR Flip Flop
When Clk=0, S=X and R= X

Output of NAND gates 1 and 2 are always 1 regardless of value of S and
R. As one input of NAND gates 3 and 4 are always 1, outputs of these NAND
gates are inversion of other inputs. So output of NAND gate 3 remains (as
inversion of ) and output of NAND gate 4 remains (as inversion of ). So
output remains unchanged regardless of values of S and R. i.e. Flip flop is not
triggered.
When Clk=1
As one input of NAND gates 1 and 2 are always 1, outputs of these NAND
gates are inversion of other inputs. i.e. Circuit responds to values of S and R.
Here NAND gates 1 and 2 work as NOT gates.
4-5
When Clk=1, S=0 and R=0
As both S and R are 0, output of NAND gates 1 and2becomes 1. So, one
input of NAND gates 3 and 4 are always 1, outputs of these NAND gates are
inversion of other inputs. So output of NAND gate 3 remains (as inversion of
) and output of NAND gate 4 remains (as inversion of ). So output remains
unchanged.

As R is 1, output of NAND gate 2 is0. As one input of NAND gate 4 is 0,
its output is 1. Therefore becomes 1. As S is 0, output of NAND gate 1 becomes
1. So both the inputs of NAND gate 3 are 1, resulting in output as 0. Therefore
becomes 0. Both the outputs remain stable as 0 and 1. i.e. flip flop is reset.

As S is 1, output of NAND gate 1 is 0. As one input of NAND gate 3 is 0,
its output is 1. Therefore becomes 1. As R is 0, output of NAND gate 2
becomes 1. So both the inputs of NAND gate 4 are 1, resulting in output as 0.
Therefore becomes 0. Both the outputs remain stable as 1 and 0. i.e. flip flop is
set.

As S is 1, output of NAND gate 1 is 0. As one input of NAND gate 3 is 0,
its output is 1. Therefore becomes 1. As R is 1, output of NAND gate 2 is 0. As
one input of NAND gate 4 is 0, its output is 1. Therefore becomes 1. Here both
and tries to become 1. That there is a race between and . This is
forbidden state.
Truth table of clocked (positive level triggered) SR flip flop is shown

below.
Table 4.3: Truth Table for clocked SR Flip Flop
Input Output
Clk S R
0 X X No change
1 0 0
1 0 1 0
1 1 0 1
1 1 1 Forbidden
4.3.1.2Clocked SR Flip Flop with Preset and Clear inputs

Flip flops generally have two additional inputs as Preset and Clear.
Preset input is used to preset the flip flop to 1. i.e. to 1.Whereas clear input is
used to clear the flip flop to 0. i.e. to 0. Both the Preset and Clear inputs are
active low (i.e. active when low). Aclocked SR flip flop with preset and
clear inputs can be implemented using NAND gates as shown below.
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1 3
2 4
Figure 4.8: Implementation of clocked SR Flip Flop with Preset & Clear
Symbol of clocked SR flip flop with Preset and Clear inputs is shown
below.
SR
Flip Flop
Figure 4.9: Symbol of clocked SR Flip Flop with Preset & Clear
When Pr=0, Cr=0, Clk=X, S=X and R= X

As Pr is 0, one of the input of NAND gate 3 becomes 0. So output of
NAND gate 3 becomes 1. i.e. becomes 1 regardless of all other inputs. As Cr is
0, one of the input of NAND gate 4 becomes 0. So output of NAND gate 4
becomes 1. i.e. becomes 1 regardless of all other inputs. This should never
happen. So this input combination is not allowed.
As Pr is 0, one of the input of NAND gate 3 becomes 0. So output of
NAND gate 3 becomes 1. i.e. becomes 1 regardless of all other inputs. So flip
flop is preset. Here becomes 0.
As Cr is 0, one of the input of NAND gate 4 becomes 0. So output of
NAND gate 4 becomes 1. i.e. becomes 1 regardless of all other inputs. Here
becomes 0. So flip flop is clear.
When Pr=1, Cr=1
For the values of Pr and Cr as 1, flip flop works same as normal clocked
SR flip flop which is already discussed in 4.3.1.1.
4-7
Truth table of clocked (positive level triggered) SR flip flop with Preset
and Clear inputs is shown below.
Table 4.4: Truth Table for clocked SR Flip Flop with Pr& Cr
Input Output
Pr Cr Clk S R
0 0 Not used
0 1 X X X 1
1 0 X X X 0
1 1 0 X X No change
1 1 1 0 0
1 1 1 0 1 0
1 1 1 1 0 1
1 1 1 1 1 Forbidden
4.3.1.3 SR Flip Flop with different triggering methods

For flip flop to be triggered it should be clocked. Various types of SR flip
flops on the basis of triggering methods are
- Positive level triggered SR flip flop
- Negative level triggered SR flip flop
- Positive edge triggered SR flip flop
- Negative edge triggered SR flip flop
Symbols and truth tables of these flip flops are given below.
SR
Flip Flop
Figure 4.10: Symbol of Positive level triggered SR Flip Flop
Table 4.5: Truth Table for Positive level triggered SR Flip Flop
Input Output
Clk S R
0 X X No change
1 0 0
1 0 1 0
1 1 0 1
1 1 1 Forbidden
4-8
SR
Flip Flop
Figure 4.11: Symbol of Negative level triggered SR Flip Flop
Table 4.6: Truth Table for Negative level triggered SR Flip Flop
Input Output
Clk S R
1 X X No change
0 0 0
0 0 1 0
0 1 0 1
0 1 1 Forbidden
SR
Flip Flop
Figure 4.12: Symbol of Positive edge triggered SR Flip Flop
Table 4.7: Truth Table for Positive edge triggered SR Flip Flop
Input Output
Clk S R
Other X X No change
 0 0
 0 1 0
 1 0 1
 1 1 Forbidden
4-9
SR
Flip Flop
Figure 4.13: Symbol of Negative edge triggered SR Flip Flop
Table 4.8: Truth Table for Negative edge triggered SR Flip Flop
Input Output
Clk S R
Other X X No change
 0 0
 0 1 0
 1 0 1
 1 1 Forbidden
4.3.2JK Flip Flop

As seen in above discussion, in all versions of SR flip flops there is one
forbidden input combination. This is the main drawback of SR flip flop. This
limitation of SR flip flop is overcome in JK flip flop. Implementation of JK flip
flop is shown below. This implementation is of positive level triggered JK flip
flop with preset and clear inputs.
1 3
2 4
Figure 4.14: Implementation of clocked JK Flip Flop with Preset & Clear
Symbol of JK flip flop is shown below.
4-10
JK
Flip Flop
Figure 4.15: Symbol of clocked JK Flip Flop with Preset & Clear
Preset input, Clear input and Clock input work same as that of SR flip
flop. So they are not discussed here.
When J=0 and K=0

As J and K are 0, one input of NAND gates 1 and 2 are 0. So outputs of
these NAND gates is 1. S is 0 and R is 0, after inversion one input of both
NAND gates is 1. As preset and clear are also 1, two inputs of NAND gates 3
and 4 are 1. So outputs of these NAND gates are inversion of remaining input.
So output of NAND gate 3 remains (as inversion of ) and output of NAND
gate 4 remains (as inversion of ). So output remains unchanged.
When J=0 and K=1

As K is 1, two inputs (i.e. K and Clk) of NAND gate 2 are 1. So output of
this gate will be inversion of its third input which is . Now may be either 0 or
1.
If is 0, output of NAND gate 2 will be1. For NAND gate 4 inputs will be
1 (as output of NAND gate 2), 1 (Cr) and 0 ( ). So output of NAND gate 4 will be
1. i.e. will be 1.
If is 1, output of NAND gate 2 will be 0. For NAND gate 4 inputs will be
0 (as output of NAND gate 2), 1 (Cr) and 1 ( ). So output of NAND gate 4 will be
1. i.e. will be 1.
So, regardless of value of the output of NAND gate 4 i.e. will be 1.
As J is 0, one input of NAND gates 1 is 0. So output of NAND gate 1 is 1.
For NAND gate 3 inputs will be 1 (as output of NAND gate 1), 1 (Pr) and 1 ( ).
So output of NAND gate 3 will be 0. i.e. will be 0.
Thus, remains 0 and remains 1. Both the outputs remain stable as 0
and 1. i.e. flip flop is reset.
When J=1 and K=0

As J is 1, two inputs (i.e. J and Clk) of NAND gate 1 are 1. So output of
this gate will be inversion of its third input which is . Now may be either 0 or
1.
4-11
1 (as output of NAND gate 1), 1 (Pr) and 0 ( ). So output of NAND gate 3 will be
1. i.e. will be 1.
0 (as output of NAND gate 1), 1 (Pr) and 1 ( ). So output of NAND gate 3 will be
1. i.e. will be 1.
So, regardless of value of the output of NAND gate 3 i.e. will be 1.
As K is 0, one input of NAND gates 2 is 0. So output of NAND gate 2 is 1.
For NAND gate 4 inputs will be 1 (as output of NAND gate 1), 1 (Cr) and 1 ( ).
So output of NAND gate 4 will be 0. i.e. will be 0.
Thus, remains 1 and remains 0. Both the outputs remain stable as 1
and 0. i.e. flip flop is set.
When J=1 and K=1

As J is 1 and K is 1, the output of JK flip flop toggles between and .
Truth table of JK flip flop with Preset and Clear inputs is shown below.
Table 4.9: Truth Table for clocked JK Flip Flop with Pr& Cr
Input Output
Pr Cr Clk J K
0 0 Not used
0 1 X X X 1
1 0 X X X 0
1 1 0 X X No change
1 1 1 0 0
1 1 1 0 1 0
1 1 1 1 0 1
1 1 1 1 1 (Toggle)
4.3.2.1 Race around condition in JK flip flop

JK flip flop overcomes the limitation of SR flip flop (which was not
handling the combination of S=1 and R=1). In JK flip flop, when J=1 and K=1,
the output of JK flip flop toggles between and . But in case of a level
triggered JK flip flop like one seen above, it creates a problem.
Let us assume a positive level triggered JK flip flop. This flip flop get
triggered on the positive level. If J=1 and K=1, = . This output is toggled
whenever clock is at HIGH level (i.e. 1). But if width of a clock pulse is greater
than propagation delay (discussed in 1.2.1.1) of the circuit, output state at the
end of HIGH level is not reliable as illustrated in the figures4.16 and 4.17 below.
4-12
Clock
Signal
Output State Here, at the end of

when = 1 and positive level of clock
=1 pulse, = 1
Figure 4.16: Sample (Sample 1) output pulse when J=K=1
Clock
Signal
Output State Here, at the end of

when = 1 and positive level of clock
=1 pulse, = 0
Figure 4.17: Sample (Sample 2) output pulse when J=K=1
This uncertainty in the output state when J=K=1 is called as race-

around condition of JK flip flop. It can be avoided by various ways as
1) Keeping the width of clock pulse smaller than propagation delay of the
circuit (difficult solution).
2) Using edge-triggered JK flip flop instead of level triggered JK flip flop.
3) Using Master-Slave JK flip flop (Discussed in 4.3.2.2).
4.3.2.2Master Slave JK Flip Flop

For avoiding race around condition in JK flip flop, Master Slave JK flip
flop is used. The implementation of Master Slave JK flip flop using two SR flip
flops is shown in following figure.
4-13
Slave SR
Master SR
Flip Flop
Flip Flop
Figure 4.18: Master Slave JK Flip Flop using two SR Flip Flops
Here two SR flip flops are used. First SR flip flop works as master and
second SR flip flop works as slave. Master SR flip flop controls the operation of
slave SR flip flop. A clock is provided to master flip flop and the same clock is
provided to slave flip flop but through a NOT gate. Therefore, when master flip
flop is enabled, slave flip flop is disables and vice-a-versa. So output is not
propagated immediately. Rather it is propagated at the end of a complete clock
pulse. This results in avoidance of race around condition.
Symbol of MS JK flip flop is shown below.
MS JK
Flip Flop
Figure 4.19: Symbol of MS JK Flip Flop
Truth table of MS JK flip flop is shown below.
4-14
Table 4.10: Truth Table for MS JK Flip Flop with Pr& Cr
Input Output
Pr Cr Clk J K
0 0 Not used
0 1 X X X 1
1 0 X X X 0
1 1 0 X X No change
1 1 1 0 0
1 1 1 0 1 0
1 1 1 1 0 1
1 1 1 1 1 (Toggle)
4.3.2.3JK Flip Flop with different triggering methods

Various types of JK flip flops on the basis of triggering methods are
- Positive level triggered JK flip flop
- Negative level triggered JK flip flop
- Positive edge triggered JK flip flop
- Negative edge triggered JK flip flop
JK
Flip Flop
Figure 4.20: Symbol of Positive level triggered JK Flip Flop
Table 4.11: Truth Table for Positive level triggered JK Flip Flop
Input Output
Clk J K
0 X X No change
1 0 0
1 0 1 0
1 1 0 1
1 1 1
4-15
JK
Flip Flop
Figure 4.21: Symbol of Negative level triggered JK Flip Flop
Table 4.12: Truth Table for Negative level triggered JK Flip Flop
Input Output
Clk J K
1 X X No change
0 0 0
0 0 1 0
0 1 0 1
0 1 1
JK
Flip Flop
Figure 4.22: Symbol of Positive edge triggered JK Flip Flop
Table 4.13: Truth Table for Positive edge triggered JK Flip Flop
Input Output
Clk J K
Other X X No change
 0 0
 0 1 0
 1 0 1
 1 1
4-16
JK
Flip Flop
Figure 4.23: Symbol of Negative edge triggered JK Flip Flop
Table 4.14: Truth Table for Negative edge triggered JK Flip Flop
Input Output
Clk J K
Other X X No change
 0 0
 0 1 0
 1 0 1
 1 1
4.3.3T Flip Flop

It is also called as Toggle flip flop. Its output changes its state each time
when it is triggered and T input is 1. We can implement T flip flop using JK flip
flop as shown below.
JK
Flip Flop
Figure 4.24: Implementation of T Flip Flop using JK Flip Flop
Symbol of T flip flop is shown below
4-17
T
Flip Flop
Figure 4.25: Symbol of T Flip Flop
Truth table of T flip flop is given below.
Table 4.15: Truth Table for T Flip Flop

Input Output
T
0 (No change)
1 (Toggle)
4.3.3.1T Flip Flop with different triggering methods

Various types of T flip flops on the basis of triggering methods are
- Positive level triggered T flip flop
- Negative level triggered T flip flop
- Positive edge triggered T flip flop
- Negative edge triggered T flip flop
T
Flip Flop
Figure 4.26: Symbol of positive level triggered T Flip Flop
4-18
Table 4.16: Truth Table for positive level triggered T Flip Flop
Input Output
Clock T
Other X No change
1 0 (No change)
1 1 (Toggle)
T
Flip Flop
Figure 4.27: Symbol of negative level triggered T Flip Flop
Table 4.17: Truth Table for negative level triggered T Flip Flop
Input Output
Clock T
Other X No change
0 0 (No change)
0 1 (Toggle)
T
Flip Flop
Figure 4.28: Symbol of positive edge triggered T Flip Flop
4-19
Table 4.18: Truth Table for positive edge triggered T Flip Flop
Input Output
Clock T
Other X No change
 0 (No change)
 1 (Toggle)
T
Flip Flop
Figure 4.29: Symbol of negative edge triggered T Flip Flop
Table 4.19: Truth Table for negative edge triggered T Flip Flop
Input Output
Clock T
Other X No change
 0 (No change)
 1 (Toggle)
4.3.4D Flip Flop or Delay Flip Flop

It is also called as Delay flip flop. Its output generates the output state
same as its D input each time when it is triggered. i.e. It delays the provided
input. It is used as a memory latch for storing a bit in it. We can implement D
flip flop using SR flip flop as shown below.
4-20
SR
Flip Flop
Figure 4.30: Implementation of D Flip Flop using SR Flip Flop
D flip can also be implemented using JK flip flop. This implementation is

shown below.
JK
Flip Flop
Figure 4.31: Implementation of D Flip Flop using JK Flip Flop
Symbol of D flip flop is shown below
D
Flip Flop
Figure 4.32: Symbol of D Flip Flop

4-21
Truth table of D flip flop is given below.
Table 4.20: Truth Table for D Flip Flop

Input Output
D
0 0
1 1
4.3.4.1D Flip Flop with different triggering methods

Various types of D flip flops on the basis of triggering methods are
- Positive level triggered D flip flop
- Negative level triggered D flip flop
- Positive edge triggered D flip flop
- Negative edge triggered D flip flop
D
Flip Flop
Figure 4.33: Symbol of positive level triggered D Flip Flop
Table 4.21: Truth Table for positive level triggered D Flip Flop
Input Output
Clock D
Other X No change
1 0 0
1 1 1
4-22
D
Flip Flop
Figure 4.34: Symbol of negative level triggered D Flip Flop
Table 4.22: Truth Table for negative level triggered D Flip Flop
Input Output
Clock D
Other X 0
0 0 1
0 1 (Toggle)
D
Flip Flop
Figure 4.35: Symbol of positive edge triggered D Flip Flop
Table 4.23: Truth Table for positive edge triggered D Flip Flop
Input Output
Clock D
Other X No change
 0 0
 1 1
4-23
D
Flip Flop
Figure 4.36: Symbol of negative edge triggered D Flip Flop
Table 4.24: Truth Table for negative edge triggered D Flip Flop
Input Output
Clock D
Other X No change
 0 0
 1 1
Questions:
1. State different applications of flip-flops. [4M]
2. Explain clocked SR flip flop using NAND gate. [4M]
3. Draw clocked SR flip flop. [2M]
4. Draw logic circuit diagram of clocked RS flip flop using NAND gates and
draw the truth table. [4M]
5. Explain function of ‘preset’ and ‘clear’ inputs in Flip-flops. [4M]
6. Draw symbol and truth table of JK flip flop. [2M]
7. Draw logic diagram of JK flip flop and write its truth table. [4M]
8. State function of “Preset” and “Clear” terminals in a JK flip flop. [4M]
9. Give significance of “Preset” and “Clear” terminals in a JK flip flop. [4M]
10. Show logic circuit of JK Flip flop using NAND gates only. Explain its
working with truth table. [4M]
11. Draw neat circuit diagram of clocked JK Flip-flop using NAND gates.
Give its truth table explain race-around condition. [4M]
12. Explain race around condition with respect to JK flip flop. [4M]
13. What is race around condition? How to eliminate it? [4M]
14. What is race around condition? How can it be avoided? [4M]
15. Draw and explain master slave flip flop. [4M]
16. Draw and explain MS-JK flip flop. [4M]
17. List different types of flip flops. Draw diagram of master slave JK flip flop.
18. Convert SR flip flop into D flip flop and explain. [4M]
19. Draw symbol and truth table of negative edge triggered T flip flop and
positive edge triggered D flip flop. [2M]
20. With the help of suitable diagram explain how do you convert JK flip flop
into T flip flop and D flip flop. [4M]
4-24
21. Draw symbol and truth table of T and D flip flop. [4M]
22. Draw logic diagram of D flip flop and write its truth table. [4M]
23. Draw symbol and truth table for following flip-flops.
a. Clocked SR flip flop.
b. JK flip flop.
c. D filp flop.
d. T flip flop.
24. Draw symbol and truth table of T flip flop for negative edge triggered.
[4M]
25. Draw and explain D flip flop using SR flip flop. Also draw truth table.
[4M]
4.4 Applications of Flip flops
Flip flops have large set of applications as they are the basic building
blocks in all the sequential circuits. Major applications of Flip flops are
- Memories (data storage)
- Counters
o Synchronous Counters
o Asynchronous Counters
o Up Counters
o Down Counters
o Mod-N Counters
- Shift Registers
o Serial In Serial Out Shift Registers
o Serial In Parallel Out Shift Registers
o Parallel In Parallel Out Shift Registers
o Parallel In Serial Out Shift Registers
o Ring Counters
o Johnson Counters
- Delay Elements
- Frequency Division
- Data Transfer
4.4.1Counters
Counter is a sequential logic circuit. It is cascaded arrangement of more
than one flip flop with or without some combinational logic devices. It is
basically used for counting applications like.
- Counting objects on conveyors.
- Counting incoming and outgoing vehicles.
- Counting numbers of papers in printing.
- Filling fixed number of tablets in a bottle.
For designing counters either JK flip flops or T flip flops are used. While
using JK flip flops, J and K inputs are to be shortened (i.e. JK flip flop is to be
used as T flip flop).
Counters can be broadly classified in two categories as

- Asynchronous Counters
- Synchronous Counters
4-25
These types are discussed later on.
4.4.1.1Modulus of a counter
Modulus of a counter is number of different states it goes through before
coming back to initial state. i.e. number of states that a counter counts is called
as modulus of counter.
Example 1:
If a counter counts from 0 to 7 (as 0, 1, 2, 3, 4, 5, 6, 7), then this
counter has modulus 8 and it is said to be a mod-8 counter.
Example 2:
If a counter counts from 0 to 5 (as 0, 1, 2, 3, 4, 5), then this counter
has modulus 6 and it is said to be a mod-6 counter.
4.4.1.2Asynchronous counter
Asynchronous counter is also called as ripple counter or serial
counter.In this type of counter, clock pulse is applied to only first flip flop.
Output of first flip flop drives clock input of second flip flop and so on. The
counter is called asynchronous as the clock pulses of all the flip flops are not
same. Due to this all the flip flops do not change their states at the same time.
Second flip flop can change the state only after change in the state of first flip
flop. So these counters have high propagation delay. Hence the operational
frequency is low. Advantage of this type of counter is that it is easy to design.
4.4.1.2.1 Steps for designing asynchronous counter or ripple counter

Fordesigning a n-bit asynchronous counter or ripple counter, following
steps are undertaken.
i. It requires n number of flip flops. The flip flops used may be either
JK flip flop or T flip flop.
ii. Preset and Clear inputs (i.e. Pr and Cr inputs) of all the n flip flops
are connected to logic 1 (or VCC) so that all the flip flops work
properly.
iii. When JK flip flops are used, J and K input of all the n flip flops are
connected to each other and then to logic 1 (or VCC). When T flip
flops are used, T inputs of all the n flip flops are connected to logic
1 (or VCC). Due to this, all the n flip flops always toggle their output
state at each trigger (i.e. output state of each flip flop gives the
negation of previous state on trigger).
iv. External clock pulse is connected to flip flop number 0 (i.e. first flip
flop). Output of first flip flop (i.e. ) is connected to clock input of
flip flop number 1 (i.e. second flip flop). Output of second flip flop
(i.e. ) is connected to clock input of flip flop number 2 (i.e. third
flip flop) and so on.
v. Output of the counter is observed at (LSB), , …, ( )
which are output states of flip flops 0, 1, …, n-1 respectively.
4.4.1.2.2Two bit asynchronous counter or 2-bit ripple counter

For designing 2-bit asynchronous counter (or 2-bit ripple counter or 2-bit
serial counter) 2 JK flip flops or 2 T flip flops are used.Preset and Clear inputs
(i.e. Pr and Cr inputs) of both flip flops are connected to logic 1 (or V CC) so that
4-26
both flip flops work properly. Following two figures show design of 2-bit
asynchronous counter using JK flip flop and using T flip flop respectively. While
implementing this counter using JK flip flop, J and K inputs of both flip flops
are connected to each other and then to logic 1 (or VCC).While implementing this
counter using T flip flop, T input of both flip flops is connected to logic 1 (or V CC).
So, flip flops work in toggle mode. External clock pulse is connected to flip flop
number 0 (i.e. first flip flop). Output of first flip flop (i.e. ) is connected to clock
input of flip flop number 1 (i.e. second flip flop).
Output of this counter is observed at (LSB) and (MSB) which are
output states of flip flop 0 and flip flop 1respectively.
4-27
Following timing diagram illustrates how the flip flops in the above
designs change their state along with the external clock pulse applied to flip flop
0. As the flip flops used are negative edge triggered, output changes on negative
edge of clock pulse.
Timing diagram
Following truth table shows the state transitions in the counter. It shows
how the counter counts from 0 (00) to 3 (11). After state 3 (11), counter again
switches to 0 (00). i.e. it repeatedly counts as 0, 1, 2, 3, 0, 1, and so on.
Truth Table
4.4.1.2.3Three bit asynchronous counter or 3-bit ripple counter

serial counter) 3 JK flip flops or 3 T flip flops are used. Preset and Clear inputs
(i.e. Pr and Cr inputs) of all the three flip flops are connected to logic 1 (or V CC)
so that these flip flops work properly. Following two figures show design of 3-bit
implementing this counter using JK flip flop, J and K inputs of all the three flip
flops are connected to each other and then to logic 1 (or VCC). While
implementing this counter using T flip flop, T input of all the three flip flops is
connected to logic 1 (or VCC). So, flip flops work in toggle mode. External clock
pulse is connected to flip flop number 0 (i.e. first flip flop). Output of first flip
flop (i.e. ) is connected to clock input of flip flop number 1 (i.e. second flip flop).
Output of second flip flop (i.e. ) is connected to clock input of flip flop number
2 (i.e. third flip flop).
Output of this counter is observed at (LSB), and (MSB) which are
output states of flip flop 0, flip flop 1 and flip flop 2 respectively.
Design using JK flip flop
4-28
Design using T flip flop
Timing diagram
how the counter counts from 0 (000) to 7 (111). After state 7 (111), counter again
switches to 0 (000). i.e. it repeatedly counts as 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, and so on.
Truth Table
4.4.1.2.4Four bit asynchronous counter or 4-bit ripple counter

serial counter) 4 JK flip flops or 4 T flip flops are used. Preset and Clear inputs
(i.e. Pr and Cr inputs) of all the four flip flops are connected to logic 1 (or V CC) so
that these flip flops work properly. Following two figures show design of 4-bit
implementing this counter using JK flip flop, J and K inputs of all the four flip
flops are connected to each other and then to logic 1 (or VCC). While
implementing this counter using T flip flop, T input of all the four flip flops is
connected to logic 1 (or VCC). So, flip flops work in toggle mode. External clock
Output of second flip flop (i.e. ) is connected to clock input of flip flop number
2 (i.e. third flip flop). Output of third flip flop (i.e. ) is connected to clock input
of flip flop number 3 (i.e. fourth flip flop).
Output of this counter is observed at (LSB), , and (MSB) which
are output states of flip flop 0, flip flop 1, flip flop 2 and flip flop 3 respectively.
Timing diagram
how the counter counts from 0 (0000) to 15 (1111). After state 15 (1111), counter
again switches to 0 (0000). i.e. it repeatedly counts as 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
10, 11, 12, 13, 14, 15, 0, 1, and so on.
4-29
Truth Table
4.4.1.2.5Steps for designing mod-N counter

Mod-N counter can also be called as mod-N asynchronous counter or mod-
N ripple counter or mod-N serial counter. For designing a mod-N counter,
following steps are undertaken.
i. Number of flip flops (i.e. n) required for designing mod-N
counter can be selected as follows. Number of flip flops (i.e. n)
should be the smallest number, for which ≤ .
Example 1: For mod-5 counter
N=5
If n=1, 2n is 2. Here, N is not less than or equal to 2n.
If n=3, 2n is 8. Here, N is less than 2n.
 3 flip flops are required for designing mod-5 counter.

N=10

N=8
If n=3, 2n is 8. Here, N is equal to 2n.
3 flip flops are required for designing mod-8 counter.
ii. Preset inputs (i.e. Pr input) of all the n flip flops are connected to
logic 1 (or VCC).
iii. When JK flip flops are used, J and K input of all the n flip flops are
connected to each other and then to logic 1 (or VCC). When T flip flops
are used, T inputs of all the n flip flops are connected to logic 1 (or
VCC). Due to this, all the n flip flops always toggle their output state at
each trigger (i.e. output state of each flip flop gives the negation of
previous state on trigger).
iv. External clock pulse is connected to flip flop number 0 (i.e. first flip
flop). Output of first flip flop (i.e. ) is connected to clock input of flip
flop number 1 (i.e. second flip flop). Output of second flip flop (i.e. )
is connected to clock input of flip flop number 2 (i.e. third flip flop) and
so on.
v. Calculate binary equivalent of N. Respective output states for
which the bits in the binary equivalent are 1, are connected to
inputs of NAND gate. Output of this NAND gate is connected to
Clear inputs (Cr inputs) of all the flip flops. But if = , no
need of NAND gate as the counter is in its full form.
4-30
N = 6 = 110
1 1 0
Bit # 2 1 0
So outputs and are connected to inputs of NAND gate
and output of NAND gate is connected to Clear inputs (Cr inputs)
of all the 3 flip flops.

N = 11 = 1011
1 0 1 1
Bit # 3 2 1 0
So outputs , and are connected to inputs of NAND
gate and output of NAND gate is connected to Clear inputs (Cr
inputs) of all the 4 flip flops.

As = 2 , no need of NAND gate as the counter is in its full
form.
vi. Output of the counter is observed at (LSB), , …, ( ) which

are output states of flip flops 0, 1, …, n-1 respectively.
Some examples are discussed below. But scope of the topic is not limited
to only these counters. We should be able to design any mod-N counter by using
above steps.
4.4.1.2.6Mod-3 counter
It is also called mod-3 ripple counter, or mod-3 asynchronous counter or
mod 3 serial counter.
Here, N=3
So, 2 JK flip flops or 2 T flip flops are used. Preset input (i.e. Prinput) of
both the flip flops are connected to logic 1 (or VCC). Following two figures show
design of 2-bit asynchronous counter using JK flip flop and using T flip flop
respectively. While implementing this counter using JK flip flop, J and K inputs
of both the flip flops are connected to each other and then to logic 1 (or V CC).
While implementing this counter using T flip flop, T input of both the flip flops
is connected to logic 1 (or VCC). So, flip flops work in toggle mode. External clock
Binary equivalent of N = 3 is 11. So outputs and are connected to
inputs of NAND gate and output of NAND gate is connected to Clear inputs (Cr
inputs) of both flip flops. Due to this modification, 2-bit asynchronous counter is
converted into mod-3 counter.
Output of this counter is observed at (LSB) and (MSB) which are
output states of flip flop 0 and flip flop 1 respectively.
4-31
Timing diagram
how the counter counts from 0 (00) to 2 (01). After state 2 (01), counter is in
state 3 (i.e. 11). But as and are 1, output of NAND gate is 0 which
immediately clears both flip flops. So instead of state 3 (i.e. 11), we get state 0
(i.e. 00). So, counter repeatedly counts as 0, 1, 2, 0, 1, 2, 0and so on.
Truth Table
mod-5 serial counter.
Here, N=5
If n=2, 2n is 4. Here, is not less than or equal to 2n.
So, 3 JK flip flops or 3 T flip flops are used. Preset input (i.e. Pr input) of
all the three flip flops are connected to logic 1 (or VCC). Following two figures
show design of 3-bit asynchronous counter using JK flip flop and using T flip
flop respectively. While implementing this counter using JK flip flop, J and K
inputs of all the three flip flops are connected to each other and then to logic 1
(or VCC). While implementing this counter using T flip flop, T input of all the
three flip flops is connected to logic 1 (or VCC). So, flip flops work in toggle mode.
External clock pulse is connected to flip flop number 0 (i.e. first flip flop). Output
of first flip flop (i.e. ) is connected to clock input of flip flop number 1 (i.e.
second flip flop) and output of second flip flop (i.e. ) is connected to clock input
of flip flop number 2 (i.e. third flip flop).
inputs) of all the three flip flops. Due to this modification, 3-bit asynchronous
counter is converted into mod-5 counter.
Output of this counter is observed at (LSB), and (MSB) which
are output states of flip flop 0, flip flop 1 and flip flop 2 respectively.
4-32
Timing diagram
how the counter counts from 0 (000) to 4 (100). After state 4 (100), counter is in
state 5 (i.e. 101). But as and are 1, output of NAND gate is 0 which
immediately clears all the flip flops. So instead of state 5 (i.e. 101), we get 0 (i.e.
000). So, counter repeatedly counts as 0, 1, 2, 3, 4, 0, 1and so on.
Truth Table
mod-10 serial counter.
Here, N=10
So, 4 JK flip flops or 4 T flip flops are used. Preset input (i.e. Pr input) of
all the four flip flops are connected to logic 1 (or VCC). Following two figures
show design of 4-bit asynchronous counter using JK flip flop and using T flip
flop respectively. While implementing this counter using JK flip flop, J and K
inputs of all the four flip flops are connected to each other and then to logic 1 (or
VCC). While implementing this counter using T flip flop, T input of all the four
flip flops is connected to logic 1 (or VCC). So, flip flops work in toggle mode.
External clock pulse is connected to flip flop number 0 (i.e. first flip flop). Output
of first flip flop (i.e. ) is connected to clock input of flip flop number 1 (i.e.
second flip flop). Output of second flip flop (i.e. ) is connected to clock input of
flip flop number 2 (i.e. third flip flop) andoutput of third flip flop (i.e. ) is
connected to clock input of flip flop number 3 (i.e. fourth flip flop).
inputs) of all the four flip flops. Due to this modification, 4-bit asynchronous
counter is converted into mod-10 counter.
Output of this counter is observed at (LSB), , and (MSB) which
are output states of flip flop 0, flip flop 1, flip flop 2 and flip flop 3 respectively.
4-33
Timing diagram
how the counter counts from 0 (0000) to 9 (1001). After state 9 (1001), counter is
in state 10 (i.e. 1010). But as and are 1, output of NAND gate is 0 which
immediately clears all the flip flops. So instead of state 10 (i.e. 1010), we get 0
(i.e. 0000). So, counter repeatedly counts as 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2 and
so on.
Truth Table
4.4.1.3Synchronous counter
Synchronous counter is also called as parallel counter. In this type of
counter, same clock pulse is applied all the flip flops. The counter is called
synchronous as the clock pulses of all the flip flops are same. i.e. all the flip flops
are synchronized. Due to this, all the flip flops change their states at the same
time in synchronization with the clock pulse. So these counters have low
propagation delay. Hence the operational frequency is high. Only drawback of
this type of counter is that it is difficult to design. Extra circuitry is required for
designing these counters.
4.4.1.3.1 Steps for designing synchronous counter

For designing a n-bit asynchronous counter, following steps are
undertaken.
i. It requires n number of flip flops. The flip flops used may be either JK
flip flop or T flip flop.
ii. Preset and Clear inputs (i.e. Pr and Cr inputs) of all the n flip flops are
connected to logic 1 (or VCC) so that all the flip flops work properly.
iii. External clock pulse is connected commonly to all the n flip flops.
iv. When JK flip flops are used, J and K input of first flip flop (flip flop 0)
is connected to logic 1 (or VCC). When T flip flops are used, T input
offirst flip flop (flip flop 0) is connected to logic 1 (or VCC).
v. In case of UP counter, output of flip flop 0 (i.e. ) is connected to J
and K input of flip flop 1. Output of flip flop 1 (i.e. ) is connected to J
and K input of flip flop 2 and so on.
In case of DOWN counter, negated output of flip flop 0 (i.e. ) is
connected to J and K input of flip flop 1. Negated output of flip flop 1
(i.e. ) is connected to J and K input of flip flop 2 and so on.
vi. Output of the counter is observed at (LSB), , …, ( ) which
are output states of flip flops 0, 1, …, n-1 respectively.
5.4.1.3.2 Two bit synchronous counter

For designing 2-bit synchronous counter 2 JK flip flops or 2 T flip flops
are used. Preset and Clear inputs (i.e. Pr and Cr inputs) of both flip flops are
connected to logic 1 (or VCC) so thatboth the flip flops work properly.External
clock pulse is connected commonly to both the flip flops. Following two figures
show design of 2-bit synchronous counter using JK flip flop and using T flip flop
respectively. While implementing this counter using JK flip flop, J and K
inputof first flip flop is connected to each other and then to logic 1 (or VCC).
4-34
While implementing this counter using T flip flop, T input of first flip flops is
connected to logic 1 (or VCC).In case of UP counter, output of flip flop 0 (i.e. ) is
connected to J and K input of flip flop 1 (in case of T flip flop implementation,
is connected to T input of flip flop 1). Output of the counter is observed at
(LSB) and (MSB) which are output states of flip flops 0 and 1respectively.
designs change their state along with the external clock pulse applied to them.
As the flip flops used are negative edge triggered, output changes on negative
Timing diagram
how the counter counts from 0 (00) to 3 (11). So, counter repeatedly counts as 0,
1, 2, 3, 0, 1, 2 and so on.
Truth Table
5.4.1.3.3 Two bit DOWN counter

It is a 2-bit synchronous DOWN counter. For designing 2-bit synchronous
DOWN counter 2 JK flip flops or 2 T flip flops are used. Preset and Clear inputs
(i.e. Pr and Cr inputs) of both flip flops are connected to logic 1 (or V CC) so that
both the flip flops work properly.External clock pulse is connected commonly to
both the flip flops. Following two figures show design of 2-bit synchronous
DOWN counter using JK flip flop and using T flip flop respectively. While
implementing this counter using JK flip flop, J and K input of first flip flop is
connected to each other and then to logic 1 (or VCC). While implementing this
counter using T flip flop, T input of first flip flop is connected to logic 1 (or VCC).
As it is DOWN counter, negated output of flip flop 0 (i.e. ) is connected to J
and K input of flip flop 1 (in case of T flip flop implementation, is connected
to T input of flip flop 1). Output of the counter is observed at (LSB) and
(MSB) which are output states of flip flops 0 and 1respectively.
Timing diagram
4-35
how the counter counts from 3 (11) to 0 (00). So, counter repeatedly counts as 3,
2, 1, 0, 3, 2 and so on.
Truth Table
5.4.1.3.4 Three bit synchronous counter

are used. Preset and Clear inputs (i.e. Pr and Cr inputs) of all the three flip flops
are connected to logic 1 (or VCC) so that all the flip flops work properly.External
clock pulse is connected commonly to all the flip flops. Following two figures
respectively. While implementing this counter using JK flip flop, J and K input
of first flip flop is connected to each other and then to logic 1 (or VCC). While
implementing this counter using T flip flop, T input of first flip flops is
connected to logic 1 (or VCC). In case of UP counter, output of flip flop 0 (i.e. )
is connected to J and K input of flip flop 1 (in case of T flip flop implementation,
is connected to T input of flip flop 1). Output of flip flop 0 (i.e. ) and output
of flip flop 1 (i.e. ) are connected to AND gate whose output is connected to J
and K input of flip flop 2 (in case of T flip flop implementation, output of flip flop
0 (i.e. ) and output of flip flop 1 (i.e. ) are connected to AND gate whose
output is connected to T input of flip flop 2).Output of the counter is observed at
(LSB), and (MSB) which are output states of flip flops 0, 1
and2respectively.
Timing diagram
how the counter counts from 7 (111) to 0 (000). So, counter repeatedly counts as
7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4and so on.
Truth Table
5.4.1.3.5 Three bit DOWN counter

(i.e. Pr and Cr inputs) of all the three flip flops are connected to logic 1 (or V CC)
so that all the flip flops work properly.External clock pulse is connected
commonly to both the flip flops. Following two figures show design of 3-bit
synchronous DOWN counter using JK flip flop and using T flip flop respectively.
While implementing this counter using JK flip flop, J and K input of first flip
4-36
flop is connected to each other and then to logic 1 (or VCC). While implementing
this counter using T flip flop, T input of first flip flop is connected to logic 1 (or
VCC). As it is DOWN counter, negated output of flip flop 0 (i.e. ) is connected to
J and K input of flip flop 1 (in case of T flip flop implementation, is connected
to T input of flip flop 1). Negated output of flip flop 0 (i.e. ) and negated output
and K input of flip flop 2 (in case of T flip flop implementation, negated output of
flip flop 0 (i.e. ) and negated output of flip flop 1 (i.e. ) are connected to AND
gate whose output is connected to T input of flip flop 2).Output of the counter is
observed at (LSB), and (MSB) which are output states of flip flops 0, 1
and2 respectively.
Timing diagram
how the counter counts from 7 (111) to 0 (000). So, counter repeatedly counts as
7, 6, 5, 4, 3, 2, 1, 0, 7, 6 and so on.
Truth Table
5.4.1.3.6 Four bit synchronous counter

are used. Preset and Clear inputs (i.e. Pr and Cr inputs) of all the four flip flops
are connected to logic 1 (or VCC) so that all the flip flops work properly.External
clock pulse is connected commonly to all the flip flops. Following two figures
respectively. While implementing this counter using JK flip flop, J and K input
of first flip flop is connected to each other and then to logic 1 (or VCC). While
implementing this counter using T flip flop, T input of first flip flops is
connected to logic 1 (or VCC). In case of UP counter, output of flip flop 0 (i.e. )
is connected to J and K input of flip flop 1 (in case of T flip flop implementation,
is connected to T input of flip flop 1). Output of flip flop 0 (i.e. ) and output
and K input of flip flop 2 (in case of T flip flop implementation, output of flip flop
0 (i.e. ) and output of flip flop 1 (i.e. ) are connected to AND gate whose
output is connected to T input of flip flop 2).Output of flip flop 0 (i.e. ), output
of flip flop 1 (i.e. ) and output of flip flop 2 (i.e. ) are connected to AND gate
whose output is connected to J and K input of flip flop 3 (in case of T flip flop
implementation, output of flip flop 0 (i.e. ), output of flip flop 1 (i.e. ) and
output of flip flop 2 (i.e. ) are connected to AND gate whose output is
4-37
connected to T input of flip flop 3).Output of the counter is observed at (LSB),
, and (MSB) which are output states of flip flops 0, 1, 2 and3respectively.
Timing diagram
how the counter counts from 15 (1111) to 0 (0000). So, counter repeatedly counts
as 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 15, 14and so on.
Truth Table
5.4.1.3.7 Four bit DOWN counter

(i.e. Pr and Cr inputs) of all the four flip flops are connected to logic 1 (or V CC) so
that all the flip flops work properly.External clock pulse is connected commonly
to both the flip flops. Following two figures show design of 4-bit synchronous
DOWN counter using JK flip flop and using T flip flop respectively. While
implementing this counter using JK flip flop, J and K input of first flip flop is
connected to each other and then to logic 1 (or VCC). While implementing this
counter using T flip flop, T input of first flip flopis connected to logic 1 (or V CC).
As it is DOWN counter, negated output of flip flop 0 (i.e. ) is connected to J
and K input of flip flop 1 (in case of T flip flop implementation, is connected
to T input of flip flop 1). Negated output of flip flop 0 (i.e. ) and negated output
and K input of flip flop 2 (in case of T flip flop implementation, negated output of
flip flop 0 (i.e. ) and negated output of flip flop 1 (i.e. ) are connected to AND
gate whose output is connected to T input of flip flop 2). Negated output of flip
flop 0 (i.e. ), negated output of flip flop 1 (i.e. ) and negated output of flip
flop 2 (i.e. ) are connected to AND gate whose output is connected to J and K
input of flip flop 3 (in case of T flip flop implementation, negated output of flip
flop 0 (i.e. ), negated output of flip flop 1 (i.e. ) and negated output of flip
flop 2 (i.e. ) are connected to AND gate whose output is connected to T input of
flip flop 3).Output of the counter is observed at (LSB), , and (MSB)
which are output states of flip flops 0, 1, 2 and3respectively.
4-38
Timing diagram
how the counter counts from 15 (1111) to 0 (0000). So, counter repeatedly counts
as 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 15, 14 and so on.
Truth Table
Questions:
1. State two applications of counters. [2M]
2. List any four applications of counters. [2M]
3. Define counter and modulus of counter. [2M]
4. Explain ‘modulus of a counter’ with example. [2M]
5. What is modulus of a counter? [2M]
6. Draw logical circuit diagram of a 3 bit asynchronous counter and explain.
[4M]
7. Explain 4-bit asynchronous counter with circuit diagram and timing
diagram. [4M]
8. Design a 3-bit asynchronous counter. Draw its truth table. [4M]
9. How many flip flops are required to construct the following modulus
counter? Why? [4M]
i) -5 ii) 83 iii) 99 iv) 10
Tip: As counter is used for counting and counting is not done in negative
numbers, counter cannot count up to -5. So instead of -5 consider 5.
10. What is modulus of counter? Design a mod-3 ripple counter using a 2-bit
ripple counter. [4M]
Tip; For mod-3 ripple counter, N=3.  n=2. i.e. 2 flip flops are used. So, it
will be similar to 2-bit asynchronous counter with little modifications
(NAND gate, Clear inputs etc.)
11. Design mod-5 asynchronous counter. [4M]
12. Design a mod-5 ripple counter. [4M]
13. Design mod-6 asynchronous counter. [4M]
14. Design asynchronous mod-6 counter with its truth table. [4M]
15. Design mod-10 asynchronous counter with suitable flip-flop. [4M]
16. Design a mod-11 asynchronous counter giving the steps of design. [4M]
17. Draw mod-11 asynchronous counter using T flip flop. [4M]
18. List steps to design a ‘n’ bit synchronous up counter. [4M]
19. Explain 3-bit synchronous counter. [4M]
20. Explain 3-bit synchronous counter with logical circuit diagram and timing
diagram. [4M]
21. Explain working of 3-bit synchronous counter with circuit diagram. [4M]
22. Explain 3-bit synchronous counter with truth table and timing diagram.
[4M]
23. Design 3-bit synchronous up counter. [4M]
4-39
24. Draw mod 8 synchronous counter with timing diagram of truth table. [4M]
25. Compare between synchronous and asynchronous counter (4 points). [4M]
4.4.2Registers
Register is a sequential logic circuit. It is also cascaded arrangement of
more than one flip flop with or without some combinational logic devices. It is
also called as Shift Register. As seen before, a single flip flop is 1-bit memory
cell. So, a single flip flop is also called as 1-bit register.It is basically used for
storing and/or transferring digital information. Applications of registers or shift
registers are
- Delay Line.
- Serial to Parallel Converter.
- Parallel to Serial Converter.
- Ring Counter.
- Twisted Ring Counter.
- Sequence Generator.
- Sequence Detector.
For designing counters either JK flip flops or D flip flops are used. While
using JK flip flops, J input is connected to K input through a NOT gate. (i.e. JK
flip flop is to be used as D flip flop).
Data can be entered or retrieved in serial or in parallel to or from a shift
register. Depending on the way how data is entered and retrieved, shift
registers can be classified as
- Serial In Serial Out (SISO) Shift Register
- Serial In Parallel Out (SIPO) Shift Register
- Parallel in Parallel Out (PIPO) Shift Register
- Parallel in Serial Out (PISO) Shift Register
Block diagrams of n-bit shift registers of all the above types are shown
below.
Block diagram of SISO
Block diagram of SIPO
Block diagram of PIPO
Block diagram of PISO
4.4.2.1Important design/ implementation issues for registers

While designing or implementing registers or shift registers, following
issues are important.
1. Number of flip flops used
For n-bit register or n-bit shift register, n flip flops are used.
If N is to be stored in a register (or shift register), then n flip flops

are required. Here value of n is selected in such a way that n should be
the smallest number, for which ≤ .
Example 1: For storing 35
4-40
N=35
6 flip flops are required for designing a register which can
store 35.
Example 2: For storing decimal 24

N=24
store decimal 24.
Example 3: For storing hexadecimal C

N=(C)16=(12)10=12
store hexadecimal C.
Example 4: For storing octal 37

N=(37)8=(31)10=31
store octal 37.
Example 5: For storing 32

N=32
If n=5, 2n is 32. Here, N is equal to 2n.
store 32.
2. Sequencing of flip flops

4-41
In the cascaded arrangement of flip flops, the flip flops are
numbered as A, B, C and so on. i.e. first flip is numbered as A, second flip
flop is numbered as B and so on. Serial input is provided at input of flip
flop A. In the truth table the columns of output are numbered as , ,
and so on. Here is considered as MSB and the last output state is
considered as LSB. (This is a major difference from counter
implementation)
3. Types of flip flops used

Either JK flip flops or D flip flops are used for implementing
registers or shift registers. In both the implementations, Preset and Clear
inputs (i.e. Pr and Cr inputs) of all the flip flops are connected to logic 1
(i.e. VCC) so that all the flip flops will work normally.
4. JK flip flop implementation

When JK flip flops are used for implementation, serial input is
provided at J input of flip flop A(i.e. ). J input of flip flop A is connected
to K input of flip flop A (i.e. ) through a NOT gate. (i.e. JK flip flop is to
be used as D flip flop). Then output of flip flop A (i.e. ) is connected to J
input of flip flop B (i.e. ) and negated output of flip flop A (i.e. ) is
connected to K input of flip flop B (i.e. ). This is equivalent to
connecting J to K through a NOT gate. Similar connections are made for
further flip flops.
5. D flip flop implementation

When D flip flops are used for implementation, serial input is
provided at D input of flip flop A (i.e. ). Then output of flip flop A (i.e.
) is connected to D input of flip flop B (i.e. ). Similar connections are
made for further flip flops.
4.4.2.2Four bit Serial In Serial Out (SISO) Shift Register

For designing or implementing 4-bit SISO shift register, either 4 JK flip
flops or 4 D flip flops are used. Both these implementations are shown below.
The flip flops are numbered as A, B, C and D. In both the implementations,
Preset and Clear inputs (i.e. Pr and Cr inputs) of all the four flip flops are
connected to logic 1 (i.e. VCC) so that all the flip flops will work normally. A
common clock pulse is applied to all the flip flops.
In implementation using JK flip flop, Serial Input(Xi) is provided at J
input of flip flop A (i.e. ). J input of flip flop A is connected to K input of flip
flop A (i.e. ) through a NOT gate. (i.e. JK flip flop is to be used as D flip flop).
Then output of flip flop A (i.e. ) is connected to J input of flip flop B (i.e. )
and negated output of flip flop A (i.e. ) is connected to K input of flip flop B
(i.e. ).Output of flip flop B (i.e. ) is connected to J input of flip flop C (i.e. )
and negated output of flip flop B (i.e. ) is connected to K input of flip flop C
(i.e. ). Output of flip flop C (i.e. ) is connected to J input of flip flop D (i.e. )
and negated output of flip flop C (i.e. ) is connected to K input of flip flop D
(i.e. ).
In implementation using D flip flop, Serial Input(Xi) is provided at D
input of flip flop A (i.e. ). Then output of flip flop A (i.e. ) is connected to D
input of flip flop B (i.e. ). Output of flip flop B (i.e. ) is connected to D input
4-42
of flip flop C (i.e. ). Output of flip flop C (i.e. ) is connected to D input of flip
flop D (i.e. ).
Serial Output(Y) is observed at .
Design using D flip flop
Following truth table shows the state transitions in the register for
sample input sequence 10110. It shows how the flip flops change their states on
each clock pulse.
Truth Table
designs change their state along with the external clock pulse applied to them
for the above sample input sequence.
Timing diagram
4.4.2.3Four bit Serial In Parallel Out (SIPO) Shift Register

For designing or implementing 4-bit SIPO shift register, either 4 JK flip
In implementation using JK flip flop, Serial Input (Xi) is provided at J
input of flip flop A (i.e. ). J input of flip flop A is connected to K input of flip
flop A (i.e. ) through a NOT gate. (i.e. JK flip flop is to be used as D flip flop).
Then output of flip flop A (i.e. ) is connected to J input of flip flop B (i.e. )
and negated output of flip flop A (i.e. ) is connected to K input of flip flop B
(i.e. ). Output of flip flop B (i.e. ) is connected to J input of flip flop C (i.e. )
(i.e. ).
In implementation using D flip flop, Serial Input (Xi) is provided at D
input of flip flop A (i.e. ). Then output of flip flop A (i.e. ) is connected to D
input of flip flop B (i.e. ). Output of flip flop B (i.e. ) is connected to D input
of flip flop C (i.e. ). Output of flip flop C (i.e. ) is connected to D input of flip
flop D (i.e. ).
Parallel Output is observed at output states of all the four flip flops i.e.
, , and .
4-43
each clock pulse.
Truth Table
Timing diagram
4.4.2.4Four bit Parallel In Parallel Out (PIPO) Shift Register

For designing or implementing 4-bit PIPO shift register, either 4 JK flip
In implementation using JK flip flop, J input of flip flop A is connected to
K input of flip flop A (i.e. ) through a NOT gate. (i.e. JK flip flop is to be used
as D flip flop). Then output of flip flop A (i.e. ) is connected to J input of flip
flop B (i.e. ) and negated output of flip flop A (i.e. ) is connected to K input of
flip flop B (i.e. ). Output of flip flop B (i.e. ) is connected to J input of flip
flop C (i.e. ) and negated output of flip flop B (i.e. ) is connected to K input of
flip flop C (i.e. ). Output of flip flop C (i.e. ) is connected to J input of flip
flop D (i.e. ) and negated output of flip flop C (i.e. ) is connected to K input of
flip flop D (i.e. ).
In implementation using D flip flop, output of flip flop A (i.e. ) is
connected to D input of flip flop B (i.e. ). Output of flip flop B (i.e. ) is
connected to D input of flip flop C (i.e. ). Output of flip flop C (i.e. ) is
connected to D input of flip flop D (i.e. ).
Parallel Input is provided at all the J inputs (or D inputs) of all the four
flip flops i.e. , , and (or , , and ).
Parallel Output is observed at output states of all the four flip flops i.e.
, , and .
each clock pulse.
Truth Table
4-44
Timing diagram
4.4.2.5Four bit Parallel In Serial Out (PISO) Shift Register

For designing or implementing 4-bit PISO shift register, either 4 JK flip
There is no separate design for Parallel in Serial Out (PISO) shift
register. Rather, this operation can be utilized from the design of universal shift
register. Universal Shift Register is a shift register that can operate in any of
the four typeswhich are SISO, SIPO, PIPO and PISO.
Here, inputs to the flip flops are provided differently. An extra input
SHIFT/LOAD is used. When this input is 1, SHIFT operations takes place. i.e.
Input is given serially. When this input is 0, LOAD operation takes place. i.e.
Input is given in parallel.
In implementation using JK flip flop, J inputs of all the flip flopsare
connected to K inputs of the same flip flops through a NOT gates. (i.e. JK flip
flops are to be used as D flip flops).
J inputs (or D inputs) are driven by output of OR gates. These OR gates
are driven by outputs of two AND gates. For each first AND gate, one input is
taken from SHIFT/LOADinput and the other input is taken from output of
previous flip flop. In case of first flip flop this other input is taken from Serial
Input. For each second AND gate, one input is taken from SHIFT/LOAD input
through NOT gate and the other input is taken fromParallel Inputs , ,
and (or , , and ).
Serial Output may be observed at output of flip flop D. Parallel Output
may be observed at output of flip flops A,B, C and D (i.e.).
Then output of flip flop A (i.e. ) is connected to J input of flip flop B (i.e.
) and negated output of flip flop A (i.e. ) is connected to K input of flip flop B
(i.e. ). Output of flip flop B (i.e. ) is connected to J input of flip flop C (i.e. )
(i.e. ).
In implementation using D flip flop, output of flip flop A (i.e. ) is
connected to D input of flip flop B (i.e. ). Output of flip flop B (i.e. ) is
connected to D input of flip flop C (i.e. ). Output of flip flop C (i.e. ) is
connected to D input of flip flop D (i.e. ).
Parallel Input is provided at all the J inputs (or D inputs) of all the four
flip flops i.e. , , and (or , , and ).
Parallel Output is observed at output states of all the four flip flops
i.e. , , and .

4-45
4.4.2.6Universal Shift Register
As already discussed in 4.4.2.5, Universal Shift Register is a shift
register that can operate universally. It can take serial as well as parallel input.
Alos it can generate serial as well as parallel output. So, it can operate in any of
the four types which are Serial In Serial Out, Serial In Parallel Out, Parallel In
Parallel Out and Parallel In Serial Out.
Design or implementation of universal shift register using JK flip flop as
well as D flip flop is already shown in 4.4.2.5.
IC 7495 can be used as universal shift register.Pin diagram of this 14-pin
IC is shown in following figure. Pin 1 is used for serial input and pin numbers 2,
3, 4 and 5 are used for parallel input. Parallel output can be taken from pin
numbers 13, 12, 11 and 10. Pin 10 (as it is output of last flip flop. i.e. ) is used
for serial output. Pin 6 is used for selecting Mode of operation of the IC. Pin
number 9 (CLK1) is used for providing clock for normal right shift operation and
pin 8 (CLK1) is used for left-shift (or LOAD operation. i.e. parallel input). Pin
number 7 and 14 are used for providing ground and VCC respectively.
4.4.2.7Ring Counter
It is also called as Circulating Register. It is one of the application of
shift register. It shifts a bit within the flip flops continuously.A ring counter is
obtained from a shift register by directly feeding back the output of the last flip-
flop to the J input (or D input) of the first flip-flop.
Ring counter can be implemented using JK flip flops as well as D flip
flops. These implementations are shown in following figuresrespectively.In J-K
flip-flop implementation, outputs of the last flip-flop (i.e. and ) are
respectively fed back to the J and Kinputs of the first flip-flop (i.e. and ).In
D flip-flop implementation, output of the last flip-flop (i.e. ) is fed back to the
D input of the first flip-flop (i.e. ).
Assuming that flip flop A is initially set to 1 and remaining flip flops are
set to 0, initial output of the ring counter will be 1000.With the first clock pulse,
this ‘1’ gets shifted to the second flip-flop output and the counter output becomes
0100. Similarly, with the second and thirdclock pulses, the counter output will
become 0010 and 0001. With the fourth clock pulse, the counteroutput will again
become 1000. The count cycle repeats in the subsequent clock pulses.
Truth table for this sample is shown below.
Truth table
Timing diagram for the same sample is shown below.
Timing Diagram
4.4.2.8Twisted Ring Counter
4-46
It is also called as Johnson Counter. It is one of the application of shift
register. A twisted ring counter is obtained from a shift register by directly
feeding back the negated output of the last flip-flop to the J input (or D input) of
the first flip-flop and output of the last flip flop to K input of the first flip flop.
Twisted ring counter can be implemented using JK flip flops as well as D
flip flops. These implementations are shown in following figures respectively. In
J-K flip-flop implementation, outputs of the last flip-flop (i.e. and ) are
respectively fed back to the K and Jinputs of the first flip-flop (i.e. and ).(i.e.
is fed back to and is fed back to .In D flip-flop implementation,
negated output of the last flip-flop (i.e. ) is fed back to the D input of the first
flip-flop (i.e. ).
Assuming that all the flip flopsare initially reset to 0, initial output of the
ring counter will be 0000. With the first clock pulse, output becomes 1000.
Similarly, with the second, thirdand fourth clock pulses, the counter output will
become 1100, 1110 and 1111. With the fifth clock pulse, the counteroutput will
again become 0111. Then on consecutive clock pulses output will be 0011, 0001,
0000, 1000 and so on.
Truth table for this sample is shown below.
Truth table
Timing diagram for the same sample is shown below.
Timing Diagram
Questions:
1. Compare counters and shift registers. [4M]
2. Give applications of shift register. [4M]
3. List different types of shift registers. [2M]
4. List different types of shift registers and draw 4-bit SISO shift register.
[4M]
5. Draw logical circuit diagram of 4-bit serial in serial out shift register.
Explain with truth table. [4M]
6. Draw and explain SISO with truth table and timing diagram. [4M][
7. Draw block diagram of SISO (Right shift mode) shift register with its
truth table and logic diagram. [4M]
8. Explain the function of 3-bit SISO with waveforms and block diagram.
[4M]
9. Draw and explain working of 4-bit SIPO shift register with truth table.
[4M]
10. Draw diagram of Serial In Parallel Out (SIPO) shift register. Also draw
timing diagram. [4M]
11. Explain 4-bit SIPO shift register with the help of block diagram, truth
table and timing diagrams. [4M]
12. Draw and describe universal shift register. [4M]
4-47
13. Draw pin diagram of universal shift register IC 7495. [2M]
14. Draw pin diagram of universal shift register IC 7495. List any two
applications of shift register. [4M]
15. Study given figure. Initial output condition is QA QB Qc = 010. Write
truth table of output QA QB Qc for 4 clock pulses. [4M]
P P P
D D D
Clk Clk Clk
C C C
Cloc
k
16. With the help of block diagram explain working of ring counter. [4M]
17. How many flip flops are required to build a shift register to store following
number. [4M]
i) Decimal 28 ii) Binary 6 bits iii) Octal 17 iv) Hexadecimal A
4.5 Memories
Semiconductor memories can be classified on the basis of various factors

as.
- Based on principle of operation
- Based on accessing method
- Based on fabrication technology
4.5.1 Classification based on principle of operation

On the basis of principle of operation, semiconductor memories can be
classified as
- Read Only Memory (ROM)
- Random Access Memory (RAM)
4.5.1.1 Read Only Memory (ROM)

In this type of semiconductor memory, data can be only read from the
memory. So, data is written in ROM at the time of manufacturing only. But,
data can be read any number of times from ROM. ROM is non-volatile memory.
i.e. Contents of ROM don’t get vanished even after power given to the computer
is switched off.
Major use of ROM is to store BIOS information and bootstrap program.
ROM can be further classified as

- Programmable Read Only Memory (PROM)
In this type of ROM, data can be written in the memory only once
after manufacturing it. For this PROM Programmer is required.
- Erasable Programmable Read Only Memory (EPROM)
In this type of ROM, data written in it can be erased with the help
4-48
of ultra-violet (UV) rays. As data can be erased at any number of times,
this type of ROM can be programmed (data can be written) at multiple
times.
- Electrically Erasable Programmable Read Only Memory (EEPROM)
As erasing data from EPROM requires UV rays, it becomes
cumbersome task. So, in this type of ROM, data can be erased electrically.
It is also called as E2PROM.
4.5.1.2 Random Access Memory (RAM)

In this type of semiconductor memory, data can be read from the memory
as well as written into the memory. As data can be read or written randomly, it
is called as Random Access Memory. RAM is volatile memory. i.e. Contents of
RAM get vanished when power given to the computer is switched off.
RAM is used as main memory of computer system. It is generally used for
storing data, program instructions and intermediate data during execution of
program. Data can be read or written any number of times.
Depending on type of memory cell used, RAM can be further classified as

- Static Random Access Memory (Static RAM)
- Dynamic Random Access Memory (Dynamic RAM)
4.5.1.2.1 Static RAM

Basic element used in static RAM (also referred as SRAM) is a latch
memory cell. Latch memory cell holds its contents as long as power is provided
to it. So, contents of SRAM don’t get lost until power given to the computer is
not switched off.
Speed of operation of SRAM is more as compared to dynamic RAM. But
Memory capacity of SRAM is less as compared to dynamic RAM.
4.5.1.2.2 Dynamic RAM

Basic element used in dynamic RAM (also referred as DRAM) is a
capacitor and MOSFET. Capacitor stores the contents as charge. But as
capacitor may get discharged contents of DRAM may get lost even if power
given to the computer is not switched off. So, refreshing of memory is required
at regular intervals (after every 5-10 ms) even if power is connected to the
computer. For this, additional refreshing circuit is required which is major
disadvantage of DRAM.
Most important advantage of this memory is its high density. i.e. More
number of bits. So, cost per bit is less. So, memory capacity of DRAM is more as
compared to SRAM whereas cost is less for DRAM as compared to SRAM.
Speed of operation of DRAM is less as compared to SRAM.
4.5.2 Classification based on accessing method

On the basis of accessing method, semiconductor memories can be
classified as
- Sequential Access Memory
In this type of memory, memory is accessed (read/written)
sequentially. e.g. Fifth byte cannot be accessed directly. For accessing
4-49
fifth byte one has to go sequentially as 1st, 2nd, 3rd, 4th and then only 5th
byte can be accessed.
So, in general speed of operation is very less.
- Random Access Memory
In this type of memory, memory can be accessed (read/written)
randomly. i.e. Any byte can be accessed at any time regardless of its
position.
So, in general speed of operation is high.
4.5.3 Classification based on fabrication technology

On the basis of fabrication technology, semiconductor memories can be
classified as
- Bipolar Memory
In this type of memory, memory is fabricated using bipolar
components like transistors.
- Unipolar Memory
In this type of memory, memory is fabricated using unipolar
components like MOSFETs.
Questions:
1. Give classification of different types of semiconductor memories. [2M]
2. Classify memories. Give function of each type. [4M]
3. Describe how memories can be classified. [4M]
4. State how memories can be classified on the basis of principle of operation.
[4M]
5. Give classification of different types of ROM memory. [4M]
6. Give classification of different types of semiconductor memories based on
fabrication technology. [2M]
7. Classify memories and explain ROM. [4M]
8. Compare ROM and RAM (4 points). [2M], [4M]
9. Differentiate between ROM and RAM. [4M]
10. Compare static RAM and dynamic RAM. [4M]
11. Differentiate between static and dynamic RAM. (any four points) [4M]
12. Write advantages and disadvantages of dynamic RAM. [4M]
13. State advantages and disadvantages of static RAM. [4M]
14. Give four features of dynamic RAM. [4M]
15. Explain EPROM. [4M]
16. State advantages and disadvantages of EPROM. [4M]
17. Distinguish between ROM, PROM, EPROM and EEPROM. [4M]
4-50

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Chapter 4 Sequential Lo232323

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Chapter 4

Sequential Logic Circuits

4.1Introduction to Sequential Logic Circuit

Logic circuits discussed previously were combinational circuits. In those

4.2.1One-bit memory cell

Figure 4.1: One-bit memory cell using NAND gates

4.2.2Clock signal and Triggering Methods

Figure 4.3: Clock signal

In level triggering, the circuit is triggered at a level. There are two

4.3 Flip flops

4.3.1SR Flip Flop or RS Flip Flop

Figure 4.5: Symbol of SR Flip Flop

When S=0 and R=0

When S=0 and R=1

When S=1 and R=0

When S=1 and R=1

Truth table of SR flip flop is shown below.

4.3.1.1 Clocked SR Flip Flop

Figure 4.6: Implementation of clocked SR Flip Flop

Symbol of clocked SR flip flop is shown below. It is positive triggered SR

Figure 4.7: Symbol of clocked SR Flip Flop

When Clk=0, S=X and R= X

When Clk=1, S=0 and R=1

When Clk=1, S=1 and R=0

When Clk=1, S=1 and R=1

Truth table of clocked (positive level triggered) SR flip flop is shown

4.3.1.2Clocked SR Flip Flop with Preset and Clear inputs

When Pr=0, Cr=0, Clk=X, S=X and R= X

4.3.1.3 SR Flip Flop with different triggering methods

Figure 4.10: Symbol of Positive level triggered SR Flip Flop

Figure 4.11: Symbol of Negative level triggered SR Flip Flop

Figure 4.12: Symbol of Positive edge triggered SR Flip Flop

Figure 4.13: Symbol of Negative edge triggered SR Flip Flop

4.3.2JK Flip Flop

Symbol of JK flip flop is shown below.

When J=0 and K=0

When J=0 and K=1

When J=1 and K=0

When J=1 and K=1

4.3.2.1 Race around condition in JK flip flop

Output State Here, at the end of

Figure 4.16: Sample (Sample 1) output pulse when J=K=1

Output State Here, at the end of

Figure 4.17: Sample (Sample 2) output pulse when J=K=1

This uncertainty in the output state when J=K=1 is called as race-

4.3.2.2Master Slave JK Flip Flop

Symbol of MS JK flip flop is shown below.

Figure 4.19: Symbol of MS JK Flip Flop

Truth table of MS JK flip flop is shown below.

4.3.2.3JK Flip Flop with different triggering methods

Figure 4.20: Symbol of Positive level triggered JK Flip Flop

Figure 4.21: Symbol of Negative level triggered JK Flip Flop

Figure 4.22: Symbol of Positive edge triggered JK Flip Flop

Figure 4.23: Symbol of Negative edge triggered JK Flip Flop

4.3.3T Flip Flop

Figure 4.24: Implementation of T Flip Flop using JK Flip Flop

Symbol of T flip flop is shown below

Figure 4.25: Symbol of T Flip Flop

Truth table of T flip flop is given below.

Table 4.15: Truth Table for T Flip Flop

4.3.3.1T Flip Flop with different triggering methods

Figure 4.26: Symbol of positive level triggered T Flip Flop

Figure 4.27: Symbol of negative level triggered T Flip Flop

Figure 4.28: Symbol of positive edge triggered T Flip Flop