Exclusive OR (XOR) Gate

Laboratory Activity no.4

Name: Paolo Winston Regalado Date Performed: 12/10/2020

Group no._________2___ Date Submitted: 12/13/2020

LEARNING OUTCOME
1. To demonstrate the concept, operation and characteristics of a XOR logic gate.

MATERIALS:

1- 7404, 7408, 7402, 7400, 7432, 7486

1- Digital trainer

DISCUSSION OF PRINCIPLES

The exclusive - or gate is modified OR gate in which a single HIGH input will yield a
HIGH output, but two HIGH or two LOW input yields a LOW output. The XOR gate may be
depicted as (A+B) symbolically where the circled OR operator indicates the Exclusive-OR
function.

XOR gate (sometimes EOR, or EXOR and pronounced as Exclusive OR) is a digital logic gate
that gives a true (1 or HIGH) output when the number of true inputs is odd. An XOR gate
implements an exclusive or; that is, a true output results if one, and only one, of the inputs to the
gate is true. If both inputs are false (0/LOW) or both are true, a false output results. XOR
represents the inequality function, i.e., the output is true if the inputs are not alike otherwise the
output is false. A way to remember XOR is "one or the other but not both". XOR can also be
viewed as addition modulo 2. As a result, XOR gates are used to implement binary addition in
computers. A half adder consists of an XOR gate and an AND gate. Other uses include
subtractors, comparators, and controlled inverters.

The algebraic expressions (A + B)(A + B) both represent the XOR gate with inputs A and B.
The behavior of XOR is summarized in the truth table shown on the right.

XOR Truth table

A B C
0 0 0
0 1 1
1 0 1
1 1 0

There are two symbols for XOR gates: the traditional symbol and the IEEE symbol. For more
information see Logic Gate Symbols.
Traditional XOR Symbol IEEE XOR Symbol

PROCEDURE:

1. Install one 7404 HEX inverter, one 7408 Quad two input AND gate and one 7432 Quad
two input OR gate in the breadboard. Connect +5V to each pin 14, common to each pin 7.

2. Construct the circuit shown in figure 4-1. Set the data switches as shown in table 1.
Record the L1 indications.
3. Install one 7400 Quad 2-input NAND gate into breadboard. Connect +5V to each pin 14,
common to each pin 7.
4. Construct the circuit as shown in figure 4-2. Set the data switches as shown in table 2.
Record L3 indications. Compare with the XOR gate truth table output.
5. Install one 7402 Quad 2-input NOR gate and one 7404 HEX inverter in the breadboard.
Connect +5V to each pin 14, common to each pin 7.
6. Construct the circuit as shown in figure 4-3. Set the data switches as shown in table 3.
Record the L2 indications. Compare the output to the XOR truth table.
7. Insert one 7486 Quad 2-input XOR gate in the breadboard. Construct the circuit as shown
in figure 4-4. Set data switches as shown in table 4. Record the L1 indications. Compare
the output with the XOR gate truth table output.
 Input Output
SW1 SW2 L1
Table 1 0 0 0 LOW
0 1 1 HIGH
1 0 1 HIGH
1 1 0 LOW

FIGURE 4-1

SW 1 = 0
SW 2 = 0
VCC U1A U3A
5V SW1

7404N 7408N U5A

Key = 1

7432N L1
U2A U4A
SW2

7404N 7408N
Key = 2

SW 1 = 0
SW 2 = 1
VCC U1A U3A
5V SW1

7404N 7408N U5A

Key = 1

7432N L1
U2A U4A
SW2

7404N 7408N
Key = 2
SW 1 = 1
SW 2 = 0
VCC Input U1A U3A Output
5V SW1
SW1 SW2 L1
0 0 7404N 07408N U5A
LOW
Key = 1
0 1 1 HIGH
7432N L1
1 0 U2A 1 U4A HIGH
SW2
1 1 0 LOW
7404N 7408N
Key = 2

SW 1 = 1
SW 2 = 1

VCC U1A U3A

5V SW1

7404N 7408N U5A

Key = 1

7432N L1
U2A U4A
SW2

7404N 7408N
Key = 2

Table 2
 FIGURE 4-2

SW 1 = 0
SW 2 = 0

U1A
VCC SW 1 = 0
5V L1
SW1 7400N U3A
U6A SW 2 = 1
U2A 7400N
Key = 1 7400N U1A
VCC SW2 7400N
5V L1
SW1 7400N U3A
U6A
Key = 2 U2A 7400N
Key = 1 7400N

SW2 7400N

Key = 2

SW 1 = 1
SW 2 = 0

U1A
VCC
5V L1
SW1 7400N U3A
U6A

U2A 7400N SW 1 = 1
Key = 1 7400N
SW 2 = 1
SW2 7400N

Key = 2

U1A
VCC
5V L1
SW1 7400N U3A
U6A

U2A 7400N
Key = 1 7400N

SW2 7400N

Key = 2
 Input Output
SW1 SW2 L1
0 0 0 LOW
0 1 1 HIGH
1 0 1 HIGH
1 1 0 LOW

Table 3

FIGURE 4-3

SW 1 = 0
SW 2 = 0
VCC SW1
5V U1A

U2B L1
Key = 1 U4A U3C
SW2 7402N
U3D
7402N
7404N 7402N
Key = 2
7402N

SW 1 = 0
SW 2 = 1

VCC SW1
5V U1A

U2B L1
Key = 1 U4A U3C
SW2 7402N
U3D
7402N
7404N 7402N
Key = 2
7402N
SW 1 = 1
SW 2 = 0 Input Output
SW1 SW2 L1
VCC SW1
5V 0 0 0 U1A LOW
0
Key = 1
1 U2B 1 HIGH L1
U4A U3C
SW2 7402N
1 0 1 HIGH
U3D
7402N
1 7404N 1 0 LOW
7402N
Key = 2
7402N

SW 1 = 1
SW 2 = 1

VCC SW1
5V U1A

U2B L1
Key = 1 U4A U3C
SW2 7402N
U3D
7402N
7404N 7402N
Key = 2
7402N

Table 4
 FIGURE 4-4

SW 1 = 0
SW 2 = 0 VCC SW1
5V
L1
U1A
Key = 1
SW2
7486N

Key = 2

SW 1 = 0
SW 2 = 1

VCC SW1
5V
L1
U1A
Key = 1
SW2
7486N

Key = 2

SW 1 = 1
SW 2 = 0

VCC SW1
5V
L1
U1A
Ke y = 1
SW2
7486N

Ke y = 2

SW 1 = 1
SW 2 = 1
 VCC SW1
5V
L1
U1A
Ke y = 1
SW2
7486N

Ke y = 2

Questions:

1. \\

a.) No because a logic circuit must have two inputs in order to be used as an enable/disable
circuit.

b.) No because the control input of an XOR gate can be either HIGH or LOW. If the control
input
A is LOW,
B the
C signal
X at the other input reaches the gate’s output unaffected. If the control
input is HIGH, the signal at the other input reaches the gate’s output INVERTED.
0 0 0 0

0 0 1 1
2.
0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 1
1 1 0 1
1 1 1 1
 BC 00 01 11 10
A
0 0 1 0 1

1 1 1 1
1

X = A + BC + BC
=A+B+C

Data Analysis:

In Figure 4-1 having 2 switches with 2 AND gates and output OR gate , there will be high
outputs or the LED will lights on when there is only 1 high input. If the two switches of are both
HIGH or LOW, then the output will be low.

In Figure 4-2, same results with the Figure 4-1 but uses 4 NAND gates, there are 2 switches and
the output is high when only 1 input is also high. If not then the output is low.

Figure 4-3 almost the same figure with Figure 4-2 with only difference is that instead of NAND
gate it uses OR gate and the SW2 had an inverter before being connected to the first gate and the
overall output is just the same with a single XOR gate. Figure 4-4 operated with two switch and
have a single XOR gate which each leg is connected to SW1 and SW2 respectively, where the
output will only be HIGH whenever both switches are the same.

Reference:
 1. Tocci, R. J. , Widmer, N. S. Digital Systems, Principles and Applications.
8th Ed.Prentice-Hall, Inc.Upper Saddle River, New Jersey. 2001.
Pp 133.