CSO (160311) - Unit 1

Madhav Institute of Technology & Science , Gwalior
COMPUTER SYSTEM ORGANIZATION (CSO) - 160311
B.Tech - II Year/ III Semester
Dr. R.K. Gupta, Deptt. of CSE 1

COMPUTER SYSTEM ORGANIZATION
160311 (DC)
COURSE OBJECTIVES :
● To provide the fundamental knowledge of a computer system
and its processing units.
● To provide the details of input & output operations, memory
management and performance measurement of the
computer system.
● To understand how computer represents and manipulate
data.

Unit 1 :
Introduction: Von-Neumann Model, Various Subsystems, CPU,
Memory, I/O, System Bus, CPU and Memory Registers, Program
Counter, Accumulator, Register Transfer and MicroOperations:
Register Transfer Language, Register Transfer, Three-State Bus
Buffers, Bus and Memory Transfers, Arithmetic Micro-Operation,
Logic Micro-Operation, Shift Micro-Operation Register Transfer
Micro Operations, Arithmetic Micro-Operations, Logic
MicroOperations and Shift Micro-Operations.

Unit 2:
Computer Arithmetic: Addition and Subtraction with Signed-
Magnitude, Multiplication Algorithm, Division Algorithms,
Floating-Point Arithmetic Operations.
Central Processing Unit (CPU): General Purpose Register
Organization, Stack Organization, Instruction Formats,
Addressing Modes, Data Transfer and Manipulation,
Program Control, Reduced Instruction Set Computer
(RISC).Hardwired and Micro programmed Control.

Unit 3 :
Microprocessors: Introduction of 8085 Microprocessor:
Architecture, Instruction Set, Addressing Modes, Interrupts and
Basic Assembly Language Programming.

Unit 4 :
Input-Output Organization: Peripheral Devices, I/O Interface,
Asynchronous Data Transfer, Modes of Transfer, Priority
Interrupt, DMA (DMA Controller, DMA Transfer),

Unit 5:
Memory Organization: Memory Hierarchy, Main Memory,
Auxiliary Memory, Associative Memory, Cache Memory-
Organization and Mappings, Memory Management Hardware,
Introduction to Pipelining & Multiprocessors.

RECOMMENDED BOOKS
Computer System Architecture, Morris Mano, PHI.
Microprocessor Architecture, Programming and Applications
with the 8085, Gaonkar,
Computer Organization, Carl Hamacher, THM.
Computer Architecture and Organization, J P Hayes, Mc-Graw
Hills, New Delhi.

COURSE OUTCOMES
After completion of the course students would be able to:
CO1. Recall the basic building blocks of computer Architecture.
CO2. Explain different memories and the functional units of a processor.
CO3. Explain the concept of working of microprocessor, multiprocessor and
pipelining.
CO4. Analyze various modes of Input-Output data transfer.
CO5. Evaluate the arithmetic related to the number system.
CO6. Develop the skill of writing low level programming.

Basic Terminologies
Bit, Nibble, Byte
Logic gates
Component, Circuit, System
Data, Information
Combinational Circuit
Half Adder, Full Adder, Word Comparator
Decoder, Multiplexer, Channel Selector
Sequential Circuit
Flip Flop
Counter

Instruction ( micro instruction, macro instruction)
Fetch Cycle, Indirect Cycle , Execution Cycle
Type of Instructions :
MRI,RRI, I/o

Program
Bus
Data Bus
Address Bus
Control Bus

Von-Neumann Architecture
● Proposed by John Von -Neumann in the year 1945.

It contains the following
- Control Unit
- Arithmetic and Logical Unit [ALU]
- Memory Unit
- Input Unit
- Output UNIT
Features :
● It is based on the Stored Program Computer
concept( Instructions and data are stored in same
memory).
● Uses a single processor
● Instructions and data are stored in same memory
● Execute the programs following the Fetch - Decode
- Execute cycle

Today’s most of the computers are based on this
designed approach.

Central Processing Unit :
● It is the heart of the computer
● It consists of : Control Unit, ALU and variety of
Registers

Control Unit
The Control Unit of a computer controls the
operations of different units/components such as
ALU, Memory (M/R) and Input- Output (I/O) devices.
It consists of number of registers :MAR, MBR/MDR,

PC, IR/CIR and AC.

Registers:
- They are high speed storage elements. Also called
CPU registers
- Before processing any data, it must be stored in a
register
- Registers are also used for some special purposes

Memory Address Register
- It is also called MAR
- It holds the memory address/ location of the data
that needs to be accessed.

Memory Buffer Register ( MBR)
- MBR is also called Memory Data Register ( MDR)
- Holds data that is being Read or Write from
Memory

READ/ WRITE Operation with Memory
MAR MEMORY
MBR

CE
MAR MEMORY
RD/WR
MBR

1011
000
1100
001
010 0000
011 1110
MAR
MBR
100 1101
101 0001
110 1000
111
1010

000
0011 MAR= 001
1100 MBR = 0001
001
CE’ = 0 , RD/WR’ = 0
010 0000
011 1111
MAR
100 MBR
1101
101
0001
110
1000
1010
111

000
0011 MAR= 001
0001 MBR = 0001
001
CE’ = 0 , RD/WR’ = 0
010 0000
011 1111
MAR =001
100 MBR= 0001
1101
101
0001
110
1000
1010
111

000
0011 MAR= 001
1100 MBR = 0001
001
CE’ = 1 , RD/WR’ = 0
010 0000
011 1111
MAR
100 MBR
1101
101
0001
110 note ; CE’ is 1. This
1000
means chip is inactive
1010
111

000
0011 MAR= 001
1100 MBR = 0001
001
CE’ = 0 , RD/WR’ = 1
010 0000
011 1111 What this will do ?
100 1101
101
0001
110
1000
1010
111

0011
000
1100 CE’ = 0 , RD/WR’ = 1
001
010 0000
011 1111
MAR = 001
100 MBR =0001
1101
101
0001 Note : Chip is ready for READ
110 operation. Location being pointed
1000
by MAR will be READ and value of
1010
111 this location will be stored in
MBR
0110
000
001 1100
010 0000
011 1111
100 MBR = 1100
1101
101
0001
110
1000
1010
111

Instruction cycle
Memory locations may contain either instruction, address or
data

MAR MEMORY
Read :
INSTRUCTION/
ADDRESS/
DATA
MBR

MAR MEMORY
Read :
INSTRUCTION (FETCH)
ADDRESS (INDIRECT)
DATA (Execution)
MBR

Instruction Execution:
Consists of three cycles :
● Fetch Cycle
● Indirect Cycle
● Execution Cycle
Note : all instructions have Fetch and execution
cycles. Some may have indirect cycle also.

Direct Instruction Vs Indirect
Instruction
Direct Instruction :
Fetch and Execution Cycle
Indirect Instruction :
Fetch cycle , Indirect cycle and Execution cycle

Types of Instructions:
● Memory Reference Instruction (MRI)
● Register Reference Instruction (RRI)
● Input Output Instruction (IOI)

Find the size of PC, MBR , MAR and AC
PC Memory
4096 X16
MAR
MBR
AC

Size of PC
PC 12 Memory
4096 X16
MAR
MBR
AC

Size of MAR
PC 12 Memory
4096 X16
MAR 12
MBR
AC

Size of MBR
PC 12 Memory
4096 X16
MAR 12
MBR 16
AC

Size of AC
PC 12 Memory
4096 X16
MAR 12
MBR 16
AC 16

Importance of Accumulator (AC) size
It shows the data handling capability of a computer
system/ microprocessor.
4 bit Computers/Microprocessors ( 4- bit CPU)
8 bit Computers/Microprocessors ( 8 - bit CPU)
16 bit Computers/Microprocessors (16 - bit CPU)
32 bit Computers/Microprocessors and so on.

Program Counter:
Program counter ( PC) is a register which contains
the address of the next instruction (of the program )
to be executed.
Or
PC is a pointer which points toward the next
instruction (of the program ) to be executed.

Program in memory
Program
Start …………….
……………..
……………..
……………..
..
..
End …………….
..

Program
Start ……………. During the execution of a
…………….. program , the value of PC
will change from Start
……………..
(address) to End
……………..
(address).
..
..
End …………….
..

Program
PC keeps track on the
instruction to be executed
……………..
Current Instruction
next.
……………..
PC
…………….. Suppose current
.. instruction which is being
.. processed was stored at
location ‘X’ then the
End …………….
Current value of PC will
..
be ‘ X + 1’

Program
PC keeps track on the
instruction to be executed
……………..
Current Instruction next.
……………..
PC =X +1
…………….. Suppose current
.. instruction which is being
.. processed was stored at
location ‘X’ then the
End …………….
Current value of PC will
..
be ‘ X + 1’

Difference Between PC & MAR
Program Counter (PC) points towards the memory

location where next instruction (to be executed)
is stored.
Memory Address Register (MAR) points towards the

memory location where Read or Write operation to
be performed.

Instruction Format
OPCODE PART + ADDRESS

PART

Instruction Format
OPCODE PART + ADDRESS

PART
OPCODE : Code of Instruction

ADDRESS : Address of the Operand (Data)/
Type of instruction

Recall the case, discussed earlier
PC Memory
4096 X16
MAR
MBR
AC

The maximum size of the word which we can store in
the memory = 16 bits
Thus maximum instruction length = 16 bits
( Note Instruction consists of opcode as well as
address part)

We also know that for the given case, size of the
address part is 12 bits
( as size of the memory is 4096 X 16 bits)
Thus, size of the opcode is restricted to 16 - 12 = 4
bits

By using these bits, one can design different
instructions such as
● MRI
- Direct
- Indirect
● RRI
● IOI

MRI
4 bits 12 bits
OPCODE PART ADDRESS PART
16 bits
OPCODE : Size is 4 bits

( it can represent maximum
16 distinguish codes :
0000, 0001, 0010,............1111)
4 bits 12 bits
I I I I
0 1 2 3 ADDRESS PART ( I4 to I15)
16 bits
OPCODE : First bit is being represented by ‘I0’ that

is called Mode bit ( used to distinguish between Direct and indirect MRI)
- Remaining three bits can represent 2 3 distinguish
codes : 000, 001, …110, 111
These codes ( 000 , 001,....... 110) [ Note 111 is kept
reserved for some other purpose ] can be assigned for
different arithmetic (i.e. Addition of two numbers )
logic (i.e. ANDing of two numbers) and for some
others operations ( i.e. Store the contents of AC in
some specific location of memory)
Addition of two numbers can be represented by
ADD, ANDING of two numbers can be represented by
AND While storing the contents of AC in memory can
be represented by STA).

These short forms such as ADD, AND and STA etc
(which help us to remember the operations ) are
called Mnemonics.
ACTIVITY : Find the Dictionary meaning of the term

‘ mnemonic’.

Different codes and Mnemonics ….
Instruction I =0 I=1 Remark
Hexadecimal Code Hexadecimal Code
qo 0H 8H AND
q1 1 9 ADD
q2 2 A LDA
q3 3 B STA
q4 4 C BUN
q5 5 D ….
q6 6 E ….
q7 Reserved for RRI and IOI

Thus, by using 3 bits ( I1, I2, I3) we have designed 8
codes ( 000, 001, 010, 011,100,101,110 and 111). Out
of these eight codes we have used first seven codes
for different MRI instructions. If we also include mode
bit (I0) then total 14 Memory Reference Instructions
(MRI) can be designed ( 7 direct and & indirect MRI)
Note : Codes 0111 ( 7H) and 1111 (FH) are reserved
for RRI and IOI respectively.

Non - MRI
4 bits 12 bits
I I I I
16 bits
If value of I1I2I3 is 111 i.e. 7H, then present instruction

is non-MRI i.e. either RRI or IOI
If mode bit is 0 i.e Io =0 then instruction is RRI
otherwise instruction is IOI
RRI
4 bits 12 bits
0 1 1 1 3 ADDRESS PART ( I4 to I15)
16 bits
If value of I0I1I2I3 is 0111 i.e. 7H, then present

instruction is RRI
In this case address part that is I4 to I15 will indicate
type of RRI
RRI
4 bits 12 bits

16 bits
7XXXH

IOI
4 bits 12 bits
1 1 1 1 3 ADDRESS PART ( I4 to I15)
16 bits
If value of I0I1I2I3 is 1111 i.e. FH, then present

instruction is IOI
In this case address part that is I4 to I15 will indicate
type of IOI
IOI
4 bits 12 bits

16 bits
FXXXH

E789H
F675 H
7896H

We have discussed, every instruction
has Fetch and Execution Cycle and some
also have indirect cycle in addition to
Fetch and Execution cycle

Instruction Cycles required
MRI - Direct Fetch, Execution
- Indirect Fetch,
Indirect,Execution
RRI Fetch, Execution
IOI Fetch, Execution
How to identify the type of instruction ?

Recall the case, discussed earlier
PC Memory
4096 X16
MAR
MBR
AC

Here we have added more registers : I , OPR & E
PC Memory
4096 X16
MAR
I : Mode bit Register/Flipflop
MBR OPR : OpCode Register
I OPR E : Extension of AC ( similar to
Carry Flag}
E AC

During fetch cycle instruction is fetched from memory and placed
in MBR. Op Code part of this instruction is divided into two parts :
Mode bit (I0) and OPR ( I1I2I3) and these are placed in I and OPR
registers respectively. ( Address part will remain in MBR for future
reference)
4 bits 12 bits
I0 I1 I2 I3 ADDRESS PART ( I4 to I15)
16 bits
OP code is divided into 2 parts

I0 : Mode bit will be placed in Register I
I1,I2,I3: will be placed in the OPR Register

Other Conditions
I OPR
3 X 8 Decoder q0 to q7 Control
and Logic Micro-instructions
Unit
2 X 4 Decoder f0 to t3
2 bit sequence C0 to C3
counter
2 X 4 Decoder
S
F R

Different Cycles
Execution of instruction consists of Fetch, Indirect
and Execution cycles. These cycles are designated by
c0, c1 and c2 respectively.
Note : Only MRI - indirect instruction requires all

these three cycles and remaining instructions
require only Fetch and Execution cycle.

C3 C2 C1 C0
2 X 4 Decoder
F R

Truth Table
F R Ci Remark
0 0 C0 Fetch Cycle
0 1 C1 Indirect Cycle
1 0 C2 Execution Cycle
1 1 C3 Interrupt Cycle

Each cycle is further divided into 4
smaller steps designated by t0, t1, t2 and
t3. During these steps control signals are
generated (called micro instruction) by
the Control and Logic Unit to achieve the
objective ( partial)
t3 t2 t1 t0
2 X 4 Decoder
2 Bit Sequence
Counter

2 bit sequence counter counts the input clock pulses.
00
01
10
11 , on the next input clock pulse it will reset
and then repeat the sequence as shown above.

OPR
q0
To control and Logic Unit

3 X 8 DECODER
q7

Truth Table for 3X8 Decoder
OPR qi = 1 Remark
000 q0 AND
001 q1 ADD
010 q2 LDA
011 q3 STA
100 q4 BUN
101 q5 ---
110 q6 ---
111 q7

AND ( q0 )
AND : Execution of this instruction will do the
ANDing of two words ; one is available in AC and
other is available in the given M/R location ( DIRECT).
AND address
AND F21 H
AND ABC H

ADD( q1 )
Execution of this instruction will ADD two words ;
address of one word is available in MBR and other
iavailable in the AC ( DIRECT) and result will be stored
in AC.
ADD address
ADD F21 H
ADD ABC H
LDA ( q2 )
Execution of this instruction will load the contents of
specified M/R location ( DIRECT) in the AC.
LDA address
LDA F21 H
LDA ABC H

STA ( q3 )
AC in the specified M/R location ( DIRECT).
STA address
STA F21 H
STA ABC H

BUN ( q4 )
specified M/R location ( DIRECT) in the PC
BUN address
BUN F21 H
BUN ABC H

Now we will see how micro instructions can be
generated for different operations discussed above

Micro- instruction for Fetch Cycle
C0,t0 : MAR ← PC
C0,t1 : MBR ← MMAR , PC ← PC + 1
C0,t2 : OPR ← MBR ( OP),
I ← MBR (I)
C0,t3 q7 I: F ← 0 , R ←1 //go to Indirect cycle
otherwise
F ← 1, R ← 0 //go to execution cycle

Unable to connect…
Please write feedback and leave

….
Micro- instruction for Indirct Cycle
C1,t0 : MAR ← MBR (AD)
C1,t1 : MBR ← MMAR
C1,t2 : NOP // No Operation
C1,t3 : F ← 1, R < ---- 0 //goto execution cycle

Micro- instruction for Execution Cycle
AND
q0 C2,t0 : MAR ← MBR ( AD)
q0C2,t1 : MBR ← MMAR
q0C2,t2 : AC ← AC . MBR
q0C2,t3 : F ← 0, R < ---- 0 //goto fetch cycle

ADD
q1 C2,t0 : MAR ← MBR ( AD)
q1C2,t1 : MBR ← MMAR
q1C2,t2 : E AC ← AC + MBR
q1C2,t3 : F ← 0, R ← 0 //go to fetch cycle

LDA
q2 C2,t0 : MAR ←---- MBR ( AD)
q2C2,t1 : MBR ←--- MMAR
q2C2,t2 : AC ←--- MBR
q2C2,t3 : F ←--- 0, R < ---- 0 //go to fetch cycle

STA
q3 C2,t0 : MAR ←---- MBR ( AD)
q3C2,t1 : MMAR ←--- AC
q3C2,t2 : NOP

BUN
q4 C2,t0 : PC ←---- MBR ( AD)
q4C2,t1 : NOP
q4C2,t2 : NOP

BUN
q4 C2,t0 : PC ←---- MBR ( AD)
q4C2,t1 : NOP
q4C2,t2 : NOP

REGISTER TRANSFER
Let A, B, C and D are 4 registers each of n bit
and connected to a common bus as shown in the
figure given below :

A C
B D

A C
B D

Objective :
Design a circuit to transfer the data from one
register to another without affecting the others

Say, we want to transfer (copy) the
contents of Register A to D
A C
B D

during the data transfer from register A to D,
registers B and C should be isolated from the bus as
shown below
A C
B D

is it easy to to disconnect the registers
physically as shown in the above figure ?

Needs mechanism which allow to
connect designated registers
electrically however remain others
isolated ( Note all are connected to the
bus physically)

One can achieve this objective by using three
state switches. They are also called Tri-state
buffer switches.

What is three state switch ?
Truth Table
Symbol
Enable Data IN Data Out
Data IN Data Out 0 0 High

Impedance
Condition
0 1 -do-
Enable (E) 1 0 0
Active High Tri state switch 1 1 1

Symbol
E = 1 (Short Circuit)
Data IN Data Out
E = 0 (Open Circuit )
Enable (E)
Active High Tri state switch

Truth Table
Symbol
Enable Data IN Data Out
Data IN Data Out 1 0 High

Impedance
Conditio
1 1 -do-
Enable (E)
0 0 0
Active Low Tri state switch 0 1 1

E = 0 (Short Circuit)
Data IN Data Out
E = 1 (Open Circuit )
Enable (E)
Active Low Tri state switch

4 - Bit Register
ENABLE
TO BUS

FROM
BUS
ENABLE
4 - Bit Register
From Bus
Enable to accept Data from Bus
Enable to transfer Data to Bus

4- Bit Register
To Bus

From Bus
LA
A
EA
To Bus

LA
A
EA

A C
B D

LA
EA
A C
LC
Ec
LB LD
EB
B D ED

Control word
CON = LAEALBEBLCECLDED

What will be the value of CON if someone wants to
transfer the data from A to D
Register A should be ready to transfer the data and

at the same time register D should be ready for
accept the data ( EA and LD should be active high and
remaining control signals should be low)
= 0 1 0 0 0 0 1 0 = 42 H
A to BUS CON = 40 H
D A can also be done in two
steps as shown below
Bus A
= 0 1 0 0 0 0 0 0 = 40 H
D Bus
= 0 0 0 0 0 0 1 0 = 02 H

Write the control words for transfer
the data from register B to C and A to C
LA
EA
A C
LC
EA
LB LD
EB
B D ED
B to C i.e. C B
Register B should be ready to transfer the data and

at the same time register C should be ready for
accept the data ( EB and LC should be active high and
remaining control signals should be low)
= 0 0 0 1 1 0 0 0 = 18 H
C B can also be done in two
Bus B
= 0 0 0 1 0 0 0 0 = 10 H
C Bus
= 0 0 0 0 1 0 0 0 = 08 H

A to C i.e. C A
Register A should be ready to transfer the data and

accepting the data ( EA and LC should be active high
and remaining control signals should be low)
= 0 1 0 0 1 0 0 0 = 48 H
C A can also be done in two
Bus A
= 0 1 0 0 0 0 0 0 = 40 H
C Bus
= 0 0 0 0 1 0 0 0 = 08 H

Write the control words for transfer the data from register B to
C ( Note that CON word is written differently)
LA
EA
A C
LC
Ec
LB LD
EB
B D ED
CON = LALBLCLDEAEBECED
B to C i.e. C B
Register B should be ready to transfer the data and

accepting the data ( EB and LC should be active high
and remaining control signals should be low)
= 0 0 1 0 0 1 0 0 = 24 H

C B can also be done in two
Bus B
= 0 0 0 0 0 1 0 0 = 04 H
C Bus
= 0 0 1 0 0 0 0 0 = 20 H

Write the control words for transfer the data amongst
registers
LA
EA
A C
LC
Ec
LB LD
EB
B D ED
Find the value of control words to transfer the data from
register B to C (i) in one step (ii) in two steps
LA
EA
A C
LC
Ec
LB LD
EB
B D ED
C B (in one step)
EB should be active low and LC should be active high and other

control signals should be inactive
= 0010 0010 =22H

C B (in two steps)
= 0 0 0 0 0 0 1 0 = 02 H ( B to Bus)
In second step data will be transferred from Bus to C
= 0 0 1 0 0 1 1 0 = 26 H ( Bus to C)

Find the value of control words to transfer the data from
register A to B (i) in one step (ii) in two steps
LA
EA
A C
LC
Ec
LB LD
EB
B D ED

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Madhav Institute of Technology & Science , Gwalior

COMPUTER SYSTEM ORGANIZATION (CSO) - 160311

B.Tech - II Year/ III Semester

Dr. R.K. Gupta, Deptt. of CSE 1

Dr. R.K. Gupta, Deptt. of CSE 2

Dr. R.K. Gupta, Deptt. of CSE 3

Dr. R.K. Gupta, Deptt. of CSE 4

Dr. R.K. Gupta, Deptt. of CSE 5

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● Proposed by John Von -Neumann in the year 1945.

Dr. R.K. Gupta, Deptt. of CSE 16

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It consists of number of registers :MAR, MBR/MDR,

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Program Counter (PC) points towards the memory

Memory Address Register (MAR) points towards the

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OPCODE PART + ADDRESS

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OPCODE PART + ADDRESS

OPCODE : Code of Instruction

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OPCODE PART ADDRESS PART