Walker PHD Thesis

Modulation and Control of
Multilevel Converters
by
Geoffrey R. Walker B.E.(Hons)
Department of Computer Science and Electrical Engineering
University of Queensland, QUEENSLAND 4072
This thesis is submitted in fulfilment of
the requirements of the degree of
Doctor of Philosophy
(Electrical Engineering)
at
The University of Queensland

November 16, 1999
ii
Declaration of Originality
The work presented in this thesis is my own work and to the best of my knowledge
and belief original, except as acknowledged in the text. The material contained in
this thesis has not been submitted, either in whole or in part, for a degree at The
University of Queensland or any other University.
Geoff Walker
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Acknowledgements
There are many people who deserve my sincerest thanks. I can only name some of
those very many people here. If you are one of the many more anonymous friends,
you will know that I have valued your friendship and support during the course of
this study. Thank you.
I would like to thank Professor Gerard Ledwich for his inspiration and direction
as my supervisor and friend. Professor Matt Darveniza, Dr. Ashwin Kambadkone
and Dr. Tapan Saha have also assisted in my supervision during the course of my
candidature.
Gordon Wyeth, Pat Bellett, Ed LoGuidice and Keith Hoffman have been my
closest friends at University. Thanks for all the ideas and laughter shared over a
cup of coffee. This isn’t to dismiss the wonderful friendships I have also formed with
the office staff, technical staff, postgraduates, undergraduates and other academics.
You have together been the reason I have always preferred to work at University
rather than from home.
My family (Mum, Dad, Lloyd, Peter, Lorraine) and all my church friends who
are as close as family have been a constant source of encouragement and love. Of
course most of all I must thank my wife Maria for her support, love, and above all
patience.
Above all I thank God. My life has always been full of abundant blessing. I can
see His guiding hand clearly at work as look back across my life. His love, forgiveness
and peace are real to me everyday. It is my prayer that God will be seen in me and
my work, including this thesis, and the glory will be given to God.
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Abstract
This thesis aims to extend the body of knowledge about the modulation and control
of converters to cover multilevel converters.
A general definition of a (power) converter, and subsequently a multilevel con-

verter, is given based on a unified converter theory. Different converter structures are
shown to have common features under this unified set of rules. The most common
multilevel topologies found in the published literature are examined and compared.
Some other example converters are also developed theoretically from the basic defi-
nition and by using the concept of duality.
Starting from the essential requirements, the different approaches to switching

power converter modulation are explained and compared. In particular, aspects of
modulation which are required or desirable for multilevel converters are discussed.
Sine-triangle carrier modulation is identified as the most promising technique to
pursue for both technical and pedagogical reasons.
Natural and uniform sampled sine-triangle modulation are examined and con-
trasted in detail. The modulators’ transfer function and spectral properties are
examined mathematically, and then confirmed both with simulations and software
and hardware implementations. The natural sampling process is shown to have a
flat, distortionless transfer function, which uniform sampling cannot achieve. Uni-
form sampling is invariably implemented digitally, either in software or hardware,
with many associated advantages, while natural sampling does not lend itself to a
digital implementation. The advantages and short-comings of each technique are
vii
generally exacerbated by multilevel converters. A digital implementation of natu-
rally sampled PWM would seem the perfect solution.
Re-sampled Uniform, a technique for achieving natural like sampling digitally is

suggested. The success of this approach is demonstrated as improvements are shown
for three implementations, one in software and two in hardware. Some unexpected
effects are commented on in the subsequent analysis of the results.
Further improvements to carrier based PWM are possible by randomising the

carrier period, and by modulating the zero sequence component in a three phase
converter. The carrier period can be varied without causing distortion of the desired
modulating waveform. It blurs the sharp spectral harmonic terms associated with
the carrier into a continuous spectrum with lower peak amplitudes. The successful
technique for generating multilevel random modulation also demonstrates that the
separate sub-cycles can be treated as PWM switch periods in their own right. This
has significance for space vector modulation, re-sampled uniform, and alternative
modulation techniques.
In a three phase converter with no neutral connection, any voltage which is com-
mon to all three phases does not cause any current to flow. Such a zero sequence
component may be deliberately introduced to increase the maximum possible mod-
ulation depth and hence converter utilisation, lower the switching rate, and possibly
lower distortion. A number of possible zero sequence components for multilevel
modulation are tested using simulations. Only the increase in maximum modula-
tion depth is a significant advantage. The distortion (spectral) benefits are minimal,
and discontinuous switching cannot be implemented in some topologies.
These different approaches to improving the modulation of multilevel converters

have been applied using sine-triangle PWM. The outcomes of this research can be
generalised to other methods of PWM, and also to conventional two-level converters.
viii
Original contributions
This thesis offers a definition of the term “multilevel converter”.
It reviews all currently published multilevel converter structures without bias,

offering the advantages and disadvantages of each. Additionally, it proposes a num-
ber of new multilevel topologies based on the theory of duals.
The many possible pulse width modulation (PWM) strategies are reviewed with
particular regard to their comparative suitability for the modulation of a general
multilevel converter. Carrier based techniques are shown to be the clear choice for
both technical and pedagogical reasons.
Natural and uniform sampled PWM are compared again with a specific focus
on their relative suitability for multilevel modulation. The new demands placed on
these PWM techniques by the new opportunities opened by multilevel converters
are examined. The mathematical expressions for these PWM techniques, extended
to describe the multilevel waveforms, are examined at the very low (even fractional)
pulse numbers which only become relevant for multilevel converters. The need for
a digital implementation of natural sampling is demonstrated.
Three different implementations of this new technique called “resampled uni-

form” are proposed, simulated, develeped, implemented, measured and analysed.
The first is a software technique implemented on a microcontroller. The other two
are hardware techniques — one is an EPROM based look up table, and the second
is a digital counter / comparator implementation in a large programmable logic
device. Their advantageous use for multilevel converters is demonstrated. Their rel-
ix
ative merits are contrasted. Many examples of the flexibility of the EPROM based
hardware approach are offered.
The technique for the extention of random modulation to multilevel converters

is developed, simulated, implemented, and measured. The digital programmable
logic device implementation of resampled uniform is randomised by varying its clock
frequency at the beginning of each new cycle. Results are gathered from a low power
five level flying capacitor converter, in addition to the logic level based results. These
additional results show that the power converter does not cause significant distortion
of the logic level signals at the output of the multilevel modulator.
Zero sequence vectors have been applied to conventional three phase converters,
but not previously to multilevel converters. Multilevel converters offer new degrees
of freedom to the creation of zero sequence vectors. The application of zero sequence
vectors to multilevel converters is simulated and the results analysed.
x
Publications
G. Walker, G. Ledwich, “ Bandwidth Considerations for Multilevel Converters”

IEEE Transactions on Power Electronics, Vol.14, No.1, pp. 74–81, Jan/Feb 99.
G. Walker, G. Ledwich, “ Implementing Natural PWM Digitally ” Proceedings of the

Australasian Universities Power Engineering Conference, Melbourne — Australia,
Oct 96. Vol.1, pp. 169–174.
G. Walker, G. Ledwich, “ An Isolated MOSFET Gate Driver ” Proceedings of the

Australasian Universities Power Engineering Conference, Melbourne — Australia,
Oct 96. Vol.1, pp. 175–180.
G. Walker, G. Ledwich, “ Bandwidth Considerations for Multiple Modulator Con-

verters” Proceedings of the Australasian Universities Power Engineering Conference,
Adelaide — Australia, Sept 94. Vol.3, pp. 514–519.
xi
xii
Contents
Declaration of Originality iii
Acknowledgements v
Abstract vii
Original contributions ix
Publications xi
List of Figures xviii
1 Introduction 1
1.1 Thesis Organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 The Multilevel Converter 5
2.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.1 Unified Converter Theory . . . . . . . . . . . . . . . . . . . . 5
2.1.2 Inverter or Rectifier? Voltage or Current Source? . . . . . . . 6
2.1.3 The General Multilevel Converter . . . . . . . . . . . . . . . . 8
2.1.4 The Traditional Multilevel Converter . . . . . . . . . . . . . . 10
2.2 Multilevel Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
xiii
2.3 Three Phase Multilevel Voltage Source Converters . . . . . . . . . . . 11
2.3.1 Transformer/Inductor summed Multiple Bridge Converter . . 12
2.3.2 Series Connected Isolated Multiple Bridge Converter . . . . . 16
2.3.3 Neutral Point Clamped (NPC) Converter . . . . . . . . . . . . 17
2.3.4 Flying Capacitor Converter . . . . . . . . . . . . . . . . . . . 21
2.4 Current Source Converters . . . . . . . . . . . . . . . . . . . . . . . . 23
2.4.1 Multilevel Current Converter Topologies . . . . . . . . . . . . 24
2.5 Applications of Multilevel Converters . . . . . . . . . . . . . . . . . . 27
2.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3 Pulse Width Modulation Candidates for Multilevel 29
3.1 A Definition of Modulation . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2 Review of PWM Techniques . . . . . . . . . . . . . . . . . . . . . . . 30
3.2.1 Requirements Common to All PWM Techniques . . . . . . . . 30
3.2.2 Selective Harmonic Elimination / Minimisation PWM . . . . . 32
3.2.3 Hysteresis Band PWM . . . . . . . . . . . . . . . . . . . . . . 33
3.3 Carrier Based PWM Techniques . . . . . . . . . . . . . . . . . . . . . 35
3.3.1 Fundamental – Carrier waveform relationships . . . . . . . . . 37
3.3.2 Modulation Variations . . . . . . . . . . . . . . . . . . . . . . 39
3.3.3 Variable and Random Period PWM . . . . . . . . . . . . . . . 41
3.4 Summary: The Best Modulation Option for Multilevel . . . . . . . . 43
4 Multilevel Carrier Based PWM 45
4.1 Carrier Based PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.2 Naturally Sampled PWM . . . . . . . . . . . . . . . . . . . . . . . . . 47
xiv
4.2.1 Constant (DC) Modulation . . . . . . . . . . . . . . . . . . . 47
4.2.2 Sinusoidal Natural Modulation . . . . . . . . . . . . . . . . . 48
4.3 Uniformly Sampled PWM . . . . . . . . . . . . . . . . . . . . . . . . 50
4.3.1 Uniform PWM Spectrum . . . . . . . . . . . . . . . . . . . . . 51
4.3.2 Extension to Multiple Modulators . . . . . . . . . . . . . . . . 51
4.4 Modulator Implementation . . . . . . . . . . . . . . . . . . . . . . . . 54
4.4.1 Experimental Hardware . . . . . . . . . . . . . . . . . . . . . 57
4.4.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.5 Input signal Attenuation, Distortion and Phase delay . . . . . . . . . 60
4.5.1 Experimentally Gathered Modulator Transfer Functions . . . 64
4.5.2 The Slew Rate Limit . . . . . . . . . . . . . . . . . . . . . . . 65
4.5.3 Lower Sidebands . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.5.4 Synchronous Natural Modulation . . . . . . . . . . . . . . . . 69
4.5.5 Overmodulation . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5 Digital Natural — Re-sampled Uniform 73
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.2 Re-sampled Uniform . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.3 Microcontroller Software Implementation . . . . . . . . . . . . . . . . 77
5.3.1 Microcontroller Re-sampled PWM Results . . . . . . . . . . . 78
5.4 Gate Array Implementation . . . . . . . . . . . . . . . . . . . . . . . 80
5.4.1 Results — Gate Array Implementation . . . . . . . . . . . . . 83
5.5 EPROM Based Implementation . . . . . . . . . . . . . . . . . . . . . 87
xv
5.5.1 Carrier Variations . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.5.2 Results of EPROM Implementation . . . . . . . . . . . . . . . 92
5.5.3 Bandwidth improvent vs. resampling ratio . . . . . . . . . . . 97
5.6 Conclusions and Applications . . . . . . . . . . . . . . . . . . . . . . 101
6 Random Carriers and Zero Vectors 103
6.1 Extending Random Modulation Techniques to Multilevel . . . . . . . 103
6.1.1 Matlab Experiments . . . . . . . . . . . . . . . . . . . . . . . 104
6.1.2 A Different Perspective . . . . . . . . . . . . . . . . . . . . . . 106
6.1.3 Hardware Generation of Random Modulation . . . . . . . . . 113
6.1.4 Flying Capacitor Converter Results . . . . . . . . . . . . . . . 114
6.2 Multilevel Zero Sequence Waveforms . . . . . . . . . . . . . . . . . . 117
6.2.1 Discontinuous Modulation . . . . . . . . . . . . . . . . . . . . 118
6.2.2 Adding a Third Harmonic . . . . . . . . . . . . . . . . . . . . 121
6.2.3 Pulse Centring Algorithms . . . . . . . . . . . . . . . . . . . . 121
6.2.4 Assessment by Distortion Analysis . . . . . . . . . . . . . . . 124
6.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
7 Conclusion 129
7.1 Multilevel Converter Topologies . . . . . . . . . . . . . . . . . . . . . 129
7.2 Pulse Width Modulation Techniques . . . . . . . . . . . . . . . . . . 130
7.3 Natural and Uniform Sampled Carrier PWM . . . . . . . . . . . . . . 131
7.4 Digital Natural — Re-sampled Uniform . . . . . . . . . . . . . . . . . 132
7.5 Random Modulation for Multilevel Converters . . . . . . . . . . . . . 133
7.6 Three Phase Zero Vector Experiments . . . . . . . . . . . . . . . . . 134
xvi
7.7 Future Research . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
A Spectral Analysis 137
A.1 The Fourier Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
A.2 Fourier analysis of double edge pulse width modulation . . . . . . . . 138
A.2.1 Constant (dc) modulation . . . . . . . . . . . . . . . . . . . . 138
A.2.2 Naturally sampled Sinusoidal modulation PWM . . . . . . . . 139
A.2.3 Uniformly sampled Sinusoidal modulation PWM . . . . . . . . 141
A.3 Jump Function Fourier Analysis . . . . . . . . . . . . . . . . . . . . . 142
B Matlab Scripts and C Code 145
B.1 Matlab Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
B.1.1 Jump function analysis code . . . . . . . . . . . . . . . . . . . 145
B.1.2 Random and zero sequence modulation scripts . . . . . . . . . 147
B.1.3 PWM EPROM Creation scripts . . . . . . . . . . . . . . . . . 151
B.2 80C196 micro-controller code . . . . . . . . . . . . . . . . . . . . . . 152
B.2.1 tria.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
B.2.2 upwmd.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
B.2.3 upwm4.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
B.2.4 upwm4o.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
B.3 Simulation C code . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
B.3.1 hdn4si.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
C Circuits 163
C.1 Natural, 80C196 and EPROM modulators . . . . . . . . . . . . . . . 163
xvii
C.2 DSP-Flex FLEX8820 configuration . . . . . . . . . . . . . . . . . . . 167
Bibliography 172
xviii
List of Figures
2.1 Voltage source / current source converters . . . . . . . . . . . . . . . 7
2.2 The matrix converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Voltage source, current source and three level matrix converters . . . 9
2.4 Transformer coupled multiple bridge . . . . . . . . . . . . . . . . . . 13
2.5 Isolated flying multiple bridge . . . . . . . . . . . . . . . . . . . . . . 17
2.6 Diode clamped multilevel converter . . . . . . . . . . . . . . . . . . . 18
2.7 Diode clamped converter — voltage sharing not guaranteed . . . . . 19
2.8 The flying capacitor multilevel converter . . . . . . . . . . . . . . . . 22
2.9 Multilevel flying capacitor converter duals . . . . . . . . . . . . . . . 24
2.10 Isolated flying bridge converter dual circuit . . . . . . . . . . . . . . . 25
2.11 Duality corrupted to meet desired outcome . . . . . . . . . . . . . . . 25
3.1 Harmonic Elimination PWM (SHE-PWM) . . . . . . . . . . . . . . . 33
3.2 Hysteretic PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.3 Time and Frequency domain comparison of PWM techniques . . . . . 36
3.4 Natural PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.5 Uniform PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.1 Trailing edge / Double edge carrier modulation . . . . . . . . . . . . 46
xix
4.2 A selection of linear carrier waveforms . . . . . . . . . . . . . . . . . 46
4.3 Natural sampled PWM timing . . . . . . . . . . . . . . . . . . . . . . 47
4.4 Natural and Uniform sampling . . . . . . . . . . . . . . . . . . . . . . 50
4.5 Creation of a Multilevel Natural PWM waveform . . . . . . . . . . . 52
4.6 49 Level converter example - ideal . . . . . . . . . . . . . . . . . . . . 53
4.7 49 Level converter example - with noise . . . . . . . . . . . . . . . . . 55
4.8 Uniform PWM hardware implementation . . . . . . . . . . . . . . . . 56
4.9 PWM spectra, Natural sampling, M = 0.9, N = 9 . . . . . . . . . . . 58
4.10 PWM spectra, Uniform sampling, M = 0.9, N = 9 . . . . . . . . . . 58
4.11 The Bessel Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.12 Natural PWM transfer function, waterfall plots . . . . . . . . . . . . 62
4.13 Uniform PWM transfer function . . . . . . . . . . . . . . . . . . . . . 62
4.14 49 Level converter example - Uniform sampled . . . . . . . . . . . . . 63
4.15 Chirp signal used for evaluating modulator transfer function . . . . . 65
4.16 Natural PWM transfer function . . . . . . . . . . . . . . . . . . . . . 66
4.17 Uniform PWM transfer function . . . . . . . . . . . . . . . . . . . . . 66
4.18 PWM Radio transmitter . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.1 Symmetric, asymmetric and re-sampled uniform . . . . . . . . . . . . 76
5.2 Implementational issues of re-sampling . . . . . . . . . . . . . . . . . 77
5.3 80c196 microcontroller re-sampled uniform — five level waveforms . . 79
5.4 80c196 microcontroller re-sampled uniform — averaged . . . . . . . . 79
5.5 80c196 microcontroller re-sampled uniform — five level sawtooth tran-

sient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
xx
5.6 The operation of the programmable gate array implementation of re-
sampled uniform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.7 The programmable gate array implementation of re-sampled uniform

– Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.8 Re-Sampled uniform modulator transfer functions vs. re-sampling ratio 83
5.9 FPGA re-sampled uniform — transfer function vs. modulation depth,

rsr = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

rsr = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

rsr = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5.12 An alternative derivation of the mathematical description of the mul-

tilevel PWM waveform. . . . . . . . . . . . . . . . . . . . . . . . . . 86
5.13 Re-Sampled uniform PWM EPROM based hardware block diagram . 88
5.14 Re-Sampled uniform PWM EPROM based hardware — EPROM

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.15 EPROM re-sampled uniform results — Examples . . . . . . . . . . . 94
5.16 EPROM re-sampled uniform results — Sine waves . . . . . . . . . . . 94
5.17 EPROM re-sampled uniform results — sawtooth demonstrating tran-

sient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.18 Sensible choice of re-sampling ratio . . . . . . . . . . . . . . . . . . . 95
5.19 Sensible choice of re-sampling ratio — spectral confirmation . . . . . 96
5.20 Success of re-sampling for pulse numbers less than one. . . . . . . . . 97
xxi
5.23 EPROM re-sampled uniform — transfer function vs. modulation
depth, rsr = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.24 EPROM re-sampled uniform — transfer function vs. modulation

depth, rsr = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.1 Matlab generation of random carrier period vectors . . . . . . . . . . 104
6.2 Multilevel spectra — Two separate random carrier pairs . . . . . . . 106
6.3 Multilevel spectra — Two identical random carrier pairs, one delayed;
Synchronous and Asynchronous . . . . . . . . . . . . . . . . . . . . . 107
6.4 Randomising the sub-cycle period . . . . . . . . . . . . . . . . . . . 108
6.5 Multilevel spectra — Randomising the sub-cycle period . . . . . . . 109
6.6 Different modulation depths (M = 0.9, 0.2) and pulse numbers (N =

9, 1.8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.7 Different random period deviations, from 2% to 20% . . . . . . . . . 112
6.8 Superiority of multilevel for small modulation depths . . . . . . . . . 113
6.9 Hardware random PWM spectra, varying random deviation . . . . . 115
6.10 Hardware random modulation spectra, varying M, N . . . . . . . . . 115
6.11 Flying capacitor hardware – Different modulation depths (M = 0.9, 0.2)

and pulse numbers (N = 9, 1.8) . . . . . . . . . . . . . . . . . . . . . 116
6.12 Zero sequence example — the modulating waveforms . . . . . . . . . 119
6.13 Zero sequence example — the PWM waveforms . . . . . . . . . . . . 119
6.14 Zero sequence example — the PWM spectra . . . . . . . . . . . . . . 119
6.15 Choosing different zero sequence waveforms . . . . . . . . . . . . . . 122
6.16 Modulating waveforms — maximum modulation depth . . . . . . . . 123
6.17 PWM waveforms — maximum modulation depth . . . . . . . . . . . 123
xxii
6.18 PWM spectra — maximum modulation depth . . . . . . . . . . . . . 123
6.19 Distortion plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
A.1 Natural sampled PWM timing . . . . . . . . . . . . . . . . . . . . . . 138
xxiii
xxiv
Chapter 1
Introduction
Conventional power electronic converters can switch each input or output connection
between two possible voltage (or three possible current) levels, namely those of the
internal DC voltage (or current) link. Multilevel converters can switch their outputs
between many voltage or current levels, and have multiple voltage or current sources
(or simply capacitors or inductors) as part of their structure.
A multilevel converter can be implemented in many different ways, each with

attendant advantages and disadvantages. The simplest techniques involve the paral-
lel or series connection of conventional converters to form the multilevel waveforms.
More complex structures effectively insert converters within converters. Whatever
approach is chosen, the subsequent voltage or current rating of the multilevel con-
verter becomes a multiple of the individual switches, and so the power rating of the
converter can exceed the limit imposed by the individual switching devices.
The most common initial application of multilevel converters has been in trac-
tion, both in locomotives and track-side static converters [60]. More recent appli-
cations have been for power system converters for VAR compensation and stability
enhancement [21], active filtering [71], and most recently for medium voltage induc-
tion motor variable speed drives [25].
With multiple switches and hence degrees of freedom, the harmonic performance
2 Chapter 1. Introduction
of the converter can also be improved. Even with low pulse numbers (switching
rates), the performance of the multilevel converter can be useful, even impressive.
The modulation and control of multilevel converters is the focus of this work.
1.1 Thesis Organisation
This thesis aims to extend the body of knowledge about the modulation and con-
trol of converters (fairly complete) to cover multilevel converters (still developing).
This first chapter explains the motivation and content of this thesis and presents a
summary of the content of each of the chapters.
In the second chapter, a basic, general definition of a (power) converter is given

based on a simple set of requirements. Different converter structures are shown to
have common features under this unified set of rules. These are then extended to
define a multilevel converter. Some examples of the most common multilevel topolo-
gies found in the published literature are given and their relative merits discussed.
Some other example converters are developed theoretically from the basic definition.
The different approaches to switching power converter modulation are explained

and compared in the third chapter, again starting from the most basic requirements.
The different techniques of pulse width modulation are examined with references to
the literature — off line or pre-calculated techniques, hysteretic and carrier based
modulation. In particular, aspects of modulation which are required or desirable for
multilevel converters are discussed.
Two specific modulation techniques, natural and uniform sampled sine-triangle

modulation are contrasted and examined in detail in chapter four. A mathemati-
cal examination of the two PWM waveforms shows that natural sampling process
has a flat, distortion-less transfer function, which uniform sampling cannot achieve.
Uniform sampling however is invariably implemented digitally, either in software
or hardware, with many associated advantages. Natural sampling does not lend
itself to a digital implementation. These differences are generally exacerbated by
1.1. Thesis Organisation 3
multilevel converters. The advantages and short-comings of each are given as the
conclusion, to lead into the next chapter.
Some specific approaches taken to improve multilevel sine-triangle modulation

are then detailed in chapters five and six. In chapter five, a technique for achieving
natural like sampling digitally is suggested. The success of this approach is demon-
strated as improvements are shown for three implementations, one in software and
two in hardware.
Further improvements to carrier based PWM are possible by randomising the

carrier period and modulating the zero sequence component in a three phase con-
verter. Both ideas are developed and tested in chapter six. The carrier period can be
varied without causing distortion of the desired modulating waveform. It blurs the
sharp spectral harmonic terms associated with the carrier into a continuous spec-
trum with lower peak amplitudes. The successful technique for generating multilevel
random modulation also demonstrates that the separate sub-cycles can be treated
as PWM switch periods in their own right. This has significance for space vector
modulation, re-sampled uniform and alternative modulation techniques.
In a three phase three wire system where the converter has no neutral connection,
any voltage which is common to all three phases does not cause any current to flow.
Such a zero sequence component, or zero vector, introduces a degree of freedom
which may be used to improve the performance of the converter. The techniques of
applying zero sequence components to two level converters reported in the literature
are extended to the multilevel case.
The different approaches to improving the modulation of multilevel converters

have been applied using sine-triangle PWM. The outcomes of this research can be
generalised to other methods of PWM.
The conclusion of this study is that the modulation of multilevel converters is

really not a discipline in its own right, but only an extension of converter modulation
generally. Many of the new approaches developed and demonstrated in this thesis
4 Chapter 1. Introduction
were born from a need created by multilevel converters. However these techniques
can equally be re-applied to two level converters.
Chapter 2
The Multilevel Converter
2.1 Definitions
Before undertaking a discussion on the modulation and control of multilevel con-

verters, a definition of what constitutes a multilevel converter is required. In turn,
a definition of the term converter is needed.
2.1.1 Unified Converter Theory
In the preface of his book Switching Power Converters [70], Wood introduces the
concept of a unified converter theory. There he states: “Most traditional views
of the field have seemed somewhat disjointed; converters were largely regarded as
related only because they all use semiconductor switches and have certain topological
similarities. . . . the view expounded herein (is that) switching power converters are
related by function and behaviour; their basic characteristics do not in any way
depend on the types of switches used, nor on the applications to which they are put,
nor on the topologies in which they are realized.”.
According to this unified theory, any power electronic converter can be viewed
as a matrix of switches which connects its input nodes to its output nodes. These
6 Chapter 2. The Multilevel Converter
nodes may be either DC or AC, and either inductive or capacitive; and the power
flow may be in either direction.
Two obvious restrictions are enforced by some basic laws of electricity.
• If one set of nodes (input or output) is inductive, the other set must be ca-
pacitive, so as not to create a cut set of voltage or current sources when the
switches are closed.
• The combination of open and closed switches should never open circuit an
inductor, or short circuit a capacitor.
2.1.2 Inverter or Rectifier? Voltage or Current Source?
This unified set of converters is generally broken into a number of subsets.
The term rectifier is used when the power flow is predominately from the AC
port to the DC port and the term inverter is used when power flow is predominately
from the DC port to the AC port. The term converter is used either when there
is no predominant direction of power flow or as a general term to encompass both
rectifiers and inverters.
In a Voltage Source Converter (VSC), the DC port is the capacitive port and
is voltage stiff (i.e. a large DC bus capacitor). The voltages in such a converter are
well defined by this port and are generally considered independent of the converter’s
operation. The value of the AC side inductance is comparatively small and modu-
lation of the converter controls these AC side inductor currents. Should the voltage
source converter be responsible for the control of the DC bus capacitor voltage, then
this voltage is indirectly controlled by controlling the net current flow in the capac-
itor. The switches in such a converter must block a unidirectional voltage, but be
able to conduct current in either direction if bidirectional power flow is desired.
The converse is true in a Current Source Converter (CSC) — the DC port is

inductive and current stiff. The current in this port (and hence the converter)
2.1. Definitions 7
is well defined and slow to change. The voltage (particularly at the AC port) is
considered the variable directly controlled by the converter modulation. Since the
AC port usually has significant line or load inductance, line to line capacitors must
be placed on the AC port. The switches must block either voltage polarity, but are
only required to conduct current in one direction. This naturally suits thyristors
and symmetrical GTOs.
Figure 2.1: A voltage source rectifier - inverter cascade (top) and a current source
rectifier - inverter cascade (bottom).
Since the AC line and AC motor loads are both inductive, Voltage Source Rec-
tifier – Inverter cascades (Fig. 2.1) are usually used for small and now increasingly
for large motor drives and similar applications, as GTOs and IGBTs have matured.
Larger converters have traditionally been current source converters, both because
this best suits the characteristics of the thyristors and because it requires a large
DC bus inductor, which was preferred to a large capacitor.
Some converters do not easily fall, or cannot be placed into either category. The
matrix or Venturini converter [1] is one example (Fig. 2.2). Both input and output
ports are AC, and the definition of voltage stiff or current stiff (and hence voltage
or current source) becomes somewhat arbitrary. Both input and output ports are
Figure 2.2: The matrix converter, with one possible implementation of the bidi-
rectional switches.
AC, and neither port can be considered as a steady dc source, whether voltage or
current.
2.1.3 The General Multilevel Converter
The next refinement is to define the meaning of multilevel. The following definition
of a multilevel converter is offered:
A multilevel converter can switch either its input or output nodes (or
both) between multiple (more than two) levels of voltage or current.
The term “two-level” will be used where it is necessary to refer specifically to a

converter which is not multilevel.
This simple definition is deliberately quite broad and inclusive, in keeping with
the spirit of the unified converter theory. For example, the multi-phase matrix
converter (Fig. 2.2) is, strictly speaking, a multilevel converter, according to this
definition. Consider the three phase to three phase matrix converter, with voltage
source inputs and an inductive load. Any single output can be switched to one of
three different voltage levels (the voltages of the three input phases) and similarly,
any input can be switched to one of four current levels (including zero).
2.1. Definitions 9
In this preceding example, both the input and the output nodes are AC peri-
odic varying quantities and so these levels can only be considered stationary for an
interval much shorter than their AC period.
Figure 2.3: The current source converter (top right), voltage source converter
(bottom left) and a simple three level voltage source converter (bottom right)
can all be derived from the general topology of the matrix converter (top left)
Both the voltage source and current source converters can be derived from the
general matrix converter by setting one port to be either a two terminal DC voltage
stiff or DC current stiff port [70, 30]. Retaining the third terminal leads to a simple
and more conventional multilevel converter (Fig. 2.3).
Note that now one of the ports has been made DC and voltage or current stiff,
only one port will experience the multilevel stepped waveforms. The other will still
have a continuous waveform similar to that of an equivalent two level converter.
For example, a converter with an appropriate structure may create a stepped

multilevel voltage waveform at the inductive nodes, but will always have a continuous
voltage waveform at its capacitive nodes. Similarly a different converter may create
a stepped multilevel current waveform at its capacitive nodes, but must have a
continuous current waveform at its inductive nodes.
2.1.4 The Traditional Multilevel Converter
The traditional understanding of what constitutes a multilevel converter follows this

more narrow definition. One of the ports has multiple (more than two) voltage or
current stiff DC nodes or terminals, while the second port has a conventional single
or three phase set of terminals which are switched to these multiple levels.
Most multilevel converters discussed in the literature step between multiple volt-
age levels. This is usually the most useful configuration for a high power converter,
as reducing conduction losses in both converter and machines will always favour in-
creasing the voltage rating rather than the current rating of the converter. Also as
power levels increase, the input and output voltage levels presented to the converter
increase. The structure of these multilevel converters place the switches in series to
share the duty of blocking these higher voltages.
Equally however, for high current applications, many switches can be placed
in parallel, with their current summed by inductors. When switched separately,
multilevel current waveforms result [2].
As expected, multilevel converters can be DC-DC, DC-AC and as explained, in

the broadest sense, even AC-AC.
2.2. Multilevel Topologies 11
2.2 Multilevel Topologies
Generally multilevel topologies can be divided into two groups, although in some
cases the dividing line is indistinct. The first approach relies on summing the outputs
of a number of conventional two-level converters, to produce a resultant multilevel
output. The second group replaces the two-level switch structure with a multi-
level switch topology within an otherwise conventional converter. These two groups
will be distinguished by the terms multi-bridge converter and multilevel converter
respectively.
Any of the basic DC-DC converters (buck, boost, buck-boost, Cuk) can be
extended to a multilevel topology. Often these are not called or perhaps even recog-
nised as multilevel converters, but rather simply described as, for example, par-
allelled converters with interleaved switching instants. Two recent examples cited
are multilevel boost converters used for power factor correction [48, 34]. In both of
these examples, the switches are effectively placed in parallel and their contributions
summed by separate boost inductors. They present multilevel current waveforms to
the input and reduced voltage ripple at the output.
Multilevel DC-AC converters range from the simplest single phase, full bridge
driven with unipolar voltage switching [49] to complex multi-phase converters. These
are the most commonly recognised and reported multilevel converters and will be
further categorised and referenced in the next section.
Even multilevel AC-AC matrix converters have been shown to be at least theo-
retically possible [45].
2.3 Three Phase Multilevel Voltage Source Con-
verters
At this point in the chapter, we will narrow the focus to that of three phase volt-
age source multilevel converters. Although this may seem somewhat limiting, it
encompasses most of the higher power multilevel converters both in the published
literature and in actual use. There are some examples of single phase converters
functioning as AC-DC switching rectifiers, either in traction, computer or telecom-
munications power supplies. These Power Factor Correction rectifiers have lower
inherent distortion and require less filtering because of their multilevel topology.
Subsequently in section 2.4, multilevel current source converters will be consid-

ered.
There are four main voltage source DC-AC multilevel topologies which have
been distinguished here and in the literature. These are:
1. Multiple bridge using transformer or inductor summing;
2. Multiple bridge using direct series connection;
3. Multilevel diode-clamped converter; and
4. Multilevel flying capacitor converter.
Each of these will be examined in turn. Each of the diagrams presented are of a
five-level converter, which can produce a nine-level phase to phase voltage waveform.
2.3.1 Transformer/Inductor summed Multiple Bridge Con-
verter
As the title suggests, these multilevel converters are simply a number of conven-
tional two-level bridges, whose inputs or outputs are summed using transformers or
inductors. The multiple transformer secondaries force voltage sharing between the
switches (Fig. 2.4).
The most common and well known example of a multi-bridge converter is the
twelve pulse thyristor converter, well covered in most power electronic textbooks [49].
Harmonic cancellation in these converters is achieved through the phase displace-

ment of the voltage waveforms of the star and delta transformer secondaries. This
2.3. Three Phase Multilevel Voltage Source Converters 13
Figure 2.4: A five-level Transformer coupled multiple bridge, which produces nine
level phase-phase waveforms on the transformer primary.
30◦ phase shift between transformer secondaries allows identical secondary switching
instants and current waveforms to appear interleaved on the transformer primary.
A series connection is used for HVDC; a parallel connection for high current ap-
plications such as electrolysis and electro-plating. The technique can and is extended
to many bridges each with a transformer secondary connection of the appropriate
phase shift to achieve cancellation of the further low order harmonics in the pri-
mary [53, 70]. By clever connection of the transformer primaries, current as well as
voltage sharing can be ensured [52].
A good example of the next degree of complexity and flexibility is seen in a 10

MW battery energy storage plant [66]. The GTO converters operate in square wave
mode and still rely on the transformer phasing for harmonic cancellation. However
because forced commutation is used, now both the magnitude and the phase (real
and reactive power) can be separately controlled. An extension of this approach to
48 pulse operation [27] is achieved by eight GTO bridges operating in square wave
mode, with reliance on the transformer for harmonic cancellation.
The cancellation of switching harmonics can also be achieved by switching strate-

gies, rather than relying on the transformer secondaries for the necessary phase
shifting. The simplest case — the series or parallel connection of two PWM bridges
— has been investigated by a number of researchers [37, 43]. By the use of ap-
propriate PWM modulation for each bridge, the odd multiples of the PWM carrier
and sidebands, including the first cluster, were entirely removed from the output
spectrum. This improvement is better than can be achieved by merely doubling the
carrier frequency as the carrier which remains has a lower amplitude.
A particularly good example of a six bridge, transformer summed multilevel

converter is used as an active filter for arc furnace static flicker compensation [71].
The AC connections of these bridges are summed by separate transformer secon-

daries, which allows either a series or parallel DC connection. Since the transformer
no longer provides phase shifting, it may seem possible to remove the transformer
entirely and place the converters directly in parallel (for a parallel connection). How-
ever, while no difference exists between the desired input and output components of
the two converters, the undesired switching components are by definition exactly out
of phase. Kirchoff’s laws would be violated if the converters were directly connected.
The solution is to use inter-phase reactors (current sharing reactors) or inter-

phase transformers on either the input or output of the converters [70]. Although
these reactors see the full combined converter current (and so have similar copper
volume and copper losses), they only experience the difference in voltage between
the converters. The volts-second component of this voltage is smaller and so the iron
content of these reactors can be reduced in comparison to the transformers which
would be required for full isolation. Normally the inductors are placed on the AC
side, which is already the inductive port of a voltage source converter.
Research on a five level three-phase motor drive which used this technique was
conducted by Matsui et al [43]. The outputs of two half bridge legs were summed
with a current sharing reactor to form a three level intermediate output. This and
another similarly formed three level output were summed by a third reactor to form
the final five level phase output.
One further solution is to sum the outputs of two converters across a bridge
connected source or load. Both ends of the transformer or motor winding are brought
out and the winding must be fully floating. One converter is driven with a phase
inverted signal, so that twice the desired converter output is impressed across the
floating load. If the carriers are appropriately phased, part of the undesired carrier
component will appear as a common mode component to the load.
Of course, this technique can only be applied for two converters.
To summarise, the transformer or inductor summed approach has the following

advantages:
• The voltages within the individual converters and thus across the switches are
well defined by the stiff voltage source output of the transformer secondaries.
• Should a converter module fail, or be removed for service, the converter may
continue operating at full voltage, but at reduced current.
• Other than the transformer (inductors), the structure is modular, which allows
easier maintenance and reduced spares.
• Its mode of operation is easily understood and, again because of its modular
structure, control is more easily applied.
but also the following disadvantages:
• The transformer itself, if not needed for isolation, adds significantly to the cost
of the converter and is one more item to maintain and potentially, to fail.
• The transformer requires multiple secondary windings, which must be isolated

from one another and from ground. This is a significant problem at high
voltages. This also increases the cost of the transformer.
2.3.2 Series Connected Isolated Multiple Bridge Converter
A second topology, which is really only a variation on the first, is that of series con-
nected bridge converters (Fig. 2.5). Each phase leg consists of series connected single
phase full bridges, the series connection being made directly (not by transformer as
in the first case) on the AC side. A three phase converter can be constructed by
connecting three of these single phase series strings to form a star or delta [57, 56].
Since this topology requires each full bridge to have an isolated DC bus, this
connection has not been considered useful until recently re-examined. Now this
topology is being considered for applications where no real power transfer is involved,
such as for active power filtering and VAR correction. Then only a floating DC bus
capacitor is required on each floating DC bus.
Some other sources of power which could easily be made modular and floating
are batteries for battery energy storage systems (BESS) used for load levelling, or
alternative energy sources such as solar panels.
It is of course possible to power the isolated bridges from multiple isolated trans-
former secondaries, each with their own rectifier [25]. By appropriate phase shifting
of the transformer secondary windings, harmonic cancellation can be achieved on
the primary side, as described previously, as well as at the multilevel output of the
multi-bridge converter. However the disadvantages of a transformer with multiple
isolated secondaries returns.
This multilevel converter structure has some very significant advantages, if its
limitations are acceptable. Its advantages:
• It has perhaps the simplest architecture and the lowest component count. No
transformer is needed, so capital costs are low.
Figure 2.5: A five-level Isolated flying multiple bridge.
• Again, the converter is very modular and easy to understand. This applies
not only to its structure, but also to its control.
and the limitations:
• There is only limited access to DC bus capacitors, which limits its area of
application to either those with only reactive power flow, or those where the
power source or load can be both modular and isolated.
• Should a module fail (or be removed), it must fail short circuit, or be bypassed.
The converter can continue to operate, at full current capacity, but at reduced
voltage rating. This will in practice mean that if fault tolerance is required,
the converter will need a more conservative voltage rating — a potential cost
penalty.
2.3.3 Neutral Point Clamped (NPC) Converter
The topologies discussed so far have generated multilevel waveforms by the series
or parallel connection of two level converters. These have been labelled multiple
bridge converters. Another group of converters achieve multilevel waveforms by
the series or parallel connection of switches within the converter bridge. These are
distinguished as multilevel bridge converters.
Figure 2.6: A five-level diode clamped multilevel converter bridge.
The published work on these multilevel bridge converters has mostly concen-
trated on three level Neutral Point Clamped (NPC) converters [51], although more
recently four [59] and five level [44] NPC converters have been investigated (Fig. 2.6).
In a three phase N + 1 level NPC converter, each of the six valve legs is composed
of N separate series connected switches, each of which may be controlled indepen-
dently. The voltage of the non-conducting switches is clamped by diodes and a
string of series connected capacitors. This series capacitor string is shared by all the
phase legs and usually serves as the DC bus or bulk capacitor.
One major disadvantage of the NPC approach is the unequal load distribution
among the switches and capacitors, especially for higher level converters [56]. For
high modulation depths using sinusoidal modulation, outer devices conduct only
for a small part of the cycle, while the inner devices conduct for a larger fraction.
For lower modulation depths, for example below M = 0.5, the outer devices will
not conduct at all in a five level converter. Under these conditions, the capacitor
voltages will become extremely unbalanced unless advanced modulation strategies,
or additional circuitry is used to redistribute the charge in the capacitors. This
problem prevents the technique being practically extended beyond five level.
Figure 2.7: A diode clamped three-level voltage source converter. This topology
does not guarantee voltage sharing between the open switches, as can be seen in
the right most phase leg.
Although this topology may remove the need for a transformer, it requires a
number of auxiliary components, namely the clamping diodes. For converters larger
than three level, although often not drawn as such in the circuit diagram, these
diodes may in fact be a series string of diodes to achieve the required voltage rat-
ing [56]. Figure 2.6 has been drawn to highlight the need for these multiple diodes.
This is another reason why this topology is seldom extended beyond five level.
A further problem is that the voltage across some switches is not strictly guar-
anteed to be less than the voltage of one level [46, 33]. For example, in a three level
converter, only the voltages across the outer switches are clamped by the protection
diodes (Fig. 2.7). One solution to this problem is to place a capacitor across the two
inner switches in each phase leg, in parallel with the clamping diodes [33]. This is
a hybrid of the diode clamped and flying capacitor topologies and has most of the
advantages of both approaches, at the expense of a high component count.
In NPC converters, not all switch states are usable as some do not guarantee a
continuous path for load current to flow. Should the modulator produce these states,
they must be re-mapped to the equivalent valid state. For this reason, space vector
modulators with this knowledge of allowed states are usually used. Further, of these
allowed states, different switch states slew the voltages on the capacitors in different
directions. This fact should be used to control the capacitor voltages. Koyama et al
present a voltage space vector based PWM method for modulation of a three level
GTO converter which addresses these problems as well as that of minimum pulse
width [35]. Velaerts et al present an alternative carrier based modulation strategy
for a three level NPC converter [64, 63].
Despite these many difficulties, the diode clamped converter, particularly in its
three level form, has received much attention and use. As a three level converter,
it is relatively simple, and can remove the need for a transformer where one would
otherwise exist.
However, it seems to have many disadvantages, particularly when extended be-

yond the simple three level topology. Many of these issues in practice limit the
diode-clamped topology to a maximum of five levels:
• Although the transformer can be eliminated, extra components (diodes) are

required to ensure load current continuity. The number of extra components
rises sharply as the number of levels increase.
• These extra components do not necessarily ensure equal voltage sharing for
all switches.
• Switch utilisation is not equal, outer switches receiving a lower average load.
This becomes particularly apparent as the number of levels increase and the
modulation depth is small.
• Similarly, the power flows to and from the different capacitors in the capacitor
string are not balanced.
• Not all switch states are allowed. The disallowed states must be re-mapped
to their equivalent allowed states.
• Different equivalent states slew the capacitor voltages in different directions.

This must be used to control the capacitor voltages.
• For the above reasons, a more complicated, dedicated modulation strategy

must be used, which has been specifically tailored to the topology of the con-
verter.
2.3.4 Flying Capacitor Converter
Probably the most important multilevel topology to appear recently is the flying
capacitor converter, or imbricated cells multilevel converter, proposed by Meynard
and Foch [46, 47, 45].
In a conventional two-level voltage source converter, each phase leg is comprised

of a switch pair in parallel with a bus capacitor (generally common to all phase
legs). These switch pairs are gated in a complimentary manner, so that the phase
leg output is always connected to either the positive or negative node of the bus
capacitor.
In a flying capacitor converter, this switch pair - capacitor “cell” is isolated,

and inserted within a similar cell — hence the term imbricated cells converter. This
inner pair of switches and their associated capacitor now “flies” as the outer pair
of devices switch. The combination of conducting switches and capacitors ensures
that the voltage across any blocking switch is always well defined (Fig. 2.8).
Like the transformer summed bridges, this topology can be extended easily to an
arbitrary number of levels and to different applications such as DC-DC, DC-AC and
even AC-AC (matrix) converters, both for unidirectional and bidirectional power
flow [45]. Since both the voltage source and current source converter topologies are
derived from the matrix converter, it is also possible to develop a current source
flying capacitor converter. This will be discussed further in a later section of this
chapter.
The flying capacitor family of converters appear very attractive:
• The flying capacitor concept can be applied to a number of different converter

types - current or voltage source, DC-DC, DC-AC or AC-AC.
Figure 2.8: The flying capacitor multilevel bridge
• Any switch combination is valid and ensures voltage sharing, so long as switch
pairs receive complementary drive signals. Most modulation strategies are
easily applied to this topology simply by phase shifting the drive signals.
• The voltages of the capacitors are automatically balanced by this conven-

tional modulation strategy. If desired, the capacitor voltages can be actively
controlled by an appropriate modification of the control signals.
• The load is by default equally shared among the switches.
• The topology is modular and not reliant on a transformer.
There are some significant disadvantages, which are not at first apparent:
• The topology requires a lot of high voltage capacitors — many more than
other topologies. These capacitors need to conduct the full load current for at
least part of the switching cycle. Fortunately, if the switch frequency is high,
these capacitors can usually be relatively small in capacitance value.
• Since these capacitors initially have zero voltage across them, starting the
converter safely may be a non-trivial task.
2.4. Current Source Converters 23
• The topology is not inherently fault tolerant.
2.4 Current Source Converters
The converters which were focused upon in the previous section were voltage source
converters, with multilevel voltage waveforms. These converters divide the total
input voltage among a number switches, and allow a reduction of the voltage har-
monics. As mentioned, these are the most commonly used and best understood
multilevel converters.
As we broaden the scope of multi-level again, it is important to see the dis-

tinction between these two aspects of a multilevel converter — the application of
the converter (voltage source or current source) and the internal topology of the
converter (multilevel voltage or multilevel current).
A current source converter has a current stiff inductive DC port and an AC

voltage source port. Some of the conventional multilevel voltage converters pre-
sented can have their DC and AC ports interchanged with little modification to
their topology. They still divide the total high input voltage (which is now an AC
quantity) across a number of switches and present a multilevel voltage waveform to
the inductive port. They are useful when the voltages present are still higher than
individual switches can withstand.
It is also possible to create completely new converter topologies based on the

concept of circuit “duals” [69, 68]. These converters effectively place a number of
switches in parallel and divide the total converter current between the switches.
The capacitive port sees a multilevel current waveform. All switches experience and
must withstand the total converter input voltage [2].
If the capacitive port were an AC port and the inductive port current stiff and
DC, then this would be classified as a current source, multilevel current converter.
+ I
V
Figure 2.9: The flying capacitor converter (left) — a multilevel voltage converter;
and a dual derived from it, the “flying inductor” converter (right) — a multilevel
current converter.
2.4.1 Multilevel Current Converter Topologies
Two of the previously presented multilevel voltage converters are shown alongside
their “duals” in figures 2.9 and 2.10. In both of these examples the duals are
multilevel current converters — they present a multilevel current waveform to the
capacitive voltage port. The voltage rating of the converter is limited to that of the
switches, however, the input current is divided between the multiple switches.
If the dual topology of the multi-bridge current converter is rearranged, a new

hybrid converter topology is obtained (Fig. 2.11). This converter is actually a series
connection of a number of three level current converters. With appropriate coor-
dinated control or each bridge, the series capacitors ensure correct voltage division
among the bridges and hence the switches. The overall converter will apply an
apparent multilevel current waveform to the capacitive voltage port.
Current source converters have a number of advantages:
• Current is well controlled — short term over-current protection is inherently

provided by the DC bus inductor; long term by the current control loop.
2.4. Current Source Converters 25
Figure 2.10: The isolated flying bridge converter is usually a series connection of
voltage source full bridges (right). These present a five level voltage waveform to
the source via the smoothing inductance. A dual of this converter is formed from
isolated current source bridges placed in parallel (left). These present a five level
current waveform which is smoothed by a parallel capacitor.
Figure 2.11: The current source circuit topology derived using duality techniques
(refer to Fig. 2.10) may be used as derived. However, for a high power converter,
the overall voltage rating of the converter needs to be increased by placing the
switches in series rather than in parallel. The final current source circuit (bottom)
bears more similarity to the voltage source converter it was originally conceived
from (top), than to its strict dual.
• The DC bus energy storage component is a large inductor, rather than a

large capacitor. A large power inductor is arguably simpler, cheaper and most
importantly, more reliable.
• Current source converters are suited to the high power devices such as thyris-
tors and GTOs, which can block voltage in either direction, but conduct cur-
rent only in the forward direction.
• Soft switching is either intrinsic to such devices, or easily ensured.
Equally, they have disadvantages:
• Inductors have higher losses than capacitors.
• Switch voltages are poorly defined. Most semiconductor switches tolerate tran-
sient over-current better than transient over-voltages.
• There are more potential resonance problems in input and output filters than
for voltage source.
• When used as a back to back rectifier inverter pair, a more complex and
expensive controlled rectifier with closed loop control is required as a current
source. An uncontrolled diode rectifier is often suitable for voltage source
converters.
Voltage source converters have become the dominant configuration, even at high
power levels. The direction of semiconductor technology has reflected this, with
asymmetrical or reverse conducting thyristors (RCTs) and GTOs being developed
specifically for VSC rather than CSC applications.
This thesis will focus on voltage source converters. It should be remembered

however that by the application of duality principles, any result for VSCs should be
applicable to CSCs.
2.5. Applications of Multilevel Converters 27
2.5 Applications of Multilevel Converters
At this point it should be clear that one of the major advantages of a multilevel
converter, regardless of topology, is increased power rating. A converter need not
be limited in size by the prevailing semiconductor technology, since a multilevel
converter allows the voltage and/or the current to be shared among a number of
switches. This advantage has traditionally justified the extra complexity of multi-
level converters only at very high power levels, for large motor drives and utility
applications.
As the understanding and acceptance of multilevel converters has increased,

these converters are being used at all power levels to extend the useful power range
of semiconductor switches. For example, using multilevel topologies, IGBTs are
challenging traditional GTO converters in motor drive and traction applications
and MOSFETs are displacing IGBTs in some larger Switch Mode Power Supplies.
The more stringent harmonic standards now being legislated also advantage
multilevel converters, since they produce lower switching harmonic spectral compo-
nents for a given switching frequency limit. This will be explained further in later
chapters.
2.6 Conclusion
The aim of this chapter has been to demonstrate the diversity of possible multilevel
converter topologies. Each has its own mixture of advantages and disadvantages
and for any one particular application, one topology will be more appropriate than
the others. Often, topologies are chosen based on what has gone before, even if that
topology may not be the best choice for the application. The advantages of the
body of research and familiarity within the engineering community may outweigh
other technical disadvantages.
Despite the diversity, these different topologies contain common underlying links.
Usually the modulation and, to a lesser extent, control strategies can be developed
independently of the converter’s topology and then subsequently applied with little
or no modification. In subsequent chapters, the simplest case of the transformer
connected multi-bridge converter will be used as the implied default multilevel con-
verter topology. Required variations on modulation and control strategies will be
explained after the general technique has been presented.
Chapter 3
Pulse Width Modulation

Candidates for Multilevel
3.1 A Definition of Modulation
Almost all power electronic converters are operated in the “switched mode”. This
means the switches within the converter are always in either one of two states —
turned off (so no current flows), or saturated (turned on completely, with only a
small voltage drop across the switch). Any operation in the linear region, other
than for the unavoidable transition from conducting to non-conducting, incurs an
undesirable loss of efficiency and an unbearable rise in switch power dissipation.
To control the flow of power in the converter, the switches alternate between
these two states. This happens rapidly enough that the inductors and capacitors at
the input and output nodes of the converter average or filter the switched signal.
The switched component is attenuated and the desired DC or low frequency AC
component is retained. This process is called Pulse Width Modulation (PWM),
since the desired average value is controlled by modulating the width of the pulses.
To achieve the greatest possible attenuation of the switching component, it is

generally desirable that the switch frequency fc is high — many times the frequency
30 Chapter 3. Pulse Width Modulation Candidates for Multilevel
of the desired fundamental AC component f1 seen at the input or output terminals.

In large converters, this is in conflict with an upper limit placed on switch frequency
by switching losses. For GTO converters, the ratio of switch frequency to fundamen-
tal frequency fc /f1 ( = N , the pulse number) may be as low as unity, which is known
as square wave switching. Another application where the pulse number maybe low
is in converters which are better described as amplifiers [50], whose upper output
fundamental frequency may be relatively high. These high power switch-mode am-
plifiers find application in active power filtering [71], test signal generation [19],
servo [42] and audio amplifiers [17].
These low pulse numbers place the greatest demands on effective modulation to
reduce the distortion as much as possible.
In these circumstances, multi-level converters can reduce the distortion substan-

tially, by staggering the switching instants of the multiple switches and increasing
the apparent pulse number of the overall converter. An extension of the best mod-
ulation techniques developed for two-level converters is required to maximise the
benefits of the multi-level converter.
In this chapter, the various forms of modulation which are used for two-level
converters are considered, with emphasis on those suitable for a low pulse number.
Some will be shown to be better candidates for extension to multilevel converters
than others.
3.2 Review of PWM Techniques
3.2.1 Requirements Common to All PWM Techniques
Two requirements which all low pulse number PWM candidates should observe are
synchronism with the fundamental frequency and quarter and half wave symmetry.
Synchronism with the fundamental frequency means ensuring the switching fre-
quency fc is an integer multiple of the synthesised fundamental frequency f1 . That
3.2. Review of PWM Techniques 31
is, the pulse number N = fc /f1 must be an exact integer. The frequency spectrum
of the PWM waveform will then consist of discrete frequencies at multiples of the
fundamental frequency nf1 , where n is an integer.
Quarter and half wave symmetry ensures that no even harmonics will exist in
the output spectrum [32]. This can be achieved by choosing N odd. An important
even harmonic which is eliminated is the DC component.
No frequency components below the fundamental frequency (commonly referred

to as sub-harmonics) will exist. This is important since an undesired harmonic
component near zero frequency, even if small in amplitude, can cause large currents
to flow in inductive loads.
Beyond these basic requirements, there are many different ways of generating
PWM switching edges. Any technique can probably be placed into one of the fol-
lowing three categories:
• Off-line or Pre-Calculated PWM techniques
• Hysteresis control
• Carrier based PWM.
One further modulation technique, delta modulation, doesn’t fall into the cat-
egory of pulse width modulation, as the pulse widths aren’t modulated, but rather
are of constant width. The correct terminology for such techniques is Pulse Density
Modulation, PDM, or Pulse Frequency Modulation, PFM. Delta modulation finds
practical use where this constant pulse width is a given (such as for resonant con-
verters [74]), or an advantage (1-bit a/d and d/a converters [13, 4]). To achieve low
distortion, such converters require the switching frequency to be much higher than
the frequency content of the modulating waveform and won’t be considered further
here.
3.2.2 Selective Harmonic Elimination / Minimisation PWM
Selective Harmonic Elimination (SHE) and Selective Harmonic Minimisation (SHM)

are two off-line (pre-calculated) non carrier based PWM techniques. SHE was pro-
posed in a early paper by Patel and Hoft [54, 55]. Accepting first the conditions
of quarter and half wave symmetry to cancel all even harmonics, the angles of the
switching edges in the first quarter cycle can be considered variables for optimisa-
tion. Each angle is one degree of freedom. For each degree of freedom, one harmonic
may be set to zero or any other reasonable desired value. Using Fourier transforms,
simultaneous equations in these angles are solved given desired values for the fun-
damental and the lowest significant harmonics.
These calculations are slow and are done off-line. A look up table of edge angles
is created which the on-line controller uses to set the edge times.
An example of Selective Harmonic Elimination applied to a three phase converter

simulation is shown in figure 3.1. Four notches per quarter cycle are shown which
allow the elimination of four harmonics, the 5th ,7th ,11th and 13th . Triplen harmonics
are not eliminated since they do not cause any current flow in a balanced three phase
system.
Setting the lowest harmonics to zero can cause the first uncancelled harmonics
to be large. SHM minimises these harmonics, rather than eliminating them, accord-
ing to some cost function (such as harmonic loss in an induction motor) to give a
better overall result [22]. A summary of Harmonic elimination PWM techniques is
presented by Enjeti et al. [16].
Optimal PWM or selected harmonic elimination PWM (SHE-PWM) seems at-

tractive, but cannot react to transients quickly. This is because pulses do not occur
at fixed intervals, that is, the switch period is not constant. Moving one edge may
completely upset the optimised spectrum. Closed loop control using SHE/SHM is
generally limited to cycle by cycle control of the fundamental frequency and modu-
lation depth. Some work has been done on closing feedback loops around optimised
3.2. Review of PWM Techniques 33
200 200
100 100
-0 -0
-100 -100
-200 -200
0s 5ms 10ms 15ms 20ms 25ms 30ms 0s 5ms 10ms 15ms 20ms 25ms 30ms
Figure 3.1: Harmonic elimination PWM. The phase current in a three phase
inductive load is plotted along with the phase leg voltage (left) and load phase
neutral waveform (right).
PWM modulators to remove errors when they occur [32]. These techniques cannot
compensate for distortions due to DC bus ripple, or switching imperfections.
Recent work has been done on implementing regular sampled or on-line SHE-
PWM [8, 10, 38]. This work has shown that the positions of edges can be ap-
proximated relatively simply online given the modulation depth. The calculation
gives their displacement from the “sampling points”, the positions of the edges for
a modulation depth of zero.
Other work has presented alternative methods to solving the optimisation prob-
lem using for example linear block codes [3] and Walsh functions [61].
Velaerts et al. [64] implement pre-calculated three-level PWM (SHM-PWM) by

optimisation of the distortion factor.
3.2.3 Hysteresis Band PWM
A hysteresis band modulator calculates the error between the desired output and
the measured output. The state of the switches is changed when this error exceeds a
certain bound (leaves the hysteresis band) so as to drive the error back within that
bound.
This method requires that the controlled output quantity of the converter is
integrated either by the load, or as part of the controller. For example, in a voltage
200
200
100
100
0 -0
-100
-100
-200
-200
0s 5ms 10ms 15ms 20ms 25ms 30ms 0s 5ms 10ms 15ms 20ms 25ms 30ms
Figure 3.2: Hysteretic PWM. The phase current in a three phase inductive load
is plotted along with the phase leg voltage (left) and load phase neutral waveform
(right). Note the lack of co-ordination between phases.
source hysteretic converter, the output current (the measured and subsequently
controlled quantity) will be integrated by an inductive load (Fig.3.2).
This technique has the advantage of bounded, predictable error and fast tran-
sient response to changes at either the input or the output. It is closed loop by
nature and demonstrates low distortion. It is simple to implement in its simplest
form. It has however a number of disadvantages, which limit its usefulness to low
power, high switching frequency applications.
One disadvantage is the variable nature of the switch period. Because of this,
the output spectra is continuous and spread to an extent, rather than discrete and
grouped as with carrier based techniques. Further, the switching instants are not
necessarily synchronous or cyclic and so sub-harmonics may be present. For these
reasons, hysteresis control is not applied for low switching frequencies.
One method of eliminating sub-harmonics is to force quarter wave symmetry

by reseting the error at each zero crossing and forcing a switching, and hence a
reflection of the pattern, at 90 degrees [23]. This gives a discrete spectra without
sub-harmonics.
Another technique which limits the variations in switching frequency is to mod-

ulate the width of the hysteresis band [40, 41]. This places upper and lower limits
on the switching frequency, but does not address the problem of sub-harmonics.
3.3. Carrier Based PWM Techniques 35
For three phase modulators with an unconnected neutral, the independent hys-
teresis phase controllers ignore the interaction of the phases. There is no strategy to
generate zero voltage vectors, so at low modulation levels, the switching frequency
rises unnecessarily. Further, the modulator may lock into high frequency limit cycles
comprising only active vectors [12]. It is also possible for the line current error to
be double that of the hysteresis band.
By including extra comparators and/or logic, and knowledge of the load back
EMF, the modulator can make more intelligent switching decisions. Another alterna-
tive solution is to translate the three independent phase voltages into a synchronous
reference frame before being acted upon by the hysteresis controllers.
Hysteresis band control has been applied to multilevel converters, by distribut-

ing each successive switching command to a new switch-pair or bridge in a round
robin manner [42]. Special precautions must be taken to ensure stable control is
maintained. These simulations were performed for single phase modulation and
extension to a three phase converter may be non trivial.
Another paper demonstrates two parallel connected boost converters with cou-
pled hysteresis control producing input ripple current cancellation [34]. With simple
cross coupling of the hysteresis feedback, the converters naturally synchronise and
operate out of phase as required.
3.3 Carrier Based PWM Techniques
There are many variations of carrier based PWM.
• analog vs. digital
• sine-triangle vs. space vector (in reality very similar)
• triangular vs. sawtooth carrier
• symmetric vs. asymmetric (sampled once/twice per triangle)

Harmonic elimination PWM

sine-sawtooth PWM
sine-triangle PWM
fundamental fs
Hysteretic PWM
carrier fc
Figure 3.3: A comparison of waveforms and frequency spectra of three different

PWM strategies. From the top, the original sinusoidal modulating waveform,
the unmodulated PWM square wave, sine-sawtooth (single edge carrier) PWM,
sine-triangle (double edge carrier) PWM, Selective Harmonic Elimination (SHE)
PWM and Hysteretic PWM. These figures are for a pulse number N = 9.
• uniform sampling vs. natural sampling
• periodic vs. aperiodic carrier
What is the common link between all these variations?
For the purposes of defining this broad category, carrier based PWM methods are
those where the switching decisions of the converter are made for each switching cycle
either at the beginning or during that switch cycle. That is, the PWM waveform
is calculated on a cycle by cycle basis, either pulse by pulse, or edge by edge.
This distinguishes it from SHE and SHM PWM, where multiple switching edges
are mapped out for the entire fundamental period or some fraction therein; and
hysteretic PWM, where neither edges nor switch period are defined, calculated or
even known in advance.
3.3.1 Fundamental – Carrier waveform relationships
The carrier frequency is the same as the switch frequency. If the modulation were
reduced to zero or a DC quantity, then the PWM spectrum would consist of the
carrier and its harmonics alone and the component at zero frequency (DC) if present.
As the amplitude of the modulating waveform is increased, sidebands appear and
increase in amplitude either side of the carrier and its harmonics. As the frequency
of the modulating waveform is increased, the sidebands spread away from the central
carrier frequency. A more detailed analysis is undertaken in the next chapter.
As mentioned, the carrier frequency should be synchronous, that is an integer

multiple of the fundamental frequency, if the pulse number is low (say N < 21).
An odd multiple guarantees half and quarter wave symmetry and therefore no even
harmonics in the carrier spectrum [49].
If the same carrier signal is used to generate all three phase leg PWM signals
in a three phase inverter, the carrier spectral terms in the phase leg signals will
also be identical. Thus the carrier spectral terms (but not the carrier sidebands or
modulating terms) will be cancelled in the phase to phase waveforms. This is true
regardless of the pulse number N .
Va Vb Vc
Vtri
Va
Vb
Vc
Vab
Figure 3.4: Natural PWM in three phase inverter; phase leg and line to line
waveforms.
Although the phase relationship between the modulating and carrier waveforms
can be arbitary, it is suggested that the slopes of the triangular carrier and modu-
lating waveform, if sinusoidal in character, should be of the opposite polarity at the
coincident zero crossings, especially for low N [49]. This has practical implementa-
tion advantages of preserving the accuracy of the edges in analog implementations,
and easing the transistion between different pulse numbers in systems where this
may change during operation. Additionally this 180 degree phase difference (phase
relative to the carrier period) results in the minimisation of the harmonic losses in
an inductive load [11].
Clearly, this 180 degree out-of-phase relationship can only exist for odd N .
Further, the reduction in harmonic losses due to a specific phase relationship between
modulating function and carrier is only significant for odd N . To achieve this phase
relationship in a three phase inverter for all three phases requires N to be an odd
multiple of three (N = 3, 9, 15, 21, . . . ), if the same carrier is to be used for all
three phases to achieve carrier cancellation in the phase-phase output [49].
In a multi-level converter with an integer pulse number, only one carrier can
ever meet this requirement, as the other carriers are usually phase shifted relative
to it. However, if a non-integer synchronous pulse number (that is a mixed fraction
such as N = 21/4) is used in a multilevel converter, this phase relationship once
again becomes valid.
3.3.2 Modulation Variations
A rising or falling sawtooth carrier may be used instead of a triangular carrier, to

produce leading or trailing edge modulation, instead of double edge modulation.
Leading edge modulation is common in switch mode power supplies, because the
carrier is more easily generated at the high frequencies used. It is also common in mi-
crocontroller PWM peripheral implementations, which generate “sawtooth ramps”
using timers.
However, the spectrum of single edge modulated PWM is inferior to double

edge modulation. Only one edge carries information, while the other fixed edge only
reinforces the carrier frequency components in the output spectra. Double edged
modulation has only half the carrier spectral lines of single edge modulation [6].
Carrier based modulators can also be implemented digitally. A desired pulse

width value can be loaded as a digital quantity directly into a counter, which is then
clocked until it overflows, generating the edge. An alternative approach is to use a
digital comparator to compare the pulse width value stored in a register with a free
running timer. These are both examples of uniform PWM.
Naturally sampled PWM is traditionally an analogue technique. A triangular

carrier can be generated for example by integrating a square wave carrier clock. A
suitably scaled modulating signal is compared with this triangular carrier to produce
the switching edges.
The technique is so named because the signal is naturally sampled by the carrier
triangle waveform at the instant of the switching edge. Naturally sampled PWM can
react instantly to changes in input modulating command and produces no distortion
of the synthesised waveform.
Uniform
Natural
Figure 3.5: Uniform PWM generation. Note the phase delay in the PWM wave-
forms, when compared to the Natural PWM.
Uniform sampled PWM is a sampled data system. The modulating input signal
is sampled at the beginning of the switch cycle, before the actual switching edge
reflects this value later in the cycle. While this need for a sample and hold would
complicate an analog modulator implementation, sampling and holding the input
value is often intrinsic in digital implementations using timers and counters.
This delay in response is significant at low switch frequencies. It leads to a fre-

quency response similar to the sinc function and unwanted odd harmonic distortion
of the synthesised waveform. The actual attenuation of a modulating sinusoid as its

frequency rises is a Bessel function. This will be shown formally in the next chapter.
Space vector modulation is a form of uniform PWM used for the modulation
of three phase converters. A three phase system with no neutral connection only
has two independent controllable quantities, as the third is defined by the other two
according to Kirchoff’s laws. This simplification can be advantageously used in the
modulation strategy.
Instead of modulating each half bridge phase leg between its two states inde-
pendently of the others, the entire three phase bridge is treated as a whole. The
converter is switched between three or four of its eight (VSI) or nine (CSI) possible
states, chosen such that each phase leg switches once in each sub-cycle (half a switch
cycle). Using a three to two dimensional transformation, the desired output aver-
aged over the switch period and the converter states are represented as vectors. The
visualisation and calculation of switching periods is then performed using simple
vector math.
Space vector modulation can equally be applied to current source and matrix
converters [30], although voltage source is the most commonly seen. It can also be
extended to multilevel converters easily.
3.3.3 Variable and Random Period PWM
For synchronous PWM, the period of the carrier cycle should be a constant; an
exact sub-multiple of the fundamental synthesised waveform’s period. This may be
impossible to do in a microcontroller based system, where the triangular carrier is
generated by a digital counter. Should the counter be clocked by a fixed period
clock, the period of the carrier can only be integer multiples of this.
These errors could lead to non synchronous operation and thus sub-harmonics,
and non exact pulse edge positions too and so waveform distortion. One technique
to mitigate this problem is to accumulate this time quantisation error cycle by cycle
and use this error integral to create a correct average carrier period and pulse period
over a number of cycles [26]. Note that this may mean the carrier period alternates
between the quantised values either side of the ideal value. This somewhat “blurs”
the spectral term associated with the carrier frequency.
This concept can be deliberately extended and exploited. If the carrier frequency
is varied randomly about the mean carrier frequency, then the spectral terms associ-
ated with the carrier become continuous rather than discrete. The desired signal is
still faithfully reproduced, as the pulse width is always calculated to be the correct
fraction of the carrier period, even if that period is now itself varying, cycle by cycle.
This technique of random period carrier modulation is successfully extended to

multilevel modulation in chapter 6, Random Carriers and Zero Vectors.
A variation of this concept is to make the carrier period a variable for optimisa-
tion over the modulation period [31]. Within each carrier period, the pulse widths
are calculated as for normal space vector modulation, cycle by cycle, which ensures
the good dynamic response of carrier PWM is retained. The optimisation seeks to
produce a constant minimum ripple in the filtered output, to minimise the distortion.
This groups the switching edges towards the zero crossings, away from the crests —
a result similar to both hysteretic and SHE modulation. This modulation can be
constrained to be synchronous over the fundamental period, by pre-calculating the
desired period widths. However, this approach retains the good dynamic response of
a carrier technique, as each edge position is still determined online at the beginning
of each switch cycle.
3.4. Summary: The Best Modulation Option for Multilevel 43
3.4 Summary: The Best Modulation Option for
Multilevel
Of all these different modulation techniques, this thesis will now focus on carrier
based PWM techniques and their application to multilevel converters. This is be-
cause carrier based PWM:
• is easily implemented in analog or digital circuitry, or using software tech-

niques,
• is easily extended to all multilevel converter topologies,
• shows good performance at moderate switch frequencies,
• has good dynamic performance, suitable for closed loop control.
The understanding of the application of carrier based modulation to multilevel con-

verters leads easily to an understanding of the requirements for and problems of
multilevel modulation using other techniques.
Chapter 4
Multilevel Carrier Based PWM
This chapter examines in detail naturally and uniformly sampled carrier pulse width
modulation (SPWM). These techniques are easily implemented, produce good re-
sults for moderate switch frequencies and are easily extended to multi-bridge con-
verters. In particular, the bandwidth and harmonics of these two techniques are
examined, both for single and multi-modulator converters.
4.1 Carrier Based PWM
As explained last chapter, for a carrier based PWM technique, the switching de-
cisions of the converter are made for each switching cycle either at the beginning
or during that switch cycle. That is, the PWM waveform is calculated on a cy-
cle by cycle basis, either pulse by pulse, or edge by edge. Using the terminology
of modulation theory, the carrier waveform, which has the same frequency as the
switch frequency, is modulated by the input waveform, to produce the desired PWM
waveform.
The aim of any pulse width modulator is to ensure that the averaged value over
the switch period of the output pulses is proportional to the value of the input sig-
nal at that time. This ensures a linear, distortion free transfer function. Firstly
considering a constant input signal, switching instants which satisfy this goal can
46 Chapter 4. Multilevel Carrier Based PWM
Figure 4.1: One switch cycle of carrier based pulse width modulation with single
trailing edge modulation (left) and double edge modulation (right).
a b c d
e f
Figure 4.2: All of the above carrier waveforms will produce a linear, distortion free
transfer function in a natural sampled pulse width modulator; because they are
constructed only with straight line segments. These different carriers do however
have different spectral qualities.
be generated by the intersection of a triangular carrier waveform with the input

value (Fig. 4.1). In general, any carrier which consists of straight line segments be-
tween the limits of modulation will guarantee modulator linearity, including triangu-
lar and sawtooth waveforms, waveforms with dead-bands, and aperiodic waveforms
(Fig. 4.2).
If the input signal is not constant or very nearly constant during a single carrier
(switch) period, then what value should the modulator assign to the pulse width?
In theory, the average value of the output pulse should be made equal to the average
value of the input signal during the total switch period; that is the areas under both
input and output signals should be equal over one switch period. Unfortunately this
requires the input signal to be known for the whole of the period ahead of time —
which may not always be possible. Distortion free reproduction is possible if a delay
is acceptable, however this is counter productive in some applications such as active
4.2. Naturally Sampled PWM 47
0 kπ π 2π ωt
0 kπ π 2π ωt
Figure 4.3: Natural sampled pulse width modulation, of pulse or carrier frequency
ω, shown for constant DC modulation k, 0 ≤ k ≤ 1 (top), and a fixed, sinusoidal
modulation k = 1/2 + M/2 cos(ω1 t) (bottom).
power filtering. In practice the technique known as natural sampling achieves the
same goal of a distortion-less transfer function, without any group delay.
4.2 Naturally Sampled PWM
In naturally sampled PWM (natural PWM), the switching instants are generated
by the intersection of the carrier waveform with the input waveform (Fig. 4.3).
The input waveform is naturally sampled by the carrier wave, the sampling instant
occurring at the same instant as the output edge (Fig. 4.4).
4.2.1 Constant (DC) Modulation
For a constant (DC) modulation input signal, the mathematical description based
on the Fourier decomposition of the PWM waveform is easily derived [70]. The DC
component is equal to the constant modulation input k, 0 ≤ k ≤ 1, and can be
included in the summation to give an alternative form.

m=∞
Vnat (ωc t) = k + (2/π) sin(k mπ)/m cos(mωc t)
m=1

m=∞
= (1/π) sin(k mπ)/m cos(mωc t) (4.1)
m=−∞
Equation 4.1 is expressed as a sum of sines and cosines; here the sines are zero as
the PWM waveform as shown is an even function. If the PWM waveform is not
even, but has some arbitrary phase displacement φc (in radians), then the Fourier
expansion is more clearly and compactly expressed as a sum of complex exponentials.

m=∞
Vnat (ωc t) = sin(k mπ)/mπ ejmφc ejmωc t (4.2)
m=−∞
A derivation of this result can be found in Appendix A.
4.2.2 Sinusoidal Natural Modulation
If the modulation input waveform is a constant amplitude sinusoid k = 1/2 +

M/2 cos(ω1 t), where M is known as the modulation depth or modulation index,
then the timing of the edges of the PWM waveform are functions of time themselves.
The complex mathematical analysis required to arrive at the Fourier expansion is
known as Bennett’s technique. It is outlined in Black [6], but a much more thorough
treatment of the double edge naturally sampled case is given by Wood [70]. Only
the result is given here.
The Fourier description of a double edge, natural sampled PWM waveform of

unity height (stepping between 0 and 1) is
Vnat (ωc t, ω1 t) = 1/2 + (M/2) cos(ω1 t)

p=∞
J0 (M (2p − 1)π/2)
− (2/π) cos(pπ) cos((2p − 1)ωc t)
p=1 (2p − 1)
q=∞
p=∞ J2q (M (2p − 1)π/2)
− (2/π) cos((p + q)π) cos((2p − 1) ωc t ± 2qω1 t)
p=1 q=1 (2p − 1)
q=∞
p=∞ J2q−1 (M 2pπ/2)
− (2/π) cos((p + q)π) cos(2pωc t ± (2q − 1)ω1 t) (4.3)
p=1 q=1 2p
4.2. Naturally Sampled PWM 49
where ω1 input signal frequency (radians)

ωc carrier (switch) frequency (radians)
M modulation depth. (0 . . . 1)
The output PWM waveform is presented in this equation as the sum of a number
of Fourier terms. The first line is the desired output term of frequency ω1 ; the
second line, the carrier (ωc ) and its harmonics (mωc ); and the third and fourth lines
are the sidebands of the carrier and its harmonics (mωc ± nω1 ). Note that there
are no fundamental harmonic distortion terms of frequency nω1 . In the preceding
discussion, n and m are positive integers.
The above equation can be simplified by observing that:
• the third term (second line) is simply a special case (q = 0) of the fourth term
(third line), and can be included by starting the summation in n (2q) from
zero.
• the fourth and fifth terms (third and fourth lines) can be combined, if it is
noted that when m is even (m = 2p), n is odd (n = 2q − 1), and visa versa.
The terms 2p, 2p − 1 and 2q, 2q − 1 can be replaced by m and n respectively,
if an extra term cos(m + n + 1)π/2 = − sin(m + n)π/2 is introduced to ensure
only terms for which m + n are odd are non-zero.
The resulting equation is
Vnat (ωc t, ω1 t) = 1/2 + (M/2) cos(ω1 t)

n=∞
m=∞ Jn (M mπ/2)
+ sin((m + n)π/2) cos(mωc t ± nω1 t) (4.4)
m=1 n=0 mπ/2
A more general representation which includes the phase of the carrier and fun-
damental waves is again better presented using the sum of exponential terms. A
derivation of this result can be found in Appendix A.
Vnat (ωc t, ω1 t) =
∞
∞
Jn (mM π/2) j(mφc +nφ1 ) j(mωc +nω1 )t
sin((m + n)π/2) e e (4.5)
m=−∞ n=−∞ mπ
Figure 4.4: The process of Natural (left) and Uniform (right) sampling. Uni-
form sampling introduces a delay of on average Tsam /2 which causes a sinc like
frequency response.
where φ1 input signal phase, (0 . . . 2π)

φc carrier phase, (0 . . . 2π)
The DC and modulating terms are both included implicitly in the summation.
Their values are found by taking the limit as m = 0, n = 0 and m = 0, n = 1
respectively.
4.3 Uniformly Sampled PWM
In uniformly or regularly sampled PWM (uniform PWM), the input signal is regu-
larly sampled and held constant at the beginning of each switch cycle before being
compared with the triangular carrier (Fig. 4.4). While this would complicate an
analog implementation, this sample and hold process occurs intrinsically in a digital
implementation, such as found in many microcontrollers. A complete discussion of
the implementation of natural and uniform sampled modulators is discussed in the
next chapter.
4.3. Uniformly Sampled PWM 51
4.3.1 Uniform PWM Spectrum
The spectra of uniform sampled, double edge PWM is similar to that of natural
PWM, and is determined using the same techniques [6, 67].
∞
∞
Jn ((m + nω1 /ωc )M π/2)
Vuni (ωc t, ω1 t) = sin((m + n)π/2)
m=−∞ n=−∞ (m + nω1 /ωc )π
× ej(mφc +nφ1 +(nω1 /ωc )π/2) ej(mωc +nω1 )t (4.6)
In the remainder of this chapter, comparisons and conclusions about the performance
of natural and uniform sampled PWM will be made based on an examination of these
equations for the output spectra of natural and uniform PWM, equations 4.5 & 4.6.
The reader is encouraged to refer back to these equations at these points.
4.3.2 Extension to Multiple Modulators
As explained in chapter 2, multilevel converters share the voltage or current which

would normally be seen by one switching device between a number of devices. These
multiple switches could be switched simultaneously to effectively form one switch
of a larger rating. However, the topology of these converters allow these switches
to be switched at different instants — independently — without placing destructive
conditions on the other switches. This additional degree of freedom allows the
creation of multilevel waveforms and calls for a more complex modulation strategy.
The modulation of the transformer summed multiple bridge converter (Fig. 2.4)
is easily understood and a good starting point. Each bridge can be modulated
independently; its output will be described by the equations presented previously if
carrier PWM is used. The action of the transformer is simply to sum the outputs of
the bridges (Fig. 4.5). This is true not only of the time domain PWM waveforms,
but equally of the equivalent frequency domain spectral description.
The phase of the spectral components of natural and uniform sampled PWM
are nφ1 + mφc and nφ1 + mφc + (nw1 /wc )π/2 respectively. For both natural
Va
Figure 4.5: By using triangular carriers with specific phase relationships, a mul-
tilevel waveform is formed when the resultant PWM waveforms are summed.
and uniform PWM, changing the carrier phase φc does not affect the phase of the
modulator input signal term f1 , as m = 0. Regardless of the phase relationship of
the carriers used for the separate bridges, the input signal frequency components
will sum.
Changing the carrier phase does affect the phase of the carrier terms and their
sidebands since m = 0. In multi-modulator converters, choosing φci for each modu-

lator such that mφci = 0 will cause all carrier and sideband terms of order m to
sum to zero.
The time domain plots of four such carriers for a five level (four bridge) converter
are shown in Fig. 4.5. The initial triangular carrier is shown in bold, along with
the resultant natural PWM waveform when modulated by the sine wave shown
(N = 9,M = 0.9). Three additional carriers are generated by delaying this first
carrier by φc = π/2, π, and 3π/2 respectively, where 2π is the carrier period. Using
these carriers, three additional natural PWM waveforms can be generated, which
when summed by the multilevel converter structure result in the five level waveform
shown. In this multilevel waveform, the first three carrier terms and their sidebands
4.3. Uniformly Sampled PWM 53
48 Bridge Natural PWM, M = 0.9, N = fc/f1 = 2 48 Bridge Natural PWM, M = 0.9, N = fc/f1 = 2
0
25 10
1st, 0.900
20
15
10 −1
10
5
−5
−2
10
−10
31st, 0.0044
−15
29th, 0.0035
−20 27th, 0.0022
−3
−25 10
0.02 0.022 0.024 0.026 0.028 0.03 0.032 0.034 0.036 0.038 0.04 0 10 20 30 40 50 60 70 80 90 100
Figure 4.6: A simulation of the time domain (left) and frequency domain (right)
response of a 49 level (48 bridge) multilevel converter, modulated using natural
modulation, modulation depth M = 0.9.
have been cancelled. The first carrier-sideband group which appears in the output
spectra is grouped around 4 ∗ fc .
Many of the early simulations and practical results which are gathered in this
chapter apply to a three bridge (four level) converter. The phases of the triangular
carriers were −2π/3, 0 and 2π/3, so the phasor sum of the harmonic terms will
be zero for m = 1, 2, 4, 5, 7, 8, . . .. Only spectral components associated with m =
0, 3, 6, . . . appear in the PWM output. Although the switch frequency fc equals
450 Hz in these results, the lowest carrier and sidebands are centred around 3 * 450
= 1350 Hz (see Section 4.4.1).
It is possible to use carrier sets with relative phase shifts not equal to 2π/k, where
k is the number of carriers (converters). This will lead to incomplete cancellation
of carrier and sideband terms, but may be advantageous for other reasons, usually
related to the multilevel converter topology (see section 5.5.1) [24].
Using this technique of carrier cancellation, it is possible to use a large number of

bridges with low carrier frequency fc and rely on cancellation to separate the desired
signal from the carrier harmonics. In one high power application for example, 48
modules with 120 Hz carrier frequency were used to synthesise a 60 Hz sinusoid [73].
Despite the low pulse number N = 2, the first uncancelled carrier would appear
at 48 ∗ 120 = 5760 Hz. For natural modulation, the significant lower sidebands
do extend down to approximately one quarter of that frequency, still greater than
1500 Hz. In any case, the amplitude of this carrier and these harmonics is also
very small, all less than one percent of the maximum modulation index. A time
domain and frequency domain plot for this example 48 bridge converter, modulated
using natural sampling with a modulation depth of M = 0.9, is shown in figure 4.6.
The frequency axis has been normalised relative to f1 (= 50/60 Hz), so that they
represent harmonics of the line frequency. The amplitude axis is relative to the
maximum modulation depth of the modulator M = 1.0. The time domain plot
amplitude is relative to the voltage seen by each bridge E; the maximum output of
the entire converter is ±24E.
However such low pulse numbers can cause some unexpected difficulties, as
explained in subsequent sections, if inappropriate modulation techniques are applied.
4.4 Modulator Implementation
In reality, the implementation of these carrier techniques led to their subsequent

analysis, rather than practical application following from the initial theory.
The natural PWM modulator is quite simply implemented in analog hardware.

The triangular carrier can be generated by integrating a square wave clock. A com-
parator generates the PWM output by comparing the input and triangular carrier
signals. An alternate approach is to sum the carrier with the input signal and then
compare this to the ‘slicing level’, signal ground.
A multilevel modulator requires a number of synchronised, phase shifted trian-

gular carriers. The simplest approach is to use digital counters and logic to create
the necessary phase shifted square-waves and integrate these. A more complex but
potentially accurate scheme is to use a number of digital to analog converters fed
from ROM lookup tables [72].
In any of these analog implementations, performance is limited by noise, drift,

and initial inaccuracy; all attributable to the analog circuit components.
4.4. Modulator Implementation 55
48 Bridge Natural PWM, M = 0.9, N = fc/f1 = 2 48 Bridge Natural PWM, M = 0.9, N = fc/f1 = 2
0
25 10
20
15
10 −1
10
5
−5
−2
10
−10
−15
−20
−3
−25 10
0.02 0.022 0.024 0.026 0.028 0.03 0.032 0.034 0.036 0.038 0.04 0 10 20 30 40 50 60 70 80 90 100
Figure 4.7: The simulated time domain (left) and frequency domain (right) re-
sponse of a 49 level (48 bridge) multilevel converter, modulated using natural
modulation, modulation depth M = 0.9, as before. One percent uniformly dis-
tributed noise has been added to the switching edges, to simulate the inaccuracies
inherent in an analog implementation.
Consider for example the effect of adding noise to the PWM edges in the previous
naturally sampled, 49 level converter simulation (Fig. 4.7). The noise is uniformly
distributed with a maximum deviation that is one percent of the carrier period.
This is a fair approximation of the error caused by triangular carriers which have
a slightly incorrect amplitude, offset, or phase shift. The overall amplitude of the
harmonics has not increased dramatically, however a number of extra harmonics
have appeared, including some at lower frequencies. Later results gathered from
actual hardware circuits also show incomplete cancellation of carriers and sidebands
(Fig. 4.9).
Natural sampling does not lend itself to digital or microcontroller implementa-

tion as the switching instants are defined by transcendental equations. Yet digital
circuits are preferred over analog circuits in many situations because they offer a
number of advantages:
• accuracy
• stability
• greater noise immunity
• easy integration
8 bit B0..7
Binary 8
Counter B0..7
osc
B7 A0..7
= R Q
D0..7 8
A0..7 S
D Q D Q
load
Q
Figure 4.8: A example digital implementation of single edge uniform sampled

PWM, as found in many microcontroller peripherals.
Microcontrollers offer in addition functional flexibility and complexity, for a com-

paratively low circuit complexity and cost.
The simplest digital hardware implementation of PWM commonly found in mi-

crocontroller peripherals is single edge uniform PWM (Fig. 4.8). A binary counter
clocked at a constant rate forms the sawtooth carrier. Each time it overflows, the
output flip-flop is set marking the beginning of the switch cycle. This flip-flop is
subsequently reset by a digital equality comparator when the counter value exceeds
the input PWM value, held in a register. For consistent results, this input register is
usually double buffered and the internal register is only updated when the counter
overflows, at the beginning of the cycle.
More complicated implementations exist, especially those intended for three

phase motor control. Many implement double edge PWM because of its superiority.
Some gain extra flexibility by allowing comparisons with 16 bit free running timers,
placing the responsibility for every edge on the software.
It might appear that a multilevel uniform PWM modulator requires multiple

synchronised digital counters, as well as multiple digital comparators. However, the
multiple phase shifted sawtooth waveforms can be derived from the one counter
simply by manipulating the most significant bits. Microcontrollers can also perform
multilevel PWM with their standard timer peripherals.
4.4.1 Experimental Hardware
For the purposes of experimental verification of the theoretical conclusions advanced,

both natural and uniform multilevel modulators were built. Results were mainly
gathered using a dedicated spectrum analyser, a Tektronix 2630. Oscilloscope plots
were obtained using a Hewlett Packard DSO.
A four level naturally sampled modulator was prototyped using analog ICs.
Three triangle reference waves were generated by integrating square waves and then
these were compared with the modulating wave to generate the PWM signals. These
three PWM logic level signals were summed to give a four level output waveform.
Stable and accurate phase shifted clock signals were provided by an 80C196 Intel
microcontroller rather than discrete logic, for simplicity and flexibility. This circuit
was later extended to five and then seven levels. The natural sampling analog PWM
modulator’s circuit appears in appendix C.
A four level uniformly sampled modulator based entirely on an 80C196 microcon-

troller was also developed. The internal 10bit a-d converter samples the modulating
waveform before every edge. This value is scaled and becomes a time offset which is
added to the mean switching instant. At this calculated time, one of three output
pins is set or cleared appropriately by the high speed output peripheral. The uni-
form sampling microcontroller PWM modulator’s circuit and some example C code
appear in appendices C & B.2 respectively
A number of Matlab routines (‘.m’ files) have been written to calculate and
display the spectral components generated by single and multiple converters, both
naturally and uniformly sampled. The switching instants of the edges are calculated
directly for the uniformly sampled case and iteratively for the naturally sampled
case. Non ideal effects such as time quantisation, switching delays and dead-times
can also be then easily included at this point. Jump function analysis [5], a variation
of the Discrete Fourier Transform (DFT), is then used to calculate the exact Fourier
spectrum of these PWM waveforms. This avoids the problems of the FFT (Fast
0 0
10 10
-1 -1
10 10
Vm
Vm
-2 -2
10 10
-3 -3
10 10
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
freq freq
Figure 4.9: These two spectra compare the predicted and measured spectra of
naturally sampled 2 (left) and 4 (right) level converters. M = 0.9, N = 9 (f1
= 50 Hz, fc = 450 Hz)
0 0
10 10
-1 -1
10 10
Vm
Vm
-2 -2
10 10
-3 -3
10 10
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
freq freq
Figure 4.10: These two spectra compare the predicted and measured spectra of
uniformly sampled 2 (left) and 4 (right) level converters. M = 0.9, N = 9 (f1
= 50 Hz, fc = 450 Hz)
Fourier Transform) which result from the necessary padding and windowing of data.
Some of these Matlab scripts and a summary of jump function analysis appear in
Appendix A.
4.4.2 Results
The spectral results of the two hardware approaches were collected and calculated
with the Tektronix spectrum analyser. This spectral data was imported into Matlab
and plotted along with predicted values for comparison. In figures 4.9 & 4.10 ,
the measured data appears as a continuous (1024 point) spectrum. The harmonic
terms appear as “spikes” in this continuous spectra, peaking at the predicted values,
indicated by horizontal bars.
The spectra of the conventional two level PWM waveforms are presented along-
side the four level PWM spectra, for both natural and uniform PWM. The cancella-
tion of the first and second carrier terms and their associated sidebands is apparent
as predicted.
In a multilevel converter, cancellation of suppressed carriers and their sidebands

should be complete and this is seen in the simulations. In practice, inaccuracies
in the generation of switching instants from bridge to bridge can lead to poor can-
cellation of harmonic terms. The uniform sampled converter did achieve excellent
cancellation, with only the 450 Hz carrier (Vm ≈ 3e-4) visible above the noise floor
of the spectrum analyser (Vm ≤ 1e-4). This is due to the precision of the digital im-
plementation of the uniform converter and not attributable to the uniform sampling
process itself.
(These two features refered to in the above paragraph are not actually visible
in the plot in figure 4.10, since the lower bound of the y-axis is 1e-3. The choice
was made here and elsewhere in this document to use identical axes where direct
comparisons are desirable. The y-axis range (here three orders of magnitude) was
chosen to show all significant information, and yet maintain resolution.)
The natural converter did not achieve the same order of cancellation (Vm ≈ 3e-3
at 450 Hz, M = 0.9 ). This is simply because of the analog nature of the circuitry
and the consequent inequalities between each of the three modulators. The results
shown were achieved after trimming the amplitudes of each integrator, as standard
tolerance components led to poor cancellation. In terms of precision, the digital
modulator has a distinct advantage over the analog modulator.
1
0
10
−1
10
0.5
−2
10
−3
10
−4
−0.5 10
0 1 2 3 4 5 6 7 8 9 10 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Figure 4.11: The first five Bessel functions of the first kind, J0 (x) . . . J4 (x) plotted
vs x. On the right, a logarithmic scale is used to clearly show their behaviour
for small values of x (the usual situation for PWM modulation). As x → 0,
J0 (x) → 1, and Jn=0 (x) → 0.
4.5 Input signal Attenuation, Distortion and Phase
delay
High power converters, both conventional and multilevel, are being considered and
used for more demanding applications such as active power filters and servo motor
drives. The design of the control system for such applications is simplified if the
PWM modulator and power conversion stage together can simply be considered as
a linear amplifier with some fixed gain. This assumption that the PWM modulator
has a flat, linear, distortion free transfer function can be validated by examining the
previously derived mathematical descriptions of the PWM waveform.
The magnitude of the harmonic terms in the Fourier summation are described
by Bessel functions of the first kind; for natural sampling:
Jn (M mπ/2)
sin((m + n)π/2)
mπ/2
and for uniform sampling:

Jn (M (m + nw1 /wc )π/2)
sin((m + n)π/2)
(m + nw1 /wc )π/2
4.5. Input signal Attenuation, Distortion and Phase delay 61
The function Jn (x) is the n-th order Bessel function. Both n and x can be
real quantities, however here n is always an integer. The first five Bessel functions
J0 (x) . . . J4 (x) are plotted against x in figure 4.11.
For x > n, the Bessel functions look qualitatively like sinusoidal waves whose
amplitudes decay as x−1/2 [18]. For x < n, the Bessel functions look qualitatively
like simple power laws, with the asymptotic form for 0 < x
n
1 1
Vn (x) ∼ ( x)n n ≥ 0
Γ(n + 1) 2
1 1 n
∼ ( x) n ≥ 0, n an integer (4.7)
n! 2
These Bessel functions describe the amplitude of the carrier and sidebands
(m = 1, 2, 3, . . .). They also define the magnitude, and hence attenuation, of
the modulating signal (m = 0, n = 1) and generation of harmonics of that signal
(m = 0, n = 3, 5, 7, . . .).
For natural sampling, the argument of the Bessel function is only a function of
m. For m = 0, the Bessel function becomes Jn (0), which is either one (n = 0) or
zero (n = 0). This means that the original modulating signal appears in the PWM
output spectra unattenuated, without any accompanying distortion components,
and without phase delay, regardless of the frequency or modulation depth of that
signal. The gain of the modulator / converter cascade is equal to the peak amplitude
of the output waveform divided by the peak amplitude of the triangular carrier.
A collection of plots of the spectra of a naturally sampled multilevel modulator

for different ratios of modulating and carrier frequencies can be grouped together
to form a waterfall plot (Fig. 4.12). This clearly shows that the amplitude of the
harmonic terms in the natural PWM spectrum are independent of pulse number.
Although not shown here, a further analysis with a pair of modulating signals
demonstrates that natural sampling produces no intermodulation distortion prod-
ucts either [67]. Intermodulation products are output distortion components which
0.9
0.8
0.7
0.6
1
0.8 0.5
200
0.6 0.4
150
0.4
0.3
0.2 100
0.2
0 50
0 0.1
500 fc
1000 0
1500 0
0 500 1000 1500
frequency frequency
Figure 4.12: This waterfall plot and its front elevation show the spectra of a nat-
urally sampled 4 level converter for different input frequencies. M = 0.9, fc =
450 Hz
0.9
0.8
0.7
0.6
1
0.5
0.8
300 0.4
0.6
250
0.3
0.4 200
0.2 150 0.2

100
0
0 50 0.1
500 fc
1000 0
1500 0
0 500 1000 1500
frequency frequency
Figure 4.13: This waterfall plot and its front elevation show the spectra of a
uniformly sampled 4 level converter for different input frequencies. Note that the
input signal response is not flat and the presence of input signal harmonics (cf.
natural sampling, fig. 4.12) M = 0.9, fc = 450 Hz
are harmonically related to signals in the input signal, for example, sums and dif-
ferences. This is an important result if the converter’s intended application is as an
active power filter, cancelling a number of closely spaced harmonic terms.
For uniform sampling, an extra term nw1 /wc makes the argument for the Bessel
function non-zero even when m = 0. For the pulse numbers generally encountered
(N > 5), this additional term is small, and the uniform PWM spectra is very similar
to natural PWM. However as demonstrated, it is possible to effectively use low
pulse numbers (even N < 2) in multilevel converters. Under these circumstances,
previously insignificant differences between uniform and natural sampling become
apparent.
48 Bridge Uniform PWM, M = 0.9, N = fc/f1 = 2 48 Bridge Uniform PWM, M = 0.9, N = fc/f1 = 2
0
25 10
1st, 0.8449
20
15
10 −1 3rd, 0.1262
10
5
5th, 0.0425
0
−5 7th, 0.0184
−2
10
−10
57th, 0.0078
−15
55th, 0.0029
−20
−3
−25 10
0.02 0.022 0.024 0.026 0.028 0.03 0.032 0.034 0.036 0.038 0.04 0 10 20 30 40 50 60 70 80 90 100
Figure 4.14: The hypothetical consequence of using uniform sampling for a 49

level converter when N = fc /f1 = 2. The synthesised fundamental has been
attenuated, and odd harmonic distortion overwhelms the switch frequency terms.
The transfer function of the modulating input signal starts at unity gain for DC
frequency, as for natural PWM, but rolls off as the ratio f1 /fc increases (Figs. 4.13
& 4.17). The effect is more pronounced for larger modulation depths. Accompany-
ing the roll off is a constant phase group delay, equal to one half of the sampling
period. This delay also becomes significant as the ratio f1 /fc increases, and should
be considered in wide bandwidth closed loop stability calculations. Odd harmonic
distortion terms of the fundamental modulating signal, nf1 are now also non-zero
for uniform modulation.
The waterfall plot of uniform PWM spectra at different pulse numbers shows
that the amplitude of all harmonic terms are dependant on the pulse number, fc /f1
(Fig. 4.13).
These three effects are generally insignificant in normal two level converters
where, except in very high power ratings, the pulse number is at least larger than
nine [49] . Indeed, they are rarely mentioned. However in multilevel converters
where the pulse number can be made very low, they can be not only significant, but
the limiting factor.
Consider the previously mentioned multilevel example, where 48 modules with

120 Hz carrier frequency were used to synthesise a 60 Hz sinusoid [73]. If simple
uniformly sampled modulation had been used, a simulation of the PWM spectra
demonstrates all the previously mentioned problems (Fig. 4.14). The first uncan-
celled carrier group would appear centred around 48 ∗ 120 = 5760 Hz, with the
significant lower sidebands extending down to approximately half that frequency,
greater than 3000 Hz. The amplitude of these carrier harmonics is also very small.
This very low level of residual switching energy is very pleasing, and justifies the use
of multilevel modulation. However with uniform PWM, the amplitude of the desired
sinusoidal output is not the 0.9 as expected, but rather 0.84; and odd harmonic dis-
tortion is clearly evident. Also obvious in the time domain plot is the group delay
due to the sampling process of uniform PWM.
4.5.1 Experimentally Gathered Modulator Transfer Func-
tions
The transfer functions of naturally and uniformly sampled PWM were experimen-
tally verified using the previously discussed analog and microcontroller based multi-
level modulators. These modulators were extended to generate seven-level signals to
achieve greater carrier cancellation, which aided in the gathering of these particular
results. The input signal to the modulator was a swept sine-wave (“chirp”) gener-
ated by the Tektronix 2630 spectrum analyser (Fig. 4.15). The transfer functions
were calculated by the spectrum analyser based on the ratio of the corresponding
frequency components in the FFTs of the input and output waveforms. This essen-
tially isolated the desired output signal from the surrounding carrier and sideband
harmonic terms in the PWM signal, and so no separate output filter was required.
Normally the output filter or load would determine the overall response of the con-
verter, however the filter is generally included as a separate block in control system
calculations.
The theoretically flat transfer function of naturally sampled PWM is plotted in

figure 4.16, alongside the experimentally gathered transfer functions for the range
of modulation depths from 0.1 to 1.0. Even when the modulating signal is many
times the frequency of the carrier signal (implying a fractional pulse number!), the
Figure 4.15: The transfer function of the modulators was automatically evaluated
by the Tektronix spectrum analyser. It calculated the ratio of input and output
spectra of the system, when stimulated using a swept sine wave chirp. The time
domain plots are shown here.
gain is still unity. Usually a filter placed between the converter and the load or the
load itself, will place an upper limit on the frequency response of the system.
The transfer function of a uniformly sampled PWM modulator is dependant

on both modulation depth M and the ratio of the modulating and carrier frequen-
cies f1 /fc . The experimentally gathered curves show excellent agreement with the
theoretical curves generated from the Bessel functions given earlier in this chapter.
In the seven level modulator implementations used, the first uncancelled carrier
group was at six times the switching or carrier frequency (m = 6). The first signifi-
cant lower sideband term (m = 6, n = −1) and the modulating signal (m = 0, n = 1)
coincide when the modulating frequency is three times the carrier frequency (imply-
ing a fractional pulse number 1/N = f1 /fc = 3). This is the cause of the distortion
of the transfer function at this point.
4.5.2 The Slew Rate Limit
As explained, natural sampling has a linear transfer function, that is, a flat fre-
quency response (Fig. 4.16, Fig. 4.12). The small signal bandwidth is theoretically
1 1
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
N = f1/fc
0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Figure 4.16: The transfer function (for the modulating component f1 ) of a natu-
ral PWM modulator plotted against the ratio of modulating signal frequency to
carrier (switch) frequency (f1 /fc = 1/N ); shown in theory (left), and as gathered
from a seven level analog implementation (right). Natural modulation introduces
no attenuation or phase delay, but is subject to a slew rate limit (dotted) if mul-
tiple pulses per switch cycle are to be avoided.
The distortion of the transfer function at 1/N = f1 /f c = 3 is due to the coinci-
dence of the modulating term and the first significant decending lower sideband
at the modulator output. These output terms constructively and destructively
interfere as the modulator input chirp sweeps past this specific frequency.
1 1
M = 0.1
0.2
0.8 0.8
0.3
0.6 0.6
0.4 0.4
1.0
0.2 0.2
0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Figure 4.17: The transfer function (as above) of uniform PWM modulation;
shown in theory (left), and as gathered from a seven level, microcontroller based
implementation (right). For Uniform modulation, the input-output attenuation
is a function of both modulation depth M and the ratio of modulating signal
frequency to carrier (switch) frequency (f1 /fc ).
unbounded. However, a limit is imposed on the input signal’s slew rate if multiple
switching edges per switch cycle are to be avoided. The slope of the input signal
should not exceed the slope of the triangular carrier wave, by remaining within the
boundary M f1 < 2/π fc .
It should be noted that a limit on slew rate does not limit the bandwidth as
such, but rather the available bandwidth at a given amplitude. If higher frequency
components in the input signal occur at lower amplitudes – as is often the case
in active filters – then these can be reproduced without attenuation and without
violating the slew rate limit.
Further, if multiple switching edges and the resultant rise in switch frequency
can be tolerated, then high frequency input signals will continue to be faithfully syn-
thesised, without distortion or intermodulation products. For example, the resonant
circuit of a radio transmitter could be excited by a pulse width modulated switching
power amplifier rather than a linear amplifier. The PWM carrier frequency could
be lower than the modulating signal — the broadcast signal carrier. The PWM
carrier and associated harmonics and sidebands would be removed by the high Q of
the transmitter’s resonant circuits (Fig. 4.18). Of course, a multilevel converter will
considerably ease the demands on the resonant filter.
4.5.3 Lower Sidebands
The harmonic terms in the output waveform which may interfere with the original
modulating signal are the lower sidebands of the first uncancelled carrier group,
found at frequencies mfc − nf1 , m + n odd. These may be difficult or impossible
to remove by filtering when their frequency is comparable or lower than that of the
original signal. This happens for those terms for which n is close in value to mN .
These unwanted harmonic terms are usually referred to as “sub-harmonics”, since
their frequency is less than that of the desired signal.
The impact of these terms depends upon their amplitude and frequency, and the
nature of the application. For loads with an inductive component, such as induction
motors and transformers, sub-harmonics of low (near zero) frequency can cause large
0.5
0
10
0.4
0.3
0.2
−1
0.1 10
−0.1
−0.2 −2
10
−0.3
−0.4
−0.5
−3
10
20 22 24 26 28 30 32 34 36 38 40 0 200 400 600 800 1000 1200 1400 1600 1800 2000
2
0
10
1.5
0.5 −1
10
−0.5
−2
10
−1
−1.5
−2
−3
10
20 22 24 26 28 30 32 34 36 38 40 0 200 400 600 800 1000 1200 1400 1600 1800 2000
8
0
10
6
2 −1
10
−2
−2
10
−4
−6
−8
−3
10
20 22 24 26 28 30 32 34 36 38 40 0 200 400 600 800 1000 1200 1400 1600 1800 2000
Figure 4.18: In theory, a pulse width modulated converter using natural sampling
could be used to excite a radio transmitter’s resonant circuits, even if the PWM
switching frequency was less than the transmitter’s carrier frequency. The high-Q
resonant circuits would filter the undistorted desired frequency component from
the other switching frequency terms.
As an example, the time and frequency domain plots of a two level, five level
and seventeen level multilevel converter are shown. The naturally sampled PWM
waveforms of switch frequency fc = 450kHz are modulated by a desired waveform
of frequency f1 = 590kHz. The maximum modulation depth chosen, M = 0.4,
would avoid the possibility of multiple switch edges per switch period at the
expense of underutilisation of the power converter.
currents to flow, even if their amplitude is only a fraction of the rated voltage at
rated frequency. Unwanted harmonic terms may also excite harmful mechanical and
electrical resonances in connected loads.
The magnitude of the n-th sideband (lower or upper) of the first carrier term
Jn (M π/2)
equals 2 sin((n + 1)π/2) π/2
. The sidebands have their largest values for M =
1.0, and decrease rapidly as M decreases for increasing n (Fig. 4.11). Although the
sidebands decay quickly as n increases even for M = 1.0, it is generally recommended
that a reasonably large pulse number (say N > 21) should be chosen to ensure the
magnitude of the sub-harmonics is negligible [49]. This guideline does seem overly
conservative. For example, the sideband term which approaches zero frequency (the
subharmonic) as N drops below nine has an normalised amplitude of approximately
5e-5.
4.5.4 Synchronous Natural Modulation
For small pulse numbers, synchronous modulation ensures sub-harmonics cannot

exist. If the carrier frequency fc is a multiple of the input signal’s frequency f1
(synchronous PWM - SPWM), that is the pulse number N = fc /f1 is an exact
integer, then all the harmonic terms in the PWM spectrum will occur at multiples
of f1 . In particular, the lower sideband harmonics will occur at mfc −nf1 = mN f1 −
nf1 = (mN − n)f1 , m + n odd. Only odd pulse numbers should be chosen, as this
ensures there is no DC component.
Two of the lower sidebands will actually coincide with the modulating sine-wave,
when n = mN − 1 and n = mN + 1, and cause an error in its desired amplitude
and possibly phase. For N = 5, M = 1.0, this is at worst less than two percent, and
improves rapidly for increasing N and decreasing M .
In a multilevel converter, the sidebands (and hence subharmonic terms) associ-

ated with the cancelled carrier terms are also cancelled. For a multilevel converter
with nc modulators (nc + 1 levels per phase leg), only the carrier and sidebands
at nc mfc ± nf1 , m + nodd, remain uncancelled. The lowest uncancelled sideband

(subharmonic) is now at f = nc mfc − nf1 = nc mN f1 − nf1 = (nc mN − n)f1 , m + n
odd. Acceptable values of pulse number N place this harmonic at the fundamental
frequency f1 , so N = (n + 1)/nc m, m + n odd. As an example, for a five level
converter (nc = 4), a pulse number N = 5.25 results in the first uncancelled carrier
and sidebands centred about f = 21 f1 .
4.5.5 Overmodulation
If the modulating input signal exceeds the amplitude of the carrier waveform, the
output saturates, or clips, as a conventional linear amplifier would. If the converter’s
application relies on a linear transfer function (such as for active filtering), this
situation should be avoided due to the rapid rise in distortion.
However, if utilisation of the converters power rating is paramount, then this

distortion may be accepted to permit the synthesised fundamental component to
continue to increase. The ultimate limit is square wave switching, for which the
fundamental component (in a single phase) is 4/π Vdc = 1.27 Vdc .
In a three phase converter, any component which is a multiple of three times the
modulating frequency will appear in-phase in all three phases, and so cancel. Such a
component is called a zero sequence term. The addition of appropriate zero sequence
waveforms to the phase leg voltages can increase the phase to phase fundamental
component before overmodulation by 1.15, which is a worthwhile improvement [7].
Another important advantage of this technique is the potential for the reduction
of switching losses. Every π/6 sector, one of the three phase legs can be forced to not
switch by the correct choice of triplen waveform. This lowers the average switching
rate of the device to two thirds of the original value. However, the harmonic content
increases significantly, which may offset the advantages of this gain [28].
This modulation strategy is most often implemented using microprocessor based

space vector modulation, but can also be implemented for sine-triangle modulation.
4.6. Conclusions 71
The addition of zero vector waveforms and the advantages to multilevel modulation
are discussed in section 6.2.
4.6 Conclusions
Multi modulator converters can achieve an effective increase in overall switch fre-
quency through the cancellation of the lowest order switch frequency terms. This
chapter has examined natural and uniform PWM modulation techniques to deter-
mine if this allows a similar effective bandwidth increase. The PWM output spectra
were calculated mathematically, simulated using Matlab, and collected from hard-
ware implementations of the modulators, and the results evaluated and compared.
Naturally sampled PWM does not attenuate or delay the synthesised fundamen-
tal, nor generate any distortion products of the fundamental. Restated another way,
the transfer function of a naturally sampled PWM modulator is a pure gain, and
places no limitations on the achievable bandwidth of the overall converter. If enough
harmonic cancellation is achieved using multilevel techniques and output filtering,
the modulating signal can even be higher than the switching frequency.
Although it appears more promising in theory, in practice, as the number of

converters increases, the variation between the analog generated carriers makes it
increasingly difficult to achieve good carrier cancellation. The digitally generated
uniform PWM can achieve consistently good cancellation of carrier terms. However,
uniform PWM attenuates the input signal and generates input signal harmonics;
these effects becoming more pronounced as the ratio f1 /fc rises. This limits uniform
PWM’s usefulness in low carrier frequency applications.
Lower sideband harmonics of the first non-zero carrier can also limit the large
signal bandwidth of both techniques. The most significant harmonics generally meet
the input signal when f1 /fc = 1, however their amplitude decreases as the number
of converters increase.
Chapter 5
Digital Natural — Re-sampled

Uniform
5.1 Introduction
As discussed in the previous chapter, uniform sampled and space vector PWM are
sampled data systems. They sample the signal input at the beginning of the switch
cycle, before the actual switching edge reflects this value later in the cycle. This
delay in response is significant when the ratio of switch frequency to carrier frequency
(the pulse number) is small. It leads to a frequency response roll-off which obeys
a Bessel function, similar to the familiar sinc function roll-off for Pulse Amplitude
Modulation (PAM). Another unwanted effect of uniform PWM is odd harmonic
distortion of the synthesised waveform. The severity of these effects is a function of
the ratio of the modulating and carrier frequencies, f1 /fc . This ratio may approach
and pass unity in high power active filters (high f1 , low fc ), by which point these
effects have become significant and limiting.
Naturally sampled PWM is traditionally an analog technique where the input

signal is naturally sampled by the carrier triangle waveform at the instant of the
switching edge. Naturally sampled PWM can react instantly to changes in input
74 Chapter 5. Digital Natural — Re-sampled Uniform
signal and produces no attenuation or distortion of the synthesised waveform. How-

ever as the ratio f1 /fc rises for a given modulation depth M , the slew rate of f1
will exceed that of the carrier triangle and an extra pulse will be generated. If
these additional pulses can be tolerated, the integrity of the synthesised waveform
is preserved.
So for a multilevel, low switch frequency converter, a naturally sampled PWM

modulator offers the most promise for wide bandwidth, low delay and low distortion.
Many multilevel converter implementations published in the literature demon-

strate their modulation technique using natural sampled carrier based diagrams.
Usually no explanation is given as to why this particular method is chosen. It is
assumed that clarity of explanation and understanding, or simplicity of implemen-
tation are two major reasons; rarely is the actual reasoning justified or explained.
However natural sampled PWM is invariably implemented as an analog tech-

nique. An analog technique does not lend itself to a high power multilevel imple-
mentation. Considering a multilevel converter consisting of a number of single level
modules, a digital implementation would be preferred because:
• Switching instants are crystal accurate, at least at the signal level. It is possible
to compensate for the switching delays in the power stages. More importantly,
the switching instants are repeatable from module to module. This ensures
good cancellation of the switching frequency terms in the combined multilevel
output.
• A digital microcontroller based implementation can be interrogated, tuned,

even reconfigured more easily than an analog one. These changes could be
made online, and again, would be consistent from module to module.
• A digital system can be distributed master slave style more easily than an
analog implementation, which is an advantage for a modular approach. Digital
signals are more easily shared among isolated modules.
5.2. Re-sampled Uniform 75
• Digital signals are more immune to noise than analog signals in a noisy high
power environment.
This is the motivation for seeking to create a digital implementation of naturally

sampled PWM.
To retain the versatility of the traditional analog implementation, the digital

implementation should accept an arbitrary real time input signal. Such signals will
occur when the modulator is in the feedback loop of a closed loop system, or part
of an active filter. The combined modulator and converter should still be able to be
modelled as a linear wideband amplifier.
The re-sampling technique allows fast control loops to benefit large, low switch-
ing frequency converters. For example, Tzou [62] has implemented a fully digital
controller for DC-AC inversion using a DSP. The sampling rate of the current loop
is 15.36kHz (256 ∗ 50Hz), and the switching frequency is twice this, as the converter
is a small UPS. A larger converter with a switching frequency many times lower
could still use this high sample rate to advantage using digital natural PWM.
5.2 Re-sampled Uniform
The first approach to generating a digital implementation of natural sampling pre-

sented here is most accurately described as re-sampled uniform. The switch fre-
quency of a large converter is often limited by its semiconductor switching devices,
particularly for GTOs. This is despite the capability of modern microcontrollers and
DSPs to sample and process control signals at a far higher rate. With re-sampled
uniform, although the same switching/carrier frequency fc is used, an attempt is
made to retain the wider bandwidth gained as a result of using a higher sampling
frequency fs . Samples are taken more frequently than once per switching edge at
the beginning of the PWM switch period. This is most easily achieved by sampling
at an integer multiple of the switching frequency. This ratio will be referred to as
the Re-Sampling Ratio, rsr = fs /2fc . Note that this is the number of samples per
Figure 5.1: From left to right, the existing techniques of symmetric and asym-
metric uniform sampling; and an extension of the concept, re-sampled uniform
sampling with re-sampling ratios (rsr) of 2 and 4.
switch edge for a single modulator/converter, rather than per pulse; hence the factor
of two.
Uniform sampling already comes in two variants — symmetric, where the sample
is held for the complete carrier period (rsr = 1/2); and asymmetric, where a second
sample is taken halfway through the carrier period for the second switch edge (rsr
= 1). Asymmetric uniform sampling is the preferred method, since each switching
edge is the result of a new sample and leads to better performance [9]. For both of
these cases, the reference is held constant throughout the switch period.
However, for a re-sampling ratio greater that one, one or more of the samples
will occur part way through the switch sub-period (Fig. 5.1). If according to a mid
switch period sample, the PWM edge is still to occur, then its position is recalculated
based on this more recent sample (Fig. 5.2A). This algorithm will react to transients
at the sampling rate rather than at the switching rate and so exhibit lower delay
and wider bandwidth. On average, the group delay of the input signal is now 1/2fs
rather than 1/2fc .
Two problems complicate the implementation of this technique. The first is

the possibility of missed edges — based on the previous sample, the edge is yet to
come; based on the current sample, the edge should have already occurred. The
best solution is to force the edge to occur immediately (Fig. 5.2B). As shown in
the figure, ‘immediately’ may not necessarily mean at the sampling instant, if some
computation delay must be allowed for in a software implementation.
The second problem is the possibility of generating more than one edge per
switching cycle. This happens when multiple intersections of the samples and the
5.3. Microcontroller Software Implementation 77
Vout
Vctrl
Vtri RSR=1 RSR=4 A C
B D
Figure 5.2: Re-sampled Uniform PWM — by re-sampling the input during the
switch cycle instead of only at the beginning, a more accurate switching edge
position can be calculated (A). However it is now possible to miss an edge (B) or
generate multiple edges (C&D).
triangular carrier occur, either erroneously, because of the stepped nature of the
sampled waveform (Fig. 5.2C), or quite legitimately — true natural sampling would
have done the same (Fig. 5.2D).
The problem of multiple edges is handled according to what is most expedient

to the implementation. In the microcontroller/software solution, only the first cal-
culated switching edge is accepted in each switch cycle. Any subsequent edges are
simply ignored. In the EPROM hardware approach, any edge is accepted, although
it would be an easy matter to latch only the first edge and reject subsequent edges
until the end of the switch cycle.
5.3 Microcontroller Software Implementation
The design of many microcontroller timer and PWM peripherals complicates or even
prevents the implementation of re-sampled uniform PWM. Double buffering and
FIFO (first-in, first-out) buffers, usually considered a feature, prevent the reloading
of the pulse width value. In these situations, the software must calculate and decide
whether the edge will occur in the current sample period, and only then load the edge
command and time. Further, an equality comparison between the pulse width value
and the timer (rather than a greater-than comparison) also requires the software
to ensure edges are not missed. These complications incur a considerable software
overhead and limit the useful possible re-sampling ratio.
This re-sampled technique was implemented on the Intel 80C196KB microcon-

troller. The samples were made by the internal 10bit ADC (analog to digital con-
verter). Within the ‘conversion finished’ interrupt routine, the microcontroller cal-
culated the position of the PWM edges, and decided if any edges should occur before
the next sample. If so, these were loaded into the timer module. To allow for this
computational overhead, a delay between sampling and loading edges must be in-
troduced. This delay was 100µs for this five level (four output) modulator. This
delay limits the useful re-sampling period and hence re-sampling ratio for a given
switching frequency for this processor.
The Motorola MC68332 microcontroller is an example of a more suitable choice

for a microcontroller implementation of re-sampled uniform. This has an intelligent
timer peripheral (TPU) which removes much of the computational overhead. The
PWM comparison is a greater-than comparison and pulse width values may be
reloaded part way through a PWM cycle. The TPU also has 16 output pins which
lends it to multilevel control.
5.3.1 Microcontroller Re-sampled PWM Results
Figures 5.3, 5.4 & 5.5 were collected from the five level 80C196 microcontroller im-
plementation, operating with a carrier frequency of 450Hz. The five level waveforms
were created by the summation of the four two level PWM waveforms at the logic
level. The circuit configuration is shown in appendix C.
Figure 5.3 shows 50Hz and 250Hz sine waves of modulation depth M = 0.9 and
the resulting five level waveforms. Although the synthesised fundamental frequency
f1 = 250Hz is a significant fraction of the carrier and hence switch frequency fc =
5.3. Microcontroller Software Implementation 79
Figure 5.3: An 80C196 generated five level waveform, fc = 450Hz, f1 = 50Hz

(left) and 250Hz (right), re-sampling ratio = 4 (fs = 3600Hz)
Figure 5.4: 80C196 re-sampled uniform. f1 = 250Hz M = 0.9, re-sampling ratio

= 1 (left) and 4 (right). (Averaged 64 times by the oscilloscope)
450Hz, a five level converter can produce a good approximation of the original. Note
that both of these waveforms were produced with an oversampling ratio of four.
The attenuation, distortion and delay inherent in uniform sampled PWM, and
then the improvement which can be achieved through re-sampling, are shown in
figure 5.4. The double edge (triangular carrier) uniform sampling converter sam-
ples at twice the switching frequency, 900Hz, which agrees with the average phase
delay seen in the fundamental of approximately 600µs (Ts /2). The odd harmonic
distortion is clearly visible.
The re-sampling ratio of four (fs = 3.6kHz) can be seen to reduce both delay
and distortion. The apparent delay of 200µs can be accounted for as 20µs for a/d
conversion, 44µs of delay deliberately introduced in the calculation of the edge times
to allow for computation time, and the average delay due to the sampling process of
140µs (Ts /2). The distortion is greatly reduced, but more interestingly, changes in
character. For simple uniform sampled, the distortion component is predominantly
third harmonic, the same as for two-level uniform sampled. The frequency of the
distortion component of the re-sampled uniform waveform is roughly 15 times f1 .
Figure 5.5: 80C196 re-sampled uniform. Re-sampling ratio = 1 (left) and 4

(right). (Below — Averaged 64 times by the oscilloscope)
The response to the sawtooth waveform shows the reduced delay, and hence
following error, and improved transient response due to re-sampling (Fig. 5.5). The
kink in the transient response is due to software latches (flags) which enforce only
one pulse per period. This was necessary due to the risk of overflowing the 80C196
timer FIFO. This demonstrates that strictly enforcing the switching frequency only
compromises the large signal transient response, or more correctly, the large signal
slew rate.
Because the PWM modulator was clocked from a crystal oscillator and not
phase locked to the input signal as it should be for truly synchronous PWM, the
PWM waveform slowly slipped with respect to the input waveform. This allowed
the oscilloscope to be used to average the waveform over 64 successive triggers.
5.4 Gate Array Implementation
The next approach documented here was a hardware implementation using a field
programmable gate array (FPGA) — the Altera FLEX series of SRAM based pro-
grammable logic.
A three phase, five level (twelve output) modulator was implemented in an Altera
5.4. Gate Array Implementation 81
FLEX 8820, initially with seven bit resolution, which was then extended to eleven bit
resolution (Fig. 5.7). The DSP interface to this PWM peripheral was through four
16 bit memory mapped registers, three for each of the PWM phase inputs, and the
fourth for configuration. A tap from the timer chain updated (latched) the new data
to the comparators synchronously. This tap position was programmable to enable
different re-sampling ratios to be evaluated. Similar circuitry (not shown) generated
the trigger signal for the ADC and subsequent DSP interrupt. Programmable dead
time (also omitted) was later implemented for each switch pair. A full set of circuits
for the seven bit implementation is given in appendix C.2.
The FPGA was part of a DSP (the TMS320C31) based controller board. As
well as the FPGA, other key components were external RAM and boot EPROM, a
serial port, four 12 bit analog to digital converters and a quad 8 bit digital to analog
converter.
Leading or trailing single edge pulse width modulation can be easily generated
digitally with an up or down counter, and a digital comparator. Double edge modu-
lation has previously been implemented with up-down counters. For this multilevel
implementation, a novel technique has avoided the need for multiple, synchronised
up-down counters. All the phase shifted double edge PWM outputs are generated
from a single up counter reference (Fig. 5.6).
Double edge PWM can be generated with a sawtooth carrier if the leading and
trailing edges are generated by two separate comparators. A sawtooth rather than
a triangular carrier only requires a unidirectional counter rather than the more
complex up-down counter. This sawtooth carrier can then be phase shifted trivially
by simply manipulating the most significant bits.
Because the two comparators are created using combinatorial logic, many of the
terms are common to both and so they do not consume many more resources than
a single comparator would. An up-down counter however is generally more complex
and resource hungry. The one counter is also common to all modulation and carrier
phases, which ensures that the entire modulator is synchronised at all times.
F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 C
5 4 (B) 3 (C) 2 D (D)
(D<C) . (D>C)
C D
A B
5 4
3 2
Figure 5.6: The operation of the programmable gate array implementation of

re-sampled uniform. A four bit counter value (C) is compared with a three
bit modulating value (D) and its complement (D̄) to create PWM with three
bit resolution. Two separate comparators implement double edge PWM, one
generates the leading edge, the second the trailing edge.
2 12
12b Phase
Synch Shifter
Counter 12 2 X<Y
T10,11 DFF
T9-0 10 Clk
Clk
8
Mux Double edge
X>Y
T11-3 1of 8 digital comparator
3
D2-0
Double edge
A11-0
digital comparator
DFF
DFF
B11-0
C11-0
Double edge
digital comparator
Data15-0 16
D15-0
DFF
/wr 5-level PWM Double edge
/cs Generator. digital comparator
2-4 One of Three
Addr1,0 2
Figure 5.7: The block diagram of the programmable gate array implementation
of re-sampled uniform.
1 1
rsr=8
0.8 0.8
rsr=4
0.6 0.6
rsr=2
0.4 0.4
0.2 0.2
Uniform
0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Figure 5.8: The transfer functions for different re-sampling ratios are shown
for the 9 level EPROM re-sampled uniform modulator (left) and Flex digital
natural implementation (right) for modulation depth M = 1.0, plotted against
1/N = f1 /fc . The transfer function of the previously analysed 80C196 based
uniform modulator (conventional uniform - no re-sampling) is shown dashed for
comparison.
5.4.1 Results — Gate Array Implementation
For the evaluation of the system, the DSP simply read the ADC result, scaled it, and
then wrote the result to the PWM peripheral. The Tektronix spectrum analyser was
again used to provide the stimulus and evaluate the transfer function. The transfer
function of this modulator was captured and plotted for a number of re-sampling
ratios for the modulation depth M = 1.0 (Fig. 5.8).
Bandwidth improvent vs. resampling ratio
Using re-sampling is seen to improve the frequency response of the modulator, pro-
ducing a family of curves similar to those produced for uniform modulation for
different modulation depths (Fig. 4.17). As expected, less roll-off occurs for larger
re-sampling ratios. Specifically, figure 5.22 shows that every doubling of the re-
sampling ratio is equivalent to the improvement in bandwidth that occurs when the
modulation depth is halved for uniform sampling.
1.4
1 0.033
1.2 0.067
0.10
1
0.8
0.20
0.8
0.6
0.6
0.4 0.30
0.2
0.4
0
0
0.2 0.2
0.4
0.6
0.5 0
0.8 1.5 1
2.5 2
1 3.5 3 0
4.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Figure 5.9: These three dimensional waterfall plots show the transfer function
of the re-sampled uniform modulator (DSP-Flex) plotted against frequency (0 <
f1 /fc < 5) for different modulation depths (0 < M < 1). These are for a re-
sampling ratio of four.
1.4
1 0.03
1.2 0.07
0.10
0.13
1
0.8 0.17
0.8
0.20
0.6
0.6
0.4
0.2 0.4
0
0
0.2 0.2
0.4
0.6
0.5 0
0.8 1.5 1
2.5 2
1 3.5 3 0
4.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Figure 5.10: Transfer function for differing modulation depths as before, but for
a re-sampling ratio of eight.
1.4
1 0.03
1.2
0.07
1
0.10
0.8
0.8
0.6 0.13
0.6
0.4
0.17
0.2 0.4
0 0.20
0
0.2 0.2
0.4
0.6
0
0.8 2
4
6
1 10
8 0
12 0 1 2 3 4 5 6 7 8 9 10
Figure 5.11: Transfer function for differing modulation depths, re-sampling ratio
of eight (as above). Note the different x-axis scale for 1/N
Bandwidth vs. modulation depth
It was also expected that there would be less roll-off for lower modulation depths
for a given re-sampling ratio, as was the case for uniform sampling. To test this,
a family of 30 transfer function curves was gathered for this DSP-Flex modulator.
The modulation depth was varied from 0.033 to 1.0 while the re-sampling ratio was
held constant, first at four, then eight. It can be seen from the plots (Fig. 5.9,
Fig. 5.10) that the transfer function is relatively independent of modulation depth
until the modulating signal’s amplitude falls below 1/rsr.
At this point the roll-off improves for smaller values of M . The attenuation
curves then closely match the uniform sampled case. However the delay will be
greatly reduced. This is the expected result.
Some understanding of this behaviour is gained by examining the process of

re-sampling (Fig. 5.12). For example, a six level (five carrier) converter which re-
samples a modulating sinusoid M = 0.2 five times during one edge period will have
an identical spectrum to that of a doubled edged uniform converter, with switch
frequency five times that of the converter and a modulation depth M = 1.0.
The magnitude of the modulating signal component (m = 0, n = 1) in the PWM

output spectrum is (referring to equation 4.6)
Jn (M (m + nw1 /wc )π/2) m=0,n=1 J1 (M π/2 w1 /wc )

−→
(m + nw1 /wc )π/2 π/2 w1 /wc
Here the equivalent carrier frequency wc has been increased five times, however, the
equivalent modulation depth M has also increased by the same amount so that the
argument of the Bessel function is the same for both. Thus, the transfer functions
for the cases M = 1.0, rsr = 1 (asymmetric uniform sampling) and M = 0.2, rsr
= 5 should be the same.
The delay and hence phase shift of the re-sampled modulator will however be
Original
Alternative
P.O.V.
Figure 5.12: This alternative point of view of the creation of the multilevel wave-
form, suggests an alternative derivation of the mathematical description of the
multilevel PWM waveform.
approximately one fifth of the uniform sampled modulator, which will improve the
transient response and stability under feedback.
Further results
Later programming implemented a simple three phase five level induction motor
drive, which used sinusoidal plus third harmonic modulation and followed a constant
Volts per Hertz modulation strategy. A five level flying capacitor converter based
on MOSFETs was built and the complete system used to drive a small 0.5 kW three
phase induction motor. Some results collected from this converter are presented in
the next chapter.
5.5. EPROM Based Implementation 87
5.5 EPROM Based Implementation
A second approach to generating digital PWM is a completely digital hardware

approach. It is better described as digital natural, as its operation is directly com-
parable to an analog natural PWM modulator. A digital comparator compares the
modulating input data value with a triangular carrier data value to generate the
output PWM waveform.
An EPROM look up table performs the digital comparison and also effectively
holds the triangular carrier waveform (Fig. 5.14). It is addressed by two values — the
modulating input data value, and a clock value generated by a digital synchronous
binary counter. This counter steps the EPROM through the comparison with the
triangular carrier waveform, overflowing at the carrier frequency (Fig. 5.13). This
allows a simple implementation of multiple comparators each with an appropriate
offset (phase shift). The EPROM also easily encodes both slopes of vtri , without
the need for an up-down counter.
The modulating input data value as shown here is generated by an analog to

digital converter. In practice, it is most likely that this digital value will be output
directly by a microcontroller or DSP, so that the control signal never leaves the
digital domain.
The PWM input data value may change at any time, asynchronously if desired.
The output will immediately reflect this change because the EPROM performs a
greater than comparison combinatorially. Although asynchronous sampling is pos-
sible, it will lead to distortion, unless the sampling rate is many times higher than
the switch frequency.
Three large (217 ∗ 8 = 1Mbit) EPROMs can implement three phase nine level
natural PWM with 8 bit resolution (Fig. 5.13). For higher carrier frequencies, this is
an acceptable resolution, especially when combined with a resolution enhancement
technique which accumulates and corrects for the truncation error [26].
Higher resolution can be obtained by cascading two EPROMs. The EPROM

ADC 8
D Q A9-16
go
ROM
8
D0-7 D Q
9
A0-8
Binary
Counter
(PLD)
osc
Figure 5.13: The simple hardware implementation of EPROM based oversampled

PWM .
Counter input
012 ... DEF 012 ... DEF 012 ... DEF
7 0111111111111110 1110011111111111 EFFDDFFBBFF77FFE

P 6 0011111111111100 1100001111111111 EEDDDDBBBB7777EE
W 5 0001111111111000 1000000111111111 ECCDD99BB337766E
M 4 0000111111110000 0000000011111111 CCCC999933336666
3 0000011111100000 0000000001111110 ... 4CC8899113322664
i 2 0000001111000000 0000000000111100 4488881111222244
n 1 0000000110000000 0000000000011000 4008800110022004
0 0000000000000000 0000000000000000 0000000000000000
D0 D1 etc... (D3:D2:D1:D0)
Figure 5.14: The structure of the contents of the PWM EPROM. This example
is compares a three bit PWM value with a 4bit counter value. Four outputs
suitable for a five level converter have been programmed.
which compares the upper bytes of the count and data values must generate an
equality output as well as a greater than comparison, to enable cascading.
The eight outputs of the EPROM can control eight pairs of switches to create
nine level PWM. Several EPROMs can also be placed in parallel to create more
than eight outputs for large converters, or for generating other synchronised control
signals such as commutation pulses.
It may at first seem possible to control eight switches individually (five level
PWM) to allow dead time to be programmed into the EPROM. However dead
time cannot be created purely combinatorially, but requires state information. For
example, an update of the input sample just after one output has switched could
cause the second output to switch instantaneously, before the required dead time
has elapsed.
The contents of the EPROM were created using a MATLAB script (see sec-
tion B.1.3). This vector was saved as a .mat binary data file, with one byte per
element. The header was then removed, leaving a raw binary file suitable for an
EPROM programmer. A simple C program could have equally been used to create
the required EPROM file.
5.5.1 Carrier Variations
To date, only the case of equally phase shifted triangular carriers has been considered
for carrier based multilevel PWM. This in theory makes the best use of the multilevel
converter, achieving complete cancellation of a number of lower carrier groups. This
achieves the minimum possible ripple current and waveform distortion.
However, some alternative arrangements of the carriers can be advantageous in

the real world implementation of some multilevel converters. The use of a lookup
table programmed into an EPROM to implement carrier based PWM can achieve
effects which would be very difficult otherwise. Some of these variations follow.
Variable Carrier Period
As explained in the previous chapter (see fig 4.2), any carrier composed of purely
straight line segments will produce a linear, distortion free transfer function. The
slopes of these lines, and hence the pulse period, may however vary, spreading the
spectral power of the carrier tones.
An EPROM implementation may clock through several slightly differing carrier

periods before overflowing and repeating the sequence. The digital modulation input
should be updated at the beginning of each of these periods to ensure the modulating
signal is reproduced undistorted. One of EPROM output bits can be used to latch
the new value at the (now random) beginning of the period.
A more detailed examination of the implementation of random modulation for

multilevel converters appears in a later chapter.
Duty Cycle Limitation
A clipped carrier waveform will ensure that the duty cycle can never reach 0 or
100%. This guarantees a switch pulse every cycle, which is important if
• the power supplies for the switch drive circuits are bootstrapped.
• the rise and fall times are significant, causing unacceptable non-linearities in
the transfer function as the pulses are dropped at the extremes of modulation.
• minimum switch on or off times must be observed.
The full modulation depth can be used while still observing minimum on and
off times by pulse dropping a proportion of pulses at the extremes of modulation.
Non-linear Transfer Function
Carriers which can implement non-linear transfer functions such as signal compres-
sion at high amplitudes to give “soft clipping”, or to give higher gain to smaller
signals are easily and accurately encoded in an EPROM implementation. Most of
these steps could be easily performed in software or analog hardware, however as
explained, a digital implementation can have some advantages.
Alternate Multilevel Carrier Arrangements
APO PO PH
A digital implementation is far better suited to the creation of alternative carrier

arrangements, such as those suggested by Carrara et al [14]. Although inferior
in the single phase case, three phase converters can benefit from the alternative
multilevel carrier arrangements of Phase Harmonious (PH) and Phase Opposition
(PO) when compared with the traditional Alternate Phase Opposition (APO) carrier
arrangement.
Alternate Multilevel Carrier Phasing
AA’
BB’
Vo
Vd
In some multilevel converter topologies, the individual PWM waveforms are summed
with the aid of passive components, for example inter-phase reactors or flying ca-
pacitors. The difference in phase between the PWM waveforms is carried by these
components. To reduce the size or ratings of these passive components, it may be
better to sacrifice the perfect spectral cancellation of carriers that can be achieved
with equal phase shift between triangular carriers, and instead lower the phase dif-
ference between PWM waveforms.
For example, reducing the phase shift to a fraction of its ideal value lowers the
required Volt-Second rating (i.e. iron content) of an inter-phase reactor in a parallel
connected multiple bridge converter. Similarly, the capacitance value of the flying
capacitors in a flying capacitor converter can be reduced for a given voltage ripple
and load current by reducing the phase shift between carriers.
AA’
BB’
Vo
Vd
By controlling the difference between the PWM waveforms, it is possible to

correct volt-second imbalances in these inter-phase reactors, again at the cost of
imperfect carrier cancellation. The sum of the PWM waveforms and hence the fun-
damental output of the multilevel converter can remain unaffected. In an EPROM
based modulator, this can be easily achieved by swapping between two (or more)
“pages” of carriers, based on the calculated or measured volt-second imbalance. In
other implementations (such as for the FPGA modulator which follows), this can
also be achieved using separate modulating signals for each PWM output.
Controlling the voltages in a flying capacitor converter is more involved, since

the voltage slew on the flying capacitors is dependent on the magnitude and phase
of the load current, as well as the phase difference of the carriers [24]. For example,
the correcting signal which creates the difference between the carriers must at least
reverse sign when the power flow and hence load current reverse to ensure the flying
capacitor voltages always converge towards their desired value under closed loop
control. When the load current is very small, the convergence of the capacitor
voltages to their equilibrium state will be very slow.
5.5.2 Results of EPROM Implementation
The actual circuitry used for gathering results consisted of a 4Mbit EPROM which
allowed 9bit PWM (see Appendix C.1). A 12bit, 8µs analog to digital converter
(AD7870) was used to supply the digital input value. Only the 9 most significant
bits were used. The binary counter and decoding logic which starts the ADC and
then latches the result is implemented in an EPLD (erasable programmable logic
device). This allowed a number of re-sampling ratios to be evaluated.
All eight phase shifted outputs of the EPROM based hardware modulator were
used to create nine level waveforms in figures 5.15–5.20. The great advantage of
multilevel conversion can be seen from figure 5.15 where the nine level waveforms
and the two level PWM signals which form it can be compared. Again the switch
frequency fc is 450Hz.
The impact of re-sampling is again evident in figures 5.16 & 5.17 where the
improvement as the re-sampling ratio is increased from 4 to 64 is clearly seen.
Minimum Valid Re-sampling Ratio for EPROM implementation
The re-sampling ratio of 4 is the minimum sensible value for this hardware imple-
mentation, as all phase shifted carriers share the same sampled input value and
sampling instant. For ratios less than 4 for 8 carriers, some carriers will be up-
dated midway through their cycle, but not at the beginning. For example, for a
re-sampling ratio of two, four of the carriers will be updated at 0, 90 180 & 270
degrees and the other four at 45, 135, 225 & 315 degrees. This can lead to a rapid
deterioration in performance for some input signals. It also spoils the cancellation
of the carriers and sidebands in the frequency domain. For the above example, one
would expect the first carrier and sidebands to be centred around 8 ∗ fc , however
those around 4 ∗ fc are not properly cancelled.
Compare this to the microcontroller implementation for five level, uniform with
no re-sampling. Here the waveform is sampled only once at the beginning of each
switch period for each of the phase shifted carriers. So the sampling rate is doubled,
but the re-sampling ratio remains one.
In general, the re-sampling ratio should ideally always be chosen so that each
Figure 5.15: EPROM re-sampled uniform, 9 level, fc = 450Hz, f1 = 50Hz (left)

and 250Hz (right), M = 1.0. 57.6kHz sampling ratio (re-sampling ratio 64)
Figure 5.16: EPROM re-sampled uniform, f1 = 250Hz, M = 1.0, re-sampling

ratio = 4 (left) and 64 (right). (Below — Averaged 64 times by the oscilloscope)
Figure 5.17: EPROM re-sampled uniform, f1 = 250Hz sawtooth, M = 0.8. re-

sampling ratio = 4 (left) and 64 (right). (Below — Averaged 64 times)
rsr
1/
2
Figure 5.18: For an five level converter, only a re-sampling ratio of two (or
greater) makes sense, since this is the lowest value which updates the sample at
the beginning of every carrier waveform. The PWM waveforms which result from
re-sampling ratios of a half, one, and two are shown, for the EPROM implemen-
tation (simultaneous sampling).
carrier triangle edge is presented with a new sample at the beginning of its sub-cycle.
For an even number of carriers, nc (an odd number of levels), carriers always come
as nc /2 inverted pairs, with their vertices (beginning of their switch cycles) at the
same instants. The required re-sampling ratio is nc /2, and so the required sampling
frequency is nc /2 ∗ 2fc = nc ∗ fc . For an odd number of carriers, the re-sampling
ratio must be at least nc to satisfy this condition.
Multiple Edges Resulting from Re-sampling
The excellent transient response which results from re-sampling is particularly evi-
dent in figure 5.17. Also evident is the possibility of producing multiple edges per
switch cycle, which may be unacceptable in some converters, even on a transient
0
10
−1
10
−2
10
−3
10
0 200 400 600 800 1000 1200 1400 1600 1800 2000
0
10
−1
10
−2
10
−3
10
0 200 400 600 800 1000 1200 1400 1600 1800 2000
0
10
−1
10
−2
10
−3
10
0 200 400 600 800 1000 1200 1400 1600 1800 2000
0
10
−1
10
−2
10
−3
10
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Figure 5.19: The PWM time domain waveforms (left) and frequency domain
spectra (right) for a five level EPROM based PWM modulator, shown for the
re-sampling ratios of 0.5, 1, 2, and 4. To ensure the complete cancellation of the
carrier and sidebands which are not multiples of the effective carrier frequency,
each pulse must be the result of a new sample - the equivalent of symmetric
sampling (fs = fc ). For a five level converter, this requires a re-sampling ratio of
at least two. A new sample for every edge (the multilevel equivalent of asymmetric
sampling) will of course produce a better result.
Figure 5.20: EPROM re-sampled uniform, fc = 450Hz. f1 = 950Hz (19th har-

monic), so N < 0.5. Modulation depth M = 0.1. 57.6kHz sampling (Oversam-
pling ratio = 64). (Right — Averaged 64 times by the oscilloscope)
basis. This may be avoided by latching the first edge for each cycle and ignoring any
subsequent edges in that switch cycle, as was done in software in the microcontroller
implementation. The ultimate solution is to limit the slew rate of the input signal,
which limits the power bandwidth, but not the bandwidth as such. For example, a
950Hz sine wave (the 19th harmonic in a 50Hz system, and over twice the 450Hz
switch frequency) can be faithfully reproduced by a nine level converter at 10%
modulation depth without producing multiple edges per switch cycle (Fig. 5.20).
To avoid multiple switching edges in each cycle, the analog or digital circuitry
preceding the modulator could include slew rate limiting. However this will com-
promise the transient response, one of the advantages of digital natural. A better
approach would be to have the digital or analog signal processing tuned so that in
the steady state, the modulating signal remains within the slew rate limit. Then
multiple edges are only generated in transient conditions. Alternatively for GTO
applications, monostables and latches could be placed after the ROM to ensure
minimum pulse widths.
5.5.3 Bandwidth improvent vs. resampling ratio
In order to quantify the improvement in bandwidth achieved through the use of re-
sampling, the transfer function of the 9 level EPROM based re-sampled modulator
was measured using the spectrum analyser. The results were measured at two
specific modulation depths, M = 1.0 and M = 0.2, for several different re-sampling
ratios (Fig. 5.21).
1 1
rsr=8
rsr=8
0.8 0.8
Uniform
rsr=4
0.6 0.6
rsr=4
rsr=2
0.4 0.4
rsr=2
0.2 0.2
Uniform
0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
for the 9 level EPROM re-sampled uniform modulator, for modulation depths
M = 1.0 (left) and M = 0.2 (right). The transfer function of the previously anal-
ysed 80C196 based uniform modulator (conventional uniform - no re-sampling)
is shown dashed for comparison.
0.075
rsr=16
0.8
0.15
rsr=8
0.6
0.30
rsr=4
0.4
0.60
rsr=2
0.2
Uniform
0
0 1 2 3 4 5 6 7 8 9 10
for the 9 level EPROM re-sampled uniform modulator, for modulation depths
M = 1.0. The fractional numbers indicate the equivalent 2 level modulation
transfer function.
For the 9 level converter shown, the first uncancelled carrier and sidebands are
centred around eight times the switch frequency. The usable bandwidth in theory
extends to four times the switch frequency, at which point the modulating term
meets the first significant lower sideband harmonic. This point of conflict can be
seen as a burst of noise in the transfer function.
The lowest re-sampling ratio shown is two and is not a good choice for the 9
level converter assessed. As previously explained, four of the eight carriers are not
updated with new samples at the beginning of their switch cycle. This leads to poor
performance at higher frequencies and incomplete cancellation of the fourth carrier
harmonic and its sidebands. These sidebands can be seen to upset the transfer
function measurement at twice the carrier frequency.
For the modulating depth M = 1.0, using re-sampling is seen to improve the
frequency response of the modulator, producing a family of curves similar to those
produced for uniform modulation for different modulation depths (Fig. 4.17). As
expected, less roll-off occurs for larger re-sampling ratios. Specifically, figure 5.22
shows that every doubling of the re-sampling ratio is equivalent to the improvement
in bandwidth that occurs when the modulation depth is halved for uniform sampling.
It was also expected that there would be less roll-off for lower modulation depths
for a given re-sampling ratio, as was the case for uniform sampling. However, the
family of curves for modulation depth M = 0.2 is almost identical to those for
M = 1.0. Indeed, uniform modulation (dotted) performs better than re-sampled
uniform at low re-sampling ratios.
To confirm this, another family of 30 transfer function curves was gathered. This
time the modulation depth was varied from 0.033 to 1.0 while the re-sampling ratio
was held constant, first at four, then eight. It can be seen from the plots (Fig. 5.23,
Fig. 5.24) that the transfer function is relatively independent of modulation depth
until the modulating signal’s amplitude falls below 1/rsr.
Unfortunately, the deterioration of the transfer function at low modulation

1.2
1
1
0.8
0.6 0.8
0.4
0.6
0.2
0 0.4
1
0.8 5
0.6 4 0.2
0.4 3
2
0.2 1
0
0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Figure 5.23: These three dimensional waterfall plots show the transfer function
of the re-sampled uniform modulator plotted against frequency (0 < f1 /fc < 5)
for different modulation depths (0 < M < 1). These are for a re-sampling ratio
of four.
1.2
1
1
0.8
0.6 0.8
0.4
0.6
0.2
0 0.4
1
0.8 6
0.6 5 0.2
4
0.4 3
0.2 2
1 0
0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Figure 5.24: Transfer function for differing modulation depths as above, but for
a re-sampling ratio of eight.
5.6. Conclusions and Applications 101
depths as seen in the gathered experimental data is the opposite of what this expla-
nation suggests. It appears these results are incorrect, as the identical set of results
gathered from the gate array implementation performed as the theory suggested.
A reason for the generation of these apparently incorrect results at low modulation
depths is yet to be established.
5.6 Conclusions and Applications
Natural sampled PWM is the best choice for applications which require closed loop,
wide bandwidth modulation such as active power filtering. It does not attenuate
or distort the modulating signal, even when the frequency of that signal is similar
to the switch frequency. Carrier based PWM is also easily adapted to multilevel
converter modulation by phase shifting the carriers.
A digital implementation is preferred for multilevel modulation. Switching edges

with crystal accuracy and more importantly repeatability are needed to give the
best carrier cancellation in a multilevel converter. Digital control is more easily
modularised and is more noise immune.
Re-sampled uniform PWM is a digital implementation which approaches the

frequency and transient response of natural PWM. Both hardware and software
multilevel implementations are presented and the improvement over uniform PWM
is demonstrated. For moderate re-sampling ratios of four or eight in the five and nine
level modulators evaluated, the transfer function of the modulator becomes relatively
independent of modulation depth. Starting from a modulation depth M = 0, the
re-sampled transfer functions are roughly equivalent to the uniform sampled transfer
functions until the modulation depths M = 1/4 and 1/8 respectively are reached.
The re-sampled transfer functions then remain essentially fixed as the modulation
depth is increased.
Chapter 6
Random Carriers and Zero

Vectors
6.1 Extending Random Modulation Techniques to
Multilevel
Carrier pulse width modulation produces a pulse each switch period with a width
proportional to the desired modulating value. The actual switch period may vary
from cycle to cycle without distorting the reproduction of the modulating waveform
so long as this proportionality is maintained.
Random modulation techniques produce a continuous spectrum, by using a vari-

able switch period, that is, an aperiodic carrier. What were previously discrete
spectral lines are spread into bands of frequency energy, whose peak is lower than
the original discrete line The total energy remains equal however.
Now that the period is no longer constant, it would seem difficult to achieve
multilevel cancellation, as this relies on being able to create “harmonic cancelling”
carriers by phase shifting. The term “harmonic cancelling” carrier is used here
to mean a carrier which, as part of a set of carriers, causes groups of carrier and
104 Chapter 6. Random Carriers and Zero Vectors
sideband harmonic terms to be greatly attenuated by cancellation in the multilevel

PWM frequency spectra.
Given a single triangular carrier whose period has been perturbed either side of
its average period, a second harmonic cancelling carrier can be created by simply
inverting this carrier. So generation of random PWM for a three-level converter is
trivial.
However, with the carrier period no longer constant, the meaning of carrier phase
is no longer clear. How can further harmonic cancelling carriers be generated? Is
there a simple technique for the creation of random PWM for the general N-level
converter?
6.1.1 Matlab Experiments
A number of methods of generating random harmonic cancelling carriers sets were

tried in Matlab. As explained, generating the first pair of harmonic cancelling
carriers (enough for three-level) was straight forward.
First, a vector of random periods that had a uniform random distribution be-
tween 90 and 110% of the average period (256 counts) was created. This vector was
then rounded so that each period was an integer. A single triangular carrier cycle
was created for each of the periods in this vector, to form a triangular carrier with
>> perchk = zeros(9,10); >> perchk = zeros(9,10);

>> perchk(:) = pwmper >> perchk(:) = pwmper
perchk = perchk =
245 254 268 257 240 251 251 277 253 263 263 238 250 254 252 234 278 261 281 273
237 240 263 273 270 233 243 245 249 248 264 245 257 250 247 241 261 269 231 273
265 244 256 244 253 255 241 241 250 271 263 265 248 238 257 259 249 275 278 264
264 257 269 241 255 254 240 244 261 269 271 274 244 269 267 273 254 237 240 268
272 240 268 245 267 252 285 252 252 268 250 247 245 264 274 252 263 236 280 263
231 270 248 262 239 255 256 264 238 247 249 238 273 231 242 273 279 264 257 248
264 264 229 274 264 267 248 257 265 228 250 261 237 271 254 245 251 273 245 258
272 277 243 250 261 277 285 264 281 252 248 231 263 259 250 240 233 260 267 264
254 258 260 258 255 260 255 260 255 258 266 278 233 245 233 249 253 264 261 255
>> mean(perchk) >> mean(perchk)

ans = ans =
256 256 256 256 256 256 256 256 256 256 258.2 253 250 253.4 252.9 251.8 257.9 259.9 260 262.9
Figure 6.1: The creation of two random period vectors by Matlab. In the case on
the left, every nine (since N = 9) carrier periods sum exactly to the modulating
period to ensure the zero crossings of the carrier and modulating waveform co-
incide. This “synchronous” carrier was compared to the purely random case on
the right to examine whether any additional sub-harmonics were suppressed.
6.1. Extending Random Modulation Techniques to Multilevel 105
constant amplitude, but with each cycle slightly different in period. This carrier
was compared with the modulating sine wave using naturally sampled PWM. Nat-
ural PWM was used to avoid clouding the results with the distortions attributable
to uniform PWM. It was reasoned that natural PWM could be approximated in
practice with the new re-sampled uniform techniques.
The carrier was asynchronous — no attempt was made to align the beginning
of the (N+1)th carrier period with the zero crossings of the modulating sine wave.
However the total period of the vector was corrected to avoid any problems in the
FFT. A “synchronous random carrier” (a contradiction in terms?!) was also tried.
Here the sum of each N carrier periods was adjusted to be equal to the modulation
waveforms period to ensure synchronous operation, if this has any meaning here.
That is, each time the modulating sine passed through zero, the carrier was also at
the beginning of a cycle. An example of two random period vectors created with
Matlab are shown in figure 6.1.
The second carrier was easily formed as explained earlier, by simply inverting
this carrier. This technique was valid and all simulations had the odd carrier groups
cancelled as expected. However, the goal was to create four harmonic cancelling
carriers for a five level converter, using a technique which could be easily generalised.
A method for creating further pairs of carriers which would cancel in a multilevel
converter was not obvious.
The first attempt was to form another random sequence, phase shift it by π/2
of the average carrier period, then form its inverted pair. This was unsuccessful
(Fig. 6.2). The first and all odd carriers and sidebands were cancelled as expected,
but the second, sixth, etc. were only slightly attenuated. The pulse polarity rule was
not always observed either. On examining the individual carriers it was noted that
although the periods only varied between 90 and 110 percent of the nominal value,
several consecutive shorter or longer periods caused the two carrier pairs to move in
phase with each other. It was concluded all random carriers should be related.
Based on this assumption, the second approach tried was simply to produce a
0 0
10 10
−1 −1
10 10
−2 −2
10 10
−3 −3
10 10
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
Figure 6.2: Two separate random carrier pairs only cancelled the odd carrier
groups; as either pair would have done on its own. (left: two-level spectra, and
right: five-level spectra). This is with pulse number N = 9 (i.e. fc = 450Hz if f1
= 50Hz), modulation depth M = 0.9, and a carrier period uniform deviation of
± 10%. The carrier and modulating waveforms were asynchronous.
second pair of harmonic cancelling carriers by shifting the first pair by π/2, based
on the average period. This produced the expected result of attenuating the second,
sixth, etc. carrier groups significantly, but not completely (Fig. 6.3).
Ensuring the random carrier is synchronous — both the modulating waveform

and carrier have matching zero crossings — as compared with asynchronous appears
to make no difference to the amplitude of the sub-harmonic components (Fig. 6.3).
This constraint does however reduce the randomness of the carrier, so that the carrier
and sideband harmonic terms are more distinct, with a higher amplitude. Since
the synchronous generation of random switch periods appears to have no beneficial
effect on the sub-harmonic performance of the modulator, but only complicates the
software, it is dropped at this point. The only constraint on the random periods
in the simulations is to ensure there are an integral number of switch cycles in the
time vector. This ensures an accurate DFT without the need for windowing.
6.1.2 A Different Perspective
The traditional method of generating harmonic cancelling carriers is based on phase

shifted triangular carriers. Each triangular carrier has the same amplitude as the
maximum possible modulation depth and a frequency equal to the switch frequency.
0 0
10 10
−1 −1
10 10
−2 −2
10 10
−3 −3
10 10
−4 −4
10 10
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
Figure 6.3: Here the second pair of random carriers were generated simply by
delaying the first pair by π/2. This is partially successful. (Two and five level
spectra overlayed). Also shown is the difference between ensuring the PWM
is synchronous each fundamental period (left), and not bothering (right). Sub-
harmonics seem unaffected, as does the multilevel spectra, although the difference
between the single level spectra is clear. When overlayed, the shape and ampli-
tude of the curves are almost identical. (N = 9, M = 0.9, dev = ±10%)
The PWM output of the comparison of this waveform and the modulating signal is
correct in its own right and can be used to modulate a single pair of switches in a
phase-leg of a two level converter. A further m − 1 carriers may be generated each
separated by an equal 2π/m phase shift. The resulting PWM signals can be used to
switch further switch pairs. When summed by the multilevel converter structure, a
multilevel waveform is formed.
This technique of forming a multilevel modulator is favoured because it is con-

ceptually easy to understand, as it is simply an extension of the two level modulator.
Its performance and spectra can be mathematically analysed by extending existing
two level results. Its implementation in analog hardware is straight forward. It
distributes the switching instants evenly automatically.
However as demonstrated, trying to extend this understanding of modulation

with a random carrier does not work. A different starting point suggests the correct
way to create a set of harmonic cancelling random period carriers (Fig. 6.4). The
clue to this line of thought stems from the work of Carrara et al [14] into alternative
multilevel carrier arrangements (section 5.5.1).
Holtz defines one carrier half period as a sub-cycle. Each of the three half
Original
Tc = 1 / fc
Random
A
(failed)
To = 1 / 8 fc
Alternative
P.O.V.
Random
B
(success)
Figure 6.4: The multilevel modulator is traditionally viewed as using a number

of identical phase shifted carriers (top). Attempting to vary the period of these
carriers independently of one another fails to lead to carrier cancellation in the
multilevel spectra. An alternative decomposition of the multilevel carriers is into
individual carriers of four times the frequency and one quarter of the amplitude
of that of the original carriers. Randomising the period or half-period of these
carriers successfully leads to carrier cancellation.
bridges in a three phase converter will make one transition in a sub-cycle [7]. For
a five level converter, in one carrier period or cycle each of the four switch pairs
(PWM waveforms) in a phase leg will switch on once and off once, so in fact there
will be eight transitions instead of just two at that converter phase output. We can
generalise the definition of sub cycle to cover the multilevel case as being the period
during which each of the phase outputs makes one transition. Using this definition,
a sub cycle T0 = 1/8fc for a five level converter.
All that is necessary for distortion free modulation is linearity over each single
switch sub-cycle. Since the load averages or integrates the stepped output of the
converter, if the area under the converter’s output equals the area under the input
modulating signal over a given period, then the modulating signal will be reproduced
faithfully (Fig. 6.4). This is true for naturally sampled PWM over a sub-cycle, even
if the period of that sub-cycle is varied.
0
10
−1
10
−2
10
−3
10
−4
10
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Figure 6.5: A successful demonstration of the cancellation of the first three carri-
ers and their sidebands achieved by varying the sub-cycle period T0 for all carriers
at the beginning of each sub-cycle. (N = 9, M = 0.9, dev = ± 10%, two and
five-level spectra overlayed)
So a new sub-cycle period T0 can be set randomly at the beginning of every

sub-cycle period or multiple thereof without causing distortion. This also leads to a
set of harmonic cancelling carriers, as can be clearly seen in figure 6.5. Further plots
demonstrate the performance of this technique of random multilevel modulation
under different combinations of modulation depth and pulse number (Fig. 6.6).
The amount of random deviation shown in these simulations (a ± 10 percent

uniform distribution) appears optimal for these five-level converter simulations. The
carrier and sideband harmonic terms are not visible as discrete terms above the
continuous spectra in the five level PWM spectra with 10% deviation. Equally the
switching spectral energy is still in a well defined band which can be filtered by the
load or load filter. The level of the “noise floor” which extends to DC is less than
0.1% for all but the low pulse number, high modulation depth case (Fig. 6.6, 3rd
down) where the sidebands are both high in amplitude and spread in frequency.
The spectra for different degrees of randomness from ± 2% to ± 20% uniform

deviation of the period about its mean value are shown in figure 6.7 for M = 0.9
and N = 9.
The optimum randomisation of the period is the amount which just causes the
uncancelled spread carrier harmonic terms to just touch one another. For a nc + 1
level converter, the first uncancelled carriers will be at frequencies nc wc ± nw1 where
n is odd if nc is even and visa versa. The separation of these terms will thus be 2w1 ,
so the spread bands of energy will just touch one another when their bandwidth
is ±w1 , i.e. 2w1 . The bandwidth of these carrier terms is ±δ ∗ nc wc = 2δnc N w1 .
Thus the optimum uniform deviation δ equals 1/nc N , or in this case 1/(4 ∗ 9) or
approximately ±3%. The amount of randomisation of the period to completely blur
the spectrum is thus generally small and falls with both rising pulse number or
number of levels.
The benefits of multilevel modulation techniques is evident in figure 6.8. When

the modulating signal is small (approaching zero), the uncancelled carrier and side-
band terms of a multilevel converter with an odd number of levels will also approach
0 0
10 10
−1 −1
10 10
−2 −2
10 10
−3 −3
10 10
−4 −4
10 10
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
0 0
10 10
−1 −1
10 10
−2 −2
10 10
−3 −3
10 10
−4 −4
10 10
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
0 0
10 10
−1 −1
10 10
−2 −2
10 10
−3 −3
10 10
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
0 0
10 10
−1 −1
10 10
−2 −2
10 10
−3 −3
10 10
−4 −4
10 10
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
Figure 6.6: The two level (left) and five level (right) spectra for different mod-
ulation depths M and pulse numbers N , with a uniformly distributed random
period deviation of ±10%. From top to bottom,
N = 9 (i.e. fc /f1 =450/50Hz), M = 0.9 and M = 0.2;
N = 1.8 (i.e. fc /f1 =450/250Hz), M = 0.9 and M = 0.2.
0 0
10 10
−1 −1
10 10
−2 −2
10 10
−3 −3
10 10
−4 −4
10 10
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
0 0
10 10
−1 −1
10 10
−2 −2
10 10
−3 −3
10 10
−4 −4
10 10
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
0 0
10 10
−1 −1
10 10
−2 −2
10 10
−3 −3
10 10
−4 −4
10 10
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
0 0
10 10
−1 −1
10 10
−2 −2
10 10
−3 −3
10 10
−4 −4
10 10
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
Figure 6.7: The two level (left) and five level (right) spectra for modulation depth
M = 0.9 and pulse number N = 9 (i.e. fc /f1 =450/50Hz) , for different amounts
of period deviation. The switch periods averaged Tc = 1/fc = 2.22ms, with a
uniformly distributed random deviation of (from top to bottom) ± 2, 5, 10, and
20%.
1 1
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0 0
−0.2 −0.2
−0.4 −0.4
−0.6 −0.6
−0.8 −0.8
−1 −1
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
0 0
10 10
−1 −1
10 10
−2 −2
10 10
−3 −3
10 10
−4 −4
10 10
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
Figure 6.8: The two level (left) and five level (right) spectra for modulation depth
M = 0.01 and pulse number N = 9 (i.e. fc /f1 =450/50Hz), with a uniformly
distributed random deviation of ± 10%. The advantages of a multilevel converter
for very small modulation depths is clear. However the usefulness of random
modulation at these low modulation depths is dubious.
zero. However, for very low modulation depths, the signal to noise ratio of the mod-
ulating signal is compromised by the noise floor of random modulation. Random
modulation techniques are possibly not suitable for applications such as audio am-
plification.
6.1.3 Hardware Generation of Random Modulation
In the previous digital hardware implementation, the carrier triangles were generated
by a counter within the gate array. The carrier frequency is determined by the clock
frequency of this counter, which is generated by one of the DSP’s timers. At the
beginning of each sub-cycle, the gate array’s carrier counter generates an interrupt
to allow the modulation input to be updated synchronously by the DSP. During
this interrupt, the DSP’s timer period can also be updated, changing the PWM
clock frequency, so that the period of each sub-cycle is varied slightly. The clock
frequency remains constant during the sub-cycle (between interrupts), to ensure the
PWM output reflects the input without distortion, as discussed.
These results were again gathered using the Tektronix spectrum analyser. The
analyser performs a 4096 point FFT on the data with no (boxcar) windowing, and
averages eight successive FFTs.
The plots in figure 6.10 show the variation in response to different pulse numbers
and modulation depth. They are consistently lower in amplitude than their simu-
lation counterparts (Fig. 6.6), particularly the low pulse number, high modulation
depth example.
This discrepency is intriguing, and frustrating after such excellent correspon-

dence has been achieved in previous chapters between theory and practice. However,
as discussed in a very recent paper devoted to this very topic, a great deal depends
on the measurement signal processing techniques [39]. This is a research topic in its
own right, and will not be pursued here.
The hardware did show some harmonic distortion of the modulating term, par-
ticularly for large modulation depths. This appears unrelated to the random modu-
lation technique and is most likely due to the low re-sampling ratio of two. Similar
harmonic distortion is evident in figure 5.19, for a re-sampling ratio of two.
The effect of varying the carrier’s randomness is shown in figure 6.9. The largest
collected value of ± 10% appears to be the best choice, in agreement with the
simulations (Fig. 6.7). A larger deviation could not be tried, because the minimum
carrier sub-period (and hence period between interrupts) became shorter than the
required background processing time, causing the DSP to crash.
6.1.4 Flying Capacitor Converter Results
The five level flying capacitor MOSFET inverter was driven by the DSP-Flex con-
troller board, with random modulation signals.
0 0
10 10
−1 −1
10 10
−2 −2
10 10
−3 −3
10 10
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
0 0
10 10
−1 −1
10 10
−2 −2
10 10
−3 −3
10 10
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
0 0
10 10
−1 −1
10 10
−2 −2
10 10
−3 −3
10 10
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
0
10
Figure 6.9: (right column)

Spectra collected from DSP-FLEX
−1
10
hardware, showing the effect of in-
creasing carrier frequency deviation.
Compare these to figure 6.7. Top to
−2
10 bottom, above, ± 2%, ± 5%, and ±
10%. This is with M = 0.9, N = 9
i.e. fc /f1 =450/50Hz.
−3
10
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Figure 6.10: (left column) Spectra of random period multilevel PWM gathered
from the DSP-FLEX hardware, for different pulse numbers N and modulation
depths M . Compare these to figure 6.6. From top to bottom,
N = 9 (i.e. fc /f1 =450/50Hz), M = 0.9 and M = 0.2;
N = 1.8 (i.e. fc /f1 =450/250Hz), M = 0.9 and M = 0.2.
0
10
−1
10
−2
10
−3
10
0 200 400 600 800 1000 1200 1400 1600 1800 2000
0
10
−1
10
−2
10
−3
10
0 200 400 600 800 1000 1200 1400 1600 1800 2000
0
10
−1
10
−2
10
−3
10
0 200 400 600 800 1000 1200 1400 1600 1800 2000
0
10
−1
10
−2
10
−3
10
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Figure 6.11: Voltage and current waveforms (left) and voltage spectra (right)
gathered from one phase leg of the flying capacitor inverter for different modu-
lation depths M and pulse numbers N . The re-sampling ratio was four, and the
random period deviation ±5%. From top to bottom,
N = 9 (ie fc /f1 =450/50Hz), M = 0.83 and M = 0.2;
N = 1.8 (ie fc /f1 =450/250Hz), M = 0.83 and M = 0.2.
6.2. Multilevel Zero Sequence Waveforms 117
The voltage and current waveforms of one phase half bridge are shown for dif-
ferent modulation depths and pulse numbers in figure 6.11. For these tests, the DC
buss voltage was limited to 10V, and a 10Ω + 12mH (10+j4Ω at 50Hz) series RL
load was placed from the phase output to the DC buss midpoint.
The five level flying capacitor half bridge phase leg consisted of eight 60V 25A
rated Nch MOSFETs (ST P25N06) connected in series, each with its own isolated
gate driver [65]. Four 470µF 385V low ESR capacitors served as the three flying
capacitors and the DC bus capacitor. Two 3300µF split the DC bus, and created a
mid-point return for the RL load. A laboratory bench dual supply was used for the
power supply.
It can be seen that the small ripple present on the flying capacitors’ voltages does
not appreciably affect the voltage spectra. The levels of all unexpected harmonics
are below 1% for all cases.
6.2 Multilevel Zero Sequence Waveforms
As explained previously, space vector modulation is a form of uniform sampled

carrier pulse width modulation, generally implemented by microcontrollers. The
state of the three phases and the converter are represented in two dimensions as
vectors, since a three phase system without a neutral connection only has two degrees
of freedom. The voltage common to all three phases can be found at the neutral
point of a balanced star connected load. It is known as the zero sequence component.
By allowing the neutral point voltage to vary, one phase leg can be held contin-
uously high or low for a 60 degree interval while the other two switch. The correct
phase to phase waveforms are still formed. This has two significant advantages.
Firstly, the converter’s full potential modulation depth can be used since the phase
to phase voltages are maximised. Secondly, the switching losses are lowered, since
the average switching frequency falls to two thirds of its original value.
The zero sequence component present in space vector modulation can be anal-
ysed and added to the modulating waveforms in a sine-triangle modulator to gain

similar advantages [28, 29]. If suitable zero sequence space vectors can be identified
for multilevel converters, the simplicity of multilevel modulator implementations
using phase shifted triangular carriers can be retained.
6.2.1 Discontinuous Modulation
For a two level converter, the zero sequence waveform is generated by finding the
phase which lies closest to the minimum or maximum modulation depth. The zero
sequence waveform takes a value which, when added to the phases, forces this phase
to the minimum or maximum modulation depth. Each 60 degrees (for sinewave
modulation), a different phase has the largest magnitude and is forced to the min-
imum or maximum modulation depth; the other phases stepping with it so that
there are no discontinuities in the phase-phase quantities. By holding one phase
at a modulation depth extreme, the maximum modulation depth without introduc-
ing distortion is assured. This technique will work regardless of the shape of the
modulating waveform.
The polarity consistency rule states that a given desired phase output value
should be generated by switching between only the two output levels either side of
that value. Restated for space vector modulation, a desired output vector should be
formed by switching between the nearest three adjacent vectors. A PWM waveform
which switches to a level or vector which is not adjacent is considered sub-optimal.
For a multilevel converter, holding one phase at this extreme value means that
that phase does not switch. The two phase-phase quantities associated with this
phase can then only be two level, and obey the polarity consistency rule. This
is not guaranteed for the third phase-phase quantity since it is the difference of
two two-level PWM waveforms. However in practice, it seems to be generally well
behaved.
The discontinuities in the zero sequence vector waveform introduce large triplen
2
1 1
0.8 0.8 1.5
0.6 0.6
1
0.4 0.4
0.5
0.2 0.2
0 0 0
−0.2 −0.2
−0.5
−0.4 −0.4
−1
−0.6 −0.6
−0.8 −0.8 −1.5
−1 −1
−2
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Figure 6.12: Three phase sinusoidal modulation, M = 0.9, with a zero order
component added to force a duty cycle of 1.0 for 60 degree sectors. Shown are
the three phase waveforms and the zero sequence waveform before (left) and
after (centre) addition. The phase-phase quantities are given by the difference of
the three modulating waveforms (right). It can be seen that the zero sequence
waveform is cancelled.
2 2
1
0.8 1.5 1.5
0.6
1 1
0.4
0.5 0.5
0.2
0 0 0
−0.2
−0.5 −0.5
−0.4
−1 −1
−0.6
−0.8 −1.5 −1.5
−1
−2 −2
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Figure 6.13: The five-level phase neutral PWM waveform (left) appears to show
some poor behaviour, but this is only a reflection of the discontinuities in the
modulating waveform. The phase-phase waveforms (centre and right) all obey
the pulse polarity consistency rule as a result of forcing one phase to remain at a
fixed level at any one time.
An asynchronous random carrier (dev = +- 10%) is used, with pulse number
N = 9. Natural sampling is used.
0 0 0
10 10 10
−1 −1 −1
10 10 10
−2 −2 −2
10 10 10
−3 −3 −3
10 10 10
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
Figure 6.14: The desired fundamental component, as well as the harmonics due
to the triplen waveform are prominent in the frequency spectrum of the five-
level phase neutral PWM waveform (centre). The triplen frequency components
are not present in the phase-phase waveform as expected (right). The two-level
spectrum is shown (left) for comparison.
spectral components in the phase-earth waveforms. These high dV/dt transients

stress the electrical insulation of attached transformers or motors, cause large tran-
sient currents to flow in the converter, and generate significant EMI. It is possible
and desirable in a multilevel converter to shift the maximal phase to the nearest
level which does not cause that phase to switch, rather than simply to an extreme
level, provided of course that this does not lead to either of the other two phases
exceeding the extreme level.
For a five-level converter, there are five such levels — +E, +E/2, 0, -E/2, -E.
The choices of level to hold at for sinusoidal modulation which minimise the step
discontinuities are:
M Action Comments
1.1547 2 tan 30 Force to +E, -E Maximum modulation depth
continuous zero seq waveform
0.8660 cos 30 Force to +E,-E/2 or +E/2,-E continuous zero seq waveform
0.7215 swap over point discontinuity in zero seq equal
0.5774 tan 30 Force to +E/2,-E/2 or equiv. continuous zero seq waveform
0.4330 cos 30/2 swap over point discontinuity in zero seq equal
0.2887 cos 30/3 Force to +E/2,0 or 0,-E/2 continuous zero seq waveform
0.1443 cos 30/4 swap over point discontinuity in zero seq equal
0.0 Force to 0 continuous zero seq waveform
Note that there is no swap over point between 1.15 and 0.866 — to swap before
reaching 0.866 would force the duty cycle of one of the other phases to exceed one.
An example of the three possible zero sequence vectors for a modulation depth
of M = 0.8 are shown in figure 6.15. For the modulation depth M = 0.8 for a
five level converter, it is possible to force the phase output to the extreme levels
E, −E (left), the midpoints E/2, −E/2 (centre), or a combination E/2, −E (right).
The combination E/2, −E produces the least discontinuities in the phase-neutral
waveforms, and so the least distortion in the phase-phase waveforms.
Five equally spaced levels are assumed for this analysis. Equally spaced lev-
els leads to equal voltage sharing between switches in most converter structures.
Switching instants can be evenly and naturally distributed using phase shifted car-
rier techniques such as those presented, since all phase leg voltage steps will be
equal. It is possible to have five levels which are not equally spaced. This would be
an unusual case. It would generally require the use of a space vector or otherwise
intellegent controller.
6.2.2 Adding a Third Harmonic
Another straight forward method of increasing the possible modulation depth of a

three phase converter is to add some third harmonic to the single phase sinusoidal
modulating waveforms. With the correct phase relationship, this flattens the crests
of the sine waves, allowing a greater modulation index. By adding third and ninth
harmonics (i.e. a continuous triplen waveform), it is possible to arrive at the same
waveform as space vector modulation at maximum modulation, and extend the
modulation index without distortion to 1.15 (Figs. 6.16, 6.17, & 6.18).
A continuous zero sequence waveform places less stress on the converter and
load and causes less high frequency electrical interference. This continuous triplen
component can either be maintained at a constant amplitude or reduced along with
the modulating waveform. Both techniques are assessed here.
6.2.3 Pulse Centring Algorithms
A triplen waveform such as this can only be generated for a known sinewave modu-
lating signal. When the modulating signal is a complex signal, such as as found in
an active filter or a converter with closed loop control, a different real-time approach
is required. One successful approach is to “centre” the three phase switching tran-
sitions in the switch sub-period. Centring the pulses in this way not only ensures
the maximum possible modulation depth of the converter is achievable, but it also
results in superior harmonic performance of the converter [28].
Centring is achieved by finding the average of the most positive and most neg-
1 1 1
0.8 0.8 0.8
0.6 0.6 0.6
0.4 0.4 0.4
0.2 0.2 0.2
0 0 0
−0.2 −0.2 −0.2
−0.4 −0.4 −0.4
−0.6 −0.6 −0.6
−0.8 −0.8 −0.8
−1 −1 −1
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
1 1 1
0.8 0.8 0.8
0.6 0.6 0.6
0.4 0.4 0.4
0.2 0.2 0.2
0 0 0
−0.2 −0.2 −0.2
−0.4 −0.4 −0.4
−0.6 −0.6 −0.6
−0.8 −0.8 −0.8
−1 −1 −1
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
1 1 1
0.8 0.8 0.8
0.6 0.6 0.6
0.4 0.4 0.4
0.2 0.2 0.2
0 0 0
−0.2 −0.2 −0.2
−0.4 −0.4 −0.4
−0.6 −0.6 −0.6
−0.8 −0.8 −0.8
−1 −1 −1
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
1.5 1.5 1.5
1 1 1
0.5 0.5 0.5
0 0 0
−0.5 −0.5 −0.5
−1 −1 −1
−1.5 −1.5 −1.5

0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
0 0 0
10 10 10
−1 −1 −1
10 10 10
−2 −2 −2
10 10 10
−3 −3 −3
10 10 10
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
0 0 0
10 10 10
−1 −1 −1
10 10 10
−2 −2 −2
10 10 10
−3 −3 −3
10 10 10
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
Figure 6.15: Three possible zero sequence waveforms for the modulation depth
M = 0.8. From the top, the modulating signals and zero sequence vector, the
modulating signals after the addition of the zero sequence vector, the phase neu-
tral waveforms, the phase phase waveforms, the spectra of the phase neutral, and
phase phase waveforms.
1 1
1.5
0.8 0.8
0.6 0.6 1
0.4 0.4
0.5
0.2 0.2
0 0 0
−0.2 −0.2
−0.5
−0.4 −0.4
−0.6 −0.6 −1
−0.8 −0.8
−1.5
−1 −1
−2
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Figure 6.16: The maximum possible distortionless three phase modulation depth,
M = 1.15, achieved by the addition of a zero order component to force a duty cy-
cle of 1.0 for 60 degree sectors. The three phase waveforms and the zero sequence
waveforms are shown before (left) and after (centre) addition. The phase-phase
quantities are given by the difference of the three modulating waveforms (right).
It can be seen that the zero sequence waveform is cancelled.
2 2
1
0.8 1.5 1.5
0.6
1 1
0.4
0.5 0.5
0.2
0 0 0
−0.2
−0.5 −0.5
−0.4
−1 −1
−0.6
−0.8 −1.5 −1.5
−1
−2 −2
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Figure 6.17: The phase neutral PWM waveform (left) and the phase-phase wave-
forms (centre and right) for M = 1.15, N = 9. Natural sampling and random
modulation (uniform distribution, deviation of +- 10%) are used for this five level
example.
0 0 0
10 10 10
−1 −1 −1
10 10 10
−2 −2 −2
10 10 10
−3 −3 −3
10 10 10
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
Figure 6.18: The desired fundamental component, as well as the harmonics due
to the triplen waveform are prominent in the frequency spectrum of the five-
level phase neutral PWM waveform (left). The triplen frequency components
are not present in the phase-phase waveform as expected (centre). The two-level
spectrum is shown (right) for comparison.
ative phase and using this signal as the zero sequence vector. When subtracted
from all three phases, it ensures the two outer phases are an equal distance from
the maximum possible modulation depth; or put another way, that the first and last
phase switch transitions are equal times from the beginning and end of the switch
cycle. This is easily done in software for a space vector modulator [15]. It has also
been successfully implemented in analog hardware [28].
6.2.4 Assessment by Distortion Analysis
To determine the relative merits of each of these techniques, a measure of spectral

performance is required. Total harmonic distortion (THD) is a measure of the
closeness in shape of a waveform to its fundamental component. It is defined as:

1 n
THD = Vi2
V1 i=2
All harmonics contribute equally to the THD figure regardless of their frequency.
A fairer measure would take into account the frequency of the harmonic as well as
amplitude, since many power system converters are connected via an LC filter or a
similar filter network to the power network. The Distortion Factor (DF) is a measure
of the harmonic distortion which remains after the harmonics have been subjected
to a second-order low-pass attenuation [58].

2
1 n
Vi
DF =
V1 i=2 i2
A third figure called Weighted Total Harmonic Distortion (weighted THD) is

proposed by Holmes [28]. This figure is a relative measure of the RMS current ripple
into an inductive load (first order attenuation) whose frequency breakpoint is at the
fundamental frequency.

2
1 n
Vi
THD(weighted) =
V1 i=2 i
Weighted THD is used in this chapter for the analysis and comparison of spectral
performance of the different modulation techniques.
All of these formulae have been written with synchronous modulation in mind,
where all harmonics are multiples of the modulating term. For asynchronous or
random modulation, where this is not the case, the definition of weighted THD is
extended by using a continuous integral in place of the discrete summation.

2
1 f <f1 f =∞
f1
THD(weighted) = (Vi )2 + V1
V1 f =0 f >f1 f
In practice, the calculated voltage spectra is discrete, as it is the result of an

FFT routine. The two integral terms become the sum of the squares of the frequency
bins, excluding the f1 bin, and scaled if beyond the f1 bin. Another difference in
practice is the finite upper frequency of the summation. This contributes very little
error as the terms diminish in proportion to the square of their frequency, 1/f 2 .
This is due in part to the inductive filtering (|Vi | ∝ 1/f ) and in part to the nature
of the carrier spectra being similar to the terms of a square wave (|Vi | ∝ 1/f ).
To demonstrate this, the FFT of a square-wave voltage waveform and the result-
ing weighted THD for different numbers of FFT bins is tabulated below. Inclusion
of the first 15 harmonics (not including f1 , so f3 to f31 ) gave less than one percent
error. An accurate value of 12.1153 % was calculated with a 65536 point FFT.
no. of FFT points no. of harmonics calc’ed WTHD % % error in calc

8 1 13.8071 13.9644
16 3 12.9269 6.6992
32 7 12.3655 2.0650
64 15 12.1832 0.5604
128 31 12.1329 0.1452
256 63 12.1198 0.0369
512 127 12.1164 0.0093
For the simulations, f1 = 50 Hz and fc = 450 Hz (N = 9). Ten fundamental

cycles are calculated giving 5 Hz bins after the FFT. The highest frequency bin is
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
0 0.2 0.4 0.6 0.8 1
Figure 6.19: Plots of weighted total harmonic distortion plotted against modu-
lation depth M , for different zero sequence waveforms. Four different cases are
shown:
– discontinuous modulation with five or three phase neutral levels (· · · ◦ · · ·),
– discontinuous modulation with four or two phase neutral levels (· · · ∗ · · ·),
– a continuous triplen component which allows maximum modulation depth and
which varies with M along with the sines (− ◦ − ),
– or remains fixed regardless of M (− ∗ − ).
The case of no zero sequence component is shown for comparison (solid).
57.6kHz, over 1000 times f1 , so there will be negligible error in the calculation of
the weighted THD. Random modulation with ±10% uniform carrier variation has
again been used. Natural sampling is used to ensure the modulation process itself
adds no additional distortion.
Referring to figure 6.19, the general trend for all plots is very similar. The
power of the carrier and sideband components remains relatively constant. Hence
the lowest distortion levels occur at high modulation depths, where the ratio of the
fundamental component to carrier and sideband components is largest.
The lowest overall average distortion is achieved with no zero sequence compo-
nent at all (Fig. 6.19, solid line). The other techniques do have features that may
make their implementation worthwhile despite their somewhat higher distortion.
All techniques show a minimum around M = 0.6 for this simulated five level
converter. At M = 0.5, the phase neutral PWM waveform will be a three level
waveform with the crests of the waveforms at the midpoint voltage levels of ±E/2.
The ripple current in an inductive load (and hence weighted THD) will be minimised
around this level [48].
The discontinuous zero sequence waveforms which form four and two level phase
neutral waveforms (Fig. 6.19, · · ·∗· · ·, Fig. 6.15, right column) will similarly produce
minima around M = 0.3 and M = 0.9 where the two and four level waveforms
respectively are near their relative maximum duty cycle, and hence producing the
minimum ripple.
A discontinuous technique can lower switching losses since the switches in each
phase leg need not switch for 120 degrees of each 360 degree cycle. However many
multilevel topologies cannot take advantage of this, the main feature of discontinuous
modulation, as they rely on continual modulation of all switches to maintain the
correct internal state of the converter. For example, the voltage balance on the
flying capacitors of the flying capacitor converter is inherently maintained by the
constant switching of the devices in each leg.
The use of a continuous triplen zero sequence vector component (Figs. 6.16 –
6.18), whether constant or varying in amplitude as M varies, leads to essentially
the same level of distortion at moderate modulation depths (Fig. 6.19, −−). They
extend the useful upper modulation range from M = 1.0 to M = 1.15, since plain
sinusoidal modulation begins to clip and distort beyond M = 1.0.
Also unexpectedly, the addition of a constant triplen component at small mod-

ulation depths M < 0.2 produces the lowest distortion of any technique (Fig. 6.19,
− ∗ −).
6.3 Conclusions
Random modulation and the addition of a three phase zero sequence vector are
two extensions of carrier modulation which have been already demonstrated for two
level modulation. This chapter has shown that both techniques can be extended to
multilevel modulation, and are equally applicable to space vector modulation.
Multilevel random modulation is particularly successful. For a multilevel mod-

ulator where lower order carrier and sidebands are cancelled, only a small random
deviation of the period is required to completely spread the carrier and sideband
terms, since their spacing is relatively close. If the correct method is used, the
modulating term and cancelled carriers and sidebands remain unaffected and no
sub-harmonics are produced.
The addition of common zero sequence waveforms to three phase modulating

waveforms extends the maximum modulation depth to M = 1.15, as it does for
two level converters. There does not appear to be any advantageous reduction
in switching distortion however. Nor is the advantage of discontinuous switching
always a possibility, since some multilevel converter topologies rely on the continuous
switching to maintain internal converter states in equilibrium.
The extra complexity of implementing these additional variations on carrier

PWM will be justified by their advantages. For example in a variable speed motor
drive inverter, random modulation techniques can lower the generation of acoustic
noise, reduce EMI problems, and lessen the troublesome excitation of system reso-
nances. Zero sequence three phase modulation ensures maximum utilisation of the
inverter and may allow a reduction in switching losses.
Chapter 7
Conclusion
7.1 Multilevel Converter Topologies
Multilevel converter structures have been known for many years, although perhaps
not by that name. They were implemented using the series and parallel connection
of individual bridges by way of multiple secondary transformers and interphase reac-
tors [70]. The first modern multilevel converter was the neutral point clamped con-
verter, introduced in the early 1980s [51]. This topology created significant research
interest, particularly in the fields of traction and static power system converters. It
remains the most immediately identified multilevel converter. This decade, other
new multilevel converters topologies have been presented, such as the flying capac-
itor or imbricated cells converter [45, 46] and the cascaded inverters with separate
DC sources [56, 25].
Each of these different multilevel converter topologies has its own mixture of
advantages and disadvantages. For any one particular application, one topology
will be more appropriate than the others. Often topologies are chosen based on
historical precedent, or the designer’s preference, even if that topology may not be
the best choice for the application. A summary of the structure and operation of
each of these different multilevel topologies is given in chapter two, along with their
advantages and disadvantages.
130 Chapter 7. Conclusion
Usually the modulation strategy for each of these converters was developed in
conjunction with or subsequently to the converter. For some structures — most
notably neutral point clamped — not all switch states are allowed. The modulation
for the converter is treated as a whole, usually using space vector modulation. Other
techniques such as hysteretic or sine-triangle cannot be easily applied.
Despite the diversity, these different topologies contain common underlying links.
Usually the modulation and, to a lesser extent, control strategies can be developed
independently of the converter’s topology and then subsequently applied with little
or no modification.
In light of this, the simplest case of the transformer connected multi-bridge con-
verter was used as the implied default multilevel converter topology for the purposes
of developing good multilevel modulation and control techniques.
7.2 Pulse Width Modulation Techniques
The multilevel PWM waveform, regardless of method of generation, can effectively

be considered as the summation of individual two level PWM waveforms. If these
two level waveforms are appropriately phased, the amplitude of the voltage steps
and hence the amplitude of the harmonic switching frequency terms are reduced in
proportion to the number of switch pairs per phase, that is, the number of two level
waveforms. The output PWM waveform also switches at an aggregate value which
is the sum of the individual two-level switch pair switch frequencies. This places the
spectral terms associated with the carrier and sidebands at a multiple of the switch
frequency as well.
All of the well know modulation techniques for power converters such as se-
lective harmonic elimination, hysteretic and carrier based PWM modulation have
been extended to multilevel modulation. Of these different modulation techniques,
the focus was placed on carrier based PWM techniques and their application to
multilevel converters. This is because carrier based PWM
7.3. Natural and Uniform Sampled Carrier PWM 131
• is easily implemented using analog or digital circuitry, or software techniques.
• is easily extended to all multilevel converter topologies.
• shows good performance at moderate switch frequencies.
• has good dynamic performance, suitable for closed loop control.
The understanding of the application of carrier based modulation to multilevel con-

verters leads easily to an understanding of the requirements for and problems of
multilevel modulation using other techniques.
7.3 Natural and Uniform Sampled Carrier PWM
Multilevel converters place new demands on these techniques. Since carrier and
sideband groups and their multiples associated with the switch frequency can be
cancelled and removed from the modulation spectrum, a low switching frequency
can be chosen without compromising the output waveform quality. The multiple
switch edges due to the many switch pairs still promise a potentially wide modulator
bandwidth.
To ensure every switching edge influences the output with a minimum delay,
triangular carrier (double edge) asymmetric uniformly sampled or naturally sampled
PWM are the best choices. Digital or software modulator implementations are by
nature uniformly sampled. The accuracy of placement of the switch edges by a
digital implementation ensures an exact phase relationship between the switch pair
signals. This results in excellent carrier cancellation in the output spectrum.
However a low switch frequency leads to a small pulse number N , the ratio of
switch frequency to modulating frequency fc /f1 . Under these conditions, uniform
sampling exhibits the problems of modulating input signal attenuation, phase lag
and significant odd harmonic distortion. Multiple modulator (multilevel) converters
cannot hide these problems.
Naturally sampled PWM does not attenuate the synthesised fundamental, nor
generate any distortion products of the fundamental. A naturally sampled modula-
tor does not affect the gain or phase response of the converter. Hence the converter
may be modelled and controlled as a linear amplifier. The passive output filter can
still of course have a significant effect on the closed loop response. The control loop
must often include knowledge of the filter states for stability.
7.4 Digital Natural — Re-sampled Uniform
In practice, since natural PWM is normally implemented using analog techniques,

as the number of levels (switch pairs) increases, the variation between the analog
generated carriers makes it increasingly difficult to achieve good carrier cancellation.
A digital implementation of natural sampling is needed.
Re-sampled uniform PWM is a digital implementation which approaches the

frequency and transient response of natural PWM. Instead of sampling only once
per switching edge at the beginning of the PWM switch period, further samples are
taken during the switch period. The position of the switch edge is determined by
the most recent sample. This achieves the desired result, but some complications
such as the possibilities of missed or multiple edges must be considered.
The Re-Sampling Ratio, rsr = fs /2fc is a measure of the rate of re-sampling;

only integer values ensure a sample is taken at the beginning of each switch period.
Simulations and results gathered from both hardware and software implementations
are compared for a number of resampling ratios. Moderate values of the re-sampling
ratio (4,8) make a significant improvement in the frequency response, delay and
distortion of the modulator, particularly for high modulation depths.
The software re-sampled multilevel modulator was implemented for an Intel

80C196 microcontroller. Most microcontroller timer peripherals hinder the imple-
mentation of re-sampled uniform, and only low re-sampling ratios are possible before
the software overheads become overwhelming. The first hardware modulator was
7.5. Random Modulation for Multilevel Converters 133
based on simple synchronous counters and EPROM lookup tables to implement a

combinatorial digital comparison. This solution is simple yet powerful and also lends
itself to many modulation variations which would be very difficult to implement us-
ing other techniques. The final hardware modulator was implemented entirely within
a large field programmable gate array (FPGA). This solution had accordingly high
resolution (because of the FPGA’s high speed) and high integration, and would be
suitable for commercial applications.
7.5 Random Modulation for Multilevel Convert-
ers
A carrier PWM technique can have its carrier frequency randomly perturbed about a
nominal switch frequency without disturbing the desired linear input output transfer
function. This moves the switching energy from discrete spectral lines and spreads it
into a continuous band of frequencies. This reduces the production of tonal acoustic
noise and reduces the problems of exciting electrical or mechanical resonances.
To extend this technique to multiple phase shifted carriers which are used to
form the multilevel waveform requires the carriers to all have equal random sub-
periods. Here a sub-period is defined as the period of one multilevel switch edge,
a submultiple of the two level PWM period. This ensures complete cancellation of
the lowest carrier and sideband spectral terms as before.
The techniques were again tested using simulations and confirmed in practice
with the FPGA re-sampled modulator. Only a relatively small period perturba-
tion is required to effectively spread the discrete spectral lines of the carrier and
sideband terms that remain, since this perturbation is large in comparison with the
frequency separation of these terms. For this small perturbation, sub-harmonics are
not generated, other than a very low level noise floor which exists from DC to the
first uncancelled sidebands.
7.6 Three Phase Zero Vector Experiments
The benefits of the addition of a common mode “zero sequence vector” to the three
phase modulating waveforms was also assessed using simulations. The phase to
phase PWM waveform of a multilevel three phase converter switches between three
levels at any one instant rather than only two, since it is the difference of two two-
level phase neutral PWM waveforms at that moment. This was suggested to be
suboptimal according to the polarity consistency rule.
A measure of distortion called weighted total harmonic distortion (WTHD) was

used to assess the relative merits of simple sinewave modulation compared to mod-
ulation using discontinuous waveforms and waveforms with triplen harmonics. Both
of these new modulating waveforms extended the maximum possible modulation
depth M before clipping to 1.15. But neither significantly altered the distortion
levels of the multilevel waveforms. The addition of a constant continuous triplen
waveform (regardless of modulation depth) produced the best results for the whole
extended modulation range.
In a two level converter, a discontinuous switching strategy has the advantage of

lowering converter switching losses by one third. However, many multilevel topolo-
gies cannot take advantage of the opportunity to cease switching for a period, as
they rely on continual cycling of the switches to maintain the balance of the internal
converter states.
7.7 Future Research
This thesis has concentrated on the theory of Pulse Width Modulation as applied
to multilevel converters. Evaluation of theories were carried out using simulations
and verified with analog, digital or microcontroller based modulator circuits. The
PWM control signals were analysed before their application to a power converter,
so the effects of finite power switch saturation, switching delay, and slew rate were
7.7. Future Research 135
not measured. Initial simulations showed that these effects should under normal cir-
cumstances, cause negligible distortion. An assessment of the importance of these
effects and the success of any countermeasures on the discussed multilevel modula-
tion techniques would be worthwhile.
Having evaluated the performance of the modulators in complete systems op-

erating open loop, the performance using closed loop feedback should be assessed.
Two suitable interesting applications would be a wide bandwidth three phase active
power filter and a multilevel class D (PWM) audio amplifier.
One further area of multilevel modulation which remains largely unexplored, is

the generic extention of Selective Harmonic Elimination / Minimisation to multilevel
modulation. SHE/SHM is increasingly limited in application, so this study would
be mostly for academic completeness.
Appendix A
Spectral Analysis
A.1 The Fourier Series
Assume that a waveform f (θ) is repetative or periodic over the interval 2π, so that
f (θ + 2π) = f (θ), and is defined between the values of −π and π. This waveform
can be written as the sum of a number of orthogonal sine and cosine components.
This series expansion is called the Fourier Series [36, 20].
∞

1
f (θ) = a0 + (an cos nθ + bn sin nθ) (A.1)
2 0
The Fourier coefficients an and bn can be calculated using
1π
an = f (θ) cos nθ dθ (n ≥ 0) (A.2)
π −π
1π
bn = f (θ) sin nθ dθ (n ≥ 1) (A.3)
π −π
The Fourier series and coefficients can alternatively be written

∞

f (θ) = cn ejnθ (A.4)
−∞
1 2π
cn = f (θ)ejnθ dθ (A.5)
2π 0
138 Appendix A. Spectral Analysis
0 kπ π 2π ωt
0 kπ π 2π ωt
Figure A.1: Natural sampled pulse width modulation, of pulse or carrier fre-
quency ω, shown for constant DC modulation k, 0 ≤ k ≤ 1 (top), and a fixed,
sinusoidal modulation k = 1/2 + M/2 sin(ω1 t) (bottom).
These two series are related by Euler’s equation,
ejθ = cos θ + j sin θ (A.6)

1 jθ
cos θ = (e + e−jθ ) (A.7)
2
1 jθ
sin θ = (e − e−jθ ) (A.8)
2j
and their coefficients are similarly related,
1
c0 = a0 ,
2
1
cn = (an − jbn )
2
1
c−n = (an + jbn ) n = 1, 2, 3, . . . (A.9)
2
a0 = 2c0 ,
an = cn + c−n
bn = j(cn + c−n ) n = 1, 2, 3, . . . (A.10)
A.2 Fourier analysis of double edge pulse width

modulation
A.2.1 Constant (dc) modulation
Consider the double edge modulated naturally sampled PWM waveform with fixed
pulse width as shown in the top of figure A.1. The waveform steps between 0 and
1 in amplitude. The pulses are 2π periodic, with a rising edge at −kπ and a falling
A.2. Fourier analysis of double edge pulse width modulation 139
edge at kπ. The Fourier coefficients calculated below are for a more general case,
for a pulse 2kπ wide centred about a phase shift of φ radians.
1π
an = f (θ) cos nθ dθ (n ≥ 0)
π −π
1 kπ+φ
= 1 cos nθ dθ
π −kπ+φ
kπ+φ
1 1
= sin nθ
π n −kπ+φ
1
= (sin n(kπ + φ) − sin n(−kπ + φ))
nπ
2
= sin nk cos nφ (A.11)
nπ
Similarly,
2
bn = − sin nk sin nφ (A.12)
nπ
Hence
1
cn = (an − jbn )
2
1
= sin nk ejnφ (A.13)
nπ
∞
1
f (ωt) = sin nk ejnφ ejnωt (A.14)
n=−∞ nπ
A.2.2 Naturally sampled Sinusoidal modulation PWM
Now assume that the width of the pulses is no longer constanst, but is allowed to
vary. The variable k becomes a function of time, k = k + M/2 sin(ω1 t + φ1 ). The
constant M is the modulation depth, and varies between 0 and 1.
1 π
cm = f (θ)e−jmθ dθ (n ≥ 0)
2π −π
1 k π+φc
= 1 e−jmθ dθ (A.15)
2π −k π+φc
c
k π+φ
1 1 −jmθ
= − e
2π jm −k π+φc
j

= ejmk π − e−jmk π ejmφc (A.16)
2mπ
but
k = k + M/2 sin(ω1 t + φ1 ) (A.17)
hence
j
cm = ejmkπ+jmM π/2 sin(ω1 t+φ1 ) − e−jmkπ−jmM π/2 sin(ω1 t+φ1 ) ejmφc
2mπ
j
= ejmkπ ejmM π/2 sin(ω1 t+φ1 ) − e−jmkπ e−jmM π/2 sin(ω1 t+φ1 ) ejmφc
2mπ ∞

j
= ejmφc ejmkπ Jn (mM π/2) ejn(ω1 t+φ1 )
2mπ n=−∞
∞

−jmkπ −jn(ω1 t+φ1 )
−e Jn (mM π/2) e (A.18)
n=−∞
where the following specific generating function of the Bessel function Jn (x) is sub-
stitued, [20]
∞

jx sin θ
e = Jn (x) ejnθ (A.19)
n=−∞
We substitute n = −n in the second summation.

∞
j
cm = ejmφc Jn (mM π/2) ejn(ω1 t+φ1 ) ejmkπ
2mπ n=−∞
∞

jn(ω1 t+φ1 ) −jmkπ
− J−n (mM π/2) e e
n=−∞
∞
j
= ejmφc Jn (mM π/2) ejn(ω1 t+φ1 ) ejmkπ
2mπ n=−∞
∞

− (−1)n Jn (mM π/2) ejn(ω1 t+φ1 ) e−jmkπ
n=−∞
j ∞
= ejmφc Jn (mM π/2) ejn(ω1 t+φ1 ) ejmkπ − (−1)n e−jmkπ (A.20)
2mπ n=−∞
∞
j
= ejmφc Jn (mM π/2) ejn(ω1 t+φ1 ) e−jnπ/2
2mπ n=−∞

× ejmkπ ejnπ/2 − e−jnπ/2 e−jmkπ
A.2. Fourier analysis of double edge pulse width modulation 141
∞

= Jn (mM π/2)/(mπ) ejn(ω1 t+φ1 ) e−jnπ/2 ejmφc
n=−∞

× − 1/2j ej(mk+n/2)π − e−j(mk+n/2)π
∞

= −Jn (mM π/2)/(mπ) ejn(ω1 t+φ1 ) e−jnπ/2 ejmφc sin(mk + n/2)π
n=−∞
∞
= − sin(mk + n/2)π Jn (mM π/2)/(mπ) ej(mφc −nπ/2) ejn(ω1 t+φ1 )
n=−∞
(A.21)
Substituting the coefficients cm into the Fourier Series

∞
∞
Jn (mM π/2) −jnπ/2 jn(ω1 t+φ1 ) jm(ωc t+φc )
f (t) = − sin((2mk + n)π/2) e e e
m=−∞ n=−∞ mπ
(A.22)
If k = 12 , then this simplifies to
∞
∞
Jn (mM π/2) −jnπ/2 jn(ω1 t+φ1 ) jm(ωc t+φc )
f (t) = − sin((m + n)π/2) e e e
m=−∞ n=−∞ mπ
∞
∞
Jn (mM π/2) j(mφc +nφ1 −nπ/2) j(mωc +nω1 )t
= − sin((m + n)π/2) e e
m=−∞ n=−∞ mπ
(A.23)
Note that this result is for a modulating Sine wave. If a cosine wave is used
instead, the equation matches up with that derived by Wood.
k = k + M/2 cos(ω1 t + φ1 ) (A.24)

= k + M/2 sin(π/2 − ω1 t − φ1 )
φ1 = π/2 − φ1
ω1 = −ω1
∞
∞
Jn (mM π/2) j(mφc +nφ1 ) j(mωc +nω1 )t
f (t) = sin((m + n)π/2) e e
m=−∞ n=−∞ mπ
(A.25)
A.2.3 Uniformly sampled Sinusoidal modulation PWM
Using similar techniques to those above, the Fourier series description of Uniformly
sampled PWM is
∞
∞
Jn ((m + nω1 /ωc )M π/2)
f (t) = sin((m + n)π/2)
m=−∞ n=−∞ (m + nω1 /ωc )π
× ej(mφc +nφ1 +(nω1 /ωc )π/2) ej(mωc +nω1 )t (A.26)
A.3 Jump Function Fourier Analysis

Jump function Fourier analysis is a method of calculating the Fourier components
(i.e. the frequency spectra) of a known periodic waveform. It has the advantages
over other techniques such as the Fast Fourier Transform (FFT) of giving an exact
answer for an arbitrary number / choice of frequency terms using a minimal number
of calculations.
The analysis requires that the waveform can be expressed as the summation of a
number of step or jump functions. This is a natural fit for Pulse Width Modulation
(or any form of pulse modulation for that matter), where each switching edge can be
represented as a step function of a given amplitude, at a given time. It assumes that
the waveform to be analysed is periodic over all time, past and future. This period
is the lowest common multiple of all the periodic components present, which for syn-
chronous modulation, is the modulating period. Rather than the regularly sampled
amplitude vector required by a FFT, jump function analysis uses the shorter, exact
description of a vector of step time / step amplitude pairs.
Assume that a continuous waveform is repetitive over 2π:
A2 A2
A1 δ2 A1
Ak-1
A0 δ1 A0 δ1
δk
0 θ1 θ2 θ3 θk 2π θ1 θ2 θ3
The Fourier series of this continuously defined waveform is:

∞

f (θ) = cn ejnθ (A.27)
−∞
1 2π
cn = f (θ)e−jnθ dθ (A.28)
2π 0
A.3. Jump Function Fourier Analysis 143
Finding the complex Fourier coefficient cn for the general waveform above:
1 θ1 1 θ2 1 0
cn = A0 e−jnθ dθ + A1 e−jnθ dθ + . . . + A0 e−jnθ dθ
2π 0 2π θ1 2π θk
−1
= (A0 e−jnθ1 − A0 e−jn0 + A1 e−jnθ2 − A1 e−jnθ1 + . . . + A0 e−jn0 − A0 e−jnθk )
j2nπ
j
= ((A0 − A1 )ejnθ1 + (A1 − A2 )ejnθ2 + . . . + (Ak−1 − A0 )ejnθk )
2nπ
−j
= ((A1 − A0 )ejnθ1 + (A2 − A1 )ejnθ2 + . . . + (A0 − Ak−1 )ejnθk )
2nπ
The jump functions are defined as δ1 = (A1 − A0 ) etc. Therefore rewriting:
j
cn = (δ1 e−jnθ1 + δ2 e−jnθ2 + . . . + δk e−jnθk ) (A.29)
2nπ
−j
= ((δ1 cos nθ1 + δ2 cos nθ2 + . . . + δk cos nθk )
2nπ
+j(δ1 sin nθ1 + δ2 sin nθ2 + . . . + δk sin nθk )) (A.30)
−j
= (δ1 cos nθ1 + δ2 cos nθ2 + . . . + δk cos nθk )
2nπ
1
+ (δ1 sin nθ1 + δ2 sin nθ2 + . . . + δk sin nθk ) (A.31)
2nπ
But cn = 1/2(an − jbn )
1
an = (δ1 sin nθ1 + δ2 sin nθ2 + . . . + δk sin nθk ) (A.32)
nπ
1
bn = (δ1 cos nθ1 + δ2 cos nθ2 + . . . + δk cos nθk ) (A.33)
nπ
For example, taking the square wave shown below:

A1
δ1 = +1 δ2 = −1
A2
θ1 = 0 θ2 = π 2π
The amplitudes of the first three cos harmonics are zero. This is expected since the
given square wave function is odd (h(t) = −h(−t)), and so is composed of only sine
terms.
1 1
a1 = (1 sin 0 + (−1) sin π) = (0 + 0) = 0
π π
1 1
a2 = (1 sin 0 + (−1) sin 2π) = (0 + 0) = 0
2π 2π
1 1
a3 = (1 sin 0 + (−1) sin 3π) = (0 + 0) = 0
3π 3π
The amplitudes of the first three sin harmonics are:
1 1 2
b1 = (1 cos 0 + (−1) cos π) = (1 + 1) =
π π π
1 1
b2 = (1 cos 0 + (−1) cos 2π) = (1 − 1) = 0
2π 2π
1 1 2
b3 = (1 cos 0 + (−1) cos 3π) = (1 + 1) =
3π 3π 3π
Appendix B
Matlab Scripts and C Code
B.1 Matlab Scripts
B.1.1 Jump function analysis code
These first four scripts are examples of the code used to perform the jump function
frequency analysis of the separately generated PWM waveforms. t2f.m performs
the actual time to frequency transformation; tplot.m and frplot.m plotted the
time and frequency vectors for checking and subsequent printing, and initt2f.m
created some necessary constants for the above files to run.
The steps (δ1 , δ2 , . . . , δk ) and angles (θ1 , θ2 , . . . , θk ) are two vectors of arbitrary
but equal length k. Since the data input will invariably be edge times rather than
angles, and the expected output will be frequency components rather than harmonic
numbers, the angles are replaced with times by using the relationship θ = ωr t. In
hindsight, this translation between angles and times, frequencies and harmonic num-
bers should have be kept separate from the jump function processing and plotting.
The frequency of periodicity, which will also be the frequency of the first (or
fundamental) harmonic is called fres , since this frequency is also the separation, or
resolution, of the harmonic terms which make up the discrete spectra.
It is quite permissible to generate multiple periods of times and edges. This will
generate multiple spectral ‘bins’, but many will be zero. If the times and edges are
not periodic over the period used, then this technique will generate ‘leakage’ errors
in the same way as a conventional Discrete Fourier Transform (DFT) calculation
would. The main value of the Jump function technique is the ability to generate the
exact spectra using the minimum calculations, if the stepped waveform’s period is
known.
145
146 Appendix B. Matlab Scripts and C Code
t2f.m
% t2f.m - takes two vectors of arbitrary but equal length:
% tlst - a vector of edge times
% ylst - a vector of edge steps (jumps)
% and generates:
% cn - a complex vector, length equal to vector n.
% abs(cn) - gives the magnitude and
% angle(cn) - gives the phase. (see fplot.m)
%
% run initt2f.m first (once) to define n, iwr, Ai_pi
csum = ylst * (exp((iwr.*tlst)’*n));

cn = Ai_pi ./ n .* csum;
cn = cn ./ 4;
% cn_mag = abs(cn); cn_ph = angle(cn);
initt2f.m
% initt2f.m - initialises the constants needed by t2f.m
% Needs to be run once at beginning of session, or after a clear,
% or to change fres or ftop.
fres = 25; % sets the freq resolution - freq bins @ multiples

ftop = 2000; % sets top freq bin.
A = 2;
ntop = round(ftop/fres); % number of freq bins

n = 1:1:ntop; % vector of freq bins for calcs
fbins = fres * n; % vector of freq bins for plots
wr = 2*pi*fres;
iwr = i * wr;
Ai_pi = A*i/pi;
tplot.m
% tplot.m Takes the tlst and ylst from hdn.m and does a time plot
% of them so I can see if they are really PWM
%
% First it converts the delta form of ylst to an absolute y vector yab
% Then it doubles up tlst and yab in such a way that plot will plot
% straight edges as appropriate for PWM (txa, tya)
% converts delta form of ylst to absolute

clear yab yabl
yab(1) = 0;
for ind = 2:1:length(ylst);
yab(ind) = ylst(ind) + yab(ind-1);
yabl(ind) = yab(ind-1);
end;
txa = [tlst;tlst];
tya = [yabl;yab];
txa = txa(:);
tya = tya(:);
figure(1)
plot (txa,tya);
ax = axis;
% ax(1) = 0.0; % sets t_min of plot
ax(2) = 0.04; % sets t_max of plot
ax(3) = ax(3) - 0.2; % y_min
ax(4) = ax(4) + 0.2; % y_max
axis(ax)
B.1. Matlab Scripts 147
frplot.m
% fplot.m - plots the freq mag response
% cn - generated by t2f.m
% other consts - generated by initt2f.m
cn_mag = abs(cn); % cn_ph = angle(cn);
% bar (n*fres,cn_mag); % a linear plot

% ax = [ 0 ntop*fres 0 1 ];
% axis(ax)
figure(2) % a log plot

[xb,yb] = bar (fbins,cn_mag);
yb = yb + eps; % insert this line if you really want bars, not tops
semilogy(xb,yb,’+’);
ax = [ 0 2000 1e-3 3 ];
axis(ax)
grid
xlabel(’freq’)
ylabel(’Vm’)
B.1.2 Random and zero sequence modulation scripts
The next six Matlab scripts were used to generate the random modulation, zero
vector PWM results found in chapter 6. makedist.m called the following scripts
to from a distortion vector. rmod2.m creates the three phase modulating waveform
vector, including any zero vector; and rcarr.m creates the random triangular carrier
(run once at the outset). rcomp.m compares the modulating and carrier vectors to
produce the PWM vectors; rfft.m then performs a conventional fft on these to
create a frequency spectrum. wthd.m calculates the weighted harmonic distortion
of this spectrum.
makedist.m
% makedist.m
% calls other files repetitively to form a distortion vector dist
% files called are rmod2.m, rcomp.m, rfft.m, wthd.m
% see individual files for details.
% takes a few minutes to run.
tic
dist = [];
for M = 0.025:0.025:1.2;
% M = 0.025
rmod2
rcomp
rfft
y = wthd(fv3)
dist = [ dist; M y]
end
plot(dist(:,1),dist(:,2:4))
toc
rcarr.m
% rcarr.m produces just the random carrier. Follow with
%
% based on
% r4c3ph.m produces natural PWM time amplitude vector which can be
% directly processed by fft routines. and added. And shifted.
% based on nat.m, but has a random PWM period.
% 4 -- aims to do this for 4 level
% c -- the cleaned up version
% 2 -- makes each subcycle random (2N), not just the cycle (N)
% 3 -- another try at quadrature - Got it!
% 3ph -- 3 phase version
%
% quadrature is achieved by allowing the slope of the triangle to
% change partway through the slope - here at zero. Not a problem for
% digital natural where the sample is updated here. Shouldn’t be a
% problem for uniform either.
N = 9; % Pulse number
dev = 0.1; % PWM period random deviation +- dev.
cycles = 10; N = N*cycles; % determines the fft resolution
pwmres = 128; % for a subcycle, not a cycle!

rand(’seed’,1861711089) % gives a known repeatable ’good’ result
pwmper = (1-dev)*pwmres + 2*dev*pwmres*rand(2*N-1,1); % uniform dist
% pwmper = pwmres + 0.1*pwmres*randn(2*N-1,1); % normal dist
pwmper = round(pwmper);
pwmper = pwmper + (pwmres - round(mean(pwmper)));
pwmper = [ pwmper; (2*N*pwmres - sum(pwmper)) ];
figure(1)
plot(1:2*N,pwmper,[1 2*N],[pwmres pwmres])
% pause
clear pwmsawr; clear pwmsawf;

clear pwmsawrq; clear pwmsawfq;
for ind = 1:2:2*N-1;
scale = pwmres/pwmper(ind); scale2 = pwmres/pwmper(ind+1);
pwmsawf = [pwmsawf 0:scale:scale*(pwmper(ind)-1) ...
pwmres+(0:scale2:scale2*(pwmper(ind+1)-1))];
pwmsawfq = [pwmsawfq pwmres/2+(0:scale:scale*(pwmper(ind)-1)) ...
rem(1.5*pwmres+(0:scale2:scale2*(pwmper(ind+1)-1)),2*pwmres)];
end
% pwmsawfq = [pwmsawf(pwmres/2+1:(pwmres*2*N)) pwmsawf(1:pwmres/2)];
pwmsawr = rem((pwmres + pwmsawf),2*pwmres);
pwmsawrq = rem((pwmres + pwmsawfq),2*pwmres);
pwmsawf = [ pwmsawf; pwmsawf; pwmsawf ]’;

pwmsawfq = [ pwmsawfq; pwmsawfq; pwmsawfq ]’;
pwmsawr = [ pwmsawr; pwmsawr; pwmsawr ]’;
pwmsawrq = [ pwmsawrq; pwmsawrq; pwmsawrq ]’;
rmod2.m
% rmod.m creates three modulating waveforms.
% run with rcarr.m, rcomp.m
% plotsines.m plots the modulating waveforms from r4c3ph.m
% M = 0.9 % Modulation Depth, max 1.15
wtindex = 0:(2*N*pwmres-1);
wt = wtindex(:) ./ (2*N*pwmres);
% sineveca = M .* sin(2*pi*wt*cycles);
sineveca = sin(2*pi*wt*cycles);
sinevecb = sin((2*pi*wt*cycles)+ 2*pi/3 );
sinevecc = sin((2*pi*wt*cycles)+ 4*pi/3 );
sinevec = [sineveca sinevecb sinevecc];
% zerovec1 = -1.0 - sinevecb(((2*N*pwmres)/cycles/3+1):((2*N*pwmres)/cycles/2));

% zerovec5 = -0.5 - sinevecb(((2*N*pwmres)/cycles/3+1):((2*N*pwmres)/cycles/2));
% zerovec0 = - sinevecb(((2*N*pwmres)/cycles/3+1):((2*N*pwmres)/cycles/2));
% zerovec = [ zerovec1; -zerovec1 ];

% zerovec = zerovec * ones(1,3*cycles);
% zerovec = zerovec(:);
clear sineveca; clear sinevecb; clear sinevecc;
sinevec2 = M .* ( sinevec + [ zerovec zerovec zerovec ]);
ssinevec = (pwmres/2 .* sinevec2) + pwmres/2;
phphmod = [ (sinevec2(:,1)-sinevec2(:,2)) ...
(sinevec2(:,2)-sinevec2(:,3)) (sinevec2(:,3)-sinevec2(:,1))];
figure(3);
xti = (1:2*N*pwmres/cycles);
xt = wt(xti)*cycles/50;
% plot(xt,sinevec(xti,1)); pause;
% plot(xt,zerovec(xti,1)); pause;
% plot(xt,sinevec2(xti,1)); pause;
% plot(xt,sinevec(xti,1),xt,sinevec(xti,2),xt,sinevec(xti,3),...
% xt,zerovec(xti,1));
% ax = axis; ax(3)=-1.2; ax(4)=+1.2; axis(ax);
% pause; % print -deps abcz115a1.eps
% plot(xt,phphmod(xti,1),xt,phphmod(xti,2),xt,phphmod(xti,3));
% ax = axis; ax(3)=-1.2; ax(4)=+1.2; axis(ax);
% pause; % print -deps abct115a1.eps
plot(xt,sinevec2(xti,1),xt,sinevec2(xti,2),xt,sinevec2(xti,3))
ax = axis; ax(3)=-1.2; ax(4)=+1.2; axis(ax);
% pause; print -deps pptm115a1.eps
rcomp.m
% rcomp.m compares the carrier and modulating waves to get PWM
% run after rcarr, rmod
% leading = ssinevec > Npwmsaw;

% trailing = (pwmres - ssinevec) < Npwmsaw;
% both = leading | trailing;
% bothv = both(:)’;
leadingr = ssinevec > pwmsawr;

trailingr = ((2*pwmres) - ssinevec) <= pwmsawr;
bothr = leadingr | trailingr;
leadingf = ssinevec > pwmsawf;
trailingf = ((2*pwmres) - ssinevec) <= pwmsawf;
bothf = leadingf | trailingf;
leadingrq = ssinevec > pwmsawrq;

trailingrq = (2*pwmres - ssinevec) <= pwmsawrq;
bothrq = leadingrq | trailingrq;
leadingfq = ssinevec > pwmsawfq;
trailingfq = (2*pwmres - ssinevec) <= pwmsawfq;
bothfq = leadingfq | trailingfq;
bothr = 2.*bothr - 1;
bothf = 2.*bothf - 1;
bothrq = 2.*bothrq - 1;
bothfq = 2.*bothfq - 1;
allv = (bothr + bothf + bothrq + bothfq)/4;
phph = [ (allv(:,1)-allv(:,2)) (allv(:,2)-allv(:,3)) ...
(allv(:,3)-allv(:,1))];
figure(1)
xti = (1:2*N*pwmres/cycles);
xt = wt(xti)*cycles/50;
% plot(xt,allv(xti,1));
% ax = axis; ax(3)=ax(3)-0.1; ax(4)=ax(4)+0.1; axis(ax);
% pause; % print -deps pwma115a1.eps
plot(xt,phph(xti,1));
ax = axis; ax(3)=ax(3)-0.1; ax(4)=ax(4)+0.1; axis(ax);
% pause; % print -deps pwmab115a1.eps
% plot(xt,phph(xti,1),xt,phph(xti,2),xt,phph(xti,3));
% ax = axis; ax(3)=ax(3)-0.1; ax(4)=ax(4)+0.1; axis(ax);
% pause; % print -deps pwmphph115a1.eps
rfft.m
% rfft.m calcs the spectrum of the PWM waveforms
% run after rcarr rmod rcomp
figure(2)
fv1 = fft(bothf) ./ (N*pwmres);
fv2 = fft(allv) ./ (N*pwmres);
fv3 = fft(phph) ./ (N*pwmres);
%%%% Good for small number of cycles %%%

% [xb1,yb1] = bar(abs(fv1(1:39*cycles,1)));
% [xb2,yb2] = bar(abs(fv2(1:39*cycles,1)));
% semilogy(xb1,yb1,’-’,xb2,yb2,’-’)
% pause
% semilogy(xb2*50/cycles,yb2)
xi = 1:40*cycles; xp = xi*50/cycles;
% semilogy(xp,abs(fv1(xi,1)),’-’,xp,abs(fv2(xi,1)),’-’);
% semilogy(xp,abs(fv1(xi,1))); grid;
% ax = axis; ax(3)=1e-3; ax(4)=2; axis(ax);
% pause; % print -deps f1a115a1.eps
% semilogy(xp,abs(fv2(xi,1))); grid;
ax = axis; ax(3)=1e-3; ax(4)=2; axis(ax);
% pause; % print -deps f4a115a1.eps
semilogy(xp,abs(fv3(xi,1))); grid;
ax = axis; ax(3)=1e-3; ax(4)=2; axis(ax);
% pause; % print -deps f4ab115a1.eps
wthd.m
function y = wthd(x,i)
% WTHD Weighted Total Harmonic Distortion y = wthd(x,i)
% Weighted wrt x(n), if i is specified, otherwise, wrt max(x).
% assumes x is the output of fft, hence removes dc component and
% reflection of negative freqs.
% for vectors, WTHD returns a single THD figure
% for matrices, WTHD returns a row vector containing the THD
% of each column.
[m,n] = size(x);
if m == 1 % handle isolated row vector
x = x’; % (this is not how they do it)
[m,n] = size(x);
end % now m rows (!= 1) and n columns
% remove dc component and top half (neg freqs) of fft output

m = floor(m/2);
x = x(2:m+1,:);
x = abs(x);
% decide on fundamental component if not specified

% if (nargin == 1)
[junk,i] = max(x);
% else
% i = i-1;
% end
mi = [(1:m)]’;
mi = mi * (1./i);
L = find(mi < 1.0);
mi(L) = ones(size(L));
x2 = x;
% x2(i,:) = [0 0 0];
for ii = 1:n
x2(i(ii),ii) = 0;
end
y = sqrt(sum((x2./mi).^2)) ./ x(i); % weighted
% y = sqrt(sum((x2).^2)) ./ x(i); % unweighted
B.1.3 PWM EPROM Creation scripts
These last two Matlab scripts were used to generate the binary files used for the
re-sampled uniform EPROM implementation EPROMs. A simple C program was
used to strip off the .mat file header. This left a simple binary file suitable for use
by a standard EPROM programmer.
pwmrom.m
% pwmrom.m Geoff Walker Fri Sep 9 1994
% this file creates a matrix which is a rom table for natural pwm
clear
pwm_bits = 9;
pwm_res = 2^pwm_bits;
addr_a = 2*pwm_res;
addr_b = 7*addr_a/8;
all1s = ones(pwm_res);
pwm1u = triu(all1s,0);
pwm1l = tril(all1s,0);
pwm1l(:,1:1:pwm_res) = pwm1l(:,pwm_res:-1:1);
pwm1 = [pwm1u; pwm1l];
pwm_all = pwm1;
for i = 1:1:7
pwmd = pwm1(addr_b+1:1:addr_a,:);
pwma = pwm1(1:1:addr_b,:);
pwm1 = [pwmd;pwma];
pwm_all = 2*pwm_all + pwm1;
end;
pwm_all_all = pwm_all(:);
save pwmrom.mat pwm_all_all
pwmrom2.m
% pwmrom2.m Geoff Walker Fri Sep 9 1994
% this file creates a matrix which is a rom table for natural pwm
% outputs 0-3 are 4 * 90 degree phase shifted "greater than" outs,
% while 4-7 are corresponding "equal" outputs to allow cascading.
clear
pwm_bits = 3; % 7;
pwm_res = 2^pwm_bits;
addr_a = 2*pwm_res;
addr_b = 6*addr_a/8; % 270 degrees thru the table
all1s = ones(pwm_res);
pwm1u = triu(all1s,0); % the greater than matrix
pwm1l = tril(all1s,0);
pwm1l(:,1:1:pwm_res) = pwm1l(:,pwm_res:-1:1);
pwm1 = [pwm1u; pwm1l];
pwm_all = pwm1;
for i = 1:1:3
pwm1 = [pwmd;pwma];
end;
pwm1d = eye(pwm_res);
pwm1d2 = pwm1d;
pwm1d2(:,1:1:pwm_res) = pwm1d2(:,pwm_res:-1:1);
pwm1 = [pwm1d; pwm1d2]; % the equals matrix
for i = 1:1:3
pwm1 = [pwmd;pwma];
end;
pwm_all = pwm_all(:);
save pwmrom2.mat pwm_all
B.2 80C196 micro-controller code
Four representative C programs written for the 80C196KB evaluation board are in-
cluded here. The first two, tria.c and upwmd.c generated the four level natural
and uniform PWM results of section 4.4.1. The tria.c program produced square
waves with the desired frequency and phase shifts, with crystal accuracy and sta-
bility. These square waves were each integrated to produce triangular carriers used
in the analog natural PWM circuit.
The second two programs, upwm4.c and upwm4o.c are five level uniform PWM
modulators. The upwm4o.c was an extention which includes re-sampling. The re-
sults of this modulator are shown in section 5.3.1
B.2.1 tria.c
/* tria.c96 - creates three phase shifted square waves for natural
* PWM circuit integrators, which create the triangular carriers.
* Every PERIOD = 2.22ms / 6 an interrupt serviced by HSO_event occurs.
* It also alternately sets/clears one of HSO.0,1,2 in sequence.
* ie set1, clear2, set3, clear1, set2, clear3, set1, ...
* Note that this simple method only works for an odd number.
* It sets up the next interrupt (caused by the next HSO edge).
* This program writes a moving bit to ioport1 LEDs in backgrd to show
* that process is still alive.
*/
#pragma code
#include <k:80c196.h>
B.2. 80C196 micro-controller code 153
#define DELAY 16000

/* With a 16MHz xtal, timer is clocked at 1MHz, so ... */
#define PERIOD 370 /* 370.37 us = 1/(6 * 450Hz) */
#pragma interrupt (HSO_event = 3)
unsigned char up,leds,pin_no,cmd;

unsigned int edge_time,count;
main()
{
up = 1;
leds = 0x04;
count = 0;
pin_no = 0;
cmd = 0x10; /* setting this bit causes an HSO int */
int_mask = 0x08; /* Allow HSO interrupts */

int_pending = 0x00; /* but clear any that might be pending */
enable(); /* and now enable them. */
hso_command = cmd; /* Set up the first int */
hso_time = 0x0000; /* to occur when the timer rolls over. */
while(1){ /* background task -- loop forever */

for (count=0;count<DELAY;count++){
/* waste some time DELAY */
}
if (leds==0x80) up=0; /* At the top, so shift down */
if (leds==0x04) up=1; /* At the bottom, shift up */
if (up==1) leds <<= 1;
else leds = (leds>>1);
ioport1 = leds;
}
}
void HSO_event()
{
ioport1 |= 0x01; /* set pin on entry to interrupt - debug */
if (++pin_no > 2) pin_no = 0;
cmd = cmd ^ 0x20; /* toggle set/clear */
edge_time += PERIOD ;
hso_command = cmd + pin_no; /* cause int + set/clear pin_no */
hso_time = edge_time; /* at time edge_time */
ioport1 &= 0xfe; /* clear pin as we leave interrupt */
}
B.2.2 upwmd.c
/* upwmd.c96 - four level (three output) uniform PWM modulator
* reads the a-d every SM_PERIOD
* then sets/clears one of HSO.0,1,2
*
* Written for 16MHz xtal, 1MHz timer clock.
* uses unsigned integers for time_offset
* this program writes a moving bit to ioport1 LEDs
* in backgrd to show that process is still alive
* include files are found in k: because of Novell map
*/
#pragma code
#define DELAY 16000
#define SM_PERIOD 370 /* sampling period, ie a/d interrupt period */
#define START_DELAY 50 /* to allow for calculations in interrupt */
#define SW_PERIOD 1110 /* = 3 * 370 = edge period of PWM wave */
#define SCALE 58 /* 0x8000 / 58d = 556 */
#pragma interrupt (ad_done = 1)
extern volatile register unsigned int ad_result;

unsigned char up, clear, leds, pin_no;

unsigned int ad_in, data_in, junk, count,
sample_time, edge_time,
start_time, end_time, time_offset;
main()
{
up = 1;
leds = 0x02;
count = 0;
clear = 0;
pin_no = 0;
int_mask = 0x02;
int_pending = 0x00 ;
enable();
ad_command = 0x00;
sample_time = timer1 + 1000;
hso_command = 0x0f;
hso_time = sample_time;
start_time = sample_time + START_DELAY;
end_time = start_time + SW_PERIOD;
while(1){
}
if (leds==0x80) up=0;
if (up==1) leds <<= 1;
ioport1 = leds;
}
}
void ad_done()
{
ioport1 |= 0x01;
ad_in = ad_result;
time_offset = (ad_in / SCALE);
pwm_control = ad_result_hi; /* for debugging */
if (clear==1) /* pin is cleared and must be set */

{
edge_time = (end_time - time_offset);
hso_command = 0x20 + pin_no; /* set pin */
hso_time = edge_time;
clear = 0;
}
else /* pin is set and must be cleared */
{
edge_time = (start_time + time_offset);
hso_command = pin_no; /* clear pin */
clear = 1;
}
sample_time += SM_PERIOD;
ad_command = 0x00;
hso_command = 0x0f;
start_time = sample_time + START_DELAY;

end_time = start_time + SW_PERIOD;
if (++pin_no > 0x02) pin_no = 0x00;
ioport1 &= 0xfe;
}
B.2.3 upwm4.c
/* upwm4.c96 - uniform PWM modulator

* reads the a-d every SM_PERIOD (1800Hz)
* then sets one of HSO.0,1,2,3 and clears one of HSO.2,3,0,1
*
* this program writes a moving bit to ioport1 LEDs
*/
#pragma code
#define DELAY 16000
#define SM_PERIOD 556
#define MID_DELAY 600
#define SCALE 59 /* 0x8000 / 59d = 556 */
unsigned char up,leds,pin_to_set,pin_to_clr;

unsigned int sample_time,mid_time,edge_time,
ad_in,junk,count;
signed int time_offset,data_in;
main()
{
up = 1;
leds = 0x02;
count = 0;
pin_to_set = 0;
pin_to_clr = 2;
sample_time = timer1 + 1000; /* start in 1ms */
ad_command = 0x00;
hso_command = 0x0f;
mid_time = sample_time + MID_DELAY;
int_mask = 0x02;
int_pending = 0x00 ;
enable();
while(1){
/* waste some time */
}
if (up==1) leds <<= 1;
ioport1 = leds;
}
}
void ad_done()
{
ioport1 |= 0x01;
ad_in = ad_result;
data_in = 0x8000 - ad_in; /* conv to twos comp */
time_offset = (data_in / SCALE); /* can be pos or neg */
edge_time = (mid_time + time_offset);

hso_command = 0x20 + pin_to_set; /* set pin */
edge_time = (mid_time - time_offset);
hso_command = pin_to_clr; /* clear pin */
A/D samples
if pin_state[pin] is SET
(to be cleared)
pwm0_t
sama_t
sami_t
hso_time
CALC_D
sam_pwm_d edge_d_sam
PWM_P_2 time_in
edge_d_0 = clr_d
ad_done()
sample_time += SM_PERIOD;
ad_command = 0x00;
hso_command = 0x0f;
mid_time = sample_time + MID_DELAY;
if (++pin_to_set > 0x03) pin_to_set = 0x00;
if (++pin_to_clr > 0x03) pin_to_clr = 0x00;
ioport1 &= 0xfe;
}
B.2.4 upwm4o.c
/* upwm4o.c - uniform PWM modulator -
* 4 - four output, ie five level
* o - with oversampling
* starts the a-d every SAM_PER -- some multiple of the switch period.
* Completion of this causes an interrupt, data is fetched, and next
* a-d conversion is scheduled.
* Also decides if there should be and edge for any of the four outputs
* before the next SAM_PER value is read. If so, then sets/clears any
* of HSO.0-3 as required.
*
* This program writes a moving bit to ioport1 LEDs
*/
#pragma code
#define TRUE 1
#define FALSE 0
#define DELAY 16000 /* for the background "I’m alive" loop */
#define SET 0x20

#define CLR 0x00
#define PIN_NO 4 /* Number of carriers, ie output pins */

#define OSR 8 /* OverSample Ratio = PWM_PER / SAM_PER */
#define OSR_2 4
/*
* The new figures are for 18.432M xtal, old for 16M.
* Both generate fc = 450Hz
* With 16.0MHz crystal, 450Hz = 2222.2us = 2222 counts approx.
* With 18.432M crystal, 450Hz = 2222.2us = 2560 counts exactly.
* Note that PWM_PER is the edge period, not pulse period.
* This SAM_PER (160) is the shortest power of two possible, since it must
* be greater than CALC_D to ensure the interrupt completes and exits
* before the next one is called.
*/
#define PWM_PER 1280 /* 1112 */
#define PWM_P_2 640 /* 556 */
#define SAM_PER 160 /* 139 */
/*
* This calculation delay is inserted between beginning of interrupt and
* the earliest possible edge to allow for calculation time of this
* edge position to ensure we don’t miss it.
*/
#define CALC_D 100
/*
* This is just short of 640, so a full scale a/d input causes
* an almost 100% duty cycle (630/640).
*/
/* #define SCALE 59 /* 0x8000 / 59d = 555d for 16M xtal */
#define SCALE 52 /* 0x8000 / 52d = 630d for 18.432M */
unsigned char up, leds, sam_no, pin, odd;

unsigned char pin_state[PIN_NO], /* current state of pin, SET or CLR */
pin_done[PIN_NO]; /* whether pin edge has occured
this period (to avoid double edges) */
unsigned int sami_t, /* imagined time of sample for PWM calcs */
sama_t, /* actual time sample occurs / is scheduled */
pwm0_t[PIN_NO], /* beginning of PWM carrier period */
ad_in, junk, count;
signed int data_in, /* signed version of ad_in */

time_in, /* scaled version of data_in, using SCALE */
sam_pwm_d, /* pwm0_t to sami_t delay, difference */
set_d, clr_d, /* pwm0_t to edge time difference */
edge_d_0, /* set_d or clr_d, as required */
edge_d_sam; /* sami_t to edge time difference */
main()
{
up = 1;
leds = 0x02;
count = 0;
sam_no = 0;
pin_state[0] = SET;
pin_state[2] = CLR;
pin_state[1] = SET;
pin_state[3] = CLR;
sama_t = timer1 + 1000;
sami_t = sama_t + CALC_D;
ad_command = 0x00;
hso_command = 0x0f;
hso_time = sama_t;
pwm0_t[0] = sami_t;
pwm0_t[2] = sami_t;
pwm0_t[1] = sami_t - PWM_P_2;
pwm0_t[3] = sami_t - PWM_P_2;
int_mask = 0x02;
int_pending = 0x00;
enable();
while(1){
}
if (up==1) leds <<= 1;
ioport1 = leds;
}
}
void ad_done()
{
ioport1 |= 0x01; /* set pin 1.0 on entry for debugging and profiling */
ad_in = ad_result;
data_in = 0x8000 - ad_in; /* conv to twos comp */
time_in = (data_in / SCALE);
set_d = (PWM_P_2 - time_in);
clr_d = (PWM_P_2 + time_in);
for (pin=0; pin<PIN_NO; pin++) {
if (pin_done[pin] == FALSE) {
if(pin_state[pin] == CLR) /* pin is to be set */
edge_d_0 = set_d;
else
edge_d_0 = clr_d;
sam_pwm_d = (sami_t - pwm0_t[pin]);
edge_d_sam = edge_d_0 - sam_pwm_d;
/* edge missed! so do best we can ... set edge time to now */

if (edge_d_sam < 0)
edge_d_sam = 0;
/* edge is this sample period, so schedule it to occur, & flag it as done. */

if (edge_d_sam < SAM_PER) {
hso_command = pin_state[pin] + pin;
hso_time = sami_t + (unsigned int)edge_d_sam;
pin_done[pin] = TRUE;
}
}
}
/*
* This period is done. Now set up for the next one.
* schedule the next a/d conversion and subsequent interrupt
*/
sama_t += SAM_PER;
ad_command = 0x00;
hso_command = 0x0f;
hso_time = sama_t;
sami_t = sama_t + CALC_D;

if (++sam_no >= OSR_2) {
sam_no = 0;
if (odd == TRUE) {
pwm0_t[1] += PWM_PER;
pin_state[1] ^= SET;
pin_done[1] = FALSE;
odd = FALSE;
} else {
B.3. Simulation C code 159
odd = TRUE;
}
}
ioport1 &= 0xfe; /* clear port pin 1.0 on exit */
}
B.3 Simulation C code
A number of C programs were written to supplement the Matlab simulation code.

These C programs were used to generate the time and step vectors more quickly than
Matlab could, and using methods that mirrored the microcontroller code. These
vectors were then imported into Matlab using the load command. The jump function
spectrum analysis and plotting were done using Matlab.
B.3.1 hdn4si.c
/*
* hdn4si.c
* hdn -- Harmonics of Digital Natural
* 4 -- the five level version.
* s -- only a single edge per edge period allowed
* i -- integer based (previous versions were floating point)
*
* Calculates the time and delta vectors of a PWM waveform as
* required for jump function analysis, and saves these as a Matlab .mat
* file ready for loading into Matlab.
*
* Can have third harmonic added to f1 - comment in/out appropriate code.
*
* f1, T1 = fundamental synthesised freq, period. eg 50 Hz
* fc, Tc = _edge_ freq, per, ie 2* carrier freq. eg 900 Hz
* fs, Ts = sample freq, per, an integer multiple of fc.
* osr = oversampling ratio = fs / fc = Tc / Ts
* nfc = normalised carrier frequency = fc / f1 = T1 / Tc
*/
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#define TRUE 1
#define FALSE 0
#define RASIZE 20
typedef struct{
long int type;
long int mrows;
long int ncols;
long int imagf;
long int namelen;
} Fmatrix;
void write_matrix(Fmatrix *x, char *pname, double *pr, double *pi, FILE *fp);
int main (void)

{
FILE *fp;
char *filename, rply[RASIZE];
Fmatrix tm;
int mi, nfc, osr, osri, itop, nc;

int f1, fc, fs, fi, fres, f1_ph_deg;
float T1, Tc, Ts, Ti, Tres, Toff, To;
float ic, is, m;
float tx, yx, w1, one_mtri;
float f1_ph;
int edge_found, tri_slope_pos, edge_delta, i;
mi = 9;
m = 0.9;
f1 = 50;
f1_ph_deg = 0;
osri = 12;
printf("enter f1 [%d] : ",f1);

gets(rply);
sscanf(rply,"%d",&f1);
printf("enter m [%.2f] : ",m);
gets(rply);
sscanf(rply,"%f",&m);
printf("enter f1_ph (deg) [%d] : ",f1_ph_deg);
gets(rply);
sscanf(rply,"%d",&f1_ph_deg);
printf("enter osri [%d] : ",osri);
gets(rply);
sscanf(rply,"%d",&osri);
osr = 1;
for (i=0;i<osri;i++)
osr = osr * 2;
fc = 900; fi = fc * 4096; fres = 25;

fs = osr * fc; nc = 4;
T1 = 1.0/f1; Tc = 1.0/fc; Ts = 1.0/fs;
Ti = 1.0/fi; Tres = 1.0/fres; Toff = 2.0*Tc/nc;
nfc = fc / f1;
itop = (fc / fres) * nc ;
f1_ph = M_PI * f1_ph_deg / 180.0;
printf(" Ok, f1 = %d, ",f1);

printf(" fc = %d, ",fc);
printf(" fs = %d, \n ",fs);
printf(" f1_ph = %.2f, ",f1_ph);
printf(" m = %.2f, ",m);
printf(" osr = %d \n",osr);
{
double tlst[itop];
double ylst[itop];
/*
* mtri = 4 / Tc = 2 / (Tc/2) = dy / dt
* mtri = (yx - y0) / (tx - t0) =>
* tx = t0 + (yx - y0) * one_mtri;
*/
w1 = 2.0 * M_PI * f1 ;
one_mtri = Tc / 2.0;
i = 0;
/* printf("%g, %g, %g\n\n",T1,Tc,Ts); */

printf("Calculating edges:\n ");
for (To=0; To<(2.0*Tc); To+=Toff) {
for (ic=0; ic<Tres; ic+=Tc) {
edge_found = FALSE;
tri_slope_pos = !tri_slope_pos;
if (tri_slope_pos)
edge_delta = -1;
else
B.3. Simulation C code 161
edge_delta = 1;
for (is=0; is<Tc; is+=Ts) {
/* printf("%g, %g, ",ic,is); */
/* yx = m * sin(w1*(ic+is+To)); */
/* yx = m * sin((w1*(ic+is+To))+f1_ph); */
yx = m*(1.15*sin((w1*(ic+is+To))+f1_ph)+0.21*sin(3.0*(w1*(ic+is+To)+f1_ph)));
tx = (yx + 1) * one_mtri;
if (tri_slope_pos)
tx = Tc - tx;
if (tx <= (is+Ts)) { /* edge this sample */
if (tx < is) /* edge missed */
tx = is;
tx += To + ic;
if (tx > Tres)
tx -= Tres;
tlst[i] = (double) (tx);
ylst[i] = (double) (edge_delta);
printf(".");
/* printf("%d, %g, %g, %d\n",i,tx,yx,edge_delta); */
i++;
break;
}
}
}
}
printf("\n done calculating - %d edges\n",i);
/*
* Now we write out the results in standard matlab .mat file format
*/
tm.type = 1000;
tm.mrows = 1;
tm.ncols = (itop);
tm.imagf = 0;
tm.namelen = 5;
filename = "temp";
printf (".mat filename? <%s> :",filename);
gets(rply);
if (rply[0] != NULL) {
filename = rply;
strcat (filename,".mat");
}
else
filename = "temp.mat";
/* printf("rply = %s\n",rply); */
printf(" Ok, filename = %s \n",filename);
if((fp = fopen (filename,"w")) == NULL) {
puts("error opening file");
exit;
}
write_matrix(&tm, "tlst", tlst, tlst, fp);

write_matrix(&tm, "ylst", ylst, ylst, fp);
fclose(fp);
}
return(0);
}/* main */
void write_matrix(Fmatrix *x, char *pname, double *pr, double *pi, FILE *fp)
{
int mn;
fwrite (x, sizeof(Fmatrix), 1, fp);

fwrite (pname, sizeof(char), x->namelen, fp);
mn = x->mrows * x->ncols;
fwrite(pr, sizeof(double), mn, fp);
if (x->imagf) {
fwrite(pi, sizeof(double), mn, fp);
}
An example run of hdn4si follows.
darkstar:~/c/c$ gcc hdn4si.c -o hdn4si -lm

hdn4si.c: In function ‘main’:
hdn4si.c:155: warning: comparison between pointer and integer
darkstar:~/c/c$ hdn4si
enter f1 [50] :
enter m [0.90] : 0.2
enter f1_ph (deg) [0] :
enter osri [12] :
Ok, f1 = 50, fc = 900, fs = 3686400,
f1_ph = 0.00, m = 0.20, osr = 4096
Calculating edges:
..............................................................................
..................................................................
done calculating - 144 edges
.mat filename? <temp> :example
Ok, filename = example.mat
darkstar:~/c/c$
Appendix C
Circuits
C.1 Natural, 80C196 and EPROM modulators
The circuits follow are
1. Natural PWM circuit
2. 80C196 Microcontroller based PWM circuit
3. EPROM based Digital Natural PWM circuit
The naturally sampled PWM modulator was initally wired as a four level circuit
using a slightly different circuit, with different components (most notably faster
LM319 comparitors). This circuit was used for the results gathered in figure 4.9.
The seven level circuit shown here was used later to gather the transfer function
results seen in figure 4.16. This circuit as shown, used slower LM339 comparitors to
give a more noise immune circuit, along with minor changes in topology to reduce
the circuits sensitivity to component tolerance.
The 80C196 microcontroller circuit was also tried as a four, five and seven level
modulator using different software. Only the appropriate number of outputs were
summed. Asymmetric uniform and re-sampled uniform were both evalutated using
this circuit. The master crystal frequency for the 80C196 was chosen to be 18.432
MHz as this was an exact multiple of the 450 Hz switching frequency that was used
for most simulations and experiments.
163
164 Appendix C. Circuits
C.1. Natural, 80C196 and EPROM modulators 165
C.2. DSP-Flex FLEX8820 configuration 167
C.2 DSP-Flex FLEX8820 configuration
Shown is the configuration for the FPGA implementation of re-sampled uniform.

These particular circuits are for the three phase five level seven bit PWM resolution
implementation with deadtime between switches. An eleven bit resolution version
was also successfully trialled.
MAX+plus II 8.1 File: PWM_1PH.GDF Date: 03/26/98 21:11:22 Page: 1
INPUT
CLK VCC
LPM_AVALUE=
LPM_SVALUE=
LPM_WIDTH=8
LPM_DFF
INPUT
TMR[7..0] VCC
INPUT data[]
CMP[7..0] VCC
INPUT
q[]
UPDATE VCC
OUTPUT
Q[3..0]
TITLE
1ph / 5lvl PWM Macro
COMPANY
UQ, UN
DESIGNER
G. Walker, E. LoGiudice
SIZE NUMBER REV
C 1.00 A
DATE SHEET OF
7:37p 9-17-1996 1 1
MAX+plus II 8.1 File: C:\USR\WALKERG\P8B5LD\PHASE.WDF Date: 03/26/98 20:19:47 Page: 1
Name: Type: 250.0ns 500.0ns 750.0ns 1.0us 1.25us 1.5us 1.75us 2.0u
[I] TMR[11..9] INPUT 0 1 2 3 4 5 6 7
[O] S000[11..9] COMB 0 1 2 3 4 5 6 7

[O] S045[11..9] COMB 7 0 1 2 3 4 5 6
[O] S090[11..9] COMB 6 7 0 1 2 3 4 5
[O] S135[11..9] COMB 5 6 7 0 1 2 3 4
[O] S180[11..9] COMB 4 5 6 7 0 1 2 3
[O] S225[11..9] COMB 3 4 5 6 7 0 1 2
[O] S270[11..9] COMB 2 3 4 5 6 7 0 1
[O] S315[11..9] COMB 1 2 3 4 5 6 7 0
168
MAX+plus II 8.1 File: P8B5LD.GDF Date: 03/26/98 20:55:34 Page: 1 LPM_AVALUE=
LPM_DIRECTION=
LPM_MODULUS=
LPM_SVALUE=
LPM_WIDTH=8
LPM_COUNTER
q[] OUTPUT
TMR7 p8b5ld@137
INPUT
p8b5ld@121 CLK_IN VCC
INPUT
/INT[3..1] VCC
INPUT
XF[1..0] VCC
INPUT
p8b5ld@11 /IACK VCC
INPUT
ADDR[7..2] VCC
OUTPUT
A[3..0]
OUTPUT
At[3..0]
OUTPUT
Ab[3..0]
OUTPUT
B[3..0]
INPUT OUTPUT
D[15..0] VCC Bt[3..0]
OUTPUT
Bb[3..0]
INPUT
p8b5ld@7 /FLEX VCC
INPUT
p8b5ld@8 R/W VCC
INPUT
ADDR[1..0] VCC
OUTPUT
C[3..0]
OUTPUT
Ct[3..0]
OUTPUT
Cb[3..0]
LPM_SIZE=8
LPM_WIDTH=1
LPM_WIDTHS=CEIL(LOG2(LPM_SIZE))
LPM_PIPELINE=
LPM_MUX
data[][] result[] OUTPUT

SAMPLE_RATE p8b5ld@139
sel[]
LPM_SIZE=4
LPM_WIDTH=1
LPM_PIPELINE=
SOFT LPM_MUX
INPUT
p8b5ld@118 EXT_CLK VCC
SOFT data[][] result[] OUTPUT
INPUT CLK_OUT p8b5ld@133
p8b5ld@12 TCLK0 VCC
SOFT
INPUT sel[]
p8b5ld@13 TCLK1 VCC
SOFT
INPUT
p8b5ld@17 H1 VCC
Appendix C. Circuits
NOT
OUTPUT
/AD_STROBE p8b5ld@194
TITLE
3Ph 5Lvl 8Bit PWM
COMPANY
UQ, UN
DESIGNER
p8b5ld@190 /AD_BUSY
INPUT
VCC
OUTPUT
/INT0 p8b5ld@205 G. Walker, E. LoGiudice
SIZE NUMBER REV
D 1.00 A
DATE SHEET OF
5:07p 3-16-1998 1 1
MAX+plus II 8.1 File: PWM.GDF Date: 03/26/98 21:09:12 Page: 1
INPUT
CLK VCC
LPM_REPRESENTATION=
LPM_WIDTH=8
LPM_COMPARE
alb
INPUT
CMP[7..0] VCC dataa[]
INPUT F*
S0[7..0] VCC datab[]
OR2 DFF
PRN OUTPUT
D Q Q0
LPM_REPRESENTATION=
LPM_WIDTH=8
LPM_COMPARE CLRN
dataa[] agb
datab[]
LPM_REPRESENTATION=
LPM_WIDTH=8
LPM_COMPARE
alb
dataa[]
INPUT F*
S1[7..0] VCC
datab[]
OR2 DFF
PRN OUTPUT
D Q Q1
LPM_REPRESENTATION=
LPM_WIDTH=8
LPM_COMPARE CLRN
dataa[] agb
datab[]
LPM_REPRESENTATION=
LPM_WIDTH=8
LPM_COMPARE
alb
dataa[]
INPUT F*
S2[7..0] VCC
datab[]
OR2 DFF
PRN OUTPUT
D Q Q2
LPM_REPRESENTATION=
LPM_WIDTH=8
LPM_COMPARE CLRN
dataa[] agb
datab[]
LPM_REPRESENTATION=
LPM_WIDTH=8
LPM_COMPARE
alb
dataa[]
INPUT F*
S3[7..0] VCC
datab[]
OR2 DFF
PRN OUTPUT
D Q Q3
LPM_REPRESENTATION=
LPM_WIDTH=8
LPM_COMPARE CLRN
dataa[] agb
datab[]
TITLE
1ph / 3lvl PWM Macro
COMPANY
UQ, UN
DESIGNER
SIZE NUMBER REV
DV 1.00 A
DATE SHEET OF
4:50p 9-30-1996 1 1
MAX+plus II 8.1 File: DEADTIME.GDF Date: 03/26/98 21:14:26 Page: 1
LPM_SIZE=8
LPM_WIDTH=1
LPM_MUX
AND2 DFF
data[][] result[]
PRN OUTPUT
D Q PWM_TOP
sel[]
INPUT CLRN
SEL[2..0] VCC
OR2 DFF
PRN OUTPUT
D Q PWM_BOT
CLRN
LPM_AVALUE=
LPM_SVALUE=
LPM_WIDTH=8
LPM_DFF
INPUT shiftin
PWM_IN VCC
shiften
1
GND
INPUT
q[]
CLK VCC
MAX+plus II 8.1 File: DT4.GDF Date: 03/26/98 20:59:37 Page: 1
INPUT
CLK VCC
INPUT
SEL[2..0] VCC
INPUT
PWM[3..0] VCC
OUTPUT
PWMT[3..0]
OUTPUT
PWMB[3..0]
MAX+plus II 8.1 File: DSP.GDF Date: 03/26/98 20:55:20 Page: 1
LPM_AVALUE=
LPM_SVALUE=
LPM_WIDTH=8
LPM_DFF
data[]
q[]
enable
LPM_AVALUE=
LPM_SVALUE=
LPM_WIDTH=8
LPM_DFF
data[]
q[]
enable
LPM_AVALUE=
LPM_SVALUE=
LPM_WIDTH=8
LPM_DFF
data[]
q[]
enable
LPM_AVALUE=
LPM_SVALUE=
LPM_WIDTH=8
LPM_DFF
data[]
q[]
enable
TITLE
DSP Interface and Buffers
COMPANY
UQ, UN
DESIGNER
SIZE NUMBER REV
C 1.00 A
DATE SHEET OF
12:15p 3-14-1998 1 1
MAX+plus II 8.1 File: INT.GDF Date: 03/26/98 21:07:26 Page: 1
TITLE
Edge to Level Interrupt Line Conditioner
COMPANY
The University of Newcastle
DESIGNER
E. LoGiudice
SIZE NUMBER REV
C 1.00 A
DATE SHEET OF
2:58p 8-13-1996 1 1
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Walker PHD Thesis

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Walker PHD Thesis

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Modulation and Control of

Geoﬀrey R. Walker B.E.(Hons)

Department of Computer Science and Electrical Engineering

University of Queensland, QUEENSLAND 4072

This thesis is submitted in fulﬁlment of

the requirements of the degree of

The University of Queensland

A general deﬁnition of a (power) converter, and subsequently a multilevel con-

Starting from the essential requirements, the diﬀerent approaches to switching

Re-sampled Uniform, a technique for achieving natural like sampling digitally is

Further improvements to carrier based PWM are possible by randomising the

These diﬀerent approaches to improving the modulation of multilevel converters

This thesis oﬀers a deﬁnition of the term “multilevel converter”.

It reviews all currently published multilevel converter structures without bias,

Three diﬀerent implementations of this new technique called “resampled uni-

The technique for the extention of random modulation to multilevel converters

G. Walker, G. Ledwich, “ Bandwidth Considerations for Multilevel Converters”

G. Walker, G. Ledwich, “ Implementing Natural PWM Digitally ” Proceedings of the

G. Walker, G. Ledwich, “ An Isolated MOSFET Gate Driver ” Proceedings of the

G. Walker, G. Ledwich, “ Bandwidth Considerations for Multiple Modulator Con-

Declaration of Originality iii

List of Figures xviii

1.1 Thesis Organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 The Multilevel Converter 5

2.1.1 Uniﬁed Converter Theory . . . . . . . . . . . . . . . . . . . . 5

2.1.2 Inverter or Rectiﬁer? Voltage or Current Source? . . . . . . . 6

2.1.3 The General Multilevel Converter . . . . . . . . . . . . . . . . 8

2.1.4 The Traditional Multilevel Converter . . . . . . . . . . . . . . 10

2.2 Multilevel Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.1 Transformer/Inductor summed Multiple Bridge Converter . . 12

2.3.2 Series Connected Isolated Multiple Bridge Converter . . . . . 16

2.3.3 Neutral Point Clamped (NPC) Converter . . . . . . . . . . . . 17

2.3.4 Flying Capacitor Converter . . . . . . . . . . . . . . . . . . . 21

2.4 Current Source Converters . . . . . . . . . . . . . . . . . . . . . . . . 23

2.4.1 Multilevel Current Converter Topologies . . . . . . . . . . . . 24

2.5 Applications of Multilevel Converters . . . . . . . . . . . . . . . . . . 27

3 Pulse Width Modulation Candidates for Multilevel 29

3.1 A Deﬁnition of Modulation . . . . . . . . . . . . . . . . . . . . . . . . 29

3.2 Review of PWM Techniques . . . . . . . . . . . . . . . . . . . . . . . 30

3.2.1 Requirements Common to All PWM Techniques . . . . . . . . 30

3.2.2 Selective Harmonic Elimination / Minimisation PWM . . . . . 32

3.2.3 Hysteresis Band PWM . . . . . . . . . . . . . . . . . . . . . . 33

3.3 Carrier Based PWM Techniques . . . . . . . . . . . . . . . . . . . . . 35

3.3.1 Fundamental – Carrier waveform relationships . . . . . . . . . 37

3.3.2 Modulation Variations . . . . . . . . . . . . . . . . . . . . . . 39

3.3.3 Variable and Random Period PWM . . . . . . . . . . . . . . . 41

3.4 Summary: The Best Modulation Option for Multilevel . . . . . . . . 43

4 Multilevel Carrier Based PWM 45

4.1 Carrier Based PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.2 Naturally Sampled PWM . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.2.2 Sinusoidal Natural Modulation . . . . . . . . . . . . . . . . . 48

4.3 Uniformly Sampled PWM . . . . . . . . . . . . . . . . . . . . . . . . 50

4.3.1 Uniform PWM Spectrum . . . . . . . . . . . . . . . . . . . . . 51

4.3.2 Extension to Multiple Modulators . . . . . . . . . . . . . . . . 51

4.4 Modulator Implementation . . . . . . . . . . . . . . . . . . . . . . . . 54

4.4.1 Experimental Hardware . . . . . . . . . . . . . . . . . . . . . 57

4.5 Input signal Attenuation, Distortion and Phase delay . . . . . . . . . 60

4.5.1 Experimentally Gathered Modulator Transfer Functions . . . 64

4.5.2 The Slew Rate Limit . . . . . . . . . . . . . . . . . . . . . . . 65

4.5.3 Lower Sidebands . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.5.4 Synchronous Natural Modulation . . . . . . . . . . . . . . . . 69

5 Digital Natural — Re-sampled Uniform 73

5.2 Re-sampled Uniform . . . . . . . . . . . . . . . . . . . . . . . . . . . 75