Dynamic

Dynamic and
and
Pass-Transistor
Pass-Transistor
Logic
Logic
Prof. Vojin G. Oklobdzija

References (used for creation of the presentation material):

1. Masaki, “Deep-Submicron CMOS Warms Up to High-Speed Logic”, IEEE
Circuits and Devices Magazine, November 1992.
2. Krambeck, C.M. Lee, H.S. Law, “High-Speed Compact Circuits with CMOS” ,
IEEE Journal of Solid-State Circuits, Vol. SC-13, No 3, June 1982.
3. V.G. Oklobdzija, R.K. Montoye, “Design-Performance Trade-Offs in CMOS-
Domino Logic”, IEEE Journal of Solid-State Circuits, Vol. SC-21, No 2, April
1986.
 References:

4. Goncalves, H.J. DeMan, “NORA: A Racefree Dynamic CMOS

Technique for Pipelined Logic Structures” , IEEE Journal of Solid-
State Circuits, Vol. SC-18, No 3, June 1983.
5. L.G. Heller, et al, “Cascode Voltage Switch Logic: A Differential
CMOS Logic Family”, in 1984 Digest of Technical Papers, IEEE
International Solid-State Circuits Conference, February 1984.
6. L.C.M.G. Pfennings, et al, “Differential Split-Level CMOS Logic for
Subnanosecond Speeds”, IEEE Journal of Solid-State Circuits,
Vol. SC-20, No 5, October 1985. 
7. K.M. Chu, D.L. Pulfrey, "A Comparison of CMOS Circuit Techniques:
Differential Cascode Voltage Switch Logic Versus Conventional
Logic", IEEE Jouirnal of Solid-State Circuits, Vol. SC-22, No.4,
August 1987.

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 2

 References:
Pass-Transistor Logic:

8. S. Whitaker, “Pass-transistor networks optimize n-MOS logic”,

Electronics, September 1983.
9. K. Yano, et al, “A 3.8-ns CMOS 16x16-b Multiplier Using
Complementary Pass-Transistor Logic”, IEEE Journal of Solid-State
Circuits, Vol. 25, No 2, April 1990.
10. K. Yano, et al, “Lean Integration: Achieving a Quantum Leap in
Performance and Cost of Logic LSIs", Proceedings of the Custom
Integrated Circuits Conference, San Diego, California, May 1-4, 1994.
11. M. Suzuki, et al, “A 1.5ns 32b CMOS ALU in Double Pass-Transistor
Logic”, Journal of Solid-State Circuits, Vol. 28. No 11, November
1993.
12. N. Ohkubo, et al, “A 4.4-ns CMOS 54x54-b Multiplier Using Pass-
transistor Multiplexer”, Proceedings of the Custom Integrated
Circuits Conference, San Diego, California, May 1-4, 1994.

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 3

 References:

13. V. G. Oklobdzija and B. Duchêne, “Pass-Transistor Dual Value

Logic For Low-Power CMOS,” Proceedings of the 1995
International Symposium on VLSI Technology, Taipei, Taiwan,
May 31-June 2nd, 1995.
14. F.S. Lai, W. Hwang, “Differential Cascode Voltage Switch with
the Pass-Gate (DCVSPG) Logic Tree for High Performance
CMOS Digital Systems”, Proceedings of the 1993 International
Symposium on VLSI Technology, Taipei, Taiwan, June 2-4, 1995
15. A. Parameswar, H. Hara, T. Sakurai, “A Swing Restored Pass-
Transistor Logic Based Multiply and Accumulate Circuit for
Multimedia Applications”, Proceedings of the Custom Integrated
Circuits Conference, San Diego, California, May 1-4, 1994.
16. T. Fuse, et al, “0.5V SOI CMOS Pass-Gate Logic”, Digest of
Technical Papers, 1996 IEEE International Solid-State Circuits
Conference, San Francisco February 8, 1996.

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 4

 Pass-Transistor Logic

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 5

 Pass-Transistor Logic
A

A F 0 1

B 0 0 1
F
B B 1 1 0

A
B B
(a) (b)

(a) XOR function implemented with pass-transistor circuit

(b) Karnaough map showing derivation of the XOR function

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 6

 Pass-Transistor Logic
A X Y F
0 0 0
0 1 A
X 1 0 A
F 1 1 1
0 B AB
Y 0 B AB
1 B AB
A 1 B AB
B 0 AB
B 1 AB
General topology of pass- B 0 A+B
transistor function generator B 1 A B
B B B
B B A B
Karnaough map of 16 possible B B A B
functions that can be realized B B B

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 7

 Pass-Transistor Logic
A A B B
Function generator
implemented with pass-
transistor logic
P0

P1
F(A,B)

P2

P3

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 8

 Pass-Transistor Logic

A=Vdd
+ V Vdd Vdd
th
B=Vdd - + V V +
th th
Fmax = Vdd-Vth -- Fmax = Vdd-Vth
Vdd
B Cout Cout

(a) (b)

Threshold voltage drop at Voltage drop does not

the output of the pass- exceed Vth when there
transistor gate are multiple transistors in
the path

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 9

 Pass-Transistor Logic
+Vdd
A=Vdd
+ V Vdd
th
- + V
th
In=Vdd Fmax= Vdd -
Vdd
ON
Cout Cin
+

Vdd -
A=0V
(a) (b)

Elimination of the threshold voltage drop by:

(a) pairing nMOS transistor with a pMOS
(b) using a swing-restoring inverter
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 10
 Complementary Pass-Transistor
Logic (CPL)
Pass Variables

Inputs

Control f f
Variables

F F
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 11
 Basic logic functions in CPL
A B B A A B A A A A A B

B B

B B

A B B A A B
A B B A A C B C
B
C
B
C

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 12

 CPL Logic
A A
A A
B
n1 n2

B B
n3 n4

B
C

Q Qb C
S S (a) (b)
S S
XOR gate
Sum circuit
CPL provides an efficient implementation of XOR function
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 13
 CPL Inverter

Level Restoration
Transistor Output Inverter

Input Output

Feedback Inverter

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 14

 Double Pass-Transistor Logic (DPL):
VDD
A B B A AND/NAND
A B
B B

A A

O
O

A B A B A B A B XOR/XNOR
B A
A B
A B
B A
A B

O
O
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 15
 Double Pass-Transistor Logic (DPL):
A A
A A

n1 p2 n1 p2
B
B
p1 n2 p1 n2

B C

Q Qb
C

O O
S S
(a) XOR (b)
One bit full-adder:
Sum circuit

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 16

 Double Pass-Transistor Logic (DPL):
AND/NAND
Vcc DPL Full Adder
A
A C C
B Vcc
B S

Vcc

A S
A
Multiplexer Buffer
B
B The critical path traverses two
transistors only
OR/NOR (not counting the buffer)
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 17
 Formal Method for CPL Logic
Derivation
Markovic et al. 2000

(a) Cover the Karnaugh-map with largest possible cubes

(overlapping allowed)
(b) Express the value of the function in each cube in
terms of input signals
(c) Assign one branch of transistor(s) to each of the
cubes and connect all the branches to one common
node, which is the output of NMOS pass-transistor
network

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 18

 Formal Method for P-T Logic
Derivation
Complementary function can be implemented from the same
circuit structure by applying complementarity principle:
Complementarity Principle: Using the same circuit
topology, with pass signals inverted, complementary logic
function is constructed in CPL.
By applying duality principle, a dual function is synthesized:

Duality Principle: Using the same circuit topology, with

gate signals inverted, dual logic function is constructed.
Following pairs of basic functions are dual:
AND-OR (and vice-versa)
NAND-NOR (and vice-versa)
XOR and XNOR are self-dual (dual to itself)
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 19
 Derivation of P-T Logic
A AND A NAND
B B

A OR A OR
B B

B B B
0 1 0 1 0 1

0 0 0 0 1 1 A 0 1 1

A 1 0 1 A 1 1 0 1 1 0
L 1 L 2 L 1 L 2 L 1 L 2

A B A B A B

L 2 L 1 L 2 L 1 L 1 L 2
B B B

B B B

AND NAND (OR) OR

Copmplementarity: AND  NAND; Duality: AND  OR

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 20
 Derivation of CPL Logic
Complementarity: AND  NAND

B
B
A 0 1 A B A B A B A B
L 2 L 1
0 0 0
B B

B B
A 1 0 1
L 1 L 2
AND NAND OR NOR
(a) (b) (c)

Duality: AND  OR
NAND  NOR

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 21

 Two-Input Function with balanced
input load
A B B A B A A B

B A B A

B A B A

AND NAND OR NOR

(a) (b)

C in  C drain  C gate

Each input A, B, or A, B has FO=2

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 22
 Derivation of CPL Logic
B
B
A 0 1 A A A A
L 2 L 1
0 0 1
B
B
A 1 1 0
L 1 L 2
XOR XNOR
(a) (b)
(a) XOR function Karnaugh map, (b) XOR/XNOR circuit

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 23

 Synthesis of three-input CPL logic
A C B A C B
BC C L 1 L 2 L 3
A 00 01 11 10
A
L 1
0 0 0 0 0 A
B
L 2
A 1 0 0 1 0 B

L 3
B
AND NAND
(a) (b)

(a) AND function Karnaugh map, (b) AND/NAND circuit

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 24

 Circuit realization of 3-input
AND/NAND function
A C B A C B
BC C
A 00 01 11 10
C A
1

0 0 0 0 0 A

C B
2

A 1 0 0 1 0 B
C 1
C 2
C 3
C 3 B
AND NAND
(a) (b)

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 25

 Double Pass-Transistor Logic (DPL):
Synthesis Rules
1. Two NMOS branches can not be overlapped covering
logic 1s. Similarly, two PMOS branches can not be
overlapped covering logic 0s.

2. Pass signals are expressed in terms of input signals

or supply. Every input vector has to be covered with
exactly two branches.

At any time, excluding transitions, exactly two

transistor branches are active (any of the pairs
NMOS/PMOS, NMOS/NMOS and PMOS/PMOS are
possible), i.e. they both provide output current.

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 26

 Double Pass-Transistor Logic (DPL):
Synthesis Rules
Complementarity Principle: Complementary logic
function in DPL is generated after the following
modifications:

• Exchange PMOS and NMOS devices. Invert all pass

and gate signals

Duality Principle: Dual logic function in DPL is

generated when:

• PMOS and NMOS devices are exchanged, and VDD

and GND signals are exchanged.

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 27

 DPL Synthesis:
B A B A
B
B L 4 L 2
A 0 1
L 3
A B A B
0 0 0
L 4 AND NAND

A 1 0 1 A B
A B
L 3 L 1
L 1 L 2
GND GND +V DD +V DD
(a) (b)

(a) AND function Karnaugh map (b) AND/NAND circuit

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 28

 DPL Synthesis: OR/NOR circuit
+V DD +V DD B A

A B A B

OR NOR

A B A B

B A GND GND

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 29

 XOR/XNOR in DPL

(PMOS) (PMOS)
C 1 B C 2
A A A A
B
A 0 1
B B B B
0 0 1 C C
1 2
C 3 XOR XNOR
(NMOS) C 4 C 3
A 1 1 0 A A A A
C 4
(NMOS)

B B B B

(a) (b)

Circuit realization of 2-input XOR/XNOR

function in DPL, with balanced input load
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 30
 DPL Synthesis: Complementarit
B A B A
y Principle:
B
B
L 4 L 2
Exchange
A 0 1
L 3 PMOS and
A B
0 0 0
A B
NMOS devices.
AND NAND
Invert all pass
L 4
and gate signals
A 1 0 1 A B AND  NAND
A B
L 3 L 1
L 1 L 2
GND GND +V DD +V DD
(a) (b)
AND function Karnaugh map AND/NAND circuit

+V DD +V DD B A
Duality Principle: PMOS
and NMOS devices are
A B A B exchanged, and VDD and
GND signals are
OR NOR exchanged:
AND  OR
A B A B NAND  NOR

B A GND GND

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 31

 DVL Logic
Advantage of CPL and DPL were recognized in DVL which attempts to generalize
pass-transistor networks and minimize the number of transistors and input loads.
Rules:

1. Cover all input vectors that produce “0” at the output, with
largest possible cubes (overlapping allowed) and represent
those cubes with NMOS devices, with sources connected to
GND
2. Repeat step 1 for input vectors that produce “1” at the output
and represent those cubes with PMOS devices, with sources
connected to Vdd
3. Finish with mapping input vectors, not mapped in steps 1 and 2
(overlapping with cubes from steps 1 and 2 allowed) that
produce”0” or “1” at the output. Represent those cubes with
parallel NMOS (good pull-down) and PMOS (good pull-up)
branches, with sources connected to one of the input signals
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 32
 Two input AND/NAND in DVL Logic
( A* )
B A B
B
A 0 1 ( B* )
C 3
B A
0 0 0 C 2
AND NAND
C 3 C 1
A 1 0 1 A B A B

C 1 C 2
V dd V dd

(a) (b)

Circuit realization of 2-input AND/NAND function in DVL

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 33

 Two input OR/NOR in DVL Logic
B A

A B

OR NOR

A B A B

V dd V dd

Circuit realization of 2-input OR/NOR circuit in DVL

XOR/XNOR realization is identical to that of DPL.

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 34

 Three input AND function in DVL
Logic
BC C C
A 00 01 11 10
C 1
0 0 0 0 A A
0

0 0 1 0 A B B B
A 1
C 2 C 1 C 3 C 3
C 3

C B
2 AND
(a) (b)

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 35

 Three input OR/NOR in DVL
V dd C C

A A A A

A B B B A B B B

OR NOR

Circuit realization of 3-input OR/NOR

functions in DVL
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 36
 Comparison
TABLE I. Realizations of 3-input function
F=B’C+ABC’

# of Signal Trans. Output

Realization input termination Count load
signals
CMOS 9 10G 10 4S

DVL (b) 9 8G + 6S 8 6S

DVL (c) 9 7G + 3S 7 4S

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 37

 Comparison
BC C BC C BC C
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10

0 0 1 0 0 0 0 1 0 0 0 0 1 0 0

A 1 0 1 0 1 A 1 0 1 0 1 A 1 0 1 0 1

C B C B C B
2 C 1
1 C 2
C 3
1
C C 3
2

(a) (b) (c)

V dd

A C

A
B
B C B B B
B
B C C F
C
C 1
C 2
C 3
C F B B
C 1
C 2
C 3
C 2
C 1
F B C B
C C C
B C C C C
C B 3 3 2
C

A
A
A B C Realizations of 3-input function F=B’C+ABC’
(a) Standard CMOS, (b) DVL, (c) DVL
F = B C + A B C
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 38
 Conclusion
General rules for synthesizing logic gates in three
representative pass-transistor techniques were
shown.
An algorithmic way for generation of various circuit
topologies (complementary and dual circuits) is
discussed.
Generation of circuits with balanced input loads is
suitable for library based designs is possible if
complementarity and commutative principles are
applied.
This lays the foundation for development of computer
aided design (CAD) tools capable of generating fast
and power-efficient pass-transistor logic.

Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 39