HDL DESPLAZAMIENTO CON SALIDA DE VECTOR:

library ieee; 
use ieee.std_logic_1164.all; 
entity shiftregister is
port(
    Clk, D, Reset, Enable: in std_logic; 
     Q : out std_logic_vector(7 downto 0 )   );
end shiftregister; 

architecture arq_shiftregister of shiftregister is

    signal tmp : std_logic_vector(7 downto 0);  
begin
    process(Clk, Reset)
     begin
      if Reset ='0' then
        tmp<="00000000";
      elsif Clk'event and Clk='1' then  
        if Enable ='1' then
            tmp<= D & tmp(7 downto 1);
        end if;
      end if;
    end process;
    Q<=tmp;
end arq_shiftregister;