IEEE INTERNATIONAL CONFERENCE ON ADVANCES IN E LECTRICAL T ECHNOLOGY F OR GREEN E NERGY 2017 (ICAETGT’ 2 K 17)
Single Bit Hybrid Full Adder Cell by Gate
Diffusion Input and Pass Transistor Logic
Technique
Rishab Goyal
Pursuing M.Tech ECE From
Lovely Professional University
Phagwara, India
Goyalris09@gmail.com
Abstract—In this paper, single bit full adder hybrid
circuit has been proposed which consist of two
techniques i.e. Pass transistor Logic (PTL) and Gate
Diffusion Technique (GDI). Several logic families are
described by PTL which is utilized in the architecture of
integrated circuits. PTL technique is used to decreases
the number of transistors in the circuits to make
different gates of logic by eradicating redundant
transistors. GDI technique is utilized for the low power
consumption. In this paper CADENCE VIRTUOSO tool
is being used and all the simulation work is done on it by
utilizing the technology node at 180nm along with a
supply voltage of 1.8V. The simulation result represents
that the proposed architecture of single bit hybrid full
adder cell absorbs 53% less power in comparison with
hybrid full adder [5], 5% less power in comparison with
3T XNOR [6], 58% less power in comparison with 8T
full adder cell [6] and 86% less power in comparison
with Adder using MDCVSL [8]. As we know that power
and propagation delay both are varying inversely but
still the propagation delay is not affected much and it is
almost similar than the existing designs.
Keywords—Gate Diffusion Input;Pass Transistor Logic;
Hybrid Logic; Average Power Dissipation
I.INTRODUCTION
In today’s era there are two major design issues which we
as a VLSI design engineers are facing i.e. Power
Dissipation and Delay. We can design our circuit by using
various technologies and techniques but there are some
constraints associated with every design technologies
which cannot be neglected. In the applications such as
microprocessor, digital signal processing and image
processing the operations which are commonly used i.e.
Subtraction, Addition, AND and OR.
In Digital Signal Processing application, the perspective
of throughput, latency and delay are the major aspects for
the performance of addition. Most of the adder circuits
not only increases the delay but also dissipates the huge
amount of power. So in the circuit our main focus is to
978-1-5386-2138-7/17/$31.00 ©2017 IEEE
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Sanjeev Sharma
Assistant Professor
Lovely Professional University
Phagwara, India
Sanjeev.15978@lpu.co.in
reduce the power and delay. But we also have to consider
the size of the circuit side by side because in era of
miniaturization, size plays a very significant role in it. If
we trying to reduce the propagation delay, the power
consumption will increase which will further cost high
heat dissipation in the circuit so we have tried to optimize
the circuit in order to achieve low power with almost
similar delay values. So in our proposed design we have
tried to achieve the following three objectives which are
as given below:-
1. Low Power Dissipation
2. Minimum Propagation Delay
3. Small Circuit size
As we know that the immunity of noise and performance
in a circuit both possess behavior of conflicting. Static
complementary metal-oxide semiconductor (CMOS) [1],
dynamic CMOS logic [2], complementary pass transistor
logic (CPL) [3] and transmission gate adder [4] are the
logic architecture which is generally utilized in the
conventional domain. If we want to develop the reliability
in the circuit then we have to waive the performance in
the circuit. So other techniques are also utilized for the
low power absorption and increasing the speed in the
circuit [7]. In the PTL, we can decrease the switching
activity in the circuit by eradicating the glitches. It can
only be done by controlling the lengths and the widths of
each pass transistor. In the PTL, the switching capacitance
of node is less when compared it to the CMOS deigns due
to the less size of the transistors while implementing.
While designing of PTL, there is no static leakage.
There are some important advantages in the Pass
Transistor Logic which are 1) Speed is high 2) Power
dissipation is low 3) interconnection effect is low [8, 9].
In the Pass Transistor Logic, due to the small node
capacitance the speed is high, due to the less number of
transistors the power dissipation is low and due to the
small area the interconnection effect is low. In Pass
Transistor Logic, there are some disadvantages i.e. across
the single channel of pass transistor there is a threshold
loss and at the regenerative inverter the high voltage level
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 IEEE INTERNATIONAL CONFERENCE ON ADVANCES IN E LECTRICAL T ECHNOLOGY F OR GREEN E NERGY 2017 (ICAETGT’ 2 K 17)

is not Vdd. There are also some advantages in the Gate Another design technique is described by B.Sathyabhama
Diffusion Input which are 1) Circuit Design power is less, et al [6] i.e. 3T XNOR Circuit. The 3T XNOR Circuit is
2) Propagation Delay is reduce, 3) Digital Circuit area is the basic building block in various blocks especially
reduce, 4) Complexity of the Circuit is low maintained. Multipliers, Arithmetic Circuit, Comparator, Compressor,
Code Converters, Parity Checkers, DSP Architecture,
In the digital combinational circuit, GDI technique is Phase Detector and microprocessor [10]. The 3T XNOR
utilize for the low power consumption. It is very Circuit is described by using the concept of hybrid CMOS
adjustable for digital circuits. In the Complementary full adder with 8T. It consists of 3 transistors. The Fig. 2
Metal Oxide Semiconductor and the Gate Diffusion represents the schematic of 3T XNOR circuit as shown
Technique, the prime difference is that in the Gate below:-
Diffusion Input Technique the Voltage drain-to drain
source is not attached with the PMOS as well as the
Ground is not attached to the NMOS which makes the
Gate Diffusion Input circuit flexible. There are the some
advantages of GDI technique over CMOS are 1) Power
Circuit Design is less, 2) Propagation Delay is reduced, 3)
Power Consumption is reduced, 4) Area of Digital Circuit
is reduced, 5) Low Complexity of logic design is
maintained. To decrease the number of transistors in a
circuit as well as the low power absorption, many
techniques have been suggested like Hybrid Circuit of
Full adder [5], 3T XNOR Circuit [6], 8T Full Adder
Circuit [6] as well as the MDCVSL [8] which is described
below. Fig. 2. 3T XNOR Circuit

II.EXISTING SYSTEM Using the PTL, 3T XNOR circuit is designed. In the 3T

In last few decades there is significant development in the
scenario of design. The hybrid full adder circuit as
described by Kshitij Shant, et al [5] is the combination of
both PTL as well as the GDI Technique and it consists of
only 10 transistors as shown in Fig. 1.
XNOR circuit, when AB = 00, this make the NMOS
transistor turn OFF and across the transistor PMOS VDD
develops. When AB= 10 or 01, it turns ON the NMOS
transistor and to the output, it passes “0” for both the
cases. When AB= 11, it turns ON the NMOS transistor
and both the transistors PMOS as well NMOS is
generated at the output. In this case, weak “1” is generated
by NMOS and strong “1” is generated by PMOS through
which we get strong ‘0’ at the output.

For Low power consumption another technique is as

described by M.Deepika et al [6] i.e. 8T Full Adder.
Circuit for 8T full adder is represented in the Fig.3.The
Boolean expressions of sum and carry for full adder are:

Sum = ((A+B)"+C)' (1)

Carry = (A.B) + [(A+B)'.C] (2)

Fig. 1. Single bit Hybrid Circuit of Full Adder

While designing both the techniques i.e. Pass Transistor

Logic (PTL) and the Gate Diffusion Input (GDI) the
common problem which we face is the low swing output
because Vdc is not included in both the techniques. On
increasing the supply voltage of input, the characteristics
of hybrid adder also changes. Due to the deficiency of
voltage source (Vdc), the GDI and PTL do not produce
the output of full swing.

Fig. 3. 8T Full Adder Circuit

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 IEEE INTERNATIONAL CONFERENCE ON ADVANCES IN E LECTRICAL T ECHNOLOGY F OR GREEN E NERGY 2017 (ICAETGT’ 2 K 17)
Another design technique is as described by Amit Dubey,
et al [8] for the low power consumption in the circuit i.e.
MDCVSL. It gives better output in terms of propagation
delay, absorption of power, operating frequency, and load
capacitance of output as well as on temperature by adding
two weak P-channel devices. The fig. of MDCVSL is
shown below:-
Fig. 4. Adder Circuit using MDCVSL
In the MDCVSL, the connection of six NMOS and the
four PMOS is done and single addition of supply is
utilized on the circuit for switching. VPULSE is
connected on every input port out of six inputs on which
we find out the fall time, rise time, voltages V1 and V2,
time period and width of pulse and Z and Zb is connected
at the two output port and at the ground port GND is
connected in the circuit. In terms of threshold loss,
MDCVSL gives the better output waveform due to the
transmission gate topology in the architecture. In the
MDCVSL, the two logic trees are efficient of processing
complex functions in a single delay circuit.
III.PRINCIPLE OF OPERATION
A. Approach of the Design Model
In the proposed architecture single bit hybrid full adder
cell is designed and basic approach is to make circuit
which works on less power along with high speed. The
proposed architecture of single bit hybrid full adder cell is
combination of two design techniques i.e. PTL and GDI
Technique. The design basically consists of four sub-
modules as shown in Fig.5.
1. GDI XOR Gate
2. PTL XOR Gate
3. PTL AND Gate
4. GDI OR Gate
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In the GDI XOR Gate, when AB=00, there is a loss in
threshold at the output of the first XOR Gate. Thus the
SUM value is not stable being of assertive power
consumption as well as the contention between the
NMOS and PMOS. When AB are less in logic, this turn
ON the added NMOS transistor and helps to discharge the
node voltage to 0.
Fig. 5. Hybrid 1 bit Full Adder Module
As we know that in the PTL XOR Gate, only PTL
network (either PMOS or NMOS) is ample to execute the
logic operation. It gives good output levels and the
driving capability of the circuit is also increased as it
utilized static CMOS inverter. The main goal of the
circuit is to reduce the unnecessary power consumption
due to the existence of the static CMOS inverter.
When AB=00, the PMOS transistor is ON and NMOS
transistor is OFF and when AB=01, the PMOS transistor
is weak “0” and it pass insufficient logic less signal to the
output. In the above two cases we observed that value of
logic A is constant while the value of logic B changes
from 0 to 1.When AB=10, the PMOS transistor is OFF
and NMOS transistor is ON as well as strong 0, it will
pass the full logic less signal to the output and when
AB=11, the PMOS transistor is OFF and NMOS transistor
is ON and due to NMOS transistor is weak, the output
will be charged due to insufficient high logic.
In the GDI OR Gate, the input is the output of the PTL
AND Gate which gives the Carry expression in the full
adder. In terms of low power absorption and high voltage
of input, the GDI OR Gate gives the improved
performance.
B. Proposed Architecture
To reduce the power absorption, propagation delay,
number of transistors and to develop the flexibility in the
circuit, GDI and PTL technique is used. The proposed
single bit hybrid full adder is implemented by utilizing the
concept of PTL “AND” and “XOR” Gate and Gate
Diffusion Input “XOR” and “OR” which is shown in
Fig.6 and in Fig.7.
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 IEEE INTERNATIONAL CONFERENCE ON ADVANCES IN E LECTRICAL T ECHNOLOGY F OR GREEN E NERGY 2017 (ICAETGT’ 2 K 17)

Fig. 6. Proposed Hybrid Full Adder

The output waveform of hybrid full adder cell is
mentioned. The typical complication in PTL and GDI
technique is that the swing output is less. In terms of
propagation delay as well as the low power consumption,
we have come across that the efficiency of the hybrid full
adder circuit lies between the Gate Diffusion Input (GDI)
and the Pass Transistor Logic (PTL).
On increasing the input voltage supply in the circuit we
noticed that the characteristics of the hybrid adder also
changes and the GDI and the PTL do not produce output
full swing. In the architecture of single bit hybrid full
adder cell when width of PMOS=900nm and width of
NMOS=600nm at supply voltage 1.8V, the power
consumption is 282.84uW.

Fig. 7. Output waveform of Proposed Hybrid Adder Cell

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 IEEE INTERNATIONAL CONFERENCE ON ADVANCES IN E LECTRICAL T ECHNOLOGY F OR GREEN E NERGY 2017 (ICAETGT’ 2 K 17)

IV.SIMULATION RESULT Circuit design Supply Voltage Delay

Modified Hybrid 1.8 1850ps
The simulation is done by CADENCE VIRTUOSO tool. Full Adder
The technology used is CMOS process 180nm
technology.

C. Power Output
The consumption of power between the existing and the
modified circuit is compared and is represented in Table 1
and the hybrid full adder is compared with the width of
1um.

Table I. Comparison of Power Consumption for various

Circuits
Circuit design Supply Power
Voltage Consumption
Hybrid full Adder 1.5V 887.9uW Fig. 9. Graph between Delay vs Supply Voltage at 180 nm
3T XNOR Gate 1.8V 9130uW Technology
8T Full Adder 1.8V 805uW
V.CONCLUSION AND FUTURE SCOPE
Adder using 1.8V ~550uW
MDCVSL
In the paper, different architecture of full adder along with
Modified Hybrid 1.8V 473.982uW
Full Adder different techniques has been implemented. A new circuit
of hybrid has been proposed by the combination of PTL
and GDI is utilized. The proposed single bit hybrid full
adder circuit contains the advantages of both the
techniques. Due to Gate Diffusion Input (GDI) the circuit
process quick while due to Pass Transistor Logic (PTL)
the circuit consumes minimum power and it comes down
with the massive merit in terms of delay product and the
power consumption.

Being utilizing the transistor the hybrid adder is utilized in

performing Multiplier, Subtractor, Compressor as well as
the sequential circuits.

ACKNOWLEDGEMENT
Fig. 8. Graph between Power vs Supply Voltage at 180nm Authors would like to thank all the researchers who have
Technology contributed in this field of research. The comments of
anonymous reviewers to improve the quality of this paper
D. Delay Output are also acknowledged.
In this category we considered the effect on delay of the
full adder at voltage supply of 1.8V. On comparing the REFERENCES
analysis, 180nm technology is utilized to find out the
value of delay and the hybrid full adder is compared with [1]. N. H. E. Weste, D. Harris, and A. Banerjee, CMOS
the width of 1um. The comparison between the modified VLSI Design:A Circuits and Systems Perspective, 3rd
full adder and the existing system is shown in Table 2. ed. Delhi, India India: Pearson Education, 2006.J. Clerk
Maxwell, A Treatise on Electricity and Magnetism, 3rd
Table II Comparison of DELAY for various Circuits ed., vol. 2. Oxford: Clarendon, 1892, pp.68-73.
Circuit design Supply Voltage Delay [2]. J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital
Integrated Circuits: A Design Perspective, 2nd ed. Delhi,
Hybrid full Adder 1.5 1770ps
India::Pearson Education, 2003.K. Elissa, “Title of paper
3T XNOR Gate 1.8 ____ if known,” unpublished.
[3]. D. Radhakrishnan, “Low-Voltage Low-Power CMOS
8T Full Adder 1.8 _____
Full Adder,” IEE Proc.-Circuits Devices Syst., vol. 148,
Adder using 1.8 ~1300ps no. 1, pp.219-214, Feb. 2001.
MDCVSL [4]. R.Zimmermann and W. Fichtner, “Low-Power Logic
Styles: CMOS Versus Pass-Transistor Logic,” IEEE

41

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 IEEE INTERNATIONAL CONFERENCE ON ADVANCES IN E LECTRICAL T ECHNOLOGY F OR GREEN E NERGY 2017 (ICAETGT’ 2 K 17)
J.Solid-State Circuits, vol. 32, no. 7, pp. 1079–1090, Jul.
1997.
[5]. Kshitij Shant1, Rita Mahajan”1-Bit Hybrid Full Adder
by GDI and PTL Technique” at International Journal of
IInnovative Research in Computer and Communication
Engineering Vol. 4, Issue 5, May 2016.
[6]. B. Sathyabhama, M. Deepika, and S. Deepthi “Area and
Power Efficient Carry Select Adder using 8T Full
Adder”IIEEE ICCSP conference Briefs, voI.16, No .6,
2015
[7]. Amit Dubey SachinDubey ShyamAkashe” A Competent
Design 2:1 Multiplexer and Its Application in 1-Bit Full
Adder Cell” at vol issued 978-1-4673-4529-3/12 2012
IEEE
[8]. W. AI-Assadi, A. P.Jayasumana and Y. K.Malaiya,
“Pass-Transistor Logic Design”, International Journal of
Electronics,1991, vol. 70, no. 4, pp. 739-749.
[9]. T.Sakurai, “Closed-form Expressions for Interconnection
Delay,Coupling, and Crosstalk in VLSI’s”, IEEE
Transactions Electron Devices, vol. 40, no. 1, pp. 118-
124,,January 1993.
42
Authorized licensed use limited to: VIT University- Chennai Campus. Downloaded on October 01,2021 at 06:35:22 UTC from IEEE Xplore. Restrictions apply.
[10]. V. Adler, E.G. Friedman, “Delay and Power Expression
for a CMOS Inverter Driving a Resistive-Capacitive
Load”, Analog Integrated Circuits and Signal Processing,
14,1997, pp. 29 39
[11]. C. H. Chang, J. M. Gu, and M. Zhang, “A Review of
0.18-Mm Adder Performances for Tree Structured
Arithmetic Circuits,” IEETrans.Very Large Scale Integr.
(VLSI) Syst., vol.13, no. 6, pp..686–695, Jun. 2005.
[12]. M. Vesterbacka, “A 14-Transistor CMOS Full Adder
with Full Voltage-Swing Nodes,” in Proc. IEEE
Workshop Signal process. Syst. (SiPS), Taipei, Taiwan,
Oct. 1999, pp.713–722.
[13]. Rajeev Kumar,Sanjeev Sharma, Rishab Goyal "A Low
Power Low-Noise Low-Pass Filter for Portable ECG
Detection System”, I J C T A, Vol 9 Issue 41, 2016, pp.
95-103 © International Science Press.