EEN 422: Digital Integrated Circuits, FA 2021

Dr. M. Hamad
HW #1 Orcad Capture Pspice Simulation:
4th Order Equal Component Low Pass RC Active filter

Design a 4th order Equal Component LP RC Active Filter using two stages pf 2 nd order LP and a
cutoff frequency of 450 Hz (f0 = 1/2πRC)

Gain of stage 1: Av1= 1+ Rf1/Ri1 = 1.1523 Gain of stage 2: Av2= 1+ Rf2/Ri2 = 2.2346

Overall Gain: Av = Av1 x Av2 = 2.5749

These are some possible design values for some of the components C= 0.01µF, Rf1 = Rf2 = 10 kΩ,
find the rest of the values (use the closest 5% standard value resistors)

1) Draw the complete circuit (shown in Figure 1 on the next page) with all component values
shown.

2) Simulate your design using Orcad CIS (PSPICE) and display your results using Probe.

- Create a Project, pspice A/D (use uA741 for the op amp and VAC for the input)
- Create a new simulation profile (PSPICE new simulation profile name it choose AC
sweep from analysis type)
- AC Sweep: logarithmic, decade, start freq. 1Hz, end freq. 100 kHz, 10 points/decade.
- Let the input be VAC (Place  part, select VAC from the SOURCE library)
- Label your output node as Vo
- Run you simulation (PSPICE  Run) or click on the blue arrow
- Assuming no errors occurred, you should be in Probe with a black screen
- In Probe, Go to Trace (Add Trace), Type 20log(Vo/Vi) or simply select the DB function on
the right hand side, DB(Vo) to obtain the magnitude vs. frequency plot.
- Change the Y-axis settings appropriately and add a title to it “Magnitude in dB”
- Use the cursor Probe (Trace cursor display) or simply click on the cursor icon to verify
the following:

i) The 3-dB or cutoff frequency (3dB below the DC gain)

ii) The roll-off (80dB/decade)

3) Submit a formal report (Soft Copy) that contains the following items: a cover page, a small
introduction about the topic, theoretical analysis section and a simulation results section, a
comparison table with % error between simulation values and theoretical values, and a brief
conclusion.

You are allowed to work in a team of up to 3 students

Due date: Sept. 8, 2021 at 10 am (Send your Name1-Name2.docx file via email)

Late Assignments are NOT accepted Copied reports are assigned a 0 grade
Table 1. Amplifier Gains for Equal component RC LP and HP Active Filters

Filter Order Stage 1 Stage 2 Stage 3 Overall Gain

Figure 1. A Cascaded design of a 4th order Low Pass equal component RC Active Filter