Chapter - 5

Multivibrator

10.2
MULTIVIBRATORS

Multivibrators are regenerative circuits intended especially for timing applications.

Multivibrators are classified as bistable, astable, and monostable.
In a bistable multivibrator both states are stable, so external commands are
needed to force the circuit to a given state. This is the popular flip-flop, which in turn
takes on different names, depending on the way in which the external commands
are effected.
 492 An astable multivibrator toggles spontaneously between one state and the other,
CHAPTER 10 without any external commands. Also called a free-running multivibrator, its timing
Signal Generators is set by a suitable network, usually comprising a capacitor or a quartz crystal.
A monostable multivibrator, also called a one-shot, is stable only in one of its
two states. If forced into the other state via an external command called a trigger, it
returns to its stable state spontaneously, after a delay set by a suitable timing network.
Here we are interested in astable and monostable multivibrators. These circuits
are implemented with voltage comparators or with logic gates, especially CMOS
gates.

Basic Free-Running Multivibrator

In the circuit of Fig. 10.7a, the 301 op amp comparator and the positive-feedback
resistances R1 and R2 form an inverting Schmitt trigger. Assuming symmetric output
saturation at ±Vsat = ±13 V, the Schmitt-trigger thresholds are also symmetric at
±VT = ±Vsat R1 /(R1 + R2 ) = ±5 V. The signal to the inverting input is provided
by the op amp itself via the RC network.
At power turn-on (t = 0) v O will swing either to +Vsat or to −Vsat , since these
are the only stable states admitted by the Schmitt trigger. Assume it swings to
+Vsat , so that v P = +VT . This will cause R to charge C toward Vsat , leading to an
exponential rise in v N with the time constant τ = RC. As soon as v N catches up with
v P = VT , v O snaps to −Vsat , reversing the capacitance current and also causing v P
to snap to −VT . So, now v N decays exponentially toward −Vsat until it catches up
with v P = −VT , at which point v O again snaps to +Vsat , thus repeating the cycle.
It is apparent that once powered, the circuit has the ability to start and then sustain
oscillation, with v O snapping back and forth between +Vsat and −Vsat , and v N
slewing exponentially back and forth between +VT and −VT . After the power-on
cycle, the waveforms become periodic.
We are interested in the frequency of oscillation, which is found from the period
T as f 0 = 1/T . Thanks to the symmetry of the saturation levels, v O has a duty cycle
of 50%, so we only need to find T /2. Applying Eq. (10.3) with t = T /2, τ = RC,

Volts
vO
C vN R Vsat

– VT
vN
301 vO
+ 0 t
R2 16 kΩ 0
vP –VT

R1 10 kΩ
–Vsat
T

(a) (b)

FIGURE 10.7
Basic free-running multivibrator.
V∞ = Vsat , V0 = −VT , and V1 = +VT , we get 493
T Vsat + VT SECTION 10.2
= RC ln Multivibrators
2 Vsat − VT
Substituting VT = Vsat /(1 + R2 /R1 ) and simplifying finally gives
1 1
f0 = = (10.9)
T 2RC ln(1 + 2R1 /R2 )
With the components shown, f 0 = 1/(1.62RC). If we use the ratio R1 /R2 = 0.859,
then f 0 = 1/(2RC).
We observe that f 0 depends only on the external components. In particular, it
is unaffected by Vsat , which is known to be an ill-defined parameter since it varies
from one op amp to another and also depends on the supply voltages. Any variation
in Vsat will cause VT to vary in proportion, thus ensuring the same transition time
and, hence, the same oscillation frequency.
The maximum operating frequency is determined by the comparator speed.
With the 301 op amp as a comparator, the circuit yields a reasonably good square
wave up to the 10-kHz range. This can be extended significantly by using a faster
device. At higher frequencies, however, the stray capacitance of the noninverting
input toward ground becomes a limiting factor. This can be compensated by using a
suitable capacitance in parallel with R2 .
The lowest operating frequency depends on the practical upper limits of R and
C, as well as the net leakage at the inverting input node. FET-input comparators may
be a good choice in this case.
Although f 0 is unaffected by uncertainties in Vsat , it is often desirable to stabilize
the output levels for a cleaner and more predictable square-wave amplitude. This is
readily achieved with a suitable voltage-clamping network. If it is desired to vary
f 0 , a convenient approach is to use an array of decade capacitances and a rotary
switch for decade selection, and a variable resistance for continuous tuning within
the selected decade.
E X A M P L E 10.1. Design a square-wave generator meeting the following specifications:
(a) f 0 must be variable in decade steps from 1 Hz to 10 kHz; (b) f 0 must be variable con-
tinuously within each decade interval; (c) amplitude must be ±5 V, stabilized. Assume
±15-V poorly regulated supplies.
Solution. To ensure stable ±5 V output levels, use a diode-bridge clamp as in Fig. 10.8.
When the op amp saturates at +13 V, current flows through the path R3 -D1 -D5 -D4 , thus
clamping v O at VD1(on) + VZ 5 + VD4(on) . To clamp at 5 V, use VZ 5 = 5 − 2VD(on) =
5 − 2 × 0.7 = 3.6 V. When the op amp saturates at −13 V, current flows through the
path D3 -D5 -D2 -R3 , clamping v O at −5 V.
To vary f 0 in decade steps, use the four capacitances and rotary switch shown.
To vary f 0 within a given decade, implement R with a pot. To cope with component
tolerances, ensure an adequate amount of overlap between adjacent decade intervals.
To be on the safe side, impose a range of continuous variability from 0.5 to 20, that
is, over a 40-to-1 range. We then have Rpot + Rs = 40Rs , or Rpot = 39Rs . To keep
input-bias-current errors low, impose I R(min) I B , say, I R(min) = 10 μA. Moreover,
let R1 = R2 = 33 k, so that VT = 2.5 V. Then, Rmax = (5 − 2.5)/(10 × 10−6 ) =
250 k. Since Rs
Rpot , use a 250-k pot. Then, Rs = 250/39 = 6.4 k (use
6.2 k).
 494 R
CHAPTER 10 C1 Rs
Signal Generators
μ
3.3 nF 6.2 kΩ 250 kΩ
C2 R4
– R3
0.33 μ
nF 10 kΩ 301 vO
+ 2.2 kΩ
C3 R2

33 nF R1 33 kΩ
C4 33 kΩ D1 D2
D5
3.3 nF
D3 D4

FIGURE 10.8
Square-wave generator of Example 10.1.

To find C1 , impose f 0 = 0.5 Hz with the pot set to its maximum value. By Eq. (10.9),
C1 = 1/[2 × 0.5 × (250 + 6.2) × 103 × ln 3] = 3.47 μF. The closest standard value is
C1 = 3.3 μF. Then, C2 = 0.33 μF, C3 = 33 nF, and C4 = 3.3 nF.
The function of R4 is to protect the comparator input stage at power turn-off, when
the capacitors may still be charged, and that of R3 is to supply current to the bridge, R2 ,
R, and to the external load, if any. The maximum current drawn by R is when v O = +5 V,
v N = −2.5 V, and the pot is set to zero. This current is [5 − (−2.5)]/6.2 = 1.2 mA. We
also have I R2 = 5/66 = 0.07 mA. Imposing a bridge current of 1 mA and allowing for
a maximum load current of 1 mA, we have I R3 (max) = 1.2 + 0.07 + 1 + 1 ∼ = 3.3 mA.
Hence, R3 = (13 − 5)/3.3 = 2.4 k (use 2.2 k to be safe). For the diode bridge use
a CA3039 array.

Figure 10.9 shows a multivibrator designed for single-supply operation. By using

a fast comparator, the circuit can operate well into the hundreds of kilohertz. As we
know, the circuit gives VOL ∼= 0 and, if R4
R3 + (R1  R2 ), it gives VOH ∼ = VCC .
At power turn-on (t = 0), when C is still discharged, v O is forced high, causing C
to charge toward VCC via R. As soon as v N reaches VTH , v O snaps low, causing C
to discharge toward ground. Henceforth, the oscillation becomes periodic with duty
cycle D(%) = 100TH /(TL + TH ) and f 0 = 1/(TL + TH ). Applying Eq. (10.3)
twice, first with t = TL , V∞ = 0, V0 = VTH , and V1 = VTL , then with t = TH ,
V∞ = VCC , V0 = VTL , and V1 = VTH , we get, after combining terms,
1
f0 =   (10.10)
VTH VCC − VTL
RC ln ×
VTL VCC − VTH
To simply inventory and achieve D = 50%, it is customary to impose R1 =
R2 = R3 , after which f 0 = 1/(RC ln 4) = 1/1.39RC. Oscillators of this type can
easily achieve stabilities approaching 0.1% with initial predictability of the order of
5% to 10%.
 VCC 495
C vN R SECTION 10.2
Multivibrators
3
– 8 R4
311 7
vO Volts
2 vO
+ 1 VCC
4
R2 VTH
VCC vN
R3 VTL
R1
0 t
0 TL TH

(a) (b)

FIGURE 10.9
Single-supply free-running multivibrator.

E X A M P L E 10.2. In the circuit of Fig. 10.9 specify components for f 0 = 1 kHz, and
verify with PSpice for VCC = 5 V.
Solution. Use R1 = R2 = R3 = 33 k, R4 = 2.2 k, C = 10 nF, and R = 73.2 k.
Using the PSpice circuit of Fig. 10.10a, we readily obtain the waveforms of Fig. 10.10b.
Cursor measurements give T = 1.002 ms, or f 0 = 998 Hz.

Free-Running Multivibrator Using CMOS Gates

CMOS logic gates are particularly attractive when analog and digital functions must
coexist on the same chip. A CMOS gate enjoys an extremely high input impedance,
a rail-to-rail input range and output swing, extremely low power consumption, and

VCC (+5 V)
R2
5V
33 kΩ R3 vO
R4
33 kΩ 2.2 kΩ
R1
2 8
+ 2.5 V
7 vN
33 kΩ LM311 vO
0 3
vN –
4 1

C R 0 0
0 0.5 1 1.5 2 2.5
10 nF 73.2 kΩ
0 Time (ms)

(a) (b)

FIGURE 10.10
(a) Free-running multivibrator of Example 10.2, and (b) waveforms.
 496 VDD
D1
CHAPTER 10
vO
Signal Generators VDD
Mp
VDD
vI vO vI vO

Mn
0 vI
0 VT VDD

D2

(a) (b) (c)

FIGURE 10.11
CMOS inverter: logic symbol, internal circuit diagram, and VTC.

the speed and low cost of logic circuitry. The simplest gate is the inverter depicted in
Fig. 10.11. This gate can be regarded as an inverting-type threshold detector giving
v O = VOH = VDD for v I < VT , and v O = VOL = 0 for v I > VT . The threshold
VT is the result of internal transistor operation, and it is nominally halfway between
VDD and 0, or VT ∼ = VDD /2. The protective diodes, normally in cutoff, prevent v I
from rising above VDD + V D(on) or dropping below −V D(on) , and thus protect the
FETs against possible electrostatic discharge.
In the circuit of Fig. 10.12a assume at power turn-on (t = 0) v2 goes high. Then,
by I2 ’s inverting action, v O remains low, and C starts charging toward v2 = VDD
via R. The ensuing exponential rise is conveyed to I1 via R1 as signal v1 . As soon as

v2
VDD

0 t
0
v3
VT + VDD
VDD
VT
VDD VDD 0 t
VT – VDD 0
v1 v2
I1 I2 vO
vO
R VDD

R1 ( >> R) v3 0 t
C 0 TH TL

(a) (b)

FIGURE 10.12
CMOS-gate free-running multivibrator.
v1 rises to VT , I1 changes state and pulls v2 low, forcing I2 to pull v O high. Since 497
the voltage across C cannot change instantaneously, the step change in v O causes v3 SECTION 10.2
to change from VT to VT + VDD ∼ = 1.5VDD , as shown in the timing diagram. These Multivibrators
changes occur by a snapping action similar to that of Schmitt triggers.
With v3 being high and v2 being low, C will now discharge toward v2 = 0 via
R. As soon as the value of v3 decays to VT , the circuit snaps back to the previous
state; that is, v2 goes high and v O goes low. The step change in v O causes v3 to
jump from VT to VT − VDD ∼ = −0.5VDD , after which v3 will again charge toward
v2 = VDD . As shown, v2 and v O snap back and forth between 0 and VDD , but in
antiphase, and they snap each time v3 reaches VT .
To find f 0 = 1/(TH +TL ), we again use Eq. (10.3), first with t = TH , V∞ = 0,
V0 = VT + VDD , and V1 = VT , then with t = TL , V∞ = VDD , V0 = VT − VDD ,
and V1 = VT . The result is
1
f0 =   (10.11)
VDD + VT 2VDD − VT
RC ln ×
VT VDD − VT
For VT = VDD /2 we get f 0 = 1/(RC ln 9) = 1/2.2RC and D(%) = 50%. In practice,
due to production variations, there is a spread in the values of VT . This, in turn,
affects f 0 , thus limiting the circuit to applications where frequency accuracy is not
of primary concern.
We observe that if v3 were applied to I1 directly, the input protective diodes of
I1 would clamp v3 and alter the timing significantly. This is avoided by using the
decoupling resistance R1 R (in practice, R1 ∼ = 10R will suffice).

CMOS Crystal Oscillator

In precise timekeeping applications, frequency must be much more accurate and

stable than that afforded by simple RC oscillators. These demands are met with
crystal oscillators, an example of which is shown in Fig. 10.13. Since the circuit
exploits the electromechanical-resonance characteristics3 of a quartz crystal to set
f 0 , it acts more like a tuned amplifier than a multivibrator. The idea here is to

Xtal

1 MHz
Rf

10 MΩ
R1
I
C2 2 kΩ C1
10 pF vO 10 pF

FIGURE 10.13
CMOS-gate crystal oscillator.
 498 place a network that includes a crystal in the feedback loop of a high-gain inverting
CHAPTER 10 amplifier. This network routes a portion of the output signal back to the input, where
Signal Generators it is reamplified in such a way as to sustain oscillation at a frequency set by the
crystal.
A CMOS gate is made to operate as a high-gain amplifier by biasing it near
the center of its VTC, where slope is the steepest and gain is thus maximized.
Using a plain feedback resistance R f , as shown, establishes the dc operating point
at VO = VI = VT ∼ = VDD /2. Thanks to the extremely low input leakage current of
CMOS gates, R f can be made quite large. The function of the remaining components
is to help establish the proper loss and phase, as well as provide a low-pass filter
action to discourage oscillation at the crystal’s higher harmonics.
Although crystals have to be ordered for specific frequencies, a number of
commonly used units are available off the shelf, namely, 32.768 kHz crystals for
digital wristwatches, 3.579545 MHz for TV tuners, and 100 kHz, 1 MHz, 2 MHz,
4 MHz, 5 MHz, 10 MHz, etc., for digital clock applications. A crystal oscillator can
be tuned slightly by varying one of its capacitances, as shown. Crystal oscillators of
the type shown can easily achieve stabilities on the order of 1 ppm/◦ C (1 part-per-
million per degree Celsius).4
The duty cycle of clock generators is not necessarily 50%. Applications requiring
perfect square-wave symmetry are easily accommodated by feeding the oscillator
to a toggle flip-flop. The latter then produces a square wave with D(%) = 50%,
but with half the frequency of the oscillator. To achieve the desired frequency, we
simply use a crystal with a frequency rating twice as high.

Monostable Multivibrator

On receiving a trigger pulse at the input, a monostable multivibrator or one-shot

produces a pulse of a specified duration T. This duration can be generated digitally,
by counting a specified number of pulses from a clock source, or in analog fashion,
by using a capacitor for time-out control. One-shots are used to generate strobe
commands and delays, and in switch debouncing.
The circuit of Fig. 10.14 uses a NOR gate G and an inverter I. The NOR yields
a high output only when both inputs are low; if at least one of the inputs is high,
the output will be low. Under normal conditions, v I is low and C is in steady state,
so v2 = VDD due to the pullup action by R, and v O = 0 by inverter action. Further,
since both inputs to the NOR gate are low, its output is high, or v1 = VDD , indicating
zero voltage across C.
The arrival of a trigger pulse v I causes the NOR gate to pull v1 low. Since the
voltage across C cannot change instantaneously, v2 will also go low, causing in turn
v O to go high. Even if the trigger pulse is now deactivated, the NOR gate will keep v1
low because v O is high. This state of affairs, however, cannot last indefinitely because
R is now charging C toward VDD . In fact, as soon as v2 reaches VT , the inverter snaps,
forcing v O back low. In response to this, the NOR gate forces v1 high, and C then
transmits this step to the inverter, thus reinforcing its initial snap in Schmitt-trigger
fashion. Even though v2 tries to swing from VT to VT + VDD ∼ = 1.5VDD , the internal
protective diode D1 of the inverter, shown explicitly in Fig. 10.11b, will clamp v2
near VDD , thus discharging C. The circuit is now back in the stable state preceding
 vI 499
VDD SECTION 10.3
0 t Monolithic Timers
v1
VDD
VDD
0 t

v2
R VDD
VT
C
G I vO 0 t
vI + v1 v2
vO
VDD
0 t
T

(a) (b)

FIGURE 10.14
CMOS-gate one-shot.

the arrival of the trigger pulse. The timeout T is found via Eq. (10.3) as
VDD
T = RC ln (10.12)
VDD − VT
For VT = VDD /2, this reduces to T = RC ln 2 = 0.69RC.
A retriggerable one-shot begins a new cycle each time the trigger is activated,
including activation during T. By contrast, a nonretriggerable one-shot is insensitive
to triggering during T.

10.3
MONOLITHIC TIMERS

The need for the astable and monostable functions arises so often that special
circuits,4 called IC timers, are available to satisfy these needs. Among the vari-
ety of available products, the one that has gained the widest acceptance in terms
of cost and versatility is the 555 timer. Another popular product is the 2240 timer,
which combines a timer with a programmable counter to provide additional timing
flexibility.

The 555 Timer

As shown in Fig. 10.15, the basic blocks of the 555 timer are: (a) a trio of identical re-
sistors, (b) a pair of voltage comparators, (c) a flip-flop, and (d) a BJT switch QO . The
resistances set the comparator thresholds at VTH = (2/3)VCC and VTL = (1/3)VCC .
For additional flexibility, the upper threshold node is externally accessible via pin 5
so that the user can modulate the value of VTH . Regardless of the value of VTH , we
always have VTL = VTH /2.