5 4 3 2 1

PCB Number: 14085-1 BOM Configuration PCB BOARD SIZE

ECO# number: 825661 (R):Unmount 6 Layers
155mm x 285.7mm
PAGE TITLE Quantity (G):GPU
01 Cover Page (U):UMA A00 BUILD
02 Block Diagram
03 Reserved (D):Debug used INTEL Braswell Platform
D 04 Reserved LAN: RTL8111H D

05 CPU_(DDR)
06 Reserved AUDIO: ALC3600
07 CPU_(VCC_CORE) SIO: IT8617E
08 CPU_(DDI/EDP)
PAGE TITLE Quantity
09 CPU_(VSS)
59 Reserved
10 CPU_(POWER CAP1)
60 HDD/ODD
11 CPU_(POWER CAP2)
61 NGFF CONN
12 DDR3_SODIMM1
62 Reserved
13 Reserved
63 Reserved
14 Reserved
64 LED/POWER BUTTON
15 CPU_(STRAP)
65 Reserved
16 CPU_(USB/UART/GPIO)
66 Reserved
17 CPU (GPIO/STRAP/I2C/SMB)
67 Reserved
18 CPU_(LPC/SIDEBAND/JTAG)
68 DEBUG CONNECTOR
19 CPU_(CLK/SATA/PCIE/SPI/HDA)
69 Reserved
20 Reserved
70 Reserved
21 CPU_(POWER1)
C 71 Reserved C
22 Reserved
72 Reserved
23 Reserved
73 Reserved
24 SIO_IT8617E
74 Reserved
25 FLASH ROM/RTC
75 Reserved
26 FAN CIRCURTS/HOLE
76 GPU_MARS_PCIE
27 AUDIO ALC3600
77 GPU_MARS_I/O
28 Reserved
78 GPU_MARS_MEMORY
29 AUDIO JACK
79 GPU_MARS_STRAP
30 Reserved
80 GPU_MARS_PWR/GND
31 LAN_RTL8111H
81 VRAM1,2(1/2)
32 RJ45+USB2.0
82 VRAM3,4(2/2)
33 RTS5170+CARD READER
83 Reserved
34 USB2.0 CONN(REAR)
84 Reserved
35 USB3.0 CONN(FRONT)
85 GPU_POWER CORE_(ISL62882C)
36 Reserved
86 GPU_POWER 0D95V/1D8V
37 USB HUB GPU_POWER 3D3V/1D35V
38 Reserved 87
88 Reserved
B
39 PWROK B

89 Reserved
40 RUN PWR
90 Reserved
41 DSW_POWER_CTL
91 Reserved
42 DCIN JACK
92 LEVEL SHIFT
43 PWR_12V_(NCP1589A)
93 Reserved
44 3D3V/5V_(RT8243A)
94 Reserved
45 VCC0/VCC1_(NCP81201)
95 Reserved
46 VGG_(NCP81201)
96 Reserved
47 0D95V_S5_(RT6220A)
97 Reserved
48 V_SM/ V_SMVTT_(RT8207M)
98 Reserved
49 1P05V_S5_(RT8237C)
99 CPU_XDP
50 1P15V_S5_(RT8068A) 100 Reserved
51 1D24V_S5_(APL5930)
101 Reserved
52 1D8V_S5_(RT8068A) 102 Power Sequence
53 1D5V_S0_(APL5930)
SVID 103 Power Block Diagram
54 Power Good & Reset Diagram
55 DP TO VGA_(RTD2168) 104
105 Clock Diagram
A
56 HDMI CONN A

57 Reserved
58 Reserved <Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
Cover Page
Size Document Number Rev
Custom Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 1 of 105
5 4 3 2 1
 5 4 3 2 1

Project Name: Tahoe SOC SFF/Lily SFF

Project Code: 3PD03C010001/3PD03D010001 PCB BOARD SIZE
PCB Version: -1 6 Layer
PCB Number: 14085 Internal Slot/Header
PCB certificaion number: LT1119 Front/Rear IO
D D

Chipset

HDMI(UMA)
Level DDI0 1.35V
(Rear) HDMI CONN Shift DDR3L CHA DDR3 SODIMM 204 PIN
HDMI(GPU) Intel CPU
PCIEx1 LAN RTL8111H RJ45 w/ USBx2 CONN (Rear)
PS8407 DPA(GPU)
AMD GPU 25W PCIEx2 Braswell
Mars LE (S3) FCBGA1170 Port2,3
USB2.0
DDI1(UMA) TDP: 6W
USB3.0 Port0
DPB(GPU) Package USB3F1 (Front)
27*25*1.4 USB2.0 Port0
C C

(Rear) VGA CONN RGB RTD2168 USB3.0 Port1

USB2.0 Port1 Resisters

HDD SATA3.0 ETHERNET (10/100/1000Mb)

TPS2546 USB
USB 3.0/2.0 ports (4/5)
High Definition Audio
CHARGER
USB3F2 (Front)
SATA ports (2)
ODD SATA3.0 PCIe ports (4)
LPC I/F
USB2.0 Port4 U2x2 USB2.0x2 CONN (Rear)
USB HUB GL850G

8MB SPI ROM SPI U2x1 RTS5170 SD 3.0 SD Card CONN (Front)
B B

U2X1
NGFF CONN
PCIEx1

PCB DELL P/N:

Azalia 1R2V6$EA VICTORYGIA
SIO IT8617E LPC 1R2V6$FA GECS
1R2V6$HA GLOBALBRAN
ALC3600 1R2V6$IA WUZHU GPU DELL P/N: 3PK94
N3700 DELL P/N: 63DMW Micron VRAM DELL P/N: PP8TP
A
N3150 DELL P/N: C12KP Samsung VRAM DELL P/N: 53DCX A

CPU FAN CTIA (Apple) N3050 DELL P/N: 63DMW SKhynix VRAM DELL P/N: W5PXV
Standard Headset <Variant Name>

(Front) Line in Line out Mic in Wistron Incorporated

21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
(Rear) (Rear) (Rear) Size
Block Diagram
Document Number Rev
C Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 2 of 105
5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 3 of 105

5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 4 of 105

5 4 3 2 1
 5 4 3 2 1

CPU1A 1 OF 13 CPU1B 2 OF 13
[12] M_DQS_A_DP[0..7]
[12] M_MAA_A[0..15] M_MAA_A15 BD49 BRASWELL BD5 DDR1
M_DQS_A_DP7 M_MAA_A14 DDR3_M0_MA_15 M_DATA_A63 M_DATA_A[0..63] [12] DDR3_M1_MA_15 BRASWELL
BD47 BG33 BD7 BG21
M_DQS_A_DP6 M_MAA_A13 BF44 DDR3_M0_MA_14 DDR3_M0_DQ_63 BH28 M_DATA_A62 BF10 DDR3_M1_MA_14 DDR3_M1_DQ_63 BH26
DDR0
M_DQS_A_DP5 M_MAA_A12 BF48 DDR3_M0_MA_13 DDR3_M0_DQ_62 BJ29 M_DATA_A61 BF6 DDR3_M1_MA_13 DDR3_M1_DQ_62 BJ25
M_DQS_A_DP4 M_MAA_A11 BB49 DDR3_M0_MA_12 DDR3_M0_DQ_61 BG28 M_DATA_A60 BB5 DDR3_M1_MA_12 DDR3_M1_DQ_61 BG26
M_DQS_A_DP3 M_MAA_A10 BJ45 DDR3_M0_MA_11 DDR3_M0_DQ_60 BG32 M_DATA_A59 BJ9 DDR3_M1_MA_11 DDR3_M1_DQ_60 BG22
M_DQS_A_DP2 M_MAA_A9 BE52 DDR3_M0_MA_10 DDR3_M0_DQ_59 BH34 M_DATA_A58 BE2 DDR3_M1_MA_10 DDR3_M1_DQ_59 BH20
M_DQS_A_DP1 M_MAA_A8 BD44 DDR3_M0_MA_9 DDR3_M0_DQ_58 BG29 M_DATA_A57 BD10 DDR3_M1_MA_9 DDR3_M1_DQ_58 BG25
M_DQS_A_DP0 M_MAA_A7 BE46 DDR3_M0_MA_8 DDR3_M0_DQ_57 BJ33 M_DATA_A56 BE8 DDR3_M1_MA_8 DDR3_M1_DQ_57 BJ21
M_MAA_A6 BB46 DDR3_M0_MA_7 DDR3_M0_DQ_56 BB8 DDR3_M1_MA_7 DDR3_M1_DQ_56
M_MAA_A5 BH48 DDR3_M0_MA_6 BD28 M_DATA_A55 BH6 DDR3_M1_MA_6 BD26
M_MAA_A4 BD42 DDR3_M0_MA_5 DDR3_M0_DQ_55 BF30 M_DATA_A54 BD12 DDR3_M1_MA_5 DDR3_M1_DQ_55 BF24
D [12] M_DQS_A_DN[0..7] M_MAA_A3 DDR3_M0_MA_4 DDR3_M0_DQ_54 M_DATA_A53 DDR3_M1_MA_4 DDR3_M1_DQ_54 D
BH47 BA34 BH7 BA20
M_DQS_A_DN7 M_MAA_A2 BJ48 DDR3_M0_MA_3 DDR3_M0_DQ_53 BD34 M_DATA_A52 BJ6 DDR3_M1_MA_3 DDR3_M1_DQ_53 BD20
M_DQS_A_DN6 M_MAA_A1 BC42 DDR3_M0_MA_2 DDR3_M0_DQ_52 BD30 M_DATA_A51 BC12 DDR3_M1_MA_2 DDR3_M1_DQ_52 BD24
M_DQS_A_DN5 M_MAA_A0 BB47 DDR3_M0_MA_1 DDR3_M0_DQ_51 BA32 M_DATA_A50 BB7 DDR3_M1_MA_1 DDR3_M1_DQ_51 BA22
M_DQS_A_DN4 DDR3_M0_MA_0 DDR3_M0_DQ_50 BC34 M_DATA_A49 DDR3_M1_MA_0 DDR3_M1_DQ_50 BC20
M_DQS_A_DN3 BF52 DDR3_M0_DQ_49 BF34 M_DATA_A48 BF2 DDR3_M1_DQ_49 BF20
M_DQS_A_DN2 [12] M_SBS_A2 AY40 DDR3_M0_BS_2 DDR3_M0_DQ_48 AY14 DDR3_M1_BS_2 DDR3_M1_DQ_48
M_DQS_A_DN1 [12] M_SBS_A1 DDR3_M0_BS_1 M_DATA_A47 DDR3_M1_BS_1
BH46 AV32 BH8 AV22
M_DQS_A_DN0 [12] M_SBS_A0 DDR3_M0_BS_0 DDR3_M0_DQ_47 AV34 M_DATA_A46 DDR3_M1_BS_0 DDR3_M1_DQ_47 AV20
BG45 DDR3_M0_DQ_46 BD36 M_DATA_A45 BG9 DDR3_M1_DQ_46 BD18
[12] M_CAS_A_N BA40 DDR3_M0_CAS# DDR3_M0_DQ_45 BF36 M_DATA_A44 BA14 DDR3_M1_CAS# DDR3_M1_DQ_45 BF18
[12] M_RAS_A_N BH44 DDR3_M0_RAS# DDR3_M0_DQ_44 AU32 M_DATA_A43 BH10 DDR3_M1_RAS# DDR3_M1_DQ_44 AU22
[12] M_WE_A_N AU38 DDR3_M0_WE# DDR3_M0_DQ_43 AU34 M_DATA_A42 AU16 DDR3_M1_WE# DDR3_M1_DQ_43 AU20
[12] M_SCS_A_N1 AY38 DDR3_M0_CS1# DDR3_M0_DQ_42 BA36 M_DATA_A41 AY16 DDR3_M1_CS1# DDR3_M1_DQ_42 BA18
[12] M_SCS_A_N0 DDR3_M0_CS0# DDR3_M0_DQ_41 BC36 M_DATA_A40 DDR3_M1_CS0# DDR3_M1_DQ_41 BC18
BD38 DDR3_M0_DQ_40 BD16 DDR3_M1_DQ_40
[12] CK_M_DDR1_A_DP BF38 DDR3_M0_CK_1 BH38 M_DATA_A39 BF16 DDR3_M1_CK_1 BH16
[12] CK_M_DDR1_A_DN AY42 DDR3_M0_CK_1# DDR3_M0_DQ_39 BH36 M_DATA_A38 AY12 DDR3_M1_CK_1# DDR3_M1_DQ_39 BH18
[12] M_SCKE_A1 DDR3_M0_CKE_1 DDR3_M0_DQ_38 BJ41 M_DATA_A37 DDR3_M1_CKE_1 DDR3_M1_DQ_38 BJ13
BD40 DDR3_M0_DQ_37 BH42 M_DATA_A36 BD14 DDR3_M1_DQ_37 BH12
[12] CK_M_DDR0_A_DP BF40 DDR3_M0_CK_0 DDR3_M0_DQ_36 BJ37 M_DATA_A35 BF14 DDR3_M1_CK_0 DDR3_M1_DQ_36 BJ17
[12] CK_M_DDR0_A_DN BB44 DDR3_M0_CK_0# DDR3_M0_DQ_35 BG37 M_DATA_A34 BB10 DDR3_M1_CK_0# DDR3_M1_DQ_35 BG17
[12] M_SCKE_A0 DDR3_M0_CKE_0 DDR3_M0_DQ_34 BG43 M_DATA_A33 DDR3_M1_CKE_0 DDR3_M1_DQ_34 BG11
AT30 DDR3_M0_DQ_33 BG42 M_DATA_A32 AT24 DDR3_M1_DQ_33 BG12
AU30 RSVD#AT30 DDR3_M0_DQ_32 AU24 RSVD#AT24 DDR3_M1_DQ_32
RSVD#AU30 BB51 M_DATA_A31 RSVD#AU24 BB3
AV36 DDR3_M0_DQ_31 AW53 M_DATA_A30 AV18 DDR3_M1_DQ_31 AW1
[12] M_ODT_A0 BA38 DDR3_M0_ODT_0 DDR3_M0_DQ_30 BC52 M_DATA_A29 BA16 DDR3_M1_ODT_0 DDR3_M1_DQ_30 BC2
[12] M_ODT_A1 DDR3_M0_ODT_1 DDR3_M0_DQ_29 AW51 M_DATA_A28 DDR3_M1_ODT_1 DDR3_M1_DQ_29 AW3
DDR3_VREF_CA AT28 DDR3_M0_DQ_28 AV51 M_DATA_A27 AT26 DDR3_M1_DQ_28 AV3
DDR3_VREF_CA DDR3_VREF_DQ DDR3_M0_OCAVREF DDR3_M0_DQ_27 M_DATA_A26 DDR3_M1_OCAVREF DDR3_M1_DQ_27
AU28 BC53 AU26 BC1
DDR3_VREF_DQ DDR3_M0_ODQVREF DDR3_M0_DQ_26 M_DATA_A25 DDR3_M1_ODQVREF DDR3_M1_DQ_26
AV52 AV2
BA42 DDR3_M0_DQ_25 BD52 M_DATA_A24 BA12 DDR3_M1_DQ_25 BD2
[12] DDR3_DRAMRST_N AV28 DDR3_M0_DRAMRST# DDR3_M0_DQ_24 AV26 DDR3_M1_DRAMRST# DDR3_M1_DQ_24
[39] DDR3_DRAM_PWROK DDR3_DRAM_PWROK AV42 M_DATA_A23 [39] DDR3_VCCA_PWRGD DDR3_VCCA_PWROK AV12
DRAM_RCOMP_0 BA28 DDR3_M0_DQ_23 AP41 M_DATA_A22 SM_RCOMP_1 BA26 DDR3_M1_DQ_23 AP13
DDR3_M0_RCOMPPD DDR3_M0_DQ_22 AV41 M_DATA_A21 DDR3_M1_RCOMPPD DDR3_M1_DQ_22 AV13
[12] M_MA_DM[7..0] M_MA_DM7 DDR3_M0_DQ_21 M_DATA_A20 DDR3_M1_DQ_21
C BH30 AT44 BH24 AT10 C
M_MA_DM6 BD32 DDR3_M0_DM_7 DDR3_M0_DQ_20 AP40 M_DATA_A19 BD22 DDR3_M1_DM_7 DDR3_M1_DQ_20 AP14
M_MA_DM5 AY36 DDR3_M0_DM_6 DDR3_M0_DQ_19 AT38 M_DATA_A18 AY18 DDR3_M1_DM_6 DDR3_M1_DQ_19 AT16
M_MA_DM4 BG41 DDR3_M0_DM_5 DDR3_M0_DQ_18 AP42 M_DATA_A17 BG13 DDR3_M1_DM_5 DDR3_M1_DQ_18 AP12
C576 (R_) M_MA_DM3 BA53 DDR3_M0_DM_4 DDR3_M0_DQ_17 AT40 M_DATA_A16 BA1 DDR3_M1_DM_4 DDR3_M1_DQ_17 AT14
1 2 DDR3_DRAMRST_N M_MA_DM2 AP44 DDR3_M0_DM_3 DDR3_M0_DQ_16 AP10 DDR3_M1_DM_3 DDR3_M1_DQ_16
M_MA_DM1 AT48 DDR3_M0_DM_2 AV45 M_DATA_A15 AT6 DDR3_M1_DM_2 AV9
SCD1U16V2KX-3GP M_MA_DM0 AP52 DDR3_M0_DM_1 DDR3_M0_DQ_15 AY50 M_DATA_A14 AP2 DDR3_M1_DM_1 DDR3_M1_DQ_15 AY4
C574 (R_) DDR3_M0_DM_0 DDR3_M0_DQ_14 AT50 M_DATA_A13 DDR3_M1_DM_0 DDR3_M1_DQ_14 AT4
1 2 DDR3_VCCA_PWRGD M_DQS_A_DP7 BH32 DDR3_M0_DQ_13 AP47 M_DATA_A12 BH22 DDR3_M1_DQ_13 AP7
M_DQS_A_DN7 BG31 DDR3_M0_DQS_7 DDR3_M0_DQ_12 AV50 M_DATA_A11 BG23 DDR3_M1_DQS_7 DDR3_M1_DQ_12 AV4
SCD1U16V2KX-3GP M_DQS_A_DP6 BC30 DDR3_M0_DQSB_7 DDR3_M0_DQ_11 AY48 M_DATA_A10 BC24 DDR3_M1_DQSB_7 DDR3_M1_DQ_11 AY6
C575 (R_) M_DQS_A_DN6 BC32 DDR3_M0_DQS_6 DDR3_M0_DQ_10 AT47 M_DATA_A9 BC22 DDR3_M1_DQS_6 DDR3_M1_DQ_10 AT7
1 2 DDR3_DRAM_PWROK M_DQS_A_DP5 AT32 DDR3_M0_DQSB_6 DDR3_M0_DQ_9 AP48 M_DATA_A8 AT22 DDR3_M1_DQSB_6 DDR3_M1_DQ_9 AP6
M_DQS_A_DN5 AT34 DDR3_M0_DQS_5 DDR3_M0_DQ_8 AT20 DDR3_M1_DQS_5 DDR3_M1_DQ_8
SCD1U16V2KX-3GP M_DQS_A_DP4 BH40 DDR3_M0_DQSB_5 AP51 M_DATA_A7 BH14 DDR3_M1_DQSB_5 AP3
M_DQS_A_DN4 BG39 DDR3_M0_DQS_4 DDR3_M0_DQ_7 AR53 M_DATA_A6 BG15 DDR3_M1_DQS_4 DDR3_M1_DQ_7 AR1
M_DQS_A_DP3 AY52 DDR3_M0_DQSB_4 DDR3_M0_DQ_6 AK52 M_DATA_A5 AY2 DDR3_M1_DQSB_4 DDR3_M1_DQ_6 AK2
M_DQS_A_DN3 BA51 DDR3_M0_DQS_3 DDR3_M0_DQ_5 AL53 M_DATA_A4 BA3 DDR3_M1_DQS_3 DDR3_M1_DQ_5 AL1
M_DQS_A_DP2 AT42 DDR3_M0_DQSB_3 DDR3_M0_DQ_4 AR51 M_DATA_A3 AT12 DDR3_M1_DQSB_3 DDR3_M1_DQ_4 AR3
M_DQS_A_DN2 AT41 DDR3_M0_DQS_2 DDR3_M0_DQ_3 AT52 M_DATA_A2 AT13 DDR3_M1_DQS_2 DDR3_M1_DQ_3 AT2
M_DQS_A_DP1 AV47 DDR3_M0_DQSB_2 DDR3_M0_DQ_2 AL51 M_DATA_A1 AV7 DDR3_M1_DQSB_2 DDR3_M1_DQ_2 AL3
M_DQS_A_DN1 AV48 DDR3_M0_DQS_1 DDR3_M0_DQ_1 AK51 M_DATA_A0 AV6 DDR3_M1_DQS_1 DDR3_M1_DQ_1 AK3
M_DQS_A_DP0 AM52 DDR3_M0_DQSB_1 DDR3_M0_DQ_0 AM2 DDR3_M1_DQSB_1 DDR3_M1_DQ_0
R527 1 2 DRAM_RCOMP_0 M_DQS_A_DN0 AM51 DDR3_M0_DQS_0 AM3 DDR3_M1_DQS_0
182R2F-GP DDR3_M0_DQSB_0 DDR3_M1_DQSB_0
BRASWELL-GP
R1217 1 2 SM_RCOMP_1 BRASWELL-GP
(071.00BSW.0B0U)
182R2F-GP (071.00BSW.0B0U)

B B
DDR_VDDQ DDR_VDDQ
1

R1215 R545
4K7R2F-GP 4K7R2F-GP
DDR3_VREF_DQ DDR3_VREF_CA
1A001 1A001
2

R1214 R539
0R0402-PAD-2-GP 0R0402-PAD-2-GP
DDR3_VREF_DQ_R 1 2 DDR3_VREF_CA_R 1 2
1

1
2

R1216 C572 R542 C385

4K7R2F-GP C573 SCD1U16V2KX-3GP 4K7R2F-GP C372 SCD1U16V2KX-3GP
SCD1U16V2KX-3DLGP (R_) (R_)
1

SCD1U16V2KX-3DLGP
2

A A

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
CPU_(DDR)
Size Document Number Rev
C Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 5 of 105
5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 6 of 105

5 4 3 2 1
 5 4 3 2 1

D D

CPU1H 8 OF 13

BRASWELL PWR_VCORE_VNN
PWR_VCORE_VCC0 AA18
AF36 UNCORE_VNN_S41 AA19
AG33 CORE_VCC1_S0IX3 UNCORE_VNN_S42 AA21
AG35 CORE_VCC1_S0IX7 UNCORE_VNN_S43 AA22
AG36 CORE_VCC1_S0IX8 UNCORE_VNN_S44 AA24
AG38 CORE_VCC1_S0IX9 UNCORE_VNN_S45 AA25
AJ33 CORE_VCC1_S0IX10 UNCORE_VNN_S46 AC18
AJ36 CORE_VCC1_S0IX14 UNCORE_VNN_S47 AC19
AJ38 CORE_VCC1_S0IX15 UNCORE_VNN_S48 AC21
PWR_VCORE_VCC0 CORE_VCC1_S0IX16 UNCORE_VNN_S49 AC22
AF30 UNCORE_VNN_S410 AC24
AG27 CORE_VCC1_S0IX2 UNCORE_VNN_S411 AC25
AG29 CORE_VCC1_S0IX4 UNCORE_VNN_S412 AD25
AG30 CORE_VCC1_S0IX5 UNCORE_VNN_S413 AD27
AJ27 CORE_VCC1_S0IX6 UNCORE_VNN_S414
AJ29 CORE_VCC1_S0IX11 AA30 1P05V_S5
C CORE_VCC1_S0IX12 RSVD#AA30 C
AJ30 V33
AF29 CORE_VCC1_S0IX13 UNCORE_V1P15_S0IX6 AA32
CORE_VCC1_S0IX1 UNCORE_V1P15_S0IX1 AA33
PWR_VCORE_VGG UNCORE_V1P15_S0IX2 AA35
AD16 UNCORE_V1P15_S0IX3 AA36
AD18 DDI_VGG_S0IX1 UNCORE_V1P15_S0IX4 AC32
AD19 DDI_VGG_S0IX2 UNCORE_V1P15_S0IX5 Y30
AF16 DDI_VGG_S0IX3 UNCORE_V1P15_S0IX7 Y32
AF18 DDI_VGG_S0IX4 UNCORE_V1P15_S0IX8 Y33
AF19 DDI_VGG_S0IX5 UNCORE_V1P15_S0IX9 Y35
DDI_VGG_S0IX6 UNCORE_V1P15_S0IX10 VCCDIGICKSI0_1P05
-1010 1P05V_S5
AF21
AF22 DDI_VGG_S0IX7 V19 1 2

iCLK
AJ19 DDI_VGG_S0IX8 ICLK_GND_OFF2 V18 R1220
AG16 DDI_VGG_S0IX15 ICLK_GND_OFF1 VCCADDR_1P05 0R0805-PAD 1P05V_S5
AG18 DDI_VGG_S0IX9 AM21 1 2
AG19 DDI_VGG_S0IX10 DDR_V1P05A_G31 AM33 R1221
AG21 DDI_VGG_S0IX11 DDR_V1P05A_G34 AM22 0R1206-PAD
AG22 DDI_VGG_S0IX12 DDR_V1P05A_G32 AN22
AG24 DDI_VGG_S0IX13 DDR_V1P05A_G35 AN32

DDR
AJ21 DDI_VGG_S0IX14 DDR_V1P05A_G36 AM32
AJ22 DDI_VGG_S0IX16 DDR_V1P05A_G33 VCCBMPD_MPHY_1P05 1P05V_S5
AJ24 DDI_VGG_S0IX17 V22 1 2
AK24 DDI_VGG_S0IX18 PCIE_V1P05A_G31#V22 V24 R1222
1P15V_S5
-1010 VCCRAM0CPU0SI1_1P15 DDI_VGG_S0IX19 PCIE_V1P05A_G32 0R0603-PAD

SATA PCIe
B
1 2 AK30 B
R1225 AK35 CORE_V1P15_S0IX1
CORE_V1P15_S0IX2 U24
0R0805-PAD AK36 SATA_V1P05A_G32
CORE_V1P15_S0IX3 U22
AM29 SATA_V1P05A_G31
CORE_V1P15_S0IX4
1P15V_S5 VCCFHVCPU0SI0_1P15 V27
1 2 AK33 USB3_V1P05A_G32 U27 1P05V_S5
R1224 AJ35 FUSE_V1P15_S0IX2 USB3_V1P05A_G31 V29

USB
1P15V_S5 0R0805-PAD VCCSRAMGEN_1P15 FUSE_V1P15_S0IX1 USBSSIC_V1P05A_G3
1 2 AM19 N18
R1223 AK21 DDI_V1P15_S0IX2 FUSE3_V1P05A_G5 U19
0R0805-PAD DDI_V1P15_S0IX1 FUSE FUSE_V1P05A_G3

BRASWELL-GP
(071.00BSW.0B0U)

A
Vinafix.com Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A

Hsichih, Taipei
Title
CPU (VCC_CORE)
Size Document Number Rev
Custom Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 7 of 105

5 4 3 2 1
 5 4 3 2 1

D D

CPU1C 3 OF 13
8/12 Richard BRASWELL
Base on Brain's issue to swap port 0 2
M44
RSVD#M44 K44
RSVD#K44
K48
1D8V_S5 D50 RSVD#K48 K47
[56] HDMI_DATA_CPU_P0 C51 DDI0_TXP_0 RSVD#K47
HDMI [56] HDMI_DATA_CPU_N0 DDI0_TXN_0 T44
MCSI_1_CLKP

2
1A016 H49 T45
R1910 [56] HDMI_DATA_CPU_P1 H50 DDI0_TXP_1 MCSI_1_CLKN
10KR2J-3-GP [56] HDMI_DATA_CPU_N1 DDI0_TXN_1 Y47

MCSI and Camera interface

(R_) F53 DDI0 MCSI_1_DP_0 Y48
[56] HDMI_DATA_CPU_P2 F52 DDI0_TXP_2 MCSI_1_DN_0 V45

1
[56] HDMI_DATA_CPU_N2 DDI0_TXN_2 MCSI_1_DP_1 V47
G53 MCSI_1_DN_1 V50
[56] HDMI_DATA_CPU_P3 G52 DDI0_TXP_3 MCSI_1_DP_2 V48
[56] HDMI_DATA_CPU_N3 DDI0_TXN_3 MCSI_1_DN_2 T41

D
H47 MCSI_1_DP_3 T42
HDMI CLK DDI0_AUXP MCSI_1_DN_3
Q1246 H46
2N7002A-7-GP DDI0_AUXN P50
G (84.2N702.J31) HDMI_CPU_HPD W51 MCSI_2_CLKP P48
[56] DDSP_C_HPD_CONN HV_DDI0_HPD MCSI_2_CLKN

1
HDMI_CTRL_CLK Y51 P47
HPD R80127 [56] HDMI_CTRL_CLK HDMI_CTRL_DATA Y52 HV_DDI0_DDC_SCL MCSI_2_DP_0 P45

S
H: Detect 100KR2J-1-GP [56] HDMI_CTRL_DATA HV_DDI0_DDC_SDA MCSI_2_DN_0
MCSI_2_DP_1
M48
V52 M47
L: No detect V51 PANEL0_BKLTEN MCSI_2_DN_1

2
W53 PANEL0_BKLTCTL T50
R1228 1 2 402R2F-GP DDI0_RCOMP_P F38 PANEL0_VDDEN RSVD#T50 T48
C C
DDI0_RCOMP_N G38 DDI0_PLLOBS_P RSVD#T48
DDI0_PLLOBS_N P44 MCSI_COMP R1230 1 2 150R2F-1-GP
1D8V_S5 J51 MCSI_COMP
[55] DP_CPU_TXP0 H51 DDI1_TXP_0 AB41
DP to RTD2168 [55] DP_CPU_TXN0 DDI1_TXN_0 GP_CAMERASB00 AB45
DBG8 [99]
DBG9 [99] XDP

2
GP_CAMERASB01
09/17 change DP to VGA 1A016 [55] DP_CPU_TXP1
K51
DDI1_TXP_1 GP_CAMERASB02
AB44
DBG10 [99]
R498 K52 AC53
[55] DP_CPU_TXN1 DDI1_TXN_1 GP_CAMERASB03 DBG11 [99]
10KR2J-3-GP AB51
(R_) L53
DDI1
GP_CAMERASB04 AB52 DBG12 [99] R:Check PIN
DDI1_TXP_2 GP_CAMERASB05 DBG13 [99]
L51 AA51

1
CPU_HPD DDI1_TXN_2 GP_CAMERASB06 AB40 DBG14 [99]
GP_CAMERASB07 DBG15 [99]
M52 Y44
DDI1_TXP_3 GP_CAMERASB08 OBSFN_C0 [15,99]
M51
DDI1_TXN_3 Y42
GP_CAMERASB09 [15]

D
M42 GP_CAMERASB09 Y41
[55] DP_CPU_AUXP K42 DDI1_AUXP GP_CAMERASB10 V40
Q6703 GP_CAMERASB11 [15]
[55] DP_CPU_AUXN DDI1_AUXN GP_CAMERASB11
2N7002A-7-GP SB002
G R51 SC001
[55] DP1_HPD HV_DDI1_HPD
(84.2N702.J31)
1

P51 M7
HPD R80128 P52 PANEL1_BKLTEN SDMMC1_CLK 1D8V_S5
S

H: Detect 100KR2J-1-GP R53 PANEL1_BKLTCTL

PANEL1_VDDEN SDMMC1_CMD
P6
(R_) R1227 1 2 402R2F-GP DDI1_RCOMP_P F47 NGFF_DETECT_USB R802451 2 10KR2J-3-GP
L: No detect DDI1_RCOMP_N F49 DDI1_PLLOBS_P M6 NGFF_DETECT_PCIE R802461 2 10KR2J-3-GP
2

DDI1_PLLOBS_N SDMMC1_D0 M4 F_LED_DET_N R530 1 2 10KR2J-3-GP

F40 SDMMC1_D1 P9
G40 DDI2_TXP_0 SDMMC1_D2 P7
SDMMC1
DDI2_TXN_0 SDMMC1_D3_CD# T6
J40 MMC1_D4_SD_WE T7 NGFF_DETECT_USB
DDI2_TXP_1 DDI2 MMC1_D5 NGFF_DETECT_PCIE NGFF_DETECT_USB [61]
K40 T10
DDI2_TXN_1 MMC1_D6 T12 F_LED_DET_N NGFF_DETECT_PCIE [61]
MMC1_D7 F_LED_DET_N [64] SC002
F42 T13
G42 DDI2_TXP_2 MMC1_RCLK P13 SDMMC1_RCOMP R802 1 2 100R2F-L1-GP-U Change NET name from
DDI2_TXN_2 SDMMC1_RCOMP PWRCN_DET_N_C to F_LED_DET_N
D44
F44 DDI2_TXP_3 K10
DDI2_TXN_3 SDMMC2_CLK K9
B
D48 SDMMC2_CMD B
C49 DDI2_AUXP M12
DDI2_AUXN SDMMC2_D0 M10
1 DDI0_HPD U51 SDMMC2_D1 K7
TP4166 HV_DDI2_HPD SDMMC2_D2
SDMMC2 K6
1 DDI0_DDCCLK T51 SDMMC2_D3_CD#
TP4167 1 DDI0_DDCDATA T52 HV_DDI2_DDC_SCL F2
TP4168 HV_DDI2_DDC_SDA SDMMC3_CLK D2
B53 SDMMC3_CMD K3
A52 RSVD#B53 SDMMC3_CD#
E52 RSVD#A52 NC's
J1
D52 RSVD#E52 SDMMC3_D0 J3
B50 RSVD#D52 SDMMC3_D1 H3
B49 RSVD#B50 SDMMC3_D2 G2
E53 RSVD#B49 SDMMC3_D3
C53 RSVD#E53 K2
SDMMC3
A51 RSVD#C53 SDMMC3_1P8_EN L3
A49 RSVD#A51 SDMMC3_PWR_EN# P12 SD_RCOMP 11/05
G44 RSVD#A49 SDMMC3_RCOMP
RSVD#G44

1
R80130
80D6R2F-L-GP

2
BRASWELL-GP
(071.00BSW.0B0U)

A A

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
CPU_(DDI/EDP)
Size Document Number Rev
C Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 8 of 105
5 4 3 2 1
 5 4 3 2 1

11/11
CPU1J 10 OF 13 CPU1K 11 OF 13 CPU1L 12 OF 13 Pin B52 can not break out CPU1M 13 OF 13
Power-VSS Power-VSS Power-VSS Power-VSS
F1 BRASWELL W1
AN3 BRASWELL AF38 AN21 BRASWELL AY9 AN33 BRASWELL Y24 check with Intel C1 VSS18 VSS57 V44
AN29 VSS98 VSS51 AF32 BG30 VSS5 VSS61 AY28 P32 VSS2 VSS102 G30 1 (R_) 2 BH53 VSS17 VSS56 V42
AN25 VSS97 VSS50 AF25 BG27 VSS101 VSS52 AY26 P27 VSS99 VSS53 G28 R1684 BH52 VSS16 VSS55 V41
AN24 VSS96 VSS49 AF10 BG24 VSS100 VSS51 AY24 P22 VSS98 VSS52 G26 0R2J-2-GP BH2 VSS15 VSS54 V38
D VSS95 VSS48 VSS99 VSS50 VSS97 VSS51 VSS14 VSS53 D
AN16 AE9 BG20 AY22 P19 G22 BH1
AN14 VSS94 VSS47 AE8 BG19 VSS98 VSS49 AY20 AF24 VSS96 VSS50 G14 BG53 VSS13 V32
AN12 VSS93 VSS46 AE6 BG18 VSS97 VSS48 AW35 N53 VSS1 VSS49 G12 2014.03.12 CRB NC BG1 VSS12 VSS52 V21
AN11 VSS92 VSS45 AE53 BG16 VSS96 VSS47 AW27 N51 VSS95 VSS48 F5 check with Intel B52 VSS10 VSS51 V16
AN1 VSS91 VSS44 AE50 BG14 VSS95 VSS46 AW19 N32 VSS94 VSS47 F35 B2 VSS5 VSS50 U9
AM50 VSS90 VSS43 AE48 BF42 VSS94 VSS45 AM13 N24 VSS93 VSS46 F32 VSS4 VSS49 U8
AM42 VSS89 VSS42 AE46 BF32 VSS93 VSS4 AK29 N22 VSS92 VSS45 F27 1 (R_) 2 A6 VSS48 U6
AM4 VSS88 VSS41 AE45 BF28 VSS92 VSS3 AK22 M9 VSS91 VSS44 F24 R1685 A5 VSS2 VSS47 U53
AM38 VSS87 VSS40 AE43 BF27 VSS91 VSS2 AV40 VSS90 VSS43 F19 0R2J-2-GP VSS1 VSS46 U5
AM35 VSS86 VSS39 AE42 BF26 VSS90 VSS44 AV35 K45 VSS42 E51 M24 VSS45 U49
AH44 VSS85 VSS38 AE40 BF22 VSS89 VSS43 AV30 M40 VSS77 VSS41 E35 A7 VSSA VSS44 U48
AM30 VSS60 VSS37 AE14 BF12 VSS88 VSS42 AV27 M35 VSS87 VSS39 E19 BF50 VSS3 VSS43 U46
VSS84 VSS36 VSS87 VSS41 VSS86 VSS38 SC029 VSS9 VSS42
AM27 AE12 BE35 AV24 M27 D42 Change to NC BF4 U45
U25 VSS83 VSS35 AE11 BE19 VSS86 VSS40 AV19 AW13 VSS85 VSS37 D40 BB50 VSS8 VSS41 U43
P10 VSS100 VSS34 AE1 C20 VSS85 VSS39 AV14 M19 VSS3 VSS36 D38 VSS7 VSS40 U42
AM16 VSS99 VSS33 AD44 BD53 VSS103 VSS38 AJ18 M14 VSS84 VSS35 D32 BB4 VSS39 U40
AD4 VSS81 VSS32 AD36 BG7 VSS84 VSS1 AU53 L35 VSS83 VSS34 D27 VSS6 VSS38 U38
C VSS31 VSS30 VSS102 VSS37 VSS82 VSS33 VSS37 C
AK7 AC29 BD35 AU51 L27 D24 BG47
AK50 VSS80 VSS23 AD32 BD27 VSS83 VSS36 AU3 L19 VSS81 VSS32 D16 Y9 VSS11 U33
AK47 VSS79 VSS29 AD30 BD19 VSS82 VSS35 AU1 L1 VSS80 VSS31 D10 Y50 VSS70 VSS35 U32
AK45 VSS78 VSS28 AD21 BD1 VSS81 VSS34 AT9 K50 VSS79 VSS30 J42 Y45 VSS69 VSS34 U30
AK44 VSS77 VSS27 AC38 BC44 VSS80 VSS33 AT51 T47 VSS78 VSS65 C47 Y40 VSS68 VSS33 U29
AK40 VSS76 VSS26 AC35 BC40 VSS79 VSS32 AT45 K4 VSS100 VSS29 C39 Y4 VSS67 VSS32
AK4 VSS75 VSS25 AC33 BC38 VSS78 VSS31 AT36 K36 VSS76 VSS28 C36 Y38 VSS66 U21
AK38 VSS74 VSS24 AC16 BC28 VSS77 VSS30 AT35 K34 VSS75 VSS27 C30 Y29 VSS65 VSS31 U18
AK32 VSS73 VSS22 AB6 BC26 VSS76 VSS29 AT3 K32 VSS74 VSS26 C3 Y22 VSS64 VSS30 U36
AK27 VSS72 VSS21 AB50 BC16 VSS75 VSS28 AT27 K30 VSS73 VSS25 C28 Y21 VSS63 VSS36 U14
AK25 VSS71 VSS20 AB47 BC14 VSS74 VSS27 AT19 K24 VSS72 VSS24 C22 Y19 VSS62 VSS29 U12
AM24 VSS70 VSS19 AB42 BC10 VSS73 VSS26 AT18 K22 VSS71 VSS23 AW41 Y16 VSS61 VSS28 U11
AK16 VSS82 VSS18 AB4 BB35 VSS72 VSS25 AP9 K16 VSS70 VSS4 BJ7 Y14 VSS60 VSS27 T9
AJ53 VSS69 VSS17 AB14 BB27 VSS71 VSS24 AP50 K14 VSS69 VSS22 BJ47 Y10 VSS59 VSS26 P42
AJ51 VSS68 VSS16 AB13 BB19 VSS70 VSS23 AP45 K12 VSS68 VSS21 BJ43 VSS58 VSS23 T14
AJ3 VSS67 VSS15 AB12 BA35 VSS69 VSS22 AP4 J53 VSS67 VSS20 BJ39 P4 VSS25 R1
AJ25 VSS66 VSS14 AB10 BA30 VSS68 VSS21 AN9 M45 VSS66 VSS19 BJ35 L41 VSS22 VSS24
B VSS65 VSS13 VSS67 VSS20 VSS88 VSS18 VSS19 B
AJ16 AA53 BA27 AN8 J38 BJ31 P36 P35
AJ1 VSS64 VSS12 AA38 BA24 VSS66 VSS19 AN6 J35 VSS64 VSS17 BJ27 VSS21 VSS20
AH9 VSS63 VSS11 AA27 BA19 VSS65 VSS18 AN53 J30 VSS63 VSS16 BJ23 BRASWELL-GP
AH47 VSS62 VSS10 AA16 B36 VSS64 VSS17 AN51 J27 VSS62 VSS15 BJ19
VSS61 VSS9 VSS63 VSS16 VSS61 VSS14 (071.00BSW.0B0U)
AH42 A47 B28 AN5 J22 BJ15
AH41 VSS59 VSS8 A43 AY7 VSS62 VSS15 AN49 J19 VSS60 VSS13 BJ11
AH14 VSS58 VSS7 A39 AY51 VSS60 VSS14 AN48 J18 VSS59 VSS12 BG5
AH13 VSS57 VSS6 A31 AY47 VSS59 VSS13 AN46 H8 VSS58 VSS11 BG49
AH12 VSS56 VSS5 A23 AY34 VSS58 VSS12 AN45 E46 VSS57 VSS10 BG40
AH10 VSS55 VSS4 A19 AY32 VSS56 VSS11 AN43 H35 VSS40 VSS9 BG38
AG25 VSS54 VSS3 A15 AY30 VSS55 VSS10 AN42 H27 VSS56 VSS8 BG36
AF47 VSS53 VSS2 A11 AY3 VSS54 VSS9 AN40 H19 VSS55 VSS7 BG35
VSS52 VSS1 AN30 VSS53 VSS8 AN38 M50 VSS54 VSS6 BG34
AY45 VSS6 VSS7 V25 VSS89 VSS5
BRASWELL-GP VSS57 VSS101 Wistron Incorporated
(071.00BSW.0B0U) 12F, 88, Hsin Tai Wu Rd
A Hsichih, Taipei A
BRASWELL-GP BRASWELL-GP
(071.00BSW.0B0U) (071.00BSW.0B0U) Title
CPU_(VSS)
Size Document Number Rev
Custom Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 9 of 105

5 4 3 2 1
 5 4 3 2 1

0812 Jeffrey add 22u 0603 *3 0812 Jeffrey add 22u 0603 *3(reserve)
D 0808 Jeffrey delete 0805 0811 change power rail PWR_VCORE_VCC1 to VCC0 D
0808 Jeffrey delete 0805

VCORE0 PLACE ALL THE CAPS

UNDER THE PKG SHADOW VCORE0 PLACE ALL THE CAPS
PWR_VCORE_VCC0 UNDER THE PKG SHADOW
PWR_VCORE_VCC0
0808 Jeffrey delete 0805
AF36, AG33, AG35, AG36, AG38, AJ33, AJ36, AJ38 PWR_VCORE_VNN
AF30, AG27, AG29, AG30, AJ27, AJ29, AJ30, AF29 AA18, AA19, AA21, AA22, AA24, AA25, AC18, AC19, AC21, AC22, AC24, AC25, AD25, AD27
1

1
C305 C304 C1620 C1621 C1622 C6726 C6727 C6728 (R_) (R_) (R_)

1
C582 C583 C1623 C1624 C1625 C6729 C6730 C6731 C597 C598 C599 C600 C6716 C6717 C6718
CRB 4*1U 0402, 3*22U 0603
2

SC22U6D3V3MX-1-DL-GP

SC22U6D3V3MX-1-DL-GP

SC22U6D3V3MX-1-DL-GP
Our 4*1U 0402, 3*22U 0603 3*22U 0805(remove)

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP
2

2
SC22U6D3V3MX-1-DL-GP

SC22U6D3V3MX-1-DL-GP

SC22U6D3V3MX-1-DL-GP

SC22U6D3V3MX-1-DL-GP

SC22U6D3V3MX-1-DL-GP
SC4D7U6D3V2MX-1-GP

SC4D7U6D3V2MX-1-GP

SC4D7U6D3V2MX-1-GP

SC22U6D3V3MX-1-DL-GP

SC22U6D3V3MX-1-DL-GP

SC22U6D3V3MX-1-DL-GP

SC22U6D3V3MX-1-DL-GP

SC22U6D3V3MX-1-DL-GP
SC4D7U6D3V2MX-1-GP

SC4D7U6D3V2MX-1-GP

SC4D7U6D3V2MX-1-GP
1P05V_S5
CRB 3*4.7U 0402, 2*22U 0603
Our 3*4.7U 0402 5*22U 0603 1*22U 0805(remove) CRB 3*4.7U 0402, 2*22U 0603 V33, AA32, AA33, AA35, AA36, AC32, Y30, Y32, Y33, Y35
Our 3*4.7U 0402, 2*22U 0603 3*22U 0603(reserve) 0808 Jeffrey modify CAP 7pcs to 5pcs
1*22U 0805(remove)
CRB 5*1U 0402

1
VCCRAM0CPU0SI1_1P15 VCCSRAMGEN_1P15 C605 C606 C607 C608 C609
Our 5*1U 0402

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP
2

2
1

1
C C625 C626 C627 C631 C629 C630 C632 C633 C634 C
SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP
2

2
VCCDIGICKSI0_1P05 VCCADDR_1P05 1P05V_S5
AM21, AM33, AM22, AN22, AN32, AM32 N18
V18, V19
CRB 6*1U 0402 CRB 3*1U 0402

1
Our 6*1U 0402 0808 Jeffrey modify CAP 2pcs to 1pcs C612 C614 C6719 C6720 C617
VNN_GFX

SC22U6D3V3MX-1-DL-GP

SC22U6D3V3MX-1-DL-GP
SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP
2

2
PWR_VCORE_VGG
1

C12377 C12378 C590 C591 C592

CRB 1*1U 0402
0808 Jeffrey add 22U 0603
2

CRB 1*1U 0402

SC4D7U6D3V2MX-1-GP

SC22U6D3V3MX-1-DL-GP

SC22U6D3V3MX-1-DL-GP

SC22U6D3V3MX-1-DL-GP

SC22U6D3V3MX-1-DL-GP

CRB 5*10U 0402, 2*270U POSCAP CRB 1*1U 0402, 2*22U 0603
Our 5*10U 0402 4*22U 0805(remove) Our 1*1U 0402, 2*22U 0603

VCCBMPD_MPHY_1P05 1P05V_S5 1P05V_S5

V22, V24, U24, U22, V27, U27 V29 U19
B B

1
C618 C619 C620 C621 C622 C623 C624

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP
2

2
CRB 3*1U 0402 CRB 2*1U 0402 CRB 2*1U 0402

A A

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
CPU (Power CAP1)
Size Document Number Rev
C Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 10 of 105

5 4 3 2 1
 5 4 3 2 1

D D

0808 Jeffrey delete 0805 0808 Jeffrey delete 0805

VCCSFRPLLDDR_1P24_1P35 VCCCLKDDR_1P24_1P35

Close to CPU Close to CPU

1
C1633 C6721 C1634 C6722

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP
SC22U6D3V3MX-1-DL-GP

SC22U6D3V3MX-1-DL-GP
2

2
CRB 1*1U 0402, 1*22U 0603

CRB 1*1U 0402, 1*22U 0603,

0808 Jeffrey modify cap

2pcs to 1 pcs 0808 Jeffrey delete 0603 cap size 0808 Jeffrey delete 0603 cap size

DDR_VDDQ 1D24V_S5 1D24V_S5 1D24V_S5 1D24V_S5 1D24V_S5 1D24V_S5 1D24V_S5

Place close to CPU M41 U35, V35 Y27, Y25 P38, V30, AC30 AF35, AD35, AD38, AC36
T40, P40
C C
V36, Y36
1

1
C641 C642 C643 C644 C1635 C1636 C1638 C1639 C1640 C1641 C1643 C1644 C1645
2

2
SC22U6D3V5MX-2DLGP

SC22U6D3V5MX-2DLGP

SC22U6D3V5MX-2DLGP

SC22U6D3V5MX-2DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP
CRB 4*22U 0603 CRB 1*1U 0402 CRB 1*1U 0402 CRB 1*1U 0402 CRB 2*1U 0402 CRB 1*1U 0402, 1*1U 0603 CRB 2*1U 0402 CRB 1*1U 0402,

0808 Jeffrey delete 0402 1cap

1D24V_S5 1D24V_S5 VCCPADCF2SI0_E_1P80 VCCPADCF1SI0_1P80 VCCCFIOAZA_1P80 VCCPADCF1SI0_1P8_3P3 VCCPADCF3SI0_1P8_3P3 VCCUSB2_1P8 VCCUSB2_3P3 V1P8_FUSE
H44

P41
1

1
C1646 C1647 C1648 C1649 C1650 C1651 C1652 C1656 C1655 C1654 C1653 C1657 C1658 C1659 C1660
2

2
B B
SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP
CRB 1*1U 0402 CRB 1*1U 0402 CRB 3*1U 0402 CRB 2*1U 0402 CRB 1*1U 0402 CRB 1*1U 0402 CRB 2*1U 0402 CRB 2*1U 0402 CRB 1*1U 0402 CRB 1*1U 0402

1P05V_S5 VCCRTC_3P3 VCCRTCSUS_3P3

H10, G10
1

C1661 C1663 C1662

2

2
SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

A A

Wistron Incorporated
CRB 1*1U 0402 CRB 1*1U 0402 CRB 1*1U 0402
12F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
CPU (Power CAP2)
Size Document Number Rev
Custom Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 11 of 105

5 4 3 2 1
 5 4 3 2 1

DIMM1

M_MAA_A0 98 NP1
M_MAA_A1 97 A0 NP1 NP2
M_MAA_A2 96 A1 NP2 DDR_VDDQ
M_MAA_A3 95 A2 110 M_RAS_A_N
M_MAA_A4 92 A3 RAS# 113 M_WE_A_N
A4 WE#

SC10U6D3V3MX-DL-GP
M_MAA_A5 91 115 M_CAS_A_N
A5 CAS#

2
M_MAA_A6 90 C68 C77 C71 C67 C64 C60 C63 C76
M_MAA_A7 86 A6 114 M_SCS_A_N0
M_MAA_A8 A7 CS0# M_SCS_A_N1

SC10U6D3V3MX-DL-GP

SC10U6D3V3MX-DL-GP

SC10U6D3V3MX-DL-GP

SC10U6D3V3MX-DL-GP

SC10U6D3V3MX-DL-GP

SC10U6D3V3MX-DL-GP

SC10U6D3V3MX-DL-GP
89 121

1
M_MAA_A9 85 A8 CS1#
M_MAA_A10 107 A9 73 M_SCKE_A0
M_MAA_A11 84 A10/AP CKE0 74 M_SCKE_A1
D M_MAA_A12 83 A11 CKE1 D
M_MAA_A13 119 A12 101 CK_M_DDR0_A_DP
M_MAA_A14 80 A13 CK0 103 CK_M_DDR0_A_DN DDR_VDDQ
M_MAA_A15 78 A14 CK0#
DDR DATA M_SBS_A2 79 A15
A16/BA2 CK1
102 CK_M_DDR1_A_DP
104 CK_M_DDR1_A_DN
[5] M_DATA_A[0..63] M_SBS_A0 CK1#
[5] M_DQS_A_DP[0..7] 109
M_SBS_A1 108 BA0 11 M_MA_DM0
[5] M_DQS_A_DN[0..7] BA1 DM0

2
28 M_MA_DM1
[5] M_MA_DM[7..0] M_DATA_A1 5 DM1 46 M_MA_DM2
0826 Richard DQ0 DM2
C62 C66 C70 C78 C61 C79 C69 C65
Refer to CRB to swap data for routing. M_DATA_A4 7 63 M_MA_DM3 SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP

1
M_DATA_A2 15 DQ1 DM3 136 M_MA_DM4 SCD1U16V2KX-3DLGP
M_DATA_A3 17 DQ2 DM4 153 M_MA_DM5 SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP
M_DATA_A0 4 DQ3 DM5 170 M_MA_DM6
DDR CMD/ADD M_DATA_A5 6 DQ4
DQ5
DM6
DM7
187 M_MA_DM7
M_DATA_A6 16
[5] M_MAA_A[0..15] M_DATA_A7 18 DQ6 200 SMB0_DATA_MAIN
M_DATA_A13 21 DQ7 SDA 202 SMB0_CLK_MAIN
[5] M_WE_A_N M_DATA_A9 23 DQ8 SCL VCC3
[5] M_CAS_A_N M_DATA_A10 33 DQ9 198 MEM_MA_EVENT_L
[5] M_RAS_A_N M_DATA_A14 35 DQ10 EVENT#
M_DATA_A8 22 DQ11 199
[5] M_SBS_A0 DQ12 VDDSPD VCC3

1
M_DATA_A12 24
[5] M_SBS_A1 M_DATA_A11 34 DQ13 197 DIMM1_SA0 C398 C399
[5] M_SBS_A2 M_DATA_A15 36 DQ14 SA0 201 DIMM1_SA1 SCD1U16V2KX-3GP

2
M_DATA_A22 39 DQ15 SA1 SCD1U16V2KX-3DLGP
M_DATA_A17 DQ16 (R_)
41 77
DDR CTRL M_DATA_A18 51 DQ17
DQ18
NC#1
NC#2
122
M_DATA_A23 53 125
[5] M_SCS_A_N0 M_DATA_A19 40 DQ19 NC#/TEST
[5] M_SCS_A_N1 M_DATA_A16 42 DQ20 75 DIMM1_SA0 R579 1 2 10KR2J-3-GP
[5] M_SCKE_A0 M_DATA_A20 DQ21 VDD1 DDR_VDDQ
50 76
[5] M_SCKE_A1 M_DATA_A21 52 DQ22 VDD2 81 DIMM1_SA1 R581 1 2 10KR2J-3-GP MEM_VTT Place these caps
[5] M_ODT_A0 M_DATA_A28 57 DQ23 VDD3 82 close to VTT1 and
[5] M_ODT_A1 M_DATA_A30 59 DQ24 VDD4 87 VTT2.
M_DATA_A24 67 DQ25 VDD5 88
M_DATA_A26 69 DQ26 VDD6 93
M_DATA_A27 56 DQ27 VDD7 94
C
DDR CLOCK DQ28 VDD8
C

2
M_DATA_A25 58 99 C407 C408 C404 C403 C406 C405
M_DATA_A31 68 DQ29 VDD9 100
M_DATA_A29 70 DQ30 VDD10 105 Note:

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP
[5] CK_M_DDR0_A_DP

1
M_DATA_A32 DQ31 VDD11

SC10U6D3V3MX-DL-GP

SC10U6D3V3MX-DL-GP
[5] CK_M_DDR0_A_DN 129 106
M_DATA_A37 131 DQ32 VDD12 111 If SA0 DIM0 = 0, SA1_DIM0 = 0
[5] CK_M_DDR1_A_DP DQ33 VDD13
[5] CK_M_DDR1_A_DN
M_DATA_A34 141
DQ34 VDD14
112 SO-DIMMA SPD Address is 0xA0
M_DATA_A38 143 117
M_DATA_A36 DQ35 VDD15 SO-DIMMA TS Address is 0x30
130 118
M_DATA_A33 132 DQ36 VDD16 123
DDR OTHERS M_DATA_A35 140 DQ37
DQ38
VDD17
VDD18
124 If SA0 DIM0 = 0, SA1_DIM0 = 1
M_DATA_A39 142 SO-DIMMA SPD Address is 0xA4
M_DATA_A40 147 DQ39 2
[5] DDR3_DRAMRST_N M_DATA_A41 149 DQ40 VSS 3 SO-DIMMA TS Address is 0x34
M_DATA_A42 157 DQ41 VSS 8
M_DATA_A46 159 DQ42 VSS 9
[17,37,55,77] SMB0_CLK_MAIN M_DATA_A44 146 DQ43 VSS 13 VCC3
[17,37,55,77] SMB0_DATA_MAIN M_DATA_A45 DQ44 VSS
148 14
M_DATA_A43 158 DQ45 VSS 19
M_DATA_A47 160 DQ46 VSS 20
M_DATA_A48 163 DQ47 VSS 25
DQ48 VSS

2
M_DATA_A52 165 26
M_DATA_A55 175 DQ49 VSS 31 R576
M_DATA_A51 177 DQ50 VSS 32
DQ51 VSS 10KR2J-3-GP
M_DATA_A53 164 37
M_DATA_A49 166 DQ52 VSS 38 1 (R_) 2 SIO_MEM_EVENT_L_B
DDR_VDDQ

1
[24] SIO_MEM_EVENT_L M_DATA_A54 174 DQ53 VSS 43 R572
M_DATA_A50 176 DQ54 VSS 44 1KR2J-1-GP

B
M_DATA_A56 181 DQ55 VSS 48 (R_)
M_DATA_A59 183 DQ56 VSS 49
M_DATA_A62 191 DQ57 VSS 54 SIO_MEM_EVENT_L 1 (R_) 2SIO_MEM_EVENT_L_C C E MEM_MA_EVENT_L
M_DATA_A60 193 DQ58 VSS 55 R565
M_DATA_A58 180 DQ59 VSS 60 0R2J-2-GP Q51
M_DATA_A63 182 DQ60 VSS 61 MMBT3904-4-GP
M_DATA_A61 192 DQ61 VSS 65
M_DATA_A57 194 DQ62 VSS 66
DQ63 VSS 71
M_DQS_A_DN0 10 VSS 72
B M_DQS_A_DN1 27 DQS0# VSS 127 B
M_DQS_A_DN2 45 DQS1# VSS 128
M_DQS_A_DN3 62 DQS2# VSS 133
M_DQS_A_DN4 135 DQS3# VSS 134
M_DQS_A_DN5 152 DQS4# VSS 138
M_DQS_A_DN6 169 DQS5# VSS 139 VREF_CA_DIMM1 VREF_DQ_DIMM1
M_DQS_A_DN7 186 DQS6# VSS 144
DQS7# VSS 145
VSS

1
M_DQS_A_DP0 12 150
M_DQS_A_DP1 29 DQS0 VSS 151 C81 C302
M_DQS_A_DP2 47 DQS1 VSS 155 SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP

2
M_DQS_A_DP3 64 DQS2 VSS 156
M_DQS_A_DP4 137 DQS3 VSS 161
M_DQS_A_DP5 154 DQS4 VSS 162
M_DQS_A_DP6 171 DQS5 VSS 167
M_DQS_A_DP7 188 DQS6 VSS 168
DQS7 VSS 172
M_ODT_A0
M_ODT_A1
116
ODT0
VSS
VSS
173 For Intel Recommend Close to DIMM1 (Bay Trail) For Intel Recommend Close to DIMM1 (Bay Trail)
120 178
ODT1 VSS 179 DDR_VDDQ DDR_VDDQ
VREF_CA_DIMM1 126 VSS 184
VREF_DQ_DIMM1 1 VREF_CA VSS 185
VREF_DQ VSS 189
VSS

1
DDR3_DRAMRST_N 1 2 DDR3_DRAMRST_N_A_1 30 190
R1672 RESET# VSS 195 R117 R484
0R0402-PAD-2-GP VSS 196 4K7R2F-GP 4K7R2F-GP
203 VSS 205
1A001 MEM_VTT VTT1 VSS 1A001 1A001
1

(R_) 204 206

2
VTT2 VSS R1671 R1670
C47
SCD1U10V2KX-5GP VREF_CA_DIMM1 1 2 VREF_CA_0 VREF_DQ_DIMM1 1 2 VREF_DQ_0
2

DDR3-204P-252-GP-U 0R0402-PAD-2-GP 0R0402-PAD-2-GP

SB 0730 Eric modify 62.10017.I31

1
1

2
1A014 R122 R483
C12413 C82 4K7R2F-GP C303 4K7R2F-GP
2015/4/13 follow EMN to modify DIMM1 symbol SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP
2

1
SC2D2U10V3KX-1DLGP-U

2
A A
SC045 close to DIMM slot pin 126 close to DIMM slot pin 1

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
DDR3_SODIMM1
Size Document Number Rev
Custom Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 12 of 105
5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking

B B

Wistron Incorporated
A A
12F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title

Size Document Number Rev

A4 Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 13 of 105

5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
A A
12F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title

Size Document Number Rev

A4 Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 14 of 105

5 4 3 2 1
 5 4 3 2 1

STRAP RESISTORS SHOULD BE PLACED CLOSE TO SOC All the straps are sampled on the rising edge of the
SSID = STRAP SHOULD BE PLACED OUTSIDE KOZ AREA
PMC_RSMRST_N signal (check list)

A16 Swap Flash Descriptor DFX Boot Halt Strap ICLK, USB2, DDI SFR ICLK SFR ICLK Xtal OSC CCU SUS RO RTC OSC
Description DDI0_Detected DDI1_Detected Override DSI Display Detected Boot BIOS Strap BBS Security Override & VISA Early POSM Debug Enable DFX Sus Debug Strap Supply Select Bypass POSM Select Bypass Bypass bypass

GPIO GPIO_SUS0 GPIO_SUS1 GPIO_SUS2 GPIO_SUS3 GPIO_SUS4 GPIO_SUS5 GPIO_SUS6 GPIO_SUS7 SEC_GPIO_SUS8 SEC_GPIO_SUS9 SEC_GPIO_SU10 GP_CAMERASB08 GP_CAMERASB09 GP_CAMERASB11
6/9 Allen modify precision 6/9 Allen modify precision 6/9 Allen modify precision
6/9 Allen modify precision 6/9 Allen modify precision 6/9 Allen modify precision
1D8V_S5 1D8V_S5 6/9 Allen modify precision 1D8V_S5 6/9 Allen modify precision 1D8V_S5 1D8V_S5 1D8V_S5 6/9 Allen modify precision 1D8V_S5 1D8V_S5 1D8V_S5 1D8V_S5 1D8V_S5 1D8V_S5
1D8V_S5 量量量量量 SC029
Change to stuff
1D8V_S5

1
(R_) (R_) (R_) (R_) (R_) (R_) (R_)

1
R1570 R1804 R1805 R1561 R1560 R1809 R1810 R1812 R1813 R1815 R1817 R1819 (R_)
R1562 4K7R2F-GP 10KR2F-2-GP 10KR2F-2-GP 100KR2F-L1-GP 100KR2F-L1-GP 10KR2F-2-GP 10KR2F-2-GP 10KR2F-2-GP 10KR2F-2-GP 10KR2F-2-GP 10KR2F-2-GP 10KR2F-2-GP R1818
4K7R2F-GP 10KR2F-2-GP
D D
Schematic

2
GPIO_SUS1 [17] GPIO_SUS2 [17] GPIO_SUS3 [17] INT_TP# [17] ME_FWP_SOC [17] SOC_RUNTIME_SCI# [17,99] SOC_EXTSMI_N [17] SEC_GPIO_SUS8 [17] SEC_GPIO_SUS9 [17] SEC_GPIO_SUS10 [17] OBSFN_C0 [8,99] GP_CAMERASB09 [8]
2

2
GP_CAMERASB11 [8]

1
GPIO_SUS0 (R_) (R_) (R_) (R_) (R_) (R_) (R_) (R_)
GPIO_SUS0 [17]

1
R1802 R1803 R1806 R1807 R544 SC030 R1808 R1811 R1565 R1814 R1816 R1559 R1558
1

10KR2F-2-GP 10KR2F-2-GP 10KR2F-2-GP 10KR2F-2-GP 4K7R2F-GP Change from 1K to 4K7 10KR2F-2-GP 10KR2F-2-GP 4K7R2F-GP 10KR2F-2-GP 10KR2F-2-GP 100KR2F-L1-GP 100KR2F-L1-GP R1557
R1801 100KR2F-L1-GP
10KR2F-2-GP TXE1

2
(R_) LPE_I2S2_DATAOUT_1 1

2
6/9 Allen modify precision 6/9 Allen modify precision 2
2

JOWLE-CON2-5-GP
(D_21.62874.102)

Weak internal pull-up Weak internal pull-up Weak internal pull-up

Normal Operation Normal 1.35V Bypass PMC
High DDI0 Detect DDI1 Detect DSI Detect Boot from SPI Normal Operation Normal with 1.05V Bypass Bypass Bypass

Change Boot Sus Debug enable 1.25V No bypass No bypass

Low Disable Disable Loader address Disable Boot from LPC Override Halt boot enable No bypass Fuse controller No bypass
(A16 Override) Weak internal pull-down Weak internal pull-down

LPE_I2S2_DATAOUT_1

2
R80267
0R2J-2-GP

D
P23 Q1205

1
2N7002H-GP
G (R_84.2N702.J31)
[24] SFD_GPIO

S
1A015

C C

B B

A A

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
CPU_(STRAP)
Size Document Number Rev
A1 Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 15 of 105

5 4 3 2 1
 5 4 3 2 1

SC032 hange to NC
CPU1F 6 OF 13
0R2J-2-GP 8/12 Richard 11/05 CHANGE TP 3PIN 21.61445.103
BRASWELL R1791 SWap USB for Length
B48 USB_OTG_ID 1 (R_) 2 1-2 CLR PASSWORD
Side IO B32 USB_OTG_ID C42
PASSWORD CLEAR
[35] USB30_TX_CPU_P0 USB3_TXP0 USB_DP0 F_USB0P [35]
C32 B42 F_USB0N [35] 2-3 NORMAL(DEFAULT)
[35] USB30_TX_CPU_N0 F28 USB3_TXN0 USB_DN0
[35] USB30_RX_CPU_P0 D28 USB3_RXP0 C43
Front USB(with 3.0)
[35] USB30_RX_CPU_N0 USB3_RXN0 USB_DP1 F_USB1P [35]
B44 F_USB1N [35] 1D8V_S5
A33 USB_DN1
[35] USB30_TX_CPU_P1 C33 USB3_TXP1 C41
[35] USB30_TX_CPU_N1 USB3_TXN1 USB_DP2 USB_DP2 [32]

2
F30 A41
[35] USB30_RX_CPU_P1 D30 USB3_RXP1 USB_DN2 USB_DN2 [32]
R89
[35] USB30_RX_CPU_N1 USB3_RXN1 C45 Rear USB(with RJ45) 10KR2J-3-GP
C34 USB_DP3 A45 USB_DP3 [32] PSWD1
USB3_TXP2 USB_DN3 USB_DN3 [32]
B34 R88 3
D USB3_TXN2 PW_CLEAR PW_CLEAR_H D

1
G32 B40 2 1 2
USB3_RXP2 USB_DP4 USB_CPU_PP4 [37]
J32 C40 USB2.0 HUB 0R0402-PAD

USB3.0

USB2.0
USB3_RXN2 USB_DN4 USB_CPU_PN4 [37] 1
C35 P16
A35 USB3_TXP3 USB_OC1# P14
USBOC02 [32] OC for Rear USB(with RJ45)
G34 USB3_TXN3 USB_OC0# USBOC01 [35] OC for Front USB(with 3.0) PIN-CON3-S-GP
J34 USB3_RXP3 B46 CPU_B46_R R1607 1 (R_) 2 49D9R2F-GP
USB3_RXN3 RSVD#B46 USB_VBUSSNS
SC033
Change to NC
B47 1D8V_S5
R1236 1 2 USB3_OBSP D34 USB_VBUSSNS A48 USB_RCOMP R1603 1 2 113R2F-GP
402R2F-GP USB3_OBSN F34 USB3_OBSP USB_RCOMP
USB3_OBSN SC031

1
M36 TP_M36 1 TP56 TPAD30
C37 USB_HSIC_0_STROBE N36 TP_N36 1 TP55 TPAD30 R1845
A37 RSVD#C37 USB_HSIC_0_DATA 05/27 20KR2J-L2-GP
F36 RSVD#A37 K38 TP_K38 1 TP53 TPAD30 EDS 0.91 from 49.9 modify to 45.3 5%, but PGD is 50. (R_)
D36 RSVD#F36 USB_HSIC_1_STROBE M38 TP_M38 1 TP54 TPAD30

HSIC

2
M34 RSVD#D36 USB_HSIC_1_DATA N38 USB_HSIC_RCOMP R1779 1 2 45D3R2F-L-GP
M32 RSVD#M34 USB_HSIC_RCOMP USB_VBUSSNS 1 (R_) 2USB_VBUSSNS_R

RESERVED
RSVD#M32 AD10 UART1_TX R1846 0R2J-2-GP
UART1_TXD

1
C38 AD12 UART1_RX Change to NC
B38 RSVD#C38 UART1_RXD AD13 TP_AD13 1 TP49 TPAD30
RSVD#B38 UART1_CTS#

UART
G36 AD14 TP_AD14 1 TP50 TPAD30 R1605
J36 RSVD#G36 UART1_RTS# 0R2J-2-GP
RSVD#J36 Y6 IO_SMI_N_C

2
N34 UART2_TXD Y7 PW_CLEAR 10/30 PD 0R as CRB
P34 RSVD#N34 1.8V UART2_RXD V9
RSVD#P34 UART2_CTS# V10
UART2_RTS#

BRASWELL-GP
(071.00BSW.0B0U)

5
CN2
SB5V ACES-CON4-37-GP
1 (D_)

UART1_TX 2
UART1_RX 3
C 4 C
For Resume SMBus

6
SB3V 1D8V_S5 1D8V_S5

1
SC035 SC034
R80146 R80145

G
Change from 1K to 10K 10KR2F-2-GP 2KR2F-3-GP Change from 1K to 2K2

2
IO_SMI_N D S IO_SMI_N_C
[24] IO_SMI_N

Q9637
DMN5L06K-7-GP

B B

A A

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
CPU_(USB/UART/GPIO)
Size Document Number Rev
C Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 16 of 105
5 4 3 2 1
 5 4 3 2 1

1D8V_S5 1D8V_S5 1D8V_S5

1
R561 R554 R556 Board ID Settings
10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP
(R_) (R_)
MB Version Board1 Board2 Board3

2
BOARD1 BOARD2 BOARD3
SA(X00) 0 0 0
SB(pre-X01) 0 0 1

1
(071.00BSW.0B0U)
CPU1E 5 OF 13 R557 R552 R553
10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP
SC(X01) 0 1 0
1A001 BRASWELL (R_)
XTAL19D2M_IN 1 R1240 2 0R0402-PAD-2-GP XTAL19D2M_IN_R P24
-1A(X02) 0 1 1

2
XTAL19D2M_OUT 1 R1241 2 0R0402-PAD-2-GP XTAL19D2M_OUT_R M22 OSCIN C11
D OSCOUT RSVD#C11 B10
-1(A00) 1 0 0 D
J26 RSVD#B10 F12
N26 RSVD#J26 RSVD#F12 F10
R1242 1 2 2K49R2F-GP ICLKICOMP P20 RSVD#N26 RSVD#F10
SC003 ICLKICOMP
R524 1 2 49D9R2F-GP ICLKRCOMP N20 iCLK RESERVED D12
C1601 P26 ICLKRCOMP RSVD#D12 E8
1 2 XTAL19D2M_IN K26 RSVD#P26 RSVD#E8 C7 1D8V_S5 1D8V_S5 1D8V_S5
M26 RSVD#K26 RSVD#C7 D6
XTAL-19D2MHZ-3-GP RSVD#M26 RSVD#D6
SC3D3P50V2CN-DL-GP (82.30071.131) AH45
RSVD#AH45
Skew ID Settings

1
J12
1

4 1 A9 RSVD#J12 F7 R567 R563 R558

R1239 C9 MF_PLT_CLK0 RSVD#F7 J14 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP
200KR2F-L-GP B8 MF_PLT_CLK1 RSVD#J14 L13 (R_) (G_)
MB Version SKEW1 SKEW2 SLEW3
B7 MF_PLT_CLK2 RSVD#L13

PLTFM CLK's
GPU 0 1 1

2
3 2 B5 MF_PLT_CLK3 AK6 I2C0_SCL SKEW1 SKEW2 SKEW3
2

B4 MF_PLT_CLK4 I2C0_SCL AH7 BOARD1

MF_PLT_CLK5 1.8V I2C0_SDA UMA 0 0 1

1
C1602 AF6 I2C1_SCL
X6 I2C1_SCL
1 2 XTAL19D2M_OUT AM40 AH6 BOARD2 R562 R560 R555
[99] DBG0 GPIO_DFX0 I2C1_SDA
AM41 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP
[99] DBG1 GPIO_DFX1 I2C2_SCL
SC3D3P50V2CN-DL-GP AM44 AF9 (U_) (R_)
[99] DBG2 AM45 GPIO_DFX2 I2C2_SCL AF7
SC003 BOARD3
[99] DBG3

2
GPIO_DFX3 I2C I2C2_SDA
XDP AM47

GPIO_DFX
Change from 8pF to 3.3pF [99] DBG4 AK48 GPIO_DFX4 AE4 CHAR_EN_CPU
[99] DBG5 GPIO_DFX5 I2C3_SCL
AM48 AD2
[99] DBG6 GPIO_DFX6 I2C3_SDA LPC_PME_N [24]
AK41
[99] DBG7 AK42 GPIO_DFX7 AC1 I2C4_SCL
[99] DBG16 GPIO_DFX8 I2C4_SCL AD3 SKEW1
AD51 I2C4_SDA
[15] GPIO_SUS0 GPIO_SUS0 I2C5_SCL
AD52 AB2
[15] GPIO_SUS1 GPIO_SUS1 I2C5_SCL
AH50 AC3 SKEW2
[15] GPIO_SUS2 AH48 GPIO_SUS2 I2C5_SDA
STRAP PIN
[15] GPIO_SUS3
AH51 GPIO_SUS3 AA1 I2C6_SCL SB3V 10/08 Change to 1D8V_S5
[15] INT_TP# AH52 GPIO_SUS4 I2C6_SCL AB3 SKEW3 SMBus Level Shift

GPIO_SUS
[15] ME_FWP_SOC GPIO_SUS5 I2C6_SDA
AG51
[15,99] SOC_RUNTIME_SCI# GPIO_SUS6

1
AG53 AA3 NFC_SCL
[15] SOC_EXTSMI_N AF52 GPIO_SUS7 I2C_NFC_SCL Y2 NFC_SDA CHAR_EN [35]
R80143
[15] SEC_GPIO_SUS9 SEC_GPIO_SUS9 I2C_NFC_SDA SB3V 1D8V_S5 1D8V_S5
C AF51 1KR2J-1-GP C
For Resume SMBus [15]
[15]
SEC_GPIO_SUS8
SEC_GPIO_SUS10
AE51 SEC_GPIO_SUS8
SEC_GPIO_SUS10 MF_SMB_CLK
AM6 SMB0_CLK_C
SMB0_DATA_C
(R_)
AC51 SMBUS AM7 3 (R_)
[64] FP_CBL_DET

2
SEC_GPIO_SUS11 MF_SMB_DATA

1
GPIO0_RCOMP AH40 AM9 SMB0_ALERT#_C Q9636B
TP4127 1 GPIO_ALERT_Y3 Y3 GPIO0_RCOMP MF_SMB_ALERT# CHAR_EN_CPU_B 5 MMBT3904DW-1-GP R1741 R1739

G
TPAD30 GPIO_ALERT 1KR2J-1-GP 1KR2J-1-GP
1

1D8V_S5
R80152 4

2
R802471 2 10KR2J-3-GP FP_CBL_DET 100R2F-L1-GP-U BRASWELL-GP SMB0_CLK_RESUME D S SMB0_CLK_C
6 (R_)
SB001 Q9636A Q1204
2

2 MMBT3904DW-1-GP DMN5L06K-7-GP

SB3V 1D8V_S5 1D8V_S5

SMBus Isolation CHAR_EN_CPU [55]

1
SB5V VCC
-1001 R1740 R1738

G
1KR2J-1-GP 1KR2J-1-GP
1

2
R1687 R1688 SMB0_DATA_RESUME SMB0_DATA_RESUME D S SMB0_DATA_C
8K2R2J-3-GP 8K2R2J-3-GP
SMBUS Q1203
D

Q1213 VCC3 DMN5L06K-7-GP

[61,77] SMB0_DATA_RESUME
2

DMN5L06K-7-GP
[61,77] SMB0_CLK_RESUME
PWRGD_3V_C [61] SMB0_ALERT#
G
[12,37,55,77] SMB0_CLK_MAIN
1

[12,37,55,77] SMB0_DATA_MAIN
R1745
1KR2J-1-GP
S

For Resume SMBus

2

SMB0_DATA_MAIN 6/3 Allen modify

C

B PWRGD_3V_B B SB3V 1D8V_S5 1D8V_S5 B

Q6714 PC5255 (R_) 1D8V_S5
LMBT3904LT1G-GP SMB0_CLK_RESUME SCD1U10V2KX-4DLGP
I2C0_SCL R1792 1 (R_) 2 1KR2J-1-GP
E

I2C1_SCL R1793 1 (R_) 2 1KR2J-1-GP

D

1
Q1212 VCC3 I2C2_SCL R1794 1 (R_) 2 1KR2J-1-GP
Q1214 DMN5L06K-7-GP R1742 CHAR_EN_CPU R1795 1 2 1KR2J-1-GP -1001

1
2N7002H-GP 1KR2J-1-GP I2C4_SCL R1796 1 (R_) 2 1KR2J-1-GP
PWRGD_3V G (84.2N702.J31) G R1743 I2C5_SCL R1797 1 (R_) 2 1KR2J-1-GP
[18,24] PWRGD_3V

G
1

1KR2J-1-GP Q1210 I2C6_SCL R1798 1 (R_) 2 1KR2J-1-GP

2
R1744 DMN5L06K-7-GP NFC_SCL R1799 1 (R_) 2 1KR2J-1-GP
S

1KR2J-1-GP NFC_SDA R1800 1 (R_) 2 1KR2J-1-GP

S

2
PC5243 SMB0_ALERT# D S SMB0_ALERT#_C
SCD1U10V2KX-4DLGP
2

(R_) (R_) (R_)

1
SMB0_CLK_MAIN PC5254 PC5251
SCD1U10V2KX-4DLGP SCD1U10V2KX-4DLGP
1

PC5256 (R_)
2

2
SCD1U10V2KX-4DLGP
6/10 Allen modify
2

A A

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
CPU_(GPIO/STRAP/I2C/SMB)
Size Document Number Rev
C Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 17 of 105
5 4 3 2 1
 5 4 3 2 1

Clock 32.768k
1D8V_S5 PCH_RTCX2
X7
R457 1 2 51R2J-2-GP XDP_H_TDI
R473 1 2 51R2J-2-GP XDP_H_TDO 1 2 RTCX_L 4 1 PCH_RTCX1
R458 1 2 51R2J-2-GP XDP_H_TMS R1261
R1746 1 2 51R2J-2-GP TAP_PREQ# 0R0402-PAD-2-GP

XDP_H_TCK
1A001
R466 1 2 51R2J-2-GP 3 2
R456 1 2 51R2J-2-GP XDP_H_TRST_N

XTAL-32D768KHZ-67-GP

D D
1 (R_) 2 EDM_SOC
R1257 10KR2J-3-GP
(071.00BSW.0B0U) R81 2 1 10MR3F-GP
CPU1G 7 OF 13
0814 Richard
BRASWELL C1619
XDP

1
VCC3 AF42 M18 PCH_RTCX1 C1618
SC036

JTAG/ITP
[99] XDP_H_TCK AD47 TCK BRTCX1_PAD K18 PCH_RTCX2 S
SC4P50V2CC-1-DL-GP C
LPC_CLKRUN# [99] XDP_H_TDI TDI BRTCX2_PAD BVCCRTC_EXTPAD Change from 6pF to 4pF 4
1 2 AF40 F16 C49 1 2SCD1U16V2KX-3DLGP P

2
R79662 10KR2J-3-GP [99] XDP_H_TDO AD48 TDO BVCCRTC_EXTPAD 5
Change to stuff [99] XDP_H_TMS AB48 TMS D18 PCH_SRTCRSTB_PULLUP
SC004 0 SC004
V

RTC
[99] XDP_H_TRST_N TRST# SRTCRST# PCH_SRTCRSTB_PULLUP [99] 2
G16 C
1 2 RCOMP_LPC_HVT COREPWROK F18 COREPWROK [99] C-
RSMRST# RSMRST_N [24,99] 1-
R1259 100R2F-L1-GP-U AD45 J16 PCH_RTCRST_PULLUP D
[99] TAP_PRDY# CX_PRDY# RTEST# RTC_INTRUDER L-
AF41 G18 R1851 1 2 10KR2J-3-GP 8/14 Richard Follow EDS
[99] TAP_PREQ# EDM_SOC CX_PREQ# RSVD_VSS#G18 G
M13 P
RSVD#M13 AE3 SUS_PWR_ACK_CPU_R R1697 1 (R_) 2 0R2J-2-GP
R664 1 2 0R0402-PAD-2-GP LPC_CLK0_R P2 SUSPWRDNACK D14 PMC_SUS_STAT 1 SUS_PWR_ACK_CPU [24]
[24] CK_25M_SIO LPC_CLK1_R MF_LPC_CLKOUT0 SUS_STAT# SUSCLK_SIO_C TP35 5/13 Allen modify
R1571 1 2 0R0402-PAD-2-GP R3 C15 1
TP100

1
LPC_CLKRUN# T3 MF_LPC_CLKOUT1 PMU_SUSCLK C12
C80 (R_) P3 LPC_CLKRUN# PMU_SLP_S4# B14 PM_SLP_S4#_CPU [24,92]
-1010 [24,68] LFRAMEJ_FW4 LPC_FRAME# PMU_SLP_S3# PM_SLP_S3#_CPU [24,92] 5/13 Allen modify
SC100P50V2JN-3GP AF2

LPC
2
M3 PMU_RESETBUTTON# F14 PLT_RST#_CPU PSTBTN_N [79,99]
LPC [24,68] LAD0_FWH0
M2 MF_LPC_AD0 PMU_PLTRST# PMC_BATLOW#

PMU
[24,68] LAD1_FWH1 C14
N3 MF_LPC_AD1 PMU_BATLOW# C13 AC_PRESENT_CPU
[24,68] LAD2_FWH2 MF_LPC_AD2 PMU_AC_PRESENT SLP_SLP_S0#_CPU
1A001
N1 A13
[68] LPC_CLK1 [24,68] LAD3_FWH3 MF_LPC_AD3 PMU_SLP_S0IX# PMU_SLP_LAN_N SLP_SLP_S0#_CPU [92]
B12 1
TP129

1
C84 RCOMP_LPC_HVT T4 PMU_SLP_LAN# N16 WAKE_N_APU R1263 1 2 0R0402-PAD-2-GP
LPC_HVT_RCOMP PMU_WAKE# APU_PWNBTN_N APU_PWNBTN_N_R PCIE_WAKE#_CPU [92]
SC100P50V2JN-3GP [24] INT_SERIRQ_CPU T2 M16 R1264 1 2 0R0402-PAD-2-GP
(R_) ILB_SERIRQ PMU_PWRBTN# P18 PMU_WAKE_LAN_N 1
TP130
2
1 PWM0 H5 PMU_WAKE_LAN#

PWM
TPAD30 TP131 PWM0 APU_PWNBTN_N [99]
TPAD30 TP132 1 PWM1 H7 AD42
PWM1

SVID
SVID0_CLK AD41 VR_SVID_CLK [54] 5/26 Allen modify
SVID0_DATA AD40 VR_SVID_DATA [54] Checklist PU 20K.
P28 SVID0_ALERT# VR_SVID_ALERT# [54] PDG & CRB 200, 60.
P30 RSVD#P28 1A001
AF50 RSVD#P30 VCC0_SENSEN_CPU_P

Voltage sense
C AG32 R1584 1 2 0R0402-PAD-2-GP C
AF48 RSVD#AF50 CORE_VCC0_SENSE AJ32 VCC0_SENSEN_CPU_N 1 2 0R0402-PAD-2-GP VCC0_SENSEN_P [18,45]
R1585

Reserved
-1010 RSVD#AF48 CORE_VSS0_SENSE VCC1_SENSEN_CPU_P VCC0_SENSEN_N [18,45]
AF44 AD29 R1586 1 2 0R0402-PAD-2-GP
RSVD#AF44 CORE_VCC1_SENSE VCC1_SENSEN_CPU_N VCC0_SENSEN_P [18,45]
R1258 AF45 AF27 R1587 1 2 0R0402-PAD-2-GP
1 2 APU_PROCHOT#_R AD50 RSVD#AF45 CORE_VSS1_SENSE AD24 VGG_SENSEN_CPU_P 1 2 0R0402-PAD-2-GP VCC0_SENSEN_N [18,45]
[45,46] APU_PROCHOT# R1588
PROCHOT# DDI_VGG_SENSE VGG_SENSEN_CPU_N VGG_SENSEN_P [46]
0R0402-PAD-2-GP AD22 R1589 1 2 0R0402-PAD-2-GP
UNCORE_VSS_SENSE2 AC27 VNN_SENSEN_CPU 1 2 100R2J-2-GP VGG_SENSEN_N [46]
PR9766 1P05V_A
UNCORE_VSS_SENSE1
1
C313 (64.10005.6DL)
SC47P50V2JN-3GP
(R_) 8/14 Richard modify 10mil trace
2

BRASWELL-GP 1-2 CLEAR CMOS 11/05 CHANGE TP 3PIN 21.61445.103

2-3 NORMAL MODE CLEAR CMOS SC037

V_3P0_BAT_VREG R87 1 2 20KR2F-L-GP PCH_RTCRST_PULLUP R85 1 2 0R2J-2-GP
1D8V_S5
Jeffrey 0703
SB3V Debug Only

CMCLR_P2
1
C50
SYS_PWRGD [39,79] SUS_PWR_ACK_CPU_R R499 2 1 10KR2J-3-GP SC1U10V2KX-1DLGP
1

AC_PRESENT_CPU R1262 2 1 10KR2J-3-GP

2
R717 PMC_BATLOW# R492 1 2 20KR2J-L2-GP
10KR2J-3-GP PSTBTN_N R1208 2 1 2KR2F-3-GP
D

CMCLR1
SC038 3
2

Q79 PDG r1p2 write pull-up 150~3K R91 1 2 20KR2F-L-GP PCH_SRTCRSTB_PULLUP R86 1 (R_) 2 0R2J-2-GP 2
SYS_PWRGD_G V_3P0_BAT_VREG
G 2N7002H-GP
(84.2N702.J31) CMCLR_P1 1

1
C52
S

1
1D8V_S0 SC1U10V2KX-1DLGP PIN-CON3-S-GP
D

R92

2
PSTBTN_N R1266 2 (R_) 1 0R0402-PAD-2-GP CLEAR CMOS JP
Q78 10KR2J-3-GP
1 2 SLP_S3_N_G G 2N7002H-GP
[24,35,40,46,48,53,92,99] SLP_S3_N

2
R1669 (84.2N702.J31) VCC3 PGD write S0 power
0R0402-PAD-2-GP
S

1A001 R94 1 2 RSMRST_N

1

B B
100KR2J-1-GP
PWRGD_3V_D 1D8V_S5 1D8V_S5
R184
10KR2J-3-GP
R181 1 2 COREPWROK V_3P3_A

1
100KR2J-1-GP
D

R56 R55

2
10KR2J-3-GP 2K2R2J-2-GP
Q77 SYS_PWRGD R178 2 1 COREPWROK R1265 2 (R_) 1 AC_PRESENT_CPU R57
1 2 PWRGD_3V_G G 2N7002H-GP 0R0402-PAD-2-GP 10KR2J-3-GP 10KR2J-3-GP

B 2
[17,24] PWRGD_3V SIO_PWNBTN_B
R1668 (84.2N702.J31) Jeffrey 0703 (R_)
2

0R0402-PAD-2-GP C111
S

1
1A001 SCD1U16V2KX-3GP
APU_PWNBTN_N_R C E
(R_) SIO_PWNBTN_N [24,99]
1

Q18
MMBT3904-4-GP
(84.T3904.H11) R1260 1 (R_) 2 0R2J-2-GP
PWRBTN_N [24,64]

VCC3
V_3P3_A

1
1
R64
R65 1KR2J-1-GP
1D8V_S5 10KR2J-3-GP
-1011 For x1 / NGFF / debug card / SIO

2
1A018
2
1

PLTRST_N [24,68]
R72 3
2K2R2J-2-GP Q20B
(R_) PLT_RST#_D 5 MMBT3904DW-GP
(75.03904.07C)
2

6 4
A R75 A
PLT_RST#_CPU 2 1 PLT_RST#_CPU_G 2 Q20A
[99] PLT_RST#_CPU MMBT3904DW-GP
10KR2J-3-GP (75.03904.07C)
1

Vinafix.com
<Variant Name>
1

(R_) (R_)
C42 C44
SCD01U25V2KX-3GP SC150P50V2KX-1-GP Wistron Incorporated
2

21F, 88, Hsin Tai Wu Rd

Hsichih, Taipei
Title
CPU_(LPC/SIDEBAND/JTAG)
Size Document Number Rev
C Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 18 of 105
5 4 3 2 1
 5 4 3 2 1

X2 GPU CPU1D 4 OF 13

PCIEX2 [76] PEG_TXP0

(G_) C325 2
(G_) C322 2
1 SCD1U16V2KX-3DLGP P_GFX_TXP0
1 SCD1U16V2KX-3DLGP P_GFX_TXN0
C24
B24 PCIE_TXP0
BRASWELL
SATA_TXP0
C31
B30 SATAHDR_TX_DP0 [60]
[76] PEG_TXN0 PCIE_TXN0 SATA_TXN0 SATAHDR_TX_DN0 [60]
[76] PEG_RXP0 G20 N28 SATAHDR_RX_DP0 [60] HDD
[76] PEG_TXP[0..1] J20 PCIE_RXP0 SATA_RXP0 M28
[76] PEG_TXN[0..1] [76] PEG_RXN0 PCIE_RXN0 SATA_RXN0 SATAHDR_RX_DN0 [60]
GPU C29
SATA_TXP1 SATAHDR_TX_DP1 [60]
(G_) C324 2 1 SCD1U16V2KX-3DLGP P_GFX_TXP1 A25 A29
[76] PEG_TXP1 1 SCD1U16V2KX-3DLGP P_GFX_TXN1 PCIE_TXP1 SATA_TXN1 SATAHDR_TX_DN1 [60]
(G_) C328 2 C25 J28 ODD
D [76] PEG_RXP[0..1] [76] PEG_TXN1 PCIE_TXN1 SATA_RXP1 SATAHDR_RX_DP1 [60] D
[76] PEG_RXP1 D20 K28
[76] PEG_RXN[0..1] F20 PCIE_RXP1 SATA_RXN1 SATAHDR_RX_DN1 [60]
[76] PEG_RXN1 PCIE_RXN1 AH3 CPU_SATA_LED_N
SATA_LED# CPU_SATA_LED_N [64]
C54 2 1 SCD1U16V2KX-3DLGP C_GPP_TXP2 B26 AH2 GPIO
[61] HSO_C_DP2 2 1 SCD1U16V2KX-3DLGP C_GPP_TXN2 C26 PCIE_TXP2 SATA_GP0 AG3 CPU_CHAR_CTL3 [35]
C56 SATA
[61] HSO_C_DN2 D22 PCIE_TXN2 PCIe SATA_GP1 AG1
WLAN [61] HSI_C_DP2 PCIE_RXP2 SATA_GP2
GPIO CHASSIS_ID_0 [64]
F22 AF3 GPIO
[61] HSI_C_DN2 PCIE_RXN2 SATA_GP3 CHASSIS_ID_1 [64]

[31] HSO_C_LAN_DP3 C315 2 1 SCD1U16V2KX-3DLGP HSO_LAN_DP3 A27 N30 SATA_RCOMP_DP R519 2 1 402R2F-GP
C316 2 1 SCD1U16V2KX-3DLGP HSO_LAN_DN3 C27 PCIE_TXP3 SATA_OBSP M30 SATA_RCOMP_DN
[31] HSO_C_LAN_DN3 PCIE_TXN3 SATA_OBSN
GLAN G24
[31] HSI_LAN_DP3 J24 PCIE_RXP3 W3
[31] HSI_LAN_DN3 PCIE_RXN3 FST_SPI_CLK SPI_CLK [25]
PCIE_CLKREQ_0 AM10 V4
R510 2 1 10KR2J-3-GP PCIE_CLKREQ_0 AM12 PCIE_CLKREQ0# FST_SPI_CS0# V6 SPI_CS0_N [25]
1D8V_S5 PCIE_CLKREQ1# FST_SPI_CS1#
AK14 V7
R1782 1 2 10KR2J-3-GP PCH_PCIECLKRQ2_N [61] PCH_PCIECLKRQ2_N AM14 PCIE_CLKREQ2# FST_SPI_CS2#
[31] LANCLK_REQ_N PCIE_CLKREQ3#
SPI
V2
FST_SPI_D0 SPI_DATAOUT [25]
A21 V3
[76] CK_PE_100M_16PORT_DP C21 CLK_DIFF_P_0 FAST SPI FST_SPI_D1 U1 SPI_DATAIN [25]
GPU [76] CK_PE_100M_16PORT_DN CLK_DIFF_N_0 FST_SPI_D2 SPI_IO2 [25]
C19 U3
B20 CLK_DIFF_P_1 FST_SPI_D3 SPI_IO3 [25]
C18 CLK_DIFF_N_1 AF13 AZ_RST_N_M
[61]
CK_PCIEX1_WLAN_DP B18 CLK_DIFF_P_2 MF_HDA_RST# AD6
C WLAN [61]
CK_PCIEX1_WLAN_DN CLK_DIFF_N_2 MF_HDA_SDI1 C
C17 AD9 AZ_BCLK_M
GLAN [31] CK_GLAN_DP A17 CLK_DIFF_P_3
CLK_DIFF_N_3
MF_HDA_CLK
MF_HDA_SDI0
AD7 AUD_LINK_SDIN HDA
CLK_DIFF_P4 [31] CK_GLAN_DN C16 AF12 AZ_SYNC_M AUD_LINK_SDIN [27]
R1267 1 (R_) 2 0R2J-2-GP CLK_DIFF_N4 B16 CLK_DIFF_P_4 MF_HDA_SYNC AF14 AZ_SDOUT_M
CLK_DIFF_N_4 MF_HDA_SDO AB9
R513 2 1 402R2F-GP PCIE_OBS_DP D26 MF_HDA_DOCKEN# AB7
PCIE_OBS_DN F26 PCIE_OBSP MF_HDA_DOCKRST#
PCIE_OBSN H4
V14 AUDIO SPKR APU_SPKR [27]
Y13 SPI1_CLK AK9
Y12 SPI1_CS0# SPI
GP_SSP_2_CLK AK10
V13 SPI1_CS1# GP_SSP_2_FS AK12
V12 SPI1_MISO GP_SSP_2_TXD AK13
SPI1_MOSI GP_SSP_2_RXD

BRASWELL-GP
0819 modify Jeffrey SWAP
(071.00BSW.0B0U)
RN10
1 8 AZ_SYNC_M
[27] AUD_LINK_SYNC
2 7 AZ_RST_N_M
[27] AUD_LINK_RST_N
3 6 AZ_SDOUT_M
[27] AUD_LINK_SDO
4 5 AZ_BCLK_M
[27] AUD_LINK_BCLK
B B
SRN75J-3-GP

1
(R_)
C86
SCD01U25V2KX-3GP

2
5/13 Allen modify Cap location is same as CRB

SPI

<Variant Name>
A A
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
CPU_(CLK/SATA/PCIE/SPI/HDA)
Size Document Number Rev
B Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 19 of 105
5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
A A
12F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title

Size Document Number Rev

A4 Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 20 of 105

5 4 3 2 1
 5 4 3 2 1

(071.00BSW.0B0U)
DDR_VDDQ VCCSFRPLLDDR_1P24_1P35 CPU1I 9 OF 13
R1245
1 2 BRASWELL
0R0603-PAD VCCSFRPLLDDR_1P24_1P35 AN27 V36 1D24V_S5
AM25 DDRSFR_VDDQ_G_S4 DDI_VDDQ_G31 Y36
DDR_VDDQ VCCCLKDDR_1P24_1P35 VCCCLKDDR_1P24_1P35 DDR_VDDQ_G_S42 DDI_VDDQ_G32
R1244 DDR_VDDQ BE1 T40 1D24V_S5
D
1 2 BE53 DDR_VDDQ_G_S416 MIPI_V1P2A_G32 P40 D
0R0603-PAD BJ2 DDR_VDDQ_G_S419 MIPI_V1P2A_G31
BJ3 DDR_VDDQ_G_S426 Y27
SB3V
-1010 VCCPADCF3SI0_1P8_3P3 DDR_VDDQ_G_S427 ICLK_VSFR_G32 1D24V_S5
BJ49 Y25
BJ5 DDR_VDDQ_G_S428 ICLK_VSFR_G31
1 2 BH50 DDR_VDDQ_G_S429 P38
SD3 IO SUPPLY DDR_VDDQ_G_S425 CORE_VSFR_G35 1D24V_S5
R80276 0R3J-0-U-GP BH5 V30
DDR_VDDQ_G_S424 CORE_VSFR_G36

DDR
BH49 AC30
VCC3 BH4 DDR_VDDQ_G_S423 PCIE_V1P05A_G31#AC30
BE3 DDR_VDDQ_G_S422
1 (R_) 2 BG51 DDR_VDDQ_G_S417 AF35
DDR_VDDQ_G_S421 CORE_VSFR_G34 1D24V_S5
R1246 0R3J-0-U-GP BG3 AD35
BJ51 DDR_VDDQ_G_S420 CORE_VSFR_G32 AD38
SB3V VCCPADCF1SI0_1P8_3P3 BJ52 DDR_VDDQ_G_S430 CORE_VSFR_G33 AC36
R1247 AY10 DDR_VDDQ_G_S431 CORE_VSFR_G31
LPC IO SUPPLY DDR_VDDQ_G_S414
1 2 AY44
0R0603-PAD AV44 DDR_VDDQ_G_S415 M41
DDR_VDDQ_G_S413 USBHSIC_V1P2A_G3 1D24V_S5
C -1010 AV10 U35 1D24V_S5 C
BE51 DDR_VDDQ_G_S410 USB_VDDQ_G32 V35

USB
1D5V_S0 VCCCFIOAZA_1P80 AV38 DDR_VDDQ_G_S418 USB_VDDQ_G33 H44
DDR_VDDQ_G_S412 USB_VDDQ_G31 1D24V_S5
AV16 P41 1D24V_S5
1 2 AU36 DDR_VDDQ_G_S411 USBSSIC_V1P2A_G3
AUDIO IO SUPPLY DDR_VDDQ_G_S49
R1248 0R3J-0-U-GP AU18 AA29 VCCUSB2_1P8
AN36 DDR_VDDQ_G_S48 USB_V1P8A_G3
1D8V_S5 AN35 DDR_VDDQ_G_S47 C23
DDR_VDDQ_G_S46 USB_V3P3A_G32 VCCUSB2_3P3
AN19 B22
1 (R_) 2 AN18 DDR_VDDQ_G_S45 USB_V3P3A_G31
R1249 0R3J-0-U-GP AM36 DDR_VDDQ_G_S44
AM18 DDR_VDDQ_G_S43 C5
DDR_VDDQ_G_S41 RTC_V3P3RTC_G52 VCCRTC_3P3
B6

RTC
RTC_V3P3RTC_G51 D4
RTC_V3P3A_G51 VCCRTCSUS_3P3
-1010 VCCPADCF3SI0_1P8_3P3 E1 E3
1D8V_S5 VCCPADCF2SI0_E_1P80 E2 SDIO_V3P3A_V1P8A_G31 RTC_V3P3A_G52
R1250 G1 SDIO_V3P3A_V1P8A_G32 U16
VCCPADCF1SI0_1P8_3P3 SDIO_V3P3A_V1P8A_G33 FUSE_V1P8A_G3 V1P8_FUSE
1 2 VCCCFIOAZA_1P80 AH4
B UNCORE_V1P8A_G32 B

FUSE
0R0603-PAD AF4 H10 1P05V_S5
VCCPADCF1SI0_1P80 Y18 UNCORE_V1P8A_G31 FUSE1_V1P05A_G4 G10
VCCPADCF2SI0_E_1P80 GPIO_V1P8A_G35 FUSE0_V1P05A_G3
R1251 AD33 A3
1 2 AK18 GPIO_V1P8A_G31 RSVD_VSS#A3 K20
VCCPADCF1SI0_1P80 GPIO_V1P8A_G33 RSVD#K20
0R0603-PAD AF33 M20
VCCUSB2_1P8 AK19 GPIO_V1P8A_G32 RSVD#M20
R1252 GPIO_V1P8A_G34
1 2
0R0603-PAD
V1P8_FUSE BRASWELL-GP
VCCUSB2_3P3
-1010 SB3V
R1253
1 2 R1256
0R0603-PAD 1 2
0R0603-PAD
Wistron Incorporated
V_3P0_BAT_VREG VCCRTC_3P3 12F, 88, Hsin Tai Wu Rd
A R1255 A
Hsichih, Taipei
1 2
0R0603-PAD Title

VCCRTCSUS_3P3 SB3V CPU_(POWER1)

R1254 Size Document Number Rev
1 2 A Rosa_Lily SFF -1
0R0603-PAD
Date: Tuesday, June 23, 2015 Sheet 21 of 105
5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
A A
12F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title

Size Document Number Rev

A4 Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 22 of 105

5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
A 12F, 88, Hsin Tai Wu Rd A
Hsichih, Taipei
Title

Size Document Number Rev

A4 Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 23 of 105

5 4 3 2 1
 5 4 3 2 1

L52 1 2 BLM18SG121TN1D-GP SIO_AVCC3

VCC3
(68.00206.021)

1
C223

1
SB003 C807 SC1U6D3V2KX-DLGP
R501 SC10U10V3MX-1-GP

2
220R5J-GP SB014
V_3P3_A

2
SIO_PSON_D For CX mount, R80210/R80212 mount, R80211/R80213 unmount
R80210 1 (R_) 2 0R2J-2-GP PM_SLP_S3#_CPU

D
PM_SLP_S3#_CPU [18,92]

1
C225
U67 C808 SCD1U16V2KX-3DLGP SIO_SLP_S3_N R80211 1 2 0R2J-2-GP SLP_S3_N
SLP_S3_N [18,35,40,46,48,53,92,99]
2N7002K-2-GP SC10U10V3MX-1-GP

2
R80212 1 (R_) 2 0R2J-2-GP PM_SLP_S4#_CPU SIO_VIN5 1.997V R915 1 2 10KR2F-2-GP
PM_SLP_S4#_CPU [18,92] V_5P0_A

1
SIO_SLP_S4_N R80213 1 2 0R2J-2-GP SLP_S4_N
SLP_S4_N [32,34,35,39,48,64,92,99]

1
C815 R930
SCD1U16V2KX-3DLGP 6K65R2F-GP

2
D U5 D

2
1
C228 SC005
SIO_PSON_N SCD1U16V2KX-3DLGP 53 1 CPU_FAN_TACH_SIO Change R915 from 5K1 to 10K
AVCC3 FAN_TAC2/GP52 CPU_FAN_CTRL_SIO CPU_FAN_TACH_SIO [26] 1D8V_S0 Change R930 from 5K1 to 6K65
2 SB013

2
11 FAN_CTL2/GP51 CPU_FAN_CTRL_SIO [26]
For CX mount SIO_GND
SIO_VCORE 3VSB SYS_FAN_TACH_SIO
1A007
12 3
VCORE FAN_TAC3/GP37 SYS_FAN_CTRL_SIO SYS_FAN_TACH_SIO [26]
VBAT2 30 4
VBAT FAN_CTL3/GP36 SYS_FAN_CTRL_SIO [26]

1
SIO_VIN2 2.0V R517 1 2 10KR2F-2-GP
VCC12

1
C809 39 MDAT R508 1 2 10KR2J-3-GP VCC3 C12385 (R_) C12384 (R_)
FAN_TAC4/GP57/MDAT

1
1 TP_SIO_VIN0 52 40 MCLK R514 1 2 10KR2J-3-GP SC10U10V3MX-1-GP SCD1U16V2KX-3DLGP
SC1U6D3V2KX-DLGP TP125 SB017

2
VIN0/VCORE_0D8V FAN_CTL4/GP56/MCLK

1
1 TP_SIO_VIN1 51 C233 R916 Change value from 1K to 10Kohm
TP126

2
SIO_VIN2 50 VIN1/VDIMM_STR_1D2V 63 SIO_GPU_RST_R R2409 1 2 0R2J-2-GP SIO_GPU_RST SCD1U16V2KX-3DLGP 2KR2F-3-GP
SIO_VIN4 VIN2_+12_SEN CTS1#/GP31/FAN_TAC5 SIO_GPU_EN_N R2415 1 SIO_GPU_RST [76]
49 61 2 0R2J-2-GP SIO_GPU_EN
SIO_GPU_EN [56,87]

2
SIO_VIN5 48 VIN4/VLDT_12/5VSB_SEN DCD1#/GP33/FAN_CTL5
Place close to pin24

2
1 TP_SIO_VIN6 47 VIN5/5VDUAL
TP127 VIN6 KBRST_N
20
1 2 SIO_REF 46 KRST#/GP62 21 A20GATE SIO_GND
SIO_GND VREF GA20
C813 SC1U6D3V2KX-DLGP -1010
CPU_THERMDA+ 45 SIO_VIN4 1.997V R914 1 2 10KR2F-2-GP
HMT SYS_THERMDA+ 44 TMPIN1 42 RSMRST_SIO_N R1592 1 2 0R0402-PAD-2-GP RSMRST_N SB5V
TMPIN2 RSMRST#/GP55 RSMRST_N [18,99]

1
28 SYS_3VSB R923 1 2 100R2F-L1-GP-U
SYS_3VSB SB3V

1
R500 1 2 1KR2J-1-GP COPEN_N 29 35 SIO_PSON_N C814 R929
Reset Buffer Input COPEN# PSON# PWRBTN_N SIO_PSON_N [43]
34 SCD1U16V2KX-3DLGP 6K65R2F-GP
PANSWH# SIO_SLP_S3_N PWRBTN_N [18,24,64]
R337 2 1 33R2J-2-GP 31
[18,68] PLTRST_N

2
LAD0_FWH0 16 SUSB# 36 SIO_SLP_S4_N
[18,68] LAD0_FWH0

2
LAD0 SUSC#/GP53

1
LAD0_FWH1 17 6 SIO_ATXPG SC005
[18,68] LAD1_FWH1 LAD0_FWH2 LAD1 ATXPG/GP30 PWROK3_1_R
C571 (R_) [18,68] LAD2_FWH2 18 37 SC066 Change R915 from 5K1 to 10K
SCD1U10V2MX-3DLGP LAD0_FWH3 19 LAD2 PWRGD3/CPU_PG/SDA0 Change R929 from 5K1 to 6K65
[18,68] LAD3_FWH3

2
LAD3 R80183 1 (R_) 2 0R2J-2-GP EVAL_PWRGD SIO_GND
PLTRST*_SIO 13 64 SLP_SUSB EVAL_PWRGD [86] 1D8V_S0 For BX/CX change
SER_IRQ 14 LRESET# VLDT_EN/SLP_SUS#/GP63 7 DPWROK R80264 1 2 0R2J-2-GP LAN_DISABLE_N
LFRAMEJ_FW4 SERIRQ DPWROK/GP23 SUS_PWR_ACK_CPU LAN_DISABLE_N [31]
15 9
[18,68] LFRAMEJ_FW4 LFRAME# SUSACK#/PWRGD1 SUS_PWR_ACK_CPU [18]

2
CK_25M_SIO 22 55 SUS_WARNB R80265 1 2 0R2J-2-GP MINI_POWER_CTRL
[18] CK_25M_SIO LPC_PME_N PCICLK VCORE_EN/GP42/PCH_C0B/SUSWARN# MINI_POWER_CTRL [61]
SERIRQ Level Shift (Only for BX) 33 R2414 R2414 BX Un_mount, CX mount
[17] LPC_PME_N PME#/GP54 Change R80183 to NC 0R2J-2-GP
1D8V_S0 VCC3 1D8V_S0 41 PCIRST3# Add R80264 (R_) R2430
SIO_JP2 56 PCIRST3#/CIRRX1/GP10 5 SYS_EUP_CTRL Add R80265 0R2J-2-GP VCC3

1
SIO_SUSLED_N 57 RTS1#/JP2 5VSB_CTRL#/GP13 24 CLK_48M_SIO_C 2 1 CK_48M_SIO
[64] SIO_SUSLED_N
1

SIO_JP3 58 DSR1#/GP45/PCH_D0A CLKIN 25 SIO_MEM_EVENT_L R80151 2 (R_) 1 10KR2F-2-GP

SIO_MEM_EVENT_L [12]
1

1
SOUT1/JP3 GPA1

2
R645 C522 C523 59 R2430 CX Un_mount, BX mount GP63/DIOD8
[64] 5V_LED SIO_JP4 SIN1/GP41
10KR2J-3-GP SCD1U10V2KX-5DLGP SCD1U10V2KX-5DLGP 60 V_3P3_A
NGFF_BT_DISABLE 62 DTR1#/JP4 R2413
2

2
[61] NGFF_BT_DISABLE RI1#/GP32 23 SIO_JP1 SLP_SUSB R80184 1 2 10KR2J-3-GP
U35 1KR2J-1-GP R2413 CX Un_mount, BX Un_mount DI SC067
2

GPO50/JP1 32 SW_ON_N_SIO (R_) Change R80151 to NC

1
6 1 ADAPTOR_PSID_SIO 26 PWRON# SUS_WARNB R2421 2 1 10KR2J-3-GP Change R80184 to STUFF
INT_SERIRQ_OE VCCB VCCA [42] ADAPTOR_PSID_SIO SFD_GPIO SST/AMDTSI_D/PCH_D1/GP43 Change R2421 from 1K to 10K
5 2 27 GP42/DIOD8
SER_IRQ OE GND INT_SERIRQ_CPU [15] SFD_GPIO PECI/AMDTSI_C/GP44
4 3 54
1

B A R80150 1 2 0R2J-2-GP GNDD

[61] MPCIE_DISABLE_N SC006 SIO_MEM_EVENT_L
R646 PCIRST1# 10 43 SIO_GND
BOM change to NC GPA1/DIOD24 R348 1 2 10KR2J-3-GP SC070
1KR2J-1-GP G2129TL1U-GP IO_SMI_N 8 PCH_C0A/PCIRST1#/GP12 GNDA/TSD-
[16] IO_SMI_N PCH_DOB/GP22
(R_) VCCA should not exceed VCCB SC064 38
[64] SIO_PWRLED_N 3VSBSW#/GP40/SCL0 2 1 1KR2J-1-GP
73.02129.02J DOD8 PCIRST3# R2419
2

IT8617E-BX-GP Reset Buffer Output GP12/DIOD8 PCIRST1# R2420 1 (R_) 2 10KR2J-3-GP

071.08617.000G
[18] INT_SERIRQ_CPU NGFF_BT_DISABLE
C GP32/DIOD8 R2432 1 2 10KR2J-3-GP C
R2416 2 1 33R2J-2-GP PCIE_RST# [61]
R2417 2 1 33R2J-2-GP MPCIE_DISABLE_N R2422 1 2 10KR2J-3-GP
PLTRST_LAN_N [31]
R2418 2 1 33R2J-2-GP
PLTRST_SL_N [76,79] SFD_GPIO
GP44/DIOD24 R2423 2 (R_) 1 10KR2J-3-GP
SER_IRQ R80214 1 (R_) 2 INT_SERIRQ_CPU
0R2J-2-GP
For CX mount
LAN_DISABLE_N R80199 1 (R_) 2 10KR2J-3-GP
SB005 SC072
Change to NC
1B002 1D8V_S5

DOD8 LPC_PME_N R855 1 2 2K2R2J-2-GP

For Braswell
SYS_THERMDA+ CPU_THERMDA+ VCC3

GP31/DIOD8 SIO_GPU_RST R2404 2 1 10KR2F-2-GP

GP33/DIOD8 SIO_GPU_EN R354 2 (R_) 1 10KR2F-2-GP -1002

C
PLTRST*_SIO 2 1 1KR2J-1-GP
GPU VCORE VRD CPU VCORE VRD R336

C
1

1
C219 C2401 B
SC2200P50V2KX-2DLGP B SC2200P50V2KX-2DLGP
LMBT3904LT1G-GP KBRST_N 2 (R_) 1 10KR2J-3-GP
Remove RT2 circuit R330
2

E
LMBT3904LT1G-GP Q7 A20GATE R333 2 (R_) 1 10KR2J-3-GP SB032
E Q6
LAD3_FWH3 R2424 2 (R_) 1 10KR2F-2-GP
G8 1 2 GAP-CLOSE-PWR SYS_THERMDA- G9 1 2 GAP-CLOSE-PWR CPU_THERMDA- LAD2_FWH2 R2425 2 (R_) 1 10KR2F-2-GP
SIO_GND SIO_GND LAD1_FWH1
DIO16 R2426 2 (R_) 1 10KR2F-2-GP
LAD0_FWH0 R2427 2 (R_) 1 10KR2F-2-GP

Layout Note: place 2200PF near SIO PIN44.45

DI LFRAMEJ_FW4 R921 1 (R_) 2 10KR2F-2-GP SB007

PWROK3_2_R R2407 2 1 10KR2J-3-GP

Power-On Strapping
EUP Control for 3D3V_S5 & 5V_S5 Disable / Enable
Symbol Value Description V_3P3_A
DIO16 SER_IRQ R323 2 (R_) 1 10KR2J-3-GP
1B005 VCC3
JP1 DSW_EUP_SEL 1 EUP

2
V_3P3_A SB019 R80215 2 (R_) 1 10KR2J-3-GP
1D8V_S5
Pin-23 0 DSW R296
R801621 2 1KR2J-1-GP V_3P3_A 10K5R2F-GP
JP2 WDT_EN 1 Disable WDT to reset PWROK R725 SB008

2
SIO_JP1 R932 1 (R_) 2 8K2R2F-1-GP 0R2J-2-GP Reserved

1
Pin-56 For BX only 0 Enable WDT to reset PWROK R304 2 (R_) 1
SIO_EUP_EN# [47,49,77,92]
B 10KR2J-3-GP

D
B
JP6 LPC/eSPI 1 Enable LPC Interface change from V_3P3_A to VCC3
SIO_JP4 R934 1 2 1KR2J-1-GP Q6706
VCC3 SB006 SB019

1
Pin-56 For CX only 0 Enable eSPI Interface R305 2N7002H-GP GP23/DIOD8 DPWROK R928 1 (R_) 2 1KR2J-1-GP V_3P3_A
SYS_EUP_CTRL 1 2 EC_EUP_EN G (84.2N702.J31)
JP3 FAN_CTL_SEL 1 EC Index 63h/73h/7B/A3 is 80h R933 CX Un_mount, BX mount DOD8 0R0402-PAD-2-GP SC069 SB009
SIO_JP3 R933 1 2 1KR2J-1-GP change to NC
VCC3

S
1
Pin-58 For BX only 0 EC Index 63h/73h/7B/A3 is 00h (R_) change from SB5V to V_3P3_A
R2431 1 (R_) 2 1KR2J-1-GP
V_3P3_A SYS_EUP_CTRL C180 SIO_EUP_EN#
JP3 Vih/Vil_SEL 1 1.8V Level H: EUP Enable SCD1U16V2ZY-2GP H: EUP Disable

2
R2431 BX Un_mount, CX mount L: EUP Disable(SIO default) L: EUP Enable G7
Pin-58 For CX only 0 3.3V Level 1 2
R80250 1 2 1KR2J-1-GP VCC3 SB031
JP4 K8PWR_EN 1 Disable K8 Power Sequence SIO_JP2
GAP-CLOSE-PWR
R931 1 (R_) 2 1KR2J-1-GP
V_3P3_A
Pin-60 0 Enable K8 Power Sequence SIO_GND
R80250 CX Un_mount, BX mount
R931 BX Un_mount, CX mount
Highlight Red letter indicate default
DOD8 SW_ON_N_SIO R391 1 2 10KR2J-3-GP SB3V For EUP
SB010
For AC OFF SEQUENCE Change pull-up from V_3P3_A to SB3V

DCBATOUT SB3V

R269 1 2PWRGD_PS_L1 0529 Eric modify for BOM DOD8 SIO_PSON_N R80216 1 2 4K7R2J-2-GP V_3P3_A
1

4K7R2F-GP
(63.47234.1DL) VCC3
R273 SB020
6

100KR2J-1-GP
2

Q29 48M CLK

1 2

PWRGD_PS_L 2N7002EDW-2-GP R2406 DOD8 RSMRST_N 1 2 10KR2J-3-GP

(75.27002.F7C) 10KR2F-2-GP
NTC R390 SB3V
2

R274 (R_) (63.10334.1DL) V_3P3_A OSC2 SB011

1

20KR2J-L2-GP C174
1

SCD1U16V2ZY-2GP PWRGD_PS_L2 1 2 SIO_ATXPG R321 1 2 OCS_48M_2 1 Change pull-up from V_3P3_A to SB3V
1

TRI-STATE
1

R280 DI 100KR2J-1-GP 2
2

0R0402-PAD-2-GP C185 CK_48M_SIO 3 GND

SCD1U16V2KX-3DLGP 4 OUTPUT
2

VDD
MINI_POWER_CTRL R80266 1 (R_) 2 10KR2F-2-GP SB3V
V_3P3_A L7 1 2 OCS_48M_1 OSC-48MHZ-16GP
MHC1608S181NBP-GP SC074
Add R80266

Power Good 3V VCC3 SB011

PWRBTN
1

DOD8 SUS_PWR_ACK_CPU R927 1 2 2KR2J-1-GP V_3P3_A

R293
A 1KR2J-1-GP R80218 1 (R_) 2 2KR2J-1-GP VCC3 A
1 2 PB_IN_N_1
[18,24,64] PWRBTN_N For SUSACK# used, pull-up to V_3P3_A
R283 R668
2

PWROK3_1_R 1 2 0R0402-PAD-2-GP For PWRGD1 used, pull-up to VCC3

PWRGD_3V [17,18]
DOD8 0R0402-PAD-2-GP C530
1

SCD1U16V2KX-3DLGP
1
1

C176
SB3V R278 R2405
(R_)
SC100P50V2JN-3DLGP

20KR2J-L2-GP R662
2

R79772 1 (R_) 2 PWRGD_3V_B_1 0R2J-2-GP

1KR2J-1-GP

1KR2J-1-GP (R_)
2

SW_ON_N_SIO 1 2
SIO_PWNBTN_N [18,99]
6

R2411
0.8VCC3-> S0_PWR_GOOD 0R0402-PAD-2-GP
<Variant Name>
Q30 SIO delay: 23h<bit 2>
2N7002KDW-GP Wistron Incorporated
1

(R_75.27002.F7C) 0b 1b 21F, 88, Hsin Tai Wu Rd

Hsichih, Taipei
PWROK3_2_R RSMRST*_R PWRGD_3V_LL
150ms 300ms
R277 1 (R_) 2 Title
1KR2J-1-GP SIO_IT8617E
Size Document Number Rev
Custom Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 24 of 105
5 4 3 2 1
 5 4 3 2 1

SSID = Flash.ROM SPI ROM

1D8V_SPI 1D8V_S5

1A001
1D8V_SPI 1 2
R1593
1D8V_SPI 0R0603-PAD-2-GP-U

D SOP8 for 8Mb D

1
R169 R172

2
10KR2J-3-GP 10KR2J-3-GP 1A008 Change flash part P/N
R186 C116
U8 10KR2J-3-GP SCD1U16V2KX-3DLGP

1
SPI_CS0_N R1733 1 2 33R2J-2-GP SPI_CS0_N_ROM_1 1 8

2
SPI_DATAIN R1731 2 1 10R2J-2-GP SPI_MISO_ROM_1 2 CS# VCC 7 SST_HOLDJ_1 R1729 2 1 10R2J-2-GP SPI_IO3
SPI_IO2 R1730 2 1 10R2J-2-GP SPI_WP# 3 DO/IO1 HOLD#/RESET#/IO3 6 SPI_CLK_1 R1714 2 1 10R2J-2-GP SPI_CLK
4 WP#/IO2 CLK 5 SPI_MOSI_1 R1732 2 1 10R2J-2-GP SPI_DATAOUT
GND DI/IO0

5/13 Allen modify W25Q64FWSSIQ-GP

CRB no R 072.25Q64.0E01
NB 33
PDG CLK & DATA 10, CS 33, but chceklist CS 30.

SC080
[19] SPI_CLK SRCON1
C 1 8 C
[19] SPI_CS0_N
2 7
[19] SPI_DATAOUT 3 6
[19] SPI_DATAIN 4 5
[19] SPI_IO2
[19] SPI_IO3 SKT-SPI8P-GP-U1
(D_62.10089.121)
62.10076.011
62.10089.001
SPI socket mount in SA stage

SSID = RTC Battery Socket

B ST: 22.70017.051 B
FLAT: 22.70017.061
TP14 TP13 Battery (CR2032):
VBAT1 TPAD30 TPAD30 23.22063.001
BAT1
BATTERY CR2032
R199 V_3P3_A (23.22063.001)
1

1 2 VBAT1_R

1
1KR2J-1-GP
A

-1011 D6 D5
RB551V30-GP BAS40C-2-GP
1
+

BT1 V_3P0_BAT_VREG
K

3
BAT-AAA-BAT-029-K01-GP-U <Variant Name>
22.70034.011
2

Wistron Incorporated
A Change symbol 21F, 88, Hsin Tai Wu Rd A

VBAT2
Hsichih, Taipei
Title
Flash ROM/RTC
Size Document Number Rev
A4 Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 25 of 105
5 4 3 2 1
 CPU_FAN_+12V
CPU FAN VCC12

1
R385
VCC3 4K7R2J-2-GP

1
CPU_FAN_TACH_1 R386 1 2 CPU_FAN_TACH_SIO
20KR2J-L2-GP CPU_FAN_TACH_SIO [24] R80248

K
1

1
0R0805-PAD
D3 CPU_FAN_+12V FANC2 ZZ.R0805.ZZZ
R2603 1SS355GP-GP 1 R389

2
2K2R2J-2-GP 8K2R2F-1-GP
2 1/14 Remove CPU FAN control circuit SB022

2
3 SC007
CPU_FAN_CTRL_SIO R2602 1 2 100R2F-L1-GP-U CPU_FAN_CTRL_CONN 4 NP1
[24] CPU_FAN_CTRL_SIO
FOX-CON4-S7-GP Change to close PAD
PWM:21-28KHz (R_21.61259.104) FANC1
1A009 CPU_FAN_+12V

1
C247 1
SC1U25V5KX-1GP For Co-Layout
(R_) 2

2
3 NP1
4

BAOT-CON4-S5-GP
021.60305.0104

SYS FAN CONTROL SYS_FAN_+12V

VCC12

SD008 Change to NC
(Reserved)

1
R2601

1
4K7R2J-2-GP
VCC3 (R_) R80249
0R0805-PAD

2
ZZ.R0805.ZZZ
SYS_FAN_TACH_1 R392 1 (R_) 2 SYS_FAN_TACH_SIO

2
20KR2J-L2-GP SYS_FAN_TACH_SIO [24]

K
1
1/14 Remove SYS FAN control circuit SB021
R394 D4 SYS_FAN_+12V FANS1 SC007

1
2K2R2J-2-GP 1SS355GP-GP 1
(R_) (R_) R395
2 8K2R2F-1-GP Change to close PAD

A
3 (R_)
SYS_FAN_CTRL_SIO R396 1 (R_) 2 100R2F-L1-GP-U SYS_FAN_CTRL_CONN 4 NP1 SYS_FAN_+12V
[24] SYS_FAN_CTRL_SIO

2
FOX-CON4-S7-GP
PWM:21-28KHz (R_21.61259.104) FANS2

1
C248 1
SC1U25V5KX-1GP
(R_) 2
1A009

2
3 NP1
4
For Co-Layout
BAOT-CON4-S5-GP
021.60305.0104
(R_)

SB029
SC008
H1 H2 H3
GEN351X331R209X189-8-F-A-GP GENS315R158-8-F-A-GP GENS315R158-8-F-A-GP
H4 H5 H6
3

2
4 4 4 4
1 6 3 6 3 1 1 1

5 8 7 2 7 2 5 8 5 8 5 8
6

7
ZZ.00PAD.DV1 GEN330R190-8-F-A-GP-U1 GENS315R158-8-F-A-GP GENS315R158-8-F-A-GP
ZZ.AFEN8.190

20150109 H1 Change from ZZ.00PAD.BV1 to ZZ.00PAD.DV1

H4 Change to ZZ.AFEN8.190

UMA BACK PLATE GPU BACK PLATE

LABEL PCB
LBL1 BP1 BP2
LABEL PCB1 PCB2 PCB3
(40.3EQ13.011) MAIN PCB MAIN PCB MAIN PCB
(1R2V6$EA) (1R2V6$FA) (1R2V6$HA)

LAN ID :
F80F4105EB9A
-1(A00)
1R2V6$EA VICTORYGIA PCB4 UMA Back Plate GPU Back Plate
1R2V6$FA GECS MAIN PCB (U_360.03D01.0001) (G_360.03D02.0001)
1R2V6$HA GLOBALBRAN (1R2V6$IA)
1R2V6$IA WUZHU For UMA For GPU
360.03D01.0001 360.03D02.0001
MYLAR SPONGE 360.03D01.0011
M1 M3

UMA COOLER GPU COOLER

MYLAR MB ISOLATION SPONGE CARD READER CSB SFF_1
COOLER1 COOLER2
(340.03A09.0001) (347.03801.0001)

2nd Source 2nd Source

340.03A09.1001 347.03801.1001

EMI GASKET RUBBER

M2 M4 UMA COOLER GPU COOLER
(U_360.03B01.0001) (G_360.03B02.0001)

For UMA For GPU

EMI GASKET SFF CSB RUB MB SUPPORT CSB SFF 360.03B01.0001 360.03B02.0001
(334.03A02.0001) (347.03802.0001) 360.03B01.0011 360.03B02.0011
360.03B01.0021 360.03B02.0021
2nd Source 360.03B01.0031 360.03B02.0031 <Variant Name>
334.03A02.1001
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
FAN CIRCUITS/HOLE
Size Document Number Rev
C Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 26 of 105
 AUD_AVDD C130 SC039
SCD1U25V2KX-1-DL-GP
AUD_AVDD AUD_BEEP_C 1 2 APU_SPKR_R R208 2 1 47KR2F-GP APU_SPKR
APU_SPKR [19,27]

1
move C789 & C12376 C12376 C789 C797 C794 AUD_LINK_RST_N R210 1 2 4K7R2F-GP
HD_LINK SC10U10V5KX-2DLGP SC10U10V5KX-2DLGP
AUD_LINK_RST_N [19,27]
closed to PIn25 & 38 SCD1U10V2KX-5DLGP SCD1U10V2KX-5DLGP
AUD_LINK_SYNC
AUD_LINK_SYNC [19,27] SC040

2
[19,27] AUD_LINK_SDIN AUD_LINK_BCLK
AUD_LINK_BCLK [19,27]
[19,27] AUD_LINK_SDO

1
C793
AGND SC22P50V2JN-4DLGP
[19,27] AUD_LINK_BCLK 1D5V_S0

2
[19,27] AUD_LINK_SYNC
SENSE_B R8 1 2 39K2R2F-L-GP LINE2_JD
[19,27] AUD_LINK_RST_N LINE2_JD [29]

1
C2702 (64.51015.6DL)
C2701 SCD1U10V2KX-5DLGP R452 1 2 5K1R2F-3-GP FRONT_JD
SC10U10V5KX-2DLGP SENSE_A LINEIN_JD FRONT_JD [29]
R2703 1 2 10KR2F-2-GP
LINE1_JD [29]

2
R425 1 2 20KR2F-L-GP MIC1_JD
MIC1_JD [29]

Layout: Near Codec

25
38

12
11
10

33

44
43

34
13
1
9

6
VCC3 U9623
From SOC

DVDD
DVDD_IO
LDO_OUT1
LDO_OUT2

BEEP
RESET#
SYNC
BITCLK
LINE1_VREFO

LFE/PORT_G_R
CENTER/PORT_G_L

SENSE_B
SENSE_A
1

1
C791
[19,27] APU_SPKR
C12383 SCD1U10V2KX-5DLGP
SC10U10V5KX-2DLGP

2
LINE1_L 23 5 AUD_LINK_SDO
[29] LINE1_L LINE1_R LINE1_L/PORT_C_L SDATA_OUT AUD_LINK_SDIN_1 AUD_LINK_SDIN AUD_LINK_SDO [19,27]
24 8 R4271 2 33R2J-2-GP
[29] LINE1_R LINE2_L 14 LINE1_R/PORT_C_R SDATA_IN AUD_LINK_SDIN [19,27]
[29] LINE2_L LINE2_R 15 LINE2_L/PORT_E_L
[29] LINE2_R LINE2_R/PORT_E_R 48
29 S/PDIF_OUT 47 EAPD
V_5_CODEC LINE2_VREFO_L LDO_IN EAPD
31
[29] LINE2_VREFO_L LINE2_VREFO
45
MIC1_L 21 DMIC_DATA 46
[27,29] MIC1_L MIC1_R 22 MIC1_L/PORT_B_L DMIC_CLK
[27,29] MIC1_R MIC2_L MIC1_R/PORT_B_R
16
[29] MIC2_L MIC2_R 17 MIC2_L/PORT_F_L 39
[29] MIC2_R MIC2_R/PORT_F_R SURR_L/PORT_A_L 41
MIC1_VREFO_R 32 SURR_R/PORT_A_R
[29] MIC1_VREFO_R MIC1_VREFO_L MIC1_VREFO_R
28
[29] MIC1_VREFO_L MIC2_VREFO MIC1_VREFO_L FRONT_L
[27,29] MIC2_VREFO 30 35
MIC2_VREFO FRONT_L/PORT_D_L 36 FRONT_R FRONT_L [29]
FRONT_R/PORT_D_R FRONT_R [29]

PIN37_VREFO

REGREF

CD_GND
ALC3600

AVSS1
AVSS2

JDREF

GPIO1
GPIO0
DVSS

VREF

CD_R
CD_L
ALC662-VD-GR-GP
Line1-in pin23/24

26
42

27

40
37

4
2
3

18
20
19
(71.03600.00G)

JDREF
Front-out pin35/36
AGND AUD_REGREF C796 1 2 SC10U10V5KX-2DLGP
Mic
AUDIO_VREF LINE2_VREFO_R
[27,29] MIC2_VREFO Mic-in 1 pin21/22 LINE2_VREFO_R [29]

1
[27,29] MIC1_L
[27,29] MIC1_R

1
C790 R12
20KR2F-L-GP
Mic-in 2 pin16/17 SC10U10V5KX-2DLGP

2
Line2-out pin14/15 AGND AGND

R423 1 2 0R0603-PAD-2-GP-U R2706 1 2 0R0603-PAD-2-GP-U

SB023

A
D28 (R_) AGND AGND
AZ2015-01H-GP L63 1 2
SB5V
MHC1608S800QBP-GP
V_5_CODEC

K
R428 1 (R_) 2 0R3J-0-U-GP R451 1 (R_) 2 0R3J-0-U-GP
L50 1 2 V_5P0_A
MHC1608S800QBP-GP
1

AGND AGND
1

1
R777 C795 C792
10KR2J-3-GP SCD1U10V2KX-5DLGP SC10U10V5KX-2DLGP
2

2 R110 1 2 0R0603-PAD-2-GP-U

AGND
AGND

AGND
Layout: separately place round AGND
SB016

V_3P3_A

1
C860 (R_)
SCD1U10V2KX-5DLGP

2
VCC3 R1009 1 (R_) 2
220KR2F-GP

E
1

R1006 R1007 1 (R_) 2 0R2J-2-GP R1008 1 (R_) 2 10KR2J-3-GP Q85_B B Q85 (R_)
10KR2J-3-GP LMBT3906LT1G-1-GP
(R_) Q84_E Q84_E2

C
2

Q84_B B Q84
LMBT3906LT1G-1-GP
C12404
SC22U6D3V3MX-1-DL-GP
Digital MUTE [29]

Analog
2

(R_) (R_)
E

R1004 1 (R_) 2 1KR2J-1-GP B Q82 B Q83

[19,27] AUD_LINK_RST_N
LMBT3906LT1G-1-GP LMBT3906LT1G-1-GP
Q82_B (R_) (R_)
C

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
EAPD R1005 1 (R_) 2 1KR2J-1-GP
Hsichih, Taipei
Q83_B Title
AUDIO ALC3600
Size Document Number Rev
C Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 27 of 105
Blanking

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 28 of 105

 LINE1 IN(Port C)
AUDIO1
AUDIN_L 32
LINE1_L C849 1 2 SC10U10V5KX-2DLGPAUD_IN_LL_1 R2914 1 2 75R2F-2-GP AUD_IN_LL L16 1 2 MCB1005S121FBP-GP AUDIN_L LINE1_JD 33
[27] LINE1_L [27] LINE1_JD
(68.00084.B21) 34
AUDIN_R 35 BLUE
LINE1_R C850 1 2 SC10U10V5KX-2DLGPAUD_IN_RR_1 R454 1 2 75R2F-2-GP AUD_IN_RR L51 1 2 MCB1005S121FBP-GP AUDIN_R FB_AUDOUT_L 22
[27] LINE1_R
(68.00084.B21) FRONT_JD 23
Line in
[27] FRONT_JD 24
LIME

1
C806 C55 FB_AUDOUT_R 25
Line out
SC100P50V2JN-3DLGP SC100P50V2JN-3DLGP
R453 R2913

2
22KR2J-GP 22KR2J-GP AUD_MIC_2L 2
MIC1_JD 3
Mic
PINK

2
[27] MIC1_JD 4
AGND AUD_MIC_2R 5
1
AGND

FRONT OUT(Port D) G1
G2
G3
TC25 1 2 E100U16VM-22-GP AUDAMPIN_L_C R53 1 2 75R2F-2-GP FB_AUDOUTR_L L14 1 2 MCB1005S121FBP-GP FB_AUDOUT_L G4
[27] FRONT_L
(68.00084.B21)
NP1

TC6 1 2 E100U16VM-22-GP AUDAMPIN_R_C R52 1 2 75R2F-2-GP FB_AUDOUTR_R L15 1 2 MCB1005S121FBP-GP FB_AUDOUT_R

[27] FRONT_R
(68.00084.B21) AGND AUDIO-JK187-GP

1
3 6 (22.10088.J41)

1
Q9642B Q9642A C802 C804
R802411 2 1KR2J-1-GP 5 MMBT3904DW-1-GP 2 MMBT3904DW-1-GP R2915 R44 SC100P50V2JN-3DLGP SC100P50V2JN-3DLGP
[27,29] MUTE (R_) (R_) (R_) 22KR2J-GP 22KR2J-GP

2
MUTE_AUDAMPIN_R_C

2
4 1

AGND AGND AGND

R802421 2 1KR2J-1-GP AGND

(R_)
MUTE_AUDAMPIN_L_C

SB033
AUDIN_R FB_AUDOUT_R
AUDIN_L FB_AUDOUT_L

MIC1(Port B)

1
Q9625 Q14
AZ5125-02S-R7G-GP AZ5125-02S-R7G-GP
MIC1_VREFO_L R975 1 2 2K2R2J-2-GP
[27] MIC1_VREFO_L (R_) (R_)
MIC1_VREFO_R R976 1 2 2K2R2J-2-GP
[27] MIC1_VREFO_R

3
C845 1 2 SC10U10V5KX-2DLGP MIC1_LL_1 R978 1 2 75R2F-2-GP MIC1_LL L1 1 2 MCB1005S121FBP-GP AUD_MIC_2L
[27] MIC1_L
(68.00084.B21)

C848 1 2 SC10U10V5KX-2DLGP MIC1_RR_1 R979 1 2 75R2F-2-GP MIC1_RR L2 1 2 MCB1005S121FBP-GP AUD_MIC_2R

[27] MIC1_R
(68.00084.B21)
[19,27] AUD_LINK_RST_N AUD_MIC_2R
AUD_MIC_2L

1
C842 C841
SC100P50V2JN-3DLGP SC100P50V2JN-3DLGP
R7 R6

1
22KR2J-GP 22KR2J-GP
Q9626

2
AZ5125-02S-R7G-GP
AGND
(R_)
AGND
Front Audio Jack

3
[27] MIC2_VREFO

[27] LINE2_R
[27] LINE2_L
[27] MIC2_L
[27] MIC2_R

LINE2_VREFO_L
[27] LINE2_VREFO_L
LINE2_VREFO_R
[27] LINE2_VREFO_R

MIC2(Port F)
MIC2_VREFO R413 1 2 2K2R2J-2-GP

(R_)
MIC2_R C269 1 2 SC4D7U10V3KX-DL-GP

ESD MIC2_L C270 1 2 SC4D7U10V3KX-DL-GP MIC2_L_C R412 1 2 1KR2F-3-GP MIC2_L_R 1

L6
2 MCB1005S121FBP-GP
(68.00084.B21)

SLEEVE_CON HPOL_CON LINE2 OUT(Port E)

HPOR_CON
LINE2_VREFO_R R419 1 2 2K2R2J-2-GP
PCB trace width of
LINE2_VREFO_L R418 1 2 2K2R2J-2-GP RING2 & SLEEVE at least 40 mil
2

1
2

UAJ1
Q24 Q57 SLEEVE_CON 4
AZ5125-02S-R7G-GP AZ5125-02S-R7G-GP TC24 L54 3
LINE2_R 1 2 E100U16VM-22-GP LINE2_R_C R414 1 2 75R2F-2-GP HPOR_CON_1 1 2 MCB1005S121FBP-GP HPOR_CON 2
(68.00084.B21) HPOL_CON 1
TC23 L53
LINE2_L 1 2 E100U16VM-22-GP LINE2_L_C R415 1 2 75R2F-2-GP HPOL_CON_1 1 2 MCB1005S121FBP-GP 5
(68.00084.B21) LINE2_JD 6
3
3

7
8
(R_) NP1
(R_) NP2

1
C2902 C2901 C274
AUDIO-JK478-GP
1

SC100P50V2JN-3DLGP

SC100P50V2JN-3DLGP

SC100P50V2JN-3DLGP
6 3 (022.10002.0A81)

2
Q9643A Q9643B R2912 R2911
R802431 2 1KR2J-1-GP 2 MMBT3904DW-1-GP 5 MMBT3904DW-1-GP 22KR2F-GP 22KR2F-GP SC009
[27,29] MUTE (R_) (R_) (R_)
MUTE_FP_OUT_L_C
20150105 change UAJ1 from
2

1 4
022.10002.0621 to
AGND AGND
022.10002.0A81
R802441 2 1KR2J-1-GP AGND
(R_) AGND
MUTE_FP_OUT_R_C

SB033
[27] LINE2_JD
AGND

CTIA (Apple) Standard Headset

oTip: Left audio
oRing1: Right audio
oRing2: Ground
oSleeve: Microphone

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
AUDIO JACK
Size Document Number Rev
D Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 29 of 105
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 30 of 105

5 4 3 2 1
 5 4 3 2 1

V_3P3_LAN V_1P05_LAN

V_3P3_LAN POWER Control

LINK_ACTIVITY_N
R377

SPEED_1000_N
SPEED_100_N
1 2 LAN_RSET
P-MOS

LAN_XTALO
LAN_XTALI
2K49R2F-GP V_3P3_LAN
R679 1 (R_) 2 0R5J-5-GP
Layout Note: near pin46.

1
Q39
R675 AO3413L-GP
D SB3V V_3P3_LAN D
10KR2J-3-GP (84.02130.031)

32
31
30
29
28
27
26
25
U20
S D

AVDD33
RSET
AVDD10
CKXTAL2
CKXTAL1
LED0
LED1/GPO
LED2

2
33
GND

1
2

2
C540 C232

SCD1U16V2KX-3DLGP

1
C562

SCD1U16V2KX-3DLGP
PC163 C536

SC2D2U10V3KX-1DLGP-U

SC2D2U10V3KX-1DLGP-U
G
V_3P3_LAN_VDDSREG
Discharge resistor

2
1

SC1U10V2KX-1DLGP

1
2
LAN_MDI0_DP 1 24 LAN_1P05_OUT

LAN_DISABLE_N_4
LAN_MDI0_DN 2 MDIP0 REGOUT 23
3 MDIN0 VDDREG 22
V_1P05_LAN LAN_MDI1_DP AVDD10 DVDD10 WAKE_N V_1P05_LAN
4 21
LAN_MDI1_DN 5 MDIP1 LANWAKE# 20 RTL_ISOLATE_N
LAN_MDI2_DP_R 6 MDIN1 ISOLATE# 19 PLTRST_LAN_N
LAN_MDI2_DN_R MDIP2 PERST# HSI_LAN_DN1_R C201 1 HSI_LAN_DN3
S0 S3 S5 DS
7 18 2 SCD1U16V2KX-3DLGP
8 MDIN2 HSON 17 HSI_LAN_DP1_R C204 1 2 SCD1U16V2KX-3DLGP HSI_LAN_DP3
V_1P05_LAN AVDD10 HSOP H H H H
SB3V

REFCLK_N
REFCLK_P
CLKREQ#

1
AVDD33
vendor advice add SB3V

MDIN3
MDIP3

HSIN
0.1uf Cap and near IC

HSIP
R705
OTHERS SB3V 8K2R2J-3-GP

1
RTL8111G-CGT-1-GP-U2 R702 R706

9
10
11
12
13
14
15
16

2
(071.8111H.0003) SC068 8K2R2J-3-GP LAN_DISABLE_N_3 1 2
[19] CK_GLAN_DP

2
Change to mount (R_) 39K2R2F-L-GP
[19] CK_GLAN_DN 0825 change P/N

LAN_MDI3_DN_R
LAN_MDI3_DP_R

HSO_C_LAN_DP3
LANCLK_REQ_U_N

HSO_C_LAN_DN3

1
CK_GLAN_DN
CK_GLAN_DP
R378
[19] HSI_LAN_DP3
10KR2J-3-GP C559

C
[19] HSI_LAN_DN3
[19] HSO_C_LAN_DP3 Q75 SC1U10V2KX-1GP

2
1
LAN_DISABLE_N_2 B MMBT3904-4-GP (R_)
[19] HSO_C_LAN_DN3
(84.T3904.H11)

C
LAN_MDI2_DP PR5249 2 1 0R2J-2-GP R704

E
LAN_DISABLE_C 1 2 LAN_DISABLE_N_1 B Q74
LAN_MDI2_DN PR5250 2 1 0R2J-2-GP MMBT3904-4-GP
[24] PLTRST_LAN_N 10KR2J-3-GP

1
2
(R_) VCC3

E
R739 C558
C LAN_MDI3_DP PR5247 2 1 0R2J-2-GP 10KR2J-3-GP SC1U10V2KX-1GP C
[24] LAN_DISABLE_N

2
2
(R_) (R_)
[19] LANCLK_REQ_N LAN_MDI3_DN PR5248 2 1 0R2J-2-GP R707
[61,92] WAKE_N

1
R701 10KR2J-3-GP
1 2

C
0R2J-2-GP Q76
[32] LAN_MDI0_DP

1
LAN_DISABLE_V3 B MMBT3904-4-GP
[32] LAN_MDI0_DN For RLT8107E Unmount (84.T3904.H11)
[32] LAN_MDI1_DP For RTL8111H Mount
[32] LAN_MDI1_DN

E
1
V_3P3_LAN (R_)
25MHz XTAL C561
[32] LAN_MDI2_DP LAN_XTALO
[32] LAN_MDI2_DN

2
SB3V VCC3 SC1U10V2KX-1GP
[32] LAN_MDI3_DP
X4
[32] LAN_MDI3_DN
XTAL-25MHZ-181-GP

1
[32] LINK_ACTIVITY_N V_3P3_LAN
4 1 LAN_XTALI R331
[32] SPEED_100_N
R329 1KR2J-1-GP
[32] SPEED_1000_N

1
8K2R2J-3-GP

2
3 2 R372 RTL_ISOLATE_N
6
2KR2F-3-GP

1
RTL_ISOLATE_N_2 2 Q35A

2
3 MMBT3904DW-GP R332
15KR2F-GP
R369 1 (R_) 2 RTL_ISOLATE_N_1 5 Q35B 1 (75.03904.07C)
1MR3F-GP MMBT3904DW-GP

2
1
R374
R368 C207 (R_) 4 (75.03904.07C) LAN_DISABLE_N 2 1 LAN_DISABLE_C
1

1KR2J-1-GP 0R0402-PAD

2
C212 C205 SC1U10V2KX-1GP
SC15P50V2JN-DL-GP SC12P50V2JN-DL-GP
2
2

Need to check leakage issue

VCC3 1D8V_S5 1D8V_S5

B B

2
R516 R502 R505
1A001 For SWR Mode: 10KR2J-3-GP
(R_)
2K2R2J-2-GP
(R_)
10KR2J-3-GP

1 2 1.Mount L16, C329, C330, C332, C334

1
R350
0R0603-PAD-2-GP-U
V_1P05_LAN 2.Un-mount C686 LAN_REQ_B

1
L8
0811 Jeffrey modify for OBS
Layout Note: Close to LAN_IC Pin3, 6, 9, 13, 29, 41, 45.
LAN_1P05_OUT 1 2 LANCLK_REQ_U_N 3 2 LANCLK_REQ_N
(R_) For LDO Mode:
2

C538 C544 C548 C547 Q47

IND-4D7UH-210-GP
1.Reserve C351 0.1u cap on LAN_1P05_OUT
2

C534 PMBS3904-1-GP
2

SCD1U16V2KX-3DLGP

SCD1U16V2KX-3DLGP

SCD1U16V2KX-3DLGP

SCD1U16V2KX-3DLGP

SCD1U16V2KX-3DLGP

C191 C1801 2.Use 0 ohm resistor to connect (R_)

1

C202 C190 SCD1U16V2KX-3GP SC1U25V3KX-1-DLGP

LAN_1P05_OUT and V_1P05_LAN
1

SCD1U16V2KX-3DLGP (R_)
1

SC4D7U6D3V3KX-DLGP 3.Un-mount C686 LANCLK_REQ_U_N R80219 1 (R_) 2 LANCLK_REQ_N

SC044 0R2J-2-GP

vendor advice 4.7UF X5R SB015

Layout Note: Close to Pin22.

V_3P3_LAN
V_3P3_LAN_VDDSREG
R671
V_3P3_LAN 1 2

0R0603-PAD
2

A C554 C537 (R_) (R_) (R_) (R_) A

C221 C220 C195 C194
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
SCD1U16V2KX-3DLGP

SCD1U16V2KX-3DLGP

SCD1U25V3KX-GP SC4D7U6D3V3KX-GP
1

vendor advice change

22UF to 4.7UF X5R <Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Layout Note: Pin 11, 32 Hsichih, Taipei
Title
LAN_RTL8111H
Size Document Number Rev
Custom Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 31 of 105
5 4 3 2 1
 5 4 3 2 1

TR11
USB_DP2 4 3 USB_EXT_DP2
[16] USB_DP2
USB_DN2 1 2 USB_EXT_DN2
[16] USB_DN2
FILTER-4P-137-GP
(068.01012.2011) RJ45R1
USB+RJ45
5
USB_EXT_DN2 USBVCC23 VBUS1 SPEED_100*_CON SPEED_100_N
TR13 6 19 R449 1 2 249R2F-GP
USB_DP3 4 3 USB_EXT_DP3 USB_EXT_DP2 7 D1_N O_LED SPEED_100_N [31,32]
[16] USB_DP3 D1_P ORANGE
8
D USB_DN3 1 2 USB_EXT_DN3 GND D
[16] USB_DN3 1 GREEN 20 SPEED_1000*_CON SPEED_1000_N
USBVCC23 R448 1 2 249R2F-GP
FILTER-4P-137-GP USB_EXT_DN3 2 VBUS2 G_LED SPEED_1000_N [31,32]
(068.01012.2011) USB_EXT_DP3 3 D2_N
4 D2_P
TR28 GND 21
[31,32] LAN_MDI0_DP LAN_MDI0_DN LAN_MDI0_DN_C LAN_MDI0_DP_C Y_LED_P V_3P3_LAN
3 4 10
[31,32] LAN_MDI0_DN [31,32] LAN_MDI0_DN LAN_MDI0_DN_C MDI0_P
[31,32] LAN_MDI1_DP 11 YELLOW
LAN_MDI0_DP 2 1 LAN_MDI0_DP_C LAN_MDI1_DP_C 12 MDI0_N
[31,32] LAN_MDI1_DN [31,32] LAN_MDI0_DP LAN_MDI1_DN_C MDI1_P LAN_LEDACT_R# LINK_ACTIVITY_N
13 22 R450 1 2 360R3-GP
LAN_MDI2_DP_C MDI1_N Y_LED_N LINK_ACTIVITY_N [31,32]
MCM1012B900FBP-GP-U 14
[31,32] LAN_MDI2_DP LAN_MDI2_DN_C MDI2_P
(66.R0036.04L) 15 SB004
[31,32] LAN_MDI2_DN LAN_MDI3_DP_C MDI2_N
[31,32] LAN_MDI3_DP 16
TR2 LAN_MDI3_DN_C 17 MDI3_P
[31,32] LAN_MDI3_DN LAN_MDI1_DN LAN_MDI1_DN_C MDI3_N
[31,32] LAN_MDI1_DN
3 4 Giga 100 10
23 9 LAN_CONN_CVT
LAN_MDI1_DP 2 1 LAN_MDI1_DP_C 24 SHD#G1 VCT 18
[31,32] LINK_ACTIVITY_N [31,32] LAN_MDI1_DP SHD#G2 GND
[31,32] SPEED_100_N 25 Link Orange Green Green
SHD#G3

1
MCM1012B900FBP-GP-U 26 UC1 UC2
[31,32] SPEED_1000_N SHD#G4
(66.R0036.04L) 27 SCD01U16V2KX-3DLGP SCD1U16V2KX-3DLGP
28 SHD#G5 (R_) Act Blink Blink Blink

2
TR29 29 SHD#G6
LAN_MDI2_DN 3 4 LAN_MDI2_DN_C 30 SHD#G7
[31,32] LAN_MDI2_DN SHD#G8 RJ45+XFORMER+2*USB 2.0
LAN_MDI2_DP 2 1 LAN_MDI2_DP_C
[31,32] LAN_MDI2_DP
SKT-RJ45-USB-87-GP
MCM1012B900FBP-GP-U 022.10001.0E11
(66.R0036.04L)
SB004
TR1
LAN_MDI3_DN 3 4 LAN_MDI3_DN_C
[31,32] LAN_MDI3_DN 20150106 change RJ45R1 from
[31,32] LAN_MDI3_DP
LAN_MDI3_DP 2 1 LAN_MDI3_DP_C 022.10001.0D21 to
MCM1012B900FBP-GP-U 022.10001.0E11
(66.R0036.04L)

C C

11/27 U9625 Change to 074.00524.0B9F BY SOURCER V_5P0_A TR34 TR32

USBVCC23 U9625
LAN_MDI0_DN_C 1 6 LAN_MDI0_DP_C 1 6 LAN_LEDACT_R#
1 5 I/O1 I/O4 I/O1 I/O4
2 OUT IN 2 5 V_3P3_LAN 2 5 V_3P3_LAN
GND

1
3 4 USB_EN_3 C3201 GND VDD GND VDD
OC# EN SC1U10V2KX-1DLGP LAN_MDI1_DP_C 3 4 LAN_MDI1_DN_C SPEED_1000*_CON 3 4 SPEED_100*_CON
SC081 I/O2 I/O3 I/O2 I/O3
C3203

2
G524B1T11U-GP
1

2
SCD1U16V2KX-3GP

TC22 C3202 C3204 AZC099-04S-R7G-GP AZC099-04S-R7G-GP

SC10U10V5KX-2DLGP (75.01215.07C) (75.01215.07C)
(
SC10U10V5KX-2DLGP
E220U16VM-L8-GP

R
2

_) TR33 TR30
1A001 LAN_MDI2_DN_C LAN_MDI2_DP_C USB_EXT_DN2 USB_EXT_DP2
1 6 1 6
1 2 I/O1 I/O4 I/O1 I/O4 USBVCC23
[24,34,35,39,48,64,92,99] SLP_S4_N R3212 2 5 V_3P3_LAN 2 5
0R0402-PAD-2-GP GND VDD GND VDD
1D8V_S5 C12336 LAN_MDI3_DP_C 3 4 LAN_MDI3_DN_C USB_EXT_DP3 3 4 USB_EXT_DN3

1
SCD1U16V2KX-3GP I/O2 I/O3 I/O2 I/O3
(R_)
2

AZC099-04S-R7G-GP AZC099-04S-R7G-GP

2
(75.01215.07C) (075.02304.007C)
R3211
B B
10KR2J-3-GP EMI
1

[16] USBOC02

A A

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
RJ45+USB2.0
Size Document Number Rev
C Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 32 of 105
5 4 3 2 1
 5 4 3 2 1

VCC3

1
C730 C731
SCD1U16V2KX-3DLGP SC4D7U6D3V3KX-DLGP

2
D D
VCC3_BOARD

1
C729 C728
SC1U10V2KX-1DLGP SC1U10V2KX-1DLGP

2
U1.6
U1.24
24

23
4

7
SU1
1A001

V18

3V3_IN

CARD_3V3

SDREG

XD_D7
XD_CD#
SR3
SD_WP_BD SR2 2 1 0R0402-PAD-2-GP U1.8 8 15 U1.15 2 1 SD_CLK_BD
9 SP1 SP8 16 0R0402-PAD-2-GP
SP2 SP9

1
SD_DATA1_BD 10 18 SD_CMD_BD C726
SD_DATA0_BD 11 SP3 SP10 19 SC6D8P50V2CN-DL-GP
12 SP4 SP11 20 SD_DATA3_BD (R_)

2
SD_CD_BD 13 SP5 SP12 21 SD_DATA2_BD
14 SP6 SP13 22
SP7 SP14

GPIO0
RREF

GND
DM
DP
RTS5170-GR-GP

2
3

U1.1 1

17

25
SL1
USB_PCH_DN6 2 1 USB_DM6_Card
[37] USB_PCH_DN6

1
USB_PCH_DP6 3 4 USB_DP6_Card
[37] USB_PCH_DP6
SR1
MCM1012B900FBP-GP-U 6K2R2F-GP
(66.R0036.04L)

2
C C

1B006
MEMCD1

F7 1 2 POLYSW-1D5A6V-12-GP V_3_CARD_BD 4 7 SD_DATA0_BD

VCC3_BOARD VDD DAT0 SD_DATA1_BD
8
DAT1 9 SD_DATA2_BD
SD_CLK_BD 5 DAT2 1 SD_DATA3_BD
CLK DAT3
1

1
C725 C722 C723 C724 SD_CMD_BD 2
SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP CMD
SC4D7U6D3V3KX-DLGP SC4D7U6D3V3KX-DLGP
SD_CD_BD 10 3
2

2
SD_WP_BD 11 CD VSS 6
WP VSS
NP1 12
NP2 NP1 GND 13
NP2 GND

SKT-SDCARD-61-GP
062.10002.0341

New P/N:062.10002.0341 replace Old P/N:062.10002.0231

B B

A A

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
RTS5170+CARD READER
Size Document Number Rev
C Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 33 of 105
5 4 3 2 1
 5 4 3 2 1

0711 Jeffrey modify

Change Power switch to popular type USBCN1
Rear USB2 12

USB_Power...Rear2 10
4
D 8 D
USB2P_EXT 3
USBVCC56
11/27 U124 Change to 074.00524.0B9F BY SOURCER USB3P_EXT 7
V_5P0_A USB2N_EXT 2
U124 USB3N_EXT 6
SC081 USBVCC56 1
1 5 5
OUT IN

DOWN
2

UP
GND

1
C272 C238 C234 3 4 USB_EN_2 9
OC# EN
1

2
TC20 C251
SC10U10V5KX-2GP

SCD1U16V2KX-3GP

SC10U10V5KX-2GP
(R_) (R_) (R_) SC1U10V2KX-1DLGP 11

2
E220U16VM-L8-GP

G524B1T11U-GP
2

1
074.00524.0B9F
SKT-USB12-24-GP
22.10321.W41

1A001
1 2
R1599
1D8V_S5 0R0402-PAD-2-GP
C249 EMI

1
SCD1U16V2KX-3GP
2

C
(R_) C
R709

2
10KR2J-3-GP
1A001 (R_)
1

1 2 USB56_FLG
[37] HUBOC01 R3403
0R0402-PAD-2-GP
[24,32,35,39,48,64,92,99] SLP_S4_N

TR5
4 3 USB3P_EXT
[37] F_USB3P
1 2 USB3N_EXT
[37] F_USB3N
FILTER-4P-137-GP
ESD (068.01012.2011)

U6703

USB2P_EXT 4 3 USB2N_EXT
I/O3 I/O2
USBVCC56 5 2
VDD GND
B B
1

USB3P_EXT 6 1 USB3N_EXT
C271 I/O4 I/O1
SCD1U16V2KX-3DLGP
2

AZC099-04S-R7G-GP TR7
(075.02304.007C) 4 3 USB2P_EXT
[37] F_USB2P
1 2 USB2N_EXT
[37] F_USB2N
FILTER-4P-137-GP
(068.01012.2011)

<Variant Name>
A A
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
USB2.0 CONN(REAR)
Size Document Number Rev
B Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 34 of 105
5 4 3 2 1
 5 4 3 2 1

11/06 DEL USB 3.0 REDRIVER

11/27 U125 Change to 074.00524.0B9F BY SOURCER
USBVCC14 V_5P0_A
U125

1 5
2 OUT IN
GND

1
3 4 USB_EN_1 C4259
OC# EN SC1U10V2KX-1DLGP
SC081
C4262 C4263

2
C4261 (R_) G524B1T11U-GP
1

2
SCD1U16V2KX-3GP

SC10U10V5KX-2DLGP
TC11
D D
SC10U10V5KX-2DLGP
E220U16VM-L8-GP
2

1
1A001
2 1
R3502 SLP_S4_N [24,32,34,39,48,64,92,99]
1D8V_S5 0R0402-PAD-2-GP

1
C4260

2
SCD1U16V2KX-3GP
(R_)

2
R3501
10KR2J-3-GP
EMI
1

[16] USBOC01

FRONT USB 3.0

(66.R0036.04L)
ESD ESD
U6704 U9627
L5 SC010
4 3
[16] USB30_RX_CPU_N0 USB_EXT_DN0 1 6 USB_EXT_DP0 1 6
1 2 USB3F1 I/O1 I/O4 I/O1 I/O4
[16] USB30_RX_CPU_P0 2 5 2 5
FRONT_USB3_RX0- GND VDD USBVCC14 GND VDD USBVCC14_CHAR
C FILTER-4P-123-GP 5 1 USBVCC14 C
FRONT_USB3_RX0+ 6 SSRX- VBUS 3 4 USB_EXT_DP1 3 4 USB_EXT_DN1
L4 SSRX+ TR4 I/O2 I/O3 I/O2 I/O3
C104 1 2 SCD1U16V2KX-3DLGP USB30_TX_CPU_N0_EMI 4 3 FRONT_USB3_TX0- 8 3 4
[16] USB30_TX_CPU_N0 FRONT_USB3_TX0+ SSTX- USB_EXT_DN0 F_USB0N [16]
9 2
C103 1 2 SCD1U16V2KX-3DLGP USB30_TX_CPU_P0_EMI 1 2 SSTX+ D- 3 USB_EXT_DP0 2 1 AZC099-04S-R7G-GP AZC099-04S-R7G-GP
[16] USB30_TX_CPU_P0 D+ F_USB0P [16]
(075.02304.007C) (075.02304.007C)

FILTER-4P-123-GP
7
GND_DRAIN 10
FILTER-4P-137-GP
(068.01012.2011)
11/18改改2個ESD PART
(66.R0036.04L) 4 10 11 避避TRACE超超PDG SPEC長長
GND 11

SKT-USB11-153-GP
022.10005.0F41 U7

FRONT_USB3_RX0- 1 10
FRONT_USB3_RX0+ 2 LINE_1 NC#10 9
20150106 change from 3 LINE_2 NC#9 8
022.10005.0761 to FRONT_USB3_TX0- 4 GND GND 7
(66.R0036.04L) FRONT_USB3_TX0+ 5 LINE_3 NC#7 6
L37 022.10005.0F41 LINE_4 NC#6
4 3
[16] USB30_RX_CPU_N1
AZ1045-04F-R7G-GP
1 2 USB3F2
[16] USB30_RX_CPU_P1
FILTER-4P-123-GP FRONT_USB3_RX1- 5 1
FRONT_USB3_RX1+ SSRX- VBUS USBVCC14_CHAR
6
L36 SSRX+ TR6
C1604 2 1 SCD1U16V2KX-3DLGP USB30_TX_CPU_N1_EMI 4 3 FRONT_USB3_TX1- 8 3 4 USBDN1_CHAR U51
[16] USB30_TX_CPU_N1 FRONT_USB3_TX1+ 9 SSTX- 2 USB_EXT_DN1
C1603 2 1 SCD1U16V2KX-3DLGP USB30_TX_CPU_P1_EMI 1 2 SSTX+ D- 3 USB_EXT_DP1 2 1 USBDP1_CHAR FRONT_USB3_RX1- 1 10
[16] USB30_TX_CPU_P1 D+ FRONT_USB3_RX1+ 2 LINE_1 NC#10 9
FILTER-4P-123-GP 7 FILTER-4P-137-GP 3 LINE_2 NC#9 8
(66.R0036.04L) GND_DRAIN 10 (068.01012.2011) FRONT_USB3_TX1- 4 GND GND 7
4 10 11 FRONT_USB3_TX1+ 5 LINE_3 NC#7 6
GND 11 LINE_4 NC#6

SKT-USB11-153-GP AZ1045-04F-R7G-GP
B B
022.10005.0F41

SB3V
TP4118
Charger IC - TI TPS2546 TPAD30 -1010 V_3P3_A

1
CHAR_CTL1 R80063 1 (R_) 2 SLP_S3_N 1D8V_S5 R80205
SLP_S3_N [18,24,40,46,48,53,92,99]

1
USBVCC14 R80061 1 (R_) 2 0R2J-2-GP USBOC01 0R2J-2-GP 10KR2J-3-GP
1

R80200 (R_)
10KR2J-3-GP
CHAR_USBOC#
CHAR_STATUS

2
(R_)

1
USBVCC14_CHAR SB024 CHAR_CTL2 R80064 1 (R_) 2 SLP_S4_N IC_CHAR_CTL3

2
1

0R2J-2-GP R80203 3
C314 2K2R2J-2-GP Q9640B
SCD1U16V2KX-3DLGP USBVCC14 USBVCC14_CHAR CHAR_CTL3_2 5
-1010 MMBT3904DW-GP
2

SB3V (R_) (R_75.03904.07C)

2
PR9884 1 2 0R0805-PAD CHAR_CTL3 R80065 1 (R_) 2 IC_CHAR_CTL3 6
PR9885 1 2 0R0805-PAD 0R2J-2-GP R80201 Q9640A 4
2

R80062 2 (R_) 1 CHAR_CTL3_1 2 MMBT3904DW-GP

[19] CPU_CHAR_CTL3
10KR2J-3-GP 11/24, when U9626 is not stuff, PR9884 (R_75.03904.07C)
(R_) & PR9885 will be stuff 10KR2J-3-GP
13

12
1

U9626 CHAR_ILIM_SEL R80059 1 (R_) 2 1

0R2J-2-GP
IN

STATUS#
FAULT#

OUT
1

R80204 1 (R_) 2 0R2J-2-GP

CHAR_EN 5 3 F_USB1P
[17] CHAR_EN EN DP_OUT F_USB1P [16]
CHAR_ILIM_SEL 4 DM_OUT
2 F_USB1N
F_USB1N [16] To CPU
CHAR_ILIM_LO ILIM_SEL USBDP1_CHAR
CTL1 CTL2 CTL3 ILIM_SEL
15 10 Mode State
CHAR_ILIM_HI 16 ILIM_LO DP_IN 11 USBDN1_CHAR To connector SLP_S3# SLP_S4# GPIO41 GPIO41
ILIM_HI DM_IN
1

R80060 R80049
CTL1
CTL2
CTL3

GND
GND

33KR2F-GP 20KR2F-L-GP 0 0 0 0 Turn off power switch & discharge VBUS S4/S5
(R_) (R_)
A TPS2546RTER-GP A
6
7
8

14
17

(R_) 0 0 1 1 DCP S4/S5

2

0 1 0 0 SDP S3
CHAR_CTL1
CHAR_CTL2
CHAR_CTL3

Current limit for ILIM_HI (CDP/DCP mode)= 2510 mA <Variant Name>

Current limit for ILIM_LO (SDP mode) = 1525 mA
0 1 1 1 DCP with HID auto detect USB data pass through S3 Wistron Incorporated
-1010 21F, 88, Hsin Tai Wu Rd
F_USB1P R_USB1P USBDP1_CHAR
1 1 0 0 SDP S0 Hsichih, Taipei
R80052 1 2 0R0402-PAD-2-GP R80053 1 2 0R0402-PAD-2-GP
F_USB1N R80050 1 2 0R0402-PAD-2-GP R_USB1N R80051 1 2 0R0402-PAD-2-GP USBDN1_CHAR Title
1 1 1 1 CDP S0 USB3.0 CONN(FRONT)
Size Document Number Rev
11/24/ SA WITH USB CHARGER IC, SO UNMOUNT R80050~53, C Rosa_Lily SFF -1
SB WILL UNMOUNT IC, NEED MOUNT 0R BACK. Date: Tuesday, June 23, 2015 Sheet 35 of 105
5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 36 of 105

5 4 3 2 1
 5 4 3 2 1

SB5V HUB_VCC
GL850G
R157 Enable/Disable USB output port: D+/D- pull high 1K to disable USB port
1 2
0R0805-PAD Set USB port to be internal (non-removable): set OC pin is floating
Set USB port to be external (removable): set OC pin is non-floating (pull high 10K to 3.3V or USB OC#)
GL852G
D Enable/Disable USB output port: setting by EEPROM D

Set USB port to be internal (non-removable) or external (removable): setting by EEPROM

U6702 TR3
USB_PN4_L 1 2
HUB_AVDD 5 2 USB_PP4_L USB_CPU_PN4 [16]
HUB_DVDD 9 AVDD DP0 1 USB_PN4_L USB_PP4_L 4 3
AVDD DM0 USB_PCH_DP6 USB_CPU_PP4 [16]
L3 14 4
HUB_DVDD 1 2 HUB_DVDD_R 21 AVDD DP1 3 USB_PCH_DN6 USB_PCH_DP6 [33]
Card Reader FILTER-4P-137-GP
DVDD DM1 USB_PCH_DN6 [33]
MHC1608S601LBP-GP 7 F_USB1P_H [61] (068.01012.2011)
DP2
1

C93 HUB_VCC
27
V5 DM2
6
F_USB1N_H [61]
NGFF
SCD1U16V3KX-3DLGP 13
DP3 F_USB2P [34]
HUB_DVDD 28 12 F_USB2N [34]
2

V33 DM3 16
DP4 F_USB3P [34] Rear USB
15 F_USB3N [34]
HUB_X1 10 DM4
HUB_X2 11 X1 25 USBOC01_H R80206 2 (R_) 1 0R2J-2-GP
X2 OVCUR1#/SMC USBOC02_H SMB0_CLK_MAIN [12,17,55,77]
24 R80207 2 (R_) 1 0R2J-2-GP
HUB_RREF 8 OVCUR2#/SMD 20 HUBOC01 SMB0_DATA_MAIN [12,17,55,77]
HUB_RESET# RREF OVCUR3# HUB_OVC4_N HUBOC01 [34] to USB2.0 CONN
17 19
HUB_PSELF 22 RESET# OVCUR4#
PSELF
1

HUB_PGANG 23
C101 PGANG
C C
SC1U25V3KX-1-DLGP HUB_TEST/SCL 18
2

HUB_SDA 26 TEST/SCL 29
SDA GND
HUB_DVDD
GL850G-OHY31-GP
(071.0850G.0003)
SC011 R3704 1 2 10KR2J-3-GP USBOC01_H
R3703 1 2 10KR2J-3-GP USBOC02_H
R802081 2 10KR2J-3-GP HUB_OVC4_N
20150109 change U6702 to 071.0850G.0003 R802091 2 10KR2J-3-GP HUBOC01
Individual Mode
HUB_PGANG R155 1 2 100KR2J-1-GP
HUB_RREF R174 1 2 619R2F-L1-GP
Co-lay GL850G and GL852G
GL850G: 71.0850G.003 (USB2.0 STT 1 to 4) HUB_DVDD

GL852G: 71.00852.A03 (USB2.0 MTT 1 to 4) R3702 1 2 10KR2J-3-GP HUB_RESET#

R3701 1 (R_) 2 10KR2J-3-GP
EEPROM
HUB_PSELF = 1 if self-powered
B
HUB_DVDD
HUB_PSELF = 0 if bus-powered EEPROM is used for customized VID, PID, String, Configuration B

R569 1 2 10KR2J-3-GP HUB_PSELF

The purpose is to set 4 USB ports to be internal/external
R156 1 (R_) 2 10KR2J-3-GP Default settings: 4 ports are external ports HUB_DVDD

1
HUB_DVDD
Internal Power U9 R180
0R2J-2-GP
(Hub Internal VR output from pin 28 V33 = HUB_DVDD) Xtal accuracy: +/- 20ppm 1
2 E0 VCC
8
7 EEPROM_WP
(R_)

2
C106 3 E1 WC# 6 HUB_TEST/SCL EEPROM_WP
HUB_DVDD HUB_AVDD SC33P50V2JN-3DLGP 4 E2 SCL 5 HUB_SDA 1 (R_) 2
VSS SDA

1
R158 10KR2J-3-GP
1 2 HUB_X1 (R_) R179

1
R577 M24C02-WMN6TP-GP-U C393 0R2J-2-GP
1 2 (R_) SCD1U16V3KX-3GP (R_)
X3

2
0R0603-PAD 4 3

1 2
2

TC10 C94 C397 C402 C105 C401 C400

SC10U10V5KX-2DLGP

XTAL-12MHZ-14GP
SCD1U16V3KX-3DLGP

SCD1U16V3KX-3DLGP
SC1U25V3KX-1-DLGP

SC1U25V3KX-1-DLGP
SCD1U16V3KX-3DLGP

SCD1U16V3KX-3DLGP

82.30006.211
1

A 1A006 A
1 2 HUB_X2 Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
SC33P50V2JN-3DLGP
Hsichih, Taipei
C107
Title
Close to GL850G pin10/11 USB HUB
close to PIN28 Close to pin 5 Close to pin 9 Close to pin 14 Size Document Number Rev
B Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 37 of 105

5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 38 of 105

5 4 3 2 1
 5 4 3 2 1

DDR_VDDQ
06/23 Allen modify

1
R543
10KR2F-L1-GP
(64.10025.6DL)
SB3V
DDR3_DRAM_PWROK

1
D
[48] 1D35V_S3_PWRGD
DDR3_VCCA_PWRGD DDR3_VCCA_PWRGD
R551
10KR2F-L1-GP
DDR_VDDQ
D

1
Q49 (64.10025.6DL)
1A001 3 4 R537

2
[24,32,34,35,48,64,92,99] SLP_S4_N 10KR2F-L1-GP
SYS_PWRGD 1 2 DDR3_VCCA_PWRGD_3P3 2 5 (64.10025.6DL)
[5] DDR3_DRAM_PWROK R1601

2
0R0402-PAD-2-GP 1 6 DDR3_VCCA_PWRGD_G DDR3_DRAM_PWROK
[5] DDR3_VCCA_PWRGD

1
(75.27002.F7C)
[18,79] SYS_PWRGD 2N7002KDW-GP R532
0R0402-PAD-2-GP SB3V
84.2N702.A3F DDR_VDDQ
2nd = 84.DM601.03F

1
3rd = 84.2N702.F3F Q48
DDR3_DRAM_PWROK_D 3 4 R549
1A001

1
10KR2F-L1-GP
R550 1D35V_S3_PWRGD 1 2 1D35V_S3_PWRGD_R 2 5 (64.10025.6DL)
10KR2J-3-GP R1891

2
(R_) 0R0402-PAD-2-GP 1 6 SLP_S5_N_D

2
2N7002KDW-GP

S
(75.27002.F7C)

2
DDR3_VCCA_PWRGD SLP_S4_N G 84.2N702.A3F
C4230 2nd = 84.DM601.03F
Q1240 SCD1U16V2KX-3GP 3rd = 84.2N702.F3F

1
2
AO3413L-GP (R_)
C380 (84.03401.D31)

D
SCD1U16V2KX-3GP

1
(R_) SC012

C C

B B

A A

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
PWROK
Size Document Number Rev
Custom Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 39 of 105
5 4 3 2 1
 5 4 3 2 1

D D

Run Power(5V_S0,3.3V_S0,1.5V_S0,1.8V_S0)
C C

V_5P0_A V_5P0_A

1 VCC VCC VCC3

C1665
SC1U10V2KX-1DLGP U52
2

15
1 GND 14
1A001 VIN1#1 VOUT1#14

1
2 13 C1668 C1670
VIN1#2 VOUT1#13

SCD1U16V2KX-3DLGP

SCD1U16V2KX-3DLGP
1 2 VCC_EN 3 12 3V5V_CT1 VCC3 C1669 C1671
[18,24,35,46,48,53,92,99] SLP_S3_N ON1 CT1 ( (
R1776 0R0402-PAD-2-GP 4 11 R R

2
1 2 VCC3_EN 5 VBIAS GND 10 3V5V_CT2 _) _)
ON2 CT2 SC10U10V5KX-2GP SC10U10V5KX-2GP
R1747 0R0402-PAD-2-GP 6 9
7 VIN2#6 VOUT2#9 8
VIN2#7 VOUT2#8

1
C1672 C1673
(R_) (R_) V_3P3_A TPS22966DPUR-GP
1

C1667 C1696 (074.08910.0093)

2
SC1KP50V2KX-1DLGP

SC1KP50V2KX-1DLGP
SC1U6D3V2KX-DLGP

SC1U6D3V2KX-DLGP
2

B B
1

C1666
SC1U10V2KX-1DLGP
2

A A

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
RUN PWR
Size Document Number Rev
C Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 40 of 105
5 4 3 2 1
 5 4 3 2 1

D D

05/27 Allen modify

C C
V_5P0_A V_5P0_A
V_3P3_A

1
SB5V SB3V SB5V

PR5258

1
10KR2J-3-GP C1698 U54
SC1U10V2KX-1DLGP

2
15

2
1 GND 14
VIN1#1 VOUT1#14

1
2 13 C1701 C1703
VIN1#2 VOUT1#13 U54_CT1 SB3V

SCD1U16V2KX-3DLGP

SCD1U16V2KX-3DLGP
1A001 3 12 C1702 C1704
ON1 CT1 ( (

SC10U10V5KX-2GP

SC10U10V5KX-2GP
4 11 R R

2
1 2 SB3V_EN 5 VBIAS GND 10 U54_CT2 _) _)
[52,92] SB3V_5V_PG ON2 CT2
R1778 6 9
0R0402-PAD-2-GP 7 VIN2#6 VOUT2#9 8
VIN2#7 VOUT2#8
EC_EUP_EN#

1
C1705 C1706
H: EUP disable (R_) V_3P3_A TPS22966DPUR-GP
L: EUP enable

SC1KP50V2KX-1DLGP

SC1KP50V2KX-1DLGP
C1700 (074.08910.0093)

2
SC1U6D3V2KX-DLGP

1
C1699
SC1U10V2KX-1DLGP

2
B B

VCC5SB LED
SB5V
1

0811 Jeffrey delete 5V always LED R306

1K5R3-GP
2
A LED_5VSB

LED2
LED-W-45-GP
(83.01921.C70)
Yellow LED
A A
K

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
DSW_POWER_CTL
Size Document Number Rev
C Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 41 of 105
5 4 3 2 1
 5 4 3 2 1

0513 Eric modify from POWER team

For layout top and bottom the same

D
U33 R981 R982 R983 D

Adaptor in to generate DCBATOUT R1718

1A002
Change Part Reference from DC_IN to DCIN1
-1009 AD_JK
Change P/N to 022.10015.0501 DC_19V DC_19V DCBATOUT

DCIN1 PU4201
5 1 S D 8 PR4201 1 2 GAP-CLOSE-PWR-3-GP
6 2 S D 7

K
9 JACK_PSID 3 S D 6 PR4202 1 2 GAP-CLOSE-PWR-3-GP

1
7 PC4202 (R_) PC4203 (R_) PD4202 AD+_2 4 G D 5
8 SCD1U25V3KX-DLGP SCD1U25V3KX-DLGP P6SBMJ24AGP-GP PR4204 PC4201 PR4203 1 2 GAP-CLOSE-PWR-3-GP

SC1U50V5ZY-1-DL-GP
AO4407AL-GP

2
1

1
200KR2F-L-GP
1 C4202 PC4204 84.04407.G37 PR4205 1 2 GAP-CLOSE-PWR-3-GP

A
2 SC1KP50V2KX-1DLGP SCD1U25V3KX-DLGP
3 Id= -10A PR4206 1 2 GAP-CLOSE-PWR-3-GP
2

2
4
Qg= -22nC PR4208 1 2 GAP-CLOSE-PWR-3-GP

2
NP1 Rdson=14~22mohm
NP2 PR9826 1 2 GAP-CLOSE-PWR-3-GP

DC-JACK324-GP PR9827 1 2 GAP-CLOSE-PWR-3-GP

022.10015.0501

1
PR9828 1 2 GAP-CLOSE-PWR-3-GP
Main source: 022.10015.0501(FOXCONN) PR4207
2nd source: 022.10015.0511(SINGATRON) 100KR2J-1-GP PR9829 1 2 GAP-CLOSE-PWR-3-GP
DEl AD off
PR9830 1 2 GAP-CLOSE-PWR-3-GP

2
C C
PR9831 1 2 GAP-CLOSE-PWR-3-GP

11/16
CHANGE TO ZZ.CLOSE.001 PAD

VCC3 VCC3

1
PSID_G
D14 R430
BAV99GP-GP 1K5R2J-3-GP
SD003
G

2
BIOS GPIO

3
L22 R426
1 2 PSID_D D S ADAPTOR_PSID_R 1 2 ADAPTOR_PSID_R_R 1 2
BLM15BD102SN1D-GP R1602 ADAPTOR_PSID_SIO [24]
Q42 33R2J-2-GP 0R0402-PAD-2-GP
DMN5L06K-7-GP 1A001

VCC
B B
1

R421
1

10KR2J-3-GP
R424
100KR2J-1-GP
2
C
2

Q40
PSID_D_1 B MMBT3904-4-GP
(84.T3904.H11)
1

R422
15KR2F-GP
2

A A

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
DCIN JACK
Size Document Number Rev
C Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 42 of 105
5 4 3 2 1
 5 4 3 2 1

Caculated Valtage=11.99V 2013.5.11

PWR_DCBATOUT_12V DCBATOUT
VCC12 VO=11.87V~12.11V
OVP=13.19V PR4302 1 2 GAP-CLOSE-PWR-3-GP
OCP>3A PR4318 1 2 GAP-CLOSE-PWR-3-GP
Iomax=2A
Fsw=300KHz PR9832 1 2 GAP-CLOSE-PWR-3-GP

PR9833 1 2 GAP-CLOSE-PWR-3-GP
D D
V_5P0_A

VCC3
Vin ripple current Imax=1A
PWR_DCBATOUT_12V
1

PR4304

1
10KR2J-3-GP (E_83.R5003.H8H)
PR4305 PD4301 PC4303 PC4301

1
2D2R5J-1-GP CH551H-30PT-GP PWR_12V VCC12
2

(83.R5003.H8H) PC4302
PWR_12V_PG SCD1U50V3KX-DL-GP S S
C C

PWR_12V_BOOT_A 2

2
PC4306 Change size to 0402 1 1
0 0
1

PC4307 U U PR4307 1 2 GAP-CLOSE-PWR-3-GP

2 2

1
SCD1U16V2KX-3DLGP PC4306 5 5
V V
SC1U10V2KX-1DLGP 6 6 PR4310 1 2 GAP-CLOSE-PWR-3-GP
K K

PWR_12V_VCC
2

5
6
7
8
X- X-

D
D
D
D
PU4301 4 4 PR9834 1 2 GAP-CLOSE-PWR-3-GP
D D
L- L-
SC013 SIS412DN-T1-GE3-GP

PU4302
PR4306
2D2R5J-1-GP 5.6uH +/-20%
G
P
G
P Iomax=2A PR9835 1 2 GAP-CLOSE-PWR-3-GP

1 2 PWR_12V_HG_A DCR=45~50mohm,
PWR_12V_FB

G
S
S
S
8 6 PR4301 PC4308 Idc=5A, Isat=9A
PWR_12V_VOS 9 FB VCC 2D2R3J-2-GP SCD1U50V3KX-DL-GP PWR_12V

4
3
2
1
PWR_12V_PG 10 VOS
PGOOD PWR_12V_BOOT 1 PL4301
1 2 1 2
BOOT
2

PC4309 2 PWR_12V_PH 1 2
C LX C
1

PR4308 PR4309 SCD01U16V2KX-3GP 3 PWR_12V_HG

158R2F-GP (R_) 5 UG 4 PWR_12V_LG 2013.5.11
2K21R3F-L-GP GND LG IND-5D6UH-45-GP

1
11 7 PWR_12V_COMP PT4301 Change to 09.1071D.F5L
2

GND COMP/EN#

5
6
7
8

1
PU4303 PR4311 PC4310
1

D
D
D
D
SIS780DN-T1-GE3-GP 2D2R5J-1-GP SC10U25V6KX-4DL-GP PT4301

1
NCP1589AMNTWG-1-GP (R_) E100U16VM-108-GP-U

2
074.01589.0A73 PR4312 100uF/16V,

2
pc4311 8K06R2F-GP
SCD22U16V3KX-2DLGP PR4313 4 PWR_12V_SNB ESR=24.0mohm,

G
Ripple Current= 2490 mA

1
S
S
S
3K3R2F-2-GP SC047

1
1 2 PWR_12V_COMP_A 2 1 pc4312 PR4314

3
2
1
Change to 8.06K SIS780 SC1500P50V3KX-DLGP 10R2F-L-GP
84.00780.037

2
PC4313 1 2 SC1KP50V2KX-1DLGP

2
Vds=30V,Id=30A
Rds(on)=14.5~17.5 mohm

PC4314
SCD01U16V2KX-3DLGP PR4315
75R2F-2-GP
1 2 PWR_12V_FB_A 2 1

PR4316 1 2 2K21R3F-L-GP PWR_12V_FB_B

B B
R1
1

PR4317
R2 158R2F-GP 1A001 Q4301
2N7002A-7-GP
1 2 G (84.2N702.J31)
2

[24] SIO_PSON_N
R80251
0R0402-PAD-2-GP
From SIO
S

Vout=0.8*(R1+R2)/R2

A <Variant Name> A

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
PWR_12V_(NCP1589A)
Size Document Number Rev
Custom Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 43 of 105
5 4 3 2 1
 5 4 3 2 1

D D

Caculated Valtage=5.0V 11/16

V_5P0_A Voltage=4.95V~5.075V
OVP=5.346V
Change to CLOSE pad

Iomax=6A
OCP>9A DCBATOUT +DCBATOUT_RT8243_1
Fsw=325KHz
PR4492 1 2 GAP-CLOSE-PWR-3-GP

PR4493 1 2 GAP-CLOSE-PWR-3-GP

PR4990 1 2 GAP-CLOSE-PWR-3-GP
Caculated Valtage=3.33V PR4991 1 2 GAP-CLOSE-PWR-3-GP
V_3P3_A Vo=3.2976~3.38V
PR9838 1 2 GAP-CLOSE-PWR-3-GP
OVP=3.56V
Iomax=4.2A PR9840 1 2 GAP-CLOSE-PWR-3-GP
OCP>6.3A PR9839 1 2 GAP-CLOSE-PWR-3-GP
Fsw=375KHz PR9841 1 2 GAP-CLOSE-PWR-3-GP
+DCBATOUT_RT8243_1 +DCBATOUT_RT8243_1
+DCBATOUT_RT8243_1

+5VL PG4901 47uF/25V,

GAP-CLOSE-PWR-3-GP ESR=30mohm
1

1
PC4901 PC4902 2 1 PC4916 Ripple Current =2800mA
SC10U25V6KX-4DL-GP SC10U25V6KX-4DL-GP SCD1U25V3KX-DLGP

1
PC4903 PC4904 PT4901
2

2
1
PR4901 SC10U25V6KX-4DL-GP SC10U25V6KX-4DL-GP SE47U25VM-13-GP
PC4917 100KR2J-1-GP (R_)

2
5
6
7
8
C
0811 Jeffrey Iomax 3A to 4.2A SC4D7U6D3V3KX-DLGP PU4901 C

2
D 8
D 7
D 6
D 5

D
D
D
D
PQ4901 PQ4904

2
SIS412DN-T1-GE3-GP 12 PWR_RT8243_ENLDO SIS412DN-T1-GE3-GP
PWR_RT8243_LDO5 14 ENLDO
Iomax=4.2A LDO5
Iomax=6A
11

G
S
S
S
3.3uH, PC4913 PR4902
VIN
PR4903 PC4914 2.2uH, DCR= 18~20
DCR=10.8~11.8mohm, SCD1U25V3KX-DLGP 2D2R5J-1-GP 2D2R5J-1-GP SCD1U25V3KX-DLGP
S
S
S
G
mohm, Idc= 8A,

4
3
2
1
V_3P3_A
Idc=10A PR4904 2 1 PWR_3V_BOOT2_R 1 2 PWR_3V_BOOT2 7 19 PWR_5V_BOOT1 1 2 PWR_5V_BOOT1_R 2 1 PR4905 220uF/6.3V,
1
2
3
4

+3D3V_PWR 0R5J-5-GP BOOT2 BOOT1 0R5J-5-GP Isat= 14A +5V_PWR V_5P0_A

ESR=15mohm
PWR_3V_UGATE2R 2 1 PWR_3V_UGATE2 8 18 PWR_5V_UGATE1 2 1 PWR_5V_UGATE1R
UGATE2 UGATE1 Ripple Current =3110mA
PL4903 PL4904
PR4906 1 2 GAP-CLOSE-PWR-3-GP 1 2 PWR_3V_PHASE2 9 17 PWR_5V_PHASE1 1 2 PR4907 1 2 GAP-CLOSE-PWR-3-GP
IND-3D3UH-116-GP PHASE2 PHASE1 IND-2D2UH-122-GP
1

PR4908 1 2 GAP-CLOSE-PWR-3-GP PQ4903 PR4909 1 2 GAP-CLOSE-PWR-3-GP

1

1
PT4902 PC4905 PR4911 SIS412DN-T1-GE3-GP 16 PWR_5V_LGATE1
LGATE1

5
6
7
8
PR4910 1 2 GAP-CLOSE-PWR-3-GP SE220U6D3VM-8GP SC1U10V2KX-1DLGP 2D2R5J-1-GP PWR_3V_LGATE2 10 PQ4902 PR4913 1 2 GAP-CLOSE-PWR-3-GP
LGATE2
D 8
D 7
D 6
D 5

D
D
D
D
PR4921 SIS780DN-T1-GE3-GP PR4912
2

1
PR9846 1 2 GAP-CLOSE-PWR-3-GP 1
PR4914 2 6K65R2F-GP PWR_3V_FB2 5 1 PWR_5V_FB1 1 2 2D2R5J-1-GP PG4903 PT4903 PC4906 PR4915 1 2 GAP-CLOSE-PWR-3-GP
1PWR_3D3V_SN 2

FB2 FB1

GAP-CLOSE-PWR-3-GP
PG4902 PC4918 SC4D7U6D3V3KX-DLGP 15K4R2F-GP SE220U6D3VM-8GP SC1U10V2KX-1DLGP

2
PR9847 1 2 GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP +3VL PG4904 1 2 20 PWR_5V_SN PR4916 1 2 GAP-CLOSE-PWR-3-GP

2
BYP1 4
PC4910 (R_) GAP-CLOSE-PWR-3-GP SC014 -1007

G
1

2
1
PWR_RT8243_LDO3 15

S
S
S
PR9848 1 2 GAP-CLOSE-PWR-3-GP 220uF/6.3V, SC22P50V2JN-4DLGP 2 1 PC4908 PR4926 1 2 GAP-CLOSE-PWR-3-GP
LDO3

1
ESR=15mohm 2 1 PC4915 5/19 modify to 15.4K SC1KP50V3KX-DLGP
1 S
2 S
3 S
4 G

3
2
1
13 PWR_RT8243_EMN +3VL SC1U16V2KX-DL-GP PR9850 1 2 GAP-CLOSE-PWR-3-GP
Iripple=2.9 A

2
PR4923 ENM

2
1
100KR2J-1-GP PR9849 1 2 GAP-CLOSE-PWR-3-GP

1
11/16 PC4907 1 2 PWR_RT8243_PGOOD 6 PC4909 (R_)
+3D3V_PWR PGOOD
CHANGE TO ZZ.CLOSE.001 PAD SC1KP50V3KX-DLGP PR4917 SC22P50V2JN-4DLGP PR9852 1 2 GAP-CLOSE-PWR-3-GP
2

10KR2F-2-GP PWR_5V_ENTRIP1 2 PR4918 2 1 PWR_5V_FB1_A

ENTRIP1 56KR2F-GP PR9851 1 2 GAP-CLOSE-PWR-3-GP
2

3 PWR_RT8243_TON

2
TON

1
PWR_3V_FB PWR_3V_ENTRIP2 4 PR9854 1 2 GAP-CLOSE-PWR-3-GP
ENTRIP2

GND

1
PR4922 PR9853 1 2 GAP-CLOSE-PWR-3-GP

1
(R_) PR4920 10KR2F-2-GP
1

1
+3D3V_PWR (R_) PR4925 PR4924 PC4912 RT8243AZQW-GP PR4919 22KR2F-GP

21

2
PC4911 100KR2F-L1-GP 137KR2F-1-GP SC18P50V2JN-1DLGP (74.08243.073) 68KR2F-GP (R_)
SC18P50V2JN-1DLGP
2

2
SC048 SC049 11/16
2

2
CHANGE TO ZZ.CLOSE.001 PAD
1

C1606
SCD1U16V2KX-3DLGP
1/25 modify to 100K 1/25 modify to 137K 11/15 modify to 22K(R)
2

B B

Table 2. Power Up Sequencing(RT8243A)

ENLDO(V) SECFB ENTRIP1 ENTRIP2 LDO5(V) LDO3(V) SMPS1 SMPS2

LOW LOW X X Off Off Off Off

>1.6V
=>High LOW X X On On Off Off
>1.6V >2.3V
=>High =>High Off Off On On Off Off
>1.6V >2.3V
=>High =>High Off On On On Off On
>1.6V >2.3V
=>High =>High On=>PD On=>PD On On On On
>1.6V >2.3V
=>High =>High On Off On On On On

A A

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
3D3V/5V_(RT8243A)
Size Document Number Rev
D Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 44 of 105
5 4 3 2 1
 5 4 3 2 1

20140902
Richard
Change input bead to short pad
PWR_VCORE_VCC0 Iomax=10A DCBATOUT PWR_VCC0_VIN
OCP>19.8A
VR12.1 POWER CKT - 1 phase 19Vin
05/22
Fsw=500KHz Allen modify
PR4490 1 2 GAP-CLOSE-PWR-3-GP

PR4491 1 2 GAP-CLOSE-PWR-3-GP

PR9837 1 2 GAP-CLOSE-PWR-3-GP

PR9836 1 2 GAP-CLOSE-PWR-3-GP
SB3V SB3V
05/27 Allen modify
SB5V DCBATOUT SB5V

PL4401, 11/16 CHANGE TO CLOSE PAD

1
SB004 68.R3310.10D
PR4430 PR4428
PR4401 PR4402 06/23 Allen modify 2D2R3J-2-GP PR4429 1R5J-2-GP 0.33uH,Rdc=3.5~3.9 mohm
1KR2J-1-GP 10KR2J-3-GP 1KR2J-1-GP Idc=20A, Isat=30A

2
0804 modify size 0804 modify size
PWR_VCC0_VIN

PWR_VCC0_VCC

PWR_VCC0_VRMP
1

1
PC4428 PC4427

PWR_VCC0_PVCC
1
(R_) (R_) (R_) SC1U10V2KX-1DLGP SCD01U25V2KX-3DLGP

1
PC4409 PC4410 PR4403 PC4426

2
SCD1U10V2KX-4DLGP SCD1U10V2KX-4DLGP 10KR2J-3-GP SC2D2U10V3KX-1DLGP-U
(R_)

1
PC4423 PC4424 PT4491

2
SC10U25V6KX-4DL-GP SE47U25VM-14-GP

28
SCD1U25V3KX-DLGP

5
6
7
8
PU4401

2
D
D
D
D
D 3 PQ4401 D

VCC

VRMP
1 SDIO 5 VCC_SVID_DATA [54]
AON6520-GP
[46] VGG_PG ENABLE SCLK
ALERT#
4 VCC_SVID_CLK
VCC_SVID_ALERT
[54]
[54] 10/16 change to 84.06520.037 Iomax=10A
6 PR4424 PC4421 PR44232 1 2D2R6J-3-GP PWR_VCC0_HGR 4

G
[48] VCC0_PG VR_READY 15

S
S
S
2D2R6J-3-GP SCD22U25V3KX-2-DL-GP PR4422
PWR_VCC0_DIFFOUT 25 PVCC 8 PWR_VCC0_BT 2 1PWR_VCC0_BTR 2 1 10KR2J-3-GP

3
2
1
DIFFOUT BST 9 PWR_VCC0_HG 2 1 PL4401
PR44042 1 47R2F-GPPWR_VCC0_COMP1 2
PC4411 1 SC330P50V2KX-3-DL-GP 2
PC4412 1 SC47P50V2JN-5DLGP PWR_VCC0_COMP 23 HG 10 PWR_VCC0_SW 1 2
COMP SW PWR_VCC0_LG PWR_VCORE_VCC0
12 IND-D33UH-12-GP
LG

1
PC4413 4X4 28PIN 11
PR44052 1 1KR2F-3-GP PR44072 1 3K3R2F-2-GP PWR_VCC0_COMP2 1 2 SC4700P50V2KX-1DLGP PGND
QFN
PWR_VCC0_FB 24 PR4421
FB

5
6
7
8
0804 modify PC4419 470pf to 560pf 2D2R6J-3-GP

D
D
D
D

1
PWR_VCORE_VCC0 (R_) SC077 PC2240 Unmount PQ4402

2
PR4406 0126 modify PC4413 to 4700pf AON6510-GP PG4401 PG4402

1
560KR2F-GP 18 PWR_VCC0_CSSUM
GAP-CLOSE GAP-CLOSE
R1822 CSSUM PWR_VCC0_CSMP1 PWR_VCC0_SN

2
100R2F-L1-GP-U PR4410 19 PWR_VCC0_CSCOMP PR4419 2 1 75KR2F-GP 2
PR4420 1 150KR2F-L-GP 4

2
CSCOMP PWR_VCC0_ILIM

S
S
S
0R2J-2-GP
2 1 PWR_VCC0_VSP 27 1 2 PC44191 2 SC560P50V2KX-2DLGP

PWR_VCC0_CSP

PWR_VCC0_CSN
2

3
2
1
[18] VCC0_SENSEN_P VSP

1
PC4414 (R_) PR4411 PR4418 PN4402 PC4429
SC1KP16V2KX-DL-GP 1K5R2F-2-GP 21 1 2 NTC-100K-20-GP PC44202 1 SC2200P50V2KX-2DLGP SC1KP50V3KX-DLGP
2 1 PWR_VCC0_VSN 26 ILIM 10KR2F-2-GP
[18] VCC0_SENSEN_N 10/16 change to 084.06510.0037

2
VSN

1
1D8V_S5 1P05V_S5 (R_)

1
17 PWR_VCC0_CSREF
R1823 PC4415
CSREF 11/12 modify To 140k
100R2F-L1-GP-U SC3300P50V2KX-1DLGP

1
(R_) SC050 1/25 6.49K(64.64915.6DL) for OCP 13A

1
R79786 R1734 1A022 4/20 10K(64.10025.6DL) for OCP 18A PC4418 1 PR4417 2 140KR2F-1-GP

2
20KR2J-L2-GP 56D2R2F SC1KP16V2KX-DL-GP
14 PWR_VCC0_VBOOT/ADDR

2
VCC0_HOT 2 VBOOT/ADDR 16 PWR_VCC0_IMAX 2 PR4416 1 10R2J-2-GP

2
VR_HOT# IMAX 22 PWR_VCC0_ROSC
PWR_VCC0_TSEN 13 ROSC 20 PWR_VCC0_IOUT

GND
TSENSE IOUT

1
1
PR4413 NCP81201MNTXG-GP-U PC4417 PR4415

29
0R2J-2-GP SC470P50V2KX-3DLGP 40K2R2F-GP
PWR_VCC0_TSEN1

1 2

2
1
PUT COLSE SC075 1/25 modify to 34K

2
2
1A022 4/20 modify to 52.3K
TO VCORE

1
5/19 modify to 40.2K
MOSFET
PC4416 -1003 (R_) (R_)
1 2 PN4401 PR4414 SCD1U16V2KX-3DLGP TC13 TC14 TC15
[18,46] APU_PROCHOT#

1
R1604 0R2J-2-GP HOT SPOT NTC-100K-20-GP 62KR2F-GP E560U6D3VM-3-GP E560U6D3VM-3-GP E560U6D3VM-3-GP
BOTTOM PAD

2
2
CONNECT TO

2
GND Through
6 VIAs

05/22 8*22U and 1*330U modify to 3*820U

08/11 Jeffrey change 820U to 560U ,and 1pcs reserve

PWR_VCC0_VBOOT/ADDR PWR_VCC0_IMAX PWR_VCC0_ROSC

VCORE
VBOOT SET

1
PR4431 VCORE Work F= PR4433
AT 1V, 0R2J-2-GP PR4432 18K7R2F-GP
SVID ADDR IMAX SET 31K6R2F-GP
500Khz
00h AT 10A
SC076

2
-1003

C C
1/27 modify to 23.2K
5/19 modify to 31.6K

7/29
Remove VCC1

B B

A A

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
VCC0+VCC1_(NCP81201)
Size Document Number Rev
Custom Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 45 of 105

5 4 3 2 1
 5 4 3 2 1
11/16
Change to ZZ.CLOSE.001 pad

PWR_VCORE_VGG Iomax=12A VR12.1 POWER CKT - 1 phase 19Vin DCBATOUT PWR_VGG_VIN

OCP>21.8A SB3V
PR4590 1 2 GAP-CLOSE-PWR-3-GP
Fsw=500KHz SB5V DCBATOUT SB5V
05/22 PR4591 1 2 GAP-CLOSE-PWR-3-GP

1
SB3V PR4530 PR4528 Allen modify PR9842 1 2 GAP-CLOSE-PWR-3-GP
05/27 Allen modify PR4502 2D2R3J-2-GP PR4529 1R5J-2-GP

1
10KR2J-3-GP 0804 modify size 1KR2J-1-GP PR9843 1 2 GAP-CLOSE-PWR-3-GP
(R_)

2
PR4501
1KR2J-1-GP PWR_VGG_VIN

PWR_VGG_VCC

PWR_VGG_VRMP
0804 modify size

1
PC4528 PC4527

PWR_VGG_PVCC
2

1
D D
(R_) (R_) SC1U10V2KX-1DLGP SCD01U25V2KX-3DLGP

1
(R_) PC4510 PR4503 PC4526

2
PC4509 SCD1U10V2KX-4DLGP 10KR2J-3-GP SC2D2U10V3KX-1DLGP-U
1

(79.47612.3GL)

1
SCD1U10V2KX-4DLGP PC4523 PC4524 PT4591

2
SC10U25V6KX-4DL-GP SE47U25VM-14-GP

28
SCD1U25V3KX-DLGP
2

5
6
7
8
PU4501

2
D
D
D
D
3 PU4502
Iomax=12A

VCC

VRMP
SDIO VGG_SVID_DATA [54]
1 5 AON6520-GP
[18,24,35,40,48,53,92,99] SLP_S3_N ENABLE SCLK VGG_SVID_CLK [54]
4
ALERT# VGG_SVID_ALERT [54]
6 PR4524 PC4521 PR45232 1 2D2R6J-3-GP PWR_VGG_HGR 4
11/27 68.R2210.10Q 缺缺
10/16 change to 84.06520.037

G
[45] VGG_PG VR_READY change to 68.R3610.10M BY MAX
15

S
S
S
2D2R6J-3-GP SCD22U25V3KX-2-DL-GP PR4522
PWR_VGG_DIFFOUT 25 PVCC 8 PWR_VGG_BT 2 1 PWR_VGG_BTR 2 1 10KR2J-3-GP
PL4501

3
2
1
DIFFOUT BST 9 PWR_VGG_HG 2 1
PR45042 1 47R2F-GP PWR_VGG_COMP1 2
PC4511 1 SC330P50V2KX-3-DL-GP 2
PC4512 1 SC47P50V2JN-5DLGP PWR_VGG_COMP 23 HG 10 PWR_VGG_SW 1 2
COMP SW PWR_VGG_LG PWR_VCORE_VGG
12 IND-D36UH-19-GP
PC4513 LG 11
4X4 28PIN PGND

5
6
7
8

1
PR45052 1 1KR2F-3-GP PR45072 1 3K3R2F-2-GPPWR_VGG_COMP2 1 2 SC4700P50V2KX-1DLGP QFN

D
D
D
D
PWR_VGG_FB 24 PU4503
FB
1

AON6510-GP 11/07 REMOVE PU4504 by MAX PR4521

1
PWR_VCORE_VGG SC041 11/27 PC4519 FROM 78.12224.2FLDL 2D2R6J-3-GP
PR4506
(R_) 0126 modify PC4513 to 4700pf change to 78.15224.2FLDL(1500P) PG4501 PG4502

2
1

560KR2F-GP 18 PWR_VGG_CSSUM 4

G
GAP-CLOSE GAP-CLOSE
CSSUM PWR_VGG_CSMP1

S
S
S
R1826 PR4520
2

100R2F-L1-GP-U PR4510 19 PWR_VGG_CSCOMP PR45192 1 75KR2F-GP 2 1 150KR2F-L-GP PWR_VGG_SN

3
2
1

2
0R2J-2-GP CSCOMP PWR_VGG_ILIM
2 1 PWR_VGG_VSP 27 1 2 PC4519 1 2 SC1500P50V2KX-2-DL-GP

PWR_VGG_CSP

PWR_VGG_CSN
[18] VGG_SENSEN_P
2

VSP
1

PC4514
(R_) PR4511 R80185 PN4502

1
SC1KP16V2KX-DL-GP 1K5R2F-2-GP 21 1 2 NTC-100K-20-GP PC4520 1 2 SC220P50V2JN-3DLGP PC4529
2 1 PWR_VGG_VSN 26 ILIM 4K02R2F-GP SC1KP50V3KX-DLGP
[18] VGG_SENSEN_N SC051
2

VSN
1

1D8V_S5 1P05V_S5 -1006 11/27 PC4520 FROM 78.10134.1FLDL

2
1
R1827 PC4515 17 PWR_VGG_CSREF
100R2F-L1-GP-U CSREF change to 78.22134.1FLDL (220P)
SC3300P50V2KX-1DLGP 10/16 change to 084.06510.0037
1

(R_) 1/25 modify to 6.65K

2

1
R1830 R1831 5/19 modify to 4.02K PC4518 PR4517 1 2 105KR2F-1-GP
2

20KR2J-L2-GP 20KR2J-L2-GP SC1KP16V2KX-DL-GP

C 14 PWR_VGG_VBOOT/ADDR C

2
VGG_HOT 2 VBOOT/ADDR 16 PWR_VGG_IMAX PR4516 2 1 10R2J-2-GP
2

VR_HOT# IMAX 22 PWR_VGG_ROSC

PWR_VGG_TSEN 13 ROSC 20 PWR_VGG_IOUT

GND
TSENSE IOUT
1

11/27 RP4517 FROM 64.88725.6DL(88.7K)

1
change to 64.10535.60L(105K)

1
PR4513 NCP81201MNTXG-GP-U PC4517 PR4515

29
0R2J-2-GP SC470P50V2KX-3DLGP 33KR2F-GP
PWR_VGG_TSEN1
1 2

2
1

PUT COLSE SC078

2
2

TO VCORE -1005
PC4516
MOSFET

1
1 2 PN4501 PR4514 SCD1U16V2KX-3DLGP (R_) (R_)
[18,45] APU_PROCHOT#
1

R1606 0R2J-2-GP HOT SPOT NTC-100K-20-GP 62KR2F-GP

BOTTOM PAD
1/26 modify to 41.2 K TC19 TC18 TC17 TC16
5/19 modify to 33K E560U6D3VM-3-GP E560U6D3VM-3-GP E560U6D3VM-3-GP E560U6D3VM-3-GP
2

2
CONNECT TO
2

GND Through
6 VIAs

05/22 8*22U and 1*330U modify to 3*820U

08/11 Jeffrey change 820U to 560U

0804 Jeffrey modify ok to 48.7k

PWR_VGG_VBOOT/ADDR PWR_VGG_IMAX PWR_VGG_ROSC

1P05V_S5 PWR_VCORE_VGG
VCORE
VBOOT SET
1

AT 1V, VCORE Work F=

PR4531 PR4532 R80269 1 (R_) 2 0R3J-0-U-GP
SVID ADDR 48D7KR2F-GP IMAX SET 38K3R2F-GP 500Khz PR4533
00h AT 12A 18K7R2F-GP
B B
SC079 1A021
2

-1004

1/27 modify to 49.9K

5/19 modify to 38.3K

A A

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
VGG_(NCP81201)
Size Document Number Rev
Custom Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 46 of 105

5 4 3 2 1
 5 4 3 2 1

D D

EE need to check net name

PWR_0D95V_PVIN DCBATOUT

PR9799 1 2 GAP-CLOSE-PWR-3-GP

PR9789 1 2 GAP-CLOSE-PWR-3-GP

PWR_0D95V PR9876 1 2 GAP-CLOSE-PWR-3-GP

PR9877 1 2 GAP-CLOSE-PWR-3-GP

Caculated Valtage=0.954V
Vo=0.944V~0.963V 2.2uH, DCR= 18~20
OVP=1.192V PWR_0D95V_PVIN (G_) (G_)
mohm, Idc= 8A,
Iomax=4.3A PR5205 PC5451 Isat= 14A Iomax=4.3A
PU5208 2D2R3J-2-GP SCD1U25V3KX-DLGP
OCP>6.45A 1 10 PWR_0D95V_BOOT 1 2PWR_0D95V_BOOT_A
1 2
VIN BOOT PWR_0D95V
Fsw=500KHz PWR_0D95V_EN 13 PL4901
EN 8 PWR_0D95V_PH 1 2
SW#8
1

1
PC5441 PC5445 9 IND-2D2UH-122-GP-U
SW#9

1
SC10U6D3V3MX-DL-GP SC10U6D3V3MX-DL-GP PWR_0D95V 15 (G_)
SW#15

1
(G_) (G_) 16 (G_) (G_) (G_) (R_) (G_)
2

2
SW#16

1
C R79708 PR9794 (R_) PG5211 PC5446 PC5444 PC5448 PC5449 PC5437 C
2 PWR_0D95V_VBYP_2 3 PWR_0D95V_VOUT

SC22U6D3V3MX-1-DL-GP

SC22U6D3V3MX-1-DL-GP

SC22U6D3V3MX-1-DL-GP

SC22U6D3V3MX-1-DL-GP

SCD1U16V2KX-3DLGP
1 7 2D2R5J-1-GP PG5212 GAP-CLOSE-PWR-3-GP
0R2J-2-GP VBYP VOUT 12 PWR_0D95V_FB GAP-CLOSE-PWR-3-GP

2
2 FB PWR_0D95V_SNB
V_5P0_A PGND

1
PR9893 4 PWR_0D95V_PG PC5440 (R_) PWR_0D95V_FB_1
1 (R_) 2 5 PGOOD 11 PWR_0D95V_VCC
AGND VCC SC1KP50V3KX-DLGP
0R2J-2-GP 6

2
AGND

1
14 (G_)
AGND

1
Reserved PR9801
30K1R2F-L-GP
R1 PC5438
SC22P50V2JN-4DLGP
RT6220AGQUF-GP (R_)

2
1
(G_) PC5204

2
SC1U10V2KX-1DLGP
(G_)

1
Vout = 0.6*(1+R1/R2) (G_)
EE need to check sequence = 0.6*(1+30.1K/51K) PR9790
R2 PWR_0D95V 0D95V_S5
51KR2F-L-GP
= 0.954V

2
PR9796 1 2 GAP-CLOSE-PWR-3-GP

PR9800 1 2 GAP-CLOSE-PWR-3-GP
V_3P3_A
V_3P3_A PR9864 1 2 GAP-CLOSE-PWR-3-GP

PR9865 1 2 GAP-CLOSE-PWR-3-GP
1

1
PR9798 (R_) PR9891 1 2 GAP-CLOSE-PWR-3-GP
2KR2J-1-GP PR9791
2 (R_) 1 10KR2J-3-GP
[24,49,77,92] SIO_EUP_EN#
PR9792 0R2J-2-GP 1A013
2

2
PR9804
2 1 1 2
[49,50,92] PWR_1P05V_PG PWR_0P95V_PG [92]
B PR9797 0R2J-2-GP 0R0402-PAD-2-GP B
1A001

1
(R_) (R_)
1

2 (R_) 1 PC5439 PC5442

[52] 1P8V_PWR_PG
PR9803 0R2J-2-GP SCD1U10V2KX-4DLGP SCD1U10V2KX-4DLGP

2
2

2 (R_) 1
[85,86,87] GPU_CORE_PWROK
PR9886 0R2J-2-GP
2 (R_) 1
3D3V_VGA_S0
PR9887 10KR2J-3-GP EE need to check net name
1A012

1P8V_PWR_EN
H: Enable
L: Disable

A A

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
0D95V_S5_(RT6220A)
Size Document Number Rev
Custom Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 47 of 105

5 4 3 2 1
 5 4 3 2 1

V_SM
D D

SB5V 11/16
Caculated Valtage=1.369V CHANGE TO ZZ.CLOSE.001 PAD
VO=1.3545V~1.3837V
OVP=1.49V PR5011
Iomax=7.3A 1 2 DCBATOUT PWR_DDR4_VIN
OCP>10.95A

1
PC5004 2D2R5J-1-GP
Fsw=400KHz SC1U10V2KX-1DLGP
PWR_DDR4_VIN

2
PR5090 1 2 GAP-CLOSE-PWR-3-GP

PR5091 1 2 GAP-CLOSE-PWR-3-GP

PWR_DDR4_VDD

1
PC5003
PWR_DDR4_VIN SB3V PR5015 SC1U10V2KX-1DLGP (R_) PR9862 1 2 GAP-CLOSE-PWR-3-GP

1
5K9R2F-GP PC5001 PC5010 PT5001

2
PWR_DDR4_BT1 SC10U25V6KX-4DL-GP SC10U25V6KX-4DL-GP SE47U25VM-14-GP PR9861 1 2 GAP-CLOSE-PWR-3-GP

2
PWR_DDR4_CS
1

1
11/15 modify to 5.9K

5
6
7
8
PR5009 PC5008

D
D
D
D
750KR2F-GP PR5010 PR5019 SCD1U25V3KX-DLGP PQ5001

13

11

12
100KR2J-1-GP PU5001 2D2R5J-1-GP AON6520-GP

2
CS

VDD

VDDP
2

2
18 PWR_DDR4_BT 4 10/16 change to 84.06520.037 Iomax=7.3A

G
1D35V_S3_PWRGD BOOT

S
S
S
10 PR5018
[39] 1D35V_S3_PWRGD PGOOD 2D2R5J-1-GP

3
2
1
PWR_DDR4_TON 9 17 PWR_DDR4_UG 2 1 PWR_DDR4_UG1 V_SM
TON UGATE PL5002
8 IND-1D5UH-53-GP
[24,32,34,35,39,64,92,99] SLP_S4_N S5
VTT_EN 7 16 PWR_DDR4_LX 1 2
S3 PHASE
C PWR_DDR4_LDOIN 19 C
VLDOIN

1
15 PWR_DDR4_LG
LGATE PC5012

5
6
7
8
PR5017

SC22U6D3V3MX-1-DL-GP
D
D
D
D

1
MEM_VTT PWR_DDR4_VTT PQ5002 2D2R6J-3-GP
1 14 AON6510-GP PC5011 PTC21

2
VTTGND PGND SCD1U16V2KX-3DLGP E820U2D5VM-6-GP

2
(R_)

PWR_DDR4_SN

1
PR5012 5 PWR_DDR4_VDDQ 4

G
PC5002
VDDQ

S
S
S
0R0805-PAD SC22P50V2JN-4DLGP
1 2 PWR_DDR4_VTT 20 6 PWR_DDR4_FB

3
2
1

2
VTT FB
10/16 change to 084.06510.0037

1
2
VTTSNS
VTTREF

PR5016 SC057
16K9R2F-GP
Rt
GND

GND

1
PC5009
SC1KP50V3KX-DLGP

2
RT8207MZQW-GP-U Change from 8.06K to 16.9K
21

2
1

PC5005 PC5006
SC10U6D3V5KX-4DLGP-U SC10U6D3V5KX-4DLGP-U
PWR_DDR4_VTTREF
2

PC5007

1
SCD033U16V2KX-DLGP
PR5001 SC058
2

21K5R2F-GP
Rb
1

2
1

PR5013 Change from 10K to 21.5K

0R0805-PAD
B B
PR5014
2

0R0402-PAD V_SM DDR_VDDQ

2

PR5003 1 2 GAP-CLOSE-PWR-3-GP

PR5004 1 2 GAP-CLOSE-PWR-3-GP

PR5005 1 2 GAP-CLOSE-PWR-3-GP

PR5006 1 2 GAP-CLOSE-PWR-3-GP

PR5007 1 2 GAP-CLOSE-PWR-3-GP

PR5008 1 2 GAP-CLOSE-PWR-3-GP

PR9855 1 2 GAP-CLOSE-PWR-3-GP
R1576 1 (R_) 20R2J-2-GP 0820 jeffrey modify mount
[18,24,35,40,46,53,92,99] SLP_S3_N
PR9856 1 2 GAP-CLOSE-PWR-3-GP

R1577 1 20R2J-2-GP VTT_EN PR9857 1 2 GAP-CLOSE-PWR-3-GP

[45] VCC0_PG
PR9858 1 2 GAP-CLOSE-PWR-3-GP
R1578 1 (R_) 20R2J-2-GP
[92,99] SLP_S0_N
PR9859 1 2 GAP-CLOSE-PWR-3-GP

PR9860 1 2 GAP-CLOSE-PWR-3-GP

11/16
CHANGE TO ZZ.CLOSE.001 PAD

A A

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
V_SM/VTT_(RT8207M)
Size Document Number Rev
C Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 48 of 105

5 4 3 2 1
 5 4 3 2 1

11/16
CHANGE TO ZZ.CLOSE.001 PAD
D D

DCBATOUT PWR_1P05V_VIN

PR4790 1 2 GAP-CLOSE-PWR-3-GP

PR4791 1 2 GAP-CLOSE-PWR-3-GP

PR9844 1 2 GAP-CLOSE-PWR-3-GP
Caculated Valtage=1.0493V PR9845 1 2 GAP-CLOSE-PWR-3-GP
1P05V_A Vo=1.039V~1.060V VIN RIPPLE CURRENT Imax=1.37A
OVP=1.300V
Iomax=6A PWR_1P05V_VIN
OCP>9A
PWR_1P05V_VIN
Fsw=290KHz
(R_)

1
PT4702

1
PC4706 SE47U25VM-14-GP
SC10U25V6KX-4DL-GP

2
2
5
6
7
8
D
D
D
D
PQ4701
1P05V_S5 SIS412DN-T1-GE3-GP
PR4716
V_3P3_A 2D2R5J-1-GP
Iomax=6A
1
1A005 2 1PWR_1P05V_HG_1

G
S
S
S
(R_)
1

05/27 Allen modify (R_) PR4712

4
3
2
1
PR5214 10KR2J-3-GP
1KR2J-1-GP PU4701 1P05V_A
2

C PR4714 C
PWR_1P05V_PG 1 11 2D2R5J-1-GP PL4701
2

PR5254 [47,50,92] PWR_1P05V_PG PWR_1P05V_CS 2 PGOOD GND 10 PWR_1P05V_BOOT 2 1PWR_1P05V_BOOT_1 1 2 IND-1D5UH-53-GP

2 1 PWR_1P05V_EN 3 CS BOOT 9 PWR_1P05V_HG PC4703 SCD1U25V3KX-DLGP
[24,47,77,92] SIO_EUP_EN# PWR_1P05V_FB 4 EN UGATE 8 PWR_1P05V_LX 1 2
0R0402-PAD-2-GP
(R_) PWR_1P05V_RF 5 FB PHASE 7 PWR_1P05V_VCC
1

RF VCC

1
6 PWR_1P05V_LG
1A001 PC5211
LGATE
SCD1U10V2KX-4DLGP PR4713
1

2D2R5J-1-GP 11/15 modify to 4.99K

2

5
6
7
8
PR4702 RT8237CZQW-2-GP V_5P0_A PQ4702

D
D
D
D

1
R79802 PC4701 470KR2F-GP SIS780DN-T1-GE3-GP
(

1
100KR2F-L1-GP R PR4701 PWR_1P05V_SN (R_) PR4717 PC4708
R1
2

_)

1
SCD1U10V2KX-4DLGP

1 2 PC4705 4K99R2F-L-GP PC4707 SC10U6D3V5KX-4DLGP-U PTC19

2

1
PC4704 SC22P50V2JN-4DLGP SCD1U16V2KX-3DLGP E820U2D5VM-6-GP
2

2
2D2R5J-1-GP Needs EE confirm 4

G
SC1KP50V3KX-DLGP

2
S
S
S
Sequence!!!

2
1
PC4702

3
2
1
11/12 modify to 100K RF=470K ohm, SC1U10V2KX-1DLGP
PWM Freq=290K Hz

2
PWR_1P05V_FB

1
PR4718
R2 10KR2F-2-GP

VOut=0.7(1+(R1/R2))

2
7/29 change to 0805

1P05V_A 1P05V_S5

B B

PR4703 1 2 6/11 Allen add

0R0805-PAD-2-GP-U

PR4704 1 2
7/29
0R0805-PAD-2-GP-U Remove R1848~R1855
PR4705 1 2
0R0805-PAD-2-GP-U

7/29 change to 0805

1P05V_A PWR_VCORE_VNN

PR4706 1 2
0R0805-PAD-2-GP-U

PR4708 1 2
0R0805-PAD-2-GP-U

PR4707 1 2
0R0805-PAD-2-GP-U

PR4709 1 2
0R0805-PAD-2-GP-U

A A

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
1P05V_S5_(RT8237C)
Size Document Number Rev
C Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 49 of 105

5 4 3 2 1
 5 4 3 2 1

11/16
CHANGE TO ZZ.CLOSE.001 PAD EE need to check net name
PWR_1D15V_A PWR_1D15V_PVIN V_5P0_A

PR5290 1 2 GAP-CLOSE-PWR-3-GP
Caculated Valtage=1.15V
D
Vo=1.138V~1.161V PR5291 1 2 GAP-CLOSE-PWR-3-GP D

OVP=1.366V PR9872 1 2 GAP-CLOSE-PWR-3-GP

Iomax=1A PWR_1D15V_PVIN
1.5uH Iomax=1A
PR9873 1 2 GAP-CLOSE-PWR-3-GP
OCP>1.5A DCR=14~15 mohm OCP>1.3A
Fsw=1MHz PU5206 Idc=9A, Isat=18A
RT8068AZQWID-GP-U
1

PL5004

1
PR5475 PC5257 PC5260 10 1 IND-1D5UH-53-GP PWR_1D15V_A
2D2R5J-1-GP SC10U6D3V3MX-DL-GP SC10U6D3V3MX-DL-GP PVIN LX#1
9 2 PWR_1D15V_LX 1 2
2

2
PVIN LX#2
2

1
PWR_1D15V_SVIN 8 3 0812 Jeffrey modify for power team
SVIN LX#3

1
PC5261 PC5258 PC5264
7 (R_) PR5474 SC22U6D3V3MX-1-DL-GP SC22U6D3V3MX-1-DL-GP SCD1U16V2KX-3DLGP
NC#7
1

1
PC5259 PWR_1D15V_EN 5 2D2R5J-1-GP

2
SC1U10V2KX-1DLGP EN 6 PWR_1D15V_FB R79796 SC060 SC059

2
FB

1
4 PWR_1D15V_SN 47KR2F-GP PC5262
2

PGOOD 11 SC33P50V2JN-3DLGP
GND

1
PC5263 (R_) Change from 10UF to 22UF Change from 10UF to 22UF

2
SC1KP50V3KX-DLGP R1 SC061

2
C C
Change from 22PF to 33PF
08/07 Richardmodify
V_3P3_A

1
PC5265 PWR_1D15V_A 1P15V_S5
1

0812 Jeffrey modify for power team SC680P50V2KX-2DLGP

PWR_1D15V_FB_N
PR5480

2
2KR2J-1-GP
1A001
R2 SC062
PR5471 1 2 GAP-CLOSE-PWR-3-GP

1
1A013 Change to stuff
0.6*(1+R1/R2)
2

PR5479 R79800 PR9863 1 2 GAP-CLOSE-PWR-3-GP

2 1 51KR2F-L-GP
[47,49,92] PWR_1P05V_PG
0R0402-PAD-2-GP
=0.6*(1+107/115)
=1.15V 11/16

2
(R_) CHANGE TO ZZ.CLOSE.001 PAD
1

1
PC5266
SCD1U10V2KX-4DLGP PR5473
14KR2F-GP
2

SC063

2
Change to stuff
B B

1P15V_S5
1

(R_)
PR4812
10KR2J-3-GP
2

PWR_1P15V_PG
[51,92] PWR_1P15V_PG
1

(R_)
PC4801
SCD1U10V2KX-4DLGP
2

<Variant Name>
A A
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
1P15V_S5_(RT8068A)
Size Document Number Rev
B Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 50 of 105
5 4 3 2 1
 5 4 3 2 1

4/29
Remove 1D2V
D D

V_3P3_A

PWR_V1P24A V1P24A 05/27 Allen modify

1
C
Caculated Valtage=1.239V
MAX=0.5A PR5213
10KR2J-3-GP
C

2
VO=1.2266V~1.2513V PWR_V1P24A_PG [52,92]
Iomax=0.5A (R_)

1
PC5217
EE need to check sequence and net name SCD1U10V2KX-5DLGP

2
V_3P3_A

Pd=(3.3-1.24)*0.5=1.03W V_5P0_A

2
V_3P3_A
PC5212

1
1D24V_S5 PWR_V1P24A SC10U6D3V3MX-DL-GP

1
PC5213
PU5201 SC1U25V3KX-1-DLGP

2
PR9871 1 2 GAP-CLOSE-PWR-3-GP PR5241
5 1KR2J-1-GP
PR5209 1 2 GAP-CLOSE-PWR-3-GP 4 VIN#5 6

2
3 VOUT#4 VCNTL 7 PWR_V1P24A_PG
VOUT#3 POK
2

B PC5215 PC5219 2 8 PWR_V1P24A_EN 1 PR5216 2 B

PC5216 SC10U6D3V3MX-GP SC100P50V2JN-3GP 1 FB EN 9 0R0402-PAD PWR_1P15V_PG [50,92]
SC10U6D3V3MX-DL-GP (R_) (R_) GND VIN#9
1

PWR_V1P24A_FB (R_)

1
APL5930KAI-TRG-1-GP PC5222
SCD1U10V2KX-4DLGP
PWR_V1P24A V_3P3_A

2
1

PR5211
5K49R2F-GP
R1 EE need to check sequence of EN & PG
2
1

Vout = 0.8*(1+R1/R2)=1.2392V
R2 PR5212
10KR2F-2-GP
2

A Wistron Incorporated A
12F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
1D24V_S5_(APL5930)
Size Document Number Rev
Custom Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 51 of 105

5 4 3 2 1
 5 4 3 2 1

power team PWR_1D8V 1D8V_S5

PR5102 1 2 GAP-CLOSE-PWR-3-GP
EE
PWR_1D8V PR9824 1 2 GAP-CLOSE-PWR-3-GP

PR9825 1 2 GAP-CLOSE-PWR-3-GP
D
V_5P0_A--> V_1P8_A PR9883 1 2 GAP-CLOSE-PWR-3-GP
D

Caculated Valtage=1.8V PR9882 1 2 GAP-CLOSE-PWR-3-GP

1D8V Vo=1.782V~1.818V
OVP=12.13V PR9881 1 2 GAP-CLOSE-PWR-3-GP

Iomax=2A 11/16
CHANGE TO ZZ.CLOSE.001 PAD
OCP>3A
Fsw=1MHz
V_5P0_A PWR_1D8V_PVIN Iomax=2A

PR5103 1 2 PU5101 PWR_1D8V

GAP-CLOSE-PWR-3-GP RT8068AZQWID-GP-U
PL5101
1

PR9878 1 2 PR5104
GAP-CLOSE-PWR-3-GP PC5102 1 2 PWR_1D8V_SVIN 10 1 PWR_1D8V_PH 1 2
PR9879 1 2 SC10U6D3V3MX-DL-GP 5D1R2F-GP PVIN LX#1 IND-1D5UH-53-GP
2

1
GAP-CLOSE-PWR-3-GP PC5104 9 2
PVIN LX#2
1

PR9880 1 2 PC5103 SC1U6D3V2KX-DLGP PR5105

GAP-CLOSE-PWR-3-GP SC10U6D3V3MX-DL-GP 8 3 2D2R6J-3-GP

2
SVIN LX#3

1
(R_) PC5105 PC5101 PC5106
2

C C
7 (R_)

2
NC#7

SC22U6D3V3MX-1-DL-GP

SC22U6D3V3MX-1-DL-GP

SC22U6D3V3MX-1-DL-GP
11/16 PWR_1D8V_EN 5

2
EN 6 PWR_1D8V_FB PWR_1D8V_SNB
CHANGE TO ZZ.CLOSE.001 PAD FB
PWR_1P8V_PG 4
PGOOD

1
11 PC5107
GND

1
SC1500P50V3KX-DLGP PC5108

1
(R_) SC22P50V2JN-4DLGP

2
PR5101
R1

2
102KR2F-GP

PR5259 2 1 0R0402-PAD
[51,92] PWR_V1P24A_PG

1
PC5109
Need EE to check

1
SC680P50V2KX-2DLGP
PR5107 (R_)
Vout = 0.6*(1+R1/R2)

2
51KR2F-L-GP
V_3P3_A = 0.6*(1+102K/51K) R2 PWR_1D8V_FB_A

1
= 1.8V

2
PR5108
18KR2F-GP
1

B 1A001 (R_) B
PR9802

2
R80195 2 1 10KR2J-3-GP
[41,92] SB3V_5V_PG 0R0402-PAD-2-GP (R_)
2

R80122 2 1
[47] 1P8V_PWR_PG 0R0402-PAD-2-GP
1

PC5230
SCD1U16V2KX-3DLGP
2

(R_)

<Variant Name>
A A
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
1D8V_S5_(RT8068A)
Size Document Number Rev
B Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 52 of 105
5 4 3 2 1
 5 4 3 2 1

SB3V

PWR_V1P5A

1
EE need to check sequence and net name
V1P5S SB3V
PR40
10KR2J-3-GP
Caculated Valtage=1.5V
MAX=0.5A

2
D VO=1485V~1.515V SB5V D

1
PC27
Iomax=0.5A

2
SCD1U16V2KX-3DLGP
PC5112

2
1
1D5V_S0 PWR_V1P5A SC10U6D3V3MX-DL-GP

1
PR9870 PC5113
GAP-CLOSE-PWR-3-GP PU5202 SC1U25V3KX-1-DLGP

2
1 2
5
1 2 4 VIN#5 6
PR5109 3 VOUT#4 VCNTL 7 PWR_V1P5S_PG PR5110
VOUT#3 POK
2

1
GAP-CLOSE-PWR-3-GP PC5115 PC5114 2 8 PWR_V1P5S_EN 1 2
PC5116 SC10U6D3V3MX-GP SC100P50V2JN-3GP 1 FB EN 9 0R0402-PAD SLP_S3_N [18,24,35,40,46,48,92,99]
SC10U6D3V3MX-DL-GP (R_) (R_) GND VIN#9
1

1
PWR_V1P5A_FB PC5221
APL5930KAI-TRG-1-GP SC22P50V2JN-4DLGP
11/16 PWR_V1P5A (R_)

2
CHANGE TO ZZ.CLOSE.001 PAD SB3V

1
change PC5221 from 78.22044.1FL to 78.22034.1FLDL
PR5113
8K66R2F-GP
C R1 EE need to check sequence of EN & PG C

R2 2
1 PR5112 Vout = 0.8*(1+R1/R2)=1.5V
10KR2F-2-GP
2

DCBATOUT 1D8V_S5

1
DCBATOUT
R163
47KR2J-2-GP Iomax=0.018A

D
1.8V_S0
1

B Q6705 B
Q23

2
R153 R164 AO3418L-GP
100KR2J-1-GP 4 3 1D8V_S0_EN2 1 2 1D8V_S0_EN_G G
10KR2J-3-GP
5 2
2

S
1

1
C97 (R_)
1D8V_S0_EN1 6 1 R162 SCD1U50V3KX-GP 1D8V_S0
100KR2J-1-GP

2
VCC3 2N7002EDW-2-GP
1

1
(75.27002.F7C) C96
2

R151 SCD1U50V3KX-DL-GP

1
100KR2J-1-GP

2
R152 C90
1

4K7R2J-2-GP SC10U10V5KX-2GP C89

2

(R_) SCD1U16V2KX-3DLGP

1
PR5

2
10KR2F-2-GP
1A001
2

R1683
1D8V_S0_EN_R 1 2 1D8V_S0_EN <Variant Name>
0R0402-PAD-2-GP
A Wistron Incorporated A
1

C100 21F, 88, Hsin Tai Wu Rd

SCD1U50V3KX-GP Hsichih, Taipei
(R_)
2

Title
1D5V_S0_(APL5930)
Size Document Number Rev
Custom Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 53 of 105
5 4 3 2 1
 5 4 3 2 1

1P05V_S5 1P05V_S5

1
R1656 R1662 1P05V_S5
200R2F-L-GP 200R2F-L-GP

1
2

2
1A003 R1660
301R2F-GP

2
D D
1A004 1A003
1A001
PR5233 2 1 0R0402-PAD-2-GP VCC_SVID_CLK_R R1655 1 2 200R2F-L-GP
[18] VR_SVID_CLK VCC_SVID_CLK [45]

PR5232 2 1 0R0402-PAD-2-GP VCC_SVID_DATA_R R1653 1 2 20R2F-GP

[18] VR_SVID_DATA VCC_SVID_DATA [45]
1A005
PR5234 2 1 0R0402-PAD-2-GP VCC_SVID_ALERT_R R1654 1 2 49D9R2F-GP
[18] VR_SVID_ALERT# VCC_SVID_ALERT [45]

1P05V_S5
C C

1
R1659
200R2F-L-GP 1P05V_S5

1
1A003
R1658
301R2F-GP

2
1A001 1A004
PR5220 2 1 0R0402-PAD-2-GP VGG_SVID_CLK_R R1657 1 2 200R2F-L-GP
VGG_SVID_CLK [46]

PR5221 2 1 0R0402-PAD-2-GP VGG_SVID_DATA_R R1647 1 2 20R2F-GP

VGG_SVID_DATA [46]
1A005
PR5222 2 1 0R0402-PAD-2-GP VGG_SVID_ALERT_R R1648 1 2 49D9R2F-GP
VGG_SVID_ALERT [46]

B B

A A

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
SVID
Size Document Number Rev
Custom Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 54 of 105
5 4 3 2 1
 5 4 3 2 1

APU DP to RTD2168 11/07 VEDER MODIFY 11/08 Del pin2&3 I2C level shift

R80074 2 (U_) 1 0R2J-2-GP DP1_TXP0 VCC3

[8] DP_CPU_TXP0 DP1_TXN0
[8] DP_CPU_TXN0 R80075 2 (U_) 1 0R2J-2-GP

1
[77] DP_GPU_TXP0 R80079 1 (G_) 2 0R2J-2-GP
[77] DP_GPU_TXN0 R80078 1 (G_) 2 0R2J-2-GP R80131 R80132
4K7R2J-2-GP 4K7R2J-2-GP

2
R80076 2 (U_) 1 0R2J-2-GP DP1_TXP1
[8] DP_CPU_TXP1 DP1_TXN1
[8] DP_CPU_TXN1 R80077 2 (U_) 1 0R2J-2-GP
D D

R80140
R80081 1 (G_) 2 0R2J-2-GP SMB_SCL_IC 2 1 0R2J-2-GP
[77] DP_GPU_TXP1 SMB0_CLK_MAIN [12,17,37,77]
[77] DP_GPU_TXN1 R80080 1 (G_) 2 0R2J-2-GP
R80141
SMB_SDA_IC 2 1 0R2J-2-GP
SMB0_DATA_MAIN [12,17,37,77]

R80116 1 (U_) 2 0R2J-2-GP DP1_AUXP

[8] DP_CPU_AUXP DP1_AUXN
R80100 1 (U_) 2 0R2J-2-GP 11/07 VEDER MODIFY
[8] DP_CPU_AUXN
VCC3
R80118 1 (G_) 2 0R2J-2-GP
[77] DP_GPU_AUXP
R80117 1 (G_) 2 0R2J-2-GP
[77] DP_GPU_AUXN

1
R5502 SB028
10R2J-2-GP
(R_) Add by 12/14
U58 R80220

2
0R2J-2-GP
C745 1 2 SCD1U10V2KX-5DLGP EDP_AVC33 24 1 DP1_HPD_2168 R5501 1 2 1KR2J-1-GP VGA_HPD 1 (U_) 2
AVCC_33 HPD DP1_HPD [8]

1
VCC3 C754 1 2 SCD1U10V2KX-5DLGP EDP_AVC12 25 2 SMB_SCL_IC
AVCC_12 SMB_SCL 3 SMB_SDA_IC R5505 R80221
5 SMB_SDA 100KR2F-L1-GP 0R2J-2-GP
20 DVCC_33 4 EDP_5VDDCCL 1 (G_) 2
DVCC_33 VGA_SCL GPU_DP_DET_CN [77]
1

C755 C756 6 EDP_5VDDCDA

2
EDP_AVC12 19 VGA_SDA
SCD1U10V2KX-5DLGP SCD1U10V2KX-5DLGP VCCK_12
2

EDP_DAC33 9 7 EDP_VSYNC
VDD_DAC_33 VSYNC 8 EDP_HSYNC
HSYNC
R407 1 2 4K7R2J-2-GP EDP_LDO_EN 21 15 EDP_RED_P
VCC3 LDO_EN RED_P 16
DP1_AUXP C748 1 2 SCD1U10V2KX-5DLGP EDP_AUX_P 26 RED_N
DP1_AUXN C749 1 2 SCD1U10V2KX-5DLGP EDP_AUX_N 27 AUX_P 12 EDP_GREEN_P
AUX_N GREEN_P 13
C C
DP1_TXP0 C750 1 2 SCD1U10V2KX-5DLGP EDP_LANE0_P 29 GREEN_N
DP1_TXN0 C751 1 2 SCD1U10V2KX-5DLGP EDP_LANE0_N 30 LANE0P 10 EDP_BLUE_P

DP1_TXP1 EDP_LANE1_P
LANE0N BLUE_P
BLUE_N
11 Mode Configure Table(Power On Latch)
C752 1 2 SCD1U10V2KX-5DLGP 31
DP1_TXN1 C753 1 2 SCD1U10V2KX-5DLGP EDP_LANE1_N 32 LANE1P 22 POL1_SDA
LANE1N POL1_SDA POL2_SCL
POL2_SCL
23 POL1_SDA(PIN22)
12/21 VENDER MODIFY XI2168 17
XI/CKIN
18 14
XO2169
XO GND_DAC 0 1
RRX2168 28 33
RRX GND
0 X EP MODE
1

POL2_SCL(PIN23)
R80138 R80139 RTD2168-CGT-GP
0R2J-2-GP 4K7R2J-2-GP R5504 1 ROM ONLY MODE EEPROM MODE
(R_) 12KR2F-L-GP

EP Mode
2

VCC3 VCC3
RTD2168 Slave Address:

1
0x64/0x65
R403 R5503 RTD2168 Supports three operation mode for system design.
4K7R2J-2-GP 4K7R2J-2-GP
VGA_PWR (R_) Reserve 4.7K resistor pull high/low for mode selection

2
POL1_SDA
POL2_SCL
1

1
C772 ROM ONLY Mode : PIN22 pull low, PIN23 pull high
SCD1U10V2KX-5DLGP
R405 R406 EP Mode : PIN22 pull high, PIN23 pull low
2

4K7R2J-2-GP 4K7R2J-2-GP
U59 (R_) EEPROM Mode : PIN22 pull high, PIN23 pull high

2
VGA_CABLE_DET 1 6 GREEN_CRT
I/O1 I/O4
2 5
B GND VDD B
BLUE_CRT 3 4 RED_CRT
I/O2 I/O3

AZC099-04S-R7G-GP 11/07 VENDER MODIFY

(075.02304.007C)
VGA_PWR
VCC
1

C773
A

SCD1U10V2KX-5DLGP L60 1 2 MHC1608S600QBP-GP EDP_AVC33

VCC3
D27
2

1SS355GP-GP

1
U60 C744 EDP_AVC12
SC10U10V3MX-1-GP
K

EDP_VSYNC_C 1 6 EDP_5VDDCCL

2
I/O1 I/O4

1
F19 Change to 069.50001.0031 C758 C757
2 5 VGA_DDC_PU SC2D2U10V3KX-1DLGP-U SCD1U10V2KX-5DLGP
GND VDD F19 SC015

2
1

EDP_HSYNC_C 3 4 EDP_5VDDCDA POLYSW-1D5A6V-12-GP

I/O2 I/O3 VGA_PWR EDP_DAC33
R402 R401 1 2 5V_DISPLAY_S0 VCC3 L61 1 2 MHC1608S600QBP-GP C758 X5R
2K2R2J-2-GP 2K2R2J-2-GP
Close pin19

1
AZC099-04S-R7G-GP C746 C747
(075.02304.007C) SC10U10V3MX-1-GP SCD1U10V2KX-5DLGP
2

VGA1

2
C769 1 2 SCD1U10V2KX-5DLGP 9 4 VGA_CABLE_DET 1
VCC_CRT NC#4 TP4126 TPAD30
1

C12381 11
C12379 C12380 SC22P50V2JN-4DLGP NC#11
EDP_5VDDCDA 12 1 2
CHAR_EN_CPU [17]
2

SC22P50V2JN-4DLGP EDP_5VDDCCL 15 DDCDATA_ID1

SC042 DDCCLK_ID3
R80274
SC22P50V2JN-4DLGP 5 0R0402-PAD-2-GP
EDP_RED_P L47 1 2 BLM18BB470SN1-GP RED_CRT 1 GND 6
EDP_GREEN_P GREEN_CRT CRT_RED GND -1001
L12 1 2 BLM18BB470SN1-GP 2 7
EDP_BLUE_P L13 1 2 BLM18BB470SN1-GP BLUE_CRT 3 CRT_GREEN GND 8
A
CRT_BLUE GND 10 VGA Cable Detect A
1

GND
C767 C760 C766 14
13 VSYNC GND
16
17
H: No detect (1.8V)
SC22P50V2JN-4DLGP SC22P50V2JN-4DLGP SC22P50V2JN-4DLGP
R408 R409 R410 HSYNC GND L: Detect
2

75R2F-2-GP 75R2F-2-GP 75R2F-2-GP

D-SUB-15-130-GP
2

20150118 modify to 47ohm & 22pF 20.20951.015 <Variant Name>

1A010 Wistron Incorporated
EDP_VSYNC R411 1 2 36R2J-GP EDP_VSYNC_C 21F, 88, Hsin Tai Wu Rd
EDP_HSYNC EDP_HSYNC_C Hsichih, Taipei
R420 1 2 36R2J-GP
Title
1

11/07 VENDER MODIFY C771 C770 DP to VGA_(RTD2168)

SC10P50V2JN-4DLGP SC10P50V2JN-4DLGP
Size Document Number Rev
2

C Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 55 of 105
5 4 3 2 1
 5 4 3 2 1

ESD
HDMI from CPU U131 (R_)
TR20 (U_068.10129.2011)
(U_) HDMI_LANE0_DN_C HDMI_LANE0_DN HDMI_LANE2_DP 5 6 HDMI_LANE2_DP
[8,56] HDMI_DATA_CPU_P0 C4279 1 2 SCD1U16V2KX-3DLGP 1 2 HDMI_LANE2_DN LINE_4 NC#6 HDMI_LANE2_DN
[8,56] HDMI_DATA_CPU_N0 4 7
[8,56] HDMI_DATA_CPU_N0 LINE_3 NC#7
(U_) 2SCD1U16V2KX-3DLGP 3 8

20
22
[8,56] HDMI_DATA_CPU_P1 C4272 1 HDMI_LANE0_DP_C 4 3 HDMI_LANE0_DP
[8,56] HDMI_DATA_CPU_P0 HDMI_LANE3_DP 2 GND GND 9 HDMI_LANE3_DP HDMI1
[8,56] HDMI_DATA_CPU_N1 HDMI_LANE3_DN LINE_2 NC#9 HDMI_LANE3_DN HDMI_LANE0_DP
1 10 1
[8,56] HDMI_DATA_CPU_P2 LINE_1 NC#10
FILTER-4P-120-GP
[8,56] HDMI_DATA_CPU_N2 2
TR21 (U_068.10129.2011)
[8,56] HDMI_DATA_CPU_P3 HDMI_LANE0_DN
(U_) C4274 1 2 SCD1U16V2KX-3DLGP HDMI_LANE1_DN_C 1 2 HDMI_LANE1_DN AZ1045-04F-R7G-GP 3
[8,56] HDMI_DATA_CPU_N3 [8,56] HDMI_DATA_CPU_N1 HDMI_LANE1_DP 4
(U_) C4273 1 2 SCD1U16V2KX-3DLGP HDMI_LANE1_DP_C 4 3 HDMI_LANE1_DP 5
[8,56] HDMI_DATA_CPU_P1 U129 (R_) HDMI_LANE1_DN 6
HDMI_LANE2_DP 7
D [8,56] HDMI_CTRL_CLK FILTER-4P-120-GP HDMI_LANE0_DP 1 10 HDMI_LANE0_DP 8 D
[8,56] HDMI_CTRL_DATA TR22 (U_068.10129.2011) HDMI_LANE0_DN 2 LINE_1 NC#10 9 HDMI_LANE0_DN HDMI_LANE2_DN 9
(U_) 3 LINE_2 NC#9 8 HDMI_LANE3_DP 10
C4276 1 2 SCD1U16V2KX-3DLGP HDMI_LANE2_DN_C 1 2 HDMI_LANE2_DN
[8,56] HDMI_DATA_CPU_N2 HDMI_LANE1_DP 4 GND GND 7 HDMI_LANE1_DP 11
[8] DDSP_C_HPD_CONN
(U_) HDMI_LANE2_DP_C HDMI_LANE2_DP HDMI_LANE1_DN 5 LINE_3 NC#7 6 HDMI_LANE1_DN SC017 HDMI CLK HDMI_LANE3_DN 12
C4275 1 2 SCD1U16V2KX-3DLGP 4 3 LINE_4 NC#6
[8,56] HDMI_DATA_CPU_P2 13
5V_DISPLAY_S0 14
FILTER-4P-120-GP AZ1045-04F-R7G-GP DDPC_CTRL_CLK_CONN 15
TR23 (U_068.10129.2011) F13 DDPC_CTRL_DATA_CONN 16
(U_) C4278 1 2 SCD1U16V2KX-3DLGP HDMI_LANE3_DN_C 1 2 HDMI_LANE3_DN POLYSW-1D5A6V-12-GP L46 17
[8,56] HDMI_DATA_CPU_N3 1 2 V_5P0_HDMI_CONN_L 2 1 V_5P0_HDMI_CONN 18
(U_) HDMI_LANE3_DP_C HDMI_LANE3_DP U130 (R_) 0R0805-PAD DDSP_C_HPD_CONN 19
C4277 1 2 SCD1U16V2KX-3DLGP 4 3
[8,56] HDMI_DATA_CPU_P3

2
DDPC_CTRL_CLK_CONN 1 10 DDPC_CTRL_CLK_CONN

21
23
DDPC_CTRL_DATA_CONN 2 LINE_1 NC#10 DDPC_CTRL_DATA_CONN
HDMI CLK Place near HDMI Connector FILTER-4P-120-GP HDMI CLK 9 C714 C721

1
R5602 R5603 R5604 R5605 R5606 R5607 R5608 R5609 3 LINE_2 NC#9 8 SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP

1
GND GND

1
470R2J-2-GP 470R2J-2-GP 470R2J-2-GP 470R2J-2-GP 470R2J-2-GP 470R2J-2-GP 470R2J-2-GP 470R2J-2-GP DDSP_C_HPD_CONN 4 7 DDSP_C_HPD_CONN
(U_) (U_) (U_) (U_) (U_) (U_) (U_) (U_) from 68.10129.201 to 068.10129.2011 5 LINE_3 NC#7 6 R80275 SKT-HDMI23-47-GP
LINE_4 NC#6 0R2J-2-GP 62.10078.641

2
DDSP_D_TX_N0
AZ1045-04F-R7G-GP

2
SIO_GPU_EN [24,87]
Please follow PDS Recommend Resistor Value:
Intel Braswell use 470 ohms 5% -1002

D
Q1254 HDMI Cable Detect
R5601 1 (U_) 2 100KR2J-1-GP DDSP_D_TX_N2 G
2N7002A-7-GP
(U_84.2N702.J31)
H: Detect (5V)
VCC3 VCC L: No detect

A
D33 SC016
VCC_DDC_HDMI 1SS355GP-GP
1D8V_S5

K
VCC_DDC_HDMI 1D8V_S5 5V_DISPLAY_S0
VCC12

1
C4280

1
SCD1U16V2KX-3DLGP R5613 R5612 R79737 R79736

1
2K2R2J-2-GP 2K2R2J-2-GP Q1256 2K2R2J-2-GP 2K2R2J-2-GP

D
DMN5L06K-7-GP R80259

1
(U_) 20KR2F-L-GP Q9644

2
AO3418L-GP R80260

2
DDPC_CTRL_DATA_CONN D S HDMI_CTRL_DATA 5V_DISPLAY_S0_G G 0R5J-5-GP
HDMI_CTRL_DATA [8,56]
(R_)

1
C12411

2
Q1255 SCD1U25V3KX-DLGP

G
C DMN5L06K-7-GP R80261 (R_) C

2
(U_) 100KR2J-1-GP

1
DDPC_CTRL_CLK_CONN D S HDMI_CTRL_CLK C12412
HDMI_CTRL_CLK [8,56]
SCD1U25V3KX-DLGP VCC
(R_)

2
Main source: 84.05067.031 FET MOS DMN5L06K-7 NC SOT-23 3P
2nd source: 84.00301.A31 FET MOS FDV301N NC SOT-23

For layout routing, 與 TR20~TR23 正正 正

from 68.10129.201 to 068.10129.2011
0711 Jeffrey modify for HDMI re-Driver
VCC3 U9628 (G_)
FILTER-4P-120-GP
11 25 HDMI_LANE2_IC_DP HDMI_LANE0_IC_DP 1 2 HDMI_LANE0_DP
VCC3 V_1P5_HDMI 37 VDD33 OUT_D0P 24 HDMI_LANE2_IC_DN
V_1P5 VDD33 OUT_D0N 27 HDMI_LANE1_IC_DP HDMI_LANE0_IC_DN 4 3 HDMI_LANE0_DN
12 OUT_D1P 26 HDMI_LANE1_IC_DN
40 VDDRX OUT_D1N 30 HDMI_LANE0_IC_DP TR35 (G_068.10129.2011)
VDDRX OUT_D2P 29 HDMI_LANE0_IC_DN
-1011 OUT_D2N
2

20 FILTER-4P-120-GP
31 VDDTX 22 HDMI_LANE3_IC_DP HDMI_LANE1_IC_DP 1 2 HDMI_LANE1_DP
HDMI from GPU U9629 (G_)
C12386
SC10U10V5KX-2DLGP
For layout routing, 與C4272~C4279 正正 正 VDDTX OUT_CKP 21 HDMI_LANE3_IC_DN
HDMI CLK
1

(G_) V_1P5_HDMI 19 OUT_CKN HDMI_LANE1_IC_DN 4 3 HDMI_LANE1_DN

3 VDDTA 8
INPUT 2 I2C_CTL_EN Check PIN TR36 (G_068.10129.2011)
OUTPUT 1 (G_) C12387 1 2SCD1U16V2KX-3DLGP HDMI1_DATA_IC_P2 6 17 EQ
[56,77] HDMI_DATA_GPU_N0 ADJ/GND [56,77] HDMI_DATA_GPU_P2 IN_D0P EQ/I2C_ADDR0
1

(G_) C12388 1 2SCD1U16V2KX-3DLGP HDMI1_DATA_IC_N2 7 23 CFG FILTER-4P-120-GP

B [56,77] HDMI_DATA_GPU_N2 HDMI1_DATA_IC_P1 IN_D0N CFG/I2C_ADDR1 HDMI_LANE2_IC_DP HDMI_LANE2_DP
[56,77] HDMI_DATA_GPU_P0 (G_) C12389 (G_) C12390 1 2SCD1U16V2KX-3DLGP 4 1 2 B
[56,77] HDMI_DATA_GPU_P1 1 2SCD1U16V2KX-3DLGP HDMI1_DATA_IC_N1 5 IN_D1P 16
AZ1117CR-ADJTRG1-GP-U R80222 SCD1U16V2KX-3DLGP (G_) C12391 PRE
R2 [56,77] HDMI_DATA_GPU_N1
1

180R3F-GP (G_) (G_) C12392 1 2SCD1U16V2KX-3DLGP HDMI1_DATA_IC_P0 1 IN_D1N PRE 34 ISET HDMI_LANE2_IC_DN 4 3 HDMI_LANE2_DN
[56,77] HDMI_DATA_GPU_P0 1 2SCD1U16V2KX-3DLGP HDMI1_DATA_IC_N0 2 IN_D2P ISET 36 PD_N 1
(G_) C12393 TP4135
2

1117_ADJ [56,77] HDMI_DATA_GPU_N0 IN_D2N PD#

Change symbol TPAD30 TR37 (G_068.10129.2011)
[56,77] HDMI_DATA_GPU_N1 (G_) C12394 1 2SCD1U16V2KX-3DLGP HDMI1_DATA_IC_P3 9 13 DCIN_EN
[56,77] HDMI_DATA_GPU_P3
1

C12395 1 2SCD1U16V2KX-3DLGP HDMI1_DATA_IC_N3 10 IN_CKP DCIN_EN/SCL_CTL 14

HDMI CLK [56,77] HDMI_DATA_GPU_N3
(G_)
IN_CKN DDCBUF/SDA_CTL
DDCBUF
HDMI_LANE3_IC_DP
FILTER-4P-120-GP
HDMI_LANE3_DP
[56,77] HDMI_DATA_GPU_P1 R80223 1 2
36R3F-GP HDMI_GPU_CTRL_CLK 38 32 DDPC_CTRL_CLK_CONN
R1 (G_) [56,77] HDMI_GPU_CTRL_CLK HDMI_GPU_CTRL_DATA 39 SCL_SRC SCL_SNK 33 DDPC_CTRL_DATA_CONN HDMI_LANE3_IC_DN 4 3 HDMI_LANE3_DN
[56,77] HDMI_GPU_CTRL_DATA SDA_SRC SDA_SNK
Vout = 1.25*(1+R1/R2)
2

Note: GPU_HDMI2_HPD 3 TR38 (G_068.10129.2011)

DDSP_C_HPD_CONN 28 HPD_SRC 15
[56,77] HDMI_DATA_GPU_N2 There is internal pull-up in HPD_SNK GND
PS8407A/PS8201A (DDCBUF = H) 35
REXT 18 GND 41
[56,77] HDMI_DATA_GPU_P2 REXT GND
10/28 modify R80224
1

VCC3 CFG R80224 PS8407ATQFN40GTR2-A1-GP

mount if use L: HDMI ID disable 4D3KR2F-GP
[56,77] HDMI_DATA_GPU_N3 R80225 1 (G_) 2 4K7R2F-GP CFG H: HDMI ID enable(default) (G_) Note:
HPD_SRC: 3.3V CMOS output
2

R80226 1 (R_) 2 4K7R2F-GP DCIN_EN DCIN_EN HPD_SNK: Internal pull-down 150Kohm,

[56,77] HDMI_DATA_GPU_P3
L: AC coupling input(default) 5V tolerant CMOS input SB025
H: DC coupling input
VCC3
[56,77] HDMI_GPU_CTRL_CLK
R80227 1 (R_) 2 4K7R2F-GP EQ EQ Add by 12/14
[56,77] HDMI_GPU_CTRL_DATA
L: 12.4dB(default)
R80228 2 (R_) 1 4K7R2F-GP H: 4.3dB R80238 1 (G_) 2 0R2J-2-GP
M: 8.6dB
VCC3
R80229 1 (R_) 2 4K7R2F-GP ISET ISET VCC3
L: 1000mV(default)
HDMI FROM GPU

2
R80230 2 (R_) 1 4K7R2F-GP H: Increase +13% V_1P5_HDMI V_1P5_HDMI V_1P5_HDMI V_1P5_HDMI
M: Reduce -13% R80231
mount if use 10KR2J-3-GP
VCC3 (R_)
R80232 1 (G_) 2 4K7R2F-GP DDCBUF DDCBUF

1
L: Passive DDC pass-through R80233 1 (R_) 2 0R2J-2-GP GPU_HDMI_DET_CN
GPU_HDMI_DET_CN [77]
1

1
R80234 2 (R_) 1 4K7R2F-GP H: Active DDC buffer with default threshold(default)
M: Active DDC buffer without internal pull up resister C12396 C12397 C12398 C12399 C12400 C12401 C12402 C12403
SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP

D
2

2
VCC3 (G_) (G_) (G_) (G_) (G_) (G_) (G_) (G_)
R80235 1 (R_) 2 4K7R2F-GP PRE PRE Q9641
L: no pre-emphasis 2N7002A-7-GP
R80236 2 (R_) 1 4K7R2F-GP H: 1.6dB pre-emphasis GPU_HDMI2_HPD G (R_84.2N702.J31)
M: 2.5dB pre-emphasis(default)

1
Near Pin 19 Near Pin 20, 31 Near Pin 12, 40 Near Pin 11, 37 HPD R80237

S
Note: H: Detect 100KR2J-1-GP
A DCIN_EN/EQ/ISET/DDCBUF/PRE pins are (G_) A
internal pull-down 150Kohm, 3.3V I/O
L: No detect

2
<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
HDMI CONN
Size Document Number Rev
D Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 56 of 105
5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 57 of 105

5 4 3 2 1
Blanking

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 58 of 105

 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 59 of 105

5 4 3 2 1
 5 4 3 2 1

D D

SATA
White
SATA_ODD HDD2
SATA 9
Layout: Please put them together 7
SATAHDR_TX_DP1 C114 1 2SCD01U25V2KX-3DLGP SATA__TXP1_C 6
Pin1(VCC12) SATAHDR_TX_DN1 C115 1 2SCD01U25V2KX-3DLGP SATA__TXN1_C 5
[19] SATAHDR_RX_DP0
[19] SATAHDR_RX_DN0 4
SATAHDR_RX_DN1 C118 1 2SCD01U25V2KX-3DLGP SATA__RXN1_C 3
[19] SATAHDR_TX_DN0
SATAHDR_RX_DP1 C119 1 2SCD01U25V2KX-3DLGP SATA__RXP1_C 2 For ODD
[19] SATAHDR_TX_DP0
1
[19] SATAHDR_RX_DP1 8
[19] SATAHDR_RX_DN1 VCC VCC
SATAP1 SKT-SATA7P-29-GP-U
NP1
[19] SATAHDR_TX_DN1
4 1 VCC12
[19] SATAHDR_TX_DP1

1
5 2 VCC
C 6 3 C112 C110 C109 C
VCC3 Blue

SC10U6D3V3MX-DL-GP
SC10U10V5KX-2DLGP

SC1U25V3KX-1-DLGP
NP2
SATA_HDD

2
SD004
BAOT-CONN6F-S-GP SD009 SD010 HDD1
20.82108.006
Change pin define same as Tigris SFF Remove TC5 SATAHDR_TX_DP0 C141 1 2SCD01U25V2KX-3DLGP SATA__TXP0_C 2 8
SATAHDR_TX_DN0 C142 1 2SCD01U25V2KX-3DLGP SATA__TXN0_C 3 TXP 8 9
TXN 9

SATAHDR_RX_DP0 SATA__RXP0_C
For HDD
C151 1 2SCD01U25V2KX-3DLGP 6 1
SATAHDR_RX_DN0 C149 1 2SCD01U25V2KX-3DLGP SATA__RXN0_C 5 RXP GND 4
RXN GND 7
GND

SKT-SATA7P-168-GP

B B

A A

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
HDD/ODD
Size Document Number Rev
Custom Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 60 of 105
5 4 3 2 1
 5 4 3 2 1

NGFF(A Key)
NGFF1
H:4.2mm
NP2 NP1
V_3P3_PCIVAUX NP2 NP1
76 77
74 76 77 75
72 3_3V GND 73 NGFF_REFCLKN1 1 TP84 TPAD30
WAKE_N R1627 1 0R0402-PAD-2-GP
2 NGFF_PEWAKE0_N 70 3_3V REFCLKN1 71 NGFF_REFCLKP1 1 TP83 TPAD30
TPAD30 TP85 1NGFF_CLKREQ1_N 68 PEWAKE1#_0/3_3V REFCLKP1 69
PCIE_RST# 66 CLKREQ1#_0/3_3V GND 67 NGFF_PCIE1_RXN 1 TP82 TPAD30
64 PERST1#_0/3_3V PETN1 65 NGFF_PCIE1_RXP 1 TP81 TPAD30
[24] NGFF_BT_DISABLE SMB0_ALERT# R1623 1 (R_) NGFF_ALERT_N RESERVED#64 PETP1
2 0R2J-2-GP 62 63
D SMB0_CLK_RESUME R14 1 (R_) 2 0R2J-2-GP M1_SMB_CLK 60 ALERT_0/3_3 GND 61 NGFF_PCIE1_TXN 1 TP80 TPAD30 D
SMB0_DATA_RESUME R1622 1 (R_) 2 0R2J-2-GP M1_SMB_DATA 58 I2C_CLK_0/3_3 PERN1 59 NGFF_PCIE1_TXP 1 TP79 TPAD30
MPCIE_DISABLE_N R1620 1 (R_) 2 0R2J-2-GP NGFF_W_DISABLE1_N 56 I2C_DATA_0/3_3 PERP1 57
NGFF_BT_DISABLE R1621 1 (R_) 2 0R2J-2-GP NGFF_W_DISABLE2_N 54 W_DISABLE#1_0/3_3V GND 55 NGFF_PEWAKE0_N R1628 1 0R0402-PAD-2-GP
2 WAKE_N
PCIE_RST# 52 RESERVED/W_DISABLE#2_0/3_3V PEWAKE0#_0/3_3V 53 NGFF_CLKREQ0_N R1612 1 0R0402-PAD-2-GP
2 PCH_PCIECLKRQ2_N_1 R1155
TPAD30 TP101 1 SUSCLK_NGFF 50 PERST0#_0/3_3V CLKREQ0#_0/3_3V 51 NGFF_DETECT_PCIE_C 1 2 NGFF_DETECT_PCIE
TPAD30 TP39 1 TP_NGFF_COEX1 48 SUSCLK/32KHZ_0/3_3V GND 49 NGFF_REFCLKN0 R23 1 0R0402-PAD-2-GP
2 CK_PCIEX1_WLAN_DN
Wireless Card TPAD30 TP38 1 TP_NGFF_COEX2 46 COEX1_0/1_8V
COEX2_0/1_8V
REFCLKN0
REFCLKP0
47 NGFF_REFCLKP0 R22 1 0R0402-PAD-2-GP
2 CK_PCIEX1_WLAN_DP 0R2J-2-GP
TPAD30 TP37 1 TP_NGFF_COEX3 44 45
TPAD30 TP67 1CLINK_CLK_LAN 42 COEX3_0/1_8V GND 43 NGFF_PCIE0_RXN R1609 1 0R0402-PAD-2-GP
2 HSI_C_DN2
[19] CK_PCIEX1_WLAN_DN CLINK_CLK PETN0
TPAD30 TP66 1CLINK_DATA_LAN 40 41 NGFF_PCIE0_RXP R1608 1 0R0402-PAD-2-GP
2 HSI_C_DP2
[19] CK_PCIEX1_WLAN_DP

2
1CLINK_RST_LAN_N 38 CLINK_DATA PETP0 39
6/10 TPAD30 TP65
CLINK_RESET GND NGFF_PCIE0_TXN HSO_C_DN2
36 37 R1611 1 0R0402-PAD-2-GP
2 R1209
Need to check DP of NGFF function. TPAD30 TP68 1 DP_ML0P 34 GND PERN0 35 NGFF_PCIE0_TXP R1610 1 0R0402-PAD-2-GP
2 HSO_C_DP2 0R2J-2-GP
[37] F_USB1P_H DP_ML0P PERP0
[37] F_USB1N_H TPAD30 TP69 1 DP_ML0N 32 33 (R_)
30 DP_ML0N GND 31 DP_HPD 1 TP78 TPAD30

1
TPAD30 TP70 1 DP_ML1P 28 GND DP_HPD_0/3_3V 29
[19] HSO_C_DN2 DP_ML1P GND
TPAD30 TP71 1 DP_ML1N 26 27 DP_ML2P 1 TP77 TPAD30 SC018
[19] HSO_C_DP2 From PCH...TX 24 DP_ML1N DP_ML2P 25 DP_ML2N 1 TP76 TPAD30 Change R1155 to stuff
TPAD30 TP72 1 DP_AUXP 22 GND DP_ML2N 23 Change R1209 to NC
[19] HSI_C_DN2 DP_AUXP GND
TPAD30 TP73 1 DP_AUXN 20 21 DP_ML3P 1 TP75 TPAD30
[19] HSI_C_DP2 From PCH...RX 18 DP_AUXN DP_ML3P 19 DP_ML3N 1 TP74 TPAD30
TPAD30 TP64 1 TP_NGFF_LED2 16 GND DP_ML3N 17 TP_NGFF_MLDIR 1 TP62 TPAD30 ??? Hi-Z Joey_SA_0412
LED#2 DP_MLDIR

TPAD30 TP63 1 TP_NGFF_LED1 6 7

4 LED#1 GND 5 USB_PCH_DN5_NN
2 3_3V USB_D- 3 USB_PCH_DP5_PP
[31,92] WAKE_N V_3P3_PCIVAUX 3_3V USB_D+ NGFF_DETECT_USB_C NGFF_DETECT_USB
1 1 2
NGFF_KEY_A 75P GND R1154 0R2J-2-GP
[17,77] SMB0_CLK_RESUME
SKT-MINI67P-3-GP-U1
[17,77] SMB0_DATA_RESUME
[17] SMB0_ALERT# (62.10043.N61)

2
R1637
0R2J-2-GP
COU_GPIO (R_)

1
[24] PCIE_RST#
SC019
Change R1154 to stuff
[24] MPCIE_DISABLE_N Change R1637 to NC
C [24] MINI_POWER_CTRL C

TR12
F_USB1N_H 4 3 USB_PCH_DN5_NN

F_USB1P_H 1 2 USB_PCH_DP5_PP
[19] PCH_PCIECLKRQ2_N
FILTER-4P-137-GP
(068.01012.2011)
[8] NGFF_DETECT_USB

[8] NGFF_DETECT_PCIE

V_3P3_PCIVAUX DUAL P-MOS

R1634 1 (R_) 2 0R5J-5-GP

Q1209
V_3P3_PCIVAUX AO3413L-GP
SB3V (84.02130.031) V_3P3_PCIVAUX

1
S D
R1633

1
1
1
10KR2J-3-GP C1617 C1615 C364 C391 C1608 C1609

1
2
1

2
TC1

SCD1U16V2KX-3DLGP

SC10U6D3V3MX-DL-GP

SC10U6D3V3MX-DL-GP
SC2D2U10V3KX-1DLGP-U
PC1

SCD1U16V2KX-3DLGP
SC2D2U10V3KX-1DLGP-U

G
ST330U2D5VDM-9GP

2
2

2
2
(R_)

2
1
2

1
SC1U10V2KX-1DLGP
B B
Discharge resistor

VREG_PCIAUX_PCH_1
SB3V

1
R10
8K2R2J-3-GP

R13

2
VREG_PCIAUX_PCH 1 2

1
39K2R2F-L-GP
C1616

D
1A001 SC1U10V2KX-1GP

2
(R_)
R15 Q3
MINI_POWER_CTRL 1 2 NGFF_POWER_CTRL_1 G 2N7002A-7-GP
0R0402-PAD-2-GP (84.2N702.J31)
SC071 0805 Jeffrey modify location

S
S0 S3 S5 DS 1B007
H H L L
VCC3
MINI CARD STAND OFF
Need to check leakage issue
HS1
0826 Jeffrey remove SPR1

2
1D8V_S5 V_3P3_PCIVAUX V_3P3_PCIVAUX STF256R109H99-GP
R1615
10KR2J-3-GP

C
2

1 NGFF_POWER_CTRL_V2
R1843 R1844 R1842 B Q6708 (334.03802.0001)

1
10KR2J-3-GP 2K2R2J-2-GP 10KR2J-3-GP LMBT3904LT1G-GP
1

(R_) (R_)

E
C864
1

A SC1U10V2KX-1GP A
2

PCH_PCIECLKRQ2_N_B (R_)
1

PCH_PCIECLKRQ2_N 3 2 PCH_PCIECLKRQ2_N_1 New P/N:334.03802.0001 replace Old P/N:34.3NH01.001

Q1236
PMBS3904-1-GP
<Variant Name>
(R_)
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
NGFF CONN
Size Document Number Rev
Custom Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 61 of 105
5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 62 of 105

5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 63 of 105

5 4 3 2 1
 5 4 3 2 1

V_3P3_A 1D8V_S5 Change pull-up from VCC3 to 1D8V_S5

CHASSIS ID SD005
POWER BUTTON

1
Change PWRSW1 SC023

1
Swap pin 1 & 3 TYPE ID_0
PWRSW1 R128 R636 R637
R999 1 2 1KR2J-1-GP HD_LED_PWR1 2 1 PWR_LED_G 3KR2J-2-GP Inspiron 1 10KR2J-3-GP 10KR2J-3-GP
VCC
D D

2
4 3 PWR_LED_Y
Vostro 0 SD006

2
FP_CBL_DET 6 5 PWR_BTNJ_C 1 2 PWRBTN_N CHASSIS_ID_1
[17] FP_CBL_DET CHASSIS_ID_0 PWRBTN_N [18,24,64] CHASSIS_ID_0 CHASSIS_ID_1 [19]
8 7 R641 33R2J-2-GP
X CHASSIS_ID_0 [19]

1
C496

1
JWT-CONN8D-SFP3-GP-U SC1U10V2KX-1DLGP
R638 R639

2
10KR2J-3-GP 10KR2J-3-GP
(R_) (R_)

2
SB027
V_5P0_A

V_3P3_A

1
V_3P3_A
R6404
Power Botton/Reset PWR_LED_G 220R5J-GP

1
R670
[18,24,64] PWRBTN_N

2
PWR_LED_G 10KR2J-3-GP R6402
6 4K7R2J-2-GP

TO SIO White LED Amber LED

2
1
C811 2 PWR_LEDJ2

2
SCD1U16V2KX-3DLGP 3
(R_) Q9627A

2
1 MMBT3904DW-1-GP 5 PWR_LEDJ3 R672 1 2 10KR2J-3-GP SIO_PWRLED_N
SIO_PWRLED_N [24]
Q9627B GP40
HD_LED PWR_LEDJ1
4 MMBT3904DW-1-GP S0: Low
S3: Blinking
[19,64] CPU_SATA_LED_N S4/S5: High

1
PWR_LED_Y
R80262 R80263
C 0R2J-2-GP 0R2J-2-GP C
(R_)
V_3P3_A

2
Dual color, white/amber SC024
Off: system off

1
Blinking Amber: system fault during POST, power is bad R506
Solid Amber: system fault during POST, power ok 4K7R2J-2-GP
Blinking White: S3 (sleep) state, slow on/off (TBD)
Solid White: S0 (on) state

2
SUS_LED4 R6401 1 2 1KR2J-1-GP SIO_SUSLED_N
SIO_SUSLED_N [24]
SUS_LED6
SB027 GP45
S0: Low
V_5P0_A S3: Low
S4/S5: Low

3
Q9628 boot failure(no code fetch): blink (1Hz)

1
2N7002KDW-1-GP
-1008 R503 SB018
130R5J-GP

4
change from 220 to 130ohm Change Q9628 from 2N3904 to 2N7002

2
PWR_LED_Y

SUS_LED5 R504 1 2 1KR2J-1-GP SLP_S4_N

SLP_S4_N [24,32,34,35,39,48,92,99]

1
C812
SCD1U16V2KX-3DLGP
2 (R_)

VCC
SC021
B B
1

R968
360R3-GP
2

VCC
VCC12
HDD_LED_PWR1
A

VCC LED1
White LED

D
2
1D8V_S0
LED-W-45-GP SB012
R1012 Q44
1

10KR2J-3-GP 2N7002K-2-GP
R80170 V_3P3_A
K
2

10KR2J-3-GP

1
R80164 SATA_LED_OUT

2
10KR2J-3-GP 3
2

Q9638B R80217

S
LED1_SATA_BJT1 5 MMBT3904DW-1-GP 10KR2J-3-GP
1

5V_LED_G
6
R80169 Q9638A

1
2 1 LED1_SATA_BJT2 2 MMBT3904DW-1-GP 4
[19,64] CPU_SATA_LED_N SC022

5V_S0_LED
Q86
10KR2J-3-GP R1011 1 2 10KR2J-3-GP 5V_LED_B B MMBT3904-4-GP
1 [24] 5V_LED
SC043 (84.T3904.H11)
Change Q9628 from MMBT3904 to MMBT3904DW -1011

E
GP41
R80144 CN4 Change CN4 P/N from
S0: Low (LED-on) 1 2 5V_S0_LED_CN 1 021.60055.0103 to
S5: High (LED-off) NP1 21.61830.103
Low (LED-ON), High (LED-off), 0R5J-5-GP 2
Dell will have AP in OS, user can control LED ON/OFF. 3 2nd source:
1A019 020.60048.0103
1B004 FOX-CON3-S15-GP
21.61830.103

F_LED_DET_N
F_LED_DET_N [8]

A
SC020 A

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
LED/POWER BUTTON
Size Document Number Rev
Custom Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 64 of 105
5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 65 of 105

5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 66 of 105

5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 67 of 105

5 4 3 2 1
 5 4 3 2 1

SSID = DEBUG PORT

D D

VCC3
LPC DEBUG PORT Layout Close SIO

1
R324
4K7R2J-2-GP

LPC1

2
LPC_CLK1 1 2 INIT_3V

C PLTRST_N 3 4 C
LAD0_FWH0 FWH_ID0 VCC3
5 6
LPC DEBUG PORT LAD1_FWH1 7 8 VCC
LAD2_FWH2 9 10
LAD3_FWH3 11 12
[18,24] LAD0_FWH0

2
[18,24] LAD1_FWH1 NP1 (R_)
LFRAMEJ_FW4 13 14 R317
[18,24] LAD2_FWH2
[18,24] LAD3_FWH3 10KR2J-3-GP
FOX-CONN14A-S1-GP
[18,24] LFRAMEJ_FW4
[18,24] PLTRST_N (D_)

1
[18] LPC_CLK1
Pin height 2.3mm

B
Follow Eagle B

0502 Eric modified from Dallas/kelia

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title
DEBUG CONNECTOR
Size Document Number Rev
A Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 68 of 105
5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 69 of 105

5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 70 of 105

5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 71 of 105

5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A Hsichih, Taipei A
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 72 of 105

 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 73 of 105

5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 74 of 105

5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 75 of 105

5 4 3 2 1
 5 4 3 2 1

PCIEX2 GPU1A 1 OF 7

[19] PEG_TXP[0..1]
[19] PEG_TXN[0..1]

[19] PEG_RXP[0..1] PEG_TXP0 AF30 AH30 PEG_C_RXP0 C1838 (G_)1 2 SCD1U16V2KX-3DLGP PEG_RXP0
[19] PEG_RXN[0..1] [19] PEG_TXP0 PEG_TXN0 PCIE_RX0P PCIE_TX0P PEG_C_RXN0 PEG_RXN0 PEG_RXP0 [19]
AE31 AG31 C1840 (G_)1 2 SCD1U16V2KX-3DLGP
[19] PEG_TXN0 PCIE_RX0N PCIE_TX0N PEG_RXN0 [19]
D D
[19,76] CK_PE_100M_16PORT_DP PEG_TXP1 AE29 AG29 PEG_C_RXP1 2 PEG_RXP1
[19] PEG_TXP1 C1839 (G_)1 SCD1U16V2KX-3DLGP
[19,76] CK_PE_100M_16PORT_DN PEG_TXN1 AD28 PCIE_RX1P PCIE_TX1P AF28 PEG_C_RXN1 2 PEG_RXN1 PEG_RXP1 [19]
[19] PEG_TXN1 C1842 (G_)1 SCD1U16V2KX-3DLGP
PCIE_RX1N PCIE_TX1N PEG_RXN1 [19]
[24,76,79] PLTRST_SL_N
AD30 AF27
AC31 PCIE_RX2P PCIE_TX2P AF26
PCIE_RX2N PCIE_TX2N

AC29 AD27
AB28 PCIE_RX3P PCIE_TX3P AD26
PCIE_RX3N PCIE_TX3N

AB30 AC25
AA31 PCIE_RX4P PCIE_TX4P AB25
PCIE_RX4N PCIE_TX4N

AA29 Y23
Y28 PCIE_RX5P PCIE_TX5P Y24
PCIE_RX5N PCIE_TX5N

Y30 AB27
W31 PCIE_RX6P PCIE_TX6P AB26
PCIE_RX6N PCIE_TX6N

W29 Y27
V28 PCIE_RX7P PCIE_TX7P Y26
PCIE_RX7N PCIE_TX7N

C V30 W24 C
U31 NC#V30 NC#W24 W23
NC#U31 NC#W23

U29 V27
T28 NC#U29 NC#V27 U26
NC#T28 NC#U26

PCI EXPRESS INTERFACE

T30 U24
R31 NC#T30 NC#U24 U23
NC#R31 NC#U23

R29 T26
P28 NC#R29 NC#T26 T27
NC#P28 NC#T27

P30 T24
N31 NC#P30 NC#T24 T23
NC#N31 NC#T23

N29 P27
M28 NC#N29 NC#P27 P26
NC#M28 NC#P26

M30 P24
L31 NC#M30 NC#P24 P23
NC#L31 NC#P23

L29 M27
K30 NC#L29 NC#M27 N26
B NC#K30 NC#N26 B
3D3V_VGA_S0
100MHz
CLOCK R1161
AK30
[19,76] CK_PE_100M_16PORT_DP PCIE_REFCLKP
2

AK32 1 2
[19,76] CK_PE_100M_16PORT_DN PCIE_REFCLKN 0D95V_VGA_S0
R1159
10KR2J-L-GP 1K69R2F-2-GP
(R_) CALIBRATION (G_)
Y22 PCIE_CALR_TX
1

PLTRST_SL_N PCIE_CALR_TX
[24,76,79] PLTRST_SL_N PWRGOOD_GPU PCIE_CALR_RX
R1158 1 (G_) 2 N10 AA22
1KR2F-3-GP TEST_PG PCIE_CALR_RX
-1011
Change symbol 2 1 AMD_RST# AL27
PERST# R1162
D34 R1160
1 0R0402-PAD 1 2
0D95V_VGA_S0
SUN-S3-XT-GP
3 (R_) (G_071.0MARS.M001) 1KR2F-3-GP
1

C12337 (G_)
2 SC47P50V2JN-3GP
[24] SIO_GPU_RST change to MESO-LE P/N:071.MESOS.M004
2

BAT54A-7-F-2-GP
(R_75.00054.R7D)

Runtime D3 function
A A

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
GPU_MARS_PCIE
Size Document Number Rev
Custom Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 76 of 105
5 4 3 2 1
 5 4 3 2 1

1B001
3D3V_VGA_S0
V_3P3_A V_3P3_A

1
1
11/13 RN16 Modify to 2.2K (G_) R80270

1
C12415 18K7R2F-GP For SOC SMBus
R80190 R80191 SCD1U16V2KX-3DLGP U9630 (G_) GPU1B 2 OF 7

2
2K2R2J-2-GP 2K2R2J-2-GP

2
(G_) (G_) 1 8 SMB0_CLK_RESUME
GPU_DPLUS 2 VCC SMBCLK 7 SMB0_DATA_RESUME

2
3 DXP SMBDATA 6 TS_ALERT# AF2
[17,61] SMB0_DATA_RESUME R1166 DXN ALERT# NC#AF2

1
(G_) Q123 (G_) 4 5 AF4
[17,61] SMB0_CLK_RESUME SMB0_CLK_MAIN 6 1 GPIO_VGA_04_CLK 1 2 GPIO_VGA_04_CLK_R THERM# GND NC#AF4
C12414
0R0402-PAD-2-GP SC2200P50V2KX-2DLGP N9 AG3

2
5 2 GPU_DMINUS G781P8F-GP L9 DBG_DATA16 NC#AG3 AG5
74.00781.AB9 AE9 DBG_DATA15 NC#AG5
DPA
4 3 (G_) Y11 DBG_DATA14 AH3
AE8 DBG_DATA13 NC#AH3 AH1
2N7002KDW-1-GP AD9 DBG_DATA12 NC#AH1
[12,17,37,55] SMB0_DATA_MAIN SMB0_DATA_MAIN SMBus slave address AC10 DBG_DATA11 AK3
[12,17,37,55] SMB0_CLK_MAIN R1165 DBG_DATA10 NC#AK3
Read: 10011001b AD7
DBG_DATA9 NC#AK1
AK1
D GPIO_VGA_03_DATA 1 2 GPIO_VGA_03_DATA_R AC8 D
0R0402-PAD-2-GP
Write:10011000b AC7 DBG_DATA8 DVO AK5
AB9 DBG_DATA7 NC#AK5 AM3
AB8 DBG_DATA6 NC#AM3
GPU_OVT_N 1 (G_) 2 AB7 DBG_DATA5 AK6
SIO_EUP_EN# [24,47,49,92] DBG_DATA4 NC#AK6
R80273 AB4 AM5
0R2J-2-GP AB2 DBG_DATA3 NC#AM5
DPB
Y8 DBG_DATA2 AJ7
Y7 DBG_DATA1 NC#AJ7 AH6
Layout Note: place 2200PF near Temp. Sensor Pin2,3 DBG_DATA0 NC#AH6
GPIO19_CTF Reserve EEPROM for VBIOS AK8
[77,79] GPIO19_CTF NC#AK8 AL7
NC#AL7

W6
V6 NC#W6
3D3V_VGA_S0 NC#V6 V4
AC6 NC#V4 U5
2009/11/21 AC5 NC#AC6 NC#U5
PS_0 NC#AC5

1
[79] PS_0 PS_1 (R_) W3
[79] PS_1 R1167 3D3V_VGA_S0 AA5 NC#W3 V2
PS_2 NC#AA5 NC#V2
[79] PS_2 PS_3 10KR2J-3-GP NC FOR MARS AA6 DPC
[79] PS_3 NC#AA6 Y4
NC#Y4 W5

2
NC#W5
U49 (R_) U1 AA3
GPU_THERMAL_INT W1 NC#U1 NC#AA3 Y2
[77] GPU_THERMAL_INT GPIO_22_ROMCS# 1 ROM_CS# NC#W1 NC#Y2
2 1 8 U3
(R_) R1168 ROM_SO_C4 2 CE# VCC 7 Y6 NC#U3 J8
33R2J-2-GP 3 SO HOLD# 6 ROM_SLK_D4 1 2GPIO_10_ROMSCK AA1 NC#Y6 NC#J8
4 WP# SCK 5 ROM_SI_D3 (R_) R1170 NC#AA1
GND SIO 33R2J-2-GP
GPIO_8_ROMSO 1 2

1
(R_) R1169 PM25LD010C-SCE-1-GP (R_) 1 2 GPIO_9_ROMSI
33R2J-2-GP C12340 (R_) R1171 I2C
SCD1U10V2KX-5GP 33R2J-2-GP

2
1 GPU_SCL R1
TPAD30 TP149 GPU_SDA SCL
1 R3
TPAD30 TP150 SDA
AM26
NC_R AK26
U6 NC_AVSSN#AK26
GENERAL PURPOSE I/O
U10 GPIO_0 AL25
T10 NC_GPIO_1 NC_G AJ25
3D3V_VGA_S0 GPIO_VGA_03_DATA_R U8 NC_GPIO_2 NC_AVSSN#AJ25
GPIO_VGA_04_CLK_R U7 SMBDATA AH24
H_VID5 T9 SMBCLK NC_B AG25 4K7R2J-2-GP 2 (G_) 1 R80252
[85] H_VID5 H_VID0 GPIO_5_AC_BATT NC_AVSSN#AG25 3D3V_VGA_S0
T8 4K7R2J-2-GP 2 (R_) 1 R80253
[85] H_VID0

1
T7 GPIO_6 DAC1 AH26 GPU_HSYNC

1
(G_) (R_) GPIO_8_ROMSO P10 NC_GPIO_7 NC_HSYNC AJ27 GPU_WAKEB 4K7R2J-2-GP 2 (G_) 1 R1883
C GPIO_9_ROMSI GPIO_8_ROMSO NC_VSYNC 3D3V_VGA_S0
R1885 R1887 P4 4K7R2J-2-GP 2 (R_) 1 R80254 C
10KR2J-3-GP 10KR2J-3-GP GPIO_10_ROMSCK P2 GPIO_9_ROMSI
N6 GPIO_10_ROMSCK AD22 GPU_RSET R80256 2 (G_) 1 499R2F-2-GP

2
N5 NC_GPIO_11 NC_RSET

2
GPIO17_THERMAL_INT
GPIO17_THERMAL_INT [79]
DP HPD,3.3V High Active N3
Y9
NC_GPIO_12
NC_GPIO_13 NC_AVDD
AG24
AE22
1D8V_VGA_AVDD
1D8V_VGA_AVDD 1D8V_VGA_S0
R80257
[55] GPU_DP_DET_CN H_VID1 N1 NC_GPIO_14 NC_AVSSQ 1 2
GPU_THERMAL_INT [85] H_VID1 GPU_GPIO16 GPIO_15_PWRCNTL_0
TPAD30 TP155 1 M4 AE23 0R0603-PAD-2-GP-U
GPU_THERMAL_INT [77] GPU_THERMAL_INT R1884 1 GPIO17_THERMAL_INT GPIO_16 NC_VDD1DI 1D8V_VGA_VDD1DI
(R_) 2 33R2J-2-GP R6 AD23
GPIO_17_THERMAL_INT NC_VSS1DI

2
W10 C12407 C12408
GPIO19_CTF GPIO19_CTF M2 NC_GPIO_18
[77,79] GPIO19_CTF H_VID2 GPIO_19_CTF FutureASIC/SEYMOUR/PARK SC026 SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP
Note: P8 AM12 (G_) (G_)
[85] H_VID2

1
GPIO_20_PWRCNTL_1 CEC_1

1
GPIO_19_CTF is 3.3V output, High active P7
(G_) GPIO_22_ROMCS# N8 GPIO_21
R1886 H_VID3 AK10 GPIO_22_ROMCS# AK12 GPIO_SVD 1
[85] H_VID3 H_VID4 GPIO_29 NC_SVI2#AK12 GPIO_SVT TP163 TPAD30
10KR2J-3-GP AM10 AL11 1
[85] H_VID4 TP_GPU_CLKREQ# GPIO_30 NC_SVI2#AL11 GPIO_SVC TP164 TPAD30
1 N7 AJ11 1
TP165 TPAD30

2
TPAD30 TP158 CLKREQ# NC_SVI2#AJ11
L6 1D8V_VGA_VDD1DI
6 OF 7 [79] JTAG_TRST#_VGA L5 JTAG_TRST#
GPU1F
[79] JTAG_TDI_VGA JTAG_TDI
L3 R80258
[79] JTAG_TCK_VGA L1 JTAG_TCK AL13 1 2
SB 20141028 [79] JTAG_TMS_VGA
K4 JTAG_TMS NC_GENLK_CLK AJ13 0R0603-PAD-2-GP-U
[79] JTAG_TDO_VGA JTAG_TDO NC_GENLK_VSYNC
NC_VARY_BL
AB11 Base on CRD to SWAP [79] TESTEN
K7
TESTEN

2
AB12 AF24 C12409 C12410
NC_DIGON From Port A/B to E/F NC#AF24 AG13 SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP
NC_SWAPLOCKA AH12 (G_) (G_)

1
AB13 NC_SWAPLOCKB
W8 NC_GENERICA
AL15 W9 NC_GENERICB
NC_UPHYAB_TMDPA_TX0N AK14 HDMI_DATA_GPU_P3 [56] W7 NC_GENERICC AC19 PS_0
NC_UPHYAB_TMDPA_TX0P HDMI_DATA_GPU_N3 [56] HDMI CLK Clock Input Configuraiton -GDDR3/DDR3 NC_GENERICD PS_0
AD10 SC027
AH16
a) 27MHz crystal connected to XTALIN or XTALOUT or 1D8V_VGA_S0 AJ9 NC_GENERICE_HPD4 AD19 PS_1
NC_UPHYAB_TMDPA_TX1N AJ15 HDMI_DATA_GPU_P2 [56] b) 27MHz (1.8V) oscillator connected to XTALIN or AL9 NC#AJ9 PS_1
NC_UPHYAB_TMDPA_TX1P HDMI HPD,3.3V High Active
HDMI_DATA_GPU_N2 [56]

HDMI c) 27MHz (3.3V) oscillator connected to XO_IN (Park, Madison, and Broadway only) DBG_CNTL0
PS_2
AE17 PS_2

2
AL17 AC14
NC_UPHYAB_TMDPA_TX2N AK16 HDMI_DATA_GPU_P1 [56] [56] GPU_HDMI_DET_CN 1 PX_EN AB16 NC_HPD1 AE20 PS_3
R1211
NC_UPHYAB_TMDPA_TX2P HDMI_DATA_GPU_N1 [56] 499R2F-2-GP TPAD30 TP159 PX_EN PS_3
AH18 (R_)
NC_UPHYAB_TMDPA_TX3N AJ17 HDMI_DATA_GPU_P0 [56] AE19

1
NC_UPHYAB_TMDPA_TX3P HDMI_DATA_GPU_N0 [56] GPU_VREFG AC16 TS_A
AL19 NC_DBG_VREFG
NC_TXOUT_L3P

2
AK18 (R_)
NC_TXOUT_L3N

1
R1210 C1846 1A001
249R2F-GP SCD1U10V2KX-5GP DDC/AUX
TMDP (R_) AE6 DDC1L_GPU_CLK 1 R80239 2 0R0402-PAD-2-GP

2
PLL/CLOCK NC_DDC1CLK AE5 DDC1L_GPU_DATA 1 R80240 2 0R0402-PAD-2-GP HDMI_GPU_CTRL_CLK [56]
HDMI_GPU_CTRL_DATA [56]

1
AH20 NC_DDC1DATA
NC_UPHYAB_TMDPB_TX0N AJ19 AD2
NC_UPHYAB_TMDPB_TX0P NC_AUX1P AD4
B AL21 NC_AUX1N B
NC_UPHYAB_TMDPB_TX1N AK20 AC11
NC_UPHYAB_TMDPB_TX1P NC_DDC2CLK AC13
X'tal NC_DDC2DATA
AH22 R1879 1 (G_) 2 1MR3F-GP
NC_UPHYAB_TMDPB_TX2N AJ21 DP_GPU_TXP1 [55] XTALIN AM28 AD13
NC_UPHYAB_TMDPB_TX2P DP_GPU_TXN1 [55] DP_GPU_AUXP [55]

NC_UPHYAB_TMDPB_TX3N
NC_UPHYAB_TMDPB_TX3P

NC_TXOUT_U3P
NC_TXOUT_U3N
AL23
AK22

AK24
AJ23
DP_GPU_TXP0
DP_GPU_TXN0
[55]
[55] DP C12338
2 1

(G_)
XTALIN 1
X8 (G_)

4
R1880
R1881
2
2
(G_)
(G_)
1 10KR2J-3-GP
1 10KR2J-3-GP
XTALOUT

GPU_XO_IN
GPU_XO_IN2
AK28

AC22
AB22
XTALIN
XTALOUT

XO_IN
XO_IN2
NC_AUX2P
NC_AUX2N

NC#AD20
NC#AC20

NC#AE16
AD11

AD20
AC20

AE16
DP_GPU_AUXN [55]

SC12P50V2JN-DL-GP AD16
2 3 XTALOUT 1 2 C12339 NC#AD16
SC12P50V2JN-DL-GP SEYMOUR/FutureASIC AC1
(G_) GPU_DPLUS T4 NC_DDCVGACLK AC3
XTAL-27MHZ-85-GP-U GPU_DMINUS T2 DPLUS THERMAL NC_DDCVGADATA
SUN-S3-XT-GP DMINUS
(G_071.0MARS.M001) MLPS_EN#
R1882 2 (G_) 1 10KR2J-3-GP R5
AD17 GPIO28_FDO
AC17 TSVDD
TSVSS
1D8V_VGA_S0 TSVDD
L55 (1.8V@13mA TSVDD)
1 2
MCB1005S121FBP-GP SUN-S3-XT-GP
(G_68.00084.B21) (G_) (G_) (G_071.0MARS.M001)

1
C12341 C759

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP
0717 modfiy for BOM

2
Change P/N from 071.EXOPR.M001 to 071.0MARS.M001

Pin AH26(HSYNC),AJ27(VSYNC)

A A

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
GPU_MARS_I/O
Size Document Number Rev
D Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 77 of 105
5 4 3 2 1
 5 4 3 2 1

GPU1C 3 OF 7
[81,82] MDA[0..31]
GDDR5/DDR3 GDDR5/DDR3
MDA0 K27 K17
DQA0_0 MAA0_0 MAA0 [81,82]
MDA1 J29 J20
DQA0_1 MAA0_1 MAA1 [81,82]
MDA2 H30 H23
DQA0_2 MAA0_2 MAA2 [81,82]
MDA3 H32 G23
D DQA0_3 MAA0_3 MAA3 [81,82] D
MDA4 G29 G24
DQA0_4 MAA0_4 MAA4 [81,82]
MDA5 F28 H24
DQA0_5 MAA0_5 MAA5 [81,82]
MDA6 F32 J19
DQA0_6 MAA0_6 MAA6 [81,82]
MDA7 F30 K19
DQA0_7 MAA0_7 MAA7 [81,82]
MDA8 C30 G20
DQA0_8 MAA0_8 MAA13 [81,82]
MDA9 F27 L17
MDA10 A28 DQA0_9 MAA0_9
MDA11 C28 DQA0_10 J14
DQA0_11 MAA1_0 MAA8 [81,82]
MDA12 E27 K14
DQA0_12 MAA1_1 MAA9 [81,82]
MDA13 G26 J11
DQA0_13 MAA1_2 MAA10 [81,82]
MDA14 D26 J13
DQA0_14 MAA1_3 MAA11 [81,82]
MDA15 F25 H11
DQA0_15 MAA1_4 MAA12 [81,82]
MDA16 A25 G11
DQA0_16 MAA1_5 MAA_BA2 [81,82]
MDA17 C25 J16
DQA0_17 MAA1_6 MAA_BA0 [81,82]
MDA18 E25 L15
DQA0_18 MAA1_7 MAA_BA1 [81,82]
MDA19 D24 G14
DQA0_19 MAA1_8 MAA14 [81,82]
MDA20 E23 L16

MEMORY INTERFACE
MDA21 F23 DQA0_20 MAA1_9
MDA22 D22 DQA0_21 E32
DQA0_22 WCKA0_0 DQMA0 [82]
MDA23 F21 E30
DQA0_23 WCKA0#_0 DQMA1 [82]
MDA24 E21 A21
DQA0_24 WCKA0_1 DQMA2 [81]
MDA25 D20 C21
DQA0_25 WCKA0#_1 DQMA3 [81]
MDA26 F19 E13
DQA0_26 WCKA1_0 DQMA4 [82]
MDA27 A19 D12
DQA0_27 WCKA1#_0 DQMA5 [81]
MDA28 D18 E3
DQA0_28 WCKA1_1 DQMA6 [81]
MDA29 F17 F4
DQA0_29 WCKA1#_1 DQMA7 [82]
MDA30 A17
MDA31 C17 DQA0_30 H28
[81,82] MDA[32..63] DQA0_31 EDCA0_0 QSAP_0 [82]
MDA32 E17 C27
DQA1_0 EDCA0_1 QSAP_1 [82]
C MDA33 D16 A23 C
DQA1_1 EDCA0_2 QSAP_2 [81]
MDA34 F15 E19
DQA1_2 EDCA0_3 QSAP_3 [81]
MDA35 A15 E15
DQA1_3 EDCA1_0 QSAP_4 [82]
MDA36 D14 D10
DQA1_4 EDCA1_1 QSAP_5 [81]
MDA37 F13 D6
DQA1_5 EDCA1_2 QSAP_6 [81]
MDA38 A13 G5
DQA1_6 EDCA1_3 QSAP_7 [82]
MDA39 C13
MDA40 E11 DQA1_7 H27
DQA1_8 DDBIA0_0 QSAN_0 [82]
MDA41 A11 A27
DQA1_9 DDBIA0_1 QSAN_1 [82]
MDA42 C11 C23
DQA1_10 DDBIA0_2 QSAN_2 [81]
MDA43 F11 C19
DQA1_11 DDBIA0_3 QSAN_3 [81]
MDA44 A9 C15
1D35V_VGA_S0 1D35V_VGA_S0 DQA1_12 DDBIA1_0 QSAN_4 [82]
MDA45 C9 E9
DQA1_13 DDBIA1_1 QSAN_5 [81]
MDA46 F9 C5
DQA1_14 DDBIA1_2 QSAN_6 [81]
MDA47 D8 H4
DQA1_15 DDBIA1_3 QSAN_7 [82]
1

MDA48 E7
R1890 R1200 MDA49 A7 DQA1_16 L18
40D2R2F-GP 40D2R2F-GP MDA50 C7 DQA1_17 ADBIA0 K16 ODTA0 [81,82]
Ra Ra DQA1_18 ADBIA1 ODTA1 [81,82]
(G_) (G_) MDA51 F7
MDA52 A5 DQA1_19 H26
2

MVREFDA MVREFSA MDA53 E5 DQA1_20 CLKA0 H25 CLKA0 [81,82]

MDA54 C3 DQA1_21 CLKA0# CLKA0# [81,82]
DQA1_22
1

MDA55 E1 G9
DQA1_23 CLKA1 CLKA1 [81,82]
1

Rb R1888 C12342 Rb R1889 C761 MDA56 G7 H9

DQA1_24 CLKA1# CLKA1# [81,82]
SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

100R2F-L1-GP-U (G_) 100R2F-L1-GP-U (G_) MDA57 G6

(G_) (G_) MDA58 G1 DQA1_25 G22
2

MDA59 G3 DQA1_26 RASA0# G17 RASA0# [81,82]

2

MDA60 J6 DQA1_27 RASA1# RASA1# [81,82]

MDA61 J1 DQA1_28 G19
MDA62 J3 DQA1_29 CASA0# G16 CASA0# [81,82]
B
MDA63 J5 DQA1_30 CASA1# CASA1# [81,82] B
DQA1_31 H22
1D35V_VGA_S0 CSA0#_0 CSA0#_0 [81,82]
NC FOR MARS MVREFDA K26 J22
MVREFSA J26 MVREFDA CSA0#_1
MVREFSA G13
CSA1#_0 CSA1#_0 [81,82]
J25 K13
NC#J25 CSA1#_1
1

(R_) (G_)1 R1201 2 MEM_CALRP0 K25

R1204 MEM_CALRP0 K20
2K2R2J-2-GP 120R2F-GP CKEA0 J17 CKEA0 [81,82]
(G_) CKEA1 CKEA1 [81,82]
R79962 G25
2

2 1 DRAM_RST_R R1202 2 (G_) 1 10R2F-L-GP DRAM_RST L10 WEA0# H10 WEA0# [81,82]
[81,82] MEM_RST DRAM_RST# WEA1# WEA1# [81,82]
47R2J-2-GP K8
CLKTESTA
1

L7
CLKTESTB
1

(G_) (G_) (R_)

C762 R1205 C839 CLKTESTA CLKTESTB
SC120P50V2JN-1-DL-GP 4K99R2F-L-GP SC68P50V2JN-1GP
2

SUN-S3-XT-GP (G_071.0MARS.M001)
2

(R_) C764 (R_) C763

SCD1U16V2KX-3GPSCD1U16V2KX-3GP
2

CLKTESTA_C CLKTESTB_C
1

R1207 R1206
(R_) 51D1R2F-GP (R_) 51D1R2F-GP
2

A A
<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
GPU_MARS_MEMORY
Size Document Number Rev
Custom Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 78 of 105
5 4 3 2 1
 5 4 3 2 1

[77] PS_0
PS_0 Aperture Size = 256MB
[77] PS_1
PS_1
PS_1[1]=0 => PCIe GEN2 (BRAWSWELL)
JTAG SIGNAL OPTION
[77] PS_2
PS_2 01001 Normal Debug pilot run
PS_3
[77] PS_3 Signal mode mode mode
1D8V_VGA_S0 11000
1D8V_VGA_S0 TESTEN "0"(PD) "1"(PU) "0"(PD)

2
R79963 JTAG_TRST# "1"(PU) "1"(PU) NC

2
8K45R2F-2-GP
R943
(G_)
8K45R2F-2-GP
JTAG_TCK "0"(PD) "1"(PU) NC

1
PS_0 (R_)

1
1
(G_) PS_1 11/27 R948 JTAG_TMS "1"(PU) "1"(PU) NC

1
R80090 C1847 change to 64.47515.6DL(4.75k)

1
2KR2F-3-GP SCD082U16V2KX-1-GP

2
(G_) R948 (R_)

2
82nF 4K75R2F-1-GP C1849

2
D (G_) SCD082U16V2KX-GP D

1
3D3V_VGA_S0

2
open

R80092 1 (R_) 2 10KR2J-L-GP

[77] JTAG_TMS_VGA

R1893 1 (R_) 2 10KR2J-L-GP

[77] JTAG_TRST#_VGA

R79965 1 (R_) 2 10KR2J-L-GP

00000 PS_3[3-1] => MEM_ID setting, need decide for AMD [77] JTAG_TDI_VGA

11XXX R1895 1 (R_) 2 10KR2J-L-GP

1D8V_VGA_S0 [77] JTAG_TDO_VGA
1D8V_VGA_S0
2

TESTEN R302 1 (R_) 2 5K11R2F-L1-GP

[77] TESTEN

1
R1900
8K45R2F-2-GP R80091
(R_) SC028 6K98R2F-GP
(G_) R1897 1 (G_) 2 1KR2F-3-GP
1

PS_2
11001:HYNIX 2G R80091:8K45 R940:2K

2
(G_) PS_3
-1011
1

C1850
11010:SAMSUNG 2G R80091:4K53 R940:2K

1
R1899 SCD68U16V3KX-3-GP (R_) R963 1 (R_) 2 10KR2J-L-GP
[77] JTAG_TCK_VGA

1
4K75R2F-1-GP R940 C1848
11011:MICRON 2G R80091:6K98 R940:4k99
2

(G_) 4K99R2F-L-GP SCD68U16V3KX-3-GP

(G_)
2

11100:SAMSUNG 1GB R80091:4K53 R940:4k99

2
680nF

2
Change to from 10nF to 680nF, same as AIO
680nF

C C

B B

THERMAL PROTECTION

11/15 Reserved to PMU_RESETBUTTON

R80198 2 (R_) 1 0R2J-2-GP
PSTBTN_N [18,99]

R1920 2 (G_) 1 0R2J-2-GP

SYS_PWRGD [18,39]

CTFb
GPIO17_THERMAL_INT 2 (R_) 1 FOR ONE TIME CTF USE 47K R79964 2 (R_) 1 0R2J-2-GP
[77] GPIO17_THERMAL_INT FOR RESETABLE CTF USE 2K GPU_THERM_SHUTDOWN* [85]
R1896 47KR2F-GP

C
R79967 Q9631
GPIO19_CTF 2 (G_) 1 GPIO19_CTF_R 1 (G_) 2 CTF_TRIP B MMBT3904-4-GP
[77] GPIO19_CTF
R79966 47KR2F-GP 2K2R2J-2-GP (G_84.T3904.H11)

E
1

1
-1011 R1894 R80268

2
Change symbol 1KR2J-1-GP 100KR2J-1-GP (G_)
D5209 (G_) (R_) C12343
1 SCD01U25V2KX-3DLGP

1
1A020
3

PLTRST_SL_N 2
[24,76] PLTRST_SL_N
A BAT54A-7-F-2-GP A
(G_75.00054.R7D)

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
GPU_MARS_STRAP
Size Document Number Rev
D Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 79 of 105
5 4 3 2 1
 5 4 3 2 1

1D8V_VGA_S0

(1.8V@100mA)
C12359 C12364 C12362

1
C12358

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC4D7U6D3V3KX-DLGP
(G_) (G_) (G_) (G_)

2
1D35V_VGA_S0
(VDDR1@3A)
GPU1D 4 OF 7

1
C12345 C12352 C775 C777 C765 C12368 C768 AM30 1D8V_VGA_S0 DPLL_PVDD GPU1G 7 OF 7
PCIE_PVDD

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

PCIE
(G_) (G_) (G_) (G_) (G_) (G_) (G_) MEM I/O
L56
H13 AB23 (G_) (1.8V@40mA) DP POWER NC/DP POWER
2

2
H16 VDDR1 NC#AB23 AC23 1 2
H19 VDDR1 NC#AC23 AD24 AG15 AE11
VDDR1 NC#AD24 MHC1608S221NBP-GP NC_DP_VDDR#AG15 NC#AE11
J10 AE24 NC FOR MARS C829 AG16 AF11
VDDR1 NC#AE24 NC_DP_VDDR#AG16 NC#AF11

1
J23 AE25 C830 C827 (G_) AF16 AE13
VDDR1 NC#AE25 NC_DP_VDDR#AF16 NC#AE13

SC4D7U6D3V3KX-DLGP

SC1U10V2KX-1DLGP

SCD1U16V2KX-3DLGP
D J24 AE26 (G_) (G_) AG17 AF13 D
J9 VDDR1 NC#AE26 AF25 AG18 NC_DP_VDDR#AG17 NC#AF13 AG8

2
K10 VDDR1 NC#AF25 AG26 AG19 NC_DP_VDDR#AG18 NC#AG8 AG10
C12347 K23 VDDR1 NC#AG26 0D95V_VGA_S0 AF14 NC_DP_VDDR#AG19 NC#AG10
VDDR1 DP_VDDR
1

1
SCD1U16V2KX-3DLGP

SC22U6D3V5MX-2DLGP
C12349 C12355 C12351 C776 C778 K24 (0.95V@2.5A(GEN3.0))
VDDR1
SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC4D7U6D3V3KX-DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP
(G_) (G_) C774 (G_) (G_) (G_) (G_) K9 L23 NC FOR MARS
L11 VDDR1 PCIE_VDDC L24 C12353 C801 C800 C803 C798 C799
2

2
VDDR1 PCIE_VDDC

1
L12 L25 C12361
VDDR1 PCIE_VDDC

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC4D7U6D3V3KX-DLGP
(G_) L13 L26 (G_) (G_) (G_) (G_) (G_) (G_) (G_) AG20 AF6
L20 VDDR1 PCIE_VDDC M22 0D95V_VGA_S0 DPLL_VDDC AG21 NC_DP_VDDC#AG20 NC#AF6 AF7

2
L21 VDDR1 PCIE_VDDC N22 AF22 NC_DP_VDDC#AG21 NC#AF7 AF8
L22 VDDR1 PCIE_VDDC N23 L57 AG22 NC_DP_VDDC#AF22 NC#AF8 AF9
VDDR1 PCIE_VDDC (0.95V@32mA) NC_DP_VDDC#AG22 NC#AF9
N24 1 2 AD14
1D8V_VGA_S0 PCIE_VDDC R22 DP_VDDC
PCIE_VDDC MHC1608S221NBP-GP (G_)
0811 eric modfiy T22 C826
PCIE_VDDC

1
VDDC_CT LEVEL U22 C828 C825 (G_)
L48 for BOM TRANSLATION PCIE_VDDC

SC4D7U6D3V3KX-DLGP

SC1U10V2KX-1DLGP

SCD1U16V2KX-3DLGP
C780 (1.8V@13mA) V22 (G_) (G_) AG14 AE1
PCIE_VDDC NC_DP_VSSR#AG14 NC#AE1
SC4D7U6D3V3KX-DLGP

1 2 AA20 VGA_CORE AH14 AE3

2
C779 AA21 VDD_CT AM14 NC_DP_VSSR#AH14 NC#AE3 AG1
(G_68.00084.B21) VDD_CT NC_DP_VSSR#AM14 NC#AG1
1

1
SCD1U16V2KX-3DLGP

SC1U10V2KX-1DLGP
(G_) AB20 AA15 AM16 AG6
MCB1005S121FBP-GP C781 (G_) AB21 VDD_CT CORE VDDC N15 C12348 C12360 C12366 C12350 C12354 C805 AM18 NC_DP_VSSR#AM16 NC#AG6 AH5
VDD_CT VDDC

1
N17 AF23 NC_DP_VSSR#AM18 NC#AH5 AF10
0717 modfiy for BOM
2

2
VDDC NC_DP_VSSR#AF23 NC#AF10

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP
R13 (G_) (G_) (G_) (G_) (G_) (G_) AG23 AG9
(G_) I/O VDDC R16 AM20 NC_DP_VSSR#AG23 NC#AG9 AH8

2
AA17 VDDC R18 AM22 NC_DP_VSSR#AM20 NC#AH8 AM6
3D3V_VGA_S0 AA18 VDDR3 VDDC Y21 AM24 NC_DP_VSSR#AM22 NC#AM6 AM8
AB17 VDDR3 VDDC T12 AF19 NC_DP_VSSR#AM24 NC#AM8 AG7
AB18 VDDR3 VDDC T15 AF20 NC_DP_VSSR#AF19 NC#AG7 AG11
C784 VDDR3 VDDC T17 AE14 NC_DP_VSSR#AF20 NC#AG11
VDDC DP_VSSR
1

1
SC4D7U6D3V3KX-DLGP

C782 C783 V12 T20

1D8V_VGA_VDDR4 NC_VDDR4#V12 VDDC
SC1U10V2KX-1DLGP

(G_) (G_) (G_) Y12 U13

U12 NC_VDDR4#Y12 VDDC U16
2

2
SC1U10V2KX-1DLGP NC_VDDR4#U12 VDDC U18 R80255 1 2 150R2F-1-GP AF17 AE10
VDDC V21 NC_UPHYAB_DP_CALR NC#AE10
SB026 VDDC V15
VDDC V17
VDDC V20
VDDC

POWER
Y13 C12370 C12346 C12356 SUN-S3-XT-GP
VDDC

SC22U6D3V3MX-1-DL-GP
Y16 C810 C12369 (G_071.0MARS.M001)
VDDC

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC4D7U6D3V3KX-DLGP

SC4D7U6D3V3KX-DLGP
Y18 (G_) (G_) (G_) (G_) (G_)
VDDC AA12

2
VDDC M11
1D8V_VGA_S0 SPV18 VDDC N12
0717 modfiy for BOM VDDC U11
VDDC
L49 (1.8V@90mA)
1 2 PLL
(G_68.00084.B21) C788 C12357
1

1
SCD1U16V2KX-3DLGP

MCB1005S121FBP-GP (G_) C12344

SC4D7U6D3V3KX-DLGP

SC1U10V2KX-1DLGP

(G_)
C R21 C
(0.95V@1.4A)
2

MPV18 BIF_VDDC U21 GPU1E 5 OF 7

BIF_VDDC 0D95V_VGA_S0
(G_)
L8
MPLL_PVDD For MARS VGA_CORE
BIF_VDDC should be connectted with 0.95V AA27 A3
ISOLATED
SPV18 AB24 GND GND A30
CORE I/O (VDDCI@5A) GND GND
M13 C822 AB32 AA13
VDDCI GND GND

SC22U6D3V3MX-1-DL-GP
H7 M15 C821 AC24 AA16
SPLL_PVDD VDDCI M16 (G_) C823 C816 (G_) AC26 GND GND AB10
VDDCI GND GND

1
SCD1U16V2KX-3DLGP
M17 AC27 AB15
VDDCI GND GND

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP
SPV10 M18 (G_) (G_) AD25 AB6
MPV18 VDDCI M20 AD32 GND GND AC9

2
H8 VDDCI M21 AE27 GND GND AD6
L58 SPLL_VDDC VDDCI N20 AF32 GND GND AD8
(1.8V@75mA) VDDCI GND GND
1 2 J7 AG27 AE7
C786 SPLL_PVSS AH32 GND GND AG12
(G_68.00084.B21) GND GND
1

1
SCD1U16V2KX-3DLGP

SCD1U16V2KX-3DLGP

C12365 C12367 K28 AH10

GND GND
SC1U10V2KX-1DLGP

MCB1005S121FBP-GP (G_) K32 AH28

L27 GND GND B10
2

SUN-S3-XT-GP C817 C818 C819 M32 GND GND B12

1
GND GND

SCD1U16V2KX-3DLGP
(G_) (G_) (G_071.0MARS.M001) C824 C820 N25 B14
GND GND

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP

SC1U10V2KX-1DLGP
(G_) (G_) (G_) (G_) (G_) N27 B16
P25 GND GND B18

2
P32 GND GND B20
R27 GND GND B22
T25 GND GND B24
T32 GND GND B26
U25 GND GND B6
SB026 GND GND
U27 B8
V32 GND GND C1
0D95V_VGA_S0 SPV10 W25 GND GND C32
W26 GND GND E28
0717 modfiy for BOM 1D8V_VGA_VDDR4 1D8V_VGA_S0 GND GND
W27 F10
L59 L62 Y25 GND GND F12
(0.95@100mA) GND GND
1 2 1 2 Y32 F14
C787(G_) C785 MCB1005S121FBP-GP GND GND F16
(G_68.00084.B21) GND
1

1
SC1U10V2KX-1DLGP

SCD1U16V2KX-3DLGP

SC4D7U6D3V3KX-DLGP (G_) (G_) (G_68.00084.B21) F18

MCB1005S121FBP-GP
1

(G_) C12363 C12405 C12406 GND F2

SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP GND F20
2

M6 GND F22
2

(G_) N13 GND GND F24

N16 GND GND F26
N18 GND GND F6
N21 GND GND F8
GND
P6 GND GND G10
P9 GND GND G27
R12 GND GND G31
R15 GND GND G8
R17 GND GND H14
B R20 GND GND H17 B
T13 GND GND H2
T16 GND GND H20
T18 GND GND H6
T21 GND GND J27
T6 GND GND J31
U15 GND GND K11
U17 GND GND K2
U20 GND GND K22
U9 GND GND K6
V13 GND GND
V16 GND
V18 GND
Y10 GND
Y15 GND
Y17 GND
Y20 GND
R11 GND A32
T11 GND VSS_MECH AM1 Note:
AA11 GND VSS_MECH AM32 VSS_MECH balls are electrically connected to the ASIC’s
M12 GND VSS_MECH ground plane (VSS), however, they are not needed as ground signals.
N11 GND
V11 GND
GND

SUN-S3-XT-GP
(G_071.0MARS.M001)

A A

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
GPU_MARS_PWR/GND
Size Document Number Rev
D Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 80 of 105
5 4 3 2 1
 5 4 3 2 1

1D35V_VGA_S0
MEM1
MDA[0..31] [78,82]
K8 E3 MDA24
K2 VDD DQL0 F7 MDA29
N1 VDD DQL1 F2 MDA28

1
VDD DQL2

SCD1U16V2KX-3DLGP

SCD1U16V2KX-3DLGP

SCD1U16V2KX-3DLGP

SCD1U16V2KX-3DLGP

SCD1U16V2KX-3DLGP
R9 F8 MDA31
C1851 C1852 C12328 C514 C500 B2 VDD DQL3 H3 MDA26
D9 VDD DQL4 H8 MDA30

2
G7 VDD DQL5 G2 MDA25
(G_) (G_) (G_) (G_) (G_) R1 VDD DQL6 H7 MDA27
N9 VDD DQL7
VDD D7 MDA21
A8 DQU0 C3 MDA19
A1 VDDQ DQU1 C8 MDA23
C1 VDDQ DQU2 C2 MDA17
D
C9 VDDQ DQU3 A7 MDA20 D
D2 VDDQ DQU4 A2 MDA16
E9 VDDQ DQU5 B8 MDA22
F1 VDDQ DQU6 A3 MDA18
H9 VDDQ DQU7
H2 VDDQ C7
VDDQ DQSU B7 QSAP_2 [78]
VRAM2_VREFDQ DQSU# QSAN_2 [78]
H1
VRAM2_VREFCA M8 VREFDQ F3
VRAM_ZQ2 VREFCA DQSL QSAP_3 [78]
1 2 L8 G3
ZQ DQSL# QSAN_3 [78]
R899
(G_) 243R2F-2-GP K1
ODT ODTA0 [78,82]
N3
[78,81,82] MAA0 P7 A0
[78,81,82] MAA1 A1
P3 L2
[78,81,82] MAA2 A2 CS# CSA0#_0 [78,82]
N2 T2
[78,81,82] MAA3 P8 A3 RESET# MEM_RST [78,81,82]
[78,81,82] MAA4 A4
P2
[78,81,82] MAA5 R8 A5
[78,81,82] MAA6 A6
R2 L9
[78,81,82] MAA7 A7 NC#L9
T8 L1
[78,81,82] MAA8 R3 A8 NC#L1 J9
[78,81,82] MAA9 A9 NC#J9
L7 J1
[78,81,82] MAA10 R7 A10/AP NC#J1
[78,81,82] MAA11 A11 1D35V_VGA_S0 1D35V_VGA_S0
N7
[78,81,82] MAA12 A12/BC#
T3 J8
[78,81,82] MAA13 T7 A13 VSS M1
[78,81,82] MAA14 A14 VSS

2
M7 M9 (G_) (G_)
A15 VSS J2 R203 R230
M2 VSS P9
[78,81,82] MAA_BA0 BA0 VSS 2K1R2F-GP 2K1R2F-GP
N8 G8
[78,81,82] MAA_BA1 M3 BA1 VSS B3
[78,81,82] MAA_BA2

1
BA2 VSS T1
VSS A9 VRAM2_VREFDQ VRAM2_VREFCA
J7 VSS T9
[78,82] CLKA0 CK VSS
K7 E1
[78,82] CLKA0# CK# VSS

2
P1 (G_) (G_) (G_) (G_) (G_)
VSS

1
C K9 R202 C1854 C835 R1905 C163 C
[78,82] CKEA0 CKE G1 2K1R2F-GP SCD1U16V2KX-3DLGP SC1U10V2KX-1DLGP 2K1R2F-GP SCD1U16V2KX-3DLGP
VSSQ F9

2
D3 VSSQ E8
[78] DQMA2

1
E7 DMU VSSQ E2
[78] DQMA3 DML VSSQ D8
VSSQ D1
L3 VSSQ B9
[78,82] WEA0# WE# VSSQ
K3 B1
[78,82] CASA0# J3 CAS# VSSQ G9
[78,82] RASA0# RAS# VSSQ

H5TQ1G63DFR-11C-1-GP

(G_PP8TP$AA)

change P/N to MICRON 4Gb VRAM

1D35V_VGA_S0
MEM2 1D35V_VGA_S0 1D35V_VGA_S0
MDA[32..63] [78,82]
K8 E3 MDA49
VDD DQL0

2
K2 F7 MDA53 (G_) (G_)
N1 VDD DQL1 F2 MDA51 R945 R79968
1

VDD DQL2
SCD1U16V2KX-3DLGP

SCD1U16V2KX-3DLGP

SCD1U16V2KX-3DLGP

SCD1U16V2KX-3DLGP

SCD1U16V2KX-3DLGP

R9 F8 MDA54 2K1R2F-GP 2K1R2F-GP

C1853 C12329 C12330 C616 C489 B2 VDD DQL3 H3 MDA50
D9 VDD DQL4 H8 MDA55
2

1
G7 VDD DQL5 G2 MDA48
(G_) (G_) (G_) (G_) (G_) R1 VDD DQL6 H7 MDA52 VRAM4_VREFDQ VRAM4_VREFCA
N9 VDD DQL7
VDD D7 MDA46
DQU0

2
A8 C3 MDA40 (G_) (G_) (G_) (G_)
VDDQ DQU1

1
A1 C8 MDA47 R946 C1860 R1911 C1861
C1 VDDQ DQU2 C2 MDA43 SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP
VDDQ DQU3 2K1R2F-GP 2K1R2F-GP
C9 A7 MDA44

2
D2 VDDQ DQU4 A2 MDA42

1
B
E9 VDDQ DQU5 B8 MDA45 B
F1 VDDQ DQU6 A3 MDA41
H9 VDDQ DQU7
H2 VDDQ C7
VDDQ DQSU QSAP_5 [78]
B7
VRAM4_VREFDQ DQSU# QSAN_5 [78]
H1
VRAM4_VREFCA M8 VREFDQ F3
VRAM_ZQ4 VREFCA DQSL QSAP_6 [78]
1 2 L8 G3
ZQ DQSL# QSAN_6 [78]
R320
(G_) 243R2F-2-GP K1
ODT ODTA1 [78,82]
N3
[78,81,82] MAA0 P7 A0
[78,81,82] MAA1 A1
P3 L2
[78,81,82] MAA2 N2 A2 CS# T2 CSA1#_0 [78,82]
[78,81,82] MAA3 A3 RESET# MEM_RST [78,81,82]
P8
[78,81,82] MAA4 A4
P2
[78,81,82] MAA5 R8 A5
[78,81,82] MAA6 A6
R2 L9
[78,81,82] MAA7 T8 A7 NC#L9 L1
[78,81,82] MAA8 A8 NC#L1
R3 J9
[78,81,82] MAA9 A9 NC#J9
L7 J1
[78,81,82] MAA10 R7 A10/AP NC#J1
[78,81,82] MAA11 A11
N7
[78,81,82] MAA12 T3 A12/BC# J8
[78,81,82] MAA13 A13 VSS
T7 M1
[78,81,82] MAA14 A14 VSS
M7 M9
A15 VSS J2
M2 VSS P9
[78,81,82] MAA_BA0 N8 BA0 VSS G8
[78,81,82] MAA_BA1 BA1 VSS
M3 B3
[78,81,82] MAA_BA2 BA2 VSS T1
VSS A9
J7 VSS T9
[78,82] CLKA1 K7 CK VSS E1
[78,82] CLKA1# CK# VSS P1
K9 VSS
[78,82] CKEA1 CKE G1
VSSQ F9
A A
D3 VSSQ E8
[78] DQMA5 DMU VSSQ
E7 E2
[78] DQMA6 DML VSSQ D8
VSSQ D1
L3 VSSQ B9
[78,82] WEA1# K3 WE# VSSQ B1 <Variant Name>
[78,82] CASA1# CAS# VSSQ
J3 G9
[78,82] RASA1# RAS# VSSQ Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
H5TQ1G63DFR-11C-1-GP
Hsichih, Taipei
(G_PP8TP$AA) Title
VRAM1,2(1/2)
Size Document Number Rev
change P/N to MICRON 4Gb VRAM C Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 81 of 105
5 4 3 2 1
 5 4 3 2 1

1D35V_VGA_S0
MEM3

K8 E3 MDA[0..31] [78,81]
MDA3
K2 VDD DQL0 F7 MDA1
N1 VDD DQL1 F2 MDA2
VDD DQL2

1
SCD1U16V2KX-3DLGP

SCD1U16V2KX-3DLGP

SCD1U16V2KX-3DLGP

SCD1U16V2KX-3DLGP

SCD1U16V2KX-3DLGP
R9 F8 MDA0
C557 C12374 C1856 C1857 C6711 B2 VDD DQL3 H3 MDA6
D9 VDD DQL4 H8 MDA4

2
G7 VDD DQL5 G2 MDA5
(G_) (G_) (G_) (G_) (G_) R1 VDD DQL6 H7 MDA7
N9 VDD DQL7
VDD D7 MDA8
A8 DQU0 C3 MDA12
A1 VDDQ DQU1 C8 MDA9
C1 VDDQ DQU2 C2 MDA14
VDDQ DQU3

1
C6710 C9 A7 MDA11 1D35V_VGA_S0 1D35V_VGA_S0
D
SC10U6D3V3MX-DL-GP D2 VDDQ DQU4 A2 MDA15 D

(G_) E9 VDDQ DQU5 B8 MDA10

2
VDDQ DQU6

2
F1 A3 MDA13 (G_) (G_)
H9 VDDQ DQU7 R80093 R885
H2 VDDQ C7
VDDQ DQSU QSAP_1 [78] 2K1R2F-GP 2K1R2F-GP
B7
VRAM1_VREFDQ H1 DQSU# QSAN_1 [78]

1
VRAM1_VREFCA M8 VREFDQ F3
1 2 VRAM_ZQ1 L8 VREFCA DQSL G3 QSAP_0 [78] VRAM1_VREFDQ VRAM1_VREFCA
ZQ DQSL# QSAN_0 [78]
R870
(G_) 243R2F-2-GP K1
ODT ODTA0 [78,81]

2
N3 (G_) (G_) (G_) (G_)
[78,81,82] MAA0 A0

1
P7 R924 C12334 R886 C12335
[78,81,82] MAA1 P3 A1 L2 2K1R2F-GP SCD1U16V2KX-3DLGP 2K1R2F-GP SCD1U16V2KX-3DLGP
[78,81,82] MAA2 A2 CS# CSA0#_0 [78,81]
N2 T2
[78,81,82] MAA3 MEM_RST [78,81,82]

2
P8 A3 RESET#
[78,81,82] MAA4

1
P2 A4
[78,81,82] MAA5 A5
R8
[78,81,82] MAA6 R2 A6 L9
[78,81,82] MAA7 A7 NC#L9
T8 L1
[78,81,82] MAA8 A8 NC#L1
R3 J9
[78,81,82] MAA9 L7 A9 NC#J9 J1
[78,81,82] MAA10 A10/AP NC#J1
R7
[78,81,82] MAA11 N7 A11
[78,81,82] MAA12 A12/BC#
T3 J8
[78,81,82] MAA13 A13 VSS
T7 M1
[78,81,82] MAA14 M7 A14 VSS M9
A15 VSS J2
M2 VSS P9
[78,81,82] MAA_BA0 BA0 VSS
N8 G8
[78,81,82] MAA_BA1 BA1 VSS
M3 B3
[78,81,82] MAA_BA2 BA2 VSS T1
VSS A9
J7 VSS T9
[78,81] CLKA0 CK VSS
K7 E1
[78,81] CLKA0# CK# VSS P1

1
R1907 K9 VSS
[78,81] CKEA0 CKE
1

C R1906 40D2R2F-GP G1 C
40D2R2F-GP (G_) VSSQ F9
(G_) D3 VSSQ E8
[78] DQMA1 DMU VSSQ
E7 E2
[78] DQMA0
2

DML VSSQ D8
2

GPU_CLKA0_T VSSQ D1
L3 VSSQ B9
[78,81] WEA0# WE# VSSQ
K3 B1
[78,81] CASA0#
2

J3 CAS# VSSQ G9
[78,81] RASA0# RAS# VSSQ
C1855
SCD01U25V2KX-3DLGP
1

(G_) H5TQ1G63DFR-11C-1-GP

(G_PP8TP$AA)

change P/N to MICRON 4Gb VRAM

1D35V_VGA_S0
MEM4
MDA[32..63] [78,81]
K8 E3 MDA38
K2 VDD DQL0 F7 MDA34
N1 VDD DQL1 F2 MDA36
1

VDD DQL2
SCD1U16V2KX-3DLGP

SCD1U16V2KX-3DLGP

SCD1U16V2KX-3DLGP

SCD1U16V2KX-3DLGP

SCD1U16V2KX-3DLGP

R9 F8 MDA32
C1859 C12332 C12333 C186 C486 B2 VDD DQL3 H3 MDA39
D9 VDD DQL4 H8 MDA35
2

G7 VDD DQL5 G2 MDA37

(G_) (G_) (G_) (G_) (G_) R1 VDD DQL6 H7 MDA33
N9 VDD DQL7 1D35V_VGA_S0 1D35V_VGA_S0
VDD D7 MDA56
A8 DQU0 C3 MDA61
VDDQ DQU1

2
A1 C8 MDA57 (G_) (G_)
C1 VDDQ DQU2 C2 MDA62 R1922 R1924
1

C1858 C9 VDDQ DQU3 A7 MDA58

VDDQ DQU4 2K1R2F-GP 2K1R2F-GP
D2 A2 MDA60
B
(G_) E9 VDDQ DQU5 B8 MDA59 B
2

1
SC10U6D3V3MX-DL-GP F1 VDDQ DQU6 A3 MDA63
H9 VDDQ DQU7 VRAM3_VREFDQ VRAM3_VREFCA
H2 VDDQ C7
VDDQ DQSU QSAP_7 [78]
B7
DQSU# QSAN_7 [78]

2
VRAM3_VREFDQ H1 (G_) (G_) (G_) (G_) (G_)
VREFDQ

1
VRAM3_VREFCA M8 F3 R1921 C1868 C1867 R1923 C1869
VRAM_ZQ3 VREFCA DQSL QSAP_4 [78]
1 2 L8 G3 2K1R2F-GP SCD1U16V2KX-3DLGP SC1U10V2KX-1DLGP 2K1R2F-GP SCD1U16V2KX-3DLGP
ZQ DQSL# QSAN_4 [78]
R299

2
(G_) 243R2F-2-GP K1
ODTA1 [78,81]

1
N3 ODT
[78,81,82] MAA0 P7 A0
[78,81,82] MAA1 A1
P3 L2
[78,81,82] MAA2 N2 A2 CS# T2 CSA1#_0 [78,81]
[78,81,82] MAA3 A3 RESET# MEM_RST [78,81,82]
P8
[78,81,82] MAA4 A4
P2
[78,81,82] MAA5 R8 A5
[78,81,82] MAA6 A6
R2 L9
[78,81,82] MAA7 T8 A7 NC#L9 L1
[78,81,82] MAA8 A8 NC#L1
R3 J9
[78,81,82] MAA9 A9 NC#J9
L7 J1
[78,81,82] MAA10 R7 A10/AP NC#J1
[78,81,82] MAA11 A11
N7
[78,81,82] MAA12 T3 A12/BC# J8
[78,81,82] MAA13 A13 VSS
T7 M1
[78,81,82] MAA14 A14 VSS
M7 M9
A15 VSS J2
M2 VSS P9
[78,81,82] MAA_BA0 N8 BA0 VSS G8
[78,81,82] MAA_BA1 BA1 VSS
M3 B3
[78,81,82] MAA_BA2 BA2 VSS T1
VSS A9
J7 VSS T9
[78,81] CLKA1 K7 CK VSS E1
[78,81] CLKA1# CK# VSS P1
1

R1908 R1909 K9 VSS

40D2R2F-GP 40D2R2F-GP [78,81] CKEA1 CKE G1
(G_) (G_) VSSQ F9
A A
D3 VSSQ E8
[78] DQMA7 DMU VSSQ
E7 E2
[78] DQMA4
2

DML VSSQ D8
GPU_CLKA1_T VSSQ D1
L3 VSSQ B9
[78,81] WEA1# K3 WE# VSSQ B1 <Variant Name>
[78,81] CASA1# CAS# VSSQ
2

J3 G9
[78,81] RASA1# RAS# VSSQ Wistron Incorporated
C12331
SCD01U25V2KX-3DLGP 21F, 88, Hsin Tai Wu Rd
1

(G_) H5TQ1G63DFR-11C-1-GP
Hsichih, Taipei
(G_PP8TP$AA) Title
VRAM3,4(2/2)
Size Document Number Rev
C
change P/N to MICRON 4Gb VRAM Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 82 of 105
5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 83 of 105

5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 84 of 105

5 4 3 2 1
 5 4 3 2 1

H_VID0
H_VID0 [77]
3D3V_VGA_S0

H_VID6

H_VID5

H_VID4

H_VID3

H_VID2

H_VID1

H_VID0
H_VID1
H_VID1 [77]

1
H_VID2
H_VID2 [77]
(G_) PR19

1 0R0402-PAD

1 0R0402-PAD

1 0R0402-PAD

1 0R0402-PAD

1 0R0402-PAD

1 0R0402-PAD

1 0R0402-PAD
10KR2F-2-GP
H_VID3

PR23

PR25

PR30

PR32

PR35

PR9773

PR9774
H_VID3 [77]
PR18

2
0R0402-PAD
1 2
H_VID4 [79] GPU_THERM_SHUTDOWN*
H_VID4 [77]

1
(R_) PC12
H_VID5 SCD1U25V3KX-GP
D H_VID5 [77] D

2
PR17
0R0402-PAD
PM_DPRSLPVR 1 2

PWR_VGA_CORE_DPRSLPVR

PWR_VGA_CORE_VID6

PWR_VGA_CORE_VID5

PWR_VGA_CORE_VID4

PWR_VGA_CORE_VID3

PWR_VGA_CORE_VID2

PWR_VGA_CORE_VID1

PWR_VGA_CORE_VID0
PWR_VGA_CORE_ON
11/16
CHANGE TO ZZ.CLOSE.001 PAD
2014/11/14
PWR_VGA_VIN DCBATOUT

PWR_VGA_VIN

3D3V_VGA_S0
12V Vin & Imax =27A PR9820 1 2 GAP-CLOSE-PWR-3-GP
084.00472.0037 SIR472ADP Iripple=7.46A
Vgs @ 4.5V, PR9821 1 2 GAP-CLOSE-PWR-3-GP

40

39

38

37

36

35

34

33

32

31
1

U8501 Id = 12.9A,
PR6 Rds(on) = 10.3~12.4mohm, PR9822 1 2 GAP-CLOSE-PWR-3-GP

CLK_EN#

DPRSLPVR

VR_ON

VID6

VID5

VID4

VID3

VID2

VID1

VID0
1K91R2F-1-GP PC5273 PC5270(G_) PC61 (G_)
(G_) SCD1U25V3KX-DLGP SC10U25V6KX-4DL-GP SC10U25V6KX-4DL-GP PR9823 1 2 GAP-CLOSE-PWR-3-GP
(G_) PC24 (G_) PC5269(G_)
2

2 PR14 1 PWR_VGA_CORE_PGOOD
1 30 84.SRA12.037 SIRA12DP SC10U25V6KX-4DL-GP SC10U25V6KX-4DL-GP PR9868 1 2 GAP-CLOSE-PWR-3-GP
[47,86,87] GPU_CORE_PWROK PGOOD BOOT2
0R0402-PAD VCC Vgs @ 4.5V,

1
1

1
PSI# 2 PR10 1 PWR_VGA_CORE_PSI# 2 29 PR9866 1 2 GAP-CLOSE-PWR-3-GP
Id = 20A,
PR9 (G_) 0R0402-PAD PSI# UGATE2
Rds(on) = 4.4~6.0mohm, PT2 (G_79.47612.3GL)
2 1 PRW_VGA_CORE_RBIAS3 28 SE47U25VM-14-GP PR9867 1 2 GAP-CLOSE-PWR-3-GP

2
2

2
RBIAS PHASE2

5
6
7
8

5
6
7
8
47KR2F-GP TP204 47uF/25V,

D
D
D
D

D
D
D
D
PR9782 (G_) (G_) 1 VR_TT# 4 27 PR9869 1 2 GAP-CLOSE-PWR-3-GP
4K02R2F-GP PR60 NTC-470K-9-GP-U
TPAD30 VR_TT# VSSP2 (G_) PR44 20140807 PU1 PU2 ESR=30mohm 0717 modfiy for BOM
1 2 62882_NTC_R 1 2 PWR_VGA_CORE_NTC 5 26 0R0402-PAD AON6552-GP AON6552-GP 2013.5.11 Ripple Current =2800mA
NTC ISL62882CHRTZ-T-GP LGATE2 (G_) (G_)

1
2 1 PWR_VGA_CORE_VW 6 25 PWR_VGA_CORE_VCCP PWR_VGA_CORE_UGATE1 4 PWR_VGA_CORE_UGATE1 4

G
0.36uH,
VW VCCP 20140729

S
S
S

S
S
S
(R_) PC9 2 1 PWR_VGA_CORE_COMP7 24 PWR_VGA_CORE_LGATE1B DCR=1.20~1.05 mohm, VGA_Power

3
2
1

3
2
1
COMP LGATE1B

1
SCD01U50V2KX-1GP (G_) (G_) PC18 PC17 (G_) Idc=35A,Isat=60A
0707 change symbol PR13 PWR_VGA_CORE_FB 8
FB DIS_Muxless LGATE1A
23 PWR_VGA_CORE_LGATE1A SC1U16V3KX-4DLGP SC1U16V3KX-4DLGP VGA_CORE Imax=27A
8K06R2F-GP

2
2 1 PWR_VGA_CORE_FB29 22 PL1 (G_)
FB2 VSSP1 0805 eric modify for BOM
PC7 (G_) IND-D36UH-19-GP
SC1KP50V2KX-1DLGP 10
ISEN2 PHASE1
21 PWR_VGA_CORE_PHASE1 PWR_VGA_CORE_PHASE1 1 2 TDC=28A
PWR_VGA_CORE_ISEN2

OCP>50A

UGATE1
BOOT1
ISUM+
ISEN1

ISUM-

1
VSEN

IMON
41 VDD
RTN

2
GND
VIN
1 (R_) 2 1 2

1
PR1 (G_) PC19 0805 eric modify PR9783 (G_) PT1
C 0R2J-2-GP PC8 (G_) (G_) SCD22U25V3KX-DL-GP 2D2R5J-1-GP PG4 PG3 E820U2D5VM-14-GP C
for BOM
PWR_VGA_CORE_ISEN1 11

12

13

14

15

16

17

18

19

20

5
6
7
8

5
6
7
8
SC33P50V2JN-3DLGP GAP-CLOSE GAP-CLOSE (G_09.8271V.08L)

2
D
D
D
D

D
D
D
D
PWR_VGA_CORE_UGATE1 PR43 (G_)

1
PWR_VGA_CORE_ISUM+

PWR_VGA_CORE_FB2 262882_COMP_R1
PWR_VGA_CORE_ISUM-

1 2 1 2 2D2R3-1-U-GP 820uF/2.5V,
PWR_VGA_CORE_VDD
PWR_VGA_CORE_RTN

PR8 PWR_VGA_CORE_BOOT1 1 2BOOT1_PHASE1 PU3 (G_) PU5207 PWR_VGA_CORE_SNB1

PWR_VGA_CORE_VIN
PWR_VGA_CORE_VSEN

ESR=7.0mohm
(G_) PC4 PC6 (G_) 47KR2F-GP PC59 (R_) 0805 eric modify for BOM AON6508-GP AON6508-GP PT3 PT4
SC22P50V2JN-4DLGP SC150P50V2JN-3DLGP (G_) SCD1U16V3KX-3GP PWR_VGA_CORE_LGATE1A (G_) 4 PWR_VGA_CORE_LGATE1A 4

G
E820U2D5VM-14-GP E820U2D5VM-14-GP

1
PWR_VGA_CORE_IMON 2 PWR_VGA_CORE_RTN

S
S
S

S
S
S
1 PC5267(G_) (G_09.8271V.08L) (G_09.8271V.08L)
2

(R_) PC5 PR9778 SC1500P50V3KX-DLGP

3
2
1

3
2
1
SCD22U25V3KX-GP 9K31R2F-GP DCBATOUT
PR12 20140729

2
PR9777 2 1
1

VCC 1 2 0R0603-PAD-2-GP-U PR101

(R_) (R_) 0R0402-PAD
2

0R2J-2-GP 2 1
1 PR11 2
VCC
1

0R0402-PAD-2-GP 2 1 PC60
SCD22U25V3KX-DL-GP 0805 eric modify TP203
PR9771 (G_) (G_)
for BOM
2

1R2F-GP TPAD30

PHASE1_R
1

1 2 62882_FB_VSEN 1 2 PC58 (G_)

(G_) PR20 SC1U16V3KX-4DLGP
562R2F-GP 1 2 (G_) PC11

1
2

+VGA_CORE_PHASE1
SC390P50V2KX-1-GP PWR_VGA_CORE_LGATE1B
0805 eric modify
PR21
1K87R2F-GP
for BOM
(G_) 0826 delete PR46
PC15 (G_) PR9781 (G_) PR45 (G_)
SCD033U25V2KX-1-GP 11KR2F-L-GP PWR_VGA_CORE_ISUM+ 3K65R3F-GP
1

PWR_VGA_CORE_ISUM+ 1 2
1

(G_) PC5268 PR42 (G_) PR9779 (G_)

SC330P50V2KX-3-DL-GP PR34 2K61R2F-1-GP 1R2F-GP
82D5R2F-1-GP PWR_VGA_CORE_VSUM- 1 2
2

(R_)
Put as
1VSUM_RR 2
1

VGA_CORE SCD22U25V3KX-DL-GP
2VSUM_RC 2

close to 20140806 (G_) PC16

GPU as
2

1 PR28 2
possible 0R0402-PAD 0805 eric modify
2
1

PC5271 (G_) (G_) PC13

SC330P50V2KX-3-DL-GP
for BOM
SCD01U25V2KX-3DLGP
PC14 (R_)
2

1 PR29 2 SCD01U50V2KX-1GP
1

0R0402-PAD PR51 (G_) 0707 change symbol

NTC-10K-27-GP-U
2 1 PWR_VGA_CORE_VSUM-
2
2

(G_) PC5272
2

SC1KP50V2KX-1DLGP PR16
1K21R2F-2-GP PC20 (G_)
1

(G_) SCD1U25V3KX-DLGP PR2

1

OCP Setting 0R0402-PAD

B 2 1 B
20140729

3D3V_VGA_S0
PR102 (R_) PR9776 (R_) PR9775 (R_) PR4 (G_)
1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP
PR103 (R_) PR9769 (G_) PR96 (G_) PR15 (R_)
1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP
1

(R_)
PR9772
1KR2J-1-GP
2

H_VID0
H_VID1 VGA Vcore 1.0V
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
VID0 VID1 VID2 VID3 VID4 VID5 VID6
PM_DPRSLPVR
PSI#
0 0 0 1 0 1 0
1

(G_) PR9768 PR3 (R_)

1KR2J-1-GP 1KR2J-1-GP
2

PR9770 (G_) PR33 (R_) PR26 (R_) PR7 (G_)

1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP
PR9780 (G_) PR31 (G_) PR5251 (G_)
1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP

A A

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
GPU_POWER CORE_(ISL62882C)
Size Document Number Rev
D Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 85 of 105
5 4 3 2 1
 5 4 3 2 1

0725 Eric modify to AO4468L

0D95V_VGA_S0
0D95V_S5 -->0D95V_VGA_S0
DCBATOUT

AO4468, SO-8

1
D
R79974
Id=11.6A, Qg=9~12nC D
470KR2F-GP Rdson=17.4~22m ohm 1A011
(G_) 0D95V_S5
0D95V_VGA_S0
R79663

2
U6707

2
VRAM_0D95_EN_D 1 (G_) 2 VRAM_0D95_EN_SW 4 5 PR9888 1 (R_) 2 0R5J-5-GP
R79971 3 6 PR9889 1 (R_) 2 0R5J-5-GP
G D
100KR2J-1-GP 10KR2J-3-GP 2 7 PR9890 1 (R_) 2 0R5J-5-GP
S D
1A001

1
(G_) 1 8
S D

2
R79975
S D
For Co-layout with U6707

1
3D3V_VGA_S0 1MR2J-1-GP (G_) AO4468L-GP

2
(G_) C6709 (G_)

1
Q9632 C12371 (G_) SCD1U16V2KX-3DLGP

2
1
2N7002KDW-1-GP SCD01U25V2KX-3DLGP 0D95V_VGA_S0

1
R79727 (G_)
10KR2J-3-GP DIS_EN_0D95_RUN_R
(R_)

2
(R_)

1
PR9784 C6705 R79972
1 2 DGPU_PWROK_0D95V R79973 (G_) (G_) SC10U10V5KX-2GP 10KR2J-3-GP
[47,85,86,87] GPU_CORE_PWROK
0R2J-2-GP 100KR2J-1-GP C6708 C6706 (G_)

2
(G_) (G_) SCD1U16V2KX-3DLGP SC10U10V5KX-2DLGP

1
1
20140729 modfiy Q6702

1
(R_)
C6707 to dual MOS
0811 modfiy for BOM

2
SCD1U10V2KX-4GP

0D95V_VGA_S0 1D8V_S5
For PX PD
Runtime D3 function

1
R79969 R79970
EVAL_PWRGD [24]
1KR2J-1-GP 1KR2J-1-GP
C (R_) (R_) 6 C

2
EVAL_PWRGD_1D5 2 Q9633A
MMBT3904DW-GP
(R_75.03904.07C)
Q9633B 1
3
MMBT3904DW-GP
EVAL_PWRGD_0D95 5 (R_75.03904.07C)

1
C12372
SC1U10V2KX-1GP 4
(R_)

2 SC065 Change to NC

1D8V_VGA_S0 0528 Eric modify from Victoria AIO

1D8V_S5 -->1D8V_VGA_S0
B
Iomax=2A B

1D8V_VGA_S0
1D8V_LDO_VGA
1D8V_S5
DCBATOUT
1

PR9874 1 2 GAP-CLOSE-PWR-3-GP
R1918
470KR2F-GP PR9875 1 2 GAP-CLOSE-PWR-3-GP
(G_) U42
1 D D 6 PR9787 1 2 GAP-CLOSE-PWR-3-GP
2

R1915 2 D D 5
1

VGA_1P8_EN2 1 2 VGA_1P8_EN4 1 2 VGA_1P8_EN3 3 G S 4 PR9788 1 2 GAP-CLOSE-PWR-3-GP

R1164 10KR2J-3-GP

2
100KR2J-1-GP (G_) 0R0402-PAD-2-GP AO6402A-GP

1
(G_) R1916 (G_) C853 11/16
4

(G_) R1917 C852 SCD1U16V2KX-3DLGP CHANGE TO ZZ.CLOSE.001 PAD

(
2

1KR2J-1-GP R (G_)

2
_)

2
R1919 (G_)
SC10U10V5KX-2GP

1
1

Q97 1MR2J-1-GP
2N7002KDW-1-GP (G_)
3

(G_)
2

VGA_1P8_EN1 C859
SCD1U50V3KX-GP
(R_)
[47,85,86,87] GPU_CORE_PWROK

High : Enable
1

LOW : Disable R1914 20140729 modfiy Q97

(G_) 100KR2J-1-GP to dual MOS
2

A A

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
GPU_POWER 0D95V/1D8V
Size Document Number Rev
C Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 86 of 105
5 4 3 2 1
 5 4 3 2 1

0528 Eric modify from victoria

3D3V_VGA_S0
3D3V_S0 to 3D3V_DELAY Transfer

3D3V_VGA_S0 VCC3
D Q9635 (G_84.02130.031) D
AO3413L-GP

D S

G
C836 (R_)
SCD1U10V2KX-4GP
1 2

GPU_VCC3_CTL_2

2
VCC3 R1195
39K2R2F-L-GP
(G_) R1129 (G_)
8K2R2J-3-GP

1
1 2

2
GPU_VCC3_CTL_3
R1126
100KR2J-1-GP
(G_)

D
1
Q9634
2N7002A-7-GP
PR5476 1 (R_) 2 0R2J-2-GP GPU_VCC3_CTL G (G_84.2N702.J31)
[24,56] SIO_GPU_EN

2
SC046 C1864

S
Change to NC SCD01U25V2KX-3DLGP

1
(G_)

C C

1D35V_VGA_S3 Pd=(1.8-1.5)*3.3=0.99W
VCC

1
PC5435 (G_)
SC1U25V3KX-1-DLGP
2
1D8V_S5

3D3V_VGA_S0 PU7

9
1 VIN 8
GND EN
1

2 7
FB POK

1
PR225 3 6
10KR2J-3-GP 4 VOUT VCNTL 5 PC5431 PC5432
(G_) VOUT VIN SC10U10V5KX-2DLGP SC10U10V5KX-2DLGP
2
Iomax=3.3A

2
(G_) (G_)
2

APL5912-KAC-TRG-GP
B +1.5V_GPU_PG 1D35V_VGA_S0 B
(G_74.00121.A31)
1

PC151
SCD1U16V2KX-3DLGP
(G_) Close to GPU DRAM
2

1
SCD1U16V2KX-3DLGP
C12373 (G_09.8271V.08L)
PC5434 PC5430 TC21
PR79 SC10U10V5KX-2DLGP SC10U10V5KX-2DLGP (G_) E820U2D5VM-7-GP

2
1P5V_GUP_FB_M1 1 (G_) 2 (G_) (G_)
1A001 10R2F-L-GP
1

1 2 DGPU_PWROK_1D5V (G_)
[47,85,86] GPU_CORE_PWROK
1

PR5261 R1 PR78 PC68

0R0402-PAD-2-GP 6K98R2F-GP SC27P50V2JN-2DLGP
1

PC5433 (G_)
2

SCD1U16V2KX-3DLGP
(R_)
2

1P5V_GUP_FB_M
1

(G_)
PR77
Vo(cal.)=1.3584V
R2
10KR2F-2-GP
Vo=0.8*(1+(R1/R2))
2

A A

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
GPU_POWER 3D3V/ 1D35V
Size Document Number Rev
C Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 87 of 105
5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 88 of 105

5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 89 of 105

5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 90 of 105

5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 91 of 105

5 4 3 2 1
 5 4 3 2 1

[18] SLP_SLP_S0#_CPU

[18,24] PM_SLP_S4#_CPU

[18,24] PM_SLP_S3#_CPU

[18,24,35,40,46,48,53,99] SLP_S3_N
[24,32,34,35,39,48,64,99] SLP_S4_N
[48,99] SLP_S0_N

[18] PCIE_WAKE#_CPU

D D
[18,99] PLT_RST#_CPU

SB3V SB3V

2
V_3P3_A SB3V V_3P3_A
R67 R1580
1D8V_S5 10KR2J-3-GP 1D8V_S5 10KR2J-3-GP

2
V_3P3_A

2
R54

1
R66 SLP_S4_N 1D8V_S5 10KR2J-3-GP R1579 SLP_S0_N
SB030

2
10KR2J-3-GP 10KR2J-3-GP

2
R63 change to NC R1582

1
10KR2J-3-GP R51 SLP_S3_N 10KR2J-3-GP
3 SB030 3

1
2
(R_) Q17B 10KR2J-3-GP (R_) Q1206B
PM_SLP_S4#_CPU_D 5 MMBT3904DW-GP R49 change to NC SLP_SLP_S0#_CPU_D 5 MMBT3904DW-GP
1

1
(75.03904.07C) 10KR2J-3-GP 3 (75.03904.07C)

1
R62 6 (R_) Q16B R1581 6
10KR2J-3-GP 4 PM_SLP_S3#_CPU_D 5 MMBT3904DW-GP 10KR2J-3-GP 4

1
PM_SLP_S4#_CPU 2 1 PM_SLP_S4#_CPU_G 2 Q17A (75.03904.07C) SLP_SLP_S0#_CPU 2 1 SLP_SLP_S0#_CPU_G 2 Q1206A
MMBT3904DW-GP R48 6 MMBT3904DW-GP
(75.03904.07C) 10KR2J-3-GP 4 (75.03904.07C)

1
C31 1 PM_SLP_S3#_CPU 2 1 PM_SLP_S3#_CPU_G 2 Q16A C1607 1
SC1U10V2KX-1GP MMBT3904DW-GP SC1U10V2KX-1GP
(R_) (75.03904.07C) (R_)
2

2
1
C30 1
C
SD011 SC1U10V2KX-1GP C
(R_)

2
SD011

6/10 Allen Add 0 ohm

SB3V SB5V
1D8V_S5 PWR_V1P24A_PG

1
1

1
R1837 R1789
R1790 0R0402-PAD-2-GP 470R2F-GP R1788
470R2F-GP 1A001 470R2F-GP 1A001
1A001 6/10 Allen Add 0 ohm 6/10 Allen Add 0 ohm
Q1231

2
Q1232 Q1233

2
V_3P3_A 4 3 PWR_V1P24A_PG_L 4 3 SB3V_5V_PG_L1 2 SB3V_5V_PG 4 3 VNN_PG_L1 2 PWR_0P95V_PG
R1836 0R0402-PAD-2-GP R1835 0R0402-PAD-2-GP
5 2 5 2 5 2

1
1D8V_S5_D 6 1 SB3V_D 6 1 SB5V_D 6 1

R5290 2N7002KDW-GP 2N7002KDW-GP 2N7002KDW-GP

10KR2J-3-GP (75.27002.F7C) (75.27002.F7C) (75.27002.F7C)

2
B B

SIO_EUP_EN#_D

6/10 Allen Add 0 ohm 6/10 Allen Add 0 ohm

PWR_VCORE_VNN 1P15V_S5 PWR_1P05V_PG 1D24V_S5 PWR_1P15V_PG

1 1P05V_S5

2
0903 Jeffrey
D

1
10/03 Del DISCHANGE_EN R1784 R1838 R1839

1
470R2F-GP
R1785 R1786 0R0402-PAD-2-GP 0R0402-PAD-2-GP
Q1234 470R2F-GP 470R2F-GP R1787
SIO_EUP_EN# 1 2 SIO_EUP_EN#_G G 2N7002H-GP 470R2F-GP
1A001 1A001
2

Q1228 Q1229

1
Q1230

1
R1840 0R2J-2-GP (84.2N702.J31)

2
1D8V_S5 4 3 1P05V_S5_D 4 3 PWR_1P05V_PG_L 4 3 PWR_1P15V_PG_L
S

2
5 2 5 2 5 2
2

SB3V R58 1D8V_S5 PWR_VCORE_VNN_D 6 1 1P15V_S5_D 6 1 1D24V_S5_D 6 1

[24,47,49,77] SIO_EUP_EN#
10KR2J-3-GP
[47,49,50] PWR_1P05V_PG 2N7002KDW-GP 2N7002KDW-GP 2N7002KDW-GP
2

[50,51] PWR_1P15V_PG (75.27002.F7C) (75.27002.F7C) (75.27002.F7C)

1

R60
10KR2J-3-GP PCIE_WAKE#_CPU_B R59
[51,52] PWR_V1P24A_PG
[41,52] SB3V_5V_PG 10KR2J-3-GP
B
1

[47] PWR_0P95V_PG WAKE_N E C PCIE_WAKE#_CPU SIO_EUP_EN# S0 S3 S5 DS

[31,61] WAKE_N
Q19
LMBT3904LT1G-GP
Enable H H H H Note
A SIO EC pin side have resister and cap A
Disable H H H L
PCIEx1 wake

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
LEVEL SHIFT
Size Document Number Rev
Custom Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 92 of 105
5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 93 of 105

5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 94 of 105

5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 95 of 105

5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 96 of 105

5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 97 of 105

5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 98 of 105

5 4 3 2 1
 5 4 3 2 1

1D8V_S0 1D8V_S5 1D8V_S0

1
C28 1 TAP_PREQ#_R OBSFN_C0 1
TPAD30 TP4136 TAP_PRDY# TP4137 TPAD30
SCD1U10V2KX-5DLGP TPAD30 TP4138 1

2
1 DBG0 DBG8 1
TPAD30 TP4139 TP4140 TPAD30
TPAD30 TP4141 1 DBG1 DBG9 1
TP4142 TPAD30

TPAD30 TP4143 1 DBG2 DBG10 1

D TP4144 TPAD30 D
1 DBG3 DBG11 1
1D8V_S5 TPAD30 TP4145 TP4146 TPAD30

TPAD30 TP4147 1 DBG16

(D_)

1
C26 1 DBG4 DBG12 1
TPAD30 TP4148 TP4149 TPAD30
SCD1U10V2KX-5DLGP 1 DBG5 DBG13 1
TPAD30 TP4150 TP4151 TPAD30

2
1 DBG6 DBG14 1
TPAD30 TP4152 TP4153 TPAD30
TPAD30 TP4154 1 DBG7 DBG15 1
TP4155 TPAD30
1 RSMRST_N_XDP
TPAD30 TP4156
1 XDP_PWNBTN_N 1
11/13 FOR APS1
TPAD30 TP2 TP4164 TPAD30
並並並並PCB空空
1 COREPWROK_XDP PLT_RST#_XDP R46 1 (D_) 2 1KR2J-1-GP
TPAD30 TP4157 SOC_RUNTIME_SCI#_XDP PSTBTN_N PLT_RST#_CPU [18]
1
TPAD30 TP4158
SMB0_DATA_MAIN XDP_H_TDO 1
SMB0_CLK_MAIN XDP_H_TRST_N 1 TP4159 TPAD30
XDP_H_TDI TP4160 TPAD30 SLP_S3_N SLP_S3_N_APS
1 1 R80187 2 1
[18,24,35,40,46,48,53,92] SLP_S3_N XDP_H_TCK XDP_H_TMS TP4161 TPAD30 TP4128 TPAD30
1 1 0R0402-PAD-2-GP
[24,32,34,35,39,48,64,92] SLP_S4_N TPAD30 TP4162 XDP_PRESENT_N TP4163 TPAD30
2 (D_) 1
[48,92] SLP_S0_N SB3V SLP_S4_N SLP_S4_N_APS
R1568 10KR2J-3-GP 1 R80189 2 1
0R0402-PAD-2-GP TP4129 TPAD30
1
TP4165 TPAD30 SLP_S0_N SLP_S0_APS
1 R80188 2 1
0R0402-PAD-2-GP TP4130 TPAD30

[18] COREPWROK Debug Header [18,24,99] RSMRST_N 1 R80192 2 RSMRST_APS 1

TP4131 TPAD30
0R0402-PAD-2-GP
[15,17] SOC_RUNTIME_SCI# PSTBTN_N
1 R80194 2 SRTCRST_APS 1
[18,79,99] PSTBTN_N [18] PCH_SRTCRSTB_PULLUP 0R0402-PAD-2-GP TP4133 TPAD30

1
[18,24,99] RSMRST_N COREPWROK R1820 1 (D_) 2 10KR2J-3-GP COREPWROK_XDP C24 1 R80193 2 PWRBTN_APS 1
[18] APU_PWNBTN_N TP4132 TPAD30
[18,24] SIO_PWNBTN_N SCD1U16V2KX-3DLGP 0R0402-PAD-2-GP

2
C C
RSMRST_N R477 2 (D_) 1 1KR2J-1-GP RSMRST_N_XDP
[12,17,37,55,77] SMB0_CLK_MAIN PSTBTN_N_APS
1 R80196 2 1
[12,17,37,55,77] SMB0_DATA_MAIN [18,79,99] PSTBTN_N TP4134 TPAD30
0R0402-PAD-2-GP
SIO_PWNBTN_N R47 1 (D_) 2 0R2J-2-GP XDP_PWNBTN_N SOC_RUNTIME_SCI#_XDP
XDP

1
SOC_RUNTIME_SCI# R1569 1 (D_) 2 0R2J-2-GP SOC_RUNTIME_SCI#_XDP (R_)
[17] DBG16
C1605
[8] DBG15
SCD1U16V2KX-3GP
[8] DBG14

2
[8] DBG13
[8] DBG12
[8] DBG11
[8] DBG10
[8] DBG9
[8] DBG8
[8,15] OBSFN_C0
[18] XDP_H_TCK
[18] XDP_H_TRST_N
[18] XDP_H_TMS
[18] XDP_H_TDI
[18] TAP_PREQ# 1D8V_S5
[18] XDP_H_TDO
[18] TAP_PRDY#

1
(R_)
[17] DBG0 1D8V_S5
R43
[17] DBG1
220R2F-GP
[17] DBG2
U2
[17] DBG3
[17] DBG4

2
1 5
[17] DBG5 TAP_PREQ#_R 2 NC#1 VCC
[17] DBG6 A TAP_PREQ#
3 4
[17] DBG7 GND Y

1
(R_)
C35 SN74AUP1G34DBVR-GP C27
SCD1U16V2KX-3DLGP (R_) SCD1U10V2KX-5GP
2

2
(D_)
B B

R34 1 (D_) 2 0R2J-2-GP

A A

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
CPU_XDP
Size Document Number Rev
C Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 99 of 105
5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 100 of 105

5 4 3 2 1
 5 4 3 2 1

D D

C C

Blanking
B B

Wistron Incorporated
12F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title

Size Document Number Rev

A Rosa_Lily SFF -1

Date: Tuesday, June 23, 2015 Sheet 101 of 105

5 4 3 2 1
 5 4 3 2 1

Source Destination Signal

RTC Battery CPU/SIO RTC_VCC

RTC_TEST#
RTC Battery CPU/SIO RTC_RST#

D
Adaptor MB DCBATOUT D

V_3P3_A
VRs CPU/SIO V_5P0_A

Power
Button SIO PWRBTN_N

SIO VRs SIO_EUP_EN#

VRs MB VNN

VRs MB 1D05V_S5

VRs MB 1D15V_S5

VRs MB 1D24V_S5

VRs MB 1D8V_S5

VRs MB SB3V/SB5V

SIO CPU RSMRST_N

C C

SIO CPU PMC_PWBTN_N

CPU SIO / VRs SLP_S4#

VRs MB DDR_VDDQ

MB CPU DDR3_DRAM_PWROK

CPU SIO / VRs SLP_S3#

SIO VRs SIO_PSON#

VRs MB 1D5V_S0

VCC3
VRs MB VCC5
B B

VRs CPU VGG

VRs MB VCC0/1

VRs MB MEM_VTT

VRs MB 1D8V_S0

SIO MB PWRGD_3V

SIO CPU PMC_CORE_PWROK

SIO CPU DDR3_VCCA_PWROK

CPU MB PMC_PLTRST#

A A

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
Power Sequence
Size Document Number Rev
D Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 102 of 105
5 4 3 2 1
 5 4 3 2 1

AC/DC ADAPTER
POWER: ADP-90WB NCP81201
INPUT: 100~240V(1.5A) (UMA) +VGG
OUTPUT: 19.5V(4.62A) PWM
D 1.00V D
SLP_S3_N EN TDC 12A

8
NCP81201 (UMA) +VCC0_CPU
PWM 1.00V
+VGG_PWRGD EN TDC 10A (UMA)
APL5930 +V1P24A
9 1.24V
PWR_1P15V_PG TDC 0.5A
EN
4 (GPU) 3D3V_VGA_S0
VCC3 P-MOS
IC 3.3V
3.3V VCC3 AO3413L TDC
SLP_S3_N TPS22966 TDC
8 9
RT8243A V_3P3_A
SB3V (UMA)
PWM 3.3V
IC +V1P5S
SB3V_5V_PG 3.3V
APL5930
+DCBATOUT_RT8243_1 EN TDC 4.3A TPS22966 SLP_S3_N 1.5V
TDC EN
6 TDC 0.5A
C 1 V_5P0_A 8 C
VCC
5V
IC
TDC 6A SLP_S3_N 5V
TPS22966 TDC
8
SB5V
SB3V_5V_PG
IC
(UMA) +VNN 5V
TPS22966 TDC
1.0V
6
TDC 3.5A

2 RT8068A (UMA)
1D8V_S0
(UMA) +V1P8A N-MOS
RT8237C +V1P05A +V3P3S_PWRGD 1.8V
PWM PWR_V1P24A_PG 1.8V AO3418 TDC
1.05V EN TDC 2A
EUP_EN# EN TDC 6A 5 9

2 RT8068A (UMA) +V1P15A (GPU) 1D35V_VGA_S0

APL5912
PWM 1.15V GPU_CORE_PWROK 1.35V
NCP1589A VCC12
PWR_1P05V_PG TDC 1A EN TDC
B
PWM 12V
EN B

SIO_PSON_N TDC 2A 10
EN
3 (GPU) 1D8V_VGA_S0
N-MOS
1.8V
GPU_CORE_PWROK AO6402A TDC
RT6220A 0D95V_S5 (GPU) 0D95V_VGA_S0
N-MOS
PWM 0.95V 0.95V
10
TDC 4.3A GPU_CORE_PWROK AO4468L TDC
PWR_1P05V_PG EN
10
3
RT8207M (UMA) +VDDQ
PWM 1.35V
SLP_S4_N EN TDC 7.3A

7 (UMA) MEM_VTT
0.675V
VCC0_PG EN TDC 1A

A 10 A

ISL62882C (GPU) VGA_CORE <Variant Name>

PWM 1.00V Wistron Incorporated
3D3V_VGA_S0 EN TDC 28A 21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
9 Power Block Diagram
Size Document Number Rev
Custom Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 103 of 105
5 4 3 2 1
 5 4 3 2 1

Braswell SoC SIO - IT8617E

D

Battery 1 PMC_RSMRST# 10 RSMRST# PANSWH# 3 Power Button

D

RTC_RST# RSMRST_N PWRBTN_N

RTC_VCC
PMC_PWRBTN# 11 PWRON# 5VSB_CTRL# 4
SW_ON_N_SIO SIO_EUP_EN#
Codec 20
RESET# HDA_RST# PMC_SLP_S4# 12 SUSC# SYS_3VSB 9
AZ_RST_N_M SLP_S4_N SB3V
13 PMC_SLP_S3# 14 SUSB# ATXPG 15
DDR3_DRAM_PWROK DDR3 DRAM PWROK SLP_S3_N VCC3
18 19 LRESET#
PMC_CORE_PWROK PMC_PLTRST# PLTRST_N
SYS_PWRGD GPU
PCIRST3# 20 Giga LAN
18 15 PSON# PCIRST3#
DDR3_VCCA_PWROK SIO_PSON_N WirelessCard
SYS_PWRGD 17
PWROK1
PWRGD_3V
C C

2 V_5P0_A 4 VNN 5 1D15V_S5 7 1D8V_S5 8 SB5V

DCBATOUT SIO_EUP_EN# PWR_1P05V_PG PWR_V1P24A_PG SB3V_5V_PG

V_3P3_A 1D05V_S5 6 1D24V_S5 SB3V

PWR_1P15V_PG

12 14 15 16 14
DDR_VDDQ 1D5V_S0 VCC0 DDR_0D675V

AND
B
SLP_S4_N SLP_S3_N VGG_PG VCC0_PG SLP_S3_N 18 B

17 SYS_PWRGD
PWRGD_3V
VCC3 VCC1 15 1D8V_S0
VCC3

VCC 15 VCC12
SIO_PSON_N

VGG
15 3D3V_VGA_S0 16 VGA_CORE 17 0D95V_VGA_S0
VCC3 3D3V_VGA_S0 GPU_CORE_PWROK

A
1D8V_VGA_S0 A

1D35V_VGA_S0
For GPU SKU <Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
Power Good & Reset Diagram
Size Document Number Rev
D Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 104 of 105
5 4 3 2 1
 5 4 3 2 1

Braswell SoC
DDR3_M0_CK_0(BD40) CK_M_DDR0_A_DP/CK_M_DDR0_A_DN
DDR3_M0_CK_0#(BF40)
DDR3_M0_CK_1(BD38) CK_M_DDR1_A_DP/CK_M_DDR1_A_DN DDR3L SODIMM
DDR3_M0_CK_1#(BF38)

DDR3_M1_CK_0(BD14)
D D
DDR3_M1_CK_0#(BF14)
DDR3_M1_CK_1(BD16)
DDR3_M1_CK_1#(BF16)

CLK_DIFF_P_0(A21) 100MHz GPU Mars LE(S3) 27MHz

CLK_DIFF_N_0(C21)

CLK_DIFF_P_1(C19)
CLK_DIFF_N_1(B20)

CLK_DIFF_P_2(C18) 100MHz
CLK_DIFF_N_2(B18) NGFF WLAN+BT

CLK_DIFF_P_3(C17) 100MHz
C CLK_DIFF_N_3(A17) LAN RTL8111H 25MHz C

CLK_DIFF_P_4(C16)
CLK_DIFF_N_4(B16)
SIO IT8617E 48MHz
25MHz
MF_LPC_CLKOUT0(P2) PCICLK(22) CLKIN(24)

25MHz
MF_LPC_CLKOUT1(R3) LPC Debug Port

20MHz/33MHz/50MHz
FST_SPI_CLK(W3) SPI ROM(1.8V)
24MHz
MF_HDA_CLK(AD9) AUDIO ALC3600
B B

ICLKICOMP(P20)
ICLKRCOMP(N20) Rs
OSCIN(P24)

19.2MHz
OSCOUT(M22)

BRTCX1_PAD(M18)

32.768KHz
BRTCX2_PAD(K18)

A A

<Variant Name>

Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
Clock Diagram
Size Document Number Rev
C Rosa_Lily SFF -1
Date: Tuesday, June 23, 2015 Sheet 105 of 105
5 4 3 2 1