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5 4 3 2 1

Schematic Block Diagram

VRAM GDDR5 PANEL


GDDR5 nVIDIA IFPD MUX  17" FHD/UHD
dGPU PS8331B EDP Lanes x4
PAGE 64‐67 GSYNC
N17E-GX PAGE 30 PAGE 31

D D

Re‐driver PAGE 52‐‐68

HDMI2.0 PI3HDX1204B IFPC Re‐driver


HDMI CONN, IFPA,DP1.3 PI3DPX1203 DP Lanes x4
PAGE 35 PAGE 34
PEG0 Gen3 16X DISPLAY PORT
DP1.3 & DP++ PAGE 33
eDP PAGE 32
INTEL Processor 
   Skylake‐H Re‐driver
IFPE PS8330B DDI
    4+4e/4+2 DP1.2 PAGE 36
TYPE‐C TYPE‐C CONN,
TPS65982 PAGE 40
BGA INTEL  PAGE 40
Re‐driver AR DP
DDR4 DIMM X4 DDR4 2133 MT/S IFPF PS8330B DDI
PAGE 12~16 42X28mm
DUAL CHANNEL 2 DIMM PAGE 2‐‐9 DP1.2 PAGE 37

DMI X4
 8GB/S USB3.1
PAGE 38‐39 USB CONN,1
PCIE 4X  PORT1 PAGE 41

Card Reader PCIE 1X  PORT6


Bayhub OZ620FJ1LN
C
USB3.0  PORT3 USB Conn,2 C

USB2.0  PORT2 W/ CHARGER


PAGE 41

PCIE 1X  PORT7
NGFF WLAN USB2.0  PORT3
2230 Conn, HD CAMERA PAGE 31
(TYPE E) USB2.0  PORT5 INTEL SKYLAKE        
WLAN/BT PAGE 42      PCH‐H USB2.0  PORT9 FPR Conn
PAGE 46
LAN
Killer PCIE 1X  PORT8
E2400-RIVL-RL USB2.0  PORT4
PAGE 27
Keyboard PAGE 48

FCBGA
NGFF SSD 1
2280 Conn, PCIE 4X  PORT13 23X23mm
(TYPE M) USB2.0  PORT1
PAGE 43
USB3.0 Conn,
USB3.0  PORT1 JUSB3
PAGE 17‐‐25
NGFF SSD 2 USB2.0  PORT6
2280 Conn, PCIE 4X  PORT9 USB3.0 Conn,
USB3.0  PORT6 JUSB4
B (TYPE M) B

PAGE 43

HP/MIC COMBO JACK


2.5" SATA HDD/SSD SATA Redriver SATA PORT4
PS8527C MIC JACK
PAGE 44 PAGE42
HDA CODEC 
ALC3268
SPI PAGE28
SPI BIOS DMIC IO DB
SMART AMP
SMBUS TAS5766DCA SPEAKER CONN,
TOUCH PAD PAGE 46 PS2 PAGE29
SENSOR DB
AMP
SMBUS I2C LPC TPA3113D2PWPR Subwoofer CONN,
PAGE29
LC I2C
IT8376VG/CX
PAGE 47 I2C
PWM FAN
EC
TURBO button IT8376VG/CX SMBUS
A
PAGE 26 Battery PAGE 73
A

THERMAL SENSOR LENOVO.CRDN
PAGE 44 Title
LID switch Block Diagram
I2C Size Document Number
IR sensors   TMP006A Custom Skylake-H
Rev V0.3
SMbus PAGE 45
Date: Thursday, May 26, 2016 Sheet 1 of 99
"PROPERTY NOTE: this document contains information confidential and
LED  Int KBD Debug 80 Port Debug Card property to LENOVO PND and shall not be reproduced or transferred to other documents
PAGE 51 PAGE 51 or disclosed to others or used for any purpose other than that for which it was
RGB sensor CS5032 obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

D D

? SKYLAKE_HALO
PCIE Reversed BGA1440
U1C
PCIE Reversed
PEG_PRX_GTX_P15 E25 B25 PEG_PTX_GRX_P15 C1 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_P15
PEG_PRX_GTX_N15 D25 PEG_RXP[0] PEG_TXP[0] A25 PEG_PTX_GRX_N15 C2 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_N15
PEG_RXN[0] PEG_TXN[0]
PEG_PRX_GTX_P14 E24 B24 PEG_PTX_GRX_P14 C3 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_P14
PEG_PRX_GTX_N14 F24 PEG_RXP[1] PEG_TXP[1] C24 PEG_PTX_GRX_N14 C4 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_N14
PEG_RXN[1] PEG_TXN[1]
PEG_PRX_GTX_P13 E23 B23 PEG_PTX_GRX_P13 C5 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_P13
PEG_PRX_GTX_N13 D23 PEG_RXP[2] PEG_TXP[2] A23 PEG_PTX_GRX_N13 C6 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_N13
PEG_RXN[2] PEG_TXN[2]
PEG_PRX_GTX_P12 E22 B22 PEG_PTX_GRX_P12 C7 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_P12
PEG_PRX_GTX_N12 F22 PEG_RXP[3] PEG_TXP[3] C22 PEG_PTX_GRX_N12 C8 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_N12
PEG_RXN[3] PEG_TXN[3]
C C
PEG_PRX_GTX_P11 E21 B21 PEG_PTX_GRX_P11 C9 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_P11
PEG_PRX_GTX_N11 D21 PEG_RXP[4] PEG_TXP[4] A21 PEG_PTX_GRX_N11 C10 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_N11
PEG_RXN[4] PEG_TXN[4]
PEG_PRX_GTX_P10 E20 B20 PEG_PTX_GRX_P10 C11 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_P10
PEG_PRX_GTX_N10 F20 PEG_RXP[5] PEG_TXP[5] C20 PEG_PTX_GRX_N10 C12 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_N10
PEG_RXN[5] PEG_TXN[5]
PEG_PRX_GTX_P9 E19 B19 PEG_PTX_GRX_P9 C13 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_P9
PEG_PRX_GTX_N9 D19 PEG_RXP[6] PEG_TXP[6] A19 PEG_PTX_GRX_N9 C14 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_N9
PEG_RXN[6] PEG_TXN[6] PEG_PRX_GTX_N[0..15] 52
PEG_PRX_GTX_P8 E18 B18 PEG_PTX_GRX_P8 C15 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_P8
PEG_PRX_GTX_N8 PEG_RXP[7] PEG_TXP[7] PEG_PTX_GRX_N8 PEG_PTX_C_GRX_N8 PEG_PRX_GTX_P[0..15] 52
dGPU PEG F18
PEG_RXN[7] PEG_TXN[7]
C18 C16 2 1 0.22U_0402_10V6K
dGPU PEG
PEG_PRX_GTX_P7 D17 A17 PEG_PTX_GRX_P7 C17 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_P7
PEG_PRX_GTX_N7 PEG_RXP[8] PEG_TXP[8] PEG_PTX_GRX_N7 PEG_PTX_C_GRX_N7 PEG_PTX_C_GRX_N[0..15] 52
E17 B17 C18 2 1 0.22U_0402_10V6K
PEG_RXN[8] PEG_TXN[8]
PEG_PRX_GTX_P6 PEG_PTX_GRX_P6 PEG_PTX_C_GRX_P6 PEG_PTX_C_GRX_P[0..15] 52
F16 C16 C19 2 1 0.22U_0402_10V6K
PEG_PRX_GTX_N6 E16 PEG_RXP[9] PEG_TXP[9] B16 PEG_PTX_GRX_N6 C20 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_N6
PEG_RXN[9] PEG_TXN[9]
PEG_PRX_GTX_P5 D15 A15 PEG_PTX_GRX_P5 C21 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_P5
PEG_PRX_GTX_N5 E15 PEG_RXP[10] PEG_TXP[10] B15 PEG_PTX_GRX_N5 C22 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_N5
PEG_RXN[10] PEG_TXN[10]
PEG_PRX_GTX_P4 F14 C14 PEG_PTX_GRX_P4 C23 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_P4
PEG_PRX_GTX_N4 E14 PEG_RXP[11] PEG_TXP[11] B14 PEG_PTX_GRX_N4 C24 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_N4
PEG_RXN[11] PEG_TXN[11]
PEG_PRX_GTX_P3 D13 A13 PEG_PTX_GRX_P3 C25 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_P3
PEG_PRX_GTX_N3 E13 PEG_RXP[12] PEG_TXP[12] B13 PEG_PTX_GRX_N3 C26 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_N3
PEG_RXN[12] PEG_TXN[12]
PEG_PRX_GTX_P2 F12 C12 PEG_PTX_GRX_P2 C27 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_P2
PEG_PRX_GTX_N2 E12 PEG_RXP[13] PEG_TXP[13] B12 PEG_PTX_GRX_N2 C28 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_N2
PEG_RXN[13] PEG_TXN[13]
PEG_PRX_GTX_P1 D11 A11 PEG_PTX_GRX_P1 C29 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_P1
PEG_PRX_GTX_N1 E11 PEG_RXP[14] PEG_TXP[14] B11 PEG_PTX_GRX_N1 C30 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_N1
PEG_RXN[14] PEG_TXN[14]
PEG_PRX_GTX_P0 F10 C10 PEG_PTX_GRX_P0 C31 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_P0
PEG_PRX_GTX_N0 E10 PEG_RXP[15] PEG_TXP[15] B10 PEG_PTX_GRX_N0 C32 2 1 0.22U_0402_10V6K PEG_PTX_C_GRX_N0
PEG_RXN[15] PEG_TXN[15]
BRD Note: +VCCIO
B W=12mils;S=15mils;L<=400mils R1 1 2 24.9_0402_1% PEG_RCOMP G2 B
PEG_RCOMP

D8 B8
18 DMI_IT_MR_0_DP DMI_RXP[0] DMI_TXP[0] DMI_MT_IR_0_DP 18
E8 A8
18 DMI_IT_MR_0_DN DMI_RXN[0] DMI_TXN[0] DMI_MT_IR_0_DN 18
E6 C6
18 DMI_IT_MR_1_DP DMI_RXP[1] DMI_TXP[1] DMI_MT_IR_1_DP 18
F6 B6
18 DMI_IT_MR_1_DN DMI_RXN[1] DMI_TXN[1] DMI_MT_IR_1_DN 18
D5 B5
18 DMI_IT_MR_2_DP DMI_RXP[2] DMI_TXP[2] DMI_MT_IR_2_DP 18
E5 A5
18 DMI_IT_MR_2_DN DMI_RXN[2] DMI_TXN[2] DMI_MT_IR_2_DN 18
J8 D4
18 DMI_IT_MR_3_DP DMI_RXP[3] DMI_TXP[3] DMI_MT_IR_3_DP 18
J9 B4
18 DMI_IT_MR_3_DN DMI_RXN[3] DMI_TXN[3] DMI_MT_IR_3_DN 18

3 OF 14 ?
SKL_H_BGA_BGA REV = 1

A A

LENOVO.CRDN
Title
PROCESSOR-PEG/DMI
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 2 of 99
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

D D

? SKYLAKE_HALO
U1D
BGA1440
30 CPU_DPB_TX0_DP K36 D29
K37 DDI1_TXP[0] EDP_TXP[0] E29
30 CPU_DPB_TX0_DN DDI1_TXN[0] EDP_TXN[0]
30 CPU_DPB_TX1_DP J35 F28
J34 DDI1_TXP[1] EDP_TXP[1] E28
30 CPU_DPB_TX1_DN DDI1_TXN[1] EDP_TXN[1]
30 CPU_DPB_TX2_DP H37 B29
H36 DDI1_TXP[2] EDP_TXN[2] A29
30 CPU_DPB_TX2_DN DDI1_TXN[2] EDP_TXP[2]
DDI B TO DP PORT, FOR DEBUG 30
30
CPU_DPB_TX3_DP
CPU_DPB_TX3_DN
J37
J38 DDI1_TXP[3]
DDI1_TXN[3]
EDP_TXN[3]
EDP_TXP[3]
B28
C28

30 CPU_DPB_AUX_DP D27 C26


E27 DDI1_AUXP EDP_AUXP B26
30 CPU_DPB_AUX_DN DDI1_AUXN EDP_AUXN
H34
H33 DDI2_TXP[0]
F37 DDI2_TXN[0] A33 EDP_UTIL 1 TP1
G38 DDI2_TXP[1] EDP_DISP_UTIL +VCCIO
C C
F34 DDI2_TXN[1]
F35 DDI2_TXP[2] D37 EDP_RCOMP R2 1 2 24.9_0402_1%
E37 DDI2_TXN[2] EDP_RCOMP
DDI2_TXP[3]
E36
DDI2_TXN[3] BRD Note:
F26
W=20mils;S=25mils;L<=100mils
E26 DDI2_AUXP
DDI2_AUXN
C34
D34 DDI3_TXP[0]
B36 DDI3_TXN[0]
B34 DDI3_TXP[1]
F33 DDI3_TXN[1]
DDI3_TXP[2]
E33
DDI3_TXN[2] CAD Note:
C33
B33 DDI3_TXP[3] Integrated Codec for DP/HDMI
DDI3_TXN[3] G27 AUD_AZACPU_SCLK R2291 1 2 2K_0402_1%
A27 PROC_AUDIO_CLK G25 AUD_AZACPU_SDO R2292 1 2 2K_0402_1%
B27 DDI3_AUXP PROC_AUDIO_SDI G29
DDI3_AUXN PROC_AUDIO_SDO

4 OF 14 ?
SKL_H_BGA_BGA REV = 1

B B

A A

LENOVO.CRDN
Title
Processor--eDP/TBT/DP
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 3 of 99
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

D D

?
SKYLAKE_HALO
U1A
BGA1440
AG1 BR6 M_A_DQ0
12 M_A_DIM0_CK_DDR0_DP DDR0_CKP[0] DDR0_DQ[0] M_A_DQ1 M_A_DQ0 12,13
AG2 BT6
12 M_A_DIM0_CK_DDR0_DN DDR0_CKN[0] DDR0_DQ[1] M_A_DQ2 M_A_DQ1 12,13
AK1 BP3
12 M_A_DIM0_CK_DDR1_DN DDR0_CKN[1] DDR0_DQ[2] M_A_DQ3 M_A_DQ2 12,13
AK2 BR3
12 M_A_DIM0_CK_DDR1_DP DDR0_CKP[1] DDR0_DQ[3] M_A_DQ4 M_A_DQ3 12,13
AL3 BN5
13 M_A_DIM1_CK_DDR2_DP DDR0_CLKP[2] DDR0_DQ[4] M_A_DQ5 M_A_DQ4 12,13
AK3 BP6
13 M_A_DIM1_CK_DDR2_DN DDR0_CLKN[2] DDR0_DQ[5] M_A_DQ6 M_A_DQ5 12,13
AL2 BP2
13 M_A_DIM1_CK_DDR3_DP DDR0_CLKP[3] DDR0_DQ[6] M_A_DQ7 M_A_DQ6 12,13
AL1 BN3
13 M_A_DIM1_CK_DDR3_DN DDR0_CLKN[3] DDR0_DQ[7] M_A_DQ8 M_A_DQ7 12,13
BL4
DDR0_DQ[8] M_A_DQ9 M_A_DQ8 12,13
AT1 BL5
12 M_A_DIM0_CKE0 DDR0_CKE[0] DDR0_DQ[9] M_A_DQ10 M_A_DQ9 12,13
AT2 BL2
12 M_A_DIM0_CKE1 DDR0_CKE[1] DDR0_DQ[10] M_A_DQ11 M_A_DQ10 12,13
AT3 BM1
13 M_A_DIM1_CKE2 DDR0_CKE[2] DDR0_DQ[11] M_A_DQ12 M_A_DQ11 12,13
AT5 BK4
13 M_A_DIM1_CKE3 DDR0_CKE[3] DDR0_DQ[12] M_A_DQ13 M_A_DQ12 12,13
BK5
DDR0_DQ[13] M_A_DQ14 M_A_DQ13 12,13
AD5 BK1
12 M_A_DIM0_CS0_N DDR0_CS#[0] DDR0_DQ[14] M_A_DQ15 M_A_DQ14 12,13
AE2 BK2
12 M_A_DIM0_CS1_N DDR0_CS#[1] DDR0_DQ[15] M_A_DQ16 M_A_DQ15 12,13
AD2 BG4
13 M_A_DIM1_CS2_N DDR0_CS#[2] DDR0_DQ[16]/DDR0_DQ[32] M_A_DQ17 M_A_DQ16 12,13
AE5 BG5
13 M_A_DIM1_CS3_N DDR0_CS#[3] DDR0_DQ[17]/DDR0_DQ[33] M_A_DQ18 M_A_DQ17 12,13
BF4
DDR0_DQ[18]/DDR0_DQ[34] M_A_DQ19 M_A_DQ18 12,13
AD3 BF5
12 M_A_DIM0_ODT0 DDR0_ODT[0] DDR0_DQ[19]/DDR0_DQ[35] M_A_DQ20 M_A_DQ19 12,13
AE4 BG2
12 M_A_DIM0_ODT1 DDR0_ODT[1] DDR0_DQ[20]/DDR0_DQ[36] M_A_DQ21 M_A_DQ20 12,13
AE1 BG1
13 M_A_DIM1_ODT2 DDR0_ODT[2] DDR0_DQ[21]/DDR0_DQ[37] M_A_DQ22 M_A_DQ21 12,13
C AD4 BF1 C
13 M_A_DIM1_ODT3 DDR0_ODT[3] DDR0_DQ[22]/DDR0_DQ[38] M_A_DQ23 M_A_DQ22 12,13
BF2
DDR0_DQ[23]/DDR0_DQ[39] M_A_DQ24 M_A_DQ23 12,13
AH5 BD2
12,13 M_A_BA0 DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR0_DQ[24]/DDR0_DQ[40] M_A_DQ25 M_A_DQ24 12,13
AH1 BD1
12,13 M_A_BA1 DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_DQ[25]/DDR0_DQ[41] M_A_DQ26 M_A_DQ25 12,13
AU1 BC4
12,13 M_A_BG0 DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_DQ[26]/DDR0_DQ[42] M_A_DQ27 M_A_DQ26 12,13
BC5
DDR0_DQ[27]/DDR0_DQ[43] M_A_DQ28 M_A_DQ27 12,13
AH4 BD5
12,13 M_A_A16_RAS_N DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR0_DQ[28]/DDR0_DQ[44] M_A_DQ29 M_A_DQ28 12,13
AG4 BD4
12,13 M_A_A14_WE_N DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR0_DQ[29]/DDR0_DQ[45] M_A_DQ30 M_A_DQ29 12,13
AD1 BC1
12,13 M_A_A15_CAS_N DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR0_DQ[30]/DDR0_DQ[46] M_A_DQ31 M_A_DQ30 12,13
BC2
DDR0_DQ[31]/DDR0_DQ[47] M_A_DQ32 M_A_DQ31 12,13
AH3 AB1
12,13 M_A_A0 DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR0_DQ[32]/DDR1_DQ[0] M_A_DQ33 M_A_DQ32 12,13
AP4 AB2
12,13 M_A_A1 DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_DQ[33]/DDR1_DQ[1] M_A_DQ34 M_A_DQ33 12,13
AN4 AA4
12,13 M_A_A2 DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDR0_DQ[34]/DDR1_DQ[2] M_A_DQ35 M_A_DQ34 12,13
AP5 AA5
12,13 M_A_A3 DDR0_MA[3] DDR0_DQ[35]/DDR1_DQ[3] M_A_DQ36 M_A_DQ35 12,13
AP2 AB5
12,13 M_A_A4 DDR0_MA[4] DDR0_DQ[36]/DDR1_DQ[4] M_A_DQ37 M_A_DQ36 12,13
AP1 AB4
12,13 M_A_A5 DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_DQ[37]/DDR1_DQ[5] M_A_DQ38 M_A_DQ37 12,13
AP3 AA2
12,13 M_A_A6 DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_DQ[38]/DDR1_DQ[6] M_A_DQ39 M_A_DQ38 12,13
AN1 AA1
12,13 M_A_A7 DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR0_DQ[39]/DDR1_DQ[7] M_A_DQ40 M_A_DQ39 12,13
AN3 V5
12,13 M_A_A8 DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_DQ[40]/DDR1_DQ[8] M_A_DQ41 M_A_DQ40 12,13
AT4 V2
12,13 M_A_A9 DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_DQ[41]/DDR1_DQ[9] M_A_DQ42 M_A_DQ41 12,13
AH2 U1
12,13 M_A_A10_AP DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR0_DQ[42]/DDR1_DQ[10] M_A_DQ43 M_A_DQ42 12,13
AN2 U2
12,13 M_A_A11 DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR0_DQ[43]/DDR1_DQ[11] M_A_DQ44 M_A_DQ43 12,13
AU4 V1
12,13 M_A_A12 DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_DQ[44]/DDR1_DQ[12] M_A_DQ45 M_A_DQ44 12,13
AE3 V4
12,13 M_A_A13 DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR0_DQ[45]/DDR1_DQ[13] M_A_DQ46 M_A_DQ45 12,13
AU2 U5
12,13 M_A_BG1 DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR0_DQ[46]/DDR1_DQ[14] M_A_DQ47 M_A_DQ46 12,13
AU3 U4
12,13 M_A_ACT_N DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_DQ[47]/DDR1_DQ[15] M_A_DQ48 M_A_DQ47 12,13
R2
DDR0_DQ[48]/DDR1_DQ[32] M_A_DQ49 M_A_DQ48 12,13
AG3 P5
12,13 DDR0_A_PARITY DDR0_PAR DDR0_DQ[49]/DDR1_DQ[33] M_A_DQ50 M_A_DQ49 12,13
AU5 R4
12,13 DDR0_A_ALERT_N DDR0_ALERT# DDR0_DQ[50]/DDR1_DQ[34] M_A_DQ51 M_A_DQ50 12,13
P4
DDR0_DQ[51]/DDR1_DQ[35] M_A_DQ52 M_A_DQ51 12,13
R5
DDR0_DQ[52]/DDR1_DQ[36] M_A_DQ53 M_A_DQ52 12,13
BR5 P2
12,13 M_A_DQS_DN0 DDR0_DQSN[0] DDR0_DQ[53]/DDR1_DQ[37] M_A_DQ54 M_A_DQ53 12,13
BL3 R1
12,13 M_A_DQS_DN1 DDR0_DQSN[1] DDR0_DQ[54]/DDR1_DQ[38] M_A_DQ55 M_A_DQ54 12,13
BG3 P1
12,13 M_A_DQS_DN2 DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQ[55]/DDR1_DQ[39] M_A_DQ56 M_A_DQ55 12,13
BD3 M4
12,13 M_A_DQS_DN3 DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQ[56]/DDR1_DQ[40] M_A_DQ57 M_A_DQ56 12,13
AB3 M1
12,13 M_A_DQS_DP4 DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQ[57]/DDR1_DQ[41] M_A_DQ58 M_A_DQ57 12,13
V3 L4
12,13 M_A_DQS_DP5 DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQ[58]/DDR1_DQ[42] M_A_DQ59 M_A_DQ58 12,13
R3 L2
B 12,13 M_A_DQS_DP6 DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQ[59]/DDR1_DQ[43] M_A_DQ60 M_A_DQ59 12,13 B
M3 M5
12,13 M_A_DQS_DP7 DDR0_DQSP[7]/DDR1_DQSP[5] DDR0_DQ[60]/DDR1_DQ[44] M_A_DQ61 M_A_DQ60 12,13
M2
DDR0_DQ[61]/DDR1_DQ[45] M_A_DQ62 M_A_DQ61 12,13
BP5 L5
12,13 M_A_DQS_DP0 DDR0_DQSP[0] DDR0_DQ[62]/DDR1_DQ[46] M_A_DQ63 M_A_DQ62 12,13
BK3 L1
12,13 M_A_DQS_DP1 DDR0_DQSP[1] DDR0_DQ[63]/DDR1_DQ[47] M_A_DQ63 12,13
BF3
12,13 M_A_DQS_DP2 DDR0_DQSP[2]/DDR0_DQSP[4]
BC3 BA2
12,13 M_A_DQS_DP3 DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_ECC[0]
AA3 BA1
12,13 M_A_DQS_DN4 DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_ECC[1]
U3 AY4
12,13 M_A_DQS_DN5 DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_ECC[2]
P3 AY5
12,13 M_A_DQS_DN6 DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_ECC[3]
L3 BA5
12,13 M_A_DQS_DN7 DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_ECC[4] BA4
AY3 DDR0_ECC[5] AY1
BA3 DDR0_DQSP[8] DDR0_ECC[6] AY2
DDR0_DQSN[8] DDR0_ECC[7]

DDR CHANNEL A

1 OF 14
SKL_H_BGA_BGA
? REV = 1

A A

LENOVO.CRDN
Title
PROCESSOR-MEM_CH A
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 4 of 99
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

D D

?SKYLAKE_HALO
U1B
BGA1440
AM9 BT11 M_B_DQ0
14 M_B_DIM0_CK_DDR0_DP DDR1_CKP[0] DDR1_DQ[0]/DDR0_DQ[16] M_B_DQ1 M_B_DQ0 14,15
AN9 BR11
14 M_B_DIM0_CK_DDR0_DN DDR1_CKN[0] DDR1_DQ[1]/DDR0_DQ[17] M_B_DQ2 M_B_DQ1 14,15
AM8 BT8
14 M_B_DIM0_CK_DDR1_DN DDR1_CKN[1] DDR1_DQ[2]/DDR0_DQ[18] M_B_DQ3 M_B_DQ2 14,15
AM7 BR8
14 M_B_DIM0_CK_DDR1_DP DDR1_CKP[1] DDR1_DQ[3]/DDR0_DQ[19] M_B_DQ4 M_B_DQ3 14,15
AM11 BP11
15 M_B_DIM1_CK_DDR2_DP DDR1_CLKP[2] DDR1_DQ[4]/DDR0_DQ[20] M_B_DQ5 M_B_DQ4 14,15
AM10 BN11
15 M_B_DIM1_CK_DDR2_DN DDR1_CLKN[2] DDR1_DQ[5]/DDR0_DQ[21] M_B_DQ6 M_B_DQ5 14,15
AJ10 BP8
15 M_B_DIM1_CK_DDR3_DP DDR1_CLKP[3] DDR1_DQ[6]/DDR0_DQ[22] M_B_DQ7 M_B_DQ6 14,15
AJ11 BN8
15 M_B_DIM1_CK_DDR3_DN DDR1_CLKN[3] DDR1_DQ[7]/DDR0_DQ[23] M_B_DQ8 M_B_DQ7 14,15
BL12
DDR1_DQ[8]/DDR0_DQ[24] M_B_DQ9 M_B_DQ8 14,15
AT8 BL11
14 M_B_DIM0_CKE0 DDR1_CKE[0] DDR1_DQ[9]/DDR0_DQ[25] M_B_DQ10 M_B_DQ9 14,15
AT10 BL8
14 M_B_DIM0_CKE1 DDR1_CKE[1] DDR1_DQ[10]/DDR0_DQ[26] M_B_DQ11 M_B_DQ10 14,15
AT7 BJ8
15 M_B_DIM1_CKE2 DDR1_CKE[2] DDR1_DQ[11]/DDR0_DQ[27] M_B_DQ12 M_B_DQ11 14,15
AT11 BJ11
15 M_B_DIM1_CKE3 DDR1_CKE[3] DDR1_DQ[12]/DDR0_DQ[28] M_B_DQ13 M_B_DQ12 14,15
BJ10
DDR1_DQ[13]/DDR0_DQ[29] M_B_DQ14 M_B_DQ13 14,15
AF11 BL7
14 M_B_DIM0_CS0_N DDR1_CS#[0] DDR1_DQ[14]/DDR0_DQ[30] M_B_DQ15 M_B_DQ14 14,15
AE7 BJ7
14 M_B_DIM0_CS1_N DDR1_CS#[1] DDR1_DQ[15]/DDR0_DQ[31] M_B_DQ16 M_B_DQ15 14,15
AF10 BG11
15 M_B_DIM1_CS2_N DDR1_CS#[2] DDR1_DQ[16]/DDR0_DQ[48] M_B_DQ17 M_B_DQ16 14,15
AE10 BG10
15 M_B_DIM1_CS3_N DDR1_CS#[3] DDR1_DQ[17]/DDR0_DQ[49] M_B_DQ18 M_B_DQ17 14,15
BG8
DDR1_DQ[18]/DDR0_DQ[50] M_B_DQ19 M_B_DQ18 14,15
AF7 BF8
14 M_B_DIM0_ODT0 DDR1_ODT[0] DDR1_DQ[19]/DDR0_DQ[51] M_B_DQ20 M_B_DQ19 14,15
AE8 BF11
14 M_B_DIM0_ODT1 DDR1_ODT[1] DDR1_DQ[20]/DDR0_DQ[52] M_B_DQ21 M_B_DQ20 14,15
AE9 BF10
15 M_B_DIM1_ODT2 DDR1_ODT[2] DDR1_DQ[21]/DDR0_DQ[53] M_B_DQ22 M_B_DQ21 14,15
AE11 BG7
15 M_B_DIM1_ODT3 DDR1_ODT[3] DDR1_DQ[22]/DDR0_DQ[54] M_B_DQ23 M_B_DQ22 14,15
BF7
DDR1_DQ[23]/DDR0_DQ[55] M_B_DQ24 M_B_DQ23 14,15
AH10 BB11
14,15 M_B_A16_RAS_N DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR1_DQ[24]/DDR0_DQ[56] M_B_DQ25 M_B_DQ24 14,15
AH11 BC11
14,15 M_B_A14_WE_N DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR1_DQ[25]/DDR0_DQ[57] M_B_DQ26 M_B_DQ25 14,15
AF8 BB8
14,15 M_B_A15_CAS_N DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR1_DQ[26]/DDR0_DQ[58] M_B_DQ27 M_B_DQ26 14,15
BC8
DDR1_DQ[27]/DDR0_DQ[59] M_B_DQ28 M_B_DQ27 14,15
AH8 BC10
14,15 M_B_BA0 DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR1_DQ[28]/DDR0_DQ[60] M_B_DQ29 M_B_DQ28 14,15
AH9 BB10
14,15 M_B_BA1 DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_DQ[29]/DDR0_DQ[61] M_B_DQ30 M_B_DQ29 14,15
AR9 BC7
14,15 M_B_BG0 DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_DQ[30]/DDR0_DQ[62] M_B_DQ31 M_B_DQ30 14,15
BB7
DDR1_DQ[31]/DDR0_DQ[63] M_B_DQ32 M_B_DQ31 14,15
AJ9 AA11
14,15 M_B_A0 DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR1_DQ[32]/DDR1_DQ[16] M_B_DQ33 M_B_DQ32 14,15
C AK6 AA10 C
14,15 M_B_A1 DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_DQ[33]/DDR1_DQ[17] M_B_DQ34 M_B_DQ33 14,15
AK5 AC11
14,15 M_B_A2 DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDR1_DQ[34]/DDR1_DQ[18] M_B_DQ35 M_B_DQ34 14,15
AL5 AC10
14,15 M_B_A3 DDR1_MA[3] DDR1_DQ[35]/DDR1_DQ[19] M_B_DQ36 M_B_DQ35 14,15
AL6 AA7
14,15 M_B_A4 DDR1_MA[4] DDR1_DQ[36]/DDR1_DQ[20] M_B_DQ37 M_B_DQ36 14,15
AM6 AA8
14,15 M_B_A5 DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_DQ[37]/DDR1_DQ[21] M_B_DQ38 M_B_DQ37 14,15
AN7 AC8
14,15 M_B_A6 DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_DQ[38]/DDR1_DQ[22] M_B_DQ39 M_B_DQ38 14,15
AN10 AC7
14,15 M_B_A7 DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR1_DQ[39]/DDR1_DQ[23] M_B_DQ40 M_B_DQ39 14,15
AN8 W8
14,15 M_B_A8 DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_DQ[40]/DDR1_DQ[24] M_B_DQ41 M_B_DQ40 14,15
AR11 W7
14,15 M_B_A9 DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_DQ[41]/DDR1_DQ[25] M_B_DQ42 M_B_DQ41 14,15
AH7 V10
14,15 M_B_A10_AP DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR1_DQ[42]/DDR1_DQ[26] M_B_DQ43 M_B_DQ42 14,15
AN11 V11
14,15 M_B_A11 DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDR1_DQ[43]/DDR1_DQ[27] M_B_DQ44 M_B_DQ43 14,15
AR10 W11
14,15 M_B_A12 DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_DQ[44]/DDR1_DQ[28] M_B_DQ45 M_B_DQ44 14,15
AF9 W10
14,15 M_B_A13 DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDR1_DQ[45]/DDR1_DQ[29] M_B_DQ46 M_B_DQ45 14,15
AR7 V7
14,15 M_B_BG1 DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR1_DQ[46]/DDR1_DQ[30] M_B_DQ47 M_B_DQ46 14,15
AT9 V8
14,15 M_B_ACT_N DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_DQ[47]/DDR1_DQ[31] M_B_DQ48 M_B_DQ47 14,15
R11
DDR1_DQ[48] M_B_DQ49 M_B_DQ48 14,15
AJ7 P11
14,15 DDR1_B_PARITY DDR1_PAR DDR1_DQ[49] M_B_DQ50 M_B_DQ49 14,15
AR8 P7
14,15 DDR1_B_ALERT_N DDR1_ALERT# DDR1_DQ[50] M_B_DQ51 M_B_DQ50 14,15
R8
DDR1_DQ[51] M_B_DQ52 M_B_DQ51 14,15
R10
DDR1_DQ[52] M_B_DQ53 M_B_DQ52 14,15
BP9 P10
14,15 M_B_DQS_DN0 DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQ[53] M_B_DQ54 M_B_DQ53 14,15
BL9 R7
14,15 M_B_DQS_DN1 DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQ[54] M_B_DQ55 M_B_DQ54 14,15
BG9 P8
14,15 M_B_DQS_DN2 DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQ[55] M_B_DQ56 M_B_DQ55 14,15
BC9 L11
14,15 M_B_DQS_DN3 DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQ[56] M_B_DQ57 M_B_DQ56 14,15
AC9 M11
14,15 M_B_DQS_DN4 DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQ[57] M_B_DQ58 M_B_DQ57 14,15
W9 L7
14,15 M_B_DQS_DN5 DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQ[58] M_B_DQ59 M_B_DQ58 14,15
R9 M8
14,15 M_B_DQS_DN6 DDR1_DQSN[6] DDR1_DQ[59] M_B_DQ60 M_B_DQ59 14,15
M9 L10
14,15 M_B_DQS_DN7 DDR1_DQSN[7] DDR1_DQ[60] M_B_DQ61 M_B_DQ60 14,15
M10
DDR1_DQ[61] M_B_DQ62 M_B_DQ61 14,15
BR9 M7
14,15 M_B_DQS_DP0 DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQ[62] M_B_DQ63 M_B_DQ62 14,15
BJ9 L8
14,15 M_B_DQS_DP1 DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQ[63] M_B_DQ63 14,15
BF9
14,15 M_B_DQS_DP2 DDR1_DQSP[2]/DDR0_DQSP[6]
BB9 AW11
14,15 M_B_DQS_DP3 DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_ECC[0]
AA9 AY11
14,15 M_B_DQS_DP4 DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_ECC[1]
V9 AY8
14,15 M_B_DQS_DP5 DDR1_DQSP[5]/DDR1_DQSP[3] DDR1_ECC[2]
P9 AW8
14,15 M_B_DQS_DP6 DDR1_DQSP[6] DDR1_ECC[3]
L9 AY10
14,15 M_B_DQS_DP7 DDR1_DQSP[7] DDR1_ECC[4] AW10
B
AW9 DDR1_ECC[5] AY7 B
AY9 DDR1_DQSP[8] DDR1_ECC[6] AW7
DDR1_DQSN[8] DDR1_ECC[7]

DDR CHANNEL B

BN13 G1 DDR_RCOMP0 R4 2 1 121_0402_1%


+V_CPU_VREF_CA DDR_VREF_CA DDR_RCOMP[0]
TP124 1 +V_CPU_VREF_DQ_CHA BP13 H1 DDR_RCOMP1 R5 2 1 75_0402_1% BRD Note:DDR_RCOMP*
BR13 DDR0_VREF_DQ DDR_RCOMP[1] J2 DDR_RCOMP2 R6 2 1 100_0402_1%
+V_CPU_VREF_DQ_CHB DDR1_VREF_DQ DDR_RCOMP[2] W=15mils;S=20mils;L<=500mils
SKL_H_BGA_BGA
? 2 OF 14 REV = 1

A A

LENOVO.CRDN
Title
PROCESSOR-MEM_CH B
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 5 of 99
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

+1.0V_VCCST PROCESSOR CFG STRAPS

2
R7 R8

100_0402_1%

56.2_0402_1%
CFG0 R10 2 @ 1 1K_0402_5%

1
BRD Note: SVID
S=18mils;Z=50ohm

D CPU_SVID_ALERT_N ? SKYLAKE_HALO D
R9 1 2 220_0402_5% U1E
83 CPU_SVIDALERT_N
BGA1440
Stall reset sequence after PCU
R46 1 2 0_0402_5% CPU_SVID_CLK B31 BN25 CFG0
83 CPU_SVIDCLK 22 CK_CPU_BCLK_P
22 CK_CPU_BCLK_N
A32 BCLKP
BCLKN
CFG[0]
CFG[1]
BN27 CFG1
CFG0 51
CFG1 51
PLL lock until de-asserted
R48 1 2 0_0402_5% CPU_SVID_DATA BN26 CFG2
83 CPU_SVIDDATA CFG[2] CFG2 51
22 CK_CPU_PCIBCLK_P
D35
PCI_BCLKP CFG[3]
BN28 CFG3
CFG3 51 1:Normal(Default)
22 CK_CPU_PCIBCLK_N
C36
PCI_BCLKN CFG[4]
CFG[5]
BR20
BM20
CFG4
CFG5
CFG4 51
CFG5 51
CFG0 *
22 CK_CPU_24M_P
22 CK_CPU_24M_N
E31
D31 CLK24P
CLK24N
CFG[6]
CFG[7]
BT20
BP20
CFG6
CFG7
CFG6 51
CFG7 51
0:Stall
BR23 CFG8
CFG[8] CFG8 51
BR22 CFG9
CFG[9] CFG9 51
+1.0V_VCCSTG BT23 CFG10
CFG[10] CFG10 51
BT22 CFG11
CFG[11] CFG11 51
BM19 CFG12
H_PROCHOT_N CFG[12] CFG12 51
R11 2 1 1K_0402_5% BR19 CFG13
CFG[13] CFG13 51
BP19 CFG14
CPU_SVID_ALERT_N CFG[14] CFG14 51
BH31 BT19 CFG15
CPU_SVID_CLK VIDALERT# CFG[15] CFG15 51
BH32
CPU_SVID_DATA BH29 VIDSCK BN23 CFG17 CFG2 R12 2 1 1K_0402_5%
+1.0V_VCCST VIDSOUT CFG[17] CFG17 51
R13 2 1 499_0402_1% H_PROCHOT_N_R BR30 BP23 CFG16
45 H_PROCHOT_N PROCHOT# CFG[16] CFG16 51
BP22 CFG19
H_VCCST_PWRGD DDR_VTT_PG_CTRL CFG[19] CFG19 51
R14 2 1 1K_0402_5% BT13 BN22 CFG18
50 DDR_VTT_PG_CTRL DDR_VTT_CNTL CFG[18] CFG18 51
R15 2 1 1K_0402_5% H_THRMTRIP_N BR27 XDP_BPM0_N
BPM#[0] XDP_BPM1_N XDP_BPM0_N 51
BT27
BPM#[1] XDP_BPM2_N 1 XDP_BPM1_N 51
BM31
50 H_VCCST_PWRGD
R17 1 2 60.4_0402_1% H_VCCST_PWRGD_R H13
VCCST_PWRGD
BPM#[2]
BPM#[3]
BT30 XDP_BPM3_N 1 TP2 PEG16x Static Lane Reversal Strap
TP3
H_PWRGD
19 H_PWRGD CPU_PLTRST_N
BT31
PROCPWRGD 1:Normal
20 CPU_PLTRST_N H_PM_SYNC
BP35
RESET# PROC_TDO
BT28
XDP_TDO 51 CFG2
20 H_PM_SYNC
BM34
PM_SYNC PROC_TDI
BL32
XDP_TDI 51 0:Reversed(Default)
20 H_PM_DOWN
20,26 H_PECI
R18 1 2 22_0402_5% H_PM_DOWN_R
H_PECI
H_THRMTRIP_N
BP31
BT34
J31
PM_DOWN
PECI
PROC_TMS
PROC_TCK
BP28
BR28
XDP_TMS 51
XDP_TCK 51
*
20,63,68 H_THRMTRIP_N THERMTRIP# BP30
H_SKTOCC_N PROC_TRST# XDP_TRST_N 51
TP115 1 BR33 BL30
PROC_SELECT_N SKTOCC# PROC_PREQ# XDP_PREQ_N 51
C R21 1 @ 2 0_0402_5% BN1 BP27 C
PROC_SELECT# PROC_PRDY# XDP_PRDY_N 51
TP4 1 H_CATERR_N BM30
CATERR# BT25 CFG_RCOMP R22 2 1
CFG_RCOMP 49.9_0402_1%

BRD Note:
CFG4 R23 2 1 1K_0402_5%
Placed near CPU within 1.1 inch
5 OF 14 ?
SKL_H_BGA_BGA REV = 1

Embedded Display Port Presence Strap


1:Disable
CFG4
0:Enable(Default)
*
CFG6 R26 2 @ 1 1K_0402_5%
? SKYLAKE_HALO
U1K CFG5 R28 2 @ 1 1K_0402_5%
BGA1440

TP5 1 TP_SKL_D1 D1 BM33 TP_SKL_BM33 1 TP6


TP7 1 TP_SKL_E1 E1 RSVD_TP RSVD_TP BL33 TP_SKL_BL33 1 TP8
TP9 1 TP_SKL_E3 E3 RSVD_TP RSVD_TP
TP10 1 TP_SKL_E2 E2 RSVD_TP BJ14 TP_SKL_BJ14 1 TP13
B RSVD_TP RSVD_TP TP_SKL_BJ13 B
BRD Note: RSVD_TP
BJ13 1 TP14
PEG CONFIG Straps
TP11 1 TP_SKL_BR1 BR1
Placed within 1.1 inch of CPU pins TP12 1 TP_SKL_BT2 BT2 RSVD_TP BK28
RSVD_TP RSVD

+1.0V_VCCST
BN35
RSVD
RSVD
BJ28

BJ18
11: x16 (Default)) *
VSS
J24
H24 RSVD
RSVD RSVD_TP
BJ16 TP_SKL_BJ16 1 TP20 CFG[6:5] 10: x8, x8
R24 2 1 51_0402_5% XDP_TDO BN33 BK16 TP_SKL_BK16 1 TP22
RSVD RSVD_TP
R25 2 @ 1 51_0402_5% XDP_PREQ_N
BL34
RSVD 01: Reserved
N29 BK24 TP_SKL_BK24 1 TP25
RSVD RSVD_TP TP_SKL_BJ24
R27 2 1 51_0402_5% XDP_TCK
R14
AE29 RSVD
RSVD
RSVD_TP
BJ24 1 TP27
00: x8,x4,x4
AA14 BK21
R29 2 @ 1 51_0402_5% XDP_TRST_N RSVD RSVD BJ21
RSVD
CAD Note: A36
RSVD
A37 BT17
CRB use 30R;DG use 0R RSVD RSVD BR17
PCH_2_CPU_TRIGGER H23 RSVD
23 PCH_2_CPU_TRIGGER R31 2 1 33_0402_5% CPU_2_PCH_TRIGGER_R J23 PROC_TRIGIN BK18 CFG7 R32 2 @ 1 1K_0402_5%
H_PWRGD 23 CPU_2_PCH_TRIGGER PROC_TRIGOUT VSS
F30 BJ34 TP_SKL_BJ34 1 TP35
E30 RSVD RSVD_TP BJ33 TP_SKL_BJ33 1 TP37
RSVD RSVD_TP
2

1
R30 C33 B30
@ @ C30 RSVD
RSVD G13
10K_0402_5%

100P_0402_50V8J

2 G3
RSVD
RSVD
RSVD
AJ8 PEG TRAINNING
1

J3 BL31
RSVD RSVD
1: follow RESET# deassertion
NCTF
NCTF
B2
B38
CFG7 *
BR35
RSVD
NCTF
NCTF
BP1
BR2 0: Wait for BIOS for training
BR31 C1
BH30 RSVD NCTF C38
RSVD NCTF
A A

11 OF 14 ?
SKL_H_BGA_BGA REV = 1 LENOVO.CRDN
Title
PROCESSOR-CLK/PM/STRAP/TP
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 6 of 99
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

D
FOR H4+4e D
CPU_CORE ? SKYLAKE_HALO
U1G CPU_CORE
? SKYLAKE_HALO
U1J
BGA1440
BGA1440
AA13 V32
BJ17 AA31 VCC VCC V33
BJ19 VCCOPC AA32 VCC VCC V34
BJ20 VCCOPC AA33 VCC VCC V35
BK17 VCCOPC AA34 VCC VCC V36
BK19 VCCOPC AA35 VCC VCC V37
BK20 VCCOPC AA36 VCC VCC V38
BL16 VCCOPC AA37 VCC VCC W13
BL17 VCCOPC AA38 VCC VCC W14
BL18 VCCOPC AB29 VCC VCC W29
BL19 VCCOPC AB30 VCC VCC W30
BL20 VCCOPC AB31 VCC VCC W31
BL21 VCCOPC AB32 VCC VCC W32
BM17 VCCOPC AB35 VCC VCC W35
BN17 VCCOPC AB36 VCC VCC W36
VCCOPC AB37 VCC VCC W37
BJ23 AB38 VCC VCC W38
BJ26 RSVD AC13 VCC VCC Y29
BJ27 RSVD AC14 VCC VCC Y30
BK23 RSVD AC29 VCC VCC Y31
BK26 RSVD AC30 VCC VCC Y32
BK27 RSVD AC31 VCC VCC Y33
BL23 RSVD AC32 VCC VCC Y34
BL24 RSVD AC33 VCC VCC Y35
BL25 RSVD AC34 VCC VCC Y36
BL26 RSVD AC35 VCC VCC L14
BL27 RSVD AC36 VCC VCC P29
BL28 RSVD AD13 VCC VCC P30
BM24 RSVD AD14 VCC VCC P31
RSVD AD31 VCC VCC P32
AD32 VCC VCC P33
BL15 AD33 VCC VCC P34
BM16 VCCOPC_SENSE AD34 VCC VCC P35
VSSOPC_SENSE AD35 VCC VCC P36
C C
BL22 AD36 VCC VCC R13
BM22 RSVD AD37 VCC VCC R31
RSVD AD38 VCC VCC R32
AE13 VCC VCC R33
BP15 AE14 VCC VCC R34
BR15 VCCEOPIO AE30 VCC VCC R35
BT15 VCCEOPIO AE31 VCC VCC R36
VCCEOPIO AE32 VCC VCC R37
BP16 AE35 VCC VCC R38
BR16 RSVD AE36 VCC VCC T29
BT16 RSVD AE37 VCC VCC T30
RSVD AE38 VCC VCC T31
AF35 VCC VCC T32
BN15 AF36 VCC VCC T35
BM15 VCCEOPIO_SENSE AF37 VCC VCC T36
VSSEOPIO_SENSE AF38 VCC VCC T37
BP17 K13 VCC VCC T38
BN16 RSVD K14 VCC VCC U29
RSVD L13 VCC VCC U30
N13 VCC VCC U31
BM14 N14 VCC VCC U32
BL14 VCC_OPC_1P8 N30 VCC VCC U33
VCC_OPC_1P8 N31 VCC VCC U34
BJ35 N32 VCC VCC U35
BJ36 RSVD N35 VCC VCC U36
RSVD N36 VCC VCC V13
N37 VCC VCC V14
AT13 N38 VCC VCC V31
AW13 ZVM# P13 VCC VCC P14
MSM# VCC VCC
AU13
AY13 ZVM2#
MSM2# AG37 CPU_VCORE_VCC_SENSE
VCC_SENSE CPU_VCORE_VCC_SENSE 83
BT29 AG38 CPU_VCORE_VSS_SENSE CPU_VCORE_VSS_SENSE 83
BR25 OPC_RCOMP VSS_SENSE
BP25 OPCE_RCOMP
OPCE_RCOMP2
B B
7 OF 14 ?
10 OF 14 ? SKL_H_BGA_BGA REV = 1
SKL_H_BGA_BGA REV = 1

CPU_VCORE_VSS_SENSE

2
R59
@
49.9_0402_1%

1
CPU_VCORE_VCC_SENSE

A A

LENOVO.CRDN
Title
PROCESSOR-POWER
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 7 of 99
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

+VCCGT
FOR H4+4e
? SKYLAKE_HALO
+VCCGT ? SKYLAKE_HALO +VCCGT
U1N U1H
+1.2V_CPU_VDDQ +1.2V_VDDQ AJ29 BGA1440
+VCCSA ? SKYLAKE_HALO VCCGT BGA1440
U1I @ AJ30 BG34 AV29
AJ31 VCCGT AF29 BG35 VCCGT VCCGT AV30
D
J30
BGA1440
AA6 PJ15 2 1 JUMP_43X118 AJ32 VCCGT VCCGTX AF30 BG36 VCCGT VCCGT AV31 D
K29 VCCSA VDDQ AE12 2 1 AJ33 VCCGT VCCGTX AF31 BH33 VCCGT VCCGT AV32
K30 VCCSA VDDQ AF5 AJ34 VCCGT VCCGTX AF32 BH34 VCCGT VCCGT AV33
K31 VCCSA VDDQ AF6 AJ35 VCCGT VCCGTX AF33 BH35 VCCGT VCCGT AV34
K32 VCCSA VDDQ AG5 AJ36 VCCGT VCCGTX AF34 BH36 VCCGT VCCGT AV35
K33 VCCSA VDDQ AG9 AK31 VCCGT VCCGTX AG13 BH37 VCCGT VCCGT AV36
K34 VCCSA VDDQ AJ12 AK32 VCCGT VCCGTX AG14 BH38 VCCGT VCCGT AW14
K35 VCCSA VDDQ AL11 AK33 VCCGT VCCGTX AG31 BJ37 VCCGT VCCGT AW31
L31 VCCSA VDDQ AP6 AK34 VCCGT VCCGTX AG32 BJ38 VCCGT VCCGT AW32
L32 VCCSA VDDQ AP7 AK35 VCCGT VCCGTX AG33 BL36 VCCGT VCCGT AW33
L35 VCCSA VDDQ AR12 AK36 VCCGT VCCGTX AG34 BL37 VCCGT VCCGT AW34
L36 VCCSA VDDQ AR6 AK37 VCCGT VCCGTX AG35 BM36 VCCGT VCCGT AW35
L37 VCCSA VDDQ AT12 AK38 VCCGT VCCGTX AG36 BM37 VCCGT VCCGT AW36
L38 VCCSA VDDQ AW6 AL13 VCCGT VCCGTX AH13 BN36 VCCGT VCCGT AW37
M29 VCCSA VDDQ AY6 AL29 VCCGT VCCGTX AH14 BN37 VCCGT VCCGT AW38
M30 VCCSA VDDQ J5 AL30 VCCGT VCCGTX AH29 BN38 VCCGT VCCGT AY29
M31 VCCSA VDDQ J6 AL31 VCCGT VCCGTX AH30 BP37 VCCGT VCCGT AY30
M32 VCCSA VDDQ K12 AL32 VCCGT VCCGTX AH31 BP38 VCCGT VCCGT AY31
M33 VCCSA VDDQ K6 AL35 VCCGT VCCGTX AH32 BR37 VCCGT VCCGT AY32
M34 VCCSA VDDQ L12 AL36 VCCGT VCCGTX AJ13 BT37 VCCGT VCCGT AY35
M35 VCCSA VDDQ L6 AL37 VCCGT VCCGTX AJ14 BE38 VCCGT VCCGT AY36
M36 VCCSA VDDQ R6 AL38 VCCGT VCCGTX BF13 VCCGT VCCGT AY37
+VCCIO VCCSA VDDQ T6 AM13 VCCGT BF14 VCCGT VCCGT AY38
VDDQ W6 +VCCVDDQ_CLK AM14 VCCGT BF29 VCCGT VCCGT BA13
AG12 VDDQ AM29 VCCGT BF30 VCCGT VCCGT BA14
G15 VCCIO Y12 AM30 VCCGT BF31 VCCGT VCCGT BA29
G17 VCCIO VDDQC +VCCSFR_OC AM31 VCCGT BF32 VCCGT VCCGT BA30
G19 VCCIO BH13 AM32 VCCGT BF35 VCCGT VCCGT BA31
G21 VCCIO VCCPLL_OC G11 AM33 VCCGT BF36 VCCGT VCCGT BA32
H15 VCCIO VCCPLL_OC AM34 VCCGT BF37 VCCGT VCCGT BA33
H16 VCCIO AM35 VCCGT BF38 VCCGT VCCGT BA34
H17 VCCIO H30 AM36 VCCGT BG29 VCCGT VCCGT BA35
VCCIO VCCST +1.0V_VCCST VCCGT VCCGT VCCGT
H19 AN13 BG30 BA36
H20 VCCIO H29 AN14 VCCGT BG31 VCCGT VCCGT BB13
VCCIO VCCSTG +1.0V_VCCSTG VCCGT VCCGT VCCGT
H21 AN31 BG32 BB14
H26 VCCIO G30 AN32 VCCGT BG33 VCCGT VCCGT BB31
H27 VCCIO VCCSTG AN33 VCCGT BC36 VCCGT VCCGT BB32
J15 VCCIO H28 AN34 VCCGT BC37 VCCGT VCCGT BB33
C +1.0V_VCCSFR C
J16 VCCIO VCCPLL J28 AN35 VCCGT BC38 VCCGT VCCGT BB34
J17 VCCIO VCCPLL AN36 VCCGT BD13 VCCGT VCCGT BB35
J19 VCCIO AN37 VCCGT BD14 VCCGT VCCGT BB36
J20 VCCIO M38 CPU_VCCSA_VCC_SENSE AN38 VCCGT BD29 VCCGT VCCGT BB37
VCCIO VCCSA_SENSE CPU_VCCSA_VCC_SENSE 83 VCCGT VCCGT VCCGT
J21 M37 CPU_VCCSA_VSS_SENSE AP13 BD30 BB38
VCCIO VSSSA_SENSE CPU_VCCSA_VSS_SENSE 83 VCCGT VCCGT VCCGT
J26 AP14 BD31 BC29
J27 VCCIO H14 CPU_VCCIO_VCC_SENSE AP29 VCCGT BD32 VCCGT VCCGT BC30
VCCIO VCCIO_SENSE CPU_VCCIO_VCC_SENSE 89 VCCGT VCCGT VCCGT
J14 CPU_VCCIO_VSS_SENSE AP30 BD33 BC31
VSSIO_SENSE CPU_VCCIO_VSS_SENSE 89 VCCGT VCCGT VCCGT
AP31 BD34 BC32
AP32 VCCGT BD35 VCCGT VCCGT BC35
AP35 VCCGT BD36 VCCGT VCCGT BE33
AP36 VCCGT BE31 VCCGT VCCGT BE34
AP37 VCCGT BE32 VCCGT VCCGT BE35
AP38 VCCGT BE37 VCCGT VCCGT BE36
AR29 VCCGT VCCGT VCCGT
AR30 VCCGT
9 OF 14 ? AR31 VCCGT
SKL_H_BGA_BGA REV = 1 AR32 VCCGT TP188 8 OF 14 ?
AR33 VCCGT AH38 CPU_VCCGT_VCC_SENSE 1 TESTPAD SKL_H_BGA_BGA REV = 1
AR34 VCCGT VCCGT_SENSE AH37 CPU_VCCGT_VSS_SENSE 1
AR35 VCCGT VSSGT_SENSE TESTPAD
AR36 VCCGT TP189
AT14 VCCGT AH36
AT31 VCCGT VCCGTX_SENSE AH35
AT32 VCCGT VSSGTX_SENSE
AT33 VCCGT
+1.0V_VCCST_VCCSFR +1.0V_VCCST AT34 VCCGT
AT35 VCCGT
AT36 VCCGT
R53 2 1 0_0603_5% AT37 VCCGT
AT38 VCCGT
+1.0V_VCCSFR AU14 VCCGT
AU29 VCCGT
AU30 VCCGT
R54 2 1 0_0603_5% AU31 VCCGT
AU32 VCCGT
AU35 VCCGT
B
AU36 VCCGT B
AU37 VCCGT
AU38 VCCGT
VCCGT

14 OF 14 ?
SKL_H_BGA_BGA REV = 1

+1.2V_CPU_VDDQ +VCCVDDQ_CLK

R52 1 2 0_0402_5%

A A

LENOVO.CRDN
Title
PROCESSOR-POWER
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 8 of 99
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

D D
? SKYLAKE_HALO ?
U1L SKYLAKE_HALO U1M
? SKYLAKE_HALO
U1F BGA1440 BGA1440
C17 BB4 AK30
Y38
BGA1440
K1 C13 VSS C25 BB3 VSS VSS AK29
Y37 VSS VSS J36 C9 VSS VSS C23 BB2 VSS VSS AK4
Y14 VSS VSS J33 BT32 VSS VSS C21 BB1 VSS VSS AJ38
Y13 VSS VSS J32 BT26 VSS VSS C19 BA38 VSS VSS AJ37
Y11 VSS VSS J25 BT24 VSS VSS C15 BA37 VSS VSS AJ6
Y10 VSS VSS J22 BT21 VSS VSS C11 BA12 VSS VSS AJ5
Y9 VSS VSS J18 BT18 VSS VSS C8 BA11 VSS VSS AJ4
Y8 VSS VSS J10 BT14 VSS VSS C5 BA10 VSS VSS AJ3
Y7 VSS VSS J7 BT12 VSS VSS BM29 BA9 VSS VSS AJ2
W34 VSS VSS J4 BT9 VSS VSS BM25 BA8 VSS VSS AJ1
W33 VSS VSS H35 BT5 VSS VSS BM18 BA7 VSS VSS AH34
W12 VSS VSS H32 BR36 VSS VSS BM11 BA6 VSS VSS AH33
W5 VSS VSS H25 BR34 VSS VSS BM8 B9 VSS VSS AH12
W4 VSS VSS H22 BR29 VSS VSS BM7 AY34 VSS VSS AH6
W3 VSS VSS H18 BR26 VSS VSS BM5 AY33 VSS VSS AG30
W2 VSS VSS H12 BR24 VSS VSS BM3 AY14 VSS VSS AG29
W1 VSS VSS H11 BR21 VSS VSS BL38 AY12 VSS VSS AG11
V30 VSS VSS G28 BR18 VSS VSS BL35 AW30 VSS VSS AG10
V29 VSS VSS G26 BR14 VSS VSS BL13 AW29 VSS VSS AG8
V12 VSS VSS G24 BR12 VSS VSS BL6 AW12 VSS VSS AG7
V6 VSS VSS G23 BR7 VSS VSS BK25 AW5 VSS VSS AG6
U38 VSS VSS G22 BP34 VSS VSS BK22 AW4 VSS VSS AF14
U37 VSS VSS G20 BP33 VSS VSS BK13 AW3 VSS VSS AF13
U6 VSS VSS G18 BP29 VSS VSS BK6 AW2 VSS VSS AF12
T34 VSS VSS G16 BP26 VSS VSS BJ30 AW1 VSS VSS AF4
T33 VSS VSS G14 BP24 VSS VSS BJ29 AV38 VSS VSS AF3
T14 VSS VSS G12 BP21 VSS VSS BJ15 AV37 VSS VSS AF2
T13 VSS VSS G10 BP18 VSS VSS BJ12 AU34 VSS VSS AF1
T12 VSS VSS G9 BP14 VSS VSS BH11 AU33 VSS VSS AE34
T11 VSS VSS G8 BP12 VSS VSS BH10 AU12 VSS VSS AE33
T10 VSS VSS G6 BP7 VSS VSS BH7 AU11 VSS VSS AE6
T9 VSS VSS G5 BN34 VSS VSS BH6 AU10 VSS VSS AD30
T8 VSS VSS G4 BN31 VSS VSS BH3 AU9 VSS VSS AD29
T7 VSS VSS F36 BN30 VSS VSS BH2 AU8 VSS VSS AD12
C C
T5 VSS VSS F31 BN29 VSS VSS BG37 AU7 VSS VSS AD11
T4 VSS VSS F29 BN24 VSS VSS BG14 AU6 VSS VSS AD10
T3 VSS VSS F27 BN21 VSS VSS BG6 AT30 VSS VSS AD9
T2 VSS VSS F25 BN20 VSS VSS BF34 AT29 VSS VSS AD8
T1 VSS VSS F23 BN19 VSS VSS BF6 AT6 VSS VSS AD7
R30 VSS VSS F21 BN18 VSS VSS BE30 AR38 VSS VSS AD6
R29 VSS VSS F19 BN14 VSS VSS BE5 AR37 VSS VSS AC38
R12 VSS VSS F17 BN12 VSS VSS BE4 AR14 VSS VSS AC37
P38 VSS VSS F15 BN9 VSS VSS BE3 AR13 VSS VSS AC12
P37 VSS VSS F13 BN7 VSS VSS BE2 AR5 VSS VSS AC6
P12 VSS VSS F11 BN4 VSS VSS BE1 AR4 VSS VSS AC5
P6 VSS VSS F9 BN2 VSS VSS BD38 AR3 VSS VSS AC4
N34 VSS VSS F8 BM38 VSS VSS BD37 AR2 VSS VSS AC3
N33 VSS VSS F5 BM35 VSS VSS BD12 AR1 VSS VSS AC2
N12 VSS VSS F4 BM28 VSS VSS BD11 AP34 VSS VSS AC1
N11 VSS VSS F3 BM27 VSS VSS BD10 AP33 VSS VSS AB34
N10 VSS VSS F2 BM26 VSS VSS BD8 AP12 VSS VSS AB33
N9 VSS VSS E38 BM23 VSS VSS BD7 AP11 VSS VSS AB6
N8 VSS VSS E35 BM21 VSS VSS BD6 AP10 VSS VSS AA30
N7 VSS VSS E34 BM13 VSS VSS BC33 AP9 VSS VSS AA29
N6 VSS VSS E9 BM12 VSS VSS BC14 AP8 VSS VSS AA12
N5 VSS VSS E4 BM9 VSS VSS BC13 AN30 VSS VSS A30
N4 VSS VSS D33 BM6 VSS VSS BC6 AN29 VSS VSS A28
N3 VSS VSS D30 BM2 VSS VSS BB30 AN12 VSS VSS A26
N2 VSS VSS D28 BL29 VSS VSS BB29 AN6 VSS VSS A24
N1 VSS VSS D26 BK29 VSS VSS BB6 AN5 VSS VSS A22
M14 VSS VSS D24 BK15 VSS VSS BB5 AM38 VSS VSS A20
M13 VSS VSS D22 BK14 VSS VSS AM37 VSS VSS A18
M12 VSS VSS D20 BJ32 VSS AM12 VSS VSS A16
M6 VSS VSS D18 BJ31 VSS AM5 VSS VSS A14
L34 VSS VSS D16 BJ25 VSS AM4 VSS VSS A12
L33 VSS VSS D14 BJ22 VSS AM3 VSS VSS A10
L30 VSS VSS D12 BH14 VSS AM2 VSS VSS A9
L29 VSS VSS D10 BH12 VSS AM1 VSS VSS A6
K38 VSS VSS D9 BH9 VSS AL34 VSS VSS
K11 VSS VSS D6 BH8 VSS C2 AL33 VSS
K10 VSS VSS D3 BH5 VSS NCTFVSS BT36 AL14 VSS B37
B
K9 VSS VSS C37 BH4 VSS NCTFVSS BT35 AL12 VSS NCTFVSS B3 B
K8 VSS VSS C31 BH1 VSS NCTFVSS BT4 AL10 VSS NCTFVSS A34
K7 VSS VSS C29 BG38 VSS NCTFVSS BT3 AL9 VSS NCTFVSS A4
K5 VSS VSS C27 BG13 VSS NCTFVSS BR38 AL8 VSS NCTFVSS A3
K4 VSS VSS BG12 VSS NCTFVSS AL7 VSS NCTFVSS
K3 VSS D38 BF33 VSS AL4 VSS
K2 VSS NCTFVSS BF12 VSS VSS
VSS BE29 VSS
BE6 VSS
6 OF 14 ? BD9 VSS 13 OF 14
SKL_H_BGA_BGA REV = 1 BC34 VSS SKL_H_BGA_BGA REV = 1 ?
BC12 VSS
BB12 VSS
VSS

12 OF 14 ?
SKL_H_BGA_BGA REV = 1

A A

LENOVO.CRDN
Title
PROCESSOR-VSS
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 9 of 99
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

D D

C C

+VCCSA
BOTTOM:1X0805(47UF), 8X0402(10UF), 3X0201(1UF);
+1.2V_CPU_VDDQ 4X0603(22UF) 10X0402(10UF) TOP:2XBULK(220UF),1X0805(22UF)
BRD Note:
Placed backside
BRD Note: BRD Note:
Placed backside Placed TOP BGA EDGE
+1.2V_CPU_VDDQ +1.2V_CPU_VDDQ +VCCSA +VCCSA +VCCSA +VCCSA

1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 C941 C942

2
C915 C916 C917 C918 C919 C920 C921 C922 C923 C924 C925 C926 C927 C928 C930 C931 C932 C933 C934 C935 C936 C937 +@ +

330U_B2_2.5VM_R9M

330U_B2_2.5VM_R9M
C929 C938 C939 C940 C312
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

47U_0805_6.3V6-M

1u_0201_10V6M

1u_0201_10V6M

1u_0201_10V6M

47U_0805_6.3V6-M
1

1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 2 2
B B

BRD Note:
Placed backside
+VCCIO 2x0805(47UF) 3X0402(10UF)

+1.0V_VCCSTG +1.0V_VCCST +1.0V_VCCSFR +1.0V_VCCSTG


BRD Note: BRD Note:
+VCCVDDQ_CLK +VCCSFR_OC
Placed TOP BGA EDGE Placed backside
+VCCIO +VCCIO

2 2 2 2 2 1 2 2
C949
C944 C945 C946 C947 C948 C950 C951
10U_0402_6.3V6M
1u_0201_10V6M

1u_0201_10V6M

1u_0201_10V6M

1u_0201_10V6M

1u_0201_10V6M

1u_0201_10V6M

1u_0201_10V6M

1 1 1 1 1 2 1 1 1 1 1
2

A C871 C872 C873 A


C240 C311
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
47U_0805_6.3V6-M

47U_0805_6.3V6-M
1

2 2 2
LENOVO.CRDN
Title
PROCESSOR Decoupling 1/2
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 10 of 99
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
D

property to LENOVO PND and shall not be reproduced or transferred to other documents
Rev V0.3
C1085

C1131

C1177

99

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


or disclosed to others or used for any purpose other than that for which it was
2

LENOVO.CRDN
C1084

C1130

C1176

of
"PROPERTY NOTE: this document contains information confidential and

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


11
2

obtained without the expressed written consent of LENOVO PND."


C1083

C1129

C1175

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


Sheet
2

1
C1082

C1128

C1174

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


PROCESSOR Decoupling 2/2
2

1
Placed backside

C1081

C1127

C1173
1

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


Thursday, May 26, 2016
2

1
C1080

C1126

C1172
BRD Note:

C1006

C1039

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


Document Number

10U_0402_6.3V6M 10U_0402_6.3V6M
Skylake-H
1

1
C1079

C1125

C1171
C1005

C1038

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


10U_0402_6.3V6M 10U_0402_6.3V6M
1

1
C1078

C1124

C1170
C1004

C1037

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


BOTTOM:4XBULK(220UF),8X0603(22U),36X0402(10UF), 69X0201(1UF);

10U_0402_6.3V6M 10U_0402_6.3V6M
Date:
1

Size
Title

C
C1077

C1123

C1169
C1003

C1036

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


10U_0402_6.3V6M 10U_0402_6.3V6M
1

1
C1076

C1122

C1168
C1002

C1035

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


10U_0402_6.3V6M 10U_0402_6.3V6M
C973

22U_0603_6.3V6M
1

1
C1075

C1121

C1167
1

C1001

C1034

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


10U_0402_6.3V6M 10U_0402_6.3V6M
C972

22U_0603_6.3V6M
1

1
C1074

C1120

C1166
1

C1000

C1033

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


10U_0402_6.3V6M 10U_0402_6.3V6M
C971

22U_0603_6.3V6M
1

1
C1073

C1119

C1165
1

C1032
C999

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


10U_0402_6.3V6M 10U_0402_6.3V6M
C970

22U_0603_6.3V6M
C1194

47U_0805_6.3V6-M
1

1
C1072

C1118

C1164
1

C1031
C998

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


TOP:4XBULK(220UF),6X0805(47UF)

10U_0402_6.3V6M 10U_0402_6.3V6M
C969

2 1
22U_0603_6.3V6M
C1193

47U_0805_6.3V6-M
1

1
C1071

C1117

C1163
1

C1030
2

2
C997

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


10U_0402_6.3V6M 10U_0402_6.3V6M
C968

2 1
22U_0603_6.3V6M
C1192
47U_0805_6.3V6-M
1

1
C1070

C1116

C1162
1

C1029
C996

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


10U_0402_6.3V6M 10U_0402_6.3V6M
C967

2 1
22U_0603_6.3V6M

C1191
47U_0805_6.3V6-M
1

1
C1069

C1115

C1161
1

C1028
C995

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


10U_0402_6.3V6M 10U_0402_6.3V6M
C966

2 1
22U_0603_6.3V6M

C1190
+VCCGT

47U_0805_6.3V6-M
1

1
C1068

C1114

C1160

Placed TOP BGA EDGE


1

C1027
C994

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


10U_0402_6.3V6M 10U_0402_6.3V6M 2 1

C1189
47U_0805_6.3V6-M
1

1
C1067

C1113

C1159
+VCCGT

C1026
C993

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


10U_0402_6.3V6M 10U_0402_6.3V6M 2 1

C1188
1

330U_B2_2.5VM_R9M
C1066

C1112

C1158

BRD Note:

+@
C1025
C992

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M

2
10U_0402_6.3V6M 10U_0402_6.3V6M

C1187
C965

330U_B2_2.5VM_R9M 330U_B2_2.5VM_R9M
C1065

C1111

C1157
C1024
C991
+

+
1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M
1

2
10U_0402_6.3V6M 10U_0402_6.3V6M
1

C1186
C1064

C1110

C1156
C964

C1023

330U_B2_2.5VM_R9M 330U_B2_2.5VM_R9M
C990

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


10U_0402_6.3V6M 10U_0402_6.3V6M
+

+
1

2
1

1
C1063

C1109

C1155
C1022

C1185
C963

C989

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


330U_B2_2.5VM_R9M 10U_0402_6.3V6M 10U_0402_6.3V6M 330U_B2_2.5VM_R9M
+VCCGT

+VCCGT

+VCCGT

+VCCGT

+VCCGT

+VCCGT

+VCCGT
+

+
1

2
3

3
C1062

C1108

C1154
1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M
2

1
C1061

C1107

C1153
1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M
2

1
C1060

C1106

C1152
1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M
2

1
C1059

C1105

C1151
1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M
2

1
Placed backside

C1058

C1104

C1150
1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M
2

1
C1057

C1103

C1149
BRD Note:

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


2

1
C1056

C1102

C1148
1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M

1
C1055

C1101

C1147
1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M

1
C1054

C1100

C1146
C1021
C988

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


BOTTOM:3XBULK(220UF),8x0603(22U),30X0402(10UF), 69X0201(1UF);

10U_0402_6.3V6M 10U_0402_6.3V6M
1

1
C1053

C1099

C1145
C1020
C987

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


4

4
10U_0402_6.3V6M 10U_0402_6.3V6M
C962

22U_0603_6.3V6M
1

1
C1052

C1098

C1144
1

C1019
C986

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


10U_0402_6.3V6M 10U_0402_6.3V6M
C961

22U_0603_6.3V6M
1

1
C1051

C1097

C1143
1

C1018
C985

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


10U_0402_6.3V6M 10U_0402_6.3V6M
C960

22U_0603_6.3V6M
1

1
C1050

C1096

C1142
1

C1017
C984

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


10U_0402_6.3V6M 10U_0402_6.3V6M
C959

22U_0603_6.3V6M
1

1
C1049

C1095

C1141
1

C1016
C983

1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M


10U_0402_6.3V6M 10U_0402_6.3V6M
C958

22U_0603_6.3V6M
1

1
C1048

C1094

C1140
1

C1015
C982 1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M
TOP:3XBULK(220UF),4X0805(47UF)

10U_0402_6.3V6M 10U_0402_6.3V6M
C957

22U_0603_6.3V6M 1

1
C1047

C1093

C1139
1

C1014
C981
1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M
10U_0402_6.3V6M 10U_0402_6.3V6M
C956

22U_0603_6.3V6M

C1184
47U_0805_6.3V6-M

1
C1046

C1092

C1138
1

C1013
C980
1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M
10U_0402_6.3V6M 10U_0402_6.3V6M
C955

2 1
22U_0603_6.3V6M

C1183
CPU_CORE

47U_0805_6.3V6-M

1
C1045

C1091

C1137

Placed TOP BGA EDGE


1

C1012
C979
1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M
10U_0402_6.3V6M 10U_0402_6.3V6M 2 1

C1182
47U_0805_6.3V6-M

1
C1044

C1090

C1136
C1011
C978
1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M
10U_0402_6.3V6M 10U_0402_6.3V6M 2 1

C1181
CPU_CORE

47U_0805_6.3V6-M

1
C1043

C1089

C1135

BRD Note:
C1010
C977
1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M
5

5
10U_0402_6.3V6M 10U_0402_6.3V6M 2 1

C1180
C954

1
C1042

C1088

C1134
330U_B2_2.5VM_R9M 330U_B2_2.5VM_R9M

C1009
C976
+

+
1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M

2
10U_0402_6.3V6M 10U_0402_6.3V6M

C1179
C1041

C1087

C1133
C953

C1008
330U_B2_2.5VM_R9M 330U_B2_2.5VM_R9M

C975
1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M
10U_0402_6.3V6M 10U_0402_6.3V6M

+
1

2
1

1
C1040

C1086

C1132
C1007

C1178
C952

C974
1u_0201_10V6M 1u_0201_10V6M 1u_0201_10V6M

CPU_CORE

CPU_CORE

CPU_CORE

CPU_CORE

CPU_CORE

CPU_CORE

CPU_CORE
330U_B2_2.5VM_R9M 10U_0402_6.3V6M 10U_0402_6.3V6M 330U_B2_2.5VM_R9M

+
1

2
D

A
5 4 3 2 1

DDR4 SODIMM CHANNEL - A BOTTOM REV DIMM0 (5.2 MM HEIGHT CONNECTOR)

JDIMM1A

137 8
4 M_A_DIM0_CK_DDR0_DP CK0_T DQ0 M_A_DQ5 4,13
139 7
4 M_A_DIM0_CK_DDR0_DN CK0_C DQ1 M_A_DQ0 4,13
138 20 +1.2V_VDDQ +0.6V_VTT
4 M_A_DIM0_CK_DDR1_DP CK1_T DQ2 M_A_DQ2 4,13
140 21 JDIMM1B
4 M_A_DIM0_CK_DDR1_DN CK1_C DQ3 M_A_DQ3 4,13

D 4 M_A_DIM0_CKE0
109
CKE0
DQ4
DQ5
4
3
M_A_DQ1 4,13
M_A_DQ4 4,13
BYTE 0 163
VDD VTT
258
D
110 16 160
4 M_A_DIM0_CKE1 CKE1 DQ6 M_A_DQ6 4,13 VDD
17 159
DQ7 M_A_DQ7 4,13 VDD
149 28 154 +2.5V_MEM
4 M_A_DIM0_CS0_N S0# DQ8 M_A_DQ8 4,13 VDD
157 29 153
4 M_A_DIM0_CS1_N S1# DQ9 M_A_DQ12 4,13 VDD
41 148
DQ10 M_A_DQ14 4,13 VDD
155 42 147 259
4 M_A_DIM0_ODT0 ODT0 DQ11 M_A_DQ11 4,13 VDD VPP2
4 M_A_DIM0_ODT1
161
ODT1 DQ12
DQ13
24
25
M_A_DQ9 4,13
M_A_DQ13 4,13
BYTE 1 142
141 VDD
VDD
VPP1
257

115 38 136
4,13 M_A_BG0 BG0 DQ14 M_A_DQ10 4,13 VDD
113 37 135
4,13 M_A_BG1 BG1 DQ15 M_A_DQ15 4,13 VDD
150 50 130 +3V
4,13 M_A_BA0 BA0 DQ16 M_A_DQ16 4,13 VDD
145 49 129
4,13 M_A_BA1 BA1 DQ17 M_A_DQ20 4,13 VDD
62 124
DQ18 M_A_DQ22 4,13 VDD
63 123 255
DQ19 M_A_DQ23 4,13 VDD VDDSPD
4,13 M_A_A0
144
A0 DQ20
46
M_A_DQ17 4,13 BYTE 2 118
VDD

2
133 45 117 C35 C36
4,13 M_A_A1 A1 DQ21 M_A_DQ21 4,13 VDD
132 58 112
4,13 M_A_A2 A2 DQ22 M_A_DQ19 4,13 VDD
131 59 111

0.1U_0402_25V6

2.2U_0402_6.3V6M
4,13 M_A_A3 A3 DQ23 M_A_DQ18 4,13 VDD

1
128 70
4,13 M_A_A4 A4 DQ24 M_A_DQ25 4,13
126 71
4,13 M_A_A5 A5 DQ25 M_A_DQ28 4,13
127 83
4,13 M_A_A6 A6 DQ26 M_A_DQ30 4,13
122 84 251 252
4,13 M_A_A7 A7 DQ27 M_A_DQ31 4,13 VSS VSS
4,13
4,13
M_A_A8
M_A_A9
125
121 A8
A9
DQ28
DQ29
66
67
M_A_DQ24 4,13
M_A_DQ29 4,13
BYTE 3 247
243 VSS
VSS
VSS
VSS
248
244
146 79 239 238
4,13 M_A_A10_AP A10_AP DQ30 M_A_DQ27 4,13 VSS VSS
120 80 235 234
4,13 M_A_A11 A11 DQ31 M_A_DQ26 4,13 VSS VSS
119 174 231 230
4,13 M_A_A12 A12 DQ32 M_A_DQ32 4,13 VSS VSS
158 173 227 226
4,13 M_A_A13 A13 DQ33 M_A_DQ37 4,13 VSS VSS
151 187 223 222
4,13 M_A_A14_WE_N A14_WE# DQ34 M_A_DQ38 4,13 VSS VSS
156 186 217 218
4,13 M_A_A15_CAS_N A15_CAS# DQ35 M_A_DQ39 4,13 VSS VSS
4,13 M_A_A16_RAS_N
152
A16_RAS# DQ36
DQ37
170
169
M_A_DQ36 4,13
M_A_DQ33 4,13
BYTE 4 213
209 VSS
VSS
VSS
VSS
214
210
183 205 206
DQ38 M_A_DQ34 4,13 VSS VSS
182 201 202
DQ39 M_A_DQ35 4,13 VSS VSS
114 195 197 196
4,13 M_A_ACT_N ACT# DQ40 M_A_DQ44 4,13 VSS VSS
194 193 192
DQ41 M_A_DQ45 4,13 VSS VSS
143 207 189 188
4,13 DDR0_A_PARITY PARITY DQ42 M_A_DQ42 4,13 VSS VSS
C 116 208 185 184 C
4,13 DDR0_A_ALERT_N DIMM0_CHA_EVENT_N ALEART# DQ43 M_A_DQ43 4,13 VSS VSS
TP126
13,14,15,16 DDR4_DRAMRST_N
1
DDR4_DRAMRST_N
134
108 EVENT#
RESET#
DQ44
DQ45
191
190
M_A_DQ41 4,13
M_A_DQ40 4,13
BYTE 5 181
175 VSS
VSS
VSS
VSS
180
176
203 171 172
DQ46 M_A_DQ46 4,13 VSS VSS
+V_DIM_VREF_CA_CHA 164 204 167 168
VREFCA DQ47 M_A_DQ47 4,13 VSS VSS
216 107 106
DQ48 M_A_DQ49 4,13 VSS VSS
215 103 102
DQ49 M_A_DQ48 4,13 VSS VSS
228 99 98
DIMM_SMB_DAT DQ50 M_A_DQ55 4,13 VSS VSS
254 229 93 94
13,14,15,16 DIMM_SMB_DAT DIMM_SMB_CLK SDA DQ51 M_A_DQ53 4,13 VSS VSS
13,14,15,16 DIMM_SMB_CLK
253
SCL DQ52
DQ53
211
212
M_A_DQ50 4,13
M_A_DQ52 4,13
BYTE 6 89
85 VSS
VSS
VSS
VSS
90
86
224 81 82
DQ54 M_A_DQ54 4,13 VSS VSS
225 77 78
DQ55 M_A_DQ51 4,13 VSS VSS
166 237 73 72
SA2 DQ56 M_A_DQ63 4,13 VSS VSS
260 236 69 68
SA1 DQ57 M_A_DQ61 4,13 VSS VSS
256 249 65 64
SA0 DQ58 M_A_DQ58 4,13 VSS VSS
250 61 60
DQ59 M_A_DQ62 4,13 VSS VSS
92
91 CB0_NC
CB1_NC
DQ60
DQ61
232
233
M_A_DQ57 4,13
M_A_DQ56 4,13
BYTE 7 57
51 VSS
VSS
VSS
VSS
56
52
101 245 47 48
CB2_NC DQ62 M_A_DQ60 4,13 VSS VSS
105 246 43 44
CB3_NC DQ63 M_A_DQ59 4,13 VSS VSS
88 39 40
87 CB4_NC 35 VSS VSS 36
100 CB5_NC 13 31 VSS VSS 30
CB6_NC DQS0_T M_A_DQS_DP0 4,13 VSS VSS
104 34 27 26
CB7_NC DQS1_T M_A_DQS_DP1 4,13 VSS VSS
55 23 22
DQS2_T M_A_DQS_DP2 4,13 VSS VSS
76 19 18
+1.2V_VDDQ DQS3_T M_A_DQS_DP3 4,13 VSS VSS
179 15 14
DQS4_T M_A_DQS_DP4 4,13 VSS VSS
200 9 10
DQS5_T M_A_DQS_DP5 4,13 VSS VSS
12 221 5 6
DM0#/DBI0# DQS6_T M_A_DQS_DP6 4,13 VSS VSS
33 242 1 2
DM1#/DB1I# DQS7_T M_A_DQS_DP7 4,13 VSS VSS
BRD Note: 54
DM2#/DBI2# DQS8_T
97
75
Connect individually to +VDDQ_MEM 178 DM3#/DBI3# 11 262
DM4#/DBI4# DQS0_C M_A_DQS_DN0 4,13 MT2
199 32 261
DM5#/DBI5# DQS1_C M_A_DQS_DN1 4,13 MT1
220 53
DM6#/DBI6# DQS2_C M_A_DQS_DN2 4,13
241 74
DM7#/DBI7# DQS3_C M_A_DQS_DN3 4,13
96 177
B DM8#/DBI8# DQS4_C M_A_DQS_DN4 4,13 B
198 SO-DIMM-DDR4-260P SD-80886-2021 5.2MM
DQS5_C M_A_DQS_DN5 4,13
219
DQS6_C M_A_DQS_DN6 4,13
162 240
S2#/C0 DQS7_C M_A_DQS_DN7 4,13
165 95
S3#/C1 DQS8_C

SO-DIMM-DDR4-260P SD-80886-2021 5.2MM

SPD ADDRESS:0xA0

Decoupling Caps
BRD Note:
placed close to CHA DIMM0
+1.2V_VDDQ +2.5V_MEM
+V_DIM_VREF_CA_CHA
2

C37 C38 1
@ 1 1
1

1
+ C39
2.2U_0402_6.3V6M

0.1U_0402_25V6

C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53
1

330U_D2_2V_Y

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

1U_0402_10V6K

1U_0402_10V6K
2

2
2 2 2

A A

+0.6V_VTT
LENOVO.CRDN
Title
1 1 1 1 1 1 1 1 1 1 1 DDR4 CHA DIMM0
1

C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 1 C66 C67
Size Document Number
Rev V0.3
1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

10U_0603_10V

10U_0603_10V

1U_0402_10V6K
C
Skylake-H
2

2 2 2 2 2 2 2 2 2 2 2
Date: Thursday, May 26, 2016 Sheet 12 of 99
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

DDR4 SODIMM CHANNEL - A TOP STD DIMM1 (4 MM HEIGHT CONNECTOR)

JDIMM2A

137 8
4 M_A_DIM1_CK_DDR2_DP CK0_T DQ0 M_A_DQ5 4,12
139 7
4 M_A_DIM1_CK_DDR2_DN CK0_C DQ1 M_A_DQ0 4,12
138 20 +1.2V_VDDQ +0.6V_VTT
4 M_A_DIM1_CK_DDR3_DP CK1_T DQ2 M_A_DQ2 4,12
140 21 JDIMM2B
4 M_A_DIM1_CK_DDR3_DN CK1_C DQ3 M_A_DQ3 4,12

D 4 M_A_DIM1_CKE2
109
CKE0
DQ4
DQ5
4
3
M_A_DQ1 4,12
M_A_DQ4 4,12
BYTE 0 163
VDD VTT
258
D
110 16 160
4 M_A_DIM1_CKE3 CKE1 DQ6 M_A_DQ6 4,12 VDD
17 159
DQ7 M_A_DQ7 4,12 VDD
149 28 154 +2.5V_MEM
4 M_A_DIM1_CS2_N S0# DQ8 M_A_DQ8 4,12 VDD
157 29 153
4 M_A_DIM1_CS3_N S1# DQ9 M_A_DQ12 4,12 VDD
41 148
DQ10 M_A_DQ14 4,12 VDD
155 42 147 259
4 M_A_DIM1_ODT2 ODT0 DQ11 M_A_DQ11 4,12 VDD VPP2
4 M_A_DIM1_ODT3
161
ODT1 DQ12
DQ13
24
25
M_A_DQ9 4,12
M_A_DQ13 4,12
BYTE 1 142
141 VDD
VDD
VPP1
257

115 38 136
4,12 M_A_BG0 BG0 DQ14 M_A_DQ10 4,12 VDD
113 37 135
4,12 M_A_BG1 BG1 DQ15 M_A_DQ15 4,12 VDD
150 50 130 +3V
4,12 M_A_BA0 BA0 DQ16 M_A_DQ16 4,12 VDD
145 49 129
4,12 M_A_BA1 BA1 DQ17 M_A_DQ20 4,12 VDD
62 124
DQ18 M_A_DQ22 4,12 VDD
63 123 255
DQ19 M_A_DQ23 4,12 VDD VDDSPD
4,12 M_A_A0
144
A0 DQ20
46
M_A_DQ17 4,12 BYTE 2 118
VDD

2
133 45 117 C68 C69
4,12 M_A_A1 A1 DQ21 M_A_DQ21 4,12 VDD
132 58 112
4,12 M_A_A2 A2 DQ22 M_A_DQ19 4,12 VDD
131 59 111

0.1U_0402_25V6

2.2U_0402_6.3V6M
4,12 M_A_A3 A3 DQ23 M_A_DQ18 4,12 VDD

1
128 70
4,12 M_A_A4 A4 DQ24 M_A_DQ25 4,12
126 71
4,12 M_A_A5 A5 DQ25 M_A_DQ28 4,12
127 83
4,12 M_A_A6 A6 DQ26 M_A_DQ30 4,12
122 84 251 252
4,12 M_A_A7 A7 DQ27 M_A_DQ31 4,12 VSS VSS
4,12
4,12
M_A_A8
M_A_A9
125
121 A8
A9
DQ28
DQ29
66
67
M_A_DQ24 4,12
M_A_DQ29 4,12
BYTE 3 247
243 VSS
VSS
VSS
VSS
248
244
146 79 239 238
4,12 M_A_A10_AP A10_AP DQ30 M_A_DQ27 4,12 VSS VSS
120 80 235 234
4,12 M_A_A11 A11 DQ31 M_A_DQ26 4,12 VSS VSS
119 174 231 230
4,12 M_A_A12 A12 DQ32 M_A_DQ32 4,12 VSS VSS
158 173 227 226
4,12 M_A_A13 A13 DQ33 M_A_DQ37 4,12 VSS VSS
151 187 223 222
4,12 M_A_A14_WE_N A14_WE# DQ34 M_A_DQ38 4,12 VSS VSS
156 186 217 218
4,12 M_A_A15_CAS_N A15_CAS# DQ35 M_A_DQ39 4,12 VSS VSS
4,12 M_A_A16_RAS_N
152
A16_RAS# DQ36
DQ37
170
169
M_A_DQ36 4,12
M_A_DQ33 4,12
BYTE 4 213
209 VSS
VSS
VSS
VSS
214
210
183 205 206
DQ38 M_A_DQ34 4,12 VSS VSS
182 201 202
DQ39 M_A_DQ35 4,12 VSS VSS
114 195 197 196
4,12 M_A_ACT_N ACT# DQ40 M_A_DQ44 4,12 VSS VSS
194 193 192
DQ41 M_A_DQ45 4,12 VSS VSS
143 207 189 188
4,12 DDR0_A_PARITY PARITY DQ42 M_A_DQ42 4,12 VSS VSS
C 116 208 185 184 C
4,12 DDR0_A_ALERT_N DIMM1_CHA_EVENT_N ALEART# DQ43 M_A_DQ43 4,12 VSS VSS
TP127
12,14,15,16 DDR4_DRAMRST_N
1
DDR4_DRAMRST_N
134
108 EVENT#
RESET#
DQ44
DQ45
191
190
M_A_DQ41 4,12
M_A_DQ40 4,12
BYTE 5 181
175 VSS
VSS
VSS
VSS
180
176
203 171 172
DQ46 M_A_DQ46 4,12 VSS VSS
+V_DIM_VREF_CA_CHA 164 204 167 168
VREFCA DQ47 M_A_DQ47 4,12 VSS VSS
216 107 106
DQ48 M_A_DQ49 4,12 VSS VSS
215 103 102
DQ49 M_A_DQ48 4,12 VSS VSS
228 99 98
DIMM_SMB_DAT DQ50 M_A_DQ55 4,12 VSS VSS
254 229 93 94
12,14,15,16 DIMM_SMB_DAT DIMM_SMB_CLK SDA DQ51 M_A_DQ53 4,12 VSS VSS
12,14,15,16 DIMM_SMB_CLK
253
SCL DQ52
DQ53
211
212
M_A_DQ50 4,12
M_A_DQ52 4,12
BYTE 6 89
85 VSS
VSS
VSS
VSS
90
86
224 81 82
DQ54 M_A_DQ54 4,12 VSS VSS
225 77 78
DQ55 M_A_DQ51 4,12 VSS VSS
166 237 73 72
SA2 DQ56 M_A_DQ63 4,12 VSS VSS
260 236 69 68
SA1 DQ57 M_A_DQ61 4,12 VSS VSS
+3V 256 249 65 64
SA0 DQ58 M_A_DQ58 4,12 VSS VSS
250 61 60
DQ59 M_A_DQ62 4,12 VSS VSS
92
91 CB0_NC
CB1_NC
DQ60
DQ61
232
233
M_A_DQ57 4,12
M_A_DQ56 4,12
BYTE 7 57
51 VSS
VSS
VSS
VSS
56
52
101 245 47 48
CB2_NC DQ62 M_A_DQ60 4,12 VSS VSS
105 246 43 44
CB3_NC DQ63 M_A_DQ59 4,12 VSS VSS
88 39 40
87 CB4_NC 35 VSS VSS 36
100 CB5_NC 13 31 VSS VSS 30
CB6_NC DQS0_T M_A_DQS_DP0 4,12 VSS VSS
104 34 27 26
CB7_NC DQS1_T M_A_DQS_DP1 4,12 VSS VSS
55 23 22
DQS2_T M_A_DQS_DP2 4,12 VSS VSS
76 19 18
+1.2V_VDDQ DQS3_T M_A_DQS_DP3 4,12 VSS VSS
179 15 14
DQS4_T M_A_DQS_DP4 4,12 VSS VSS
200 9 10
DQS5_T M_A_DQS_DP5 4,12 VSS VSS
12 221 5 6
DM0#/DBI0# DQS6_T M_A_DQS_DP6 4,12 VSS VSS
33 242 1 2
DM1#/DB1I# DQS7_T M_A_DQS_DP7 4,12 VSS VSS
54 97
75 DM2#/DBI2# DQS8_T
178 DM3#/DBI3# 11 262
DM4#/DBI4# DQS0_C M_A_DQS_DN0 4,12 MT2
199 32 261
DM5#/DBI5# DQS1_C M_A_DQS_DN1 4,12 MT1
220 53
DM6#/DBI6# DQS2_C M_A_DQS_DN2 4,12
241 74
DM7#/DBI7# DQS3_C M_A_DQS_DN3 4,12
96 177
B DM8#/DBI8# DQS4_C M_A_DQS_DN4 4,12 B
198 SO-DIMM-DDR4-260P SD-80888-1021 4MM
DQS5_C M_A_DQS_DN5 4,12
219
DQS6_C M_A_DQS_DN6 4,12
162 240
S2#/C0 DQS7_C M_A_DQS_DN7 4,12
165 95
S3#/C1 DQS8_C

SO-DIMM-DDR4-260P SD-80888-1021 4MM

SPD ADDRESS:0xA2

Decoupling Caps
BRD Note:
placed close to CHA DIMM0
+1.2V_VDDQ +2.5V_MEM

1
+V_DIM_VREF_CA_CHA
1 1
1

1
+ C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86
@
330U_D2_2V_Y

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

1U_0402_10V6K

1U_0402_10V6K
2

2
2 2 2
2

C70 C54
@
2.2U_0402_6.3V6M

0.1U_0402_25V6
1

A A

+0.6V_VTT
LENOVO.CRDN
Title
1 1 1 1 1 1 1 1 1 1 1 DDR4 CHA DIMM1
1

C88 C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 1 C99 C100
Size Document Number
Rev V0.3
1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

10U_0603_10V

10U_0603_10V

1U_0402_10V6K
C
Skylake-H
2

2 2 2 2 2 2 2 2 2 2 2
Date: Thursday, May 26, 2016 Sheet 13 of 99
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

DDR4 SODIMM CHANNEL - B BOTTOM STD DIMM0 (5.2 MM HEIGHT CONNECTOR)

JDIMM3A

137 8
5 M_B_DIM0_CK_DDR0_DP CK0_T DQ0 M_B_DQ4 5,15
139 7
5 M_B_DIM0_CK_DDR0_DN CK0_C DQ1 M_B_DQ0 5,15
138 20 +1.2V_VDDQ +0.6V_VTT
5 M_B_DIM0_CK_DDR1_DP CK1_T DQ2 M_B_DQ6 5,15
140 21 JDIMM3B
5 M_B_DIM0_CK_DDR1_DN CK1_C DQ3 M_B_DQ7 5,15

D 5 M_B_DIM0_CKE0
109
CKE0
DQ4
DQ5
4
3
M_B_DQ2 5,15
M_B_DQ5 5,15
BYTE 0 163
VDD VTT
258
D
110 16 160
5 M_B_DIM0_CKE1 CKE1 DQ6 M_B_DQ1 5,15 VDD
17 159
DQ7 M_B_DQ3 5,15 VDD
149 28 154 +2.5V_MEM
5 M_B_DIM0_CS0_N S0# DQ8 M_B_DQ10 5,15 VDD
157 29 153
5 M_B_DIM0_CS1_N S1# DQ9 M_B_DQ14 5,15 VDD
41 148
DQ10 M_B_DQ13 5,15 VDD
155 42 147 259
5 M_B_DIM0_ODT0 ODT0 DQ11 M_B_DQ15 5,15 VDD VPP2
5 M_B_DIM0_ODT1
161
ODT1 DQ12
DQ13
24
25
M_B_DQ9 5,15
M_B_DQ8 5,15
BYTE 1 142
141 VDD
VDD
VPP1
257

115 38 136
5,15 M_B_BG0 BG0 DQ14 M_B_DQ11 5,15 VDD
113 37 135
5,15 M_B_BG1 BG1 DQ15 M_B_DQ12 5,15 VDD
150 50 130 +3V
5,15 M_B_BA0 BA0 DQ16 M_B_DQ18 5,15 VDD
145 49 129
5,15 M_B_BA1 BA1 DQ17 M_B_DQ22 5,15 VDD
62 124
DQ18 M_B_DQ20 5,15 VDD
63 123 255
DQ19 M_B_DQ21 5,15 VDD VDDSPD
5,15 M_B_A0
144
A0 DQ20
46
M_B_DQ17 5,15 BYTE 2 118
VDD

2
133 45 117 C101 C102
5,15 M_B_A1 A1 DQ21 M_B_DQ16 5,15 VDD
132 58 112
5,15 M_B_A2 A2 DQ22 M_B_DQ19 5,15 VDD
131 59 111

0.1U_0402_25V6

2.2U_0402_6.3V6M
5,15 M_B_A3 A3 DQ23 M_B_DQ23 5,15 VDD

1
128 70
5,15 M_B_A4 A4 DQ24 M_B_DQ30 5,15
126 71
5,15 M_B_A5 A5 DQ25 M_B_DQ31 5,15
127 83
5,15 M_B_A6 A6 DQ26 M_B_DQ24 5,15
122 84 251 252
5,15 M_B_A7 A7 DQ27 M_B_DQ29 5,15 VSS VSS
5,15
5,15
M_B_A8
M_B_A9
125
121 A8
A9
DQ28
DQ29
66
67
M_B_DQ28 5,15
M_B_DQ27 5,15
BYTE 3 247
243 VSS
VSS
VSS
VSS
248
244
146 79 239 238
5,15 M_B_A10_AP A10_AP DQ30 M_B_DQ25 5,15 VSS VSS
120 80 235 234
5,15 M_B_A11 A11 DQ31 M_B_DQ26 5,15 VSS VSS
119 174 231 230
5,15 M_B_A12 A12 DQ32 M_B_DQ39 5,15 VSS VSS
158 173 227 226
5,15 M_B_A13 A13 DQ33 M_B_DQ35 5,15 VSS VSS
151 187 223 222
5,15 M_B_A14_WE_N A14_WE# DQ34 M_B_DQ37 5,15 VSS VSS
156 186 217 218
5,15 M_B_A15_CAS_N A15_CAS# DQ35 M_B_DQ33 5,15 VSS VSS
5,15 M_B_A16_RAS_N
152
A16_RAS# DQ36
DQ37
170
169
M_B_DQ34 5,15
M_B_DQ38 5,15
BYTE 4 213
209 VSS
VSS
VSS
VSS
214
210
183 205 206
DQ38 M_B_DQ32 5,15 VSS VSS
182 201 202
DQ39 M_B_DQ36 5,15 VSS VSS
114 195 197 196
5,15 M_B_ACT_N ACT# DQ40 M_B_DQ41 5,15 VSS VSS
194 193 192
DQ41 M_B_DQ45 5,15 VSS VSS
143 207 189 188
5,15 DDR1_B_PARITY PARITY DQ42 M_B_DQ42 5,15 VSS VSS
C 116 208 185 184 C
5,15 DDR1_B_ALERT_N DIMM0_CHB_EVENT_N ALEART# DQ43 M_B_DQ47 5,15 VSS VSS
TP102
12,13,15,16 DDR4_DRAMRST_N
1
DDR4_DRAMRST_N
134
108 EVENT#
RESET#
DQ44
DQ45
191
190
M_B_DQ40 5,15
M_B_DQ44 5,15
BYTE 5 181
175 VSS
VSS
VSS
VSS
180
176
203 171 172
DQ46 M_B_DQ46 5,15 VSS VSS
+V_DIM_VREF_CA_CHB 164 204 167 168
VREFCA DQ47 M_B_DQ43 5,15 VSS VSS
216 107 106
DQ48 M_B_DQ54 5,15 VSS VSS
215 103 102
DQ49 M_B_DQ51 5,15 VSS VSS
228 99 98
DIMM_SMB_DAT DQ50 M_B_DQ53 5,15 VSS VSS
254 229 93 94
12,13,15,16 DIMM_SMB_DAT DIMM_SMB_CLK SDA DQ51 M_B_DQ55 5,15 VSS VSS
12,13,15,16 DIMM_SMB_CLK
253
SCL DQ52
DQ53
211
212
M_B_DQ52 5,15
M_B_DQ48 5,15
BYTE 6 89
85 VSS
VSS
VSS
VSS
90
86
224 81 82
DQ54 M_B_DQ50 5,15 VSS VSS
225 77 78
DQ55 M_B_DQ49 5,15 VSS VSS
166 237 73 72
SA2 DQ56 M_B_DQ62 5,15 VSS VSS
+3V 260 236 69 68
SA1 DQ57 M_B_DQ61 5,15 VSS VSS
256 249 65 64
SA0 DQ58 M_B_DQ60 5,15 VSS VSS
250 61 60
DQ59 M_B_DQ56 5,15 VSS VSS
92
91 CB0_NC
CB1_NC
DQ60
DQ61
232
233
M_B_DQ57 5,15
M_B_DQ59 5,15
BYTE 7 57
51 VSS
VSS
VSS
VSS
56
52
101 245 47 48
CB2_NC DQ62 M_B_DQ58 5,15 VSS VSS
105 246 43 44
CB3_NC DQ63 M_B_DQ63 5,15 VSS VSS
88 39 40
87 CB4_NC 35 VSS VSS 36
100 CB5_NC 13 31 VSS VSS 30
CB6_NC DQS0_T M_B_DQS_DP0 5,15 VSS VSS
104 34 27 26
CB7_NC DQS1_T M_B_DQS_DP1 5,15 VSS VSS
55 23 22
DQS2_T M_B_DQS_DP2 5,15 VSS VSS
76 19 18
+1.2V_VDDQ DQS3_T M_B_DQS_DP3 5,15 VSS VSS
179 15 14
DQS4_T M_B_DQS_DP4 5,15 VSS VSS
200 9 10
DQS5_T M_B_DQS_DP5 5,15 VSS VSS
12 221 5 6
DM0#/DBI0# DQS6_T M_B_DQS_DP6 5,15 VSS VSS
33 242 1 2
DM1#/DB1I# DQS7_T M_B_DQS_DP7 5,15 VSS VSS
54 97
75 DM2#/DBI2# DQS8_T
178 DM3#/DBI3# 11 262
DM4#/DBI4# DQS0_C M_B_DQS_DN0 5,15 MT2
199 32 261
DM5#/DBI5# DQS1_C M_B_DQS_DN1 5,15 MT1
220 53
DM6#/DBI6# DQS2_C M_B_DQS_DN2 5,15
241 74
DM7#/DBI7# DQS3_C M_B_DQS_DN3 5,15
96 177
B DM8#/DBI8# DQS4_C M_B_DQS_DN4 5,15 B
198 SO-DIMM-DDR4-260P SD-80888-2021 5.2MM
DQS5_C M_B_DQS_DN5 5,15
219
DQS6_C M_B_DQS_DN6 5,15
162 240
S2#/C0 DQS7_C M_B_DQS_DN7 5,15
165 95
S3#/C1 DQS8_C

SO-DIMM-DDR4-260P SD-80888-2021 5.2MM

SPD ADDRESS:0xA4

Decoupling Caps
BRD Note:
placed close to CHA DIMM0
+1.2V_VDDQ +2.5V_MEM

+V_DIM_VREF_CA_CHB

1
1 1
2

1
C104 C103 + C105 C106 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119
@ @
2.2U_0402_6.3V6M

0.1U_0402_25V6

330U_D2_2V_Y

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

1U_0402_10V6K

1U_0402_10V6K
1

2
2 2 2

A A

+0.6V_VTT
LENOVO.CRDN
Title
1 1 1 1 1 1 1 1 1 1 1 DDR4 CHB DIMM0
1

C121 C122 C123 C124 C125 C126 C127 C128 C129 C130 C131 1 C132 C133
Size Document Number
Rev V0.3
1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

10U_0603_10V

10U_0603_10V

1U_0402_10V6K
C
Skylake-H
2

2 2 2 2 2 2 2 2 2 2 2
Date: Thursday, May 26, 2016 Sheet 14 of 99
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

DDR4 SODIMM CHANNEL - B TOP REV DIMM1 (4.0 MM HEIGHT CONNECTOR)

JDIMM4A

137 8
5 M_B_DIM1_CK_DDR2_DP CK0_T DQ0 M_B_DQ4 5,14
139 7
5 M_B_DIM1_CK_DDR2_DN CK0_C DQ1 M_B_DQ0 5,14
138 20 +1.2V_VDDQ +0.6V_VTT
5 M_B_DIM1_CK_DDR3_DP CK1_T DQ2 M_B_DQ6 5,14
140 21 JDIMM4B
5 M_B_DIM1_CK_DDR3_DN CK1_C DQ3 M_B_DQ7 5,14

D 5 M_B_DIM1_CKE2
109
CKE0
DQ4
DQ5
4
3
M_B_DQ2 5,14
M_B_DQ5 5,14
BYTE 0 163
VDD VTT
258
D
110 16 160
5 M_B_DIM1_CKE3 CKE1 DQ6 M_B_DQ1 5,14 VDD
17 159
DQ7 M_B_DQ3 5,14 VDD
149 28 154 +2.5V_MEM
5 M_B_DIM1_CS2_N S0# DQ8 M_B_DQ10 5,14 VDD
157 29 153
5 M_B_DIM1_CS3_N S1# DQ9 M_B_DQ14 5,14 VDD
41 148
DQ10 M_B_DQ13 5,14 VDD
155 42 147 259
5 M_B_DIM1_ODT2 ODT0 DQ11 M_B_DQ15 5,14 VDD VPP2
5 M_B_DIM1_ODT3
161
ODT1 DQ12
DQ13
24
25
M_B_DQ9 5,14
M_B_DQ8 5,14
BYTE 1 142
141 VDD
VDD
VPP1
257

115 38 136
5,14 M_B_BG0 BG0 DQ14 M_B_DQ11 5,14 VDD
113 37 135
5,14 M_B_BG1 BG1 DQ15 M_B_DQ12 5,14 VDD
150 50 130 +3V
5,14 M_B_BA0 BA0 DQ16 M_B_DQ18 5,14 VDD
145 49 129
5,14 M_B_BA1 BA1 DQ17 M_B_DQ22 5,14 VDD
62 124
DQ18 M_B_DQ20 5,14 VDD
63 123 255
DQ19 M_B_DQ21 5,14 VDD VDDSPD
5,14 M_B_A0
144
A0 DQ20
46
M_B_DQ17 5,14 BYTE 2 118
VDD

2
133 45 117 C134 C135
5,14 M_B_A1 A1 DQ21 M_B_DQ16 5,14 VDD
132 58 112
5,14 M_B_A2 A2 DQ22 M_B_DQ19 5,14 VDD
131 59 111

0.1U_0402_25V6

2.2U_0402_6.3V6M
5,14 M_B_A3 A3 DQ23 M_B_DQ23 5,14 VDD

1
128 70
5,14 M_B_A4 A4 DQ24 M_B_DQ30 5,14
126 71
5,14 M_B_A5 A5 DQ25 M_B_DQ31 5,14
127 83
5,14 M_B_A6 A6 DQ26 M_B_DQ24 5,14
122 84 251 252
5,14 M_B_A7 A7 DQ27 M_B_DQ29 5,14 VSS VSS
5,14
5,14
M_B_A8
M_B_A9
125
121 A8
A9
DQ28
DQ29
66
67
M_B_DQ28 5,14
M_B_DQ27 5,14
BYTE 3 247
243 VSS
VSS
VSS
VSS
248
244
146 79 239 238
5,14 M_B_A10_AP A10_AP DQ30 M_B_DQ25 5,14 VSS VSS
120 80 235 234
5,14 M_B_A11 A11 DQ31 M_B_DQ26 5,14 VSS VSS
119 174 231 230
5,14 M_B_A12 A12 DQ32 M_B_DQ39 5,14 VSS VSS
158 173 227 226
5,14 M_B_A13 A13 DQ33 M_B_DQ35 5,14 VSS VSS
151 187 223 222
5,14 M_B_A14_WE_N A14_WE# DQ34 M_B_DQ37 5,14 VSS VSS
156 186 217 218
5,14 M_B_A15_CAS_N A15_CAS# DQ35 M_B_DQ33 5,14 VSS VSS
5,14 M_B_A16_RAS_N
152
A16_RAS# DQ36
DQ37
170
169
M_B_DQ34 5,14
M_B_DQ38 5,14
BYTE 4 213
209 VSS
VSS
VSS
VSS
214
210
183 205 206
DQ38 M_B_DQ32 5,14 VSS VSS
182 201 202
DQ39 M_B_DQ36 5,14 VSS VSS
114 195 197 196
5,14 M_B_ACT_N ACT# DQ40 M_B_DQ41 5,14 VSS VSS
194 193 192
DQ41 M_B_DQ45 5,14 VSS VSS
143 207 189 188
5,14 DDR1_B_PARITY PARITY DQ42 M_B_DQ42 5,14 VSS VSS
C 116 208 185 184 C
5,14 DDR1_B_ALERT_N DIMM1_CHB_EVENT_N ALEART# DQ43 M_B_DQ47 5,14 VSS VSS
TP128
12,13,14,16 DDR4_DRAMRST_N
1
DDR4_DRAMRST_N
134
108 EVENT#
RESET#
DQ44
DQ45
191
190
M_B_DQ40 5,14
M_B_DQ44 5,14
BYTE 5 181
175 VSS
VSS
VSS
VSS
180
176
203 171 172
DQ46 M_B_DQ46 5,14 VSS VSS
+V_DIM_VREF_CA_CHB 164 204 167 168
VREFCA DQ47 M_B_DQ43 5,14 VSS VSS
216 107 106
DQ48 M_B_DQ54 5,14 VSS VSS
215 103 102
DQ49 M_B_DQ51 5,14 VSS VSS
228 99 98
DIMM_SMB_DAT DQ50 M_B_DQ53 5,14 VSS VSS
254 229 93 94
12,13,14,16 DIMM_SMB_DAT DIMM_SMB_CLK SDA DQ51 M_B_DQ55 5,14 VSS VSS
12,13,14,16 DIMM_SMB_CLK
253
SCL DQ52
DQ53
211
212
M_B_DQ52 5,14
M_B_DQ48 5,14
BYTE 6 89
85 VSS
VSS
VSS
VSS
90
86
224 81 82
DQ54 M_B_DQ50 5,14 VSS VSS
225 77 78
DQ55 M_B_DQ49 5,14 VSS VSS
166 237 73 72
SA2 DQ56 M_B_DQ62 5,14 VSS VSS
+3V 260 236 69 68
SA1 DQ57 M_B_DQ61 5,14 VSS VSS
256 249 65 64
SA0 DQ58 M_B_DQ60 5,14 VSS VSS
250 61 60
DQ59 M_B_DQ56 5,14 VSS VSS
92
91 CB0_NC
CB1_NC
DQ60
DQ61
232
233
M_B_DQ57 5,14
M_B_DQ59 5,14
BYTE 7 57
51 VSS
VSS
VSS
VSS
56
52
101 245 47 48
CB2_NC DQ62 M_B_DQ58 5,14 VSS VSS
105 246 43 44
CB3_NC DQ63 M_B_DQ63 5,14 VSS VSS
88 39 40
87 CB4_NC 35 VSS VSS 36
100 CB5_NC 13 31 VSS VSS 30
CB6_NC DQS0_T M_B_DQS_DP0 5,14 VSS VSS
104 34 27 26
CB7_NC DQS1_T M_B_DQS_DP1 5,14 VSS VSS
55 23 22
DQS2_T M_B_DQS_DP2 5,14 VSS VSS
76 19 18
+1.2V_VDDQ DQS3_T M_B_DQS_DP3 5,14 VSS VSS
179 15 14
DQS4_T M_B_DQS_DP4 5,14 VSS VSS
200 9 10
DQS5_T M_B_DQS_DP5 5,14 VSS VSS
12 221 5 6
DM0#/DBI0# DQS6_T M_B_DQS_DP6 5,14 VSS VSS
33 242 1 2
DM1#/DB1I# DQS7_T M_B_DQS_DP7 5,14 VSS VSS
54 97
75 DM2#/DBI2# DQS8_T
178 DM3#/DBI3# 11 262
DM4#/DBI4# DQS0_C M_B_DQS_DN0 5,14 MT2
199 32 261
DM5#/DBI5# DQS1_C M_B_DQS_DN1 5,14 MT1
220 53
DM6#/DBI6# DQS2_C M_B_DQS_DN2 5,14
241 74
DM7#/DBI7# DQS3_C M_B_DQS_DN3 5,14
96 177
B DM8#/DBI8# DQS4_C M_B_DQS_DN4 5,14 B
198 SO-DIMM-DDR4-260P SD-80886-1021 4MM
DQS5_C M_B_DQS_DN5 5,14
219
DQS6_C M_B_DQS_DN6 5,14
162 240
S2#/C0 DQS7_C M_B_DQS_DN7 5,14
165 95
S3#/C1 DQS8_C

SO-DIMM-DDR4-260P SD-80886-1021 4MM

SPD ADDRESS:0xA6

Decoupling Caps
BRD Note:
placed close to CHA DIMM0
+1.2V_VDDQ +2.5V_MEM
+V_DIM_VREF_CA_CHB

1
2

C136 C120 1 1
1

1
@ + C138 C139 C140 C141 C142 C143 C144 C145 C146 C147 C148 C149 C150 C151 C152
2.2U_0402_6.3V6M

0.1U_0402_25V6
1

330U_D2_2V_Y

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

1U_0402_10V6K

1U_0402_10V6K
2

2
2 2 2

A A

+0.6V_VTT
LENOVO.CRDN
Title
1 1 1 1 1 1 1 1 1 1 1 DDR4 CHB DIMM1
1

C154 C155 C156 C157 C158 C159 C160 C161 C162 C163 C164 1 C165 C166
Size Document Number
Rev V0.3
1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

10U_0603_10V

10U_0603_10V

1U_0402_10V6K
C
Skylake-H
2

2 2 2 2 2 2 2 2 2 2 2
Date: Thursday, May 26, 2016 Sheet 15 of 99
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

D D

DIMM_SMB_CLK
DDR VREF 19,46,51 PCH_SMB_CLK
19,46,51 PCH_SMB_DAT
R81
R82
1
1
2 0_0402_5%
2 0_0402_5% DIMM_SMB_DAT
DIMM_SMB_CLK 12,13,14,15
DIMM_SMB_DAT 12,13,14,15

BRD Note:
VREF trace width 20mils;spacing 20 mils to other signal/planes +1.2V_VDDQ

2
R84
470_0402_5%

+1.2V_VDDQ

1
R86 1 2 0_0402_5%
19 DRAM_CRESET_N DDR4_DRAMRST_N 12,13,14,15

2
R89 C171 C170
1K_0402_1% @
0.1U_0402_25V6 0.1U_0402_25V6

1
1

+V_CPU_VREF_CA
+V_DIM_VREF_CA_CHA

R90 1 2 2.2_0402_1%

C C172 C
2

0.022U_0402_25V7K C173
1 R91
1K_0402_1% 0.1U_0402_25V6
1
2

R92
1

24.9_0402_1%
1

+1.2V_VDDQ
2

R93 C174
1K_0402_1%
0.1U_0402_25V6
1
1

+V_CPU_VREF_DQ_CHB
+V_DIM_VREF_CA_CHB

R94 1 2 2.2_0402_1%
B B
2
C175
2

0.022U_0402_25V7K C176
1 R95
1K_0402_1% 0.1U_0402_25V6
1
2

R96
1

24.9_0402_1%
1

A A

LENOVO.CRDN
Title
DDR4-VREF
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 16 of 99
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

?
SPT-H_PCH
U2K
GSPI1_MOSI AT29
19 GSPI1_MOSI GPP_B22/GSPI1_MOSI
AR29 AL44
AV29 GPP_B21/GSPI1_MISO GPP_D9 AL36
+3VALW_PCH BC27 GPP_B20/GSPI1_CLK GPP_D10 AL35
GPP_B19/GSPI1_CS# GPP_D11 AJ39
GSPI0_MOSI BD28 GPP_D12 +3V
PCH_UART2_TXD 19 GSPI0_MOSI GPP_B18/GSPI0_MOSI
R534 1 2 49.9K_0402_1% BD27 AJ43
R266 1 2 49.9K_0402_1% PCH_UART2_RXD AW27 GPP_B17/GSPI0_MISO GPP_D16/ISH_UART0_CTS# AL43
AR24 GPP_B16/GSPI0_CLK GPP_D15/ISH_UART0_RTS# AK44 PCH_I2C_CLK2 R548 2 1 1K_0402_5%
+3VALW_PCH GPP_B15/GSPI0_CS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL AK45 PCH_I2C_CLK2 26 PCH_I2C_DATA2
EC R549 2 1 1K_0402_5%
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA PCH_I2C_DATA2 26
AV44
D
BA41 GPP_C9/UART0_TXD D
R535 1 2 49.9K_0402_1% PCH_UART2_CTS_N AU44 GPP_C8/UART0_RXD
R536 1 2 49.9K_0402_1% PCH_UART2_RTS_N AV43 GPP_C11/UART0_CTS#
GPP_C10/UART0_RTS#
AU41 BC38
AT44 GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H20/ISH_I2C0_SCL BB38
+3V AT43 GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_H19/ISH_I2C0_SDA
AU43 GPP_C13/UART1_TXD/ISH_UART1_TXD BD38
GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H22/ISH_I2C1_SCL BE39
R106 2 1 1K_0402_5% PCH_I2C_CLK1 PCH_UART2_CTS_N AN43 GPP_H21/ISH_I2C1_SDA
R107 2 1 1K_0402_5% PCH_I2C_DATA1 PCH_UART2_RTS_N AN44 GPP_C23/UART2_CTS#
PCH_UART2_TXD AR39 GPP_C22/UART2_RTS#
51 PCH_UART2_TXD PCH_UART2_RXD AR45 GPP_C21/UART2_TXD BC22
51 PCH_UART2_RXD GPP_C20/UART2_RXD GPP_A23/ISH_GP5
+3V BD18
PCH_I2C_CLK1 AR41 GPP_A22/ISH_GP4 BE21
LED Controller 47 PCH_I2C_CLK1 PCH_I2C_DATA1 AR44 GPP_C19/I2C1_SCL GPP_A21/ISH_GP3 BD22
PCH_I2C_CLK0 47 PCH_I2C_DATA1 PCH_I2C_CLK0 GPP_C18/I2C1_SDA GPP_A20/ISH_GP2
R109 2 1 1K_0402_5% AR38 BD21
R111 2 1 1K_0402_5% PCH_I2C_DATA0 SMART AMP 28 PCH_I2C_CLK0 PCH_I2C_DATA0 AT42 GPP_C17/I2C0_SCL GPP_A19/ISH_GP1 BB22
28 PCH_I2C_DATA0 GPP_C16/I2C0_SDA GPP_A18/ISH_GP0 BC19 FPBACK R97 2 @ 1 100K_0402_5%
AM44 GPP_A17/ISH_GP7
AJ44 GPP_D4/ISH_I2C2_SDA/ISH_I2C3_SDA
GPP_D23/ISH_I2C2_SCL/ISH_I2C3_SCL

SPT_PCH_H 11 OF 12
REV = 1.3 ? +3V

CAM_PWR_EN R103 1 2 10K_0402_5%

? RF_KILL_WIFI_N R99 1 2 10K_0402_5%


SPT-H_PCH
U2A
RF_KILL_BT_N R102 1 2 10K_0402_5%
BD17 BB27
GPP_A11/PME# GPP_B13/PLTRST# PCH_PLTRST_N 50
AG15 P43
RSVD GPP_G16/GSXCLK FPBACK 31
AG14 R39 +3V
RSVD GPP_G12/GSXDOUT LC_INT0_N 47
C AF17 R36 C
RSVD GPP_G13/GSXSLOAD DGPU_PWROK_N CAM_PWR_EN 90
AE17 R42 R270 1 @ 2 0_0402_5%
RSVD GPP_G14/GSXDIN DGPU_PWROK 52,68,80 GPU_EVENT_N
R41 R112 1 @ 2 10K_0402_5%
GPP_G15/GSXSRESET# EC_INT_N 26
CAD Note: AR19
TP2
AN17 AF41
Reserve for PCH strpping TP1 GPP_E3/CPU_GP0 AE44
PCH_SI BB29 GPP_E7/CPU_GP1 BC23
51 PCH_SI PCH_SO SPI0_MOSI GPP_B3/CPU_GP2 RF_KILL_BT_N 42
+3VALW_SPI BE30 BD24
PCH_CS0_N SPI0_MISO GPP_B4/CPU_GP3 RF_KILL_WIFI_N 42
BD31
R931 1 @ 2 10K_0402_5% PCH_SI PCH_SCK BC31 SPI0_CS0# BC36
AW31 SPI0_CLK GPP_H18/SML4ALERT# BE34
R936 1 @ 2 10K_0402_5% PCH_SO SPI0_CS1# GPP_H17/SML4DATA BD39
PCH_WP_N BC29 GPP_H16/SML4CLK BB36
PCH_CS0_N 51 PCH_WP_N PCH_HOLD_N SPI0_IO2 GPP_H15/SML3ALERT# GPU_EVENT_N 63
R937 1 @ 2 10K_0402_5% BD30 BA35
SPI0_IO3 GPP_H14/SML3DATA GC6_FB_EN_LS 68
AT31 BC35
R938 1 @ 2 10K_0402_5% PCH_SCK SPI0_CS2# GPP_H13/SML3CLK BD35
AN36 GPP_H12/SML2ALERT# AW35 +VCC_RTC
AL39 GPP_D1/SPI1_CLK GPP_H11/SML2DATA BD34
AN41 GPP_D0/SPI1_CS# GPP_H10/SML2CLK
AN38 GPP_D3/SPI1_MOSI BE11 PCH_INTRUDER_N PCH_INTRUDER_N R114 2 1 1M_0402_5%
AH43 GPP_D2/SPI1_MISO INTRUDER#
AG44 GPP_D22/SPI1_IO3
GPP_D21/SPI1_IO2
CAD Note:
SPT_PCH_H 1 OF 12
CRB use 330KR;DG use 1MR
REV = 1.3 ?

PLT_RST_N Buffer
+3V

SPI ROM 2
C179

+3VALW_PCH +3VALW_SPI 0.1U_0402_25V6


B
+3VALW_SPI 1 B

5
R115 2 1 0_0603_5% U4
EC/SSD/LAN/WLAN/CR/XDP

Vcc
1 2 R116 2 1 1K_0402_5% PCH_WP_N 2
C177 C178 PCH_PLTRST_N A 4 PLT_RST_N
PCH_HOLD_N_R Y PLT_RST_N 26,27,38,40,42,43,49,50,63
R118 2 1 1K_0402_5% 1
B

Gnd
10U_0402_6.3V6M 0.1U_0402_25V6
2 1

2
1
R126 2 @ 1 1K_0402_5% PCH_HOLD_N C180 74AUP1G08GW_SOT353-1 R123

3
@ AND Gate
CAD Note:PCH_HOLD_N(PCH SPI0_IO3) 2
100K_0402_5%

100P_0402_50V8J
PD:INTEL MOW for SKL-H Pre-ES1/ES1 sample

1
PCH_PLTRST_N R117 1 @ 2 0_0402_5% PLT_RST_N

+3VALW_SPI

PCH_CS0_N
U3 DISPLAY_MUX_SW Buffer
1 8
CS VCC
PCH_SO R119 2 1 15_0402_5% PCH_SO_R 2 7 PCH_HOLD_N_R R120 2 1 15_0402_5% PCH_HOLD_N
DO HOLD
PCH_WP_N R121 2 1 15_0402_5% PCH_WP_N_R 3 6 PCH_SCK_R R122 2 1 15_0402_5% PCH_SCK
WP CLK
CAD Note:DISPLAY_MUX_SW
4 5 PCH_SI_R R124 2 1 15_0402_5% PCH_SI
GND DI L=CPU output selected
H=dGPU output selected(default)
W25Q128FVSIQ_SO8
16MB
SA00005LW00
A A

LENOVO.CRDN
PCH_SCK_R
26 PCH_SCK_R PCH_SI
R125 2 @ 1 10K_0402_5% Title
PCH_CS0_N PCH-SPI/I2C/GPIO
26 PCH_CS0_N
CAD Note:PCH_SI
PCH_SI_R Size Document Number
26 PCH_SI_R PD:For EC Mirror Code feature C Rev V0.3
PCH_SO_R Skylake-H
26 PCH_SO_R
Date: Thursday, May 26, 2016 Sheet 17 of 99
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

USB2.0 Configuration
USB2 # Assignment OCx #
USB2 1 JUSB3(IO DB) USB_OC0_N
USB2 2 JUSB2 USB_OC1_N
Flexible I/O Configuration USB2 3 HD camera
I/O High Speed Signals Configuration DEVICE GEN USB2 4 KB
Port 7 USB3_7 / PCIE 1 AR (L0) USB2 5 BT
D Port 8 USB3_8 / PCIE 2 AR (L1) USB2 6 JUSB4(IO DB) USB_OC3_N D
U2005
Port 9 USB3_9 / PCIE 3 AR (L2) (Intel USB2 7 NC
Port 10 USB3_10 / PCIE 4 AR (L3) AR DP)
USB2 8 NC
Port 11 PCIE 5 NC USB2 9 NC
Port 12 PCIE 6 Card Reader U3001 PCIE 1x Gen2 USB2 10 NC
Port 13 PCIE 7 WLAN JWLAN1 PCIE 1x Gen2 USB2 11 NC
Port 14 PCIE 8 LAN U6 PCIE1x Gen1 USB2 12 NC
USB2 13 NC
USB2 14 NC

?
SPT-H_PCH
U2B

L27 AF5
2 DMI_MT_IR_0_DN DMI_RXN0 USB2N_1 USB2_DN1 49 USB3.0 PORT (IO)
N27 AG7
2 DMI_MT_IR_0_DP DMI_RXP0 USB2P_1 USB2_DP1 49
C27 AD5
2 DMI_IT_MR_0_DN DMI_TXN0 USB2N_2 USB2_DN2 41
B27 AD7 USB3.0 PORT
2 DMI_IT_MR_0_DP DMI_TXP0 USB2P_2 USB2_DP2 41
E24 AG8
2 DMI_MT_IR_1_DN DMI_RXN1 USB2N_3 USB2_DN3 31 HD CAMERA
G24 AG10
2 DMI_MT_IR_1_DP DMI_RXP1 USB2P_3 USB2_DP3 31
B28 AE1
2 DMI_IT_MR_1_DN DMI_TXN1 USB2N_4 USB2_DN4 48 KB
A28 DMI AE2
2 DMI_IT_MR_1_DP DMI_TXP1 USB2P_4 USB2_DP4 48
G27 AC2
2 DMI_MT_IR_2_DN DMI_RXN2 USB2N_5 USB2_DN5 42 BT
E26 AC3
2 DMI_MT_IR_2_DP DMI_RXP2 USB2P_5 USB2_DP5 42
B29 AF2
2 DMI_IT_MR_2_DN DMI_TXN2 USB2N_6 USB2_DN6 49 USB3.0 PORT (IO)
C29 AF3
2 DMI_IT_MR_2_DP DMI_TXP2 USB2P_6 USB2_DP6 49
C BRD Note: PCIE_RCOMP* 2 DMI_MT_IR_3_DN
L29
DMI_RXN3 USB2N_7
AB3 C
K29 USB 2.0 AB2
W=15mils;S=15mils; 2 DMI_MT_IR_3_DP
B30 DMI_RXP3 USB2P_7 AL8
4 mils PIPE GND shiedling required; 2 DMI_IT_MR_3_DN DMI_TXN3 USB2N_8
A30 AL7
2 DMI_IT_MR_3_DP DMI_TXP3 USB2P_8
Avoid routing next to clock USB2N_9
AA1
PCIE_RCOMPN B18 AA2
Lenght matched within 1% R129 1 2 100_0402_1% PCIE_RCOMPP C17 PCIE_RCOMPN USB2P_9 AJ8
PCIE_RCOMPP USB2N_10 AJ7
H15 USB2P_10 W2
38 PCIE1_TBT_RX_DN0 PCIE1_RXN/USB3_7_RXN USB2N_11
G15 W3
38 PCIE1_TBT_RX_DP0 PCIE1_RXP/USB3_7_RXP USB2P_11
A16 AD3
38 PCIE1_TBT_TX_DN0 B16 PCIE1_TXN/USB3_7_TXN USB2N_12 AD2

PCIe/USB 3
38 PCIE1_TBT_TX_DP0 B19 PCIE1_TXP/USB3_7_TXP USB2P_12 V2
38 PCIE2_TBT_TX_DN1 C19 PCIE2_TXN/USB3_8_TXN USB2N_13 V1
38 PCIE2_TBT_TX_DP1 E17 PCIE2_TXP/USB3_8_TXP USB2P_13 AJ11
38 PCIE2_TBT_RX_DN1 PCIE2_RXN/USB3_8_RXN USB2N_14 +3VALW_PCH
G17 AJ13
38 PCIE2_TBT_RX_DP1 PCIE2_RXP/USB3_8_RXP USB2P_14
L17 RP1
38 PCIE3_TBT_RX_DN2 PCIE3_RXN/USB3_9_RXN USB_OC0_N
K17 1 8
38 PCIE3_TBT_RX_DP2 PCIE3_RXP/USB3_9_RXP USB_OC2_N
B20 2 7
38 PCIE3_TBT_TX_DN2 C20 PCIE3_TXN/USB3_9_TXN USB_OC1_N 3 6
38 PCIE3_TBT_TX_DP2 E20 PCIE3_TXP/USB3_9_TXP AD43 USB_OC3_N 4 5
38 PCIE4_TBT_RX_DN3 PCIE4_RXN/USB3_10_RXN GPP_E9/USB2_OC0# USB_OC0_N 49
G19 AD42
38 PCIE4_TBT_RX_DP3 PCIE4_RXP/USB3_10_RXP GPP_E10/USB2_OC1# USB_OC1_N 41
B21 AD39 10K_8P4R_5%
38 PCIE4_TBT_TX_DN3 PCIE4_TXN/USB3_10_TXN GPP_E11/USB2_OC2# USB_OC2_N 41 USB_OC_N
A21 AC44 R875 2 1 10K_0402_5%
38 PCIE4_TBT_TX_DP3 PCIE4_TXP/USB3_10_TXP GPP_E12/USB2_OC3# USB_OC_N USB_OC3_N 49
K19 Y43
L19 PCIE5_RXN GPP_F15/USB2_OCB_4 Y41
D22 PCIE5_RXP GPP_F16/USB2_OCB_5 W44
C22 PCIE5_TXN GPP_F17/USB2_OCB_6 W43
G22 PCIE5_TXP GPP_F18/USB2_OCB_7
49 PCIE_CR_RX_DN PCIE6_RXN
49 PCIE_CR_RX_DP
E22
PCIE6_RXP BRD Note: USB2_COMP
PCIE_CR_TX_DN USB2_COMP
Card Reader 49 PCIE_CR_TX_C_DN
C181
C182
1
1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K PCIE_CR_TX_DP
B22
A23 PCIE6_TXN USB2_COMP
AG3 R130 1 2 113_0402_1%
Total length within 1 inch;
49 PCIE_CR_TX_C_DP L22 PCIE6_TXP AD10 USB_OTG_VBUSSENSE R62 2 1 1K_0402_5% S=15mils;
42 PCIE_WLAN_RX_DN PCIE7_RXN USB2_VBUSSENSE
42 PCIE_WLAN_RX_DP
K22
PCIE7_RXP
4 mils PIPE GND shiedling suggested
PCIE_WLAN_TX_DN
WLAN 42 PCIE_WLAN_TX_C_DN
42 PCIE_WLAN_TX_C_DP
C183
C184
1
1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K PCIE_WLAN_TX_DP
C23
B23 PCIE7_TXN
PCIE7_TXP
RSVD_AB13
AB13

K24 AG2 USB2_OTG_ID R63 2 1 1K_0402_5%


27 PCIE_LAN_RX_DN PCIE8_RXN USB2_ID
L24
B 27 PCIE_LAN_RX_DP PCIE_LAN_TX_DN PCIE8_RXP B
LAN 27 PCIE_LAN_TX_C_DN
27 PCIE_LAN_TX_C_DP
C185
C186
1
1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K PCIE_LAN_TX_DP
C24
B24 PCIE8_TXN
PCIE8_TXP GPD7/RSVD
BD14

SPT_PCH_H 2 OF 12
REV = 1.3 ?

BRD Note:PCIE BUS


All the AC-coupling caps placed close to device down or connector;
Non-interleaved breakout is required

A A

LENOVO.CRDN
Title
PCH-DMI/PCIE/USB2.0
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 18 of 99
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

R131 2 1 33_0402_5% HDA_BCLK_R ?


28 HDA_BCLK R132 2 1 33_0402_5% HDA_SYNC_R U2D SPT-H_PCH +3V
28 HDA_SYNC R134 2 1 33_0402_5% HDA_SDOUT_R
28 HDA_SDOUT R2286 1 2 0_0402_5%
26 ME_FLASH HDA_BCLK_R PCH_CLKRUN_N R136 2
BA9
HDA_BCLK
BB17
GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF# AW22 CAD Note:PCH_VRALERT_N 1 8.2K_0402_5%
HDA_RST_N_R BD8 PCH_CLKRUN_N
HDA_SDIN BE7 HDA_RST# GPP_A8/CLKRUN# ICC max throttling indicator for the
HDA_RST_N_R 28 HDA_SDIN HDA_SDI0 PCH voltage regulators
R135 2 @ 1 33_0402_5% BC8 AR15
28 HDA_RST_N HDA_SDI1 GPD11/LANPHYPC +3VALW_PCH
CAD Note:HDA_RST_N HDA_SDOUT_R BB7 AV13
HDA_SYNC_R BD9 HDA_SDO GPD9/SLP_WLAN#
Reserve and use the codec internal RST# default HDA_SYNC BC14 DRAM_CRESET_N SYS_RESET_N R143 1 2 10K_0402_5%
D DRAM_RESET# PCH_VRALERT_N DRAM_CRESET_N 16 D
BD1 BD23
BE2 RSVD_BD1 GPP_B2/VRALERT# AL27 PCH_VRALERT_N R137 1 @ 2 10K_0402_5%
RSVD_BE2 GPP_B1 AR27
AM1 AUDIO GPP_B0 N44 PCIE_WAKE_N R138 1 2 10K_0402_5%
AN2 DISPA_SDO GPP_G17/ADR_COMPLETE AN24 MPHY_EXT_PWR_GATE_N 1 TP76
AM2 DISPA_SDI GPP_B11 AY1 SYS_PWROK PM_BATLOW_N R139 2 1 8.2K_0402_5%
DISPA_BCLK SYS_PWROK SYS_PWROK 26
AL42 BC13 PCIE_WAKE_N AC_PRESENT R142 1 2 10K_0402_5%
GPP_D8/I2S0_SCLK WAKE# PCIE_WAKE_N 38,42
AN42 BC15
AM43 GPP_D7/I2S0_RXD GPD6/SLP_A# AV15 PCH_LAN_WAKE_N R288 1 2 10K_0402_5%
AJ33 GPP_D6/I2S0_TXD SLP_LAN# BC26
AH44 GPP_D5/I2S0_SFRM GPP_B12/SLP_S0# AW15 SLP_S3_N_R R144 1 2 0_0402_5% PCH_PWRBTN_N R381 2 1 100K_0402_5%
GPP_D20/DMIC_DATA0 GPD4/SLP_S3# SLP_S4_N_R SLP_S3_N 26,38
AJ35 BD15 R145 1 2 0_0402_5%
PM_PCH_PWROK GPP_D19/DMIC_CLK0 GPD5/SLP_S4# SLP_S5_N SLP_S4_N 26,76
R147 1 @ 2 10K_0402_5% AJ38 BA13 1 TP71
AJ42 GPP_D18/DMIC_DATA1 GPD10/SLP_S5# SYS_PWROK R146 1 @ 2 10K_0402_5%
R149 1 2 10K_0402_5% PM_RSMRST_N GPP_D17/DMIC_CLK1 AN15 SUSCLK
GPD8/SUSCLK PM_BATLOW_N SUSCLK 42
BD13 SUSCLK R148 1 @ 2 10K_0402_5%
R547 1 @ 2 10K_0402_5% PCH_GPP_B23 GPD0/BATLOW# BB19 SUSACK_N 1 TP72
RTCRST_N BC10 GPP_A15/SUSACK# BD19 SUSPWRDNACK 1 TP73
SRTCRST_N BB10 RTCRST# GPP_A13/SUSWARN#/SUSPWRDNACK
SRTCRST#
CAD Note:PCH_GPP_B23
AW11 BD11 PCH_LAN_WAKE_N
Reserve for PCH strpping 26 PM_PCH_PWROK
BA11 PCH_PWROK GPD2/LAN_WAKE# BB15 AC_PRESENT
26 PM_RSMRST_N RSMRST# GPD1/ACPRESENT SLP_SUS_N AC_PRESENT 26
SLP_SUS#
BB13 1 TP74 CAD Note:PCH_PWRBTN_N
AV11 AT13 PCH_PWRBTN_N
+3VALW_PCH SMBALERT_N BB41 DSW_PWROK GPD3/PWRBTN# AW1 SYS_RESET_N R178 1 @ 2 0_0402_5%
PCH_PWRBTN_N 26,51 PCH internal PU and 16ms de-bounce
SMB_CLK GPP_C2/SMBALERT# SYS_RESET# HDA_SPKR FP_RST_N 51
AW44 BD26

SMBUS
SML0_CLK 76 SMB_CLK SMB_DATA GPP_C0/SMBCLK GPP_B14/SPKR H_PWRGD HDA_SPKR 28
R150 2 1 1K_0402_5% BB43 AM3
SML0_DATA 76 SMB_DATA SML0ALERT_N GPP_C1/SMBDATA PROCPWRGD H_PWRGD 6
R151 2 1 1K_0402_5% BA40
SML0_CLK AY44 GPP_C5/SML0ALERT# AT2 PCH_ITP_PMODE
SML0_DATA GPP_C3/SML0CLK ITP_PMODE PCH_JTAGX PCH_ITP_PMODE 51
BB39 AR3
SMB_CLK PCH_GPP_B23 GPP_C4/SML0DATA JTAGX PCH_JTAG_TMS PCH_JTAGX 51
R153 2 1 1K_0402_5% AT27 JTAG AR2
SMB_DATA SML1_CLK GPP_B23/SML1ALERT#/PCHHOT# JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TMS 51
R155 2 1 1K_0402_5% AW42 AP1
SML1_DATA GPP_C6/SML1CLK JTAG_TDO PCH_JTAG_TDI PCH_JTAG_TDO 51
AW45 AP2
GPP_C7/SML1DATA JTAG_TDI PCH_JTAG_TCK PCH_JTAG_TDI 51
AN3 1 TP79
R158 2 1 1K_0402_5% SML1_CLK JTAG_TCK
R159 2 1 1K_0402_5% SML1_DATA
C SPT_PCH_H 4 OF 12 C
REV = 1.3 ?

PCH Straps SMBus Isolation


+VCC_RTC
CAD Note:
+3V +3V
CRB use 30.1KR;DG use 20KR ME RESET
R160 2 1 20K_0402_1%
1
SRTCRST_N
1:SAVE ME (Default) *
C187
SRTCRST_N

1
1U_0402_10V6K
0:CLEAR ME R161 R162
2 2.2K_0402_5% 2.2K_0402_5%
2
1 TP77
CMOS RESET

2
SMB_CLK 6 1 PCH_SMB_CLK 16,46,51
R163 2 1 20K_0402_1%
1
RTCRST_N
1:SAVE CMOS (Default) * 5
Q1A
SODIMM/TP/XDP
C188
RTCRST_N AO5804EL_SC89-6
1U_0402_10V6K
0:CLEAR CMOS SMB_DATA 3 4
PCH_SMB_DAT 16,46,51
2 1 TP78
Q1B
AO5804EL_SC89-6
Top Swap MODE
+3V
B
R164 2 @ 1 1K_0402_5% HDA_SPKR 1:Enabled +3V +3V B

HDA_SPKR
0:Disabled(Default),Internal PD *

1
+3VALW_PCH R165 R166
Flash Descriptor Security Override 2 2.2K_0402_5% 2.2K_0402_5%
R167 2 @ 1 1K_0402_5% HDA_SDOUT

1:Disabled

2
SML1_CLK
HDA_SDOUT 6 1 EC_SMB_CLK1 26,45,63
0:Enabled(Default),Internal PD * 5
Q2A
AO5804EL_SC89-6
EC
SML1_DATA 3 4
+3V TCO Timer System No Reboot mode EC_SMB_DAT1 26,45,63
Q2B
R168 2 @ 1 1K_0402_5%
GSPI0_MOSI 17 1:Enable "No reboot" mode AO5804EL_SC89-6

GSPI0_MOSI
0:Disable (Default),Internal PD *
+3V
Intel ME TLS cipher suite EC Clear CMOS
R169 1 @ 2 4.7K_0402_5% SMBALERT_N 1:Enabled
SMBALERT_N
0:Disabled(Default),Internal PD *
+3V CAD Note:EC_CLEAR_CMOS RTCRST_N

A R170 2 @ 1 1K_0402_5% SML0ALERT_N eSPI or LPC bus for EC LOW:Keep CMOS 1


A
Hi:Clear CMOS
R372 2 @ 1 20K_0402_1%
1:eSPI 26 EC_CLEAR_CMOS
EC_CLEAR_CMOS 2
Q12
DMG1012T-7_SOT523-3 LENOVO.CRDN
SML0ALERT_N
*
2

0:LPC(Default),Internal PD R428
1
C401
Title
PCH-HDA/PM/SMBUS/STRAP
@ 3
10K_0402_5%

+3V
0.1U_0402_25V6

Size Document Number


2 C Rev V0.3
Boot BIOS Destination Bit 10 Skylake-H
1

R171 2 @ 1 1K_0402_5%
GSPI1_MOSI 17
Date: Thursday, May 26, 2016 Sheet 19 of 99
R506 2 @ 1 20K_0402_1%
1:LPC "PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
GSPI1_MOSI
0:SPI(Default),Internal PD * obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

Flexible I/O Configuration


I/O High Speed Signals Configuration DEVICE GEN
Port 15 SATA 0A / PCIE 9 M.2 SSD2 (L0) / SATA0
Port 16 SATA 1A / PCIE 10 M.2 SSD2 (L1)
M.2 SSD2 (L2) JSSD2 PCIE 4x Gen 3
Port 17 / PCIE 11 /SATA Gen 3
Port 18 / PCIE 12 M.2 SSD2 (L3)
Port 19 SATA 0B / PCIE 13 M.2 SSD12(L0)
D Port 20 SATA 1B / PCIE 14 M.2 SSD1 (L1) PCIE 4 x Gen 3 D
JSSD1
Port 21 SATA 2 / PCIE 15 M.2 SSD1 (L2)
Port 22 SATA 3 / PCIE 16 M.2 SSD1 (L3)
Port 23 SATA 4 / PCIE 17 SATA HDD U14 SATA Gen 3
Port 24 SATA 5 / PCIE 18 NC
Port 25 SATA6 / PCIE 19 NC
Port 26 SATA7 / PCIE 20 NC

?
SPT-H_PCH
U2C

AV2 L37
AV3 CL_CLK PCIE19_RXN/SATA6_RXN L39
AW2 CL_DATA CLINK PCIE19_RXP/SATA6_RXP H43
CL_RST# PCIE19_TXN/SATA6_TXN H44
R44 PCIE19_TXP/SATA6_TXP
R43 GPP_G8/FAN_PWM_0 AD44 PCH_GPP_E8 1 TP160
U39 GPP_G9/FAN_PWM_1 GPP_E8/SATALED#
N42 GPP_G10/FAN_PWM_2
GPP_G11/FAN_PWM_3
U43 FAN G35 PCIE13_SSD1_RX_DN0
GPP_G0/FAN_TACH_0 PCIE13_RXN/SATA0B_RXN PCIE13_SSD1_RX_DP0 PCIE13_SSD1_RX_DN0 43
U42 E35
GPP_G1/FAN_TACH_1 PCIE13_RXP/SATA0B_RXP PCIE13_SSD1_TX_DN0 PCIE13_SSD1_RX_DP0 43
U41 C36
EC_SCI_N GPP_G2/FAN_TACH_2 PCIE13_TXN/SATA0B_TXN PCIE13_SSD1_TX_DP0 PCIE13_SSD1_TX_DN0 43
C M44 B36 C
26 EC_SCI_N GPP_G3/FAN_TACH_3 PCIE13_TXP/SATA0B_TXP PCIE13_SSD1_TX_DP0 43
U36
P44 GPP_G4/FAN_TACH_4 D39 PCIE14_SSD1_RX_DN1
GPP_G5/FAN_TACH_5 PCIE14_RXN/SATA1B_RXN PCIE14_SSD1_RX_DP1 PCIE14_SSD1_RX_DN1 43
T45 E37
GPP_G6/FAN_TACH_6 PCIE14_RXP/SATA1B_RXP PCIE14_SSD1_TX_DN1 PCIE14_SSD1_RX_DP1 43
T44
GPP_G7/FAN_TACH_7 PCIE14_TXN/SATA1B_TXN
B38
PCIE14_SSD1_TX_DN1 43 Gen3

PCIe/SATA
+3V C38 PCIE14_SSD1_TX_DP1
PCIE14_TXP/SATA1B_TXP PCIE14_SSD1_TX_DP1 43
AB33
AB35 GPP_F10/SCLOCK F41 PCIE15_SSD1_RX_DN2
EC_SCI_N GPP_F11/SLOAD PCIE15_RXN/SATA2_RXN PCIE15_SSD1_RX_DP2 PCIE15_SSD1_RX_DN2 43
R173 1 2 10K_0402_5% AA44
AA45 GPP_F13/SDATAOUT0
GPP_F12/SDATAOUT1
PCIE15_RXP/SATA2_RXP
PCIE15_TXN/SATA2_TXN
E41
B39 PCIE15_SSD1_TX_DN2 PCIE15_SSD1_RX_DP2 43
PCIE15_SSD1_TX_DN2 43
PCIE SSD1
A39 PCIE15_SSD1_TX_DP2
PCIE15_TXP/SATA2_TXP PCIE15_SSD1_TX_DP2 43
D43 PCIE16_SSD1_RX_DN3
PCIE16_RXN/SATA3_RXN PCIE16_SSD1_RX_DP3 PCIE16_SSD1_RX_DN3 43
J45 E42
PCIE20_TXP/SATA7_TXP PCIE16_RXP/SATA3_RXP PCIE16_SSD1_TX_DN3 PCIE16_SSD1_RX_DP3 43
K44 A41
PCIE20_TXN/SATA7_TXN PCIE16_TXN/SATA3_TXN PCIE16_SSD1_TX_DP3 PCIE16_SSD1_TX_DN3 43
N38 A40
PCIE20_RXP/SATA7_RXP PCIE16_TXP/SATA3_TXP PCIE16_SSD1_TX_DP3 43
N39
PCIE20_RXN/SATA7_RXN

G31 PCIE9_SSD2_RX_DN0
PCIE9_RXN/SATA0A_RXN PCIE9_SSD2_RX_DP0 PCIE9_SSD2_RX_DN0 43
H31
PCIE9_RXP/SATA0A_RXP PCIE9_SSD2_TX_DN0 PCIE9_SSD2_RX_DP0 43
C31
PCIE9_TXN/SATA0A_TXN PCIE9_SSD2_TX_DP0 PCIE9_SSD2_TX_DN0 43
B31
PCIE9_TXP/SATA0A_TXP PCIE9_SSD2_TX_DP0 43
G44
G45 PCIE18_TXP/SATA5_TXP G29 PCIE10_SSD2_RX_DN1
PCIE18_TXN/SATA5_TXN PCIE10_RXN/SATA1A_RXN PCIE10_SSD2_RX_DP1 PCIE10_SSD2_RX_DN1 43
G37 E29
PCIE18_RXP/SATA5_RXP PCIE10_RXP/SATA1A_RXP PCIE10_SSD2_TX_DN1 PCIE10_SSD2_RX_DP1 43
K37 C32
PCIE18_RXN/SATA5_RXN PCIE10_TXN/SATA1A_TXN PCIE10_SSD2_TX_DP1 PCIE10_SSD2_TX_DN1 43

44 SATA_TX_DP0 SATA_TX_DP0
SATA_TX_DN0
F45
PCIE17_TXP/SATA4_TXP
PCIE10_TXP/SATA1A_TXP
B32

PCIE11_SSD2_RX_DN2
PCIE10_SSD2_TX_DP1 43 Gen3
SATA HDD 44 SATA_TX_DN0
SATA_RX_DP0
E45
PCIE17_TXN/SATA4_TXN PCIE11_RXN
L31
PCIE11_SSD2_RX_DP2 PCIE11_SSD2_RX_DN2 43
44
44
SATA_RX_DP0
SATA_RX_DN0 SATA_RX_DN0
H40
H42 PCIE17_RXP/SATA4_RXP
PCIE17_RXN/SATA4_RXN
PCIE11_RXP
PCIE11_TXN
K31
C33 PCIE11_SSD2_TX_DN2 PCIE11_SSD2_RX_DP2 43
PCIE11_SSD2_TX_DN2 43
PCIE SSD2
B33 PCIE11_SSD2_TX_DP2
PCIE11_TXP PCIE11_SSD2_TX_DP2 43
G33 PCIE12_SSD2_RX_DN3
PCIE12_RXN PCIE12_SSD2_RX_DP3 PCIE12_SSD2_RX_DN3 43
AB44 H33
GPP_F4/SATAXPCIE7/SATAGP7 PCIE12_RXP PCIE12_SSD2_TX_DN3 PCIE12_SSD2_RX_DP3 43
AC43 B35
GPP_F3/SATAXPCIE6/SATAGP6 PCIE12_TXN PCIE12_SSD2_TX_DP3 PCIE12_SSD2_TX_DN3 43
AD38 A35
B GPP_F2/SATAXPCIE5/SATAGP5 PCIE12_TXP PCIE12_SSD2_TX_DP3 43 B
AD31
AD35 GPP_F1/SATAXPCIE4/SATAGP4
AG39 GPP_F0/SATAXPCIE3/SATAGP3
AG35 GPP_E2/SATAXPCIE2/SATAGP2 W36
AG36 GPP_E1/SATAXPCIE1/SATAGP1 GPP_F21/EDP_BKLTCTL W35
GPP_E0/SATAXPCIE0/SATAGP0 HOST GPP_F20/EDP_BKLTEN W42
GPP_F19/EDP_VDDEN
AJ3 PCH_THERMTRIP_N R287 1 2 604_0402_1%
THERMTRIP# PCH_PECI H_THRMTRIP_N 6,63,68
AL3 R174 1 2 12.1_0402_5%
PECI H_PECI 6,26
AJ4 H_PM_SYNC_R R175 1 2 33_0402_5%
PM_SYNC CPU_PLTRST_N_R H_PM_SYNC 6
AK2 R176 1 2 0_0402_5%
PLTRST_PROC# H_PM_DOWN CPU_PLTRST_N 6
AH2
PM_DOWN H_PM_DOWN 6

1
SPT_PCH_H 3 OF 12 R177
REV = 1.3 ? @

10K_0402_5%
2
BRD Note:PCIE BUS
All the AC-coupling caps placed close to connector side;
Non-interleaved breakout is required

A A

LENOVO.CRDN
Title
PCH-PCIE/SATA/HOST
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 20 of 99
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

Flexible I/O Configuration


I/O High Speed Signals Configuration DEVICE OCx #
Port 1 USB3 1 Capable of OTG USB3.0 JUSB3(IO DB) USB_OC0_N
Port 2 USB2 3 / SSIC 1 NC
Port 3 USB3 3 / SSIC 2 USB3.0 JUSB2 USB_OC1_N
D Port 4 USB3 4 NC D

Port 5 USB3 5 NC
Port 6 USB3 6 USB3.0 JUSB4(IO DB) USB_OC3_N

+3V ?
SPT-H_PCH
U2F
C11
USB3_1_TXN USB3_TX_DN1 49
R179 2 1 10K_0402_5% SERIRQ AT22 B11 USB3_TX_DP1 49

LPC/eSPI
26 LPC_AD0_ESPI_IO0 GPP_A1/LAD0/ESPI_IO0 USB3_1_TXP USB3.0 PORT IO
AV22 B7 USB3_RX_DN1 49
H_A20GATE 26 LPC_AD1_ESPI_IO1 GPP_A2/LAD1/ESPI_IO1 USB3_1_RXN
R180 2 1 10K_0402_5% AT19 A7 USB3_RX_DP1 49
26 LPC_AD2_ESPI_IO2 GPP_A3/LAD2/ESPI_IO2 USB3_1_RXP
BD16
KBRST_N 26 LPC_AD3_ESPI_IO3 GPP_A4/LAD3/ESPI_IO3
R181 1 2 10K_0402_5% B12
BE16 USB3_2_TXN/SSIC_1_TXN A12
EC_SMI_N 26 LPC_FRAME_N_ESPI_CS_N GPP_A5/LFRAME#/ESPI_CS0# USB3_2_TXP/SSIC_1_TXP
R182 1 2 10K_0402_5% BA17 C8
26 SERIRQ GPP_A6/SERIRQ/ESPI_CS1# USB3_2_RXN/SSIC_1_RXN
AW17 B8
26 H_A20GATE GPP_A7/PIRQA#/ESPI_ALERT0# USB3_2_RXP/SSIC_1_RXP
AT17
26 KBRST_N GPP_A0/RCIN#/ESPI_ALERT1#
BC18 B15
26 LPC_PD_N_ESPI_RST_N GPP_A14/SUS_STAT#/ESPI_RESET# USB3_6_TXN USB3_TX_DN6 49
+3V C15 USB3_TX_DP6 49
USB3_6_TXP K15 USB3.0 PORT IO
USB3_6_RXN USB3_RX_DN6 49

USB
R183 1 2 22_0402_5% CK_LPC/ESPI_CLK_R BC17 K13
26 CK_LPC/ESPI_CLK GPP_A9/CLKOUT_LPC0/ESPI_CLK USB3_6_RXP USB3_RX_DP6 49
R303 2 1 10K_0402_5% PCH_GPP_G18 CAD Note: TP184 1 CK_LPC1 AV19
GPP_A10/CLKOUT_LPC1 B14
LPC:24M Hz USB3_5_TXN
eSPI:20/30/60M Hz 26 EC_SMI_N
M45
GPP_G19/SMI# USB3_5_TXP
C14 BRD Note:USB3.0
TP122 1 PCH_GPP_G18 N43 G13
GPP_G18/NMI# USB3_5_RXN H13
Non-interleaved breakout is required
USB3_5_RXP
BOARD_ID2 AE45 D13
GPP_E6/DEVSLP2 USB3_3_TXP/SSIC_2_TXP USB3_TX_DP3 41
BOARD_ID1 AG43 C13
GPP_E5/DEVSLP1 USB3_3_TXN/SSIC_2_TXN USB3_TX_DN3 41
BOARD_ID0 AG42 A9 USB3.0 PORT
GPP_E4/DEVSLP0 USB3_3_RXP/SSIC_2_RXP USB3_RX_DP3 41
TP169 1 PCH_GPP_F9 AB39 B10
GPP_F9/DEVSLP7 USB3_3_RXN/SSIC_2_RXN USB3_RX_DN3 41
C TP168 1 PCH_GPP_F8 AB36 C

SATA
TP171 1 PCH_GPP_F7 AB43 GPP_F8/DEVSLP6 B13
TP170 1 PCH_GPP_F6 AB42 GPP_F7/DEVSLP5 USB3_4_TXP A14
AB41 GPP_F6/DEVSLP4 USB3_4_TXN G11
GPP_F5/DEVSLP3 USB3_4_RXP E11
USB3_4_RXN

SPT_PCH_H 6 OF 12
REV = 1.3 ?

B B

+3V

BOARD_ID2 BOARD_ID1 BOARD_ID0 Description


2

R856 R185 R186


10K_0402_5%
10K_0402_5%

10K_0402_5%

0 0 0
1

BOARD_ID2 0 0 1
BOARD_ID1

BOARD_ID0
0 1 0
0 1 1
2

R855 R187 R188 1 0 0


A @ @ @ A

1 0 1
10K_0402_5%

10K_0402_5%

10K_0402_5%
1

LENOVO.CRDN
1 1 0 Title
PCH-USB3.0/LPC
1 1 1 Size Document Number
Rev V0.3
C
Skylake-H
Date: Thursday, May 26, 2016 Sheet 21 of 99
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

+3V
RP2
1 8 CK_REQ_PEG1_N
2 7 CK_REQ_SSD2_N
3 6 CK_REQ_LAN_N
4 5 CK_REQ_CR_N

10K_8P4R_5%
D D
+3V

R787 1 2 10K_0402_5% CK_REQ_WLAN_N

+3V

R304 1 2 10K_0402_5% CK_REQ_SSD1_N

R309 1 2 10K_0402_5% CK_REQ_TBT_N

?
SPT-H_PCH
U2G

AR17 L1
GPP_A16/CLKOUT_48 CLKOUT_ITPXDP CK_XDP_N 51
L2
CLKOUT_ITPXDP_P CK_XDP_P 51
G1
6 CK_CPU_24M_P F1 CLKOUT_CPUNSSC_P
6 CK_CPU_24M_N CLKOUT_CPUNSSC J1
CLKOUT_CPUPCIBCLK CK_CPU_PCIBCLK_N 6
G2 J2
6 CK_CPU_BCLK_P CLKOUT_CPUBCLK_P CLKOUT_CPUPCIBCLK_P CK_CPU_PCIBCLK_P 6
H2
6 CK_CPU_BCLK_N CLKOUT_CPUBCLK
BRD Note: XCLK_BIASREF PCH_XTAL24_OUT A5 N7
PCH_XTAL24_IN XTAL24_OUT CLKOUT_PCIE_N0 CK_PEG1_N 52
Ground reference;Max via:2 A6
XTAL24_IN CLKOUT_PCIE_P0
N8
CK_PEG1_P 52 dGPU
Isolation spacing:20mils +VCCF24_1P0_L R189 2 1 2.7K_0402_0.5% XCLK_BIASREF E1 L7
XCLK_BIASREF CLKOUT_PCIE_N1
Segment Length:100mils;Total length:1000mils CLKOUT_PCIE_P1
L5
PCH_RTC_X1 BC9
VSS shield recommened;S:W:S=6:4:6 PCH_RTC_X2 BD10 RTCX1 D3
RTCX2 CLKOUT_PCIE_N2 CK_WLAN_N 42
C
52 CK_REQ_PEG1_N
BC24
GPP_B5/SRCCLKREQ0#
CLKOUT_PCIE_P2
F2
CK_WLAN_P 42 WLAN C
AW24 E5
GPP_B6/SRCCLKREQ1# CLKOUT_PCIE_N3 CK_CR_N 49
42
49
CK_REQ_WLAN_N
CK_REQ_CR_N
AT24
BD25 GPP_B7/SRCCLKREQ2#
GPP_B8/SRCCLKREQ3#
CLKOUT_PCIE_P3
G4
CK_CR_P 49 Card Reader
BB24 D5
43 CK_REQ_SSD2_N GPP_B9/SRCCLKREQ4# CLKOUT_PCIE_N4 CK_PCIE_SSD2_N 43
27 CK_REQ_LAN_N
BE25
AT33 GPP_B10/SRCCLKREQ5#
GPP_H0/SRCCLKREQ6#
CLKOUT_PCIE_P4
E6
CK_PCIE_SSD2_P 43 PCIE SSD2
AR31 D8
GPP_H1/SRCCLKREQ7# CLKOUT_PCIE_N5 CK_LAN_N 27
38 CK_REQ_TBT_N
43 CK_REQ_SSD1_N
BD32
BC32 GPP_H2/SRCCLKREQ8#
GPP_H3/SRCCLKREQ9#
CLKOUT_PCIE_P5
D7
CK_LAN_P 27 LAN
BB31 R8
BC33 GPP_H4/SRCCLKREQ10# CLKOUT_PCIE_N6 R7
BA33 GPP_H5/SRCCLKREQ11# CLKOUT_PCIE_P6
AW33 GPP_H6/SRCCLKREQ12# U5
BB33 GPP_H7/SRCCLKREQ13# CLKOUT_PCIE_N7 U7
BD33 GPP_H8/SRCCLKREQ14# CLKOUT_PCIE_P7
GPP_H9/SRCCLKREQ15# W10
CLKOUT_PCIE_N8 CK_TBT_N 38
R13
R11 CLKOUT_PCIE_N15
CLKOUT_PCIE_P15
CLKOUT_PCIE_P8
W11
CK_TBT_P 38 TBT
N3
CLKOUT_PCIE_N9 CK_PCIE_SSD1_N 43
P1
R2 CLKOUT_PCIE_N14
CLKOUT_PCIE_P14
CLKOUT_PCIE_P9
N2
CK_PCIE_SSD1_P 43 PCIE SSD1
P3
W7 CLKOUT_PCIE_N10 P2
Y5 CLKOUT_PCIE_N13 CLKOUT_PCIE_P10
CLKOUT_PCIE_P13 R3
U2 CLKOUT_PCIE_N11 R4
U3 CLKOUT_PCIE_N12 CLKOUT_PCIE_P11
CLKOUT_PCIE_P12

SPT_PCH_H 7 OF 12
REV = 1.3 ?

B B

BRD Note:
Z0=50 ohm +-15%;Ground reference;Max via:2
Group spacing:15mils;Isolation spacing:20mils
Segment Length:100mils;Total length:1000mils;Length match:100mils
VSS shield recommened;S:W:S=6:4:6
CAD Note:
Max crystal ESR 50K ohm
R190 2 1 1M_0402_5%

C205 PCH_RTC_X1

10P_0402_50V8J
2

4
Y2
1

R192 PCH_XTAL24_IN 1 3 PCH_XTAL24_OUT


Y1 10M_0402_5%

2
32.768KHZ_9PF_CM8V-T1A 1 24MHZ_8PF_EXS00A-CS07257 1
2

C206 C207
C208 PCH_RTC_X2 10P_0402_50V8J 10P_0402_50V8J
2 2
10P_0402_50V8J

A A

LENOVO.CRDN
Title
PCH-CLOCK
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 22 of 99
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

D D

?
U2E
SPT-H_PCH
+3V
Reseved for UMA debug.
Hi Active AW4 BB3
30 CPU_DPB_HPD GPP_I0/DDPB_HPD0 GPP_I7/DDPC_CTRLCLK CPU_DPB_CTRL_CLK
AY2 BD6 R198 2 1 2.2K_0402_5%
AV4 GPP_I1/DDPC_HPD1 GPP_I8/DDPC_CTRLDATA BA5 CPU_DPB_CTRL_CLK
BA4 GPP_I2/DDPD_HPD2 GPP_I5/DDPB_CTRLCLK BC4 CPU_DPB_CTRL_DATA CPU_DPB_CTRL_DATA R199 2 1 2.2K_0402_5%
GPP_I3/DDPE_HPD3 GPP_I6/DDPB_CTRLDATA BE5
GPP_I9/DDPD_CTRLCLK BE6
GPP_I10/DDPD_CTRLDATA
Y44
GPP_F14 DGPU_HOLD_RST_N 63
100K_0402_5% 1 2 R934 CPU_EDP_HPD BD7 V44
GPP_I4/EDP_HPD GPP_F23 DGPU_PWR_EN 68,69
W39
GPP_F22 GPU_ALL_PGOOD 68
L43
GPP_G23 TBT_CIO_PLUG_EVENT_N 38
L44
GPP_G22 TBT_USB_PWR_EN 38
U35
GPP_G21 TBT_FORCE_PWR 38,40
R35
GPP_G20 TBT_CIO_PWR_EN 38
BD36
GPP_H23
C C
+3V

SPT_PCH_H 5 OF 12 DGPU_PWR_EN R108 2 1 10K_0402_5%


REV = 1.3 ?
DGPU_HOLD_RST_N R110 1 2 10K_0402_5%

GPU_ALL_PGOOD R113 1 @ 2 10K_0402_5%

?
B SPT-H_PCH B
U2J

AR22
BD2 RSVD W13
BD45 VSS RSVD U13
BD44 VSS RSVD P31
BE44 VSS RSVD N31
D45 VSS RSVD
A42 VSS P27
B45 VSS RSVD R27
B44 VSS RSVD N29
A4 VSS RSVD P29
A3 VSS RSVD AN29
B2 VSS RSVD R24
A2 VSS RSVD P24
B1 VSS RSVD AT3 PCH_XDP_PREQ_N
VSS PREQ# PCH_XDP_PRDY_N PCH_XDP_PREQ_N 51
BB1 AT4
VSS PRDY# PCH_TRST_N PCH_XDP_PRDY_N 51
BC1 AY5
VSS CPU_TRST# PCH_2_CPU_TRIGGER_R PCH_TRST_N 51
A44
VSS PCH_TRIGOUT
AL2 R203 2 1 33_0402_5%
PCH_2_CPU_TRIGGER 6 CAD Note:
AK1 CPU_2_PCH_TRIGGER
C1 PCH_TRIGIN CPU_2_PCH_TRIGGER 6 CRB use 30R;DG use 0R
D1 RSVD
RSVD

SPT_PCH_H 10 OF 12
REV = 1.3 ?

A A

LENOVO.CRDN
Title
PCH-DISPLAY/RSVD
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 23 of 99
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

+1.0VALW +VCCPRIM_1P0
@
2.899A +3VALW_PCH +3VALW
PJ16 2 1 JUMP_43X118
2 1 @
+VCCPRIM_1P0 ? PJ18
SPT-H_PCH
U2H
+1.0VALW +1.0VALW_PCH
NO CAP AA23
@ AA26 VCCPRIM_1P0
PJ17 AA28 VCCPRIM_1P0 AL22
VCCPRIM_1P0 VCCPRIM_1P0 +VCCFHV_2P8
AC23

CORE
AC26 VCCPRIM_1P0 BA24 NO CAP
D VCCPRIM_1P0 VCCDSW_3P3 +VCCPDSW_3P3 D
AC28 BA31 NO CAP
VCCPRIM_1P0 VCCPGPPA +V3.3A_1.8A_VCCPGPPA

VCCGPIO
+1.0VALW +VCCDSW_1P0 AE23
+VCCDSW_1P0 AE26 VCCPRIM_1P0 BC42
VCCPRIM_1P0 VCCPGPPBCH +V3.3A_VCCPGPPBCH
0.0454A Y23
VCCPRIM_1P0 VCCPGPPBCH
BD40
R205 2 @ 1 0_0402_5% Y25 AJ41 +V3.3A_VCCPGPPEF
BA29 VCCPRIM_1P0 VCCPGPPEF AL41
+1.0VALW_PCH DCPDSW_1P0 VCCPGPPEF AD41 +VCCFHV_2P8 +1.0VALW_PCH
+VCC19P2_1P0 VCCPGPPG +V3.3A_VCCPGPPG
NO CAP N17 AN5
+VCC19P2_1P0 VCCCLK1 VCCPRIM_3P3 +VCCPHVC_3P3
+VCCF135_1P0
NO CAP R19
VCCCLK3 0.0908A
0.0348A +VCCF100OC_1P0
NO CAP U20
VCCCLK4
R204 2 1 0_0402_5%
R207 2 1 0_0402_5% NO CAP V17 AD15
+VCCF100_1P0 VCCCLK2 VCCPRIM_1P0 +VCCDTS_1P0
R17 AD13 +V3.3S_VCCATS
VCCCLK2 VCCATS BA20 +VCCPDSW_3P3 +3VALW_PCH
+VCCF135_1P0 VCCRTCPRIM_3P3 +VCCPRTCPRIM_3P3
K2 BA22
+VCCF24_1P0_L VCCCLK5 VCCRTC +VCCPRTC_3P3
K3 BA26 VCC_RTCEXT_CAP 0.403A
VCCCLK5 DCPRTC
0.0237A R206 1 2 0_0603_5%

2
R209 2 1 0_0402_5% +VCCMPHY_1P0 U21 AJ20 C209
U23 VCCMPHY_1P0 VCCPRIM_1P0 AJ21 +VCCPRIM_1P0

MPHY
U25 VCCMPHY_1P0 VCCPRIM_1P0 AJ23 0.1U_0402_25V6
VCCMPHY_1P0 VCCPRIM_1P0

1
+VCCF100OC_1P0 U26 AJ25
V26 VCCMPHY_1P0 VCCPRIM_1P0 +3VALW_PCH
VCCMPHY_1P0 +V3.3A_1.8A_VCCPGPPA
0.0327A +VCCAMPHYPLL_1P0 A43
VCCMPHYPLL_1P0
R212 2 1 0_0402_5% B43 BE41 +V3.3A_VCCPSPI
VCCMPHYPLL_1P0 VCCSPI
C44
VCCPCIE3PLL_1P0 VCCSPI
BE43 0.0879A
C45 BE42 NO CAP R208 1 2 0_0603_5%
+VCCF100_1P0 NO CAP V28 VCCPCIE3PLL_1P0 VCCSPI BC44
+VCCAPLLEBB_1P0 VCCAPLLEBB_1P0 VCCPGPPD +1.8VALW_PCH
+VCCDUSB_1P0 AC17 BA45 +V3.3A_VCCPGPPD
VCCPRIM_1P0 VCCPGPPD
0.205A AJ5 BC45

USB
+VCCAUSB_1P0_L VCCUSB2PLL_1P0 VCCPGPPD
R214 2 1 0_0603_5% AL5 BB45 NO CAP
NO CAP AN19 VCCUSB2PLL_1P0 VCCPGPPD
+VCCAAZPLL_1P0_L VCCHDAPLL_1P0 BD3 +VCCPFUSE_3P3 R290 1 @ 2 0_0603_5%
BA15 VCCPRIM_3P3 BE3
+V3.3A_VCCPAZIO VCCHDA VCCPRIM_3P3
W15 BE4 NO CAP
+VCCPUSBDSW_3P3 VCCDSW_3P3 VCCPRIM_3P3
CAD Note:
May change to 2.2UH inductor
and 2*22UF caps filter SPT_PCH_H 8 OF 12 +3VALW_PCH
C REV = 1.3 ? +V3.3A_VCCPGPPBCH C
+1.0VALW_PCH +VCCF24_1P0_L
0.27262A
0.006 R210 1 2 0_0603_5%
R305 1 2 0_0603_5%
+V3.3A_VCCPGPPEF
1 1 1
C213 C214 C215 0.14107A
@ @ @ R211 1 2 0_0603_5%
1U_0402_10V6K
22U_0603_6.3V6M

22U_0603_6.3V6M

2 2 2 +VCCMPHY_1P0 +V3.3A_VCCPGPPG
+VCCAPLLEBB_1P0
0.1318A
0.09A R213 1 2 0_0603_5%
R218 2 1 0_0402_5%
3.53A
+VCCMPHY_1P0 +VCCAMPHYPLL_1P0 +VCCDUSB_1P0 +VCCPHVC_3P3 +3VALW_PCH

0.08A
+1.0VALW_PCH
0.533A PCH POWER RAIL TABLE 0.2875A
R234 1 2 0_0603_5% R221 1 2 0_0603_5%

+VCCAAZPLL_1P0_L LEVEL IccMAX R215 1 2 0_0603_5%

1
C217
@
1
C319
@
1
C316
L39 1 2
POWER RAIL (v) current EDS +VCCDTS_1P0 +1.0VALW_PCH
2
(A)
1U_0402_10V6K

C2693
22U_0603_6.3V6M

22U_0603_6.3V6M

2 2 2
0.0061A
2P_0402_50V8J

BLM15GA750SN1D_2P
1 LC Filter for EMI +VCCPRIM_1P0 1.0 2.899 R217 2 1 0_0402_5%

+V3.3S_VCCATS +3V
+VCC19P2_1P0 1.0 0.021
+3VALW_PCH
0.0066A
+1.0VALW_PCH +VCCAUSB_1P0_L +VCCPUSBDSW_3P3 +VCCF100_1P0 1.0 0.138 R219 2 1 0_0402_5%

0.233A
B
R223 1 2 0_0603_5% R224 2 1 0_0402_5% 0.013A R229 1 2 0_0603_5% +VCCF135_1P0 1.0 0.051 +VCCPRTCPRIM_3P3 +3VALW_PCH B
+VCCAAZPLL_1P0_L +V3.3A_VCCPAZIO
1
C210
1
C211 +VCCF100OC_1P0 1.0 0.024 0.0002A
L38 0.075A R222 2 1 0_0402_5%
0.008A
R226 2 1 0_0402_5% 1 2
+VCCMPHY_1P0 1.0 3.53
22U_0603_6.3V6M

22U_0603_6.3V6M

2 2
1 2 2 2 2
@ C399 C398 C2692 BLM15GA750SN1D_2P C400 C405
+VCCPRTC_3P3
+VCCAAZPLL_1P0_L 1.0 0.008
2P_0402_50V8J

4.7U_0402_6.3V6M

+VCC_RTC
1U_0402_10V6K

0.1U_0402_25V6

0.1U_0402_25V6

@ @
2 1 1 1 1
LC Filter for EMI 0.0002A
+VCCAMPHYPLL_1P0 1.0 0.08 R225 2 1 0_0402_5%

+VCCAUSB_1P0_L 1.0 0.013


BRD Note: +V3.3A_VCCPSPI +3VALW_PCH
Placed 1~3mm within PCH package edge +V3.3A_VCCPGPPA 3.3 0.084
0.0121A
+3VALW_PCH +1.8VALW_PCH +VCCMPHY_1P0 +VCCDUSB_1P0 +VCCPUSBDSW_3P3 +V3.3A_VCCPGPPBCH
+V3.3A_VCCPGPPBCH 3.3 0.259 R228 2 1 0_0402_5%

+1.0VALW_PCH +VCCDSW_1P0

+V3.3A_VCCPGPPD 3.3 0.101 +V3.3A_VCCPGPPD


2

C547 1 1 1 1 1
+V3.3A_VCCPGPPEF 3.3 0.134
2

C545 C546 @ C212 C216 C314 C219 C220 C221 0.0395A


@ R230 1 2 0_0603_5%
47U_0805_6.3V6-M

47U_0805_6.3V6-M

47U_0805_6.3V6-M
1

+V3.3A_VCCPGPPG 3.3 0.125


1U_0402_10V6K

1U_0402_10V6K 1U_0402_10V6K 1U_0402_10V6K 0.1U_0402_25V6


22U_0603_6.3V6M

2 2 2 2 2

+V3.3A_VCCPSPI 3.3 0.012 +VCCPFUSE_3P3

0.0811A
+V3.3S_VCCATS 3.3 0.007 R231 1 2 0_0603_5%

+V3.3A_VCCPGPPEF +V3.3A_VCCPGPPG +VCCPHVC_3P3 +V3.3S_VCCATS


+VCCPRTCPRIM_3P3 +VCCPRTC_3P3 +V3.3A_V1.8A_VCCPAZIO
3.3 0.06 A

+VCCPFUSE_3P3 3.3 0.3 LENOVO.CRDN


1 1 Title
2

C223
@
C224
@
C225
@
1
C222
C226 C227 C228 C229
+VCCPUSBDSW_3P3 3.3 0.233 PCH-POWER
1U_0402_10V6K

0.1U_0402_25V6

1U_0402_10V6K

0.1U_0402_25V6

0.1U_0402_25V6 0.1U_0402_25V6 0.1U_0402_25V6 Size Document Number


1

2 2 Rev V0.3
2
1U_0402_10V6K
+VCCPRTCPRIM_3P3 3.3 0.001 C
Skylake-H
Date: Thursday, May 26, 2016 Sheet 24 of 99

+VCCPRTC_3P3 3.3 0.001 "PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

D D

?
U2I ?
SPT-H_PCH
U2L
SPT-H_PCH
AC18 AR5
AN4 VSS VSS AR7
AN10 VSS VSS U15 AB11
BE14 VSS VSS AL4 C42 VSS AB7
BE18 VSS VSS AE29 D10 VSS VSS AB14
BE23 VSS VSS AE4 D12 VSS VSS AB31
BE28 VSS VSS AE42 D15 VSS VSS AB32
BE32 VSS VSS AF18 D16 VSS VSS AB38
BE37 VSS VSS AF20 D17 VSS VSS AB4
BE40 VSS VSS AF21 D19 VSS VSS AB5
BE9 VSS VSS AF23 D21 VSS VSS AC1
C10 VSS VSS AF25 D24 VSS VSS AC20
C2 VSS VSS AF26 D25 VSS VSS AC21
C28 VSS VSS AF28 D27 VSS VSS AC25
C37 VSS VSS AF29 D29 VSS VSS AC29
J7 VSS VSS AG11 D30 VSS VSS AC45
K10 VSS VSS AG13 D31 VSS VSS AB8
K27 VSS VSS AG31 D33 VSS VSS AD11
K33 VSS VSS AG32 D35 VSS VSS AD14
K36 VSS VSS AG33 D36 VSS VSS AB15
K4 VSS VSS AG38 E13 VSS VSS AD32
K42 VSS VSS AG4 E15 VSS VSS AD33
K43 VSS VSS AH1 E31 VSS VSS AD36
L12 VSS VSS AH17 E33 VSS VSS AD4
L13 VSS VSS AH18 F44 VSS VSS AD8
L15 VSS VSS AH20 F8 VSS VSS AE18
L4 VSS VSS AH21 G42 VSS VSS AE20
L41 VSS VSS AH23 G9 VSS VSS AE21
C C
L8 VSS VSS AH25 H17 VSS VSS AE25
M35 VSS VSS AH26 H19 VSS VSS AE28
M42 VSS VSS AH28 H22 VSS VSS AL10
N10 VSS VSS AH29 H24 VSS VSS AL11
N15 VSS VSS AH45 H27 VSS VSS AL13
N19 VSS VSS AJ10 H29 VSS VSS AL17
N22 VSS VSS AJ14 H3 VSS VSS AL19
N24 VSS VSS AJ15 H35 VSS VSS AL24
N35 VSS VSS AJ17 J10 VSS VSS AL29
N36 VSS VSS AJ18 J11 VSS VSS AL32
N4 VSS VSS AJ26 J3 VSS VSS AL33
N41 VSS VSS AJ28 J39 VSS VSS AL38
N5 VSS VSS AJ29 J5 VSS VSS AM15
P17 VSS VSS AJ31 T42 VSS VSS AM17
P19 VSS VSS AJ32 U10 VSS VSS AM19
P22 VSS VSS AJ36 U11 VSS VSS AM22
P45 VSS VSS AK4 U14 VSS VSS AM24
R10 VSS VSS AK42 U17 VSS VSS AM27
R14 VSS VSS AU7 U18 VSS VSS AM29
R22 VSS VSS AV17 U28 VSS VSS AM45
R29 VSS VSS AV24 U29 VSS VSS AN11
R33 VSS VSS AV27 U31 VSS VSS AN22
R38 VSS VSS AV31 U32 VSS VSS AN27
R5 VSS VSS AV33 U33 VSS VSS AN31
T1 VSS VSS AV6 U38 VSS VSS AN39
T2 VSS VSS AW13 U4 VSS VSS AN7
T4 VSS VSS AW19 U8 VSS VSS AN8
Y18 VSS VSS AW29 V18 VSS VSS AP11
Y20 VSS VSS AW37 V20 VSS VSS AP4
Y21 VSS VSS AW9 V21 VSS VSS AR33
Y26 VSS VSS AY38 V23 VSS VSS AR34
Y28 VSS VSS AY45 V25 VSS VSS AR42
Y29 VSS VSS B25 V29 VSS VSS AR9
A18 VSS VSS B3 V3 VSS VSS AT10
A25 VSS VSS B37 V45 VSS VSS AT15
A32 VSS VSS B40 W14 VSS VSS AT36
A37 VSS VSS B6 W31 VSS VSS AT9
B
AA17 VSS VSS BA1 W32 VSS VSS AU1 B
AA18 VSS VSS BB11 W33 VSS VSS AU35
AA20 VSS VSS BB16 W38 VSS VSS AU36
AA21 VSS VSS BB21 W4 VSS VSS AU39
AA25 VSS VSS BB25 W8 VSS VSS AU45
AA29 VSS VSS BB30 Y17 VSS VSS C4
AA4 VSS VSS BB34 VSS VSS
AA42 VSS VSS BC2
AB10 VSS VSS BD43
VSS VSS

SPT_PCH_H 12 OF 12
SPT_PCH_H 9 OF 12 REV = 1.3 ?
REV = 1.3 ?

A A

LENOVO.CRDN
Title
PCH-VSS
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 25 of 99
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

BRD Note:
+3VLP_EC and RTCVCC trace width 12mils
+3VLP_EC 0.1u placed close to each VCC-GND pair +VSTBY0_EC +VBAT_EC
+3VLP +3VLP_EC +3V +3V_1.8V_EC +3VALW +3VALW_EC_FSPI +3VLP_EC +3VLP_EC_AVCC

L1 1 2 R232 1 2 0_0402_5%

2
R233 1 2 0_0402_5% R297 1 2 0_0402_5% L3 1 2
BLM15BD221SN1D_2P 1 2 2 2 2 2 2 2 2 2 R235
+3VALW C238 C239 0_0402_5% BLM15BD221SN1D_2P
@ C230 C231 C232 C233 C234 C235 C236 C237 C308 2
L2 1 2

10U_0402_6.3V6M

2.2U_0402_6.3V6M

0.1U_0402_25V6
0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
0.1U_0402_25V6

1
2 1 1 1 1 1 1 1 1 1 C241
D BLM15BD221SN1D_2P 0.1U_0402_25V6 D
1
2
C242
0.1U_0402_25V6
1 EC_AGND

+3V_1.8V_EC +3VLP_EC +3VLP_EC_AVCC +VSTBY0_EC


+3VALW_EC_FSPI
+VBAT_EC

+3VLP_EC

D10

K10
U5

D5

D4

K4

E4

E9

A1
J5

J4
EC_SMB_CLK0 R236 2 1 2.2K_0402_5%
EC_SMB_DAT0 R243 2 1 2.2K_0402_5%

VCC

VSTBY_FSPI

AVCC

Vstby0
VBAT
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
21 LPC_AD0_ESPI_IO0
K1
EIO0/LAD0/GPM0
SMCLK0/GPF2
SMDAT0/GPF3
A10
B10
EC_SMB_CLK0 40,51,73,74
EC_SMB_DAT0 40,51,73,74
BATT/CHARGER/TI +3VLP_EC
J2
21 LPC_AD1_ESPI_IO1 EIO1/LAD1/GPM1 EC_I2C_CLK3
J1 B3 R563 2 1 2.2K_0402_5%
21 LPC_AD2_ESPI_IO2 EIO2/LAD2/GPM2 SMCLK1/GPC1 EC_SMB_CLK1 19,45,63 EC_I2C_DATA3
H2 B2 R564 2 1 2.2K_0402_5%
21 LPC_AD3_ESPI_IO3
21 LPC_FRAME_N_ESPI_CS_N
H1 EIO3/LAD3/GPM3
ECS#/LFRAME#/GPM5
SMDAT1/GPC2 EC_SMB_DAT1 19,45,63 PCH/TS/dGPU/MXM
K2 E8
21 CK_LPC/ESPI_CLK EC_RST_N ESCK/LPCCLK/GPM4 CRX1/WUI17/SIN1/SMCLK3/GPH1/ID1 EC_I2C_CLK3 32,34,47,79,80,87,90
17,27,38,40,42,43,49,50,63 PLT_RST_N
21 SERIRQ
R237 1
R294 1
2
2
0_0402_5%
0_0402_5% SERIRQ_R
M4
G2 ERST#/LPCRST#/WUI4/GPD2
ALERT#/SERIRQ/GPM6
SM BUS CTX1/WUI18/SOUT1/GPH2/SMDAT3/ID2
D7
EC_I2C_DATA3 32,34,47,79,80,87,90 LC/Switch/RE-PEATER +3VLP_EC

LPC N2 EC_I2C_CLK5 R238 2 1 2.2K_0402_5%

L
e
n
o
v
o
H_A20GATE_R L80HLAT/BAO/WUI24/SMCLK4/GPE0 PCH_I2C_CLK2 17 EC_I2C_DATA5
21 H_A20GATE
21 LPC_PD_N_ESPI_RST_N
R239 1
R240 1
2
2
0_0402_5%
0_0402_5% LPC_PD_N_R
F1
M1 GA20/GPB5
LPCPD#/WUI6/GPE6
L80LLAT/WUI7/SMDAT4/GPE7
M3
PCH_I2C_DATA2 17 PCH R244 2 1 2.2K_0402_5%

D1 2 1 SDM10U45LP-7_DFN1006-2-2 EC_SMI_N_R L2 K6 CAD Note:


21 EC_SMI_N EC_SCI_N_R ECSMI#/GPD4 PWM4/SMCLK5/GPA4 EC_I2C_CLK5 28,45

C
20 EC_SCI_N
21 KBRST_N
D2
D4
2
2 1 SDM10U45LP-7_DFN1006-2-2
1 SDM10U45LP-7_DFN1006-2-2 KBRST_N_R
N4
H4 ECSCI#/GPD3
KBRST#/GPB6
PWM5/SMDAT5/GPA5
J6
EC_I2C_DATA5 28,45 AMP/SENSOR I2C polling mode default +3V
C
CAD Note:EC_WRST_N A11 TP_PS2_CLK R241 1 2 4.7K_0402_5%
PCH_PWRBTN_N_R PS2CLK0/TMB0/CEC/GPF0 TP_PS2_CLK 46 TP_PS2_DAT
Trstpw=50ms;Twrstw=10us 19,51 PCH_PWRBTN_N
49,51 NBSWON_N
D3 2 1 SDM10U45LP-7_DFN1006-2-2 M2
B4 RXD/SIN0/PWUREQ#/BBO/SMCLK2ALT/WUI38/GPC7
PWRSW#/GPB3
PS2 PS2DAT0/TMB1/GPF1
B11
TP_PS2_DAT 46 TOUCH PAD R242 1 2 4.7K_0402_5%

+3VLP_EC EC_WRST_N L1 M11


WRST# TACH0A/GPD6 EC_FAN_TACH1 45

IT8376VG
M12
EC_PECI TACH1A/TMA1/GPD7 EC_FAN_TACH2 45
B1 M6
EC_WRST_N PECI/WUI22/SMCLK2/GPF6 FAN PWM2/GPA2 EC_FAN_PWM1 45
R246 1 2 100K_0402_5% A3 N6
31 MXLID_N ACOK_R LID_SW#/GPB1 PWM3/GPA3 EC_FAN_PWM2 45
1 R248 1 2 0_0402_5% A4
74 ACOK AC_IN#/GPB0
C244
M5 5VT 16mA
PWM0/GPA0 PWR_LED_W 49
1U_0402_10V6K N5 5VT 16mA +3VLP_EC
2 EC_SCK PWM1/GPA1 BATT_LOW_LED_A 49
B5 M7 5VT 16mA
EC_CS_N FSCK/GPG7 PWM6/SSCK/GPA6 AC_CHARGED_LED_W 46
A7 K7 5VT 16mA
EC_SI FSCE#/GPG3 PWM7/RIG1#/GPA7 AC_CHARGING_LED_A 46
B6 FSPI ACOK R245 2 1 100K_0402_5%
EC_SO A6 FMOSI/GPG4
FMISO/GPG5 D2 CHG_PROCHOT_N_R R247 2 1 100K_0402_5%
CTX0/TMA0/GPB2 EC_THERM_ALERT_N 63
A2
R252 2 1 33_0402_5% EC_PECI J12 XLP_OUT/GPB4 EC Input, GPU heat, active low. NOVO_BTN_N R249 2 1 100K_0402_5%
6,20 H_PECI 51 MX0 KSI0/STB#
J13
51 MX1 J9 KSI1/AFD# NBSWON_N R250 2 1 100K_0402_5%
2 51 MX2 KSI2/INIT#
C245 H12
@ 51 MX3 H9 KSI3/SLIN# D1 SUSON R258 2 @ 1 100K_0402_5%
51 MX4 KSI4 CRX0/GPC0 USB_CHG_EN 41
47P_0402_25V8J H10 C2
1 51 MX5 KSI5 TMRI0/WUI2/GPC4 USB_CHG_CLT1 41
MX6 H13 E1 MAINON R299 2 @ 1 100K_0402_5%
51 MX6 KSI6 TMRI1/WUI3/GPC6 USB_CHG_CLT3 41
MX7 G9
51 MX7 M8 KSI7 EC_ON R251 2 1 100K_0402_5%
51 MY0 J7 KSO0/PD0
51 MY1 KSO1/PD1 KB MX BIOS_ONEKEY_N
N9 R268 2 1 100K_0402_5%
51 MY2 M9 KSO2/PD2
RP4 51 MY3 K8 KSO3/PD3 N1 USB_STATUS_N_R R379 2 1 100K_0402_5%
51 MY4 KSO4/PD4 RI1#/WUI0/GPD0 PWR_LEVEL 63
J8 N3
EC_SCK 51 MY5 KSO5/PD5 RI2#/WUI1/GPD1 EC_ON_R PM_RSMRST_N 19
4 5 N10 N7 R256 1 2 0_0402_5% Staff as default
17 PCH_SCK_R EC_SO 51 MY6 KSO6/PD6 GINT/CTS0#/GPD5 EC_ON 41,75,77,92
3 6 M10 GPIO +3V
17 PCH_SO_R EC_SI 51 MY7 KSO7/PD7
2 7 N11
17 PCH_SI_R EC_CS_N 51 MY8 KSO8/ACK#
1 8 K9
17 PCH_CS0_N 51 MY9 KSO9/BUSY EC_FAN_TACH1
N12 R253 2 1 100K_0402_5%
0_0804_8P4R_5% 51 MY10 N13 KSO10/PE A13
51 MY11 KSO11/ERR# EGAD/WUI25/GPE1 SLP_S4_N 19,76 EC_FAN_TACH2
M13 A12 R254 2 1 100K_0402_5%
51 MY12 KSO12/SLCT EGCS#/WUI26/GPE2 SLP_S3_N 19,38
L12 B12
51 MY13 KSO13 EGCLK/WUI27/GPE3 AR_HOLD_RST_N 40 PWR_LEVEL
L13 E2 R255 1 @ 2 10K_0402_5%
51 MY14 KSO14 GPE4 SUSON 41,48,49,76,90,92
K12 N8 R257 1 2 0_0402_5%
VDDQ_PWRGD 76
R578511MY15 2 0_0402_5% EC_KSO16 K13 KSO15 RTS1#/WUI5/GPE5 EC_INT_N R566 2 1 100K_0402_5%
47 LC_KSO16 EC_KSO17 KSO16/SMOSI/GPC3
R579 1 2 0_0402_5% J10
47 LC_KSO17 KSO17/SMISO/GPC5 EC_THERM_ALERT_N
B CAD Note: R337 1 2 10K_0402_5% B
Reserve TPC for SMBus flash D5 2 1 SDM10U45LP-7_DFN1006-2-2 AC_PRESENT_R C12 D9 EC Input, GPU heat, active low.
19 AC_PRESENT DAC5/RIG0#/GPJ5 PS2CLK2/WUI20/SMINT10/GPF4 ALL_SYS_PWRGD R260 1 MAINON 50,78,86,90,91,92
B13 B9 2 0_0402_5%
45 VCOUT1_PROCHOT DAC4/DCD0#/GPJ4 PS2DAT2/WUI21/SMINT11/GPF5 PM_PCH_PWROK_RR262 1 CPU_VR_PWRGD 83
TP147 1 MX6 C13 C1 2 0_0402_5%
45,63,74 CHG_PROCHOT_N_R DAC3/TACH1B/SMINT7/GPJ3 PECIRQT#/WUI23/SMDAT2/GPF7 PM_PCH_PWROK 19
TP152 1 MX7 D12
73 EC_ADP_ID_ON_N LC_INT1_N_R DAC2/TACH0B/SMINT6/GPJ2
R308 1 2 0_0402_5% D13
47 LC_INT1_N EC_INT_N_R SMINT5/GPJ1
R370 1 2 0_0402_5% E12
17 EC_INT_N TACH2/SMINT4/GPJ0 EC_KSO16
E6 R267 2 @ 1 100K_0402_5%
SSCE1#/GPG0 NOVO_BTN_N_R R265 1 CODEC_PD_N 28,29
R777 1 @ 2 0_0402_5% A5 2 0_0402_5%
90 VBL_INT_N DTR1#/SBUSY/GPG1/ID7 EC_TEST1 NOVO_BTN_N 49 EC_KSO17
R546 1 2 0_0402_5% E13 GPIO E7 R324 2 @ 1 100K_0402_5%
50 TURBO_GPIO1 ADC7/CTS1#/WUI31/GPI7 SSCE0#/GPG2 SYS_PWROK_R R263 1
F12 D6 2 0_0402_5%
74,83 PSYS ADC6/DSR1#/WUI30/GPI6 DSR0#/GPG6 SYS_PWROK 19
F10
74 BMON ADC5/DCD1#/WUI29/GPI5
CAD Note: 74 AMON
F13
ADC4/WUI28/SMINT3/GPI4
F9
ADC VIN range 0~3.0V 73 ADAPTER_ID
G12 ADC3/SMINT2/GPI3 BIOS_ONEKEY_N 48
45 VCIN0_PT1 ADC2/SMINT1/GPI2
G13 D8
51,73,74 MBAT_PRES_N ADC1/SMINT0/GPI1 CLKRUN#/WUI16/GPH0/ID0
R523 1 2 0_0402_5% G10 A9 CAD Note:
19 EC_CLEAR_CMOS ADC0/GPI0 WUI19/GPH3/ID3/YM ME_FLASH 19
B8 GPH4:From VR_ON change to USB_CHG_CLT2
GPH4/ID4/YP A8 USB_STATUS_N_R R540 1 2 0_0402_5%
USB_CHG_CLT2 41 GPG0,GPG2,GPG6 reserved for
EC_VCORE2/CK32KE GPH5/ID5/DM USB_CHG_STATUS_N 41 Hardware strapping
G1 B7
VCORE2(CK32KE) GPH6/ID6/DP LAN_WAKE_N 27
R526 1 2 0_0402_5% EC_CK32K/GPJ6F2 CLOCK
50 TURBO_GPIO3 GPJ6(CK32K) +3VLP_EC
1
VCORE
2

C243 EC_TEST1 R259 1 2 10K_0402_5%


AVSS
VSS

VSS
VSS
VSS
VSS
VSS

CAD Note: R261


@
IT8371 NC 2
0.1U_0402_25V6

10K_0402_5%
K5

H5

E5
F4
F5
G4
G5

E10

IT8376VG-128/CX
1

@
ACOK_R C71 1 2 100P_0402_50V8J
1 J1
C310 1 2 ALL_SYS_PWRGD C246 2 1 0.1U_0402_25V6
CAD Note:
0.1U_0402_25V6

JUMPER CK_LPC/ESPI_CLK R264 2 1 C247


IT8371 Stuff 2 EC_AGND
33_0402_5% 10P_0402_50V8J

Note 1 : Since all GPIO belong to VSTBY power domain, and EC_AGND

there are some special considerations below:


(1) If it is output to external VCC derived power domain
A circuit, this signal should be isolated by a diode such as A

KBRST# and GA20.


(2) If it is input from external VCC derived power domain
circuit, this external circuit must consider not to float LENOVO.CRDN
the GPIO input. Title
EC IT8376VG

Note 2 : Size
Custom
Document Number
Skylake-H
Rev V0.3

(1) Each input pin should be driven or pulled. Date: Thursday, May 26, 2016 Sheet 26 of 99
"PROPERTY NOTE: this document contains information confidential and

(2) Each output-drain output pin should be pulled. property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

WWW.AliSaler.Com 5 4 3 2 1
5 4 3 2 1

+3VALW 0.152A CAD Note:LX_LAN BRD Note: BRD Note: BRD Note: BRD Note: BRD Note:
+VDD33_LAN SWR MODE DEFAULT Placed close Placed close Placed close Placed close Placed close
R271 2 1 0_0603_5%
L4 to L2 1.1V to Pin37 L5 to Pin6 to Pin13,19,31 L6 to Pin34
LAN_LX 1 2 +DVDDL_LAN 1 2 +AVDDL_LAN 1 2 +AVDDVCO_LAN
1 2 2
1

1
C250 C251 C252 C253 C254 4.7uH NRS4012T4R7MDGJ 1.5A BLM18KG601SN1_600 ohm 1.3A BLM18KG601SN1_600 ohm 1.3A
2 2 1 2 1 2 2 2 2 1 1 2

1
10U_0603_10V

10U_0603_10V

1U_0402_10V6K

0.1U_0402_25V6

1000P_0402_50V7K
C255 C256 C258 C259 C260 C261 C262 C263 C264 C265 C266 C267
2

2
2 1 1
BRD Note: C257 @ @

10U_0603_10V

0.1U_0402_25V6

1000P_0402_50V7K

1U_0402_10V6K

0.1U_0402_25V6

1U_0402_10V6K

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
W=40mils;S=40mils;

2
1 1 2 1 2 1 1 1 1 2 2 1

4.7U_0402_6.3V6M

1U_0402_10V6K
Keep L2 within200mils;
D
Keep LAN_LX on internal layer of PCB D
and GND coverd

BRD Note: BRD Note:


Placed close Placed close
to Pin9 to Pin22
2.7V
+AVDDHREG_LAN R272 1 2 0_0402_5% +AVDDH_LAN
R273 2 1 0_0603_5% +AVDD33_LAN

1 2 2
1 2 2 C271 C272 C273
C268 C269 C270

+AVDDL_LAN
1U_0402_10V6K

0.1U_0402_25V6

0.1U_0402_25V6
2 1 1
1U_0402_10V6K

0.1U_0402_25V6

1000P_0402_50V7K
2 1 1

+AVDDHREG_LAN
+AVDDVCO_LAN
+AVDD33_LAN

+AVDDH_LAN
+DVDDL_LAN

+AVDDL_LAN
+VDD33_LAN
+VDD33_LAN R275 1 2 10K_0402_5% LAN_WAKE_N_R

16

37

13
31
19

34

22
1

9
U6

VDD33
AVDD33

DVDDL_REG

AVDDL_REG

AVDDL
AVDDL
AVDDL

AVDDVCO

AVDDH_REG
AVDDH
Q35A @ AO5804EL_SC89-6 CAD Note:PERSTn
C
6 1 LAN_CK_REQ_N Keep low 100ms after the VDD33 valid 40 LAN_LX
C

22,27 CK_REQ_LAN_N LX
R274 1 2 0_0402_5% LAN_RST_N 2
17,26,38,40,42,43,49,50,63 PLT_RST_N LAN_WAKE_N_R PERSTn MDI_P0
R276 1 2 0_0402_5% 3 11
26 LAN_WAKE_N R277 1 2 0_0402_5% LAN_CK_REQ_N 4 WAKEn TRXP0 12 MDI_N0
2 22,27 CK_REQ_LAN_N CLKREQn TRXN0
3 +VDD33_LAN 14 MDI_P1
TRXP1 15 MDI_N1
TRXN1
2

Q35B
18 PCIE_LAN_TX_C_DN
36
RX_N BRD Note:MDI*
R477 35 17 MDI_P2
5 @
18 PCIE_LAN_TX_C_DP RX_P TRXP2 18 MDI_N2 Trace lengh between E-2011B and Transformer
100K_0402_5% TRXN2 be 1.5~10inch
C274 1 2 0.1U_0402_16V7K PCIE_LAN_RX_C_DN 29 20 MDI_P3
18 PCIE_LAN_RX_DN TX_N TRXP3
1

AO5804EL_SC89-6 C275 1 2 0.1U_0402_16V7K PCIE_LAN_RX_C_DP 30 21 MDI_N3


4 18 PCIE_LAN_RX_DP TX_P TRXN3

22 CK_LAN_N
R278 1 2 0_0402_5% 32
REFCLK_N BRD Note:LAN_RBIAS
R279 1 2 0_0402_5% 33 10 LAN_RBIAS R2801 2 2.37K_0402_1%
22 CK_LAN_P REFCLK_P RBIAS Keep away from other signals 25mils;
24 LAN_PPS 1 TP90 placed on the other side is possible
XTAL_LAN_IN 8 PPS
XTAL_LAN_OUT 7 XTLI
XTLO 5 R282 1 2 30K_0402_1% +VDD33_LAN
DEBUGMODE[0]
TESTMODE[0]
25 CAD Note:PPS
26
38 TESTMODE[1] 27
1 Hz clock output for IEEE1588 timing sync
LED[0] TESTMODE[2]
CAD Note:PECLK 39
LED[1]
23 28
Clock must be valid within 3ms

GND
LED[2] NC
after the VDD33 reach 2.0V level

41
E2400-RIVL-RL_QFN40 JRJ1

R281 2 @ 1 1M_0402_5%
9
MDO_P0 1 GND
PR1+
B MDO_N0 B
2
PR1-
4

Y4
XTAL_LAN_IN 1 3 XTAL_LAN_OUT MDO_P1 3
PR2+
25MHZ_8PF_EXS00A-CS07258 MDO_P2 4
PR3+
2

1 1 CHASSIS1_GND
MDO_N2 5
C276 C277 PR3-
10P_0402_50V8J 10P_0402_50V8J MDO_N1 6
2 2 PR2-
MDO_P3 7
PR4+ 10
MDO_N3 8 GND
TL1 PR4-
1 24 MCT1_TL
TCT1 MCT1
MDI_P0 2 23 MDO_P0
TD1+ MX1+ Foxconn_JM3611-RS800003-7H
MDI_N0 3 22 MDO_N0 CHASSIS1_GND
D6 TD1- MX1-
MDI_P2 1 4 MDI_P3 4 21
I/O1 I/O3 TCT2 MCT2
MDI_P1 5 20 MDO_P1
TD2+ MX2+
2 5 MDI_N1 6 19 MDO_N1 C278 1 2 0.1U_0402_25V6
GND VDD TD2- MX2-
7 18 C279 1 2 0.1U_0402_25V6
TCT3 MCT3
MDI_N3 3 6 MDI_N2 MDI_P2 8 17 MDO_P2 C280 1 2 0.1U_0402_25V6
I/O2 I/O4 TD3+ MX3+
MDI_N2 9 16 MDO_N2 C281 1 2 0.1U_0402_25V6
AZC099-04S.R7G TD3- MX3-
10 15
TCT4 MCT4
MDI_P3 11 14 MDO_P3 CHASSIS1_GND
TD4+ MX4+
MDI_N3 12 13 MDO_N3
TD4- MX4-
1
A A
D7
1 2 2 2 2 R283
1

1
MDI_P0 1 4 MDI_P1 C282 C283 C284 C285 C286 C287 C288 C289 C290 GST5009-E LF 75_0805_5%
I/O1 I/O3 @ @ @ @ @ DL1 LENOVO.CRDN

1
2nd:MHPC NS892407(SP05000680J)
1U_0402_10V6K

1000P_0402_50V7K

0.1U_0402_25V6

1000P_0402_50V7K

0.1U_0402_25V6

1000P_0402_50V7K

0.1U_0402_25V6

1000P_0402_50V7K

0.1U_0402_25V6
2

2 1 1 1 1 PDT5061 Title
2 5

2
GND VDD LAN-E-E2400-RIVL

2
Size Document Number
Rev V0.3
1

C291 C
MDI_N1 3 6 MDI_N0 Skylake-H
I/O2 I/O4 1000P_1206_2KV7-K Date: Thursday, May 26, 2016 Sheet 27 of 99
2

"PROPERTY NOTE: this document contains information confidential and


AZC099-04S.R7G property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
CHASSIS1_GND

5 4 3 2 1
5 4 3 2 1

+5V +5VD_AUD +5V +5VA_AUD +1.8V +1.8VA_AUD +3V +3VD_AUD +3VALW +3VALW_AUD

L7 L8
1 2 1 2 R284 2 1 0_0603_5% R285 2 1 0_0603_5% R286 2 1 0_0603_5%

2 BLM15PX121SN1D_2P 2 2 BLM15PX121SN1D_2P 2 1.8V power rail should be supplied by linear regulator, 2 2 2 2 2 2


1

1
C292 C293 C294 C295 C296 C297 C298 C299 not switching regulator. if switching regulator is C301 C303 C305
unavoidable, Pls make sure that switching frequency C300 C302 C304
operates at out‐ band(Over 20KHz).

10U_0603_10V

10U_0603_10V
10U_0603_10V

10U_0603_10V

0.1u_0402_16V7K

0.1u_0402_16V7K

2.2U_0402_6.3V6M

0.1u_0402_16V7K

2.2U_0402_6.3V6M

0.1u_0402_16V7K

2.2U_0402_6.3V6M

0.1u_0402_16V7K
0.1u_0402_16V7K

0.1u_0402_16V7K
2

2
1 1 1 1 1 1 1 1 1 1

AGND AGND AGND AGND

D D

+5VD_AUD +3VD_AUD +3VALW_AUD +5VA_AUD

+2.25V

CAD Note:HD_I2C SEL 2


C306 C307
Hi: HDA mode; POR strap

0.1u_0402_16V7K

2.2U_0402_6.3V6M
U7

51

46

19

10

45

43
1

7
R319 1 2 0_0402_5% R289 2 1 100K_0402_5% HDA_I2S_SEL
26,45 EC_I2C_CLK5 +3VD_AUD
EC

VD33STB

VREF
PVDD2

PVDD1

DVDD-IO

AVDD1
DVDD
R318 1 2 0_0402_5% AGND AGND
26,45 EC_I2C_DATA5

R321 1 @ 2 0_0402_5% POST_I2C_CLK


17 PCH_I2C_CLK0 CODEC/AMP
PCH SPK_R+ 47
29 SPK_R+ SPK-OUT-LP
R320 1 @ 2 0_0402_5% POST_I2C_DATA 44 +4.5V C309 1 210U_0402_6.3V6M
17 PCH_I2C_DATA0 LDO1-CAP AGND
SPK_R- 48
29 SPK_R- SPK-OUT-LN 41 C313 1 210U_0402_6.3V6M AGND
TP91 1 SPK_L+ 49 MIC1-CAP
R292 2 1 10K_0402_5% SPK-OUT-RN 40 MIC2_VREF
+3VD_AUD Line1-VREFO
TP92 1 SPK_L- 50
SPK-OUT-RP 39 MIC1_VREF_R
D8 1 2 SDM10U45LP-7_DFN1006-2-2 CODEC_PD_N_R 52 Mic1-VREFO-R/AGPO-1
CODEC_PD_N_R 26,29 CODEC_PD_N EAPD+PD#/GPIO_11 MIC1_VREF_L
C 29 CODEC_PD_N_R 38 C
R293 1 2 22_0402_5% DMIC_CLK_R 53 Mic1-Vref_O-L
31 DMIC_CLK DMIC-CLK1 37 MIC1R_SLEEVE
R295 1 2 0_0402_5% DMIC_DATA_R 54 Mic1-R/Sleeve
31 DMIC_DATA DMIC-DATA1 36 MIC1L_RING2

+3VD_AUD 29 POST_I2S_MCLK
R296 1

R298 1
2 22_0402_5%

2 22_0402_5%
55

56
I2S_MCLK ALC3268-CG Mic1-L/Ring2

Line1-L
35 MIC2L
29 POST_I2S_BCLK I2S_BCLK 34 MIC2R
R301 1 2 22_0402_5% 1 Line1-R
29 POST_I2S_LRCLK I2S_LRCLK
2

33 HP_OUTR
SPDIF_OUT HP_Out-R HP_OUTR 49
R310 TP103 1 2
GPIO_1/DMIC_CLK2 32 HP_OUTL
100K_0402_1%

HP_JD HP_Out-L HP_OUTL 49


R311 1 2 200K_0402_1% R302 1 2 22_0402_5% 3
49 HP_JD 29 POST_I2S_OUT I2S_OUT -1.8V C315 1
31 2 2.2U_0402_6.3V6M AGND
CPVEE
1

TP93 1 4
MIC_JD R312 2 1 100K_0402_1% HDA_JD2 GPIO_2/DMIC DATA2 30 0V
49 MIC_JD CPVREF AGND
5
29 POST_I2S_IN I2S_IN 29 +1.8V C317 1 2 2.2U_0402_6.3V6M
CPVPP AGND
TP94 1 HDA_I2S_SEL 6
HD-I2S SEL 28 C318 1 2 2.2U_0402_6.3V6M
2 CBN1
C332 TP95 1 HDA_JD1 8
@ GPI-JD1 27
HDA_JD2 9 CBP1
0.1u_0402_16V7K

1 GPI-JD2 26 C321 1 2 2.2U_0402_6.3V6M


11 CBP2 +1.8VA_AUD
29 POST_I2C_DATA I2C -SDA 25
12 CBN2
29 POST_I2C_CLK I2C-SCL 24
13 CPVDD/AVDD2
19 HDA_BCLK MHDA BCLK 2 1
23 PC_BEEP C322 C323
14 PCBEEP
19 HDA_SYNC MHDA SYNC +1.5V
22

10U_0402_6.3V6M
0.1u_0402_16V7K
15 LDO2-CAP 1 2
19 HDA_RST_N MHDA RESET 2 1
21 +0.45V C324 C325
R307 2 1 33_0402_5% HDA_SDIN_R O 16 VBG_OUT @
19 HDA_SDIN MHDA SDATA In AGND AGND

10U_0402_6.3V6M
2 2

0.1u_0402_16V7K
R3132 1 1K_0402_5% C3302 10.1u_0402_16V7K PC_BEEP I 17 42 C326 C327 1 2
B 19 HDA_SPKR 19 HDA_SDOUT MHDA SDATA OUT AVSS1 B

0.1u_0402_16V7K

4.7U_0402_6.3V6M
+1.2V 18 20
LDO3-CAP AVSS2 1 1
1

1 2 2 AGND AGND
R314 C331 C328 C329
@ 57 AGND AGND AGND

0.1u_0402_16V7K
1K_0402_5%

4.7U_0402_6.3V6M
TPAD
100P_0402_50V8J

2 1 1
2

POST_I2S_MCLK
POST_I2S_BCLK
POST_I2S_LRCLK
POST_I2S_OUT J2 1 2 @ JUMPER
POST_I2S_IN

J3 1 2 @ JUMPER
MIC1_VREF_R R845 1 2 2.2K_0402_5%
1

C333 C334 C335 C336 C337


MIC1_VREF_L R846 1 2 2.2K_0402_5% R315 1 2 0_0402_5%
22P_0402_50V8-J

22P_0402_50V8-J

22P_0402_50V8-J

22P_0402_50V8-J

22P_0402_50V8-J
2

R316 1 2 0_0402_5%

MIC1R_SLEEVE MIC1R_SLEEVE 49 R317 1 2 0_0402_5%

MIC1L_RING2 MIC1L_RING2 49
AGND

A A
MIC2_VREF D9 2 1 R847 1 2 2.2K_0402_5%

SDM10U45LP-7_DFN1006-2-2 LENOVO.CRDN
HDA_BCLK DMIC_CLK D10 2 1 R848 1 2 2.2K_0402_5% Title
CODEC-ALC3268
SDM10U45LP-7_DFN1006-2-2
1

C339 C338 Size Document Number


@ C Rev V0.3
22P_0402_50V8-J
10P_0402_50V8J
MIC2L C510 1 2 R849 2 1 MIC2L_C Skylake-H
MIC2L_C 49
2

Date: Thursday, May 26, 2016 Sheet 28 of 99


4.7U_0805_25V6K 1K_0402_5% "PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
MIC2R C511 1 2 R850 2 1 MIC2R_C or disclosed to others or used for any purpose other than that for which it was
MIC2R_C 49 obtained without the expressed written consent of LENOVO PND."
4.7U_0805_25V6K 1K_0402_5%

5 4 3 2 1
5 4 3 2 1

CAD Note:POST_I2C*
connect to PCH default and reserve to EC
PU at PCH or EC side BRD Note:
+PVCC_AMP +3VA_AMP +3VD_AMP
placed near to Pin6&7
+PVCC_AMP and Pin41&42&43 seperately +3V +3VA_AMP +3V +3VD_AMP
B+
+GVDD_AMP @ L11 L12
PJ4 1 2 1 2

+6.9V C340 1 2 1U_0402_25V6K 2 BLM15PX121SN1D_2P 2 BLM15PX121SN1D_2P 2

1
C341 C342 C343 C344 C345 C346 C347 C348
@ @ C349 C350

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

0.1U_0402_25V6

10U_0603_10V

0.1u_0402_16V7K

1U_0402_10V6K

1U_0402_10V6K
43
42
41

14

31
30

2
1 1 1

6
7

8
U8

PVCC
PVCC
PVCC
PVCC
AVCC

AVDD

CPVDD
DVDD

GVDD
D D

16 5 C351 2 1 0.22U_0402_25V6K separate to two group and place need to Pin6&7 and Pin42&43;
28 POST_I2C_DATA SDA BSPR
17 4 AMP_SPK_R+
28 POST_I2C_CLK SCL OUTPR
CAD Note:POST_I2S_MCLK 18 2 AMP_SPK_R-
GPIO1 OUTNR
BRD Note:
Internal
Use TAS5766M internal MCLK default 19 1 C352 2 1 0.22U_0402_25V6K Speaker
GPIO2 BSNR Route 40 mils width and As short as possible
R322 1 2 22_0402_5% 21 48 C353 2 1 0.22U_0402_25V6K
28 POST_I2S_IN GPIO3 BSNL JSPKR1
22 47 AMP_SPK_L- AMP_SPK_R+ R66 2 1 0_0603_5% SPK_CON_R+ 4 6
28 POST_I2S_MCLK MCLK OUTNL AMP_SPK_R- SPK_CON_R- 4 GND
R67 2 1 0_0603_5% 3
23 45 AMP_SPK_L+ AMP_SPK_L+ R68 2 1 0_0603_5% SPK_CON_L+ 2 3
28 POST_I2S_BCLK BCLK OUTPL AMP_SPK_L- SPK_CON_L- 2
+3VD_AMP R69 2 1 0_0603_5% 1 5
24 44 C354 2 1 0.22U_0402_25V6K 1 GND
28 POST_I2S_OUT

28 POST_I2S_LRCLK
25
DIN

LRCLK
TAS5766M BSPL
2
C359
2
C355
2
C356
2
C357
ACES_ 50281-00401-001

2
27 AMP_PD_N_R
XSMT/UVP
C358 1 2 1U_0402_25V6K 28 CAD Note:AMP_PD_R_N

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
R323
LDOO 9 AMP_GAIN/FSW @ 1 1 1 1
C360 1 2 1U_0402_25V6K 32 GAIN/FSW 10K_0402_5%
Low active to mute,
CAPP 40 Tr/Tf less than 20ns
FAULTZ

1
34
CAPM 26 @
C361 1 2 1U_0402_25V6K 35 ADR1 AMP_PD_N_R D19 2 1
SDM10U45LP-7_DFN1006-2-2
VNEG CODEC_PD_N 26,28
20
C362 2 1 0.22U_0402_25V6K 36 ADR2
DACL R338 1 2 0_0402_5%
CODEC_PD_N_R 28
37
INPL
C363 2 1 0.22U_0402_25V6K 38 3 +GVDD_AMP
INNL GND 10
C364 2 1 0.22U_0402_25V6K 11 GND 15
INNR GND

1
29
C365 2 1 0.22U_0402_25V6K 12 GND 33 R325
C C
INPR GND 39 75K_0402_1%
13 GND 46
DACR GND

2
49 AMP_GAIN/FSW
TGND

1
R328
47K_0402_5%

2
I2C ADDRESS:0x 1001_100x

+VCC_SWF +12V_SWF_BOOST +VCC_SWF


U9
R329 2 1 10_0603_5% SWF_AVDD @
+VCC_SWF PJ7
C366 1 2 1U_0402_25V6K

1
7 27 C369 C370 C371 C372 C367 C368
AVDD LPVDD 28 @ @
AMP_PD_N_R R330 2 1 1K_0402_5% SWF_SD_N 1 LPVDD

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

0.1U_0402_25V6
SD#

2
2 15
FLAG# RPVDD 16
RPVDD
C373 1 2 1U_0402_25V6K SWF_VCLAMP 9
VCLAMP
TPA3113D2PWPR 26
R331 2 1 R332 2 1 LBSP 25 C374 1 2 0.47U_0402_25V6K
20K_0402_1% 62K_0402_1% LOUTP
SWF_PLIMIT 10
PLIMIT 23 SWF_R+
C375 1 2 1U_0402_25V6K LOUTN 22
3 LBSN
LINP
B
4
LINN BRD Note: Sub Woofer B
21
RBSN 20 SWF_R- Route 40 mils width
ROUTN JSWF1
SWF_RINN 11 SWF_R- R70 2 1 0_0603_5% SWF_CON_R- 1
SWF_RINP 12 RINN 18 C376 1 2 0.47U_0402_25V6K SWF_R+ R71 2 1 0_0603_5% SWF_CON_R+ 2 1
RINP ROUTP 17 3 2
RBSP 4 GND
GND

1
R333 R334 ACES_50271-00201-001
@ @ 2 2
13 33_0402_5% 33_0402_5% C377 C378
SWF_AVDD R335 1 2 100K_0402_5% AMP_MONO 14 NC 8
MONO AGND

1 2

1 2
19

1000P_0402_50V7K

1000P_0402_50V7K
SWF_GAIN0 5 PGND 24 C379 C380 1 1
SWF_GAIN1 6 GAIN0 PGND 29 @ @
GAIN1 TGND

22P_0402_50V8-J

22P_0402_50V8-J
2

2
+5V

2
R339 2 1 3.3K_0402_1% R340 2 1 3.3K_0402_1% C381 1 2 1U_0402_10V6K SWF_RINN
28 SPK_R-
R341 R342
2 2 @ @
C382 C383 10K_0402_5% 10K_0402_5%
1

1
A 680P_0402_50V7K 680P_0402_50V7K SWF_GAIN0 A
1 1 SWF_GAIN1
2

2
R343 2 1 3.3K_0402_1% R344 2 1 3.3K_0402_1% C384 1 2 1U_0402_10V6K SWF_RINP LENOVO.CRDN
28 SPK_R+
R345 R348
1

CAD Note:SWF_GAIN[1::0] 10K_0402_5% 10K_0402_5% Title


R346 R347
00:Gain=20dB,RI=60k ohm(Default) AMP
2.2K_0402_5%

2.2K_0402_5%

01:Gain=26dB,RI=30k ohm
1

Size Document Number


00:Gain=32dB,RI=15k ohm C Rev V0.3
Skylake-H
2

00:Gain=38dB,RI=9k ohm Date: Thursday, May 26, 2016 Sheet 29 of 99


"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

500mA
+3V +3V_DP_UMA_CON

R404 2 1 0_0603_5%

1 2

1
C2711 C2712 C2710

0.1U_0402_25V6
10U_0603_10V

1U_0402_10V6K
2
2 1

D D

+3V_DP_UMA_CON
JDP2

20
DP_PWR
19
C2702 1 2 0.1U_0402_16V7K CPU_DP_TX0_C_DP 1 RETURN
3 CPU_DPB_TX0_DP CPU_DP_TX0_C_DN ML_LANE0+ CPU_DPB_HPD_CON
C2706 1 2 0.1U_0402_16V7K 3 18
3 CPU_DPB_TX0_DN ML_LANE0- HOT_PLUG_DETECT
C2703 1 2 0.1U_0402_16V7K CPU_DP_TX1_C_DP 4 2
3 CPU_DPB_TX1_DP CPU_DP_TX1_C_DN ML_LANE1+ GND1
C2707 1 2 0.1U_0402_16V7K 6 5
3 CPU_DPB_TX1_DN ML_LANE1- GND2 8
C2705 1 2 0.1U_0402_16V7K CPU_DP_TX2_C_DP 7 GND3 11
3 CPU_DPB_TX2_DP CPU_DP_TX2_C_DN ML_LANE2+ GND4 CPU_HDMI_DONGLE_DETECT
C2708 1 2 0.1U_0402_16V7K 9 13
3 CPU_DPB_TX2_DN ML_LANE2- CONFIG1 CPU_HDMI_CEC
14
C2704 1 2 0.1U_0402_16V7K CPU_DP_TX3_C_DP 10 CONFIG2 16
3 CPU_DPB_TX3_DP CPU_DP_TX3_C_DN ML_LANE3+ GND
C2709 1 2 0.1U_0402_16V7K 12
3 CPU_DPB_TX3_DN ML_LANE3-

1
C2713 1 2 0.1U_0402_16V7K CPU_DP_AUX_C_DP_SCL 15 21
3 CPU_DPB_AUX_DP CPU_DP_AUX_C_DN_SDA 17 AUXCH+ CASE_GND1
C2714 1 2 0.1U_0402_16V7K 22 R2322 R2323
3 CPU_DPB_AUX_DN AUXCH- CASE_GND2 23 1M_0402_5% 1M_0402_5%
CASE_GND3 24
CASE_GND4

2
ACON_DRA45-20

C CAD Note:HDMI_DONGLE_DETECT C
LOW:DP PORT ENABLED(Default)*
Hi:HDMI ENABLED

+3V_DP_UMA_CON +3V

R2319

1
100K_0402_5%
R2325
1M_0402_5% 5
1

CPU_DP_AUX_C_DP_SCL 2
CPU_DP_AUX_C_DN_SDA

2
1

4 3 CPU_DPB_HPD_CON
23 CPU_DPB_HPD
R2320 1 6
100K_0402_5%

1
Q103B R2326
Q103A
2

AO5804EL_SC89-6 20K_0402_1%
AO5804EL_SC89-6

2
B B

A A

LENOVO.CRDN
Title
UMA DP PORT
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 30 of 99
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

Panel Backlight Control eDP/RGB sensor JEDP1

1
+3VALW 2 1
3 2
4 3
4

1
R894 1 @ 2 0_0402_5% 5
63 FRAME_LOCK_N_R 5
R368 6
7 6
100K_0402_5% 7
C421 1 2 0.1U_0402_16V7K EDP_TX1_C_DN 8
59 GPU_EDP_TX1_DN EDP_TX1_C_DP 8
C419 1 2 0.1U_0402_16V7K 9
59 GPU_EDP_TX1_DP 9

2
D D
10
C422 1 2 0.1U_0402_16V7K EDP_TX0_C_DN 11 10
46 LID_30_N 59 GPU_EDP_TX0_DN EDP_TX0_C_DP 11
D20 C423 1 2 0.1U_0402_16V7K 12
EDP_BL_EN 59 GPU_EDP_TX0_DP 12
R369 1 2 1K_0402_5% 1 2 SDM10U45LP-7_DFN1006-2-2 13
26 MXLID_N C424 1 2 0.1U_0402_16V7K EDP_AUX_C_DP 14 13
59 GPU_EDP_AUX_DP EDP_AUX_C_DN 14
2 C425 1 2 0.1U_0402_16V7K 15
59 GPU_EDP_AUX_DN 15
16
C416 17 16
2 17
1
0.1U_0402_25V6
C418 eDP panel 18
19 18
19
0.1U_0402_25V6 +3V_EDP_CONN 20
1 21 20
22 21
23 22
24 23
GPU_EDP_HPD 25 24
59 GPU_EDP_HPD 26 25
6 3 26
27
Q5B 28 27
Q5A 29 28
AO5804EL_SC89-6 29
2 AO5804EL_SC89-6 5 EDP_BL_EN 30
17 FPBACK 63 EDP_BL_EN EDP_BL_PWM 30
31
63 EDP_BL_PWM 31
32
33 32 45
1 4 34 33 45 44
35 34 44 43
+V_BL_LED 35 43
36 42
37 36 42 41
38 37 41
39 38
40 39
40

C PANLE Contrl Signals ACES_50398-04071-001 C

+3V_EDP_CONN

2
+3V_EDP +3V_EDP_CONN
R373
100K_0402_5%
R65 1 2 0_0603_5%

1
1 EDP_AUX_C_DP

2
C427 C428 EDP_AUX_C_DN

1
10U_0402_6.3V6M

0.1U_0402_25V6
1
2 R374
100K_0402_5%

2
B B

Camera/DMIC
JCAM1

1
+3V_CAMERA 1
USB2_DN3
HD camera 18 USB2_DN3
18 USB2_DP3
USB2_DP3
2
3 2
3
4 9
5 4 9 10
6 5 10
28 DMIC_CLK 6
DMIC 28 DMIC_DATA
+3VD_AUD
7
8 7
8

I2C Repeater ACES_50376-00801-001

+3V_CAMERA

A A

LENOVO.CRDN

2
C433 C434
Title

10U_0603_10V

0.1U_0402_25V6
eDP/RGB/CAMERA/DMIC

1
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 31 of 99
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

CAD Note:
300mA Internal pull up at ~100kΩ, 3.3V I/O.
+3V +3V_DPA_REP

R382 2 1 0_0603_5%

1 2 2 2 2 2

1
C449 C435 C436 C437 C438 C439 C450
DPC_SW[1:0]=11, output swing=1000mv DPA_REP_SW0 R390 2 @ 1 4.7K_0402_5%

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
Inputs with internal 100 kΩ pull-up.

10U_0603_10V

1U_0402_10V6K
2
2 1 1 1 1 1 This pin sets the output Voltage Level in all channel when ENI2C is LOW.
D DPA_REP_SW1 D
R391 2 @ 1 4.7K_0402_5%
DPC_FG[1:0]=10, gain=0.5db
Inputs with internal 100 kΩ pull up resistor.
Sets the output flat gain level on all channels when ENI2C is low. DPA_REP_FG0 R392 2 1 4.7K_0402_5%

DPC_EQ[3:0]=0010, about 10inch,


Inputs with internal 100 kΩ pull-up. DPA_REP_FG1 R393 2 @ 1 4.7K_0402_5%
This pins set the amount of Equalizer Boost in all channel when ENI2C is LOW.
I2C Address=0xF2
DPA_REP_EQ0 R394 2 1 4.7K_0402_5%
DPC_I2C_RESET#:
Inputs with internal 100 kΩ pull up resistor.
Reset pin for I2C. When set low with reset the registers to default state. DPA_REP_EQ1 R397 2 @ 1 4.7K_0402_5%

1
+3V_DPA_REP
R2314 DPC_I2C_DONE:
4.7K_0402_5% Valid register load status output, use for daisy chain master DPA_REP_EQ2 R398 2 1 4.7K_0402_5%
Low = External EEPROM load failed
HIGH = External EEPROM load passed

2
DPA_REP_EQ3 R399 2 1 4.7K_0402_5%
DPC_PRSNT#:
This pin is active in both PIN mode(ENI2C=LOW) and I2C mode (ENI2C=HIGH).
U2015 Cable present detect input. This pin has internal 100 kΩ pull-up.

12
15
24
27
30
33
36
43

20
When High, a cable is not present, and the device is put in lower power mode.

3
6
9
When LOW, the device is enabled and in normal operation
Place BOT side.

PRSNT#
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
HGND
C448 1 2 0.1U_0402_16V7K DPA_TX0_DP_C 4 35 DP_TX0_OUT_DP
58 GPU_DPA_TX0_DP DPA_TX0_DN_C IN0P OUT0P DP_TX0_OUT_DN DP_TX0_OUT_DP 33
C451 1 2 0.1U_0402_16V7K 5 34
58 GPU_DPA_TX0_DN IN0N OUT0N DP_TX0_OUT_DN 33
C452 1 2 0.1U_0402_16V7K DPA_TX1_DP_C 7 32 DP_TX1_OUT_DP
58 GPU_DPA_TX1_DP DPA_TX1_DN_C IN1P OUT1P DP_TX1_OUT_DN DP_TX1_OUT_DP 33 Tuning by Pericom tool
C453 1 2 0.1U_0402_16V7K 8 31
58 GPU_DPA_TX1_DN IN1N OUT1N DP_TX1_OUT_DN 33
1 2 0.1U_0402_16V7K DPA_TX2_DP_C 10
PI3DPX1203ZHE-TQFN42P 29 DP_TX2_OUT_DP DPA_REP_SDA
C454 +3V_DPA_REP R2108 2 @ 1 4.7K_0402_5%
58 GPU_DPA_TX2_DP DPA_TX2_DN_C IN2P OUT2P DP_TX2_OUT_DN DP_TX2_OUT_DP 33
C455 1 2 0.1U_0402_16V7K 11 28
58 GPU_DPA_TX2_DN IN2N OUT2N DP_TX2_OUT_DN 33 DPA_REP_SCL
R2109 2 @ 1 4.7K_0402_5%
C456 1 2 0.1U_0402_16V7K DPA_TX3_DP_C 13 26 DP_TX3_OUT_DP
58 GPU_DPA_TX3_DP DPA_TX3_DN_C IN3P OUT3P DP_TX3_OUT_DN DP_TX3_OUT_DP 33
C457 1 2 0.1U_0402_16V7K 14 25

FG1/I2C_RESET#
58 GPU_DPA_TX3_DN IN3N OUT3N DP_TX3_OUT_DN 33 DPA_REP_ENI2C
C R2144 2 @ 1 4.7K_0402_5% C
16 23
17 NC NC 22 DPA_REP_I2C_DONE TESTPAD 1 TP96 R2242 1 2 0_0402_5% DPA_REP_SCL
NC I2C_DONE 26,34,47,79,80,87,90 EC_I2C_CLK3

EQ0/AD0
EQ1/AD1
EQ2/AD2
EQ3/AD3
R2243 1 2 0_0402_5% DPA_REP_SDA
26,34,47,79,80,87,90 EC_I2C_DATA3

ENI2C
SW1
SW0

SDA
FG0

SCL
Tuning by EC

Place BOT side.

1
2
37
38
39
40
41
42

DPA_REP_SDA 18
DPA_REP_SCL 19

21
DPC_ENI2C:

DPA_REP_SW1
DPA_REP_SW0

DPA_REP_EQ0
DPA_REP_EQ1
DPA_REP_EQ2
DPA_REP_EQ3
DPA_REP_FG0
DPA_REP_FG1

2DPA_REP_ENI2C
Input with internal 100 kΩ pull-up.
When LOW, each channel is programmed by the external pin voltage.
When HIGH, each channel is programmed by the data stored in the I2C bus.
When floating, master mode (Read External EEPROM)

Place BOT side.


+5V

R389

4.7K_0402_5%

2
+3V_DPA_REP R386

1
4.7K_0402_5%

1
2
DPA_DDC_EN
R387 6
4.7K_0402_5% Q6A
CAD Note:HDMI_DONGLE_DETECT AO5804EL_SC89-6

1
DPA_DDC_AUX_SEL 2
LOW:DP PORT ENABLED(Default)*
3
Hi:HDMI ENABLED
Q6B
1
AO5804EL_SC89-6
HDMI_DONGLE_DETECT 5
33 HDMI_DONGLE_DETECT

B B
4

+3V_DPA_REP +3V_DPA_REP

2
R395 R396

4.7K_0402_5% 4.7K_0402_5%
GPU_DPA_SDA
GPU_DPA_SCL

1
6 3
Q7A Q7B
AO5804EL_SC89-6 AO5804EL_SC89-6
DPA_DDC_EN 2 5
U2016
5

2
C599
M+

M-

GND

1 4
0.01U_0402_25V7K

1
C460 1 2 0.1U_0402_16V7K DPA_AUX_DN_C 6 2
58 GPU_DPA_AUX_DN_SDA D- Y- DP_AUX_OUT_DN_SDA 33
C461 1 2 0.1U_0402_16V7K DPA_AUX_DP_C 7 1
58 GPU_DPA_AUX_DP_SCL D+ Y+ DP_AUX_OUT_DP_SCL 33
VDD
OE#

SEL
8

DPA_DDC_AUX_SEL 10

PI3USB103ZLE-TQFN10P GPU_DPA_AUX_DN_SDA R402 1 2 0_0402_5% GPU_DPA_SDA

GPU_DPA_AUX_DP_SCL R403 1 2 0_0402_5% GPU_DPA_SCL


True Table for PI3USB102G
+3V_DPA_REP
2

A A
SEL OE# Y+ Y- R2315
4.7K_0402_5%

LENOVO.CRDN
X H Hi-Z Hi-Z 2
1

Title
C2715 DP1.3 REPEATER
L L M+ M-
1 Size Document Number
0.1U_0402_25V6

C Rev V0.3
H L D+ D- Skylake-H
Date: Thursday, May 26, 2016 Sheet 32 of 99
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

DPI SPEC IS 500mA


+3V +3V_DP_CON

1 2

1
C463 C464 C465

0.1U_0402_25V6
2

2
100K_0402_5%

10U_0603_10V

1U_0402_10V6K
2
R2313 U2030 2 1
1
6 1

R2312

100K_0402_5%
C2701 IN OUT
0.1U_0402_25V6 4 2
EN ILIM

1
2
D D
3 5
FAULT# GND

2
7
GND_PAD R2311
46.4K_0402_1%
AP2553FDC-7_U-DFN2020-6_2X2
ILIM=500mA

1
+3V_DP_CON
JDP1

20
DP_PWR
19
C466 1 2 0.1U_0402_16V7K DP_TX0_C_DP 1 RETURN
32 DP_TX0_OUT_DP DP_TX0_C_DN ML_LANE0+ DP_HPD_CON
C467 1 2 0.1U_0402_16V7K 3 18
32 DP_TX0_OUT_DN ML_LANE0- HOT_PLUG_DETECT DP_HPD_CON 58
C468 1 2 0.1U_0402_16V7K DP_TX1_C_DP 4 2
32 DP_TX1_OUT_DP DP_TX1_C_DN ML_LANE1+ GND1
C469 1 2 0.1U_0402_16V7K 6 5
32 DP_TX1_OUT_DN ML_LANE1- GND2 8
C470 1 2 0.1U_0402_16V7K DP_TX2_C_DP 7 GND3 11
32 DP_TX2_OUT_DP DP_TX2_C_DN ML_LANE2+ GND4 HDMI_DONGLE_DETECT
C471 1 2 0.1U_0402_16V7K 9 13
32 DP_TX2_OUT_DN ML_LANE2- CONFIG1 HDMI_CEC HDMI_DONGLE_DETECT 32
14
C472 1 2 0.1U_0402_16V7K DP_TX3_C_DP 10 CONFIG2 16
32 DP_TX3_OUT_DP DP_TX3_C_DN ML_LANE3+ GND
C473 1 2 0.1U_0402_16V7K 12
32 DP_TX3_OUT_DN ML_LANE3-

1
R405 1 2 0_0402_5% DP_AUX_C_DP_SCL 15 21
32 DP_AUX_OUT_DP_SCL DP_AUX_C_DN_SDA AUXCH+ CASE_GND1
R406 1 2 0_0402_5% 17 22 R807 R408
32 DP_AUX_OUT_DN_SDA AUXCH- CASE_GND2 23 1M_0402_5% 1M_0402_5% R409
CASE_GND3 24 100K_0402_5%
CASE_GND4
C C

2
ACON_DRA45-20

CAD Note:HDMI_DONGLE_DETECT
LOW:DP PORT ENABLED(Default)*
Hi:HDMI ENABLED

+3V_DP_CON
2

R410
100K_0402_5%
1

DP_AUX_OUT_DP_SCL
DP_AUX_OUT_DN_SDA
1

R411
100K_0402_5%
2

B B
CAD Note:Reserve for ESD

CAD Note:Reserve for ESD

DP_AUX_C_DN_SDA
DP_AUX_C_DP_SCL
DP_HPD_CON
D2019
DP_TX3_C_DN 1
DP_TX3_C_DP 2 D1+ 10
3 D1- NC4 9
8 GND1 NC3 7
DP_TX2_C_DN 4 GND2 NC2 6
DP_TX2_C_DP 5 D2+ NC1
D2-

2
TPD4E02B04DQAR_USON10
SC300005A00 D22 D23 D24

2
@ @ @

AZ5425-01F.R7GR

AZ5425-01F.R7GR

AZ5425-01F.R7GR
1

1
D2018

1
DP_TX1_C_DN 1
DP_TX1_C_DP 2 D1+ 10
3 D1- NC4 9
8 GND1 NC3 7
DP_TX0_C_DN 4 GND2 NC2 6
DP_TX0_C_DP 5 D2+ NC1
D2-
TPD4E02B04DQAR_USON10
SC300005A00
A A

LENOVO.CRDN
Title
DISPLAY PORT
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 33 of 99
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

CAD Note:
290mA Internal pull up at ~100kΩ, 3.3V I/O.
+3V +3V_HDMI_REP

R2137 2 1 0_0603_5%

1 2 2 2 2 2

1
C2172 C2169 C2171 C2170 C2167 C2166 C2168
DE[1:0]=01, De-emphasis=3.5db HDMI_REP_SW0 R2123 2 @ 1 4.7K_0402_5%

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
Inputs with internal 100k-Ohm Pull-Up.

10U_0603_10V

1U_0402_10V6K
2
2 1 1 1 1 1 This pins set the output De-Emphasis Level in all channel when Pin_Mode is HIGH.
HDMI_REP_SW1 R2138 2 1 4.7K_0402_5%
D D

PS[1:0]=10, Pre-shoot=3.5db HDMI_REP_FG0 R2140 2 1 4.7K_0402_5%


Inputs with internal 100k-Ohm Pull-Up.
This pins set the output Pre-Shoot Level in all channel when Pin_Mode is HIGH.
HDMI_REP_FG1 R2139 2 @ 1 4.7K_0402_5%

BST[3:0]:
Inputs with internal 100k-Ohm Pull-Up. HDMI_REP_EQ0 R2141 2 1 4.7K_0402_5%
This pins set the amount of Equalizer Boost in all channel when Pin mode is HIGH.

HDMI_REP_EQ1 R2142 2 @ 1 4.7K_0402_5%


+3V_HDMI_REP PEN:(PI3HDX1204B)

2
Power Enable with internal 100K-Ohm Pull-Up device is enabled and in normal operation.
R2316 Reserve 4.7K PD for PI3HDX1204D. HDMI_REP_EQ2 R2125 2 1 4.7K_0402_5%
@

4.7K_0402_5%
HDMI_REP_EQ3 R2126 2 1 4.7K_0402_5%

1
HDMI_REP_VOD1:
Inputs with internal 100k-Ohm Pull-Up.
U2019 This pin sets the output Voltage Level in all channel when Pin mode is HIGH. HDMI_REP_VOD1 R2238 2 1 4.7K_0402_5%

15
24
27
33
36

12
30
43

20
3
9

6
AC couping cap @ GPU side, and place close to U2019. A4/A1/A0:

VDD
VDD
VDD
VDD
VDD
VDD
VDD

GND
GND
GND
HGND

PEN
I2C programmable address bits, with internal 100k-Ohm Pull-Up. HDMI_REP_I2C_DONE_A0 R2239 2 @ 1 4.7K_0402_5%
I2C Addres=0xC2
GPU_HDMI_DATA2_DP 4 35 HDMI_DATA2_DP
59 GPU_HDMI_DATA2_DP GPU_HDMI_DATA2_DN A0RX+ A0TX+ HDMI_DATA2_DN HDMI_DATA2_DP 35 HDMI_REP_A1_VTH1
5 34 R2236 2 1 4.7K_0402_5%
59 GPU_HDMI_DATA2_DN A0RX- A0TX- HDMI_DATA2_DN 35
GPU_HDMI_DATA1_DP 7 32 HDMI_DATA1_DP
59 GPU_HDMI_DATA1_DP GPU_HDMI_DATA1_DN A1RX+ A1TX+ HDMI_DATA1_DN HDMI_DATA1_DP 35 HDMI_REP_A4_VTH0
8 31 R2237 2 1 4.7K_0402_5%
59 GPU_HDMI_DATA1_DN A1RX- A1TX- HDMI_DATA1_DN 35
GPU_HDMI_DATA0_DP 10
PI3HDX1204BZHE-TQFN42P 29 HDMI_DATA0_DP
59 GPU_HDMI_DATA0_DP GPU_HDMI_DATA0_DN A2RX+ A2TX+ HDMI_DATA0_DN HDMI_DATA0_DP 35
11 28
59 GPU_HDMI_DATA0_DN A2RX- A2TX- HDMI_DATA0_DN 35

59 GPU_HDMI_CLK_DP
GPU_HDMI_CLK_DP 13
A3RX+ A3TX+
26 HDMI_CLK_DP
HDMI_CLK_DP 35
Place BOT side.
GPU_HDMI_CLK_DN 14 25 HDMI_CLK_DN

FG1/I2C_RESET#
59 GPU_HDMI_CLK_DN A3RX- A3TX- HDMI_CLK_DN 35
C HDMI_REP_A1_VTH1 16 23 HDMI_REP_VOD1 C
HDMI_REP_A4_VTH0 17 DNC DNC 22 HDMI_REP_I2C_DONE_A0
DNC I2C_DONE

EQ0/AD0
EQ1/AD1
EQ2/AD2
EQ3/AD3

ENI2C
SW1
SW0

SDA
FG0

SCL
HDMI_REP_SW1 1
HDMI_REP_SW0 2
HDMI_REP_FG0 37
HDMI_REP_FG1 38
HDMI_REP_EQ0 39
HDMI_REP_EQ1 40
HDMI_REP_EQ2 41
HDMI_REP_EQ3 42

HDMI_REP_SDA 18
HDMI_REP_SCL 19

2HDMI_REP_ENI2C 21
Pin_Mode:(PI3HDX1204BZHE)
Input with internal 100k-Ohm Pull-Up.
When HIGH, each channel is programmed by the external pin voltage. Tuning by pericom tool
When LOW, each channel is programmed by the data stored in the I2C bus.
Place BOT side. R2130 2 @ 1 4.7K_0402_5% HDMI_REP_SDA
+3V_HDMI_REP
R2122 R2131 2 @ 1 4.7K_0402_5% HDMI_REP_SCL
@

4.7K_0402_5%
R2143 2 1 4.7K_0402_5% HDMI_REP_ENI2C

1
R2240 1 2 0_0402_5% HDMI_REP_SCL
26,32,47,79,80,87,90 EC_I2C_CLK3 HDMI_REP_SDA
26,32,47,79,80,87,90 EC_I2C_DATA3 R2241 1 2 0_0402_5%

Tuning by EC

Place BOT side.

B B

A A

LENOVO.CRDN
Title
HDMI2.0 REPEATER
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 34 of 99
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was

WWW.AliSaler.Com
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

+5V_HDMI_CON

2
C544
D D
0.1U_0402_25V6
1 JHDMI1
For HDMI2.0 CTS:
Test ID HF1-9, 100ohm impedance test 18 15 HDMI_DDC_CLK_R R443 1 2 0_0402_5% HDMI_DDC_CLK
+5V_POWER SCL 16 HDMI_DDC_DATA_R R444 1 2 0_0402_5% HDMI_DDC_DATA
SDA
HDMI_DATA0_DP R445 1 @ 2 0_0402_5% HDMI_DATA0_R_DP R2272 1 2 6.04_0402_1% HDMI_DATA0_Rs_DP 7
34 HDMI_DATA0_DP HDMI_DATA0_DN HDMI_DATA0_R_DN HDMI_DATA0_Rs_DN TMDS_DATA0+
R446 1 @ 2 0_0402_5% R2273 1 2 6.04_0402_1% 9 13
34 HDMI_DATA0_DN HDMI_DATA1_DP HDMI_DATA1_R_DP HDMI_DATA1_Rs_DP TMDS_DATA0- CEC
R447 1 @ 2 0_0402_5% R2274 1 2 6.04_0402_1% 4 17
34 HDMI_DATA1_DP HDMI_DATA1_DN HDMI_DATA1_R_DN HDMI_DATA1_Rs_DN TMDS_DATA1+ DDC/CEC_GROUNG HDMI_HPD
R448 1 @ 2 0_0402_5% R2275 1 2 6.04_0402_1% 6 19
34 HDMI_DATA1_DN HDMI_DATA2_DP HDMI_DATA2_R_DP HDMI_DATA2_Rs_DP TMDS_DATA1- HOT_PLUG_DETECT
R449 1 @ 2 0_0402_5% R2276 1 2 6.04_0402_1% 1
34 HDMI_DATA2_DP HDMI_DATA2_DN HDMI_DATA2_R_DN HDMI_DATA2_Rs_DN TMDS_DATA2+
R450 1 @ 2 0_0402_5% R2277 1 2 6.04_0402_1% 3 14
34 HDMI_DATA2_DN TMDS_DATA2- RESERVED#2

1
8
5 TMDS_DATA0_SHIELD R451
2 TMDS_DATA1_SHIELD
TMDS_DATA2_SHIELD 100K_0402_5%
20
11 GND0 21
TMDS_CLOCK_SHIELD GND1

2
HDMI_CLK_DP R452 1 @ 2 0_0402_5% HDMI_CLK_R_DP R2278 1 2 6.04_0402_1% HDMI_CLK_Rs_DP 10 22
34 HDMI_CLK_DP HDMI_CLK_DN HDMI_CLK_R_DN HDMI_CLK_Rs_DN TMDS_CLOCK+ GND2
R453 1 @ 2 0_0402_5% R2279 1 2 6.04_0402_1% 12 23
34 HDMI_CLK_DN TMDS_CLOCK- GND3

Singatron_2HE3Y36-000111F

CM BRD Note: CAD Note:


LS +3V_GPU
HDMI_DDC_CLK
2.2K_0402_5% D2014
1 R862 2 1 2 +5V_HDMI_CON
SDM10U45LP-7_DFN1006-2-2
C
Co-lay with R Reserve for EMI HDMI_DDC_DATA 1 R565 2 1 2 C
2.2K_0402_5% D2015
SDM10U45LP-7_DFN1006-2-2
CM3
HDMI_DATA0_DN 3 4 HDMI_DATA0_R_DN
3 4 NV recommended:
5
HDMI 2.0 requires I2C line capacitance less than 50pF
HDMI_DATA0_DP 2 1 HDMI_DATA0_R_DP
2 1
EXC24CH500U 4 3 HDMI_DDC_CLK
59 GPU_HDMI_DDC_CLK
2
Q41B
CM4 AO5804EL_SC89-6
HDMI_DATA1_DN 3 4 HDMI_DATA1_R_DN
3 4 1 6 HDMI_DDC_DATA
59 GPU_HDMI_DDC_DATA
HDMI_DATA1_DP 2 1 HDMI_DATA1_R_DP Q41A
2 1
AO5804EL_SC89-6
EXC24CH500U

+3V_GPU
CM5
HDMI_DATA2_DN 3 4 HDMI_DATA2_R_DN
3 4

HDMI_DATA2_DP 2 1 HDMI_DATA2_R_DP
2 1

1
EXC24CH500U R2285
1M_0402_5% 5
2
CM6

2
HDMI_CLK_DN 3 4 HDMI_CLK_R_DN
3 4 4 3 HDMI_HPD
59 GPU_HDMI_HPD
1 6
HDMI_CLK_DP 2 1 HDMI_CLK_R_DP
2 1

1
EXC24CH500U Q25B R568
AO5804EL_SC89-6 Q25A
B
20K_0402_1% B
AO5804EL_SC89-6

2
CAD Note:Reserve for ESD

Power switch ESD

HDMI_DDC_DATA_R
D26

HDMI_DDC_CLK_R
HDMI_CLK_R_DN 1
HDMI_CLK_R_DP 2 D1+ 10
3 D1- NC4 9

HDMI_HPD
8 GND1 NC3 7
HDMI_DATA0_R_DN 4 GND2 NC2 6
HDMI_DATA0_R_DP D2+ NC1
200mA 5
D2-
+5V_HDMI_CON TPD4E05U06DQAR_USON10
PU1 SC300005800

2
+5V
2 R440 2 1 0_0603_5% D27 D28 D29

2
OUT
3 2 @ @ @
IN
1

2 C542 C543
1

AZ5425-01F.R7GR

AZ5425-01F.R7GR

AZ5425-01F.R7GR
C541 @
GND
10U_0603_10V

0.1U_0402_25V6

D30
2

1
0.1U_0402_25V6

1
1 AP2331W-7_SC59 HDMI_DATA1_R_DN 1
D1+

1
HDMI_DATA1_R_DP 2 10
3 D1- NC4 9
8 GND1 NC3 7
HDMI_DATA2_R_DN 4 GND2 NC2 6
HDMI_DATA2_R_DP 5 D2+ NC1
A A
D2-
TPD4E05U06DQAR_USON10
SC300005800 LENOVO.CRDN
Title
HDMI CONN,
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 35 of 99
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

210mA
+3V +3V_DPE_REP DPE_CFG0 2 R492 1 +3V_DPE_REP
Configuration pin for automatic EQ and AUX interception; Internal pull down at ~150kΩ, 3.3V I/O.
@ 4.7K_0402_5% L: default, automatic EQ enable & AUX interception enable
R421 2 1 0_0603_5% H: automatic EQ disable & AUX interception enable
2 R541 1 M: automatic EQ disable & AUX interception disable, no pre-emphasis, 600mVpp swing
1 2 2 2 2 2

1
C529 C526 C528 C527 C496 C493 C497 @ 4.7K_0402_5%

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
10U_0603_10V

1U_0402_10V6K
2
2 1 1 1 1 1
DPE_CFG1 2 R454 1 +3V_DPE_REP
Configuration pin for auto test and input offset cancellation, 3.3V IO, internal pull up at ~150K
@ 4.7K_0402_5% H: default, auto test disable & input offset cancellation enable
D L: auto test enable & input offset cancellation enable D
2 R422 1 M: auto test disable & input offset cancellation disable

@ 4.7K_0402_5%
+3V_DPE_REP

DPE_PEQ 2 R518 1 +3V_DPE_REP


Programmable input equalization levels; Internal pull down at ~150kΩ, 3.3V I/O.
R2280 2 1 10K_0402_5% DPE_RST_N 4.7K_0402_5% L: default, LEQ, compensate channel loss up to 12dB @ HBR2
H: HEQ, compensate channel loss up to 15dB @ HBR2
M: LLEQ, compensate channel loss up to 5dB @ HBR2
CAD Note:DPE_REDRIVER_PD 2 R436 1
TP97 Chip power down,active LOW 4.7K_0402_5%
C2687 2.2U_0402_6.3V6M

TESTPAD Internal pull UP at ~150kΩ, 3.3V I/O.


H=Normal operation(default)
L=Chip power down

1
DDI1_AUX_OUT_DN
DDI1_AUX_OUT_DP
+3V_DPE_REP

+3V_DPE_REP

+3V_DPE_REP
DPE_AUX_DN_C
DPE_AUX_DP_C
DPE_RST_N

DPE_PD
U2013

36
35
34
33
32
31
30
29
28
27
26
25
VDD33
RST#

AUX_SRCp
AUX_SRCn
AUX_SNKp
AUX_SNKn
PD#
SDA_DDC
SCL_DDC
VDD33
GND

VDD33
37 24
NC GND
C480 1 2 0.1U_0402_16V7K DPE_TX0_DP_C 38 23 DDI1_DP0
60 GPU_DPE_TX0_DP DPE_TX0_DN_C IN0p OUT0p DDI1_DN0 DDI1_DP0 38
C479 1 2 0.1U_0402_16V7K 39 22
60 GPU_DPE_TX0_DN DPE_CFG1 IN0n OUT0n DDI1_DN0 38
C 40 21 C
C477 1 2 0.1U_0402_16V7K DPE_TX1_DP_C 41 CFG1 NC 20 DDI1_DP1
60 GPU_DPE_TX1_DP DPE_TX1_DN_C IN1p OUT1p DDI1_DN1 DDI1_DP1 38
1 2 0.1U_0402_16V7K 42 19
IN1n PS8330BQFN48GTR2
C481
60 GPU_DPE_TX1_DN OUT1n DDI1_DN1 38
43 18
NC GND
C478 1 2 0.1U_0402_16V7K DPE_TX2_DP_C 44 17 DDI1_DP2
60 GPU_DPE_TX2_DP DPE_TX2_DN_C IN2p OUT2p DDI1_DN2 DDI1_DP2 38
C484 1 2 0.1U_0402_16V7K 45 16
60 GPU_DPE_TX2_DN IN2n OUT2n DDI1_DN2 38

SDA_CTL/CFG0
46 15 +3V_DPE_REP

SCL_CTL/PEQ
C483 1 2 0.1U_0402_16V7K DPE_TX3_DP_C 47 NC NC 14 DDI1_DP3
60 GPU_DPE_TX3_DP DPE_TX3_DN_C IN3p OUT3p DDI1_DN3 DDI1_DP3 38
1 2 0.1U_0402_16V7K 48 13

I2C_ADDR
C482

CAD_SRC
HPD_SRC
CAD_SNK
HPD_SNK
60 GPU_DPE_TX3_DN IN3n OUT3n DDI1_DN3 38
49

VDD33

VDD33

VDD33
EPAD

2
CEXT

REXT
R510
100K_0402_5%
+3V_DPE_REP 1
2
3
4
5
+3V_DPE_REP 6
7
1DPE_CAD_SRC 8
GPU_DPE_HPD 9
1 DPE_CAD_SNK10
DPE_HPD_SNK11
+3V_DPE_REP12

1
DDI1_AUX_OUT_DP R584 1 2 0_0402_5% DDI1_AUX_OUT_DP
DDI1_AUX_DP 38 DDI1_AUX_OUT_DN
DPE_CFG0
DPE_PEQ

DDI1_AUX_OUT_DN R585 1 2 0_0402_5%


DDI1_AUX_DN 38

1
C530 1 2 0.1U_0402_16V7K DPE_AUX_DN_C
60 GPU_DPE_AUX_DN_SDA DPE_AUX_DP_C
C531 1 2 0.1U_0402_16V7K R489
60 GPU_DPE_AUX_DP_SCL
100K_0402_5%
1
R455

2
C525 2.2U_0402_6.3V6M

R2104

60 GPU_DPE_HPD
4.99K_0402_1%

TP186
1M_0402_5%

DPE_CAD_SNK PD:
DP mode. Internal PD 150KR
TESTPAD
2

2
1

DPE_HPD_SNK R420 1 2 0_0402_5%


DDI1_HPD 38
R940
@
100K_0402_5%
2

B B
I2C_ADDR:
LOW=Pin control is selected.
High=I2C control is selected with default I2C address 42/437

A A

LENOVO.CRDN
Title
AR DP REPEATER-1
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 36 of 99
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

210mA
+3V +3V_DPF_REP

R424 2 1 0_0603_5%

1 2 2 2 2 2

1
C573 C538 C540 C539 C508 C507 C514

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
10U_0603_10V

1U_0402_10V6K
2
2 1 1 1 1 1

D DPF_CFG0 D
2 R590 1 +3V_DPF_REP
Configuration pin for automatic EQ and AUX interception; Internal pull down at ~150kΩ, 3.3V I/O.
@ 4.7K_0402_5% L: default, automatic EQ enable & AUX interception enable
H: automatic EQ disable & AUX interception enable
2 R595 1 M: automatic EQ disable & AUX interception disable, no pre-emphasis, 600mVpp swing
+3V_DPF_REP
@ 4.7K_0402_5%
CAD Note:DPF_REDRIVER_PD
R2281 2 1 10K_0402_5% DPF_RST_N TP185 Chip power down,active LOW
TESTPAD Internal pull UP at ~150kΩ, 3.3V I/O. DPF_CFG1 2 R487 1 +3V_DPF_REP
H=Normal operation(default) Configuration pin for auto test and input offset cancellation, 3.3V IO, internal pull up at ~150K
@ 4.7K_0402_5% H: default, auto test disable & input offset cancellation enable
L=Chip power down L: auto test enable & input offset cancellation enable
C2688 2.2U_0402_6.3V6M

M: auto test disable & input offset cancellation disable

1
2 R425 1

DDI2_AUX_OUT_DN
DDI2_AUX_OUT_DP
DPF_AUX_DN_C
DPF_AUX_DP_C
@ 4.7K_0402_5%

+3V_DPF_REP

+3V_DPF_REP

+3V_DPF_REP
DPF_PD
DPF_RST_N
DPF_PEQ 2 R591 1 +3V_DPF_REP
Programmable input equalization levels; Internal pull down at ~150kΩ, 3.3V I/O.
4.7K_0402_5% L: default, LEQ, compensate channel loss up to 12dB @ HBR2
H: HEQ, compensate channel loss up to 15dB @ HBR2
2 R437 1 M: LLEQ, compensate channel loss up to 5dB @ HBR2

U2014 4.7K_0402_5%

36
35
34
33
32
31
30
29
28
27
26
25
VDD33
RST#

AUX_SRCp
AUX_SRCn
AUX_SNKp
AUX_SNKn
PD#
VDD33
SDA_DDC
SCL_DDC
VDD33
GND
37 24
NC GND
C488 1 2 0.1U_0402_16V7K DPF_TX0_DP_C 38 23 DDI2_DP0
60 GPU_DPF_TX0_DP DPF_TX0_DN_C IN0p OUT0p DDI2_DN0 DDI2_DP0 38
C487 1 2 0.1U_0402_16V7K 39 22
60 GPU_DPF_TX0_DN DPF_CFG1 IN0n OUT0n DDI2_DN0 38
40 21
C485 1 2 0.1U_0402_16V7K DPF_TX1_DP_C 41 CFG1 NC 20 DDI2_DP1
60 GPU_DPF_TX1_DP DPF_TX1_DN_C IN1p OUT1p DDI2_DN1 DDI2_DP1 38
1 2 0.1U_0402_16V7K 42 19
IN1n PS8330BQFN48GTR2
C489
60 GPU_DPF_TX1_DN OUT1n DDI2_DN1 38
C C
43 18
NC GND
C486 1 2 0.1U_0402_16V7K DPF_TX2_DP_C 44 17 DDI2_DP2
60 GPU_DPF_TX2_DP DPF_TX2_DN_C IN2p OUT2p DDI2_DN2 DDI2_DP2 38
C492 1 2 0.1U_0402_16V7K 45 16
60 GPU_DPF_TX2_DN IN2n OUT2n DDI2_DN2 38

SDA_CTL/CFG0
46 15

SCL_CTL/PEQ
C491 1 2 0.1U_0402_16V7K DPF_TX3_DP_C 47 NC NC 14 DDI2_DP3
60 GPU_DPF_TX3_DP DPF_TX3_DN_C IN3p OUT3p DDI2_DN3 DDI2_DP3 38
1 2 0.1U_0402_16V7K 48 13

I2C_ADDR
C490

CAD_SRC
HPD_SRC
CAD_SNK
HPD_SNK
60 GPU_DPF_TX3_DN IN3n OUT3n DDI2_DN3 38
49

VDD33

VDD33

VDD33
EPAD +3V_DPF_REP

CEXT

REXT
+3V_DPF_REP 1
2
3
4
5
+3V_DPF_REP 6
7
1DPF_CAD_SRC 8
GPU_DPF_HPD 9
1 DPF_CAD_SNK10
DPF_HPD_SNK11
+3V_DPF_REP12

2
R439

DPF_CFG0
100K_0402_5%
DPF_PEQ DDI2_AUX_OUT_DP R773 1 2 0_0402_5%
DDI2_AUX_DP 38

1
DDI2_AUX_OUT_DN R632 1 2 0_0402_5% DDI2_AUX_OUT_DP
DDI2_AUX_DN 38 DDI2_AUX_OUT_DN
C582 1 2 0.1U_0402_16V7K DPF_AUX_DN_C
60 GPU_DPF_AUX_DN
1

1
C583 1 2 0.1U_0402_16V7K DPF_AUX_DP_C
60 GPU_DPF_AUX_DP Internal PD 150KR
C537

R488 R2105 R438


DPF_HPD_SNK R423 1 2
4.99K_0402_1%

1M_0402_5%
0_0402_5% 100K_0402_5%
TP187 CAD_SNK PD: DDI2_HPD 38
TESTPAD

DP mode
2.2U_0402_6.3V6M

60 GPU_DPF_HPD
2

2
1

R942
@
100K_0402_5%
2

I2C_ADDR:
LOW=Pin control is selected.
High=I2C control is selected with default I2C address 42/437

B B

A A

LENOVO.CRDN
Title
AR DP MUX-2
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 37 of 99
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
1

VCC3V3_LC

AR-DP TYPE C +USB 3.1 (3.0)


JTAG

2
R2011

R2012

R2013

R2014
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
1

1
C2027 2 1 0.22U_0201_6.3V Y23 V23 C2028 2 1 0.22U_0201_6.3V
TBT_TDI 18 PCIE1_TBT_TX_DP0 PCIE_RX0_P PCIE_TX0_P PCIE1_TBT_RX_DP0 18
C2029 2 1 0.22U_0201_6.3V Y22 V22 C2030 2 1 0.22U_0201_6.3V
TBT_TMS 18 PCIE1_TBT_TX_DN0 PCIE_RX0_N PCIE_TX0_N PCIE1_TBT_RX_DN0 18
TBT_TCK C2031 2 1 0.22U_0201_6.3V T23 P23 C2032 2 1 0.22U_0201_6.3V
TBT_TDO 18 PCIE2_TBT_TX_DP1 PCIE_RX1_P PCIE_TX1_P PCIE2_TBT_RX_DP1 18
C2033 2 1 0.22U_0201_6.3V T22 P22 C2034 2 1 0.22U_0201_6.3V

PCIe GEN3
18 PCIE2_TBT_TX_DN1 PCIE_RX1_N PCIE_TX1_N PCIE2_TBT_RX_DN1 18
C2035 2 1 0.22U_0201_6.3V M23 K23 C2036 2 1 0.22U_0201_6.3V
18 PCIE3_TBT_TX_DP2 PCIE_RX2_P PCIE_TX2_P PCIE3_TBT_RX_DP2 18
C2037 2 1 0.22U_0201_6.3V M22 K22 C2038 2 1 0.22U_0201_6.3V
18 PCIE3_TBT_TX_DN2 PCIE_RX2_N PCIE_TX2_N PCIE3_TBT_RX_DN2 18
C2039 2 1 0.22U_0201_6.3V H23 F23 C2040 2 1 0.22U_0201_6.3V
18 PCIE4_TBT_TX_DP3 PCIE_RX3_P PCIE_TX3_P PCIE4_TBT_RX_DP3 18
C2041 2 1 0.22U_0201_6.3V H22 F22 C2042 2 1 0.22U_0201_6.3V
18 PCIE4_TBT_TX_DN3 PCIE_RX3_N PCIE_TX3_N PCIE4_TBT_RX_DN3 18
R2010 2 1 1M_0402_5%
XTAL 22 CK_TBT_P
V19
T19 PCIE_REFCLK_100_IN_P PERST_N
L4 PCIE_AR_RST_N R2101 1 2 0_0402_5%
PLT_RST_N 17,26,27,40,42,43,49,50,63
22 CK_TBT_N CK_REQ_TBT_N_R PCIE_REFCLK_100_IN_N PCIE_RBIAS
R2067 1 20_0402_5% AC5 N16 R2015 1 2 3.01k_0402_1%
22 CK_REQ_TBT_N PCIE_CLKREQ_N PCIE_RBIAS
4
Y2001
TBT_XTAL_25_IN 1 3 TBT_XTAL_25_OUT C2043 2 1 0.1u_0201_10V6K AB7 R2
36 DDI1_DP0 DPSNK0_ML0_P DPSRC_ML0_P
C2044 2 1 0.1u_0201_10V6K AC7 R1
36 DDI1_DN0 DPSNK0_ML0_N DPSRC_ML0_N
1 1
2

C2048 C2045 2 1 0.1u_0201_10V6K AB9 N2


36 DDI1_DP1 DPSNK0_ML1_P DPSRC_ML1_P
25MHZ_8PF_EXS00A-CS07258 C2046 C2047 2 1 0.1u_0201_10V6K AC9 N1
36 DDI1_DN1 DPSNK0_ML1_N DPSRC_ML1_N

SOURCE PORT 0
10P_0402_50V8J 10P_0402_50V8J
2 2

SINK PORT 0
C2049 2 1 0.1u_0201_10V6K AB11 L2
36 DDI1_DP2 DPSNK0_ML2_P DPSRC_ML2_P
C2050 2 1 0.1u_0201_10V6K AC11 L1
36 DDI1_DN2 DPSNK0_ML2_N DPSRC_ML2_N
C2051 2 1 0.1u_0201_10V6K AB13 J2
36 DDI1_DP3 DPSNK0_ML3_P DPSRC_ML3_P
C2052 2 1 0.1u_0201_10V6K AC13 J1
36 DDI1_DN3 DPSNK0_ML3_N DPSRC_ML3_N
C2153 1 2 0.1U_0402_16V7K Y11 W19
36 DDI1_AUX_DP DPSNK0_AUX_P DPSRC_AUX_P
C2154 1 2 0.1U_0402_16V7K W11 Y19
36 DDI1_AUX_DN DPSNK0_AUX_N DPSRC_AUX_N
VCC3V3_SX_SYS_AR DDI1_HPD AA2 G1 TBT_SRC_HPD
36 DDI1_HPD
GPIO TBT_SNK0_DDC_CLK Y5
DPSNK0_HPD DPSRC_HPD
N6 R2032 1 2 14k_0402_1%
CK_REQ_TBT_N_R R2066 1 @ 2 10K_0402_5% TBT_SNK0_DDC_DATA R4 DPSNK0_DDC_CLK DPSRC_RBIAS
DPSNK0_DDC_DATA U1 TBT_I2C_SDA
TBT_I2C_SDA GPIO_0 TBT_I2C_SCL TBT_I2C_SDA 40
R2026 1 2 2.2K_0402_5% C2056 2 1 0.1u_0201_10V6K AB15 U2
37 DDI2_DP0 DPSNK1_ML0_P GPIO_1 TBT_EE_WP_N TBT_I2C_SCL 40
C2057 2 1 0.1u_0201_10V6K AC15 V1
37 DDI2_DN0 DPSNK1_ML0_N GPIO_2

LC GPIO
TBT_I2C_SCL R2028 1 2 2.2K_0402_5% V2 TBT_TMU_CLK_OUT
C2058 2 1 0.1u_0201_10V6K AB17 GPIO_3 W1 TBT_WAKE_N R2094 1 2 0_0402_5%
TBT_CIO_PLUG_EVENT_N_R R2053 1 37 DDI2_DP1 DPSNK1_ML1_P GPIO_4 TBT_CIO_PLUG_EVENT_N_R PCIE_WAKE_N 19,42
2 10K_0402_5% C2059 2 1 0.1u_0201_10V6K AC17 W2 R2031 2 1 0_0402_5%
37 DDI2_DN1 DPSNK1_ML1_N GPIO_5 TBT_HDMI_DDC_DATA TBT_CIO_PLUG_EVENT_N 23
Y1
DP/HDMI CONFIGURATION: TBT_SRC_CFG1 R2023 1 2 10K_0402_5% C2060 2 1 0.1u_0201_10V6K AB19 GPIO_6 Y2 TBT_HDMI_DDC_CLK
High:HDMI 37 DDI2_DP2 DPSNK1_ML2_P GPIO_7 TBT_SRC_CFG1

SINK PORT 1
@ C2061 2 1 0.1u_0201_10V6K AC19 AA1
Low: DP TBTA_I2C_INT 37 DDI2_DN2 DPSNK1_ML2_N GPIO_8 TBTA_I2C_INT
R2037 1 2 10K_0402_5% J4
C2062 2 1 0.1u_0201_10V6K AB21 POC_GPIO_0 E2 TBT_PROC_GPIO1 TBTA_I2C_INT 40
37 DDI2_DP3 DPSNK1_ML3_P POC_GPIO_1

POC GPIO
TBT_PROC_GPIO1 R2024 1 2 10K_0402_5% C2063 2 1 0.1u_0201_10V6K AC21 D4 RTD3_USB_PWR_EN_R R2043 1 @ 2 0_0402_5%
37 DDI2_DN3 DPSNK1_ML3_N POC_GPIO_2 TBT_FORCE_PWR_R TBT_USB_PWR_EN 23
H4 R2039 1 2 0_0402_5%
TBT_SLP_S3_N R2034 1 @ 2 10K_0402_5% C2133 1 2 0.1U_0402_16V7K Y12 POC_GPIO_3 F2 TBT_BATLOW_N TBT_FORCE_PWR 23,40
37 DDI2_AUX_DP DPSNK1_AUX_P POC_GPIO_4 TBT_SLP_S3_N
C2134 1 2 0.1U_0402_16V7K W12 D2 R2033 2 1 0_0402_5%
TBT_BATLOW_N 37 DDI2_AUX_DN DPSNK1_AUX_N POC_GPIO_5 RTD3_CIO_PWR_EN_R SLP_S3_N 19,26
R2036 1 2 10K_0402_5% F1 R2041 1 @ 2 0_0402_5%
Change to 10k ohm PU DDI2_HPD Y6 POC_GPIO_6 TBT_CIO_PWR_EN 23
37 DDI2_HPD DPSNK1_HPD
RTD3_CIO_PWR_EN_R R2282 1 2 10K_0402_5% E1 TBT_TEST_EN R2025 1 2 100_0402_5%
TBT_SNK1_DDC_CLK Y8 TEST_EN
DPSNK1_DDC_CLK

Misc
TBT_SNK0_CFG1 N4 AB5 TBT_TEST_PWG R2027 1 2 100_0402_5%
DPSNK1_DDC_DATA TEST_PWR_GOOD
R2029 1 2 14k_0402_1% DPSNK_RBIAS Y18 F4 TBT_RESET_N_R R2030 1 2 0_0402_5%
DPSNK_RBIAS RESET_N TBT_RESET_N 40
DDI1_HPD R2057 1 2 100K_0402_5% TBT_TDI Y4 D22 TBT_XTAL_25_IN
TBT_TMS V4 TDI XTAL_25_IN D23 TBT_XTAL_25_OUT
TMS XTAL_25_OUT
1 1
DDI2_HPD R2083 1 2 100K_0402_5% TBT_TCK T4
TBT_TDO TCK TBT_EE_DI
W4
TDO MISC EE_DI
AB3
TBT_EE_DI 38,40
TBT_SNK1_DDC_CLK R2054 1 2 100K_0402_5% AC4 TBT_EE_DO
R2035 1 2 4.75k_0402_0.5% TBT_RBIAS H6 EE_DO AC3 TBT_EE_CS_N TBT_EE_DO 38,40
TBT_SNK0_CFG1 R2082 1 2 100K_0402_5% TBT_RSENSE J6 RBIAS EE_CS_N AB4 TBT_EE_CLK TBT_EE_CS_N 38,40
RSENSE EE_CLK TBT_EE_CLK 38,40
TBT_TMU_CLK_OUT R2038 1 2 100K_0402_5% A15 B7
Change to 10k ohm PD 40 TBTA_RX1_P PA_RX1_P PB_RX1_P
B15 A7
TBT_FORCE_PWR_R 40 TBTA_RX1_N PA_RX1_N PB_RX1_N
R2040 1 2 10K_0402_5%
C2066 2 1 0.22U_0201_6.3V A17 A9
RTD3_CIO_PWR_EN_R R2042 1 2 100K_0402_5% 40 TBTA_TX1_P C2067 2 1 0.22U_0201_6.3V B17 PA_TX1_P PB_TX1_P B9
@ 40 TBTA_TX1_N PA_TX1_N PB_TX1_N
RTD3_USB_PWR_EN_R R2044 1 2 100K_0402_5% C2068 2 1 0.22U_0201_6.3V A19 A11
40 TBTA_TX0_P C2069 2 1 0.22U_0201_6.3V B19 PA_TX0_P PB_TX0_P B11 TBTB_TX0_P 41
TBTA_LSRX R2045 2 1 1M_0402_5% 40 TBTA_TX0_N PA_TX0_N PB_TX0_N TBTB_TX0_N 41
B21 A13

TBT PORTS
TBTA_LSTX 40 TBTA_RX0_P PA_RX0_P PB_RX0_P TBTB_RX0_P 41
R2048 2 1 1M_0402_5% A21 B13
40 TBTA_RX0_N PA_RX0_N PB_RX0_N TBTB_RX0_N 41

Port A

PORT B
TBTA_HPD R2049 1 2 100K_0402_5% C2070 2 1 0.1u_0201_10V6K Y15 Y16
40 TBTA_DPSRC_AUX_P PA_DPSRC_AUX_P PB_DPSRC_AUX_P
C2071 2 1 0.1u_0201_10V6K W15 W16
TBTB_HPD 40 TBTA_DPSRC_AUX_N PA_DPSRC_AUX_N PB_DPSRC_AUX_N
R2050 1 2 100K_0402_5%
DPSRC NOT USED. E20 E19
TBT_SNK0_DDC_CLK 40 TBTA_USB2_D_P PA_USB2_D_P PB_USB2_D_P TBTB_USB2_D_P 41
R2118 1 2 100K_0402_5% D20 D19
40 TBTA_USB2_D_N PA_USB2_D_N PB_USB2_D_N TBTB_USB2_D_N 41
TBT_SNK0_DDC_DATA R2119 1 2 100K_0402_5% A5 B4 TBTB_LSTX R2051 1 2 100K_0402_5%
40 TBTA_LSTX A4 PA_LSTX PB_LSTX B5 TBTB_LSRX R2052 1 2 100K_0402_5%

POC
POC
TBT_SRC_CFG1 40 TBTA_LSRX PA_LSRX PB_LSRX TBTB_HPD
R2120 2 1 1M_0402_5% M4 G2
40 TBTA_HPD PA_DPSRC_HPD PB_DPSRC_HPD
TBT_SRC_HPD R2121 2 1 1M_0402_5% R2046 2 1 499_0402_1% PA_USB2_RBIAS H19 F19 PB_USB2_RBIAS R2047 2 1 499_0402_1%
PA_USB2_RBIAS PB_USB2_RBIAS
TBT_HDMI_DDC_CLK R2283 1 2 100K_0402_5% AC23 D6
AB23 THERMDA MONDC_SVR
TBT_HDMI_DDC_DATA R2284 1 2 100K_0402_5% THERMDA A23
V18 ATEST_P B23
PCIE_ATEST ATEST_N
AC1
TEST_EDM DEBUG USB2_ATEST
E18

L15 W13
N15 FUSE_VQPS_64 MONDC_DPSNK_0
FUSE_VQPS_128 W18
C23 MONDC_DPSNK_1
VCC3V3_FLASH C22 MONDC_CIO_0 AB2
AR/PPS COMMON FLASH MONDC_CIO_1 MONDC_DPSRC
ROM U2005A
AR_4C_C0 STEP
1 1 SA00007YH00
R2017 R2018 R2019 C2055 C2100 R2020
2
2.2K_0402_5%

2.2K_0402_5%
3.3k_0402_5%

3.3k_0402_5%
2

0.1u_0201_10V6K 10U_0402_6.3V6M
2 2
1

U2012
1

38,40 TBT_EE_CS_N 1 8
CS VCC
38,40 TBT_EE_DO 2 7 TBT_HOLD_N IF SOME OF GPIOs ARE NOT IN USE FOLLOW TABLE BELOW:
DO HOLD
GPIO | TERMINATION | Power Rail
TBT_EE_WP_N 3 6 ----------------------------------------------------
WP CLK TBT_EE_CLK 38,40
GPIO_0 | 10K PU | VCC3V3_LC DEBUG PINs:
4 5
GND DI TBT_EE_DI 38,40 GPIO_1 | 10K PU | VCC3V3_LC
GPIO_2 | 3.3K PU | PIN | TERMINATION LENOVO.CRDN
GPIO_3 | 100k PD | ------------------------------- Title
W25Q80DVSSIG_SO8 MONDC_SVR | GND
GPIO_4 | 10K PU | VCC3V3_LC DDI redriver PS8330
GPIO_5 | 10K PU | VCC3V3_LC MONDC_DPSNK_0 | GND
GPIO_6 | 100K PD | SRC NOT USED MONDC_DPSNK_1 | GND Size Document Number
MONDC_DPSRC | GND C Rev V0.3
GPIO_7 | 100K PD | SRC NOT USED Skylake-H
GPIO_8 | 1M PD | SRC NOT USED MONDC_CIO_0 | GND
POC_GPIO_0 | 10K PU | VCC3V3_TBT_SX MONDC_CIO_1 | GND Date: Thursday, May 26, 2016 Sheet 38 of 99

WWW.AliSaler.Com
TEST_EDM | GND "PROPERTY NOTE: this document contains information confidential and
POC_GPIO_1 | 10K PU | VCC3V3_TBT_SX property to LENOVO PND and shall not be reproduced or transferred to other documents
POC_GPIO_2 | 100K PD | FUSE_VQPS_64 | GND or disclosed to others or used for any purpose other than that for which it was
POC_GPIO_3 | 10K PD | FUSE_VQPS_128 | GND obtained without the expressed written consent of LENOVO PND."
POC_GPIO_4 | 10K PU | VCC3V3_TBT_SX ATEST_P/N | FLOATING
POC_GPIO_5 | 10K PU | VCC3V3_TBT_SX USB2_ATEST | FLOATING
POC_GPIO_6 | 100K PD | PCIE_ATEST | FLOATING
1

VCC3V3_LC VCC3V3_SX_SYS_AR

VCC0V9_USB VCC0V9_DP VCC3V3_S0 VCC3V3_S0_SYS

0.1u_0201_10V6K C2081

1U_0201_10V6K C2082
1 1

1U_0201_10V6K C2074

1U_0201_10V6K C2076

1U_0201_10V6K C2077

1U_0201_10V6K C2078

1U_0201_10V6K C2079

1U_0201_10V6K C2080
1 1 1 1 1 1 1 1 1 1 1 1
C2083 C2084 C2085 C2086 C2087 C2088
1U_0201_10V6K C2072

1U_0201_10V6K C2073

1 1
2 2

1U_0201_10V6K

1U_0201_10V6K

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
2 2 2 2 2 2 2 2 2 2 2 2
2 2 VCC0V9_CIO VCC0V9_USB VCC0V9_PCIE VCC0V9_DP

R13
R6

H9
F8
L8 A2

VCC3P3_SX

VCC3P3A
VCC3P3_S0
VCC3P3_LC
L11 VCC0P9_DP VCC3P3_SVR A3
L12 VCC0P9_DP VCC3P3_SVR B3
M8 VCC0P9_DP VCC3P3_SVR
T11 VCC0P9_DP
T12 VCC0P9_DP L9 VCC0V9_SVR
L6 VCC0P9_DP VCC0P9_SVR M9

1U_0201_10V6K C2089

1U_0201_10V6K C2090

1U_0201_10V6K C2091

1U_0201_10V6K C2092

1U_0201_10V6K C2093

1U_0201_10V6K C2094

1U_0201_10V6K C2095
VCC0P9_ANA_DPSRC VCC0P9_SVR 1 1 1 1 1 1 1
M6 E12
V11 VCC0P9_ANA_DPSRC VCC0P9_SVR_ANA E13
V12 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F11
V13 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F12 2 2 2 2 2 2 2
VCC0V9_CIO VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F13
M13 VCC0P9_SVR_ANA F15
VCC0V9_PCIE M15 VCC0P9_PCIE VCC0P9_SVR_ANA J9
M16 VCC0P9_PCIE VCC0P9_SVR_SENSE
L19 VCC0P9_PCIE
N19 VCC0P9_ANA_PCIE_1 C1 TBT_SVR_IND 1 2
1U_0201_10V6K C2101

1U_0201_10V6K C2102

1 1 VCC0P9_ANA_PCIE_1 SVR_IND
L18 C2 PL2001
1U_0201_10V6K C2096

1U_0201_10V6K C2097

1U_0201_10V6K C2098

1U_0201_10V6K C2099

1 1 1 1 VCC0P9_ANA_PCIE_2 SVR_IND
M18 D1 0.68uH_EM-68BM01V01_7.5A_20%
1 1 1
N18 VCC0P9_ANA_PCIE_2 SVR_IND C2103 C2104 C2105
VCC0P9_ANA_PCIE_2

VCC
2 2

47U_0603_4V

47U_0603_4V

47U_0603_4V
2 2 2 2 R15 A1
R16 VCC0P9_USB SVR_VSS B1 2 2 2
VCC0P9_USB SVR_VSS B2
R8 SVR_VSS
R9 VCC0P9_CIO
R11 VCC0P9_CIO
R12 VCC0P9_CIO F18
VCC0P9_CIO VCC0P9_LVR H18
VCC3V3_ANA_PCIE L16 VCC0P9_LVR J11
VCC3V3_ANA_USB2 J16 VCC3P3_ANA_PCIE VCC0P9_LVR H11
VCC3P3_ANA_USB2 VCC0P9_LVR_SENSE VCC0V9_LVR_OUT
1 1
C2107 C2108 A6 V5 1 1 1 1
+3V VCC3V3_S0_SYS 1U_0201_10V6K 1U_0201_10V6K A8 VSS_ANA VSS_ANA V6 C2109 C2110 C2111 C2112
A10 VSS_ANA VSS_ANA V8
2 2 A12 VSS_ANA VSS_ANA V9

1U_0201_10V6K

1U_0201_10V6K
10U_0402_6.3V6M

10U_0402_6.3V6M
A14 VSS_ANA VSS_ANA V15 2 2 2 2
R2055 1 @ 2 0_0603_5% A16 VSS_ANA VSS_ANA V16
A18 VSS_ANA VSS_ANA V20
A20 VSS_ANA VSS_ANA W5
VSS_ANA VSS_ANA
1 1
A22 W6
+3VALW B6 VSS_ANA VSS_ANA W8
B8 VSS_ANA VSS_ANA W9
@ B10 VSS_ANA VSS_ANA W20
PJ1508 B12 VSS_ANA VSS_ANA W22
B14 VSS_ANA VSS_ANA W23
Default short. B16 VSS_ANA VSS_ANA Y9
B18 VSS_ANA VSS_ANA Y13
B20 VSS_ANA VSS_ANA Y20
B22 VSS_ANA VSS_ANA AA22
D8 VSS_ANA VSS_ANA AA23
D9 VSS_ANA VSS_ANA AB6
D11 VSS_ANA VSS_ANA AB8
D12 VSS_ANA VSS_ANA AB10
VCC3V3_S0_SYS VCC3V3_S0 D13 VSS_ANA VSS_ANA AB12
D15 VSS_ANA VSS_ANA AB14
D16 VSS_ANA VSS_ANA AB16
VSS_ANA VSS_ANA

GND
D18 AB18
L2001 1 2 LQM18PN1R0M_2P E8 VSS_ANA VSS_ANA AB20
E9 VSS_ANA VSS_ANA AB22
ADD 2* 47uf cap E11 VSS_ANA VSS_ANA AC6
E15 VSS_ANA VSS_ANA AC8
1 1 1 VSS_ANA VSS_ANA
C2689 C2690 C2151 E16 AC10
E22 VSS_ANA VSS_ANA AC12
47U_0603_4V

47U_0603_4V

E23 VSS_ANA VSS_ANA AC14


1U_0201_10V6K

2 2 2 F9 VSS_ANA VSS_ANA AC16


F16 VSS_ANA VSS_ANA AC18
F20 VSS_ANA VSS_ANA AC20
G22 VSS_ANA VSS_ANA AC22
G23 VSS_ANA VSS_ANA D5
H1 VSS_ANA VSS E4
H2 VSS_ANA VSS E5
H12 VSS_ANA VSS E6
H13 VSS_ANA VSS F5
H15 VSS_ANA VSS F6
H16 VSS_ANA VSS H5
H20 VSS_ANA VSS H8
J5 VSS_ANA VSS J8
J18 VSS_ANA VSS J12
J19 VSS_ANA VSS J13
J20 VSS_ANA VSS J15
J22 VSS_ANA VSS L13
J23 VSS_ANA VSS M11
+3VALW VCC3V3_SX_SYS_AR K1 VSS_ANA VSS M12
K2 VSS_ANA VSS N8
L5 VSS_ANA VSS N9
R2056 1 2 0_0603_5% L20 VSS_ANA VSS N11
L22 VSS_ANA VSS N12
L23 VSS_ANA VSS N13
M1 VSS_ANA VSS T6
M2 VSS_ANA VSS T8
M5 VSS_ANA VSS T9
M19 VSS_ANA VSS T13
M20 VSS_ANA VSS T15
N5 VSS_ANA VSS T16
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA

N20 VSS_ANA VSS T18


N22 VSS_ANA VSS AB1
N23 VSS_ANA VSS AC2
VSS_ANA VSS
U2005B
P1
P2
R5
R18
R19
R20
R22
R23
T1
T2
T5
T20
U22
U23

AR_4C_C0 STEP LENOVO.CRDN


Y
SA00007YH00 Title
TBT-AR POWER
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 39 of 99
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
1
VCC20V0_SYS

20V 3A

C2119
1
4.7U_0603_25V6M

3.3A 2

VCC5V0_SYS

3A
TBTA_VBUS

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V
1

1
C2120

C2113

C2114

C2115

C2116
+

150U_B2_6.3VM_R35M
2

2
TBTA_LDO_BMC 2
VCC1V8D_TBTA_LDO
VCC1V8A_TBTA_LDO 1
C2136
JTYPC1
1U_0201_10V6K C2117

1U_0201_10V6K C2118

1 1
Foxconn_UT11111-13401-7H

1U_0201_10V6K C2121
1 2

1
2
3
4
4.7U_0603_25V6M
Y
@ D2004 A1 B12

CGND1
CGND2
CGND3
CGND4
2 2 GND1 GND2
AZ4024-01F_0402
2 A2 B11

P/N SWAP
38 TBTA_TX0_N
38 TBTA_TX0_P
A3 TX0_P
TX0_N
RX0_P
RX0_N
B10 TBTA_RX0_N 38
TBTA_RX0_P 38
P/N SWAP

2
VCC3V3_SX_SYS
C2122 2 1 0.47U_0402_25V6 A4 B9 C2123 1 2 0.47U_0402_25V6
VBUS1 VBUS2
TBTA_CC1 A5 B8 TBTA_SBU2
CC1 SBU2
1
C2124 TBTA_USB2_P_T A6 B7 TBTA_USB2_N_B
TBTA_USB2_N_T A7 USB2_P_T USB2_N_B B6 TBTA_USB2_P_B
USB2_N_T USB2_P_B

H10

C11
D11
A11
B11

B10

A10
10U_0402_6.3V6M

H1

B1

K1

A2

E1

A6
A7
A8
B7

B9

A9
2 TBTA_SBU1 A8 B5 TBTA_CC2
F1 SBU1 CC2

VIN_3V3

VDDIO

LDO_1V8A

LDO_1V8D

LDO_BMC

PP_CABLE

PP_5V0
PP_5V0
PP_5V0
PP_5V0

PP_HV
PP_HV
PP_HV
PP_HV

SENSEP

SENSEN

HV_GATE1

HV_GATE2
I2C_ADDR C2125 2 1 0.47U_0402_25V6 A9 B4 C2126 2 1 0.47U_0402_25V6
D1 VBUS3 VBUS4
38 TBT_I2C_SDA D2 I2C_SDA1 A10 B3
38 TBT_I2C_SCL I2C_SCL1 VCC3V3_TBT_SX VCC3V3_FLASH 38 TBTA_RX1_N RX1_N TX1_N TBTA_TX1_N 38

CGND10
C1 A11 B2

CGND5
CGND6
CGND7
CGND8
CGND9
38 TBTA_I2C_INT I2C_IRQ1Z 38 TBTA_RX1_P RX1_P TX1_P TBTA_TX1_P 38
R2058 1 2 0_0402_5% A5 A12 B1
26,51,73,74 EC_SMB_DAT0 I2C_SDA2 GND3 GND4
R2059 1 2 0_0402_5% B5 3A 3A

1U_0201_10V6K C2128

1U_0201_10V6K C2127
26,51,73,74 EC_SMB_CLK0 I2C_SCL2 1 1
B6 H11
I2C_IRQ2Z VBUS

5
6
7
8
9
10
J10
R2060 1 2 0_0402_5% B2 VBUS J11
C2 GPIO_0 VBUS K11 2 2
VCC3V3_SX_SYS R2062 1 2 0_0402_5% D10 GPIO_1 VBUS
R2084 1 2 0_0402_5% G11 GPIO_2 H2
R2063 10_0402_5%2 C10 GPIO_3 VOUT_3V3
38 TBTA_HPD GPIO_4
E10
GPIO_5
2

R2085 1 2 0_0402_5% G10 G1


R2091 R2086 1 2 0_0402_5% D7 GPIO_6 LDO_3V3
H6 GPIO_7
4.02K_0402_1% GPIO_8
Competible with TPS65982D. K6 TBTA_USB2_P_T
R2287 1 2 0_0402_5% A3 C_USB_TP L6 TBTA_USB2_N_T
38 TBT_EE_CLK SPI_CLK C_USB_TN
1

R2288 1 2 0_0402_5% B4
SWD_DAT 38 TBT_EE_DI R2289 1 2 0_0402_5% A4 SPI_MOSI
38 TBT_EE_DO R2290 1 2 0_0402_5% B3 SPI_MISO
SWD_CLK 38 TBT_EE_CS_N SPI_SC_Z
L5 TBTA_TX0_N TBTA_USB2_P_T TBTA_USB2_P_B
38 TBTA_USB2_D_P USB_RP_P TBTA_USB2_P_B TBTA_TX0_P TBTA_USB2_N_T TBTA_USB2_N_B
K5 K7
38 TBTA_USB2_D_N USB_RP_N C_USB_BP
1

L7 TBTA_USB2_N_B
R2092 E2 C_USB_BN
UART_TX

2
100K_0402_5% 1 R2064 2 100K_0402_5% TBTA_UART_RX F2
UART_RX D60 D61 D2005 D2006

2
SWD_DAT F4 L9 TBTA_CC1 C2130 1 2 220P_0201_25V7-K AZ5213_0402-3 AZ5213_0402-3
SWD_DAT C_CC1
2

SWD_CLK G4 L10 TBTA_CC2 C2129 1 2 220P_0201_25V7-K


SWD_CLK C_CC2
1 1

PESD5V0H1BSF SOD962

PESD5V0H1BSF SOD962
1 R2065 2 100K_0402_5% TBTA_MRESET_R E11 K9

3
M_RESET RPD_G1 K10
RPD_G2

3
VCC3V3_TBT_SX VCC3V3_FLASH
1

E4 R2068 1 2 10K_0402_5%
R2069 R2087 1 2 0_0402_5% L4 DEBUG_CTL1 D5 R2070 1 2 10K_0402_5%
100K_0402_5% 38 TBTA_LSTX R2088 1 2 0_0402_5% K4 LSX_R2P DEBUG_CTL2
38 TBTA_LSRX LSX_P2R
1 R2071 2 100K_0402_5% TBTA_DEBUG3 L3 TBTA_RX0_P
DEBUG3
2

1 R2072 2 100K_0402_5% TBTA_DEBUG4 K3 K8 R2089 1 2 0_0402_5% TBTA_SBU1 TBTA_RX0_N


DEBUG4 C_SBU1
1 R2075 2 100K_0402_5% TBTA_DEBUG1 L2 L8 R2090 2 1 0_0402_5% TBTA_SBU2
DEBUG1 C_SBU2

2
1 R2076 2 100K_0402_5% TBTA_DEBUG2 K2
DEBUG2 D62 D63 TBTA_SBU1

2
J1
38 TBTA_DPSRC_AUX_P AUX_P TBTA_CC1
J2 F11
38 TBTA_DPSRC_AUX_N AUX_N RESETZ TBT_RESET_N 38

PESD5V0H1BSF SOD962

PESD5V0H1BSF SOD962

2
VCC1V8D_TBTA_LDO R2077 1 @ 2 0_0402_5% F10 H7 C2131 2 1 0.22U_0201_6.3V
BUSPOWERZ SS D59 D58

2
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
2

TBTA_ROSC G2

1
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9

R_OSC
1

L11

AZ5425-01F.R7GR

AZ5425-01F.R7GR
R2078
NC0

1
1

R2080 0_0402_5%
100K_0402_5% R2079 U2007
A1
B8
D6
D8
E5
E6
E7
E8
F5
F6
F7
F8
G5
G6
G7
G8
H4
H5
H8
L1

VCC3V3_FLASH 15K_0402_0.1% TPS65982


1

1
2

1
TBTA_TX1_N
TBTA_TX1_P

2
D64 D65 TBTA_SBU2

2
TBTA_CC2

PESD5V0H1BSF SOD962

PESD5V0H1BSF SOD962

2
D56 D57

2
1

AZ5425-01F.R7GR

AZ5425-01F.R7GR
1

1
1

1
VCC3V3_SX_SYS TBTA_RX1_P
TBTA_RX1_N
PLT_RST_N R2096 1 2 0_0402_5%
+3VALW VCC3V3_SX_SYS U2011

2
R2097 1 @ 2 0_0402_5%
23,38 TBT_FORCE_PWR 1 6 D66 D67

2
2 NC1 Vcc 5
R2098 1 2 0_0402_5% 3 A NC2 4 R2093 1 @ 2 0_0402_5% TBTA_MRESET_R
GND Y

PESD5V0H1BSF SOD962

PESD5V0H1BSF SOD962
1

C2139 @ 74AUP1G04FW4-7_DFN1010-6_1X1

1
0.47U_0402_25V6
2

1
+5VALW VCC5V0_SYS

@ LENOVO.CRDN
PJ12
Title
TBT TPS65982/TYPEC
Size Document Number
Custom Rev V0.3
Skylake-H

WWW.AliSaler.Com
PLT_RST_N R2099 1 @ 2 0_0402_5% TBTA_MRESET_R Date: Thursday, May 26, 2016 Sheet 40 of 99
17,26,27,38,42,43,49,50,63 PLT_RST_N "PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
R2103 1 2 0_0402_5% or disclosed to others or used for any purpose other than that for which it was
26 AR_HOLD_RST_N obtained without the expressed written consent of LENOVO PND."
5 4 3 2 1

2.0A
+5V_USB1

R497 1 2 0_0402_5%
JUSB1
CM13 @
38 TBTB_RX0_P 3 4 TBTB_RX0_P_R TBTB_TX0_P_R 9
+5V_USB1 3 4 1 SSTX+
TBTB_TX0_N_R 8 VBUS
+5VALW 2 1 TBTB_RX0_N_R TBTB_USB2_D_N_R 2 SSTX-
38 TBTB_RX0_N 2 1 D-
4
EXC24CH900U TBTB_USB2_D_P_R 3 GND 10
1 D+ GND
1 1 TBTB_RX0_P_R 6 11
+ C1335 C495 R500 1 2 0_0402_5% 7 SSRX+ GND 12
C494 TBTB_RX0_N_R 5 GND GND 13
D SSRX- GND D

220U_B2_6.3VM_R35M

0.1U_0402_25V6
0.1U_0402_25V6
2 2 2
Foxconn_UAA111C-441R1-7H
U18 R499 1 @ 2 0_0402_5%
6 1
IN OUT CM14
5 2 C648 1 2 USB3_TX_DP6_C 3 4 TBTB_TX0_P_R
GND ILIM 38 TBTB_TX0_P 3 4
R496 1 2 0_0402_5% 4 3 0.1U_0402_16V7K
26,48,49,76,90,92 SUSON EN FAULT# USB_OC1_N 18 C621 1 2 USB3_TX_DN6_C 2 1 TBTB_TX0_N_R
38 TBTB_TX0_N 2 1
7
GND_PAD

1
0.1U_0402_16V7K EXC24CH500U
AP2553FDC-7_U-DFN2020-6_2X2 R495
10.7K_0402_1% R501 1 @ 2 0_0402_5%

2
TBTB_USB2_D_N_R
R519 1 @ 2 0_0402_5%
TBTB_USB2_D_P_R
EXC24CH900U
D54

2
2 1 TBTB_USB2_D_N_R
38 TBTB_USB2_D_N 2 1 TBTB_TX0_P_R 1 D33

2
TBTB_TX0_N_R 2 D1+ 10
D1- NC4 AZ5213_0402-3
3 4 TBTB_USB2_D_P_R 3 9
38 TBTB_USB2_D_P 3 4 GND1 NC3
8 7
CM15 TBTB_RX0_P_R 4 GND2 NC2 6
TBTB_RX0_N_R 5 D2+ NC1
R522 1 @ 2 0_0402_5% D2-

3
AZ1043-04F_DAQ10

3
C C

2.0A
+5V_USB2

+5VALW_USB_CHG +5V_USB2

R528 1 2 0_0402_5% JUSB2

CM10 @ USB3_TX_DP3_R 9
3 4 USB3_RX_DP3_R 1 SSTX+
1 21 USB3_RX_DP3 3 4 VBUS
1 USB3_TX_DN3_R 8
+ C624 C625 USB2_CHG_PN_R 2 SSTX-
2 1 USB3_RX_DN3_R 4 D-
1 1 21 USB3_RX_DN3 2 1 GND
USB2_CHG_PP_R 3 10
220U_B2_6.3VM_R35M

0.1U_0402_25V6

C600
C602 2 2 EXC24CH900U USB3_RX_DP3_R 6 D+ GND 11
0.1U_0402_25V6 10U_0402_6.3V6M 7 SSRX+ GND 12
2 2 R530 1 2 0_0402_5% USB3_RX_DN3_R 5 GND GND 13
SSRX- GND

U21 Foxconn_UEA1111-N40AM2-7H
1 12
IN OUT 10 USB2_CHG_PP R529 1 @ 2 0_0402_5%
3 DP_IN 11 USB2_CHG_PN
18 USB2_DP2 DP_OUT DM_IN
18 USB2_DN2 2 14 CM11
DM_OUT GND C500 1 2 USB3_TX_DP3_C 3 4 USB3_TX_DP3_R
21 USB3_TX_DP3 3 4
9 USB_CHG_STATUS_N 0.1U_0402_16V7K
STATUS# USB_CHG_STATUS_N 26
21 USB3_TX_DN3 C504 1 2 USB3_TX_DN3_C 2 1 USB3_TX_DN3_R
4 USB_CHG_ILIM_SEL 2 1
13 ILIM_SEL 0.1U_0402_16V7K EXC24CH500U
18 USB_OC2_N R498 1 2 0_0402_5% 5 FAULT#
26 USB_CHG_EN EN 15 USB_CHG_ILIM_LO R531 1 @ 2 0_0402_5%
6 ILIM_LO 16 USB_CHG_ILIM_HI USB2_CHG_PN_R
26 USB_CHG_CLT1 CLT1 ILIM_HI
26 USB_CHG_CLT2 7
8 CLT2 17 USB2_CHG_PP_R
26 USB_CHG_CLT3 CLT3 GND_Pad
B D53 B

2
R532 1 @ 2 0_0402_5%
NCT3955Y_QFN16_3X3 USB3_TX_DP3_R 1 D49

2
EXC24CH900U USB3_TX_DN3_R 2 D1+ 10
D1- NC4 AZ5213_0402-3
TPS2546RTER PN:SA00005TD00 USB2_CHG_PN 2 1 USB2_CHG_PN_R 3 9
SLG55546VTR PN:SA00007G300 2 1 8 GND1 NC3 7
NCT3955Y PN:SA00007G200 USB3_RX_DP3_R 4 GND2 NC2 6
USB2_CHG_PP USB2_CHG_PP_R USB3_RX_DN3_R D2+ NC1
CAD Note:USB_CHG_CTL* 3
3 4
4 5
D2-

3
CLT1 CLT2 CLT3 ILIM_SEL CM12 AZ1043-04F_DAQ10
0 1 0 1 -- SDP

3
0 0 1 1-- DCP/Auto R533 1 @ 2 0_0402_5%
+5VALW_USB_CHG

CAD Note:
ILIM_SEL=Vin,ILIM_HI=22.6KR: USB_CHG_ILIM_SEL R503 1 2 100K_0402_5%
output current limit=2.3A
CAD Note:For Power consumption
Support Mouse/Keyboard wake up. USB_CHG_ILIM_LO R504 1 2 80.6K_0402_1%
Support Power Wake
USB_CHG_ILIM_HI R505 1 2 22.6K_0402_1%
+5VLDO +5VALW_USB_CHG +5VALW

@
R376 1 2 0_0603_5% R378 1 2 0_0603_5%

Q29 3 1 LP2301ALT1G_SOT23-3
S

D
1
+5VLDO C137
G
2

4.7U_0603_25V6M
A R377 1 2 100K_0402_5% 2 A

6 LENOVO.CRDN
R791 1 @ 2 0_0402_5% Title
75 5VALW_PG
Q52A 2 HDMI CONN,
R152 1 2 10K_0402_5% 2 C406
26,75,77,92 EC_ON
AO5804EL_SC89-6 @ 3 Size Document Number
0.1U_0402_25V6 Q52B C Rev V0.3
2
C407 1 AO5804EL_SC89-6
Skylake-H
1 Date: Thursday, May 26, 2016 Sheet 41 of 99
0.1U_0402_25V6 5 "PROPERTY NOTE: this document contains information confidential and
1 property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."
4

5 4 3 2 1
5 4 3 2 1

+3V +3V_WLAN

@
PJ8

D D

+3V_WLAN
BRD Note:
Placed close to pin2,4

2
C604 C603 C549 C551 C552

10U_0603_10V

10U_0603_10V

0.01U_0402_25V7K

0.01U_0402_25V7K
0.1U_0402_25V6
2

1
1

+3V_WLAN BRD Note:


Placed close to pin72,74
+3V_WLAN

JWLAN1
2

2
1 2 C607 C608 C550 C605 C606
3 GND1 3.3AUX1 4
18 USB2_DP5 USB_D+ 3.3AUX2
5 6

10U_0603_10V

10U_0603_10V

0.01U_0402_25V7K

0.01U_0402_25V7K
0.1U_0402_25V6
18 USB2_DN5 USB_D- LED1#

1
7 8 1
9 GND2 PCM_CLK 10
11 SDIO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_IN 14
15 SDIO_DAT0 PCM_OUT 16
17 SDIO_DAT1 LED2# 18
19 SDIO_DAT2 GND11 20
C C
21 SDIO_DAT3 UART_WAKE 22
23 SDIO_WAKE UART_RX
SDIO_RESET

KEY E
25 PIN24~PIN31 NC PIN 24
27 26
29 28
31 30

33 32
35 GND3 UART_TX 34
18 PCIE_WLAN_TX_C_DP PETP0 UART_CTS
37 36
18 PCIE_WLAN_TX_C_DN PETN0 UART_RTS
39 38
41 GND4 RSRVD10 40
18 PCIE_WLAN_RX_DP 43 PERP0 RSRVD11 42
18 PCIE_WLAN_RX_DN PERN0 RSRVD9
45
GND5 COEX3
44 CAD Note:
47 46
22 CK_WLAN_P
49 REFCLKP0 COEX2 48
WLAN module SUSCLK NC
22 CK_WLAN_N REFCLKN0 COEX1 WLAN_SUSCLK
51 50 R456 1 @ 2 0_0402_5%
GND6 SUSCLK SUSCLK 19
R457 1 2 0_0402_5% WLAN_CK_REQ_N 53 52 WLAN_RST_N R458 1 2 0_0402_5%
22,42 CK_REQ_WLAN_N CLKEQ0# PERSTO# PLT_RST_N 17,26,27,38,40,43,49,50,63
R459 1 @ 2 0_0402_5% WLAN_WAKE_N 55 54 R484 1 2 0_0402_5% RF_KILL_BT_N 17
19,38 PCIE_WAKE_N 57 PEWAKE0# RSRVD/W_DISABLE2# 56 R517 1 2 0_0402_5%
GND7 W_DISABLE1# RF_KILL_WIFI_N 17

59 58
61 RSRVD/PETP1 I2C_DATA 60
63 RSRVD/PETN1 I2C_CLK 62
65 GND8 ALERT 64
67 RSRVD/PERP1 RSRVD6 66
69 RERVD/PERN1 RSRVD7 68 +3V_WLAN
71 GND9 RSRVD8 70
73 RSRVD1 RSRVD12 72
75 RSRVD2 3.3VAUX3 74
GND10 3.3VAUX4
77 76
B GND15 GND14 B

Bellwether_80152-3221

Q8A @ AO5804EL_SC89-6

6 1 WLAN_CK_REQ_N
22,42 CK_REQ_WLAN_N

+3V_WLAN
2
3
2

Q8B
R460
5 @ @
100K_0402_5%
1

AO5804EL_SC89-6
4

A A

LENOVO.CRDN
Title
NGFF WLAN
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 42 of 99
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

2A
+3V +3V_SSD1

@
PJ10
+3V_SSD1

JSSD1 2 2

2
C609 C610 C611 C612 C577 C576 C574 C575
1 2
3 CONFIG_3 3V3 4

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

0.01U_0402_25V7K

0.01U_0402_25V7K
0.1U_0402_25V6

0.1U_0402_25V6
GND 3V3

1
PCIE16_SSD1_RX_DN3 5 6 1 1
20 PCIE16_SSD1_RX_DN3 PCIE16_SSD1_RX_DP3 PERn3 FULL_CARD_POWER_OFF
7 8
20 PCIE16_SSD1_RX_DP3 PERp3 W_DISABEL SSD1_DAS
9 10 1 TP99
D
C195 2 1 0.22U_0402_10V6K PCIE16_SSD1_TX_C_DN3 11 GND GPIO9/DAS/DSS 12 D
20 PCIE16_SSD1_TX_DN3 PCIE16_SSD1_TX_C_DP3 PETn3 3V3
C196 2 1 0.22U_0402_10V6K 13 14
20 PCIE16_SSD1_TX_DP3 PETp3 3V3
15 16
PCIE15_SSD1_RX_DN2 17 GND 3V3 18
20 PCIE15_SSD1_RX_DN2 PCIE15_SSD1_RX_DP2 PERn2 3V3
19 20
20 PCIE15_SSD1_RX_DP2 PERp2 GPIO_5
21 22
C193 2 1 0.22U_0402_10V6K PCIE15_SSD1_TX_C_DN2 23 GND GPIO_6 24
20 PCIE15_SSD1_TX_DN2 PCIE15_SSD1_TX_C_DP2 PETn2 GPIO_7
C194 2 1 0.22U_0402_10V6K 25 26
20 PCIE15_SSD1_TX_DP2 PETp2 GPIO_10
27 28
PCIE14_SSD1_RX_DN1 29 GND GPIO_8 30
20 PCIE14_SSD1_RX_DN1 PCIE14_SSD1_RX_DP1 PERN1 UIM_RESET
31 32
20 PCIE14_SSD1_RX_DP1 PERP1 UIM_CLK
33 34
C191 2 1 0.22U_0402_10V6K PCIE14_SSD1_TX_C_DN1 35 GND UIM_DAT 36
20 PCIE14_SSD1_TX_DN1 PCIE14_SSD1_TX_C_DP1 PETN1 UIM_PWR
C192 2 1 0.22U_0402_10V6K 37 38
20 PCIE14_SSD1_TX_DP1 PETP1 DEVSLP
39 40
PCIE13_SSD1_RX_DN0 41 GND GPIO_0 42 R512 1 2 0_0402_5%
20 PCIE13_SSD1_RX_DN0 PCIE13_SSD1_RX_DP0 PERN0/SATA_B+ GPIO_1
43 44
20 PCIE13_SSD1_RX_DP0 PERP0/SATA_B- GPIO_2
45 46
C189 2 1 0.22U_0402_10V6K PCIE13_SSD1_TX_C_DN0 47 GND GPIO_3 48
20 PCIE13_SSD1_TX_DN0 PCIE13_SSD1_TX_C_DP0 PETN0/SATA_A- GPIO_4 PCIE_SSD1_RST_N
C190 2 1 0.22U_0402_10V6K 49 50 R478 1 2 0_0402_5%
20 PCIE13_SSD1_TX_DP0 PETP0/SATA_A+ PERST_N PCIE_SSD1_CLKREQ_N PLT_RST_N 17,26,27,38,40,42,49,50,63
51 52 Q9A @ AO5804EL_SC89-6
CK_PCIE_SSD1_N 53 GND CLKREQ_N 54
22 CK_PCIE_SSD1_N CK_PCIE_SSD1_P REFCLKN PEWAKE_N PCIE_SSD1_CLKREQ_N
55 56 1 6
22 CK_PCIE_SSD1_P REFCLKP NC_56 CK_REQ_SSD1_N 22
57 58
GND NC_58

2
@
+3V_SSD1 R479
2
10K_0402_5%
KEY M

1
2
PIN59~PIN66 NC PIN
R480
@
100K_0402_5%

1
67
69 RESET_N 68
71 PEDET_PCIE/GND_SATA SSCLK 70
C C
73 GND 3V3 72
75 GND 3V3 74
USB3.0IND/GND_OTHER 3V3
77 76
GND GND

ARGOSY_NASM0-S6701-TP50

2A
+3V_SSD2 +3V +3V_SSD2

@
JSSD2 PJ11
1 2
3 CONFIG_3 3V3 4
PCIE12_SSD2_RX_DN3 5 GND 3V3 6
20 PCIE12_SSD2_RX_DN3 PERn3 FULL_CARD_POWER_OFF 2 2

2
PCIE12_SSD2_RX_DP3 7 8 C613 C614 C615 C616 C581 C580 C579 C578
20 PCIE12_SSD2_RX_DP3 PERp3 W_DISABEL SSD2_DAS_DSS
9 10 1 TP100
C203 2 1 0.22U_0402_10V6K PCIE12_SSD2_TX_C_DN3 11 GND GPIO9/DAS/DSS 12

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

0.01U_0402_25V7K

0.01U_0402_25V7K
0.1U_0402_25V6

0.1U_0402_25V6
20 PCIE12_SSD2_TX_DN3 PETn3 3V3

1
C204 2 1 0.22U_0402_10V6K PCIE12_SSD2_TX_C_DP3 13 14 1 1
20 PCIE12_SSD2_TX_DP3 PETp3 3V3
15 16
PCIE11_SSD2_RX_DN2 17 GND 3V3 18
20 PCIE11_SSD2_RX_DN2 PCIE11_SSD2_RX_DP2 PERn2 3V3
19 20
20 PCIE11_SSD2_RX_DP2 PERp2 GPIO_5
21 22
C201 2 1 0.22U_0402_10V6K PCIE11_SSD2_TX_C_DN2 23 GND GPIO_6 24
20 PCIE11_SSD2_TX_DN2 PCIE11_SSD2_TX_C_DP2 PETn2 GPIO_7
C202 2 1 0.22U_0402_10V6K 25 26
20 PCIE11_SSD2_TX_DP2 PETp2 GPIO_10
27 28
PCIE10_SSD2_RX_DN1 29 GND GPIO_8 30
20 PCIE10_SSD2_RX_DN1 PCIE10_SSD2_RX_DP1 PERN1 UIM_RESET
31 32
20 PCIE10_SSD2_RX_DP1 PERP1 UIM_CLK
33 34
B
C199 2 1 0.22U_0402_10V6K PCIE10_SSD2_TX_C_DN1 35 GND UIM_DAT 36 B
20 PCIE10_SSD2_TX_DN1 PCIE10_SSD2_TX_C_DP1 PETN1 UIM_PWR
C200 2 1 0.22U_0402_10V6K 37 38
20 PCIE10_SSD2_TX_DP1 PETP1 DEVSLP
39 40
R481 1 2 0_0402_5% PCIE9_SSD2_RX_R_DP0 41 GND GPIO_0 42
20 PCIE9_SSD2_RX_DP0 PCIE9_SSD2_RX_R_DN0 PERN0/SATA_B+ GPIO_1
R482 1 2 0_0402_5% 43 44
20 PCIE9_SSD2_RX_DN0 PERP0/SATA_B- GPIO_2
45 46 R508 1 2 0_0402_5%
C197 2 1 0.22U_0402_10V6K PCIE9_SSD2_TX_C_DN0 47 GND GPIO_3 48
20 PCIE9_SSD2_TX_DN0 PCIE9_SSD2_TX_C_DP0 PETN0/SATA_A- GPIO_4 PCIE_SSD2_RST_N PLT_RST_N
C198 2 1 0.22U_0402_10V6K 49 50 R483 1 2 0_0402_5%
20 PCIE9_SSD2_TX_DP0 PETP0/SATA_A+ PERST_N PCIE_SSD2_CLKREQ_N
51 52
CK_PCIE_SSD2_N 53 GND CLKREQ_N 54
22 CK_PCIE_SSD2_N CK_PCIE_SSD2_P REFCLKN PEWAKE_N
55 56 Q9B @ AO5804EL_SC89-6
22 CK_PCIE_SSD2_P REFCLKP NC_56
57 58
GND NC_58 PCIE_SSD2_CLKREQ_N 4 3
CK_REQ_SSD2_N 22

2
CAD Note: +3V_SSD2
@
R485
PCIE port 9 is multiplexed with SATA port 0; KEY M 5
10K_0402_5%
SSD2 can be reworked to SATA SSD for debug PIN59~PIN66 NC PIN

1
2
CAD Note:
R486
PCIE polarity inversion @
67 100K_0402_5%
69 RESET_N 68
PEDET_PCIE/GND_SATA SSCLK

1
71 70
73 GND 3V3 72
75 GND 3V3 74
USB3.0IND/GND_OTHER 3V3
77 76
GND GND

ARGOSY_NASM0-S6701-TP50

A A

LENOVO.CRDN
Title
NGFF SSD
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 43 of 99
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

CAD Note:PS8527A VDD


1.2V/1.35V/1.5V
+5V_HDD
0.142A +5V

+3V +3V_SATA @
PJ9
R461 1 2 0_0402_5%
/RE_SATA
1 2 2 1 1 2

2
C553 C554 C555 C556 C557 C558 C559 C560 C561 C562 C563
/RE_SATA @ @ @

1U_0402_10V6K
/RE_SATA

0.1U_0402_25V6
/RE_SATA

0.1U_0402_25V6
/RE_SATA

/RE_SATA

10U_0603_10V

10U_0603_10V

1U_0402_10V6K

1U_0402_10V6K

0.1U_0402_25V6
10U_0603_10V

0.01U_0402_25V7K

0.1U_0402_16V7K
2

1
D 2 1 1 2 2 1 D

+3V_SATA +3V_SATA
U14
/RE_SATA
10 7 R462 2 1 4.7K_0402_5%
20 VDD EN
@/RE_SATA VDD @/RE_SATA
C565 1 2 0.01U_0402_25V7K SATA_TX_C_DP0 1 15 SATA_TX__R_P0 1 R2112 2 0_0402_5% SATA_TX_P0
20 SATA_TX_DP0 A_INp A_OUTp
C566 1 2 0.01U_0402_25V7K SATA_TX_C_DN0 2 14 SATA_TX__R_N0 1 2 0_0402_5% SATA_TX_N0
20 SATA_TX_DN0 A_INn A_OUTn
@/RE_SATA@/RE_SATA R2113 @/RE_SATA
C567 1 2 0.01U_0402_25V7K SATA_RX_C_DN0 4 12 SATA_RX__R_N0 1 R2234 @/RE_SATA
2 0_0402_5% SATA_RX_N0
20 SATA_RX_DN0 B_OUTn B_INn
C571 1 2 0.01U_0402_25V7K SATA_RX_C_DP0 5 11 SATA_RX__R_P0 1 2 0_0402_5% SATA_RX_P0 CAD Note:
20 SATA_RX_DP0 B_OUTp B_INp R2115 @/RE_SATA
@/RE_SATA SATA_B_DE 8
SATA_REXT=7.5KR:
SATA_A_DE 9 B_DE 6 SATA_REXT R463 1 /RE_SATA
2 7.5K_0402_1% Vtx_diff=700 mV
SATA_B_EQ2 13 A_DE REXT
SATA_A_EQ1 B_EQ2
17
A_EQ1 DEW
16 R464 1 2 4.7K_0402_5% CAD Note:SATA_DEW
SATA_A_EQ2 18 3
SATA_B_EQ1 19 A_EQ2 GND 21 /RE_SATA
L:For SATA Gen3
B_EQ1 EPAD H:For SATA Gen2
C C
PS8527CTQFN20GTR2-A2
/RE_SATA

SATA_TX_DP0 R2229 1 /SATA 2 0_0402_5% R2232 1 /SATA 2 0_0402_5% SATA_TX_P0


SATA_TX_DN0 R2106 1 /SATA 2 0_0402_5% R2107 1 /SATA 2 0_0402_5% SATA_TX_N0

SATA_RX_DN0 R2233 1 /SATA 2 0_0402_5% R2230 1 /SATA 2 0_0402_5% SATA_RX_N0


SATA_RX_DP0 R2110 1 /SATA 2 0_0402_5% R2231 1 /SATA 2 0_0402_5% SATA_RX_P0

JHDD1
B B
+3V_SATA
SATA_TX_P0 C564 1 2 0.01U_0402_25V7K SATA_TX_C_P0 1
SATA_TX_N0 C568 1 2 0.01U_0402_25V7K SATA_TX_C_N0 2 1
2
CAD Note:SATA_x_DE 3
3
SATA_RX_N0 C569 1 2 0.01U_0402_25V7K SATA_RX_C_N0 4
De-emphasis level setting for channel x(x=A,B), SATA_RX_P0 C570 1 2 0.01U_0402_25V7K SATA_RX_C_P0 5 4
internally tied to VDD/2 5
2

R465 R466 R467 R468 R469 R470 6


6
[A_DE,B_DE]=M,L 7
7
8
4.7K_0402_5%
@/RE_SATA

4.7K_0402_5%
@/RE_SATA

4.7K_0402_5%
/RE_SATA

4.7K_0402_5%
/RE_SATA

4.7K_0402_5%
@/RE_SATA

4.7K_0402_5%
@/RE_SATA

M:-3.5dB +5V_HDD
9 8
L: 0dB 10 9
10
1

H: -6dB

SATA_B_DE 11
12 GND
SATA_A_DE GND

SATA_B_EQ2 ACES_50208-01001-001

SATA_B_EQ1
CAD Note:SATA_x_EQ
SATA_A_EQ2
Equalization level setting for channel x(x=A,B),
internally tied to VDD/2 SATA_A_EQ1
[x_EQ2,x_EQ1]=
L/M: for channel loss up to 2.4dB
2

L/L: for channel loss up to 7.4dB(CH A)


2

R471 R472 R473 R474 R475 R476


L/H: for channel loss up to 14.4dB
4.7K_0402_5%

4.7K_0402_5%

@/RE_SATA
4.7K_0402_5%

@/RE_SATA
4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%
/RE_SATA

M/M: for channel loss up to 12.2dB


/RE_SATA

@/RE_SATA

/RE_SATA

M/L: for channel loss up to 9.4dB


1

M/H: for channel loss up to 13.3dB


1

H/M: for channel loss up to 6.2dB


H/L: for channel loss up to 11.2dB
A H/H: for channel loss up to 5dB(CH B) A

LENOVO.CRDN
Title
SATA HDD
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 44 of 99
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

PROCHOT_N Logic
Theamal Sensor
+3V CAD Note: H_PROCHOT_N
Hi: Throttle OFF
+3V +3V_THERM U26 Low:Throttle ON
1 5
R553 1 2 0_0402_5% +3V_THERM U25 NC1 VCC
2 4 R580 2 1 100_0402_5%
26 VCOUT1_PROCHOT A Y H_PROCHOT_N 6
1 2 1 10
D VDD SMCLK EC_SMB_CLK1 19,26,63 D
1

1
C632 C630 C631 3 2
REMOTE1_P 2 9 GND

0.1U_0402_25V6
DP1 SMDATA EC_SMB_DAT1 19,26,63
R555 74AUP1G06GW_SO353-1 C633
10U_0603_10V

1U_0402_10V6K
2

2 1 REMOTE1_N 3 8 100K_0402_5% OD Inverter 47P_0402_25V8J


DN1 ALERT# 1

2
REMOTE2_P 4 7 R554 2 @ 1 10K_0402_5%
DP2 THERM# +3V_THERM
REMOTE2_N 5 6
DN2 GND

EMC1403-2-AIZL-TR_MSOP10 R556 2 1 100_0402_5%


83 CPU_VR_HOT_N

SMBus ADDRESS:0x 1001_101x


+3V

2
R827
@
100K_0402_5%
6

1
BRD Note:
Placed close to DDR
BRD Note: W/S=10:10
2
AO5804EL_SC89-6
Placed close to EMC1403 Q53A
REMOTE1_P REMOTE1_P 3 @
1

1
2 1 C
C635 2 Q10 AO5804EL_SC89-6
C634 @ B MMST3904-7-F_SOT323-3 R435 1 @ 2 0_0402_5% 5 Q53B
2200P_0402_50V7K 100P_0402_50V8J E 26,63,74 CHG_PROCHOT_N_R @

3
1 2
C REMOTE1_N REMOTE1_N C
4

BRD Note:
Placed close to FAN
REMOTE2_P REMOTE2_P
1

2 1 C
C638 2 Q24
C636 @ B MMST3904-7-F_SOT323-3
2200P_0402_50V7K 100P_0402_50V8J E
3

1 2
REMOTE2_N REMOTE2_N

IR Sensor
B

FAN CONN. +3V


B

+5V JFAN1

1
R559 1 2 0_0603_5% +5V_FAN1 1 6 +3V U24
2 1 6 R552
26 EC_FAN_TACH1 2 IR_I2C_CLK
3 A3 B3 100K_0402_5%
26 EC_FAN_PWM1 3 VDD SCL
1

C637 4 5 C3 IR_I2C_DATA
4 5 SDA

2
1

2
C2 SENSOR_INT_N
10U_0603_10V

C628 C629
DRDY#
2

DRAPHO_WS33041-S0351-HF A1 C1 +3V
A2 GND ADR0 B1

1U_0402_10V6K
+3VLP_EC_AVCC

0.01U_0402_25V7K
GND ADR1

1
2
BRD Note:

1
TMP006AIYZFR_DSBGA6P
NTC R placed under R557
SLAVE I2C ADDRESS:0x82 the CPU bottom side 16.5K_0402_1%

2
26 VCIN0_PT1

1
R558
+5V JFAN2 +3V U23
100K_0402_1%_NCP15WF104F03RC

R560 1 2 0_0603_5% +5V_FAN2 1 6 A3 B3 IR_I2C_CLK


1 6 VDD SCL

2
2 C3 IR_I2C_DATA
26 EC_FAN_TACH2 2 SDA
3 1
26 EC_FAN_PWM2 3
1

C639 4 5 C626 C627 C2 SENSOR_INT_N


4 5 A1 DRDY# C1 EC_AGND
A2 GND ADR0 B1
10U_0603_10V

1U_0402_10V6K

0.01U_0402_25V7K

GND ADR1
2

DRAPHO_WS33041-S0351-HF 2

A TMP006AIYZFR_DSBGA6P A

SLAVE I2C ADDRESS:0x80


LENOVO.CRDN
Title
Thermal/IR Sensor/FAN
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 45 of 99
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
R550 1 2 0_0402_5% IR_I2C_CLK or disclosed to others or used for any purpose other than that for which it was
26,28 EC_I2C_CLK5 IR_I2C_DATA obtained without the expressed written consent of LENOVO PND."
26,28 EC_I2C_DATA5 R551 1 2 0_0402_5%

5 4 3 2 1
5 4 3 2 1

D D

C C

RTC CONN. +RTC_VCC

JRTC1
1
2 1
3 2
BATT CR2032 3V 210MAH MB 5 W/C 4 GND
30MM GND
ACES_50271-00201-001

+3VLP

R429 1 2 1.8K_0402_1% D38 2 1

AC Charge LED SDM10U45LP-7_DFN1006-2-2

+3VLP

2
R430
45.3K_0402_1%

2
R569

1
B B
@
LD1 0_0402_5%
26 AC_CHARGED_LED_W R184 1 2 820_0402_5% 3 FSL-2408035WA-F8S2NBLX-CC CAD Note:+VCC_RTC

1
+RTC_VCC Q11
2
2
DMG1013UW_SOT323-3
Keep below +3.2V for PCH protection
@ +VCC_RTC
26 AC_CHARGING_LED_A R191 1 2 820_0402_5% 1
R570 2 1 1K_0402_5% D39 2 1 3 1
1 1
C168 C169 SDM10U45LP-7_DFN1006-2-2
@ @ 1
C640
2 2 R571 2 1 0_0402_5%
220P_0201_25V7-K

220P_0201_25V7-K

1U_0402_10V6K
2

Touch Pad +3V_TP


LID
+3V +3V_TP JTP1
R572 1 2 0_0402_5% TP_SMB_DAT 6 8 +3VALW
16,19,51 PCH_SMB_DAT TP_SMB_CLK 6 G2
R574 1 2 0_0402_5% R573 1 2 0_0402_5% 5 7
16,19,51 PCH_SMB_CLK 5 G1
4
R575 1 2 0_0402_5% TP_PS2_DAT_R 3 4 U51
A A
26 TP_PS2_DAT TP_PS2_CLK_R 3
1 2 R576 1 2 0_0402_5% 2 1
26 TP_PS2_CLK 2 VDD
C641 C642 1 2
1 2
1 1 31 LID_30_N OUT
C512 LENOVO.CRDN
2

2
4.7U_0402_6.3V6M

0.1U_0402_25V6

C643 C644 DRAPHO_FC1AF061-1201H


2 1 @ @ D40 D41 3 0.1U_0402_25V6 Title
2

GND 1
100P_0402_50V8J

100P_0402_50V8J

2 2
@ @ TP/FPR/RTC/LED CONN
AZ5425-01F.R7GR

AZ5425-01F.R7GR

HGDEPT001B Size Document Number


C Rev V0.3
Skylake-H
1

Date: Thursday, May 26, 2016 Sheet 46 of 99


"PROPERTY NOTE: this document contains information confidential and
1

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

+3VALW +3VALW_LC

L21 1 2 BLM15BD221SN1D_2P

+3V
1 2 2 2 2 2 2 2
C1367 C1369 C1359 C1361 C1362 C1363 C1364 C1365

1
R380 1 2 0_0402_5%

10U_0402_6.3V6M
@

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
2 1 1 1 1 1 1 1 +3VALW_LC +3VALW_LC
R930
D 0_0402_5% D

2
D10

K10
U19

D5

D4

K4

E4

E9

A1
J5

J4
VCC

Vstby0
VSTBY_FSPI

AVCC

VBAT
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
A10 LC_GPF2 R877 1 2 0_0402_5%
SMCLK0/GPF2 LC_GPF3 LED_KB_PWM5 48
K1 B10 R878 1 2 0_0402_5%
EIO0/LAD0/GPM0 SMDAT0/GPF3 LED_KB_PWM6 48
J2
J1 EIO1/LAD1/GPM1 B3
EIO2/LAD2/GPM2 SMCLK1/GPC1 EC_I2C_CLK3 26,32,34,79,80,87,90
H2 B2
EIO3/LAD3/GPM3 SMDAT1/GPC2 EC_I2C_DATA3 26,32,34,79,80,87,90
H1 +3VALW_LC
K2 ECS#/LFRAME#/GPM5 E8
M4 ESCK/LPCCLK/GPM4 CRX1/WUI17/SIN1/SMCLK3/GPH1/ID1 D7
48 LED_KB_PWM11 ERST#/LPCRST#/WUI4/GPD2 SM BUS CTX1/WUI18/SOUT1/GPH2/SMDAT3/ID2 LC_I2C_CLK
G2 R524 2 1 2.2K_0402_5%
ALERT#/SERIRQ/GPM6 LC_I2C_DATA
CAD Note: LPC L80HLAT/BAO/WUI24/SMCLK4/GPE0
N2
LED_KB_PWM17 48
R513 2 1 2.2K_0402_5%
F1 M3
FOR EC_I2C 26 LC_INT1_N
M1 GA20/GPB5 L80LLAT/WUI7/SMDAT4/GPE7 LED_KB_PWM24 48
48 LED_KB_PWM23 LPCPD#/WUI6/GPE6 LC_GPA4 R879 1
L2 K6 2 0_0402_5%
48 LED_KB_PWM13 ECSMI#/GPD4 PWM4/SMCLK5/GPA4 LC_GPA5 R880 1 PCH_I2C_CLK1 17
N4 J6 2 0_0402_5%
48 LED_KB_PWM12 LED_GPB6 ECSCI#/GPD3 PWM5/SMDAT5/GPA5 PCH_I2C_DATA1 17
TP142 1 H4
KBRST#/GPB6 A11
PS2CLK0/TMB0/CEC/GPF0 LED_KB_PWM25 48
CAD Note:EC_WRST_N M2
RXD/SIN0/PWUREQ#/BBO/SMCLK2ALT/WUI38/GPC7 PS2DAT0/TMB1/GPF1
B11
LED_KB_PWM26 48
LC_GPB3 B4 PS2
Trstpw=50ms;Twrstw=10us PWRSW#/GPB3
+3VALW_LC LC_WRST_N L1 M11
WRST# TACH0A/GPD6 LED_KB_PWM15 48

IT8376VG
M12
LC_I2C_CLK TACH1A/TMA1/GPD7 LED_KB_PWM16 48
B1 M6
LC_WRST_N PECI/WUI22/SMCLK2/GPF6 FAN PWM2/GPA2 LED_KB_PWM3 48
R525 1 2 100K_0402_5% A3 N6
LC_GPB0 LID_SW#/GPB1 PWM3/GPA3 LED_KB_PWM4 48
1 A4
C1368 AC_IN#/GPB0
M5
PWM0/GPA0 LED_KB_PWM1 48
1U_0402_10V6K N5
2 LC_SCK PWM1/GPA1 LED_KB_PWM2 48
B5 M7
LC_CS_N FSCK/GPG7 PWM6/SSCK/GPA6 LED_KB_PWM7 48
A7 K7 +3VALW_LC
LC_SI FSCE#/GPG3 PWM7/RIG1#/GPA7 LED_KB_PWM8 48
B6 FSPI
LC_SO A6 FMOSI/GPG4
FMISO/GPG5 CAD Note:
D2 LC_INT0_N_R R876 1 2 0_0402_5%
CTX0/TMA0/GPB2 A2
LC_INT0_N 17 PCH_I2C1 LC_INT0_N R567 2 1 100K_0402_5%
J12 XLP_OUT/GPB4
C KSI0/STB# C
J13 LC_INT1_N R620 2 1 100K_0402_5%
J9 KSI1/AFD#
H12 KSI2/INIT# LC_GPB0 R814 1 2 10K_0402_5%
H9 KSI3/SLIN# D1 LED_GPC0 1
KSI4 CRX0/GPC0 TP137
H10 C2 LED_GPC4 R896 1 2 0_0402_5% LC_GPB3 R825 1 2 10K_0402_5%
LC_KSI6 KSI5 TMRI0/WUI2/GPC4 LED_GPC6 TURBO_LED 48
H13 E1 1
KSI6 TMRI1/WUI3/GPC6 TP139
LC_KSI7 G9
M8 KSI7
J7 KSO0/PD0
KSO1/PD1 KB MX
N9
M9 KSO2/PD2
K8 KSO3/PD3 N1
KSO4/PD4 RI1#/WUI0/GPD0 LED_KB_PWM9 48
J8 N3
KSO5/PD5 RI2#/WUI1/GPD1 LED_KB_PWM10 48
N10 N7
KSO6/PD6 GINT/CTS0#/GPD5 LED_KB_PWM14 48
M10 GPIO
N11 KSO7/PD7
K9 KSO8/ACK#
N12 KSO9/BUSY
N13 KSO10/PE A13
KSO11/ERR# EGAD/WUI25/GPE1 LED_KB_PWM18 48
M13 A12
KSO12/SLCT EGCS#/WUI26/GPE2 LED_KB_PWM19 48
L12 B12
KSO13 EGCLK/WUI27/GPE3 LED_KB_PWM20 48
L13 E2
KSO14 GPE4 LED_KB_PWM21 48
K12 N8
KSO15 RTS1#/WUI5/GPE5 LED_KB_PWM22 48
K13
26 LC_KSO16 KSO16/SMOSI/GPC3
J10
26 LC_KSO17 KSO17/SMISO/GPC5

C12 D9
48 LED_TURBO_PWM_B DAC5/RIG0#/GPJ5 PS2CLK2/WUI20/SMINT10/GPF4 LED_KB_PWM27 48
B13 B9 CAD Note:
48 LED_TURBO_PWM_G DAC4/DCD0#/GPJ4 PS2DAT2/WUI21/SMINT11/GPF5 LC_I2C_DATA LED_KB_PWM28 48
C13 C1
48 LED_TURBO_PWM_R
TP143 1 D12 DAC3/TACH1B/SMINT7/GPJ3 PECIRQT#/WUI23/SMDAT2/GPF7 Hi:Enalbe Mirror +3VALW_LC
TP155 1 D13 DAC2/TACH0B/SMINT6/GPJ2 Low:Disable Mirror
TP161 1 E12 SMINT5/GPJ1
TACH2/SMINT4/GPJ0 E6
SSCE1#/GPG0 A5 LC_TEST1 R793 1 2 10K_0402_5%
E13 DTR1#/SBUSY/GPG1/ID7 E7 LC_TEST1
48 LED_SPKR_PWM_B ADC7/CTS1#/WUI31/GPI7 GPIO SSCE0#/GPG2
F12 D6 R407 1 @ 2 10K_0402_5%
48 LED_SPKR_PWM_G ADC6/DSR1#/WUI30/GPI6 DSR0#/GPG6
F10
48 LED_SPKR_PWM_R ADC5/DCD1#/WUI29/GPI5
F13
48 LED_TP_PWM_B ADC4/WUI28/SMINT3/GPI4
F9
48 LED_TP_PWM_G ADC3/SMINT2/GPI3
G12
48 LED_TP_PWM_R ADC2/SMINT1/GPI2 LED_GPH0
G13 D8 1 TP134
48 LED_KB_PWM30 ADC1/SMINT0/GPI1 CLKRUN#/WUI16/GPH0/ID0 LED_GPH3
G10 A9 1 TP135
48 LED_KB_PWM29 ADC0/GPI0 WUI19/GPH3/ID3/YM LED_GPH4
B8 1 TP136
GPH4/ID4/YP A8
B GPH5/ID5/DM B
LC_VCORE2/CK32KE G1 B7
VCORE2(CK32KE) GPH6/ID6/DP
LC_CK32K/GPJ6F2 CLOCK
GPJ6(CK32K)
1 VCORE
2

C249

AVSS
VSS

VSS
VSS
VSS
VSS
VSS
CAD Note: R511
@
IT8371 NC 2
0.1U_0402_25V6

10K_0402_5%
K5

H5

E5
F4
F5
G4
G5

E10
IT8376VG-128/AX
1

1
C320
CAD Note:
0.1U_0402_25V6

IT8371 Stuff 2

SPI ROM LC debug

+3VALW_LC +3VALW_LC_SPI LC_I2C_CLK 1 TP153


+3VALW_LC_SPI LC_I2C_DATA 1 TP154

R433 2 1 0_0603_5%
LC_KSI6 1 TP145
1 2 R783 2 1 1K_0402_5% LC_WP_N LC_KSI7 1 TP146
C475 C476
R788 2 1 1K_0402_5% LC_HOLD_N
10U_0402_6.3V6M 0.1U_0402_25V6
2 1

A A

+3VALW_LC_SPI

U16
LC_CS_N 1 8 LENOVO.CRDN
CS VCC
LC_SO R434 2 1 15_0402_5% LC_SO_R 2 7 LC_HOLD_N Title
DO HOLD
LED Contorller
LC_WP_N 3 6 LC_SCK_R R431 2 1 15_0402_5% LC_SCK
WP CLK Size Document Number
4 5 LC_SI_R R432 2 1 15_0402_5% LC_SI Custom Rev V0.3
GND DI Skylake-H
Date: Thursday, May 26, 2016 Sheet 47 of 99
W25Q64FVSSIG_SO8 "PROPERTY NOTE: this document contains information confidential and
8MB property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

JKB1

+5V +5V_KB_LED
+5V_KB_LED 1
1
@
PJ14
2
3
4
2
3
4
KB CONN.
1 2 2 5
47 LED_KB_PWM1 5

1
C1379 C1376 C1378 C1377 6
47 LED_KB_PWM2 6
7

0.1U_0402_25V6

0.1U_0402_25V6
47 LED_KB_PWM3 7
8

10U_0603_10V

1U_0402_10V6K
47 LED_KB_PWM4 8

2
2 1 1 9
D 47 LED_KB_PWM5 9 D
10
47 LED_KB_PWM6 10
11
47 LED_KB_PWM7 11
12
47 LED_KB_PWM8 12
13
47 LED_KB_PWM9 13
14
47 LED_KB_PWM10 14
15
47 LED_KB_PWM11 15
16
47 LED_KB_PWM12 16
17
47 LED_KB_PWM13 17
18
47 LED_KB_PWM14 18
19
47 LED_KB_PWM15 19
20
47 LED_KB_PWM16 20
21
47 LED_KB_PWM17 21
22
47 LED_KB_PWM18 22
23
47 LED_KB_PWM19 23
24
47 LED_KB_PWM20 24
25
47 LED_KB_PWM21 25
26
+5V_USB_KB 47 LED_KB_PWM22 26
27
47 LED_KB_PWM23 27
28
+5VALW 47 LED_KB_PWM24 28 USB2_DN4_R
29
47 LED_KB_PWM25 29
30
47 LED_KB_PWM26 30 USB2_DP4_R
1 31
47 LED_KB_PWM27 31
1 1 32
47 LED_KB_PWM28 32

2
+ C1371 C1372 33
47 LED_KB_PWM29 33
C1370 34 D37 D48

2
47 LED_KB_PWM30 34
35

220U_B2_6.3VM_R35M

0.1U_0402_25V6
0.1U_0402_25V6 @ @
2 2 2 47 LED_TURBO_PWM_R 35
36

AZ5425-01F.R7GR

AZ5425-01F.R7GR
47 LED_TURBO_PWM_G 36
37
47 LED_TURBO_PWM_B 37
U50 38
6 1 39 38
IN OUT R917 1 2 0_0402_5% USB2_DN4_R 40 39

1
18 USB2_DN4 USB2_DP4_R 40
5 2 R918 1 2 0_0402_5% 41
GND ILIM 18 USB2_DP4 41

1
42
R873 1 2 0_0402_5% 4 3 1 43 42
26,41,49,76,90,92 SUSON EN FAULT# TP130 43
44 51
7 50 TURBO_BTN_N 45 44 51 52
GND_PAD 26 BIOS_ONEKEY_N 45 52
1

46
AP2553FDC-7_U-DFN2020-6_2X2 R872 47 46
C C
10.7K_0402_1% 48 47
47 TURBO_LED 48
+5V_USB_KB 49
50 49
50
2

KYOCERA_046800650012846+

TP LED CONN.

+5V +5V_TP_LED +5V_TP_LED


B B
JTPBL1
@
PJ19 1
2 1
3 2
1 47 LED_TP_PWM_B 3
1

C1386 C1385 4
47 LED_TP_PWM_G 4
5 7
47 LED_TP_PWM_R 5 G1
6 8
10U_0603_10V

1U_0402_10V6K

6 G2
2

2
DRAPHO_FC1AF061-1201H

SPKR LED CONN.


+5V +5V_SPKR_LED +5V_SPKR_LED
JSPBL1
@
PJ21 1
2 1
3 2
1 47 LED_SPKR_PWM_B 3
1

C1392 C1391 4
47 LED_SPKR_PWM_G 4
5 7
47 LED_SPKR_PWM_R 5 G1
6 8
10U_0603_10V

1U_0402_10V6K

A A
6 G2
2

2
ACES_50208-00601-001
LENOVO.CRDN
Title
KB/BACKLIGHT LED
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 48 of 99
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

D D

JIO1

4A 1
+5VALW 1
2
3 2
4 3
5 4
6 5
7 6
8 7
9 8
10 9
2.4A 11 10
+3V 11
12
13 12
14 13
15 14
16 15
PLT_RST_N 17 16
17,26,27,38,40,42,43,50,63 PLT_RST_N CK_REQ_CR_N 17
18
22 CK_REQ_CR_N 19 18
PCIE_CR_TX_C_DP 20 19
18 PCIE_CR_TX_C_DP PCIE_CR_TX_C_DN 20
21
18 PCIE_CR_TX_C_DN 21
22
PCIE_CR_RX_DP 23 22
18 PCIE_CR_RX_DP PCIE_CR_RX_DN 23
card reader 18 PCIE_CR_RX_DN
24
25 24
25
CK_CR_P 26
22 CK_CR_P CK_CR_N 26
27
22 CK_CR_N 27
C 28 C
USB2_DN6 29 28
18 USB2_DN6 29
USB2_DP6
USB2.0 18 USB2_DP6 30
31 30
31
USB2_DN1 32
18 USB2_DN1 32
USB2_DP1 33
18 USB2_DP1 33
34
35 34
21 USB3_TX_DN1 35
21 USB3_TX_DP1 36
37 36
38 37
21 USB3_RX_DN1 38
39
21 USB3_RX_DP1 39
USB3.0 21 USB3_TX_DN6
40
41 40
41
21 USB3_TX_DP6 42
43 42
44 43
21 USB3_RX_DN6 44
21 USB3_RX_DP6 45
46 45
SUSON 47 46
26,41,48,76,90,92 SUSON USB_OC3_N 47
48
18 USB_OC3_N USB_OC0_N 49 48
18 USB_OC0_N NBSWON_N 50 49
26,51 NBSWON_N NOVO_BTN_N 50
BUTTON/LED 26 NOVO_BTN_N
26 PWR_LED_W
PWR_LED_W
51
52 51
52
BATT_LOW_LED_A 53
26 BATT_LOW_LED_A 53
54
55 54
56 55
57 56
58 57
59 58
60 59
HP_JD 61 60
28 HP_JD MIC_JD 61
62
28 MIC_JD 62
63
64 63
65 64
B MIC1R_SLEEVE 65 B
Audio Jack 28 MIC1R_SLEEVE
28 MIC1L_RING2
MIC1L_RING2
66
67 66
67
68
69 68
70 69
HP_OUTL 71 70
28 HP_OUTL HP_OUTR 71
72
28 HP_OUTR 72
73
MIC2L_C 74 73 78
28 MIC2L_C MIC2R_C 74 GND
75
28 MIC2R_C 75
76 77
76 GND

KYOCERA_046287676012846+_76P P0.4

AGND

A A

LENOVO.CRDN
Title
IO BTB Conn
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 49 of 99
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

VCCIO_EN SLG4P4603VTR

+1.0VALW
+1.0V_VCCSTG

+3VALW +3VALW +3VALW_SLG

2
C601 R831 2 1 0_0402_5% +3VALW

2
R60 @
@ U59 @ 0.1U_0402_25V6 R51 H_VCCST_PWRGD R64 2 @ 1 100K_0402_5%
1

2
220K_0402_5% 1 5 @ C505 C506
NC1 Vcc

1
D D
100K_0402_5%
+1.0V_VCCSTG_RC 2

1U_0402_10V6K

0.1U_0402_25V6
+3V
A

1
2 3.3V level 2
C248 3 4 R537 1 @ 2 0_0402_5% VCCIO_EN TURBO_BTN_N R830 2 1 100K_0402_5%
@ GND Y VCCIO_EN 89
1500P_0402_50V7-K 74AUP1G07GW_SOT353-1
1

OD BUFFER

R520 1 2 0_0402_5% +3VALW_SLG


26,78,86,90,91,92 MAINON
U22

1 20 1 TP132
VDD IO17

ALL_SYS_PWRGD_PMIC 48 TURBO_BTN_N
R832 2 1 0_0402_5% 2
IN IO16
19 1 TP133

R833 2 1 0_0402_5% 3 18 1 TP144


26 TURBO_GPIO1 IO1 IO15
TP138 1 R834 2 @ 1 0_0402_5% 4 17 1 TP181
IO2 IO14
R835 2 @ 1 0_0402_5% 5 16 1 TP182
17 PCH_PLTRST_N IO3 IO13
+3VALW
1.0V LEVLE +1.0V_VCCSTG_RC R836 2 @ 1 0_0402_5% 6 15 R844 2 1 0_0402_5%
IO4 IO12 TURBO_GPIO3 26
3.3V LEVLE VCCIO_PWRGD R837 2 @ 1 0_0402_5% 7 14 R843 2 @ 1 0_0402_5% ALL_SYS_PWRGD_PMIC 3.3V LEVLE
IO5 IO11
3.3V LEVLE VDDQ_VTT_EN R839 2 @ 1 0_0402_5% OD 8 13 OD R842 2 @ 1 0_0402_5% H_VCCST_PWRGD 1.0V LEVLE
IO6 IO10
2

C623
R840 2 @ 1 0_0402_5% 9 12 OD R841 2 @ 1 0_0402_5% VCCIO_EN 3.3V LEVLE
17,26,27,38,40,42,43,49,63 PLT_RST_N IO7 IO9
0.1U_0402_25V6
1

1.2V LEVLE DDR_VTT_PG_CTRL R838 2 @ 1 0_0402_5% 10 11


IO8 GND
C C
5

U61 SLG4P4603VTR_QFN20P
Vcc

R521 1 2 0_0402_5% 2 3.3V level


89 VCCIO_PWRGD A ALL_SYS_PWRGD_PMIC_R
4 R538 1 2 0_0402_5%
1 Y ALL_SYS_PWRGD_PMIC 83
B
Gnd

1
+3V 74AUP1G08GW_SOT353-1 R56
3

ADD GATE 1M_0402_5%


2

2
R61
220K_0402_5%
1
2

C572
1500P_0402_50V7-K
1

H_VCCST_PWRGD

B +3VALW B
2

C622
U58 0.1U_0402_25V6
1

1
NC1 Vcc
5 CAD Note: H_VCCST_PWRGD
ALL_SYS_PWRGD_PMIC_R R300 2 1 0_0402_5% 2
1K PU at CPU side
A 1.0V level
1 3 4 H_VCCST_PWRGD
C699 GND Y H_VCCST_PWRGD 6

74AUP1G07GW_SOT353-1
1U_0402_10V6K

2 OD BUFFER

VDDQ_VTT_EN

A +1.2V_VDDQ A

C426 2 1 0.1U_0402_25V6 +3V


LENOVO.CRDN
2

Title
U56
PWRGD CONTROL
1 5 R49 System Memory Power Gate Control:
NC1 Vcc 220K_0402_5% Disables the platform memory VTT regulator Size Document Number
R57 1 2 0_0402_5% 2 in C8 and deeper and S3. C Rev V0.3
6 DDR_VTT_PG_CTRL A Skylake-H
1

3 4 VDDQ_VTT_EN Date: Thursday, May 26, 2016 Sheet 50 of 99


GND Y VDDQ_VTT_EN 76
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
74AUP1G07GW_SOT353-1 or disclosed to others or used for any purpose other than that for which it was
OD Buffer obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

XDP CONN.

1 TP48 1 XDP_TCK
6 XDP_PREQ_N XDP_TDO XDP_TCK 6
1 TP21 TP49 1
6 XDP_PRDY_N XDP_TRST_N XDP_TDO 6
TP23 TP50 1
XDP_TDI XDP_TRST_N 6
6 CFG0 1 TP51 1
XDP_TMS XDP_TDI 6
1 TP24 TP52 1
D 6 CFG1 XDP_TMS 6 D
1 TP26
6 CFG2
CFG3 1 TP28
6 CFG3
1 TP29 TP54 1
6 CFG4 CK_XDP_P 22
1 TP30 TP55 1
6 CFG5 CK_XDP_N 22
1 TP31
6 CFG6
1 TP33
6 CFG7
1 TP32
6 CFG8
1 TP34
6 CFG9
1 TP36
6 CFG10 XDP_PRSENT_CPU
1 TP39 CFG3 R269 1 @ 2 0_0402_5%
6 CFG11
1 TP38
6 CFG12 XDP_PRS XDP_PRSENT_PCH
1 TP40 R336 1 @ 2 0_0402_5%
6 CFG13
1 TP41
6 CFG14
1 TP43
6 CFG15
1 TP42
6 CFG16
1 TP44
6 CFG17
1 TP45
6 CFG18
1 TP47
6 CFG19
TP46

6 XDP_BPM0_N 1
1 TP56
6 XDP_BPM1_N
TP62
1
16,19,46 PCH_SMB_DAT
1 TP63 +1.0VALW
16,19,46 PCH_SMB_CLK
TP64

1
R596
2.2K_0402_5%

2
TP61 1 XDP_HOOK6
PCH_ITP_PMODE 19
C C
+3VALW

1
R202 1 2 0_0402_5% XDP_TRST_N R588
23 PCH_TRST_N
2.2K_0402_5%
R216 1 2 0_0402_5% XDP_TMS
19 PCH_JTAG_TMS

2
R220 1 2 0_0402_5% XDP_TCK
19 PCH_JTAGX XDP_HOOK3
TP60 1 R593 1 2 1K_0402_1%
XDP_TDI PCH_SI 17
R306 1 2 0_0402_5%
19 PCH_JTAG_TDI XDP_PRS
TP59 1 R594 1 2 1K_0402_5%
XDP_TDO PCH_WP_N 17
R507 1 2 0_0402_5%
19 PCH_JTAG_TDO

TP57 1 FP_RST_N
PCH_XDP_PREQ_N XDP_PREQ_N FP_RST_N 19
R200 1 2 0_0402_5%
23 PCH_XDP_PREQ_N
PCH_XDP_PRDY_N R201 1 2 0_0402_5% XDP_PRDY_N TP58 1
23 PCH_XDP_PRDY_N PCH_PWRBTN_N 19,26

EC Debug CONN. 80 Port Debug CONN.


B
MB PWRBTN B

CAD Note:
For EC flash and debug CAD Note:
SWPWR2
For 80 port debug SKSHAAE010_4P
JEC1 R326 1 @ 2 0_0402_5% @
+5VLDO
1 R327 1 2 0_0402_5% NBSWON_N R854 1 2 0_0402_5% 1 2
1 +5V 26,49 NBSWON_N
2 JDBUG1
3 2 +5V_DEBUG 1
26 MY15 3 1
26 MY10 4 26,40,73,74 EC_SMB_CLK0 EC_SMB_CLK0 2 6
5 4 EC_SMB_DAT0 3 2 GND 3 4
26 MY11 5 26,40,73,74 EC_SMB_DAT0 3
26 MY14 6 26,73,74 MBAT_PRES_N MBAT_PRES_N 4 7
7 6 5 4 GND
26 MY13 7 5
26 MY12 8 @
9 8 KRYO_046809605020846+ C509 2 1 1000P_0402_50V7K
26 MY3 9
26 MY6 10
11 10
26 MY8 11
26 MY7 12
13 12 1 2
26 MY4 13 1 2
26 MY2 14
15 14
26 MX0 15
26 MY1 16 D55 @
17 16
26 MY5 17 AZ5425-01F.R7GR
26 MX3 18
18
26 MX2
26 MY0
26 MX5
19
20
21
19
20
21
PCH UART Debug CONN.
26 MX4 22
23 22
26 MY9 23
26 MX6 24
24 G1
27 CAD Note:
25 28
26 MX7
26 25 G2 For PCH UART port debug
26 MX1 26 +3V
KRYO_046299626120846+ +5V

A A
1 TP15 +5V +3V TP19 1

1 TP16 TXD LENOVO.CRDN


17 PCH_UART2_TXD
1 TP17 RXD Title
17 PCH_UART2_RXD
XDP/DEBUG
1 TP18 GND
Size Document Number
C Rev V0.3
Skylake-H
BRD Note:
Date: Thursday, May 26, 2016 Sheet 51 of 99
Place TP on board edge and "PROPERTY NOTE: this document contains information confidential and
Add sickscreen of net name property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

G2A
+3V_GPU R1004 1 @ 2 10K_0402_5% INS35183435
BGA2152 +PEX_VDD
+3V_GPU pull up, follow NV COMMON

1/23 PCI_EXPRESS

R1003 1 2 10K_0402_5%

10U_0603_10V

10U_0603_10V
1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

4.7U_0603_6.3VAK

4.7U_0603_6.3VAK
D 17,68,80 DGPU_PWROK D
+3V_GPU BB33

C661

C2684

22U_0603_6.3V6M
0.1U_0402_16V7K
PEX_DVDD 1 1 1

1
DGPU_PEX_RST_N BK26 BB35

C1340

C655

C656

C657

C658

C659

C660

C665
1 63,68 DGPU_PEX_RST_N PEX_RST PEX_DVDD
@ PEX_DVDD BB36
CLK_REQ_PEG_N_R BL26 PEX_CLKREQ PEX_DVDD BC33

2
2 2 2

1
PEX_DVDD BC35
2 R600 CK_PEG1_P BM26 BC36
22 CK_PEG1_P PEX_REFCLK PEX_DVDD
CK_PEG1_N BM27 PEX_REFCLK PEX_DVDD BD33
22 CK_PEG1_N
2 10K_0402_5% PEX_DVDD BD36
PEG_PRX_GTX_P0 C650 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_P0 BG26 PEX_TX0

2
PEG_PRX_GTX_N0 C662 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_N0 BH26 PEX_TX0 Place NEAR BALLS Place between GPU and PS

6 1 CLK_REQ_PEG_N_R PEG_PTX_C_GRX_P0 BL27 PEX_RX0


22 CK_REQ_PEG1_N PEG_PTX_C_GRX_N0 BK27 PEX_RX0
Q13A
AO5804EL_SC89-6 PEG_PRX_GTX_P1 C663 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_P1 BF26 PEX_TX1
PEG_PRX_GTX_N1 C664 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_N1 BE26 PEX_TX1 PEX_HVDD BB26
R601 2 @ 1 0_0402_5% PEX_HVDD BB27
PEG_PTX_C_GRX_P1 BK29 PEX_RX1 PEX_HVDD BB29 +1.8V_MAIN
PEG_PTX_C_GRX_N1 BL29 PEX_RX1 PEX_HVDD BB32
PEX_HVDD BC26
PEG_PRX_GTX_P2 C653 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_P2 BF27 PEX_TX2 PEX_HVDD BC27
PEG_PRX_GTX_N2 C654 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_N2 BG27 PEX_TX2 PEX_HVDD BC29
BC30

10U_0603_10V

10U_0603_10V
1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

4.7U_0603_6.3VAK

4.7U_0603_6.3VAK
PEX_HVDD
PEG_PTX_C_GRX_P2 BM29 BC32

C677

C684

22U_0603_6.3V6M
PEX_RX2 PEX_HVDD 1 1 1

1
PEG_PTX_C_GRX_N2 BM30 BD27

C666

C667

C668

C669

C676

C678

C683
PEX_RX2 PEX_HVDD
5 PEX_HVDD BD30
PEG_PRX_GTX_P3 C670 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_P3 BG29 PEX_TX3

2
PEG_PRX_GTX_N3 C671 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_N3 BH29 2 2 2
PEX_TX3

4 3 PEG_PTX_C_GRX_P3 BL30 PEX_RX3


PEG_PTX_C_GRX_N3 BK30 PEX_RX3

PEG_PRX_GTX_P4 C672 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_P4 BF29 PEX_TX4 Place NEAR BALLS Place between GPU and PS
Q13B PEG_PRX_GTX_N4 C673 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_N4 BE29 PEX_TX4
AO5804EL_SC89-6
PEG_PTX_C_GRX_P4 BK32 PEX_RX4
PEG_PTX_C_GRX_N4 BL32 PEX_RX4
C +1.8V_MAIN C
PEG_PRX_GTX_P5 C674 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_P5 BF30 PEX_TX5
PEG_PRX_GTX_N5 C675 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_N5 BG30 PEX_TX5 R16
PEX_PLL_HVDD BB30 2 1
PEG_PTX_C_GRX_P5 BM32

0.1U_0402_16V7K
PEX_RX5
PEG_PTX_C_GRX_N5 BM33 PEX_RX5 0_0402_5%

C685
1
PEG_PRX_GTX_P6 C679 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_P6 BG32 PEX_TX6
PEG_PRX_GTX_N6 C680 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_N6 BH32 PEX_TX6

PEG_PTX_C_GRX_P6 BL33 2
PEX_RX6
PEG_PTX_C_GRX_N6 BK33 PEX_RX6

PEG_PRX_GTX_P7 C681 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_P7 BF32 PEX_TX7


PEG_PRX_GTX_N7 C682 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_N7 BE32 PEX_TX7

PEG_PTX_C_GRX_P7 BK35 PEX_RX7


PEG_PTX_C_GRX_N7 BL35 PEX_RX7

PEG_PRX_GTX_P8 C869 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_P8 BF33 PEX_TX8


PEG_PRX_GTX_N8 C868 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_N8 BG33 PEX_TX8

PEG_PTX_C_GRX_P8 BM35 PEX_RX8


PEG_PTX_C_GRX_N8 BM36 PEX_RX8

PEG_PRX_GTX_P9 C874 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_P9 BG35 PEX_TX9


PEG_PRX_GTX_N9 C870 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_N9 BH35 PEX_TX9

PEG_PTX_C_GRX_P9 BL36 PEX_RX9


PEG_PTX_C_GRX_N9 BK36 PEX_RX9

PEG_PRX_GTX_P10 C876 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_P10 BF35 PEX_TX10


PEG_PRX_GTX_N10 C875 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_N10 BE35 PEX_TX10

PEG_PTX_C_GRX_P10 BK38 PEX_RX10


PEG_PTX_C_GRX_N10 BL38 PEX_RX10

PEG_PRX_GTX_P11 C878 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_P11 BF36 PEX_TX11


B PEG_PRX_GTX_N11 PEG_PRX_C_GTX_N11 B
C877 2 1 0.22U_0402_10V6K BG36 PEX_TX11

PEG_PTX_C_GRX_P11 BM38 PEX_RX11


PEG_PTX_C_GRX_N11 BM39 PEX_RX11

PEG_PRX_GTX_P12 C880 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_P12 BG38 PEX_TX12


PEG_PRX_GTX_N12 C879 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_N12 BH38 PEX_TX12

PEG_PTX_C_GRX_P12 BL39 PEX_RX12


PEG_PTX_C_GRX_N12 BK39 PEX_RX12

PEG_PRX_GTX_P13 C882 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_P13 BF38 PEX_TX13


PEG_PRX_GTX_N13 C881 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_N13 BE38 PEX_TX13

PEG_PTX_C_GRX_P13 BK41 PEX_RX13


PEG_PTX_C_GRX_N13 BL41 PEX_RX13

PEG_PRX_GTX_P14 C883 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_P14 BF39 PEX_TX14


PEG_PRX_GTX_N14 C884 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_N14 BG39 PEX_TX14

PEG_PTX_C_GRX_P14 BM41 PEX_RX14


PEG_PTX_C_GRX_N14 BM42 PEX_RX14

PEG_PRX_GTX_P15 C886 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_P15 BH41 PEX_TX15 Close to GPU


PEG_PRX_GTX_N15 C885 2 1 0.22U_0402_10V6K PEG_PRX_C_GTX_N15 BG41 PEX_TX15
R606
PEG_PTX_C_GRX_P15 BL42 PEX_RX15 PEX_TERMP BL44 GPU_TERMP 1 2
PEG_PTX_C_GRX_N15 BK42 PEX_RX15 2.49K_0402_1%

PEG_PTX_C_GRX_P[0..15]
2 PEG_PTX_C_GRX_P[0..15]

PEG_PTX_C_GRX_N[0..15]
2 PEG_PTX_C_GRX_N[0..15]
A A

PEG_PRX_GTX_P[0..15]
LENOVO.CRDN
2 PEG_PRX_GTX_P[0..15] Title

PEG_PRX_GTX_N[0..15]
GPU PCIE
2 PEG_PRX_GTX_N[0..15] Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 52 of 96
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

MDB[0..63]
65 MDB[0..63]

MDA[0..63]
64 MDA[0..63]

G2B G2C
INS35189394 INS35190030
BGA2152 BGA2152
COMMON COMMON
CMDA[0..31] 64
2/23 FBA 3/23 FBB
D CMDB[0..31] 65 D
MDA0 U51 FBA_D0 FBA_CMD0 Y51 CMDA0 MDB0 H32 FBB_D0 FBB_CMD0 B35 CMDB0
MDA1 U48 FBA_D1 FBA_CMD1 Y52 CMDA1 MDB1 D32 FBB_D1 FBB_CMD1 A35 CMDB1
MDA2 U50 FBA_D2 FBA_CMD2 Y49 CMDA2 MDB2 A33 FBB_D2 FBB_CMD2 D35 CMDB2
MDA3 U49 FBA_D3 FBA_CMD3 AA52 CMDA3 MDB3 B32 FBB_D3 FBB_CMD3 A36 CMDB3
MDA4 R51 FBA_D4 FBA_CMD4 AA51 CMDA4 MDB4 E32 FBB_D4 FBB_CMD4 B36 CMDB4
MDA5 R50 FBA_D5 FBA_CMD5 AA50 CMDA5 MDB5 G32 FBB_D5 FBB_CMD5 C36 CMDB5
MDA6 R47 FBA_D6 FBA_CMD6 AC50 CMDA6 MDB6 J30 FBB_D6 FBB_CMD6 C38 CMDB6
MDA7 U46 FBA_D7 FBA_CMD7 AC51 CMDA7 MDB7 F32 FBB_D7 FBB_CMD7 B38 CMDB7
MDA8 V46 FBA_D8 FBA_CMD8 AC52 CMDA8 MDB8 H36 FBB_D8 FBB_CMD8 A38 CMDB8
MDA9 Y45 FBA_D9 FBA_CMD9 AC49 CMDA9 MDB9 G36 FBB_D9 FBB_CMD9 D38 CMDB9
MDA10 Y47 FBA_D10 FBA_CMD10 AD52 CMDA10 MDB10 J36 FBB_D10 FBB_CMD10 A39 CMDB10
MDA11 Y46 FBA_D11 FBA_CMD11 AD51 CMDA11 MDB11 F36 FBB_D11 FBB_CMD11 B39 CMDB11
MDA12 V50 FBA_D12 FBA_CMD12 AD50 CMDA12 MDB12 F33 FBB_D12 FBB_CMD12 C39 CMDB12
MDA13 V47 FBA_D13 FBA_CMD13 AF50 CMDA13 MDB13 D33 FBB_D13 FBB_CMD13 C41 CMDB13
MDA14 U52 FBA_D14 FBA_CMD14 AF51 CMDA14 MDB14 J32 FBB_D14 FBB_CMD14 B41 CMDB14
MDA15 V51 FBA_D15 FBA_CMD15 AF52 CMDA15 MDB15 G33 FBB_D15 FBB_CMD15 A41 CMDB15
MDA16 AJ44 FBA_D16 FBA_CMD16 AN50 CMDA16 MDB16 E45 FBB_D16 FBB_CMD16 B49 CMDB16
MDA17 AG48 FBA_D17 FBA_CMD17 AN51 CMDA17 MDB17 D45 FBB_D17 FBB_CMD17 A49 CMDB17
MDA18 AJ45 FBA_D18 FBA_CMD18 AN52 CMDA18 MDB18 F45 FBB_D18 FBB_CMD18 A48 CMDB18
MDA19 AG49 FBA_D19 FBA_CMD19 AM49 CMDA19 MDB19 G45 FBB_D19 FBB_CMD19 D47 CMDB19
MDA20 AF46 FBA_D20 FBA_CMD20 AM52 CMDA20 MDB20 D42 FBB_D20 FBB_CMD20 A47 CMDB20
MDA21 AF47 FBA_D21 FBA_CMD21 AM51 CMDA21 MDB21 E42 FBB_D21 FBB_CMD21 B47 CMDB21
MDA22 AF48 FBA_D22 FBA_CMD22 AM50 CMDA22 MDB22 F42 FBB_D22 FBB_CMD22 C47 CMDB22
MDA23 AD47 FBA_D23 FBA_CMD23 AK50 CMDA23 MDB23 H41 FBB_D23 FBB_CMD23 C45 CMDB23
MDA24 AD49 FBA_D24 FBA_CMD24 AK51 CMDA24 MDB24 E41 FBB_D24 FBB_CMD24 B45 CMDB24
MDA25 AD48 FBA_D25 FBA_CMD25 AK52 CMDA25 MDB25 F39 FBB_D25 FBB_CMD25 A45 CMDB25
MDA26 AC46 FBA_D26 FBA_CMD26 AJ49 CMDA26 MDB26 E39 FBB_D26 FBB_CMD26 D44 CMDB26
MDA27 AC47 FBA_D27 FBA_CMD27 AJ52 CMDA27 MDB27 D39 FBB_D27 FBB_CMD27 A44 CMDB27
MDA28 AA47 FBA_D28 FBA_CMD28 AJ51 CMDA28 MDB28 F38 FBB_D28 FBB_CMD28 B44 CMDB28
MDA29 AA46 FBA_D29 FBA_CMD29 AJ50 CMDA29 MDB29 E38 FBB_D29 FBB_CMD29 C44 CMDB29
MDA30 AA45 FBA_D30 FBA_CMD30 AG50 CMDA30 MDB30 D36 FBB_D30 FBB_CMD30 C42 CMDB30
MDA31 Y44 FBA_D31 FBA_CMD31 AG51 CMDA31 MDB31 E36 FBB_D31 FBB_CMD31 B42 CMDB31
MDA32 AW51 FBA_D32 FBA_CMD32 AG52 +1.55VSG MDB32 M50 FBB_D32 FBB_CMD32 A42 +1.55VSG
MDA33 BA52 FBA_D33 FBA_CMD33 AF49 MDB33 P48 FBB_D33 FBB_CMD33 D41
MDA34 AW50 FBA_D34 FBA_CMD34 Y50 FBA_DEBUG0 R607 1 @ 2 60.4_0402_1% MDB34 M51 FBB_D34 FBB_CMD34 C35 FBB_DEBUG0 R610 1 @ 2 60.4_0402_1%
MDA35 BA51 FBA_D35 FBA_CMD35 AR50 FBA_DEBUG1 R608 1 @ 2 60.4_0402_1% MDB35 M49 FBB_D35 FBB_CMD35 B50 FBB_DEBUG1 R609 1 @ 2 60.4_0402_1%
C MDA36 BA50 FBA_D36 MDB36 P47 FBB_D36 C
MDA37 BB50 FBA_D37 MDB37 P52 FBB_D37
MDA38 BA49 FBA_D38 MDB38 R46 FBB_D38
MDA39 AW49 FBA_D39 FBA_DBG_RFU1 AA44 MDB39 P46 FBB_D39 FBB_DBG_RFU1 J35
MDA40 AV48 FBA_D40 FBA_DBG_RFU2 AN44 MDB40 L50 FBB_D40 FBB_DBG_RFU2 J41
MDA41 AT49 FBA_D41 MDB41 L51 FBB_D41
MDA42 AT47 FBA_D42 MDB42 L52 FBB_D42
MDA43 AT48 FBA_D43 MDB43 L49 FBB_D43
MDA44 AT46 FBA_D44 FBA_CLK0 AG45 CLKA0 MDB44 M46 FBB_D44 FBB_CLK0 H42 CLKB0
MDA45 AV51 AG46 CLKA0_N CLKA0 64 MDB45 L47 G42 CLKB0_N CLKB0 65
FBA_D45 FBA_CLK0 FBB_D45 FBB_CLK0
MDA46 AV52 AK46 CLKA1 CLKA0_N 64 MDB46 M48 F47 CLKB1 CLKB0_N 65
FBA_D46 FBA_CLK1 FBB_D46 FBB_CLK1
MDA47 AV49 AK45 CLKA1_N CLKA1 64 MDB47 M47 E47 CLKB1_N CLKB1 65
FBA_D47 FBA_CLK1 CLKA1_N 64 FBB_D47 FBB_CLK1 CLKB1_N 65
MDA48 AJ48 FBA_D48 MDB48 D48 FBB_D48
MDA49 AJ46 FBA_D49 MDB49 C50 FBB_D49
MDA50 AJ47 FBA_D50 MDB50 C48 FBB_D50
MDA51 AK49 FBA_D51 MDB51 C49 FBB_D51
MDA52 AM47 FBA_D52 MDB52 E49 FBB_D52
MDA53 AM46 FBA_D53 MDB53 E50 FBB_D53
MDA54 AN48 FBA_D54 MDB54 F49 FBB_D54
MDA55 AN49 FBA_D55 MDB55 F48 FBB_D55
MDA56 AM44 FBA_D56 FBA_WCK01 U45 FBA_WCK01 MDB56 F50 FBB_D56 FBB_WCK01 J33 FBB_WCK01
MDA57 AM45 U44 FBA_WCK01_N FBA_WCK01 64 MDB57 D52 H33 FBB_WCK01_N FBB_WCK01 65
FBA_D57 FBA_WCK01 FBA_WCK01_N 64 FBB_D57 FBB_WCK01 FBB_WCK01_N 65
MDA58 AN45 FBA_D58 FBA_WCKB01 V45 MDB58 J50 FBB_D58 FBB_WCKB01 G35
MDA59 AN46 FBA_D59 FBA_WCKB01 V44 MDB59 H48 FBB_D59 FBB_WCKB01 H35
MDA60 AR48 FBA_D60 FBA_WCK23 AC45 FBA_WCK23 MDB60 H51 FBB_D60 FBB_WCK23 J39 FBB_WCK23
MDA61 AN47 AC44 FBA_WCK23_N FBA_WCK23 64 MDB61 J51 H39 FBB_WCK23_N FBB_WCK23 65
FBA_D61 FBA_WCK23 FBB_D61 FBB_WCK23
MDA62 AR47 AD46 FBA_WCK23_N 64 MDB62 H49 F41 FBB_WCK23_N 65
FBA_D62 FBA_WCKB23 FBB_D62 FBB_WCKB23
MDA63 AR46 FBA_D63 FBA_WCKB23 AD45 MDB63 H52 FBB_D63 FBB_WCKB23 G41
FBA_WCK45 AV47 FBA_WCK45 FBB_WCK45 L46 FBB_WCK45
AV46 FBA_WCK45_N FBA_WCK45 64 L45 FBB_WCK45_N FBB_WCK45 65
FBA_WCK45 FBB_WCK45
64 DQMA[0..3] DQMA0 U47 AW48 FBA_WCK45_N 64 65 DQMB[0..3] DQMB0 C32 M44 FBB_WCK45_N 65
FBA_DQM0 FBA_WCKB45 FBB_DQM0 FBB_WCKB45
DQMA1 Y48 FBA_DQM1 FBA_WCKB45 AW47 DQMB1 E33 FBB_DQM1 FBB_WCKB45 M45
DQMA2 AG47 FBA_DQM2 FBA_WCK67 AR45 FBA_WCK67 DQMB2 E44 FBB_DQM2 FBB_WCK67 H47 FBB_WCK67
DQMA3 AC48 AR44 FBA_WCK67_N FBA_WCK67 64 DQMB3 G39 H46 FBB_WCK67_N FBB_WCK67 65
64 DQMA[4..7] FBA_DQM3 FBA_WCK67 FBA_WCK67_N 64 65 DQMB[4..7] FBB_DQM3 FBB_WCK67 FBB_WCK67_N 65
DQMA4 BB51 FBA_DQM4 FBA_WCKB67 AT45 DQMB4 P49 FBB_DQM4 FBB_WCKB67 J47
DQMA5 AV50 FBA_DQM5 FBA_WCKB67 AT44 DQMB5 L48 FBB_DQM5 FBB_WCKB67 J46
DQMA6 AM48 FBA_DQM6 DQMB6 D50 FBB_DQM6
DQMA7 AR49 FBA_DQM7 DQMB7 H50 FBB_DQM7
B B

64 DQSA[0..3] DQSA0 R48 65 DQSB[0..3] DQSB0 B33


FBA_DQS_WP0 FBB_DQS_WP0
DQSA1 V48 FBA_DQS_WP1 DQSB1 E35 FBB_DQS_WP1
DQSA2 AF44 FBA_DQS_WP2 DQSB2 G44 FBB_DQS_WP2
DQSA3 AA48 FBA_DQS_WP3 DQSB3 H38 FBB_DQS_WP3
64 DQSA[4..7] DQSA4 BB52 +FB_PLL_AVDD +FB_PLLVDD +1.8V_MAIN 65 DQSB[4..7] DQSB4 P50 +FB_PLL_AVDD
FBA_DQS_WP4 FBB_DQS_WP4
DQSA5 AT50 FBA_DQS_WP5 DQSB5 J48 FBB_DQS_WP5
DQSA6 AK48 FBA_DQS_WP6 L18 DQSB6 D51 FBB_DQS_WP6
DQSA7 AR51 FBA_DQS_WP7 FBA_PLL_AVDD AN42 1 R19 2 1 2 DQSB7 F51 FBB_DQS_WP7 FBB_PLL_AVDD L38 +FB_PLL_AVDD
0_0603_5% MPZ1608S300AT_30ohm_0.010ohm DCR_5A

W47 NV DG: 30 ohm bead(0603 max ESR 10 mohm) Y17


0.1U_0402_16V7K

0.1U_0402_16V7K
GND GND
W49 GND Y18 GND
W51 Y19
C686

C690
22U_0603_6.3V6M

GND 1 1 GND 1
W6 Y20
C687

GND GND
W8 GND Y21 GND
Y14 GND Y22 GND
Y15 2 2 Y23 2
GND GND
Y16 GND Y24 GND

+FB_PLLVDD
AF42 FB_REFPLL_AVDD0
R20 1 2 FB_REFPLL_AVDD_GPU L29 FB_REFPLL_AVDD1
0_0603_5%
0.1U_0402_16V7K

0.1U_0402_16V7K
C688

C689

1 1

2 2

A A

+1.55VSG
LENOVO.CRDN
CMDA1 10K_0402_5%1 2 R2195 CMDA2 10K_0402_5%1 2 R2200
Title
GPU FB A/B
CMDA17 10K_0402_5%1 2 R2197 CMDA18 10K_0402_5%1 2 R2193
Size Document Number
C Rev V0.3
CMDB1 10K_0402_5%1 2 R2198 CMDB2 10K_0402_5%1 2 R2194
Skylake-H
Date: Thursday, May 26, 2016 Sheet 53 of 96
"PROPERTY NOTE: this document contains information confidential and
CMDB17 10K_0402_5%1 2 R2199 CMDB18 10K_0402_5%1 2 R2196 property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

MDC[0..63]
66 MDC[0..63] MDD[0..63]
67 MDD[0..63]

G2D G2E
INS35199744 INS35200249
BGA2152 BGA2152
COMMON COMMON

4/23 FBC 5/23 FBD


CMDC[0..31] 66 CMDD[0..31] 67
MDC0 C6 FBC_D0 FBC_CMD0 C11 CMDC0 MDD0 AK8 FBD_D0 FBD_CMD0 AD2 CMDD0
MDC1 D6 FBC_D1 FBC_CMD1 B11 CMDC1 MDD1 AK4 FBD_D1 FBD_CMD1 AD1 CMDD1
D D
MDC2 A6 FBC_D2 FBC_CMD2 A11 CMDC2 MDD2 AK2 FBD_D2 FBD_CMD2 AD4 CMDD2
MDC3 B6 FBC_D3 FBC_CMD3 D11 CMDC3 MDD3 AK3 FBD_D3 FBD_CMD3 AC1 CMDD3
MDC4 B4 FBC_D4 FBC_CMD4 A12 CMDC4 MDD4 AK5 FBD_D4 FBD_CMD4 AC2 CMDD4
MDC5 A4 FBC_D5 FBC_CMD5 B12 CMDC5 MDD5 AK6 FBD_D5 FBD_CMD5 AC3 CMDD5
MDC6 B3 FBC_D6 FBC_CMD6 C12 CMDC6 MDD6 AK9 FBD_D6 FBD_CMD6 AA3 CMDD6
MDC7 C4 FBC_D7 FBC_CMD7 C14 CMDC7 MDD7 AK7 FBD_D7 FBD_CMD7 AA2 CMDD7
MDC8 D9 FBC_D8 FBC_CMD8 B14 CMDC8 MDD8 AG4 FBD_D8 FBD_CMD8 AA1 CMDD8
MDC9 C9 FBC_D9 FBC_CMD9 A14 CMDC9 MDD9 AF9 FBD_D9 FBD_CMD9 AA4 CMDD9
MDC10 E9 FBC_D10 FBC_CMD10 D14 CMDC10 MDD10 AG6 FBD_D10 FBD_CMD10 Y1 CMDD10
MDC11 B9 FBC_D11 FBC_CMD11 A15 CMDC11 MDD11 AG7 FBD_D11 FBD_CMD11 Y2 CMDD11
MDC12 B8 FBC_D12 FBC_CMD12 B15 CMDC12 MDD12 AJ4 FBD_D12 FBD_CMD12 Y3 CMDD12
MDC13 A8 FBC_D13 FBC_CMD13 C15 CMDC13 MDD13 AJ5 FBD_D13 FBD_CMD13 V3 CMDD13
MDC14 F6 FBC_D14 FBC_CMD14 C17 CMDC14 MDD14 AJ6 FBD_D14 FBD_CMD14 V2 CMDD14
MDC15 E6 FBC_D15 FBC_CMD15 B17 CMDC15 MDD15 AG5 FBD_D15 FBD_CMD15 V1 CMDD15
MDC16 F18 FBC_D16 FBC_CMD16 B24 CMDC16 MDD16 Y6 FBD_D16 FBD_CMD16 L3 CMDD16
MDC17 G18 FBC_D17 FBC_CMD17 A24 CMDC17 MDD17 Y5 FBD_D17 FBD_CMD17 L2 CMDD17
MDC18 E18 FBC_D18 FBC_CMD18 D23 CMDC18 MDD18 V5 FBD_D18 FBD_CMD18 L1 CMDD18
MDC19 H18 FBC_D19 FBC_CMD19 A23 CMDC19 MDD19 Y4 FBD_D19 FBD_CMD19 M4 CMDD19
MDC20 D15 FBC_D20 FBC_CMD20 B23 CMDC20 MDD20 AA6 FBD_D20 FBD_CMD20 M1 CMDD20
MDC21 E15 FBC_D21 FBC_CMD21 C23 CMDC21 MDD21 AA5 FBD_D21 FBD_CMD21 M2 CMDD21
MDC22 G17 FBC_D22 FBC_CMD22 C21 CMDC22 MDD22 AC5 FBD_D22 FBD_CMD22 M3 CMDD22
MDC23 H17 FBC_D23 FBC_CMD23 B21 CMDC23 MDD23 AC4 FBD_D23 FBD_CMD23 P3 CMDD23
MDC24 J15 FBC_D24 FBC_CMD24 A21 CMDC24 MDD24 AD7 FBD_D24 FBD_CMD24 P2 CMDD24
MDC25 H15 FBC_D25 FBC_CMD25 D20 CMDC25 MDD25 AC6 FBD_D25 FBD_CMD25 P1 CMDD25
MDC26 E14 FBC_D26 FBC_CMD26 A20 CMDC26 MDD26 AF6 FBD_D26 FBD_CMD26 R4 CMDD26
MDC27 F14 FBC_D27 FBC_CMD27 B20 CMDC27 MDD27 AD6 FBD_D27 FBD_CMD27 R1 CMDD27
MDC28 H11 FBC_D28 FBC_CMD28 C20 CMDC28 MDD28 AF7 FBD_D28 FBD_CMD28 R2 CMDD28
MDC29 G11 FBC_D29 FBC_CMD29 C18 CMDC29 MDD29 AF8 FBD_D29 FBD_CMD29 R3 CMDD29
MDC30 F11 FBC_D30 FBC_CMD30 B18 CMDC30 MDD30 AF2 FBD_D30 FBD_CMD30 U3 CMDD30
MDC31 E11 FBC_D31 FBC_CMD31 A18 CMDC31 MDD31 AF3 FBD_D31 FBD_CMD31 U2 CMDD31
MDC32 J29 FBC_D32 FBC_CMD32 D17 +1.55VSG MDD32 F4 FBD_D32 FBD_CMD32 U1 +1.55VSG
MDC33 F30 FBC_D33 FBC_CMD33 A17 MDD33 E1 FBD_D33 FBD_CMD33 V4
MDC34 H29 FBC_D34 FBC_CMD34 A9 FBC_DEBUG0 R612 1 @ 2 60.4_0402_1% MDD34 F3 FBD_D34 FBD_CMD34 AD3 FBD_DEBUG0 R614 1 @ 2 60.4_0402_1%
MDC35 G30 FBC_D35 FBC_CMD35 C24 FBC_DEBUG1 R611 1 @ 2 60.4_0402_1% MDD35 F5 FBD_D35 FBD_CMD35 J3 FBD_DEBUG1 R613 1 @ 2 60.4_0402_1%
MDC36 B30 FBC_D36 MDD36 D2 FBD_D36
MDC37 A30 FBC_D37 MDD37 D1 FBD_D37
MDC38 H30 FBC_D38 MDD38 C3 FBD_D38
C MDC39 C30 FBC_D39 FBC_DBG_RFU1 J14 MDD39 C2 FBD_D39 FBD_DBG_RFU1 AC9 C
MDC40 D27 FBC_D40 FBC_DBG_RFU2 J23 MDD40 J5 FBD_D40 FBD_DBG_RFU2 P9
MDC41 J26 FBC_D41 MDD41 J4 FBD_D41
MDC42 F27 FBC_D42 MDD42 L8 FBD_D42
MDC43 G27 FBC_D43 MDD43 J2 FBD_D43
MDC44 C27 FBC_D44 FBC_CLK0 G15 CLKC0 MDD44 F1 FBD_D44 FBD_CLK0 Y8 CLKD0
MDC45 B27 F15 CLKC0_N CLKC0 66 MDD45 F2 Y7 CLKD0_N CLKD0 67
FBC_D45 FBC_CLK0 CLKC0_N 66 FBD_D45 FBD_CLK0 CLKD0_N 67
MDC46 A27 FBC_D46 FBC_CLK1 H21 CLKC1 MDD46 H4 FBD_D46 FBD_CLK1 R8 CLKD1
MDC47 G29 J21 CLKC1_N CLKC1 66 MDD47 H5 R7 CLKD1_N CLKD1 67
FBC_D47 FBC_CLK1 CLKC1_N 66 FBD_D47 FBD_CLK1 CLKD1_N 67
MDC48 H20 FBC_D48 MDD48 V7 FBD_D48
MDC49 D18 FBC_D49 MDD49 V8 FBD_D49
MDC50 G20 FBC_D50 MDD50 V6 FBD_D50
MDC51 E20 FBC_D51 MDD51 V9 FBD_D51
MDC52 F23 FBC_D52 MDD52 U4 FBD_D52
MDC53 E21 FBC_D53 MDD53 R5 FBD_D53
MDC54 D21 FBC_D54 MDD54 R6 FBD_D54
MDC55 E23 FBC_D55 MDD55 U8 FBD_D55
MDC56 G24 FBC_D56 FBC_WCK01 F8 FBC_WCK01 MDD56 P6 FBD_D56 FBD_WCK01 AJ8 FBD_WCK01
MDC57 H26 G8 FBC_WCK01_N FBC_WCK01 66 MDD57 R9 AJ7 FBD_WCK01_N FBD_WCK01 67
FBC_D57 FBC_WCK01 FBC_WCK01_N 66 FBD_D57 FBD_WCK01 FBD_WCK01_N 67
MDC58 F24 FBC_D58 FBC_WCKB01 G9 MDD58 P4 FBD_D58 FBD_WCKB01 AG8
MDC59 G26 FBC_D59 FBC_WCKB01 F9 MDD59 P5 FBD_D59 FBD_WCKB01 AG9
MDC60 F26 FBC_D60 FBC_WCK23 H12 FBC_WCK23 MDD60 L7 FBD_D60 FBD_WCK23 AD8 FBD_WCK23
MDC61 D26 G12 FBC_WCK23_N FBC_WCK23 66 MDD61 L6 AD9 FBD_WCK23_N FBD_WCK23 67
FBC_D61 FBC_WCK23 FBC_WCK23_N 66 FBD_D61 FBD_WCK23 FBD_WCK23_N 67
MDC62 B26 FBC_D62 FBC_WCKB23 G14 MDD62 L4 FBD_D62 FBD_WCKB23 AC7
MDC63 C26 FBC_D63 FBC_WCKB23 H14 MDD63 L5 FBD_D63 FBD_WCKB23 AC8
FBC_WCK45 J27 FBC_WCK45 FBD_WCK45 J6 FBD_WCK45
H27 FBC_WCK45_N FBC_WCK45 66 J7 FBD_WCK45_N FBD_WCK45 67
66 DQMC[0..3] FBC_WCK45 FBC_WCK45_N 66 67 DQMD[0..3] FBD_WCK45 FBD_WCK45_N 67
DQMC0 A5 FBC_DQM0 FBC_WCKB45 E29 DQMD0 AJ1 FBD_DQM0 FBD_WCKB45 H7
DQMC1 C8 FBC_DQM1 FBC_WCKB45 F29 DQMD1 AG1 FBD_DQM1 FBD_WCKB45 H6
DQMC2 J18 FBC_DQM2 FBC_WCK67 G23 FBC_WCK67 DQMD2 AA7 FBD_DQM2 FBD_WCK67 P8 FBD_WCK67
DQMC3 F12 H23 FBC_WCK67_N FBC_WCK67 66 DQMD3 AD5 P7 FBD_WCK67_N FBD_WCK67 67
FBC_DQM3 FBC_WCK67 FBD_DQM3 FBD_WCK67
66 DQMC[4..7] DQMC4 D29 H24 FBC_WCK67_N 66 67 DQMD[4..7] DQMD4 D3 M7 FBD_WCK67_N 67
FBC_DQM4 FBC_WCKB67 FBD_DQM4 FBD_WCKB67
DQMC5 E27 FBC_DQM5 FBC_WCKB67 J24 DQMD5 H3 FBD_DQM5 FBD_WCKB67 M8
DQMC6 F20 FBC_DQM6 DQMD6 U5 FBD_DQM6
DQMC7 E26 FBC_DQM7 DQMD7 M9 FBD_DQM7

66 DQSC[0..3] DQSC0 D5 67 DQSD[0..3] DQSD0 AJ3


B
FBC_DQS_WP0 FBD_DQS_WP0 B
DQSC1 D8 FBC_DQS_WP1 DQSD1 AG2 FBD_DQS_WP1
DQSC2 E17 FBC_DQS_WP2 DQSD2 AA9 FBD_DQS_WP2
DQSC3 E12 FBC_DQS_WP3 DQSD3 AF4 FBD_DQS_WP3
66 DQSC[4..7] DQSC4 E30 +FB_PLL_AVDD 67 DQSD[4..7] DQSD4 E3 +FB_PLL_AVDD
FBC_DQS_WP4 FBD_DQS_WP4
DQSC5 B29 FBC_DQS_WP5 DQSD5 H2 FBD_DQS_WP5
DQSC6 G21 FBC_DQS_WP6 DQSD6 U6 FBD_DQS_WP6
DQSC7 E24 FBC_DQS_WP7 FBC_PLL_AVDD L17 +FB_PLL_AVDD DQSD7 M5 FBD_DQS_WP7 FBD_PLL_AVDD V11 +FB_PLL_AVDD

Y25 Y33
0.1U_0402_16V7K

0.1U_0402_16V7K
GND GND
Y26 GND Y34 GND
Y27 Y35
C691

C692
GND 1 GND 1
Y28 GND Y36 GND
Y29 GND Y37 GND
Y30 GND Y38 GND
Y31 2 Y39 2
GND GND
Y32 GND Y9 GND

GP104 GP106

FBD UNUSED

A A
+1.55VSG

CMDC1 10K_0402_5%1 2 R2202 CMDC2 10K_0402_5%1 2 R2206 LENOVO.CRDN


Title
CMDC17 10K_0402_5%1 2 R2203 CMDC18 10K_0402_5%1 2 R2207 GPU FB C/D
Size Document Number
CMDD1 10K_0402_5%1 2 R2204 CMDD2 10K_0402_5%1 2 R2201 C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 54 of 96
CMDD17 10K_0402_5%1 2 R2205 CMDD18 10K_0402_5%1 2 R857 "PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

G2J
G2F G2G G2H +NVVDDS INS35211931 +NVVDDS
+VGA_CORE INS35213064 +VGA_CORE +VGA_CORE INS35212479 +VGA_CORE +1.55VSG INS35213710 +1.55VSG BGA2152
BGA2152 COMMON
BGA2152 BGA2152
COMMON COMMON COMMON
23/23 VDDS
18/21 VDD_1/2 19/23 VDD_2/2 20/23 FBVDDQ

AA14 VDD VDD AG22 AP21 VDD VDD BB45 AA10 FBVDDQ FBVDDQ AT43 AP27 VDDS VDDS AC14
AA15 VDD VDD AG23 AP22 VDD VDD BB46 AA11 FBVDDQ FBVDDQ K12 AP28 VDDS VDDS AC15
AA16 VDD VDD AG40 AP23 VDD VDD BB47 AA42 FBVDDQ FBVDDQ K14 AP29 VDDS VDDS AC16
AA17 VDD VDD AH14 AP30 VDD VDD BB48 AA43 FBVDDQ FBVDDQ K15 AP35 VDDS VDDS AC17
AA18 VDD VDD AH15 AP31 VDD VDD BC38 AC10 FBVDDQ FBVDDQ K17 AP36 VDDS VDDS AC18
AA19 VDD VDD AH16 AP32 VDD VDD BC39 AC11 FBVDDQ FBVDDQ K18 AP37 VDDS VDDS AC24
D D
AA20 VDD VDD AH17 AP33 VDD VDD BC40 AC42 FBVDDQ FBVDDQ K20 AP38 VDDS VDDS AC25
AA21 VDD VDD AH18 AP34 VDD VDD BC41 AC43 FBVDDQ FBVDDQ K21 AP39 VDDS VDDS AC26
AA22 VDD VDD AH19 AR13 VDD VDD BC45 AD10 FBVDDQ FBVDDQ K23 AV14 VDDS VDDS AC27
AA23 VDD VDD AH20 AR40 VDD VDD BC47 AD11 FBVDDQ FBVDDQ K24 AV15 VDDS VDDS AC28
AA24 VDD VDD AH21 AT14 VDD VDD BC49 AD42 FBVDDQ FBVDDQ K26 AV16 VDDS VDDS AC29
AA25 VDD VDD AH22 AT15 VDD VDD BD39 AD43 FBVDDQ FBVDDQ K27 AV17 VDDS VDDS AC35
AA26 VDD VDD AH23 AT16 VDD VDD BD41 AF10 FBVDDQ FBVDDQ K29 AV18 VDDS VDDS AC36
AA27 VDD VDD AH24 AT17 VDD VDD BD46 AF43 FBVDDQ FBVDDQ K30 AV24 VDDS VDDS AC37
AA28 VDD VDD AH25 AT18 VDD VDD BD47 AG10 FBVDDQ FBVDDQ K32 AV25 VDDS VDDS AC38
AA29 VDD VDD AH26 AT19 VDD VDD BD48 AG11 FBVDDQ FBVDDQ K33 AV26 VDDS VDDS AC39
AA30 VDD VDD AH27 AT20 VDD VDD BD49 AG42 FBVDDQ FBVDDQ K35 AV27 VDDS VDDS AF14
AA31 VDD VDD AH28 AT21 VDD VDD BD50 AG43 FBVDDQ FBVDDQ K36 AV28 VDDS VDDS AF15
AA32 VDD VDD AH29 AT22 VDD VDD BD51 AJ10 FBVDDQ FBVDDQ K38 AV29 VDDS VDDS AF16
AA33 VDD VDD AH30 AT23 VDD VDD BE41 AJ11 FBVDDQ FBVDDQ K39 AV35 VDDS VDDS AF17
AA34 VDD VDD AH31 AT24 VDD VDD BE42 AJ42 FBVDDQ FBVDDQ K41 AV36 VDDS VDDS AF18
AA35 VDD VDD AH32 AT25 VDD VDD BE43 AJ43 FBVDDQ FBVDDQ L14 AV37 VDDS VDDS AF24
AA36 VDD VDD AH33 AT26 VDD VDD BE46 AK10 FBVDDQ FBVDDQ L15 AV38 VDDS VDDS AF25
AA37 VDD VDD AH34 AT27 VDD VDD BE47 AK11 FBVDDQ FBVDDQ L18 AV39 VDDS VDDS AF26
AA38 VDD VDD AH35 AT28 VDD VDD BE48 AK42 FBVDDQ FBVDDQ L20 R14 VDDS VDDS AG27
AA39 VDD VDD AH36 AT29 VDD VDD BE49 AK43 FBVDDQ FBVDDQ L21 R15 VDDS VDDS AG28
AB13 VDD VDD AH37 AT30 VDD VDD BE50 AM42 FBVDDQ FBVDDQ L23 R16 VDDS VDDS AG29
AB40 VDD VDD AH38 AT31 VDD VDD BE51 AM43 FBVDDQ FBVDDQ L24 R17 VDDS VDDS AG35
AC19 VDD VDD AH39 AT32 VDD VDD BE52 AN43 FBVDDQ FBVDDQ L26 R18 VDDS VDDS AG36
AC20 VDD VDD AK19 AT33 VDD VDD BF42 AR42 FBVDDQ FBVDDQ L27 R24 VDDS VDDS AG37
AC21 VDD VDD AK20 AT34 VDD VDD BF44 AR43 FBVDDQ FBVDDQ L30 R25 VDDS VDDS AG38
AC22 VDD VDD AK21 AT35 VDD VDD BF45 R42 FBVDDQ FBVDDQ L32 R26 VDDS VDDS AG39
AC23 VDD VDD AK22 AT36 VDD VDD BF47 R43 FBVDDQ FBVDDQ L33 R27 VDDS VDDS AK14
AC30 VDD VDD AK23 AT37 VDD VDD BF49 U10 FBVDDQ FBVDDQ L35 R28 VDDS VDDS AK15
AC31 VDD VDD AK30 AT38 VDD VDD BF51 U11 FBVDDQ FBVDDQ L36 R29 VDDS VDDS AK16
AC32 VDD VDD AK31 AT39 VDD VDD BG43 U43 FBVDDQ FBVDDQ L39 R35 VDDS VDDS AK17
AC33 VDD VDD AK32 AT42 VDD VDD BG44 V10 FBVDDQ FBVDDQ M10 1 2 R36 VDDS VDDS AK18
AC34 AK33 AU43 U16 V42 M43 0_0402_5% R1026 FBVDD_VSS_SENSE 79 R37 AK24
VDD VDD VDD VDD FBVDDQ FBVDDQ VDDS VDDS
AE14 VDD VDD AK34 AV19 VDD VDD U17 V43 FBVDDQ FBVDDQ P10 R38 VDDS VDDS AK25
AE15 VDD VDD AL13 AV20 VDD VDD U18 Y10 FBVDDQ FBVDDQ P11 R39 VDDS VDDS AK26
AE16 VDD VDD AL40 AV21 VDD VDD U19 Y11 FBVDDQ FBVDDQ P42 +1.55VSG W14 VDDS VDDS AK27
AE17 VDD VDD AM14 AV22 VDD VDD U20 Y42 FBVDDQ FBVDDQ P43 W15 VDDS VDDS AK28
AE18 VDD VDD AM15 AV23 VDD VDD U21 Y43 FBVDDQ FBVDDQ R10 W16 VDDS VDDS AK29

1
C AE19 VDD VDD AM16 AV30 VDD VDD U22 FBVDDQ R11 W17 VDDS VDDS AK35 C
AE20 VDD VDD AM17 AV31 VDD VDD U23 R1024 W18 VDDS VDDS AK36
AE21 VDD VDD AM18 AV32 VDD VDD U24 @ 100_0402_1% W24 VDDS VDDS AK37
AE22 VDD VDD AM19 AV33 VDD VDD U25 W25 VDDS VDDS AK38
AE23 VDD VDD AM20 AV34 VDD VDD U26 W26 VDDS VDDS AK39

2
AE24 VDD VDD AM21 AV42 VDD VDD U27 FBVDDQ_SENSE E52 1 2 W27 VDDS VDDS AP14
AE25 AM22 AV43 U28 0_0402_5% R1025 FBVDD_VCC_SENSE 79 W28 AP15
VDD VDD VDD VDD VDDS VDDS
AE26 VDD VDD AM23 AV44 VDD VDD U29 W29 VDDS VDDS AP16
AE27 VDD VDD AM24 AW13 VDD VDD U30 W35 VDDS VDDS AP17
AE28 VDD VDD AM25 AW40 VDD VDD U31 FB_VREF P45 1 TP118 W36 VDDS VDDS AP18
AE29 VDD VDD AM26 AW42 VDD VDD U32 W37 VDDS VDDS AP24
AE30 VDD VDD AM27 AW43 VDD VDD U33 W38 VDDS VDDS AP25
AE31 VDD VDD AM28 AW44 VDD VDD U34 W39 VDDS VDDS AP26
AE32 VDD VDD AM29 AW45 VDD VDD U35 +1.55VSG
AE33 VDD VDD AM30 AY14 VDD VDD U36
AE34 VDD VDD AM31 AY18 VDD VDD U37 FB_CAL_PD_VDDQ R44 40.2_0402_1% 2 1 R1022
AE35 VDD VDD AM32 AY22 VDD VDD U38
AE36 VDD VDD AM33 AY26 VDD VDD U39 FB_CAL_PU_GND P44 40.2_0402_1% 2 1 R1021
AE37 VDD VDD AM34 AY27 VDD VDD V13
AE38 VDD VDD AM35 AY31 VDD VDD V40 FB_CALTERM_GND R45 60.4_0402_1% 1 2 R1023 VDDS_SENSE BM45 VCCSENSE_NVVDDS
AE39 AM36 AY35 W19 BM44 VSSSENSE_NVVDDS VCCSENSE_NVVDDS 87
VDD VDD VDD VDD GNDS_SENSE
AF13 AM37 AY39 W20 VSSSENSE_NVVDDS 87
VDD VDD VDD VDD
AF30 VDD VDD AM38 AY43 VDD VDD W21
AF31 VDD VDD AM39 AY45 VDD VDD W22
AF32 VDD VDD AP19 BA43 VDD VDD W23
AF33 VDD VDD AP20 BA44 VDD VDD W30
AF34 VDD VDD BK52 BA45 VDD VDD W31
AF40 VDD VDD BL46 BA46 VDD VDD W32
AG13 VDD VDD BL47 BA47 VDD VDD W33
AG19 VDD VDD BL48 BB38 VDD VDD W34
AG20 VDD VDD BL49 BB39 VDD
AG21 VDD VDD BL50
BG45 VDD VDD BL51
BG46 VDD VDD BL52
BG47 VDD VDD BM47
BG48 VDD VDD BM48
BG49 VDD VDD BM49
BG50 VDD VDD BM50
B B
BG51 VDD VDD BM51
BG52 VDD VDD N14
BH44 VDD VDD N18
BH45 VDD VDD N22
BH47 VDD VDD N26
BH48 VDD VDD N27
BH49 VDD VDD N31
BH50 VDD VDD N35 NVVDD_SENSE BK45 VCCSENSE_VGA
BH51 N39 BL45 VSSSENSE_VGA VCCSENSE_VGA 80
VDD VDD GND_SENSE VSSSENSE_VGA 80
BH52 VDD VDD P13
BJ44 VDD VDD P40
BJ45 VDD VDD R19
BJ46 VDD VDD R20
BJ47 VDD VDD R21
BJ48 VDD VDD R22
BJ49 VDD VDD R23
BJ50 VDD VDD R30 G2I
BJ51 VDD VDD R31 INS35212361
BJ52 VDD VDD R32 BGA2152
COMMON
BK47 VDD VDD R33 +1.8V_AON
BK48 VDD VDD R34 21/23 NC/1V8
BK49 VDD VDD U14
BK50 VDD VDD U15 AT9 NC 1V8_AON BA10
BK51 VDD BA6 NC 1V8_AON BB14
BA9 NC 1V8_AON BC14
BD14 NC
BE12 NC
BG6 NC
BH6 NC
BJ11 NC VDD18_GPU
BJ9 NC
BK44 NC
VDD18 AM10
VDD18 AM11
VDD18 AN10
VDD18 AN11
VDD18 AR10
A VDD18 AR11 A
VDD18 AT10
VDD18 AT11
VDD18 AV10 LENOVO.CRDN
VDD18 AV11
VDD18 AW10 Title
VDD18 AW11 GPU PWR
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 55 of 96
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

G2K G2L G2M


INS34699418 INS34701250 INS34700388
BGA2152 BGA2152 BGA2152
COMMON COMMON COMMON

16/23 GND_1/3 17/23 GND_2/3 22/23 GND_3/3

A2 GND GND AH6 AR20 GND GND B52 BL43 GND GND N6
A26 GND GND AH8 AR21 GND GND B7 BL5 GND GND N8
A29 GND GND AJ14 AR22 GND GND BA48 BL7 GND GND P14
A3 GND GND AJ15 AR23 GND GND BB49 BM2 GND GND P15
A32 GND GND AJ16 AR24 GND GND BC13 BM3 GND GND P16
A50 GND GND AJ17 AR25 GND GND BC16 C1 GND GND P17
A51 GND GND AJ18 AR26 GND GND BC19 C29 GND GND P18
AA49 GND GND AJ19 AR27 GND GND BC2 C33 GND GND P19
AA8 GND GND AJ2 AR28 GND GND BC22 C5 GND GND P20
D D
AB10 GND GND AJ20 AR29 GND GND BC25 C51 GND GND P21
AB14 GND GND AJ21 AR30 GND GND BC28 C52 GND GND P22
AB15 GND GND AJ22 AR31 GND GND BC31 D10 GND GND P23
AB16 GND GND AJ23 AR32 GND GND BC34 D12 GND GND P24
AB17 GND GND AJ24 AR33 GND GND BC37 D13 GND GND P25
AB18 GND GND AJ25 AR34 GND GND BC4 D16 GND GND P26
AB19 GND GND AJ26 AR35 GND GND BC51 D19 GND GND P27
AB2 GND GND AJ27 AR36 GND GND BC6 D22 GND GND P28
AB20 GND GND AJ28 AR37 GND GND BC8 D24 GND GND P29
AB21 GND GND AJ29 AR38 GND GND BD26 D25 GND GND P30
AB22 GND GND AJ30 AR39 GND GND BD29 D28 GND GND P31
AB23 GND GND AJ31 AR4 GND GND BD32 D30 GND GND P32
AB24 GND GND AJ32 AR52 GND GND BD35 D31 GND GND P33
AB25 GND GND AJ33 AR9 GND GND BD38 D34 GND GND P34
AB26 GND GND AJ34 AT4 GND GND BD52 D37 GND GND P35
AB27 GND GND AJ35 AT5 GND GND BE10 D4 GND GND P36
AB28 GND GND AJ36 AT51 GND GND BE13 D40 GND GND P37
AB29 GND GND AJ37 AT52 GND GND BE15 D43 GND GND P38
AB30 GND GND AJ38 AT8 GND GND BE16 D46 GND GND P39
AB31 GND GND AJ39 AU10 GND GND BE18 D49 GND GND P51
AB32 GND GND AJ9 AU14 GND GND BE19 D7 GND GND R49
AB33 GND GND AK1 AU15 GND GND BE21 E2 GND GND R52
AB34 GND GND AK44 AU16 GND GND BE22 E4 GND GND T10
AB35 GND GND AK47 AU17 GND GND BE24 E48 GND GND T14
AB36 GND GND AL10 AU18 GND GND BE25 E5 GND GND T15
AB37 GND GND AL14 AU19 GND GND BE27 E51 GND GND T16
AB38 GND GND AL15 AU2 GND GND BE28 E8 GND GND T17
AB39 GND GND AL16 AU20 GND GND BE30 F10 GND GND T18
AB4 GND GND AL17 AU21 GND GND BE31 F13 GND GND T19
AB43 GND GND AL18 AU22 GND GND BE33 F16 GND GND T2
AB45 GND GND AL19 AU23 GND GND BE34 F17 GND GND T20
AB47 GND GND AL2 AU24 GND GND BE36 F19 GND GND T21
AB49 GND GND AL20 AU25 GND GND BE37 F21 GND GND T22
AB51 GND GND AL21 AU26 GND GND BE39 F22 GND GND T23
AB6 GND GND AL22 AU27 GND GND BE40 F25 GND GND T24
AB8 GND GND AL23 AU28 GND GND BF2 F28 GND GND T25
AD14 GND GND AL24 AU29 GND GND BF4 F31 GND GND T26
C AD15 GND GND AL25 AU30 GND GND BF41 F34 GND GND T27 C
AD16 GND GND AL26 AU31 GND GND BF6 F35 GND GND T28
AD17 GND GND AL27 AU32 GND GND BG10 F37 GND GND T29
AD18 GND GND AL28 AU33 GND GND BG13 F40 GND GND T30
AD19 GND GND AL29 AU34 GND GND BG16 F43 GND GND T31
AD20 GND GND AL30 AU35 GND GND BG19 F44 GND GND T32
AD21 GND GND AL31 AU36 GND GND BG22 F46 GND GND T33
AD22 GND GND AL32 AU37 GND GND BG25 F52 GND GND T34
AD23 GND GND AL33 AU38 GND GND BG28 F7 GND GND T35
AD24 GND GND AL34 AU39 GND GND BG31 G2 GND GND T36
AD25 GND GND AL35 AU4 GND GND BG34 G38 GND GND T37
AD26 GND GND AL36 AU45 GND GND BG37 G4 GND GND T38
AD27 GND GND AL37 AU47 GND GND BG40 G47 GND GND T39
AD28 GND GND AL38 AU49 GND GND BG42 G49 GND GND T4
AD29 GND GND AL39 AU51 GND GND BG7 G51 GND GND T43
AD30 GND GND AL4 AU6 GND GND BH15 G6 GND GND T45
AD31 GND GND AL43 AU8 GND GND BH18 H1 GND GND T47
AD32 GND GND AL45 AV4 GND GND BH2 H10 GND GND T49
AD33 GND GND AL47 AV45 GND GND BH21 H13 GND GND T51
AD34 GND GND AL49 AV9 GND GND BH24 H16 GND GND T6
AD35 GND GND AL51 AW14 GND GND BH27 H19 GND GND T8
AD36 GND GND AL6 AW15 GND GND BH30 H22 GND GND U7
AD37 GND GND AL8 AW16 GND GND BH33 H25 GND GND U9
AD38 GND GND AM4 AW17 GND GND BH36 H28 GND GND V14
AD39 GND GND AM9 AW18 GND GND BH39 H31 GND GND V15
AD44 GND GND AN14 AW19 GND GND BH42 H34 GND GND V16
AE10 GND GND AN15 AW20 GND GND BH5 H37 GND GND V17
AE2 GND GND AN16 AW21 GND GND BJ10 H40 GND GND V18
AE4 GND GND AN17 AW22 GND GND BJ12 H43 GND GND V19
AE43 GND GND AN18 AW23 GND GND BJ13 J1 GND GND V20
AE45 GND GND AN19 AW24 GND GND BJ14 J12 GND GND V21
AE47 GND GND AN20 AW25 GND GND BJ15 J17 GND GND V22
AE49 GND GND AN21 AW26 GND GND BJ16 J20 GND GND V23
AE51 GND GND AN22 AW27 GND GND BJ17 J38 GND GND V24
AE6 GND GND AN23 AW28 GND GND BJ18 J49 GND GND V25
AE8 GND GND AN24 AW29 GND GND BJ19 J52 GND GND V26
AF1 GND GND AN25 AW30 GND GND BJ20 K13 GND GND V27
AF19 GND GND AN26 AW31 GND GND BJ21 K16 GND GND V28
B B
AF20 GND GND AN27 AW32 GND GND BJ22 K19 GND GND V29
AF21 GND GND AN28 AW33 GND GND BJ23 K2 GND GND V30
AF22 GND GND AN29 AW34 GND GND BJ24 K22 GND GND V31
AF23 GND GND AN30 AW35 GND GND BJ25 K25 GND GND V32
AF27 GND GND AN31 AW36 GND GND BJ26 K28 GND GND V33
AF28 GND GND AN32 AW37 GND GND BJ27 K31 GND GND V34
AF29 GND GND AN33 AW38 GND GND BJ28 K34 GND GND V35
AF35 GND GND AN34 AW39 GND GND BJ29 K37 GND GND V36
AF36 GND GND AN35 AW4 GND GND BJ30 K4 GND GND V37
AF37 GND GND AN36 AW46 GND GND BJ31 K40 GND GND V38
AF38 GND GND AN37 AW5 GND GND BJ32 K45 GND GND V39
AF39 GND GND AN38 AW52 GND GND BJ33 K47 GND GND V49
AF45 GND GND AN39 AW8 GND GND BJ34 K49 GND GND V52
AF5 GND GND AN4 AY10 GND GND BJ35 K51 GND GND W10
AG14 GND GND AN5 AY2 GND GND BJ36 K6 GND GND W2
AG15 GND GND AN8 AY4 GND GND BJ37 K8 GND GND W4
AG16 GND GND AP10 AY47 GND GND BJ38 M52 GND GND W43
AG17 GND GND AP2 AY49 GND GND BJ39 M6 GND GND W45
AG18 GND GND AP4 AY51 GND GND BJ40 N10 GND
AG24 GND GND AP43 AY6 GND GND BJ41 N2 GND
AG25 GND GND AP45 AY8 GND GND BJ42 N4 GND
AG26 GND GND AP47 B1 GND GND BJ43 N43 GND
AG3 GND GND AP49 B10 GND GND BJ7 N45 GND
AG30 GND GND AP51 B13 GND GND BK1 N47 GND
AG31 GND GND AP6 B16 GND GND BL1 N49 GND
AG32 GND GND AP8 B19 GND GND BL10 N51 GND
AG33 GND GND AR14 B2 GND GND BL13 BL40 GND
AG34 GND GND AR15 B22 GND GND BL16
AG44 GND GND AR16 B25 GND GND BL19
AH10 GND GND AR17 B28 GND GND BL2
AH2 GND GND AR18 B31 GND GND BL22
AH4 GND GND AR19 B34 GND GND BL25
AH43 GND GND BL37 B37 GND GND BL28
AH45 GND GND BD24 B40 GND GND BL31
AH47 GND GND BC24 B43 GND GND BL34
AH49 GND B46 GND GND B5
AH51 GND B48 GND GND B51
A A

LENOVO.CRDN
Title
GPU GND
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 56 of 99
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
A
B
C
D
+VGA_CORE

+NVVDDS
C592 2 1 2 1 2 1 2 1

2
1
2
1
2
1

+
+
C2175 10U_0603_10V C2343 C2370 C2328 C2344 C34
330U_B2_2VM_R15M 1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K 330U_B2_2VM_R15M

C593 2 1 2 1 2 1 2 1

2
1
2
1
+

10U_0603_10V C2349 C2382 C2334 C2355 C87


1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K 330U_B2_2VM_R15M
C2174
2 1 C594 2 1 2 1 2 1 2 1

5
5

2
1
47U_0805_6.3V6-M 10U_0603_10V C2361 C2376 C2346 C2367 C153
1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K 2 1

C595 2 1 2 1 2 1 2 1 47U_0805_6.3V6-M

2
1
10U_0603_10V C2356 C2385 C2338 C2374 C167
1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K 2 1

2 1 2 1 2 1 2 1 47U_0805_6.3V6-M

C2366 C2393 C2350 C2392


1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K
2
1

2 1 2 1 2 1 2 1
C2323
C2373 C2324 C2358 C2326 22U_0603_6.3V6M
1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K

16 x 1uF
4 x 10uF
1 x 47uF
2
1

2 1 2 1 2 1 2 1

1 x 330uF
C2333
C2379 C2331 C2369 C414 22U_0603_6.3V6M
1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K

2 1 2 1 2 1 2 1
2
1

C2384 C2341 C548 C408 C2342


1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K 22U_0603_6.3V6M
Follow NV ref-design

2 1 2 1 2 1 2 1
2
1

C2321 C2336 C2377 C415 C2352


1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K 22U_0603_6.3V6M

2
1
2 1 2 1 2 1

@
C2204

2
1
+
4.7U_0402_6.3V6M C2389 C2381 C417 C2371

+1.8V_AON
2
1

1U_0402_6.3V7K C2440 1U_0402_6.3V7K 1U_0402_6.3V7K


2 1 330U_B2_2VM_R15M 10U_0603_10V
2 1 2 1 2 1

4
4

@
C2210

2
1
1U_0402_6.3V7K C586 + C2386 C2387 C2380

Near GPU
2
1

1U_0402_6.3V7K C2441 1U_0402_6.3V7K 1U_0402_6.3V7K


330U_B2_2VM_R15M 10U_0603_10V

2
1
2 1 2 1 2 1
C2211
0.1U_0402_16V7K C587 C2391 C420 C2388
2
1

1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K


10U_0603_10V

2
1
2 1 2 1 2 1
C2212
0.1U_0402_16V7K C588 C2330 C429 C2327
2
1

1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K


49 X 1uF
4 x 22uF
2 x 47uF

10U_0603_10V
11 x 10uF
2 x 330uF

2
1
@ 2 1 2 1 2 1

1 X 4.7UF, 1 X 1UF, 3 X 0.1UF


C2213
0.1U_0402_16V7K C589 C2325 C430 C2335
2
1

1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K

place 1 0.1uF cap near BA10


10U_0603_10V
2 1 2 1 2 1

place 1 0.1uf cap for BB14 and BC14 to share


C591 C2337 C432 C2345
2
1

1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K


2 x 330uF, Near GPU

10U_0603_10V
2 1 2 1 2 1

C590 C2340 C431 C2354


2
1

1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K


10U_0603_10V
2 1 2 1

C2348 C2365 C2363


2
1

1U_0402_6.3V7K 1U_0402_6.3V7K
10U_0603_10V
2 1 2 1

C2353 C2360 C2375


2
1

+1.8V_MAIN
1U_0402_6.3V7K 1U_0402_6.3V7K
10U_0603_10V
2 1 2 1

3
3

C2364 C2372 C2383

R2147 1
2
1

1U_0402_6.3V7K 1U_0402_6.3V7K
10U_0603_10V
2 1 2 1

C2359 C2378 C2390


2
1

1U_0402_6.3V7K 1U_0402_6.3V7K
10U_0603_10V
2 0_0603_5%
VDD18_GPU

2
1
2
1
2
1

C2198 C2193 C2189


4.7U_0402_6.3V6M 4.7U_0402_6.3V6M 4.7U_0402_6.3V6M

2 1 2 1 2 1

C2209 C2208 C2207


1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K

2
1
2
1
2
1

C2218 C2216 C2214


0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K

2
1
2
1
2
1
+1.55VSG

C2219 C2217 C2215


1 X 4.7UF, 1 X 1UF, 2X 0.1UF
1 X 4.7UF, 1 X 1UF, 2X 0.1UF

0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K C2394 2 1 2 1 2 1 2 1


2
1
2
1

1 X 4.7UF, 1 X 1UF, 3 X 0.1UF

C2180 10U_0603_10V C620 C2400 C2319 C596

2
1
22U_0603_6.3V6M 1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K

2
2

C2220
0.1U_0402_16V7K C2396 2 1 2 1 2 1 2 1
Partition D
Partition C
Partition B
Partition A

2
1
2
1

C2181 10U_0603_10V C619 C2401 C2329 C597


22U_0603_6.3V6M 1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K
Place close to GPU
Place close to GPU

C2395 2 1 2 1 2 1 2 1
2
1
2
1

C2182 10U_0603_10V C2405 C2402 C2332 C598


22U_0603_6.3V6M 1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K

C2397 2 1 2 1 2 1 2 1
2
1
2
1

C2183 10U_0603_10V C2404 C2403 C2339 C2357


22U_0603_6.3V6M 1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K
2
1

2 1 2 1 2 1 2 1
2 X 10UF, 6 X 1UF
2 X 10UF, 6 X 1UF
2 X 10UF, 6 X 1UF

C2184
2 X 10UF, 6 X 1UF

9 X 22UF
4 X 10UF

22U_0603_6.3V6M C2406 C2399 C2347 C2368


1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K
2
1

2 1 2 1 2 1 2 1
C2186
22U_0603_6.3V6M C2407 C2398 C2351 C2362
1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K 1U_0402_6.3V7K
C
Title

Size

Date:
2
1

C2320 C2178 C2408 C2176


2
1
2
1
2
1
2
1

C2185
22U_0603_6.3V6M 10U_0603_10V 10U_0603_10V 10U_0603_10V 10U_0603_10V
2
1

C2322 C2179 C2409 C2177


2
1
2
1
2
1
2
1

C2187
22U_0603_6.3V6M 10U_0603_10V 10U_0603_10V 10U_0603_10V 10U_0603_10V
Skylake-H
Document Number
2
1

GPU Decoupling

C2188
22U_0603_6.3V6M
Thursday, May 26, 2016

1
1

Sheet

obtained without the expressed written consent of LENOVO PND."


57
"PROPERTY NOTE: this document contains information confidential and
of
LENOVO.CRDN

or disclosed to others or used for any purpose other than that for which it was
96
Rev V0.3

property to LENOVO PND and shall not be reproduced or transferred to other documents
A
B
C
D
5 4 3 2 1

G2N
INS35340949
BGA2152
COMMON
stuff as default, close to GPU
D D
7/23 IFPAB

DL-DVI DVI/HDMI DP

IFPA_AUX BH11 GPU_DPA_AUX_DN_SDA GPU_DPA_AUX_DN_SDA R919 1 2 100K_0402_5%


1kohm_1% pull down for DP mode. SDA SDA
BG11 GPU_DPA_AUX_DP_SCL GPU_DPA_AUX_DN_SDA 32
SCL SCL IFPA_AUX
GPU_DPA_AUX_DP_SCL 32
GPU_DPA_AUX_DP_SCL R2208 1 2 100K_0402_5%
IFPA_L3 BF21 GPU_DPA_TX3_DN
2 R1015 1 IFPAB_RSET BD23 TXC TXC
BG21 GPU_DPA_TX3_DP GPU_DPA_TX3_DN 32
IFPAB_RSET TXC TXC IFPA_L3 GPU_DPA_TX3_DP 32
1K_0402_1%
+CORE_PLLVDD +IFPAB_PLLVDD IFPA_L2 BG23 GPU_DPA_TX2_DN
TXD0 TXD0 GPU_DPA_TX2_DN 32
IFPA_L2 BH23 GPU_DPA_TX2_DP
TXD0 TXD0 GPU_DPA_TX2_DP 32
R41 1 2 0_0603_5% BD21

0.1U_0402_16V7K
IFPAB_PLLVDD

MAX 102mA BF23 GPU_DPA_TX1_DN To DP port

C1343
1 TXD1 TXD1 IFPA_L1
GPU_DPA_TX1_DN 32
IFPA_L1 BE23 GPU_DPA_TX1_DP
TXD1 TXD1 GPU_DPA_TX1_DP 32

2 BF24 GPU_DPA_TX0_DN
TXD2 TXD2 IFPA_L0
BG24 GPU_DPA_TX0_DP GPU_DPA_TX0_DN 32
TXD2 TXD2 IFPA_L0
GPU_DPA_TX0_DP 32

IFPB_AUX BG12
SDA
SCL IFPB_AUX BH12

+IFP_IOVDD
IFPB_L3 BL18
MAX 118mA TXC
BB17 IFP_IOVDD IFPB_L3 BK18
TXC
BB15
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
IFP_IOVDD
1U_0402_6.3V7K

BB18 BK20
C2446

C2447

C1405

C1407
C 1 1 1 1 IFP_IOVDD TXD3 TXD0 IFPB_L2 C
1

BB20 BL20
C1406

IFP_IOVDD TXD3 TXD0 IFPB_L2


2

2 2 2 2 BM20
TXD4 TXD1 IFPB_L1
TXD4 TXD1 IFPB_L1 BM21

TXD5 TXD2 IFPB_L0 BL21


TXD5 TXD2 IFPB_L0 BK21

IFPAB

+1.8V_AON

1
R993
10K_0402_5%

2
GPU_DPA_HPD_R
B GPU_DPA_HPD_R 63 B
3
Q74B
AO5804EL_SC89-6

DP_HPD_CON 1 2 5
33 DP_HPD_CON
0_0402_5% R997
2

R994 4
@ 100K_0402_5%
1

A A

LENOVO.CRDN
Title
GPU IFP AB
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 58 of 96
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

G2R
INS35235742
BGA2152
COMMON

1kohm_1% pull down for HDMI mode. 8/23 IFPC

2 R922 1 IFPCD_RSET BD20 IFPCD_RSET


1K_0402_1% DVI/HDMI DP
+CORE_PLLVDD +IFPCD_PLLVDD 3.3V tolerance.

R36 1 2 0_0603_5% BD18 BL9 GPU_HDMI_DDC_DATA GPU_HDMI_DDC_DATA 1.8K_0402_1% 2 1 R2145

0.1U_0402_16V7K
IFPCD_PLLVDD SDA IFPC_AUX GPU_HDMI_DDC_DATA 35 +3V_GPU
MAX 102mA IFPC_AUX BK9 GPU_HDMI_DDC_CLK
SCL GPU_HDMI_DDC_CLK 35 GPU_HDMI_DDC_CLK 1.8K_0402_1% 2 1 R2146

C701
D 1 D

TXC IFPC_L3 BF17 C2410 2 1 0.1u_0201_10V6K


BE17 C2164 2 1 0.1u_0201_10V6K GPU_HDMI_CLK_DN 34
TXC IFPC_L3
2 GPU_HDMI_CLK_DP 34
IFPC_L2 BF18 C2414 2 1 0.1u_0201_10V6K
TXD0 GPU_HDMI_DATA0_DN 34
TXD0 IFPC_L2 BG18 C2163 2 1 0.1u_0201_10V6K
GPU_HDMI_DATA0_DP 34 To HDMI port
IFPC BG20 C2412 2 1 0.1u_0201_10V6K
TXD1 IFPC_L1
BH20 C2413 2 1 0.1u_0201_10V6K GPU_HDMI_DATA1_DN 34
TXD1 IFPC_L1 GPU_HDMI_DATA1_DP 34
+IFP_IOVDD IFPC_L0 BF20 C2411 2 1 0.1u_0201_10V6K
+PEX_VDD +IFP_IOVDD TXD2
BE20 C2165 2 1 0.1u_0201_10V6K GPU_HDMI_DATA2_DN 34
TXD2 IFPC_L0
GPU_HDMI_DATA2_DP 34
@
PJ1507 MAX 87mA BB21 IFP_IOVDD
AC coupling cap close to U2019
BB23

0.1U_0402_16V7K

0.1U_0402_16V7K
IFP_IOVDD
+1.8V_AON
4.7U_0603_6.3VAK

4.7U_0603_6.3VAK

4.7U_0603_6.3VAK

C2442

C1394
1 1
1

1
C705

C704
C1393

1
2

2 2 R1016
10K_0402_5%

2
GPU_HDMI_HPD_R
GPU_HDMI_HPD_R 63
6
Q74A
AO5804EL_SC89-6

GPU_HDMI_HPD 1 2 2
35 GPU_HDMI_HPD
0_0402_5% R1018

2
R1017 1
@ 100K_0402_5%

C Reserver @ HDMI conn. C

1
+1.8V_AON

1
R995
10K_0402_5%

2
GPU_EDP_HPD_R
GPU_EDP_HPD_R 63
3
Q75B
AO5804EL_SC89-6

GPU_EDP_HPD 1 2 5 6
31 GPU_EDP_HPD
0_0402_5% R998 Q75A
AO5804EL_SC89-6

2
R996 4 2
100K_0402_5%

G2Q

1
1
INS35235794
BGA2152
COMMON

9/23 IFPD

DVI/HDMI DP
stuff as default, close to GPU
IFPD_AUX BF11 GPU_EDP_AUX_DN
SDA
BE11 GPU_EDP_AUX_DP GPU_EDP_AUX_DN 31
SCL IFPD_AUX GPU_EDP_AUX_DP 31
B B

TXC IFPD_L3 BM14 GPU_EDP_AUX_DP R921 1 2 100K_0402_5%


TXC IFPD_L3 BM15

IFPD_L2 BL15 GPU_EDP_AUX_DN R920 1 2 100K_0402_5%


TXD0
IFPD_L2 BK15
TXD0
IFPD BK17 GPU_EDP_TX1_DN
TXD1 IFPD_L1
BL17 GPU_EDP_TX1_DP GPU_EDP_TX1_DN 31
TXD1 IFPD_L1 GPU_EDP_TX1_DP 31
IFPD_L0 BM17 GPU_EDP_TX0_DN To eDP
TXD2 GPU_EDP_TX0_DN 31
IFPD_L0 BM18 GPU_EDP_TX0_DP
TXD2 GPU_EDP_TX0_DP 31
+IFP_IOVDD

MAX 118mA BC15 IFP_IOVDD


BC17
0.1U_0402_16V7K

0.1U_0402_16V7K

IFP_IOVDD
1U_0402_6.3V7K

C2443

C1395

1 1
1

C703
2

2 2

A A

LENOVO.CRDN
Title
GPU IFP CD
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 59 of 96
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

G2P
INS35237467
BGA2152
COMMON
D D
1kohm_1% pull down for DP mode. 10/23 IFPE
DVI/HDMI DP

2 R923 1 IFPEF_RSET BD17 IFPEF_RSET SDA IFPE_AUX BL8 GPU_DPE_AUX_DN_SDA


1K_0402_1% BK8 GPU_DPE_AUX_DP_SCL GPU_DPE_AUX_DN_SDA 36
SCL IFPE_AUX
GPU_DPE_AUX_DP_SCL 36
+CORE_PLLVDD +IFPEF_PLLVDD
IFPE_L3 BG14 GPU_DPE_TX3_DN
TXC GPU_DPE_TX3_DP GPU_DPE_TX3_DN 36
R37 1 2 0_0603_5% BD15 BH14

0.1U_0402_16V7K
IFPEF_PLLVDD TXC IFPE_L3 GPU_DPE_TX3_DP 36
MAX 102mA
BF14 GPU_DPE_TX2_DN AR DP1

C702
1 TXD0 IFPE_L2
GPU_DPE_TX2_DN 36
TXD0 IFPE_L2 BE14 GPU_DPE_TX2_DP
GPU_DPE_TX2_DP 36
TXD1 IFPE_L1 BF15 GPU_DPE_TX1_DN
2 BG15 GPU_DPE_TX1_DP GPU_DPE_TX1_DN 36
TXD1 IFPE_L1 GPU_DPE_TX1_DP 36
IFPE
IFPE_L0 BG17 GPU_DPE_TX0_DN
TXD2 GPU_DPE_TX0_DN 36
TXD2 IFPE_L0 BH17 GPU_DPE_TX0_DP
GPU_DPE_TX0_DP 36
+IFP_IOVDD

MAX 118mA BC18 IFP_IOVDD


BC20

0.1U_0402_16V7K

0.1U_0402_16V7K
IFP_IOVDD

1U_0402_6.3V7K

C2445

C1398
1 1

C1397
2
2 2

stuff as default, close to GPU


C C

GPU_DPE_AUX_DN_SDA R925 1 2 100K_0402_5%

GPU_DPE_AUX_DP_SCL R924 1 2 100K_0402_5%

GPU_DPF_AUX_DN R927 1 2 100K_0402_5%

GPU_DPF_AUX_DP R926 1 2 100K_0402_5%

G2O
INS35237536
BGA2152
COMMON

6/23 IFPF
+IFP_IOVDD
DVI/HDMI DP

MAX 118mA BC21 IFP_IOVDD IFPF_AUX BM9 GPU_DPF_AUX_DN


SDA GPU_DPF_AUX_DN 37
BC23 BM8 GPU_DPF_AUX_DP
0.1U_0402_16V7K

0.1U_0402_16V7K

IFP_IOVDD SCL IFPF_AUX GPU_DPF_AUX_DP 37


C2444

C1396

1 1
IFPF_L3 BK11 GPU_DPF_TX3_DN
TXC GPU_DPF_TX3_DN 37
IFPF_L3 BL11 GPU_DPF_TX3_DP
B TXC GPU_DPF_TX3_DP 37 B
2 2 BM11 GPU_DPF_TX2_DN
TXD0 IFPF_L2 GPU_DPF_TX2_DN 37
IFPF_L2 BM12 GPU_DPF_TX2_DP
TXD0 GPU_DPF_TX2_DP 37

TXD1 IFPF_L1 BL12 GPU_DPF_TX1_DN


GPU_DPF_TX1_DN 37
AR DP2
IFPF_L1 BK12 GPU_DPF_TX1_DP
TXD1 GPU_DPF_TX1_DP 37
IFPF_L0 BK14 GPU_DPF_TX0_DN
TXD2 GPU_DPF_TX0_DN 37
IFPF TXD2 IFPF_L0 BL14 GPU_DPF_TX0_DP
GPU_DPF_TX0_DP 37

+1.8V_AON
1

R987
10K_0402_5%
2

GPU_DPE_HPD_R
GPU_DPE_HPD_R 63
6
Q76A
AO5804EL_SC89-6

GPU_DPE_HPD 1 2 2
36 GPU_DPE_HPD
0_0402_5% R988
2

R989 1
@ 100K_0402_5%
1

+1.8V_AON
1

R990
10K_0402_5%
A A
2

GPU_DPF_HPD_R
GPU_DPF_HPD_R 63
3
Q76B
AO5804EL_SC89-6

GPU_DPF_HPD 1 2 5 LENOVO.CRDN
37 GPU_DPF_HPD
0_0402_5% R991
Title
2

4
GPU IFP EF
R992
@ 100K_0402_5% Size Document Number
Custom Rev V0.3
Skylake-H
1

Date: Thursday, May 26, 2016 Sheet 60 of 96


"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

WWW.AliSaler.Com
5 4 3 2 1
5 4 3 2 1

G2S
Need confirm the Bead type/current with NV. INS35239550 G2T
BGA2152
INS35239489
+1.8V_MAIN +CORE_PLLVDD COMMON
BGA2152
COMMON
14/23 XTAL/PLL
L20 15/23 MISC 2
2 1 R33 1 2 0_0603_5% +VID_PLLVDD_GPU_1 BD12 SP_PLLVDD
MPZ1608S300AT_30ohm_0.010ohm DCR_5A ROM_CS BJ4 ROM_CS
R34 1 2 0_0603_5% +VID_PLLVDD_GPU_2 BC12 VID_PLLVDD
BK2 ROM_SI

0.1U_0402_16V7K

0.1U_0402_16V7K
4.7U_0603_6.3VAK
D
ROM_SI D
BK4 ROM_SO

22U_0603_6.3V6M
1 ROM_SO

1
STRAP0 BL3 BK3 ROM_SCLK

C693

C694

C696

C695
1 1 STRAP0 ROM_SCLK
STRAP1 BL4 STRAP1
STRAP2 BM4 STRAP2

2
2 STRAP3 BM5 STRAP3
2 2 STRAP4 BK5 STRAP4
STRAP5 BJ5 STRAP5

R35 1 2 0_0603_5% +CORE_PLLVDD_GPU U42 GPCPLL_AVDD0

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
AF11 GPCPLL_AVDD1 BUFRST BF9

C697

C698

C2415

C2416
1 1 1 1
BB24 XS_PLLVDD

2 2 2 2

R2251
BJ6 XTALSSIN XTALOUTBUFF BK6 2 @ 1 +1.8V_AON
BL6 XTALIN XTALOUT BM6 10K_0402_5%

Need confirm the crystal and CAP.

Y6 27MHZ_10PF_7V27000050

XTAL_IN 1 3 XTAL_OUT
1 3
GND GND

1
C 1 1 C
R2253 R2252
10K_0402_5% C1399 2 4 C1400 10K_0402_5%
10P_0402_50V8J 10P_0402_50V8J
2 2

2
+1.8V_AON +1.8V_MAIN
@
1 R962 2 1 R963 2
0_0402_5% 0_0402_5% +1.8V_AON +1.8V_AON
100K_0402_5%

100K_0402_5%

100K_0402_5%

100K_0402_5%

100K_0402_5%

100K_0402_5%
1

2
R944
R2156

R2157

R2158

R2159

R2160

R2161

1 1
+1.8V_AON 10K_0402_5% C1401 C1402

10U_0402_6.3V6M 0.1U_0402_16V7K
2

1
ROM_SCLK R2154 2 @ 1 100K_0402_5% U2021 2 2
@ @ @ @ ROM_CS ROM_CS_R
STRAP0 R2168 2 1 33_0402_5% 1 8
CS VCC
STRAP1 R2155 2 1 100K_0402_5% ROM_SO R928 1 2 0_0402_5% ROM_SO_R 2 7
DO HOLD
STRAP2 +1.8V_AON 3 6 ROM_SCLK_R R2209 2 1 33_0402_5% ROM_SCLK
WP CLK
STRAP3 HIGH 4 5 ROM_SI_R R929 2 1 33_0402_5% ROM_SI
ROM_SI R2150 2 1 100K_0402_5% GND DI
STRAP4 LOW
W25Q80EWSNIG_SOP 8P_150mil
STRAP5 HIGH R2151 2 @ 1 100K_0402_5% SA000080E00
+1.8V_AON NV RVL
100K_0402_5%

100K_0402_5%

100K_0402_5%

100K_0402_5%

100K_0402_5%

100K_0402_5%
1

ROM_SO R2152 2 @ 1 100K_0402_5%


R2162

R2163

R2164

R2165

R2166

R2167

B B
R2153 2 1 100K_0402_5%
2

@ @ @ @ @

STRAP0~2 , Please ref RVL for BOM stuffing

A
ROM_SCLK(LSB)/ROM_SI/ROM_SO(MSB) : A

LENOVO.CRDN
Title
GPU PLL/XTAL
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 61 of 96
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

G2V
INS35240765
BGA2152
COMMON

11/23 MIOA

MIOAD0 AN9
MIOAD1 AM2
MIOAD2 AN7
MIOAD3 AN6
MIOAD4 AR1
MIOAD5 AR6
MIOAD6 AR5
MIOAD7 AM8
D D
MIOAD8 AN3
MIOAD9 AR8
MIOAD10 AR3
AM5 MIOACAL_PD_VDDQ MIOAD11 AR2

AM6 MIOACAL_PU_GND

AM7 MIOA_VREF

MIOA_CTL3 AT7
MIOA_HSYNC AM1
MIOA_VSYNC AR7
MIOA_DE AN1

MIOA_CLKOUT AN2

MIOA_CLKIN AM3

C C

G2U
INS35240692
BGA2152
COMMON

12/23 MIOB

MIOBD0 AT3
MIOBD1 AV6
MIOBD2 AT2
MIOBD3 AT1
MIOBD4 AW6
MIOBD5 AV2
MIOBD6 AV1
MIOBD7 AV3
MIOBD8 AW3
MIOBD9 BA8
MIOBD10 AW7
AV7 MIOBCAL_PD_VDDQ MIOBD11 BB8
B B
AV8 MIOBCAL_PU_GND

AW9 MIOB_VREF

MIOB_CTL3 BB7
MIOB_HSYNC AV5
MIOB_VSYNC BA7
MIOB_DE AW2

GP104 GP106
MIOB_CLKOUT AW1

MIOB UNUSED MIOB_CLKIN AT6

A A

LENOVO.CRDN
Title
GPU MIO
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 62 of 96
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

OVER Heat Protect G2W


INS35243086
+1.8V_AON +3V_GPU

BGA2152
COMMON
R796 2 1 10K_0402_5%

+3V_GPU
13/23 MISC 1
SMBUS Address= 0x9E GPU_OVERT_N R797 2 @ 1 10K_0402_5%

GPU_OVERT_N BG5 OVERT I2CS_SCL BJ8 SMB_CLK_GPU


I2CS_SDA BH8 SMB_DATA_GPU +3V_GPU
H_THRMTRIP_N 6,20,68
need to confirm the resistor value

1
To PCH BF12 TS_VREF change to 0ohm from 33ohm-20160324
R798 I2CC_SCL BG9 I2CC_SCL_R R2169 1 2 0_0402_5% I2CC_SCL
BH9 I2CC_SDA_R R2170 1 2 0_0402_5% I2CC_SDA I2CC_SCL 68,80
10K_0402_5% 3 I2CC_SDA
I2CC_SDA 68,80
SMB_CLK_GPU R2294 1 2 2.2K_0402_5%

0.1U_0402_16V7K
2
BG8 I2CB_SCL SMB_DATA_GPU R2295 1 2 2.2K_0402_5%

@ C1329
D 1 I2CB_SCL D
GPU_OVERT 5 I2CB_SDA BF8 I2CB_SDA
AO5804EL_SC89-6
Q87B
2 BJ1
6 4
THERMDN
Q87A I2CC_SCL R2296 1 2 2.2K_0402_5%
AO5804EL_SC89-6 +1.8V_AON BJ2 THERMDP I2CC_SDA R2297 1 2 2.2K_0402_5%

GPU_OVERT_N 2

0.1U_0402_16V7K
68 GPU_OVERT_N

@ C1330
1
GPIO0 BD6 NVVDD_PWM_VID To PWR VGA CORE
NVVDD_PWM_VID 80

1
BB5 GC6_FB_EN I2CB_SCL R2298 1 2 2.2K_0402_5%

180_0402_1%

10K_0402_5%

10K_0402_5%
GPIO1 GC6_FB_EN 68
1 BD1 GPU_EVENT_N_R I2CB_SDA R2299 1 2 2.2K_0402_5%

R2256

R2255

R2254
6 2
GPIO2
GPIO3 BE4 NVVDDS_PWM_VID To PWR VGA CORE
1.8V_MAIN_EN_R NVVDDS_PWM_VID 87
@ GPIO4 BE1 Output,Open Drain,10 K? pull-up to 1V8_AON
R808 GPIO5 BG2 FRAME_LOCK_N NVSR pannel not used.

2
DGPU_PEX_RST_N 2 1 2 GPIO6 BD2 NVVDD_PSI
@ @ GPU_EDP_BL_PWM_LS NVVDD_PSI 80,87
0_0402_5% 0.1U_0402_16V7K AO5804EL_SC89-6 3 GPIO7 BD7
Q88A Q88B TP114 1 BK24 BH4 VRAM_VDDQ_ADJ_R
@ C1332

1 JTAG_TCK GPIO8
AO5804EL_SC89-6 TP117 1 BL23 JTAG_TMS GPIO9 BJ3 THERM_ALERT_N THERM_ALERT_N:
1 TP116 1 BM23 BD3 VRAM_VREF_CTL
JTAG_TDI GPIO10 VRAM_VREF_CTL 64,65,66,67 Output,Open Drain,10 K? pull-up to 1V8_AON
5 TP113 1 BM24 JTAG_TDO GPIO11 BH3 GPU_EDP_VDD_EN_LS
2 BL24 BE6 PWR_LEVEL_R Active Low Thermal Alert
JTAG_TRST GPIO12
GPIO13 BB1 GPU_EDP_BL_EN_LS N17E GPU uses GPIO9 as a dedicated output, not supported as an input.
GPIO14 BG4 GPU_DPA_HPD_R
4 GPU_DPA_HPD_R 58
GPIO15 BG1
BK23 NVJTAG_SEL GPIO16 BE2 SYS_PEX_RST_MON_N
GPIO17 BH1 GPU_EDP_HPD_R
GPU_EDP_HPD_R 59

1
BE3 GPU_DPE_HPD_R

10K_0402_5%

270_0402_1%
GPIO18 GPU_DPE_HPD_R 60

2 R1020 1
BD4

10K_0402_5%
R1019

R2257
GPIO19
GPIO20 BE5 NVVDDS_PSI Output,Open Drain,10 K? pull-up to 1V8_AON
BA5 NVVDDS_PSI 87
GPIO21
GPIO22 BB6

2
GPIO23 BG3 GPU_PEX_RST_HOLD_N
@ GPU_DPF_HPD_R
+3V_GPU GPIO24 BD5
GPU_DPF_HPD_R 60
GPIO25 BB2
GPIO26 BE7
C2694 1 2 0.1U_0402_16V7K GPIO27 BA4 GPU_HDMI_HPD_R
OC_WARN GPU_HDMI_HPD_R 59
C GPIO28 BB4 C
OC_WARN 68
GPIO29 BA3 GPU_EDPc_OUTPUT_CAP
GPU_EDPc_OUTPUT_CAP 81
U2027 GPIO30 BB3
5

M74VHC1GT08DFT2G_SC-70-5P GPIO31_RFU BA2


GPIO32_RFU BA1 +1.8V_AON
Vcc

VCC=3.3V, VIH>=1.4V 2
A 4 GPU_EDP_BL_PWM_R
GPU_EDP_BL_PWM_LS 1 Y GPU_EVENT_N_R R974 2 1 10K_0402_5%
B
Gnd

1.8V_MAIN_EN_R R975 2 1 10K_0402_5%


3
1

SA000080W00 NVVDD_PSI R977 2 1 10K_0402_5%


R2305 1.8V_MAIN_EN_R R976 1 2 1.8V_MAIN_EN
R2300

1.8V_MAIN_EN 68,69 VRAM_VDDQ_ADJ


10K_0402_5% AND Gate 0_0402_5% to open 1.8V_main and NVVDD R980 2 @ 1 10K_0402_5%
100K_0402_5%

GPU_EDP_BL_PWM_R R979 1 2 EDP_BL_PWM


0_0402_5% EDP_BL_PWM 31 THERM_ALERT_N R982 2 1 10K_0402_5%
2

VRAM_VDDQ_ADJ_R R981 1 2 VRAM_VDDQ_ADJ


VRAM_VDDQ_ADJ 79 PWR_LEVEL_R
0_0402_5% Need confirm. R983 1 2 100K_0402_5%
GPU_EDP_VDD_EN_R R905 1 2 EDP_VDD_EN
0_0402_5% EDP_VDD_EN 90,92 OC_WARN R986 2 1 10K_0402_5%
GPU_EDP_BL_EN_R R985 1 2 EDP_BL_EN
0_0402_5% EDP_BL_EN 31 SYS_PEX_RST_MON_N R999 2 @ 1 10K_0402_5%

+3V_GPU GPU_PEX_RST_HOLD_N R1000 2 1 10K_0402_5%


+3V_GPU
NVVDDS_PSI R1002 2 @ 1 10K_0402_5%
C2696 1 2 0.1U_0402_16V7K
C2695 1 2 0.1U_0402_16V7K FRAME_LOCK_N R2271 2 1 10K_0402_5%

U2029
5

U2028 M74VHC1GT08DFT2G_SC-70-5P GC6_FB_EN R660 2 1 10K_0402_5%


5

M74VHC1GT08DFT2G_SC-70-5P
Vcc

VCC=3.3V, VIH>=1.4V 2
Vcc

VCC=3.3V, VIH>=1.4V 2 A 4 GPU_EDP_BL_EN_R


A 4 GPU_EDP_VDD_EN_R GPU_EDP_BL_EN_LS 1 Y
Y B
Gnd

GPU_EDP_VDD_EN_LS 1
B
Gnd

3
3

B B
1

SA000080W00 +3V_GPU +1.8V_AON Q93B


3
1

SA000080W00 R2307
R2304

AO5804EL_SC89-6
R2306 10K_0402_5% AND Gate 5
R2302

100K_0402_5%

10K_0402_5% AND Gate


100K_0402_5%

2
2

1
2

4
2
THERM_ALERT_N 1 6
EC_THERM_ALERT_N 26
GPU Thermal Alert, OD, output
SMB_CLK_GPU 1 6 To EC
EC_SMB_CLK1 19,26,45 Q93A
Q80A AO5804EL_SC89-6
5
AO5804EL_SC89-6

SMB_DATA_GPU 4 3
EC_SMB_DAT1 19,26,45
FRM_LOCK Reserved GPU_EVENT_N_R D52 2 1
GPU_EVENT_N 17
Q80B SDM10U45LP-7_DFN1006-2-2
+3V_EDP AO5804EL_SC89-6 From PCH
R973 1 @ 2 0_0402_5%

GPU_EDP_VDD_EN_LS 1 2 10K_0402_5%
0.1U_0402_16V7K

R781
C888

1
2

R2172 1 2 0_0402_5%
R784
2 PWR_LEVEL_R 2 1
2 PWR_LEVEL 26
10K_0402_5% +1.8V_AON +1.8V_AON D2011
SDM10U45LP-7_DFN1006-2-2 From EC
1

0.1U_0402_16V7K

0.1U_0402_16V7K

FRAME_LOCK_N 6 1 FRAME_LOCK_N_R 2 1
C1333

C1339

FRAME_LOCK_N_R 31 1 1 CHG_PROCHOT_N_R 26,45,74


D2016
OD, input, Active low Frame Lock. Q49A SDM10U45LP-7_DFN1006-2-2 @ From Charger
AO5804EL_SC89-6
2 2
5

A R780 2 @ 1 0_0402_5% From PCH, 3.3V level A


5
Vcc

2 R2171 To GPU, 1.8V level


Vcc

23 DGPU_HOLD_RST_N A 4 2 @ 1SYS_PEX_RST_MON_N2 LENOVO.CRDN


1 Y 0_0402_5% A 4 DGPU_PEX_RST_N
5 17,26,27,38,40,42,43,49,50 PLT_RST_N B Y DGPU_PEX_RST_N 52,68
Gnd

GPU_PEX_RST_HOLD_N 1 Title
B
Gnd

GPU GPIO
U63 @
3

3 4 74AUP1G08GW_SOT353-1 U62 Size Document Number


3

AND Gate 74AUP1G08GW_SOT353-1 R1001 C Rev V0.3


Q49B AND Gate Skylake-H
100K_0402_5%
AO5804EL_SC89-6 Date: Thursday, May 26, 2016 Sheet 63 of 96
"PROPERTY NOTE: this document contains information confidential and
1

property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

MDA[0..63]
53 MDA[0..63]
CMDA[0..31]
53 CMDA[0..31]

DQMA[0..7]
53 DQMA[0..7]
DQSA[0..7]
53 DQSA[0..7]

U48
MIRROR
U2022
NORMAL
MF=0 MF=1 MF=1 MF=0
MF=0 MF=1 MF=1 MF=0
A4 MDA24
D

DQSA3 C2 DQ24 DQ0 A2 MDA25 A4 MDA32


D

DQSA2 C13 EDC0 EDC3 DQ25 DQ1 B4 MDA26 DQSA4 C2 DQ24 DQ0 A2 MDA33
DQSA1 R13 EDC1 EDC2 DQ26 DQ2 B2 MDA27 DQSA5 C13 EDC0 EDC3 DQ25 DQ1 B4 MDA34
DQSA0 R2 EDC2 EDC1 DQ27 DQ3 E4 MDA28 DQSA6 R13 EDC1 EDC2 DQ26 DQ2 B2 MDA35
EDC3 EDC0 DQ28 DQ4 E2 MDA29 DQSA7 R2 EDC2 EDC1 DQ27 DQ3 E4 MDA36
DQ29 DQ5 F4 MDA30 EDC3 EDC0 DQ28 DQ4 E2 MDA37
DQMA3 D2 DQ30 DQ6 F2 MDA31 DQ29 DQ5 F4 MDA38
DQMA2 D13 DBI0# DBI3# DQ31 DQ7 A11 MDA16 DQMA4 D2 DQ30 DQ6 F2 MDA39
DQMA1 P13 DBI1# DBI2# DQ16 DQ8 A13 MDA17 DQMA5 D13 DBI0# DBI3# DQ31 DQ7 A11 MDA40
DQMA0 P2 DBI2# DBI1# DQ17 DQ9 B11 MDA18 DQMA6 P13 DBI1# DBI2# DQ16 DQ8 A13 MDA41
DBI3# DBI0# DQ18 DQ10 B13 MDA19 DQMA7 P2 DBI2# DBI1# DQ17 DQ9 B11 MDA42
CLKA0 R774 2 140.2_0402_1% CLKA0 J12 DQ19 DQ11 E11 MDA20 DBI3# DBI0# DQ18 DQ10 B13 MDA43
53 CLKA0 CLKA0_N CK DQ20 DQ12 DQ19 DQ11
J11 E13 MDA21 CLKA1 R2218 2 1 40.2_0402_1% CLKA1 J12 E11 MDA44
CK# DQ21 DQ13 53 CLKA1 CLKA1_N CK DQ20 DQ12
CMDA1 J3 F11 MDA22 J11 E13 MDA45
CLKA0_N R2219 2 140.2_0402_1% CKE# DQ22 DQ14 F13 MDA23 CMDA17 J3 CK# DQ21 DQ13 F11 MDA46
53 CLKA0_N DQ23 DQ15 CLKA1_N CKE# DQ22 DQ14
CMDA6 J5 U11 MDA8 R2215 2 1 40.2_0402_1% F13 MDA47
A12/A13 DQ8 DQ16 53 CLKA1_N DQ23 DQ15
U13 MDA9 CMDA22 J5 U11 MDA48
CMDA5 K4 DQ9 DQ17 T11 MDA10 A12/A13 DQ8 DQ16 U13 MDA49
1 A8/A7 A10/A0 DQ10 DQ18 DQ9 DQ17
C887 CMDA4 K5 T13 MDA11 1 CMDA25 K4 T11 MDA50
CMDA14 K10 A11/A6 A9/A1 DQ11 DQ19 N11 MDA12 C907 CMDA24 K5 A8/A7 A10/A0 DQ10 DQ18 T13 MDA51
0.01U_0402_25V7K CMDA13 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 MDA13 0.01U_0402_25V7K CMDA27 K10 A11/A6 A9/A1 DQ11 DQ19 N11 MDA52
2 BA2/A4 BA0/A2 DQ13 DQ21 M11 MDA14 CMDA28 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 MDA53
CMDA11 H10 DQ14 DQ22 M13 MDA15 2 BA2/A4 BA0/A2 DQ13 DQ21 M11 MDA54
CMDA12 H11 BA3/A3 BA1/A5 DQ15 DQ23 U4 MDA0 CMDA30 H10 DQ14 DQ22 M13 MDA55
CMDA8 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2 MDA1 CMDA29 H11 BA3/A3 BA1/A5 DQ15 DQ23 U4 MDA56
CMDA9 H4 A9/A1 A11/A6 DQ1 DQ25 T4 MDA2 CMDA20 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2 MDA57
A10/A0 A8/A7 DQ2 DQ26 T2 MDA3 CMDA21 H4 A9/A1 A11/A6 DQ1 DQ25 T4 MDA58
DQ3 DQ27 N4 MDA4 A10/A0 A8/A7 DQ2 DQ26 T2 MDA59
A5 DQ4 DQ28 N2 MDA5 DQ3 DQ27 N4 MDA60
+1.55VSG U5 NC DQ5 DQ29 M4 MDA6 A5 DQ4 DQ28 N2 MDA61
NC DQ6 DQ30 M2 MDA7 U5 NC DQ5 DQ29 M4 MDA62
DQ7 DQ31 NC DQ6 DQ30 M2 MDA63
R874 1 2 1K_0402_1% J1 +1.55VSG DQ7 DQ31
J10 MF R2216 1 2 1K_0402_1% J1 +1.55VSG
2 R2211 1 FBA_ZQ_1_B J13 SEN B1 J10 MF
121_0402_1% ZQ VDDQ D1 2 R826 1 FBA_ZQ_2_B J13 SEN B1
VDDQ F1 121_0402_1% ZQ VDDQ D1
C
CMDA7 J4 VDDQ M1 VDDQ F1 C

CMDA0 G3 ABI# VDDQ P1 CMDA23 J4 VDDQ M1


CMDA10 G12 RAS# CAS# VDDQ T1 CMDA19 G3 ABI# VDDQ P1
CMDA3 L3 CS# WE# VDDQ G2 CMDA31 G12 RAS# CAS# VDDQ T1
CMDA15 L12 CAS# RAS# VDDQ L2 CMDA16 L3 CS# WE# VDDQ G2
WE# CS# VDDQ B3 CMDA26 L12 CAS# RAS# VDDQ L2
VDDQ D3 WE# CS# VDDQ B3
VDDQ F3 VDDQ D3
FBA_WCK23_N D5 VDDQ H3 VDDQ F3
53 FBA_WCK23_N FBA_WCK23 WCK01# WCK23# VDDQ FBA_WCK45_N D5 VDDQ
D4 K3 H3
53 FBA_WCK23 WCK01 WCK23 VDDQ 53 FBA_WCK45_N FBA_WCK45 WCK01# WCK23# VDDQ
M3 D4 K3
FBA_WCK01_N P5 VDDQ 53 FBA_WCK45 WCK01 WCK23 VDDQ
P3 M3
53 FBA_WCK01_N FBA_WCK01 WCK23# WCK01# VDDQ FBA_WCK67_N P5 VDDQ
P4 T3 P3
53 FBA_WCK01 WCK23 WCK01 VDDQ 53 FBA_WCK67_N FBA_WCK67 WCK23# WCK01# VDDQ
E5 P4 T3
VDDQ 53 FBA_WCK67 WCK23 WCK01 VDDQ
N5 E5
A10 VDDQ E10 VDDQ N5
U10 VREFD VDDQ N10 A10 VDDQ E10
2 1 FBA_VREFC J14 VREFD VDDQ B12 U10 VREFD VDDQ N10
C889 820P_0402_50V7K VREFC VDDQ D12 2 1 FBA_VREFC J14 VREFD VDDQ B12
VDDQ F12 C890 820P_0402_50V7K VREFC VDDQ D12
VDDQ H12 VDDQ F12
CMDA2 J2 VDDQ K12 VDDQ H12
RESET# VDDQ M12 CMDA18 J2 VDDQ K12
VDDQ P12 RESET# VDDQ M12
VDDQ T12 VDDQ P12
VDDQ G13 +1.55VSG VDDQ T12
VDDQ VDDQ
VDDQ
L13
B14
For U2022 VDDQ
G13
L13
+1.55VSG VDDQ D14 VDDQ B14
VDDQ F14 +1.55VSG VDDQ D14
VDDQ M14 VDDQ F14

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V
G1 VDDQ P14 VDDQ M14

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
VDD VDDQ 1 1 1 1 1 1 1 1 1 1 1 VDDQ
L1 T14 G1 P14

C2448

C2449

C2450

C2451

C2452

C2453

C2454

C2455

C2456

C2457

C2458
G4 VDD VDDQ L1 VDD VDDQ T14
+1.55VSG L4 VDD G4 VDD VDDQ
C5 VDD A1 2 2 2 2 2 2 2 2 2 2 2 L4 VDD
R5 VDD VSSQ C1 C5 VDD A1
C10 VDD VSSQ E1 R5 VDD VSSQ C1
B
VDD VSSQ VDD VSSQ B
1

R10 N1 C10 E1
R2217 D11 VDD VSSQ R1 R10 VDD VSSQ N1
G11 VDD VSSQ U1 Place near to VRAM Place under VRAM D11 VDD VSSQ R1
549_0402_1% VDD VSSQ VDD VSSQ
L11 H2 G11 U1
P11 VDD VSSQ K2 L11 VDD VSSQ H2
VDD VSSQ VDD VSSQ
2

G14 A3 P11 K2
FBA_VREFC L14 VDD VSSQ C3 G14 VDD VSSQ A3
VDD VSSQ E3 L14 VDD VSSQ C3
VSSQ N3 VDD VSSQ E3
VSSQ VSSQ
1

R3 N3
1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K
R2213 R2212 H1 VSSQ U3 VSSQ R3
VSS VSSQ VSSQ
1

1
K1 C4 H1 U3
C2461

C2462

C2459

C2460

C2465

C2466

C2463

C2464

C2469

C2470

C2467

C2468
931_0402_1% 1.33K_0402_1% VSS VSSQ VSS VSSQ
B5 R4 K1 C4
G5 VSS VSSQ F5 B5 VSS VSSQ R4
VSS VSSQ VSS VSSQ
2

2
L5 M5 G5 F5
T5 VSS VSSQ F10 L5 VSS VSSQ M5
B10 VSS VSSQ M10 T5 VSS VSSQ F10
6 VSS VSSQ VSS VSSQ
D10 C11 B10 M10
AO5804EL_SC89-6

G10 VSS VSSQ R11 D10 VSS VSSQ C11


Q81A L10 VSS VSSQ A12 G10 VSS VSSQ R11
2 P10 VSS VSSQ C12 L10 VSS VSSQ A12
3 VSS VSSQ VSS VSSQ
T10 E12 P10 C12
AO5804EL_SC89-6

H14 VSS VSSQ N12 T10 VSS VSSQ E12


Q81B K14 VSS VSSQ R12 H14 VSS VSSQ N12
1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1 5 VSS170-BALL VSSQ U12 K14 VSS VSSQ R12


63,65,66,67
VRAM_VREF_CTL

VSSQ VSS170-BALL VSSQ


1

H13 U12
C2473

C2474

C2471

C2472

C2475

C2476

VSSQ VSSQ
1

SGRAM GDDR5 K13 H13


R858 VSSQ A14 SGRAM GDDR5 VSSQ K13
VSSQ VSSQ
2

4 C14 A14
100K_0402_5% VSSQ VSSQ
E14 C14
VSSQ N14 VSSQ E14
VSSQ VSSQ
2

R14 N14
VSSQ U14 VSSQ R14
VSSQ Place under VRAM VSSQ U14
K4G41325FC-HC04_FBGA170~D VSSQ
+1.55VSG K4G41325FC-HC04_FBGA170~D
A
For U48 A

LENOVO.CRDN
10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1 1 1 1 1 1 1 1 1 1 1
1

1
Title
C2477

C2478

C2479

C2480

C2481

C2482

C2483

C2485

C2484

C2486

C2487

C2497

C2499

C2496

C2498

C2490

C2491

C2488

C2489

C2493

C2495

C2492

C2494

C2502

C2503

C2500

C2501

C2504

C2505 GPU VRAM A


2

2 2 2 2 2 2 2 2 2 2 2 Size Document Number


C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 64 of 96
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
Place near to VRAM Place under VRAM property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

MDB[0..63]
53 MDB[0..63]
CMDB[0..31]
53 CMDB[0..31]

DQMB[0..7]
53 DQMB[0..7]
DQSB[0..7]
53 DQSB[0..7]

U2023
MIRROR
U55
NORMAL
MF=0 MF=1 MF=1 MF=0
MF=0 MF=1 MF=1 MF=0
A4 MDB24
D
DQSB3 C2 DQ24 DQ0 A2 MDB25 A4 MDB32 D
DQSB2 C13 EDC0 EDC3 DQ25 DQ1 B4 MDB26 DQSB4 C2 DQ24 DQ0 A2 MDB33
DQSB1 R13 EDC1 EDC2 DQ26 DQ2 B2 MDB27 DQSB5 C13 EDC0 EDC3 DQ25 DQ1 B4 MDB34
DQSB0 R2 EDC2 EDC1 DQ27 DQ3 E4 MDB28 DQSB6 R13 EDC1 EDC2 DQ26 DQ2 B2 MDB35
EDC3 EDC0 DQ28 DQ4 E2 MDB29 DQSB7 R2 EDC2 EDC1 DQ27 DQ3 E4 MDB36
DQ29 DQ5 F4 MDB30 EDC3 EDC0 DQ28 DQ4 E2 MDB37
DQMB3 D2 DQ30 DQ6 F2 MDB31 DQ29 DQ5 F4 MDB38
DQMB2 D13 DBI0# DBI3# DQ31 DQ7 A11 MDB16 DQMB4 D2 DQ30 DQ6 F2 MDB39
DQMB1 P13 DBI1# DBI2# DQ16 DQ8 A13 MDB17 DQMB5 D13 DBI0# DBI3# DQ31 DQ7 A11 MDB40
DQMB0 P2 DBI2# DBI1# DQ17 DQ9 B11 MDB18 DQMB6 P13 DBI1# DBI2# DQ16 DQ8 A13 MDB41
DBI3# DBI0# DQ18 DQ10 B13 MDB19 DQMB7 P2 DBI2# DBI1# DQ17 DQ9 B11 MDB42
CLKB0 R2223 2 1 40.2_0402_1% CLKB0 J12 DQ19 DQ11 E11 MDB20 DBI3# DBI0# DQ18 DQ10 B13 MDB43
53 CLKB0 CLKB0_N CK DQ20 DQ12 DQ19 DQ11
J11 E13 MDB21 CLKB1 R2220 2 1 40.2_0402_1% CLKB1 J12 E11 MDB44
CK# DQ21 DQ13 53 CLKB1 CLKB1_N CK DQ20 DQ12
CMDB1 J3 F11 MDB22 J11 E13 MDB45
CLKB0_N R2221 2 1 40.2_0402_1% CKE# DQ22 DQ14 F13 MDB23 CMDB17 J3 CK# DQ21 DQ13 F11 MDB46
53 CLKB0_N DQ23 DQ15 CLKB1_N CKE# DQ22 DQ14
CMDB6 J5 U11 MDB8 R871 2 1 40.2_0402_1% F13 MDB47
A12/A13 DQ8 DQ16 53 CLKB1_N DQ23 DQ15
U13 MDB9 CMDB22 J5 U11 MDB48
CMDB5 K4 DQ9 DQ17 T11 MDB10 A12/A13 DQ8 DQ16 U13 MDB49
1 A8/A7 A10/A0 DQ10 DQ18 DQ9 DQ17
C908 CMDB4 K5 T13 MDB11 1 CMDB25 K4 T11 MDB50
CMDB14 K10 A11/A6 A9/A1 DQ11 DQ19 N11 MDB12 C1326 CMDB24 K5 A8/A7 A10/A0 DQ10 DQ18 T13 MDB51
0.01U_0402_25V7K CMDB13 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 MDB13 CMDB27 K10 A11/A6 A9/A1 DQ11 DQ19 N11 MDB52
2 BA2/A4 BA0/A2 DQ13 DQ21 M11 MDB14 0.01U_0402_25V7K CMDB28 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 MDB53
CMDB11 H10 DQ14 DQ22 M13 MDB15 2 BA2/A4 BA0/A2 DQ13 DQ21 M11 MDB54
CMDB12 H11 BA3/A3 BA1/A5 DQ15 DQ23 U4 MDB0 CMDB30 H10 DQ14 DQ22 M13 MDB55
CMDB8 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2 MDB1 CMDB29 H11 BA3/A3 BA1/A5 DQ15 DQ23 U4 MDB56
CMDB9 H4 A9/A1 A11/A6 DQ1 DQ25 T4 MDB2 CMDB20 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2 MDB57
A10/A0 A8/A7 DQ2 DQ26 T2 MDB3 CMDB21 H4 A9/A1 A11/A6 DQ1 DQ25 T4 MDB58
DQ3 DQ27 N4 MDB4 A10/A0 A8/A7 DQ2 DQ26 T2 MDB59
A5 DQ4 DQ28 N2 MDB5 DQ3 DQ27 N4 MDB60
+1.55VSG U5 NC DQ5 DQ29 M4 MDB6 A5 DQ4 DQ28 N2 MDB61
NC DQ6 DQ30 M2 MDB7 U5 NC DQ5 DQ29 M4 MDB62
DQ7 DQ31 NC DQ6 DQ30 M2 MDB63
R859 1 2 1K_0402_1% J1 +1.55VSG DQ7 DQ31
J10 MF R2222 1 2 1K_0402_1% J1 +1.55VSG
2 R868 1 FBB_ZQ_1_B J13 SEN B1 J10 MF
121_0402_1% ZQ VDDQ D1 2 R869 1 FBB_ZQ_2_B J13 SEN B1
VDDQ F1 121_0402_1% ZQ VDDQ D1
CMDB7 J4 VDDQ M1 VDDQ F1
C C
CMDB0 G3 ABI# VDDQ P1 CMDB23 J4 VDDQ M1
CMDB10 G12 RAS# CAS# VDDQ T1 CMDB19 G3 ABI# VDDQ P1
CMDB3 L3 CS# WE# VDDQ G2 CMDB31 G12 RAS# CAS# VDDQ T1
CMDB15 L12 CAS# RAS# VDDQ L2 CMDB16 L3 CS# WE# VDDQ G2
WE# CS# VDDQ B3 CMDB26 L12 CAS# RAS# VDDQ L2
VDDQ D3 WE# CS# VDDQ B3
VDDQ F3 VDDQ D3
FBB_WCK23_N D5 VDDQ H3 VDDQ F3
53 FBB_WCK23_N FBB_WCK23 WCK01# WCK23# VDDQ FBB_WCK45_N D5 VDDQ
D4 K3 H3
53 FBB_WCK23 WCK01 WCK23 VDDQ 53 FBB_WCK45_N FBB_WCK45 WCK01# WCK23# VDDQ
M3 D4 K3
FBB_WCK01_N P5 VDDQ 53 FBB_WCK45 WCK01 WCK23 VDDQ
P3 M3
53 FBB_WCK01_N FBB_WCK01 WCK23# WCK01# VDDQ FBB_WCK67_N P5 VDDQ
P4 T3 P3
53 FBB_WCK01 WCK23 WCK01 VDDQ 53 FBB_WCK67_N FBB_WCK67 WCK23# WCK01# VDDQ
E5 P4 T3
VDDQ 53 FBB_WCK67 WCK23 WCK01 VDDQ
N5 E5
A10 VDDQ E10 VDDQ N5
U10 VREFD VDDQ N10 A10 VDDQ E10
2 1 FBB_VREFC J14 VREFD VDDQ B12 U10 VREFD VDDQ N10
C909 820P_0402_50V7K VREFC VDDQ D12 2 1 FBB_VREFC J14 VREFD VDDQ B12
VDDQ F12 C910 820P_0402_50V7K VREFC VDDQ D12
VDDQ H12 VDDQ F12
CMDB2 J2 VDDQ K12 VDDQ H12
RESET# VDDQ M12 CMDB18 J2 VDDQ K12
VDDQ P12 RESET# VDDQ M12
VDDQ T12 VDDQ P12
VDDQ G13 +1.55VSG VDDQ T12
VDDQ VDDQ
VDDQ
L13
B14
For U55 VDDQ
G13
L13
+1.55VSG VDDQ D14 VDDQ B14
VDDQ F14 +1.55VSG VDDQ D14
VDDQ M14 VDDQ F14

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V
G1 VDDQ P14 VDDQ M14

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
VDD VDDQ 1 1 1 1 1 1 1 1 1 1 1 VDDQ
L1 T14 G1 P14

C2514

C2515

C2517

C2516

C2518

C2519

C2520

C2521

C2522

C2523

C2524
G4 VDD VDDQ L1 VDD VDDQ T14
+1.55VSG L4 VDD G4 VDD VDDQ
C5 VDD A1 2 2 2 2 2 2 2 2 2 2 2 L4 VDD
R5 VDD VSSQ C1 C5 VDD A1
C10 VDD VSSQ E1 R5 VDD VSSQ C1
B VDD VSSQ VDD VSSQ B
1

R10 N1 C10 E1
R867 D11 VDD VSSQ R1 R10 VDD VSSQ N1
G11 VDD VSSQ U1 Place near to VRAM Place under VRAM D11 VDD VSSQ R1
549_0402_1% VDD VSSQ VDD VSSQ
L11 H2 G11 U1
P11 VDD VSSQ K2 L11 VDD VSSQ H2
VDD VSSQ VDD VSSQ
2

G14 A3 P11 K2
FBB_VREFC L14 VDD VSSQ C3 G14 VDD VSSQ A3
VDD VSSQ E3 L14 VDD VSSQ C3
VSSQ N3 VDD VSSQ E3
VSSQ VSSQ
1

R3 N3
1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K
R866 R865 H1 VSSQ U3 VSSQ R3
VSS VSSQ VSSQ
1

1
K1 C4 H1 U3
C2533

C2534

C2531

C2532

C2509

C2508

C2507

C2506

C2512

C2513

C2510

C2511
931_0402_1% 1.33K_0402_1% VSS VSSQ VSS VSSQ
B5 R4 K1 C4
G5 VSS VSSQ F5 B5 VSS VSSQ R4
VSS VSSQ VSS VSSQ
2

2
L5 M5 G5 F5
T5 VSS VSSQ F10 L5 VSS VSSQ M5
B10 VSS VSSQ M10 T5 VSS VSSQ F10
6 VSS VSSQ VSS VSSQ
D10 C11 B10 M10
AO5804EL_SC89-6

G10 VSS VSSQ R11 D10 VSS VSSQ C11


Q82A L10 VSS VSSQ A12 G10 VSS VSSQ R11
3 VSS VSSQ VSS VSSQ
2 P10 C12 L10 A12
AO5804EL_SC89-6

T10 VSS VSSQ E12 P10 VSS VSSQ C12


Q82B H14 VSS VSSQ N12 T10 VSS VSSQ E12
5 K14 VSS VSSQ R12 H14 VSS VSSQ N12
1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K
1 VSS170-BALL VSSQ U12 K14 VSS VSSQ R12
63,64,66,67
VRAM_VREF_CTL

VSSQ VSS170-BALL VSSQ


1

H13 U12
C2526

C2528

C2525

C2527

C2529

C2530

SGRAM GDDR5 VSSQ K13 VSSQ H13


4 VSSQ A14 SGRAM GDDR5 VSSQ K13
VSSQ VSSQ
2

C14 A14
VSSQ E14 VSSQ C14
VSSQ N14 VSSQ E14
VSSQ R14 VSSQ N14
VSSQ U14 VSSQ R14
VSSQ Place under VRAM VSSQ U14
K4G41325FC-HC04_FBGA170~D VSSQ
K4G41325FC-HC04_FBGA170~D
+1.55VSG
A For U2023 A

LENOVO.CRDN
10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K
Title
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1 1 1 1 1 1 1 1 1 1 1
1

1
GPU VRAM B
C2535

C2536

C2537

C2538

C2539

C2540

C2541

C2543

C2542

C2544

C2545

C2556

C2557

C2554

C2555

C2548

C2549

C2546

C2547

C2551

C2553

C2550

C2552

C2560

C2561

C2558

C2559

C2562

C2563
Size Document Number
2

2 2 2 2 2 2 2 2 2 2 2 2 C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 65 of 96
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
Place near to VRAM Place under VRAM or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

MDC[0..63]
54 MDC[0..63]
CMDC[0..31]
54 CMDC[0..31]

DQMC[0..7]
54 DQMC[0..7]
DQSC[0..7]
54 DQSC[0..7]

U2025
MIRROR
U2024
NORMAL
MF=0 MF=1 MF=1 MF=0
MF=0 MF=1 MF=1 MF=0
A4 MDC24
DQSC3 C2 DQ24 DQ0 A2 MDC25 A4 MDC32
DQSC2 C13 EDC0 EDC3 DQ25 DQ1 B4 MDC26 DQSC4 C2 DQ24 DQ0 A2 MDC33
DQSC1 R13 EDC1 EDC2 DQ26 DQ2 B2 MDC27 DQSC5 C13 EDC0 EDC3 DQ25 DQ1 B4 MDC34
D
DQSC0 R2 EDC2 EDC1 DQ27 DQ3 E4 MDC28 DQSC6 R13 EDC1 EDC2 DQ26 DQ2 B2 MDC35 D
EDC3 EDC0 DQ28 DQ4 E2 MDC29 DQSC7 R2 EDC2 EDC1 DQ27 DQ3 E4 MDC36
DQ29 DQ5 F4 MDC30 EDC3 EDC0 DQ28 DQ4 E2 MDC37
DQMC3 D2 DQ30 DQ6 F2 MDC31 DQ29 DQ5 F4 MDC38
DQMC2 D13 DBI0# DBI3# DQ31 DQ7 A11 MDC16 DQMC4 D2 DQ30 DQ6 F2 MDC39
DQMC1 P13 DBI1# DBI2# DQ16 DQ8 A13 MDC17 DQMC5 D13 DBI0# DBI3# DQ31 DQ7 A11 MDC40
DQMC0 P2 DBI2# DBI1# DQ17 DQ9 B11 MDC18 DQMC6 P13 DBI1# DBI2# DQ16 DQ8 A13 MDC41
DBI3# DBI0# DQ18 DQ10 B13 MDC19 DQMC7 P2 DBI2# DBI1# DQ17 DQ9 B11 MDC42
CLKC0 R2226 2 1 40.2_0402_1% CLKC0 J12 DQ19 DQ11 E11 MDC20 DBI3# DBI0# DQ18 DQ10 B13 MDC43
54 CLKC0 CLKC0_N CK DQ20 DQ12 DQ19 DQ11
J11 E13 MDC21 CLKC1 R903 2 1 40.2_0402_1% CLKC1 J12 E11 MDC44
CK# DQ21 DQ13 54 CLKC1 CLKC1_N CK DQ20 DQ12
CMDC1 J3 F11 MDC22 J11 E13 MDC45
CLKC0_N R2227 2 1 40.2_0402_1% CKE# DQ22 DQ14 F13 MDC23 CMDC17 J3 CK# DQ21 DQ13 F11 MDC46
54 CLKC0_N DQ23 DQ15 CLKC1_N R901 2 CKE# DQ22 DQ14
CMDC6 J5 U11 MDC8 1 40.2_0402_1% F13 MDC47
A12/A13 DQ8 DQ16 54 CLKC1_N DQ23 DQ15
U13 MDC9 CMDC22 J5 U11 MDC48
CMDC5 K4 DQ9 DQ17 T11 MDC10 A12/A13 DQ8 DQ16 U13 MDC49
1 A8/A7 A10/A0 DQ10 DQ18 DQ9 DQ17
C1353 CMDC4 K5 T13 MDC11 1 CMDC25 K4 T11 MDC50
0.01U_0402_25V7K CMDC14 K10 A11/A6 A9/A1 DQ11 DQ19 N11 MDC12 C2425 CMDC24 K5 A8/A7 A10/A0 DQ10 DQ18 T13 MDC51
CMDC13 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 MDC13 0.01U_0402_25V7K CMDC27 K10 A11/A6 A9/A1 DQ11 DQ19 N11 MDC52
2 BA2/A4 BA0/A2 DQ13 DQ21 M11 MDC14 CMDC28 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 MDC53
CMDC11 H10 DQ14 DQ22 M13 MDC15 2 BA2/A4 BA0/A2 DQ13 DQ21 M11 MDC54
CMDC12 H11 BA3/A3 BA1/A5 DQ15 DQ23 U4 MDC0 CMDC30 H10 DQ14 DQ22 M13 MDC55
CMDC8 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2 MDC1 CMDC29 H11 BA3/A3 BA1/A5 DQ15 DQ23 U4 MDC56
CMDC9 H4 A9/A1 A11/A6 DQ1 DQ25 T4 MDC2 CMDC20 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2 MDC57
A10/A0 A8/A7 DQ2 DQ26 T2 MDC3 CMDC21 H4 A9/A1 A11/A6 DQ1 DQ25 T4 MDC58
DQ3 DQ27 N4 MDC4 A10/A0 A8/A7 DQ2 DQ26 T2 MDC59
A5 DQ4 DQ28 N2 MDC5 DQ3 DQ27 N4 MDC60
+1.55VSG U5 NC DQ5 DQ29 M4 MDC6 A5 DQ4 DQ28 N2 MDC61
NC DQ6 DQ30 M2 MDC7 U5 NC DQ5 DQ29 M4 MDC62
DQ7 DQ31 NC DQ6 DQ30 M2 MDC63
R900 1 2 1K_0402_1% J1 +1.55VSG DQ7 DQ31
J10 MF R904 1 2 1K_0402_1% J1 +1.55VSG
2 R898 1 FBC_ZQ_1_B J13 SEN B1 J10 MF
121_0402_1% ZQ VDDQ D1 2 R899 1 FBC_ZQ_2_B J13 SEN B1
VDDQ F1 121_0402_1% ZQ VDDQ D1
CMDC7 J4 VDDQ M1 VDDQ F1
CMDC0 G3 ABI# VDDQ P1 CMDC23 J4 VDDQ M1
CMDC10 G12 RAS# CAS# VDDQ T1 CMDC19 G3 ABI# VDDQ P1
CMDC3 L3 CS# WE# VDDQ G2 CMDC31 G12 RAS# CAS# VDDQ T1
C C
CMDC15 L12 CAS# RAS# VDDQ L2 CMDC16 L3 CS# WE# VDDQ G2
WE# CS# VDDQ B3 CMDC26 L12 CAS# RAS# VDDQ L2
VDDQ D3 WE# CS# VDDQ B3
VDDQ F3 VDDQ D3
FBC_WCK23_N D5 VDDQ H3 VDDQ F3
54 FBC_WCK23_N FBC_WCK23 WCK01# WCK23# VDDQ FBC_WCK45_N D5 VDDQ
D4 K3 H3
54 FBC_WCK23 WCK01 WCK23 VDDQ 54 FBC_WCK45_N FBC_WCK45 WCK01# WCK23# VDDQ
M3 D4 K3
FBC_WCK01_N P5 VDDQ 54 FBC_WCK45 WCK01 WCK23 VDDQ
P3 M3
54 FBC_WCK01_N FBC_WCK01 WCK23# WCK01# VDDQ FBC_WCK67_N P5 VDDQ
P4 T3 P3
54 FBC_WCK01 WCK23 WCK01 VDDQ 54 FBC_WCK67_N FBC_WCK67 WCK23# WCK01# VDDQ
E5 P4 T3
VDDQ 54 FBC_WCK67 WCK23 WCK01 VDDQ
N5 E5
A10 VDDQ E10 VDDQ N5
U10 VREFD VDDQ N10 A10 VDDQ E10
2 1 FBC_VREFC J14 VREFD VDDQ B12 U10 VREFD VDDQ N10
C1354 820P_0402_50V7K VREFC VDDQ D12 2 1 FBC_VREFC J14 VREFD VDDQ B12
VDDQ F12 C1355 820P_0402_50V7K VREFC VDDQ D12
VDDQ H12 VDDQ F12
CMDC2 J2 VDDQ K12 VDDQ H12
RESET# VDDQ M12 CMDC18 J2 VDDQ K12
VDDQ P12 RESET# VDDQ M12
VDDQ T12 VDDQ P12
VDDQ G13 +1.55VSG VDDQ T12
VDDQ VDDQ
VDDQ
L13
B14
For U2024 VDDQ
G13
L13
+1.55VSG VDDQ D14 VDDQ B14
VDDQ F14 +1.55VSG VDDQ D14
VDDQ M14 VDDQ F14

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V
G1 VDDQ P14 VDDQ M14

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
VDD VDDQ 1 1 1 1 1 1 1 1 1 1 1 VDDQ
L1 T14 G1 P14

C2572

C2574

C2576

C2573

C2575

C2578

C2577

C2580

C2579

C2582

C2581
G4 VDD VDDQ L1 VDD VDDQ T14
+1.55VSG L4 VDD G4 VDD VDDQ
C5 VDD A1 2 2 2 2 2 2 2 2 2 2 2 L4 VDD
R5 VDD VSSQ C1 C5 VDD A1
C10 VDD VSSQ E1 R5 VDD VSSQ C1
VDD VSSQ VDD VSSQ
1

R10 N1 C10 E1
R897 D11 VDD VSSQ R1 R10 VDD VSSQ N1
G11 VDD VSSQ U1 Place near to VRAM Place under VRAM D11 VDD VSSQ R1
B
549_0402_1% VDD VSSQ VDD VSSQ B
L11 H2 G11 U1
P11 VDD VSSQ K2 L11 VDD VSSQ H2
VDD VSSQ VDD VSSQ
2

G14 A3 P11 K2
FBC_VREFC L14 VDD VSSQ C3 G14 VDD VSSQ A3
VDD VSSQ E3 L14 VDD VSSQ C3
VSSQ N3 VDD VSSQ E3
VSSQ VSSQ
1

R3 N3
1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K
R2224 R895 H1 VSSQ U3 VSSQ R3
VSS VSSQ VSSQ
1

1
K1 C4 H1 U3
C2590

C2592

C2589

C2591

C2567

C2566

C2565

C2564

C2569

C2571

C2568

C2570
931_0402_1% 1.33K_0402_1% VSS VSSQ VSS VSSQ
B5 R4 K1 C4
G5 VSS VSSQ F5 B5 VSS VSSQ R4
VSS VSSQ VSS VSSQ
2

2
L5 M5 G5 F5
T5 VSS VSSQ F10 L5 VSS VSSQ M5
B10 VSS VSSQ M10 T5 VSS VSSQ F10
6 VSS VSSQ VSS VSSQ
D10 C11 B10 M10
AO5804EL_SC89-6

G10 VSS VSSQ R11 D10 VSS VSSQ C11


Q83A L10 VSS VSSQ A12 G10 VSS VSSQ R11
3 VSS VSSQ VSS VSSQ
2 P10 C12 L10 A12
AO5804EL_SC89-6

T10 VSS VSSQ E12 P10 VSS VSSQ C12


Q83B H14 VSS VSSQ N12 T10 VSS VSSQ E12
5 K14 VSS VSSQ R12 H14 VSS VSSQ N12
1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1 VSS170-BALL VSSQ U12 K14 VSS VSSQ R12


63,64,65,67
VRAM_VREF_CTL

VSSQ VSS170-BALL VSSQ


1

H13 U12
C2585

C2587

C2583

C2584

C2586

C2588

SGRAM GDDR5 VSSQ K13 VSSQ H13


4 VSSQ A14 SGRAM GDDR5 VSSQ K13
VSSQ VSSQ
2

C14 A14
VSSQ E14 VSSQ C14
VSSQ N14 VSSQ E14
VSSQ R14 VSSQ N14
VSSQ U14 VSSQ R14
VSSQ Place under VRAM VSSQ U14
K4G41325FC-HC04_FBGA170~D VSSQ
K4G41325FC-HC04_FBGA170~D

+1.55VSG
For U2025
A A
10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K
LENOVO.CRDN
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1 1 1 1 1 1 1 1 1 1 1
1

1
C2593

C2594

C2595

C2596

C2597

C2598

C2599

C2601

C2600

C2602

C2603

C2614

C2615

C2612

C2613

C2605

C2608

C2604

C2606

C2609

C2611

C2607

C2610

C2618

C2619

C2616

C2617

C2620

C2621 Title
GPU VRAM C
2

2 2 2 2 2 2 2 2 2 2 2
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 66 of 96
Place near to VRAM Place under VRAM "PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

MDD[0..63]
54 MDD[0..63]
CMDD[0..31]
54 CMDD[0..31]

DQMD[0..7]
54 DQMD[0..7]
DQSD[0..7]
54 DQSD[0..7]

U2026
MIRROR
U60
NORMAL
MF=0 MF=1 MF=1 MF=0
MF=0 MF=1 MF=1 MF=0
A4 MDD24
DQSD3 C2 DQ24 DQ0 A2 MDD25 A4 MDD32
DQSD2 C13 EDC0 EDC3 DQ25 DQ1 B4 MDD26 DQSD4 C2 DQ24 DQ0 A2 MDD33
D
DQSD1 R13 EDC1 EDC2 DQ26 DQ2 B2 MDD27 DQSD5 C13 EDC0 EDC3 DQ25 DQ1 B4 MDD34 D
DQSD0 R2 EDC2 EDC1 DQ27 DQ3 E4 MDD28 DQSD6 R13 EDC1 EDC2 DQ26 DQ2 B2 MDD35
EDC3 EDC0 DQ28 DQ4 E2 MDD29 DQSD7 R2 EDC2 EDC1 DQ27 DQ3 E4 MDD36
DQ29 DQ5 F4 MDD30 EDC3 EDC0 DQ28 DQ4 E2 MDD37
DQMD3 D2 DQ30 DQ6 F2 MDD31 DQ29 DQ5 F4 MDD38
DQMD2 D13 DBI0# DBI3# DQ31 DQ7 A11 MDD16 DQMD4 D2 DQ30 DQ6 F2 MDD39
DQMD1 P13 DBI1# DBI2# DQ16 DQ8 A13 MDD17 DQMD5 D13 DBI0# DBI3# DQ31 DQ7 A11 MDD40
DQMD0 P2 DBI2# DBI1# DQ17 DQ9 B11 MDD18 DQMD6 P13 DBI1# DBI2# DQ16 DQ8 A13 MDD41
DBI3# DBI0# DQ18 DQ10 B13 MDD19 DQMD7 P2 DBI2# DBI1# DQ17 DQ9 B11 MDD42
CLKD0 R785 2 1 40.2_0402_1% CLKD0 J12 DQ19 DQ11 E11 MDD20 DBI3# DBI0# DQ18 DQ10 B13 MDD43
54 CLKD0 CLKD0_N CK DQ20 DQ12 DQ19 DQ11
J11 E13 MDD21 CLKD1 R916 2 1 40.2_0402_1% CLKD1 J12 E11 MDD44
CK# DQ21 DQ13 54 CLKD1 CLKD1_N CK DQ20 DQ12
CMDD1 J3 F11 MDD22 J11 E13 MDD45
CLKD0_N R906 2 1 40.2_0402_1% CKE# DQ22 DQ14 F13 MDD23 CMDD17 J3 CK# DQ21 DQ13 F11 MDD46
54 CLKD0_N DQ23 DQ15 CLKD1_N R914 2 CKE# DQ22 DQ14
CMDD6 J5 U11 MDD8 1 40.2_0402_1% F13 MDD47
A12/A13 DQ8 DQ16 54 CLKD1_N DQ23 DQ15
U13 MDD9 CMDD22 J5 U11 MDD48
CMDD5 K4 DQ9 DQ17 T11 MDD10 A12/A13 DQ8 DQ16 U13 MDD49
1 A8/A7 A10/A0 DQ10 DQ18 DQ9 DQ17
C1373 CMDD4 K5 T13 MDD11 1 CMDD25 K4 T11 MDD50
0.01U_0402_25V7K CMDD14 K10 A11/A6 A9/A1 DQ11 DQ19 N11 MDD12 C2439 CMDD24 K5 A8/A7 A10/A0 DQ10 DQ18 T13 MDD51
CMDD13 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 MDD13 0.01U_0402_25V7K CMDD27 K10 A11/A6 A9/A1 DQ11 DQ19 N11 MDD52
2 BA2/A4 BA0/A2 DQ13 DQ21 M11 MDD14 CMDD28 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 MDD53
CMDD11 H10 DQ14 DQ22 M13 MDD15 2 BA2/A4 BA0/A2 DQ13 DQ21 M11 MDD54
CMDD12 H11 BA3/A3 BA1/A5 DQ15 DQ23 U4 MDD0 CMDD30 H10 DQ14 DQ22 M13 MDD55
CMDD8 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2 MDD1 CMDD29 H11 BA3/A3 BA1/A5 DQ15 DQ23 U4 MDD56
CMDD9 H4 A9/A1 A11/A6 DQ1 DQ25 T4 MDD2 CMDD20 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2 MDD57
A10/A0 A8/A7 DQ2 DQ26 T2 MDD3 CMDD21 H4 A9/A1 A11/A6 DQ1 DQ25 T4 MDD58
DQ3 DQ27 N4 MDD4 A10/A0 A8/A7 DQ2 DQ26 T2 MDD59
A5 DQ4 DQ28 N2 MDD5 DQ3 DQ27 N4 MDD60
+1.55VSG U5 NC DQ5 DQ29 M4 MDD6 A5 DQ4 DQ28 N2 MDD61
NC DQ6 DQ30 M2 MDD7 U5 NC DQ5 DQ29 M4 MDD62
DQ7 DQ31 NC DQ6 DQ30 M2 MDD63
R913 1 2 1K_0402_1% J1 +1.55VSG DQ7 DQ31
J10 MF R2228 1 2 1K_0402_1% J1 +1.55VSG
2 R911 1 FBD_ZQ_1_B J13 SEN B1 J10 MF
121_0402_1% ZQ VDDQ D1 2 R912 1 FBD_ZQ_2_B J13 SEN B1
VDDQ F1 121_0402_1% ZQ VDDQ D1
CMDD7 J4 VDDQ M1 VDDQ F1
CMDD0 G3 ABI# VDDQ P1 CMDD23 J4 VDDQ M1
CMDD10 G12 RAS# CAS# VDDQ T1 CMDD19 G3 ABI# VDDQ P1
C C
CMDD3 L3 CS# WE# VDDQ G2 CMDD31 G12 RAS# CAS# VDDQ T1
CMDD15 L12 CAS# RAS# VDDQ L2 CMDD16 L3 CS# WE# VDDQ G2
WE# CS# VDDQ B3 CMDD26 L12 CAS# RAS# VDDQ L2
VDDQ D3 WE# CS# VDDQ B3
VDDQ F3 VDDQ D3
FBD_WCK23_N D5 VDDQ H3 VDDQ F3
54 FBD_WCK23_N FBD_WCK23 WCK01# WCK23# VDDQ FBD_WCK45_N D5 VDDQ
D4 K3 H3
54 FBD_WCK23 WCK01 WCK23 VDDQ 54 FBD_WCK45_N FBD_WCK45 WCK01# WCK23# VDDQ
M3 D4 K3
FBD_WCK01_N P5 VDDQ 54 FBD_WCK45 WCK01 WCK23 VDDQ
P3 M3
54 FBD_WCK01_N FBD_WCK01 WCK23# WCK01# VDDQ FBD_WCK67_N P5 VDDQ
P4 T3 P3
54 FBD_WCK01 WCK23 WCK01 VDDQ 54 FBD_WCK67_N FBD_WCK67 WCK23# WCK01# VDDQ
E5 P4 T3
VDDQ 54 FBD_WCK67 WCK23 WCK01 VDDQ
N5 E5
A10 VDDQ E10 VDDQ N5
U10 VREFD VDDQ N10 A10 VDDQ E10
2 1 FBD_VREFC J14 VREFD VDDQ B12 U10 VREFD VDDQ N10
C1374 820P_0402_50V7K VREFC VDDQ D12 2 1 FBD_VREFC J14 VREFD VDDQ B12
VDDQ F12 C1375 820P_0402_50V7K VREFC VDDQ D12
VDDQ H12 VDDQ F12
CMDD2 J2 VDDQ K12 VDDQ H12
RESET# VDDQ M12 CMDD18 J2 VDDQ K12
VDDQ P12 RESET# VDDQ M12
VDDQ T12 VDDQ P12
VDDQ G13 +1.55VSG VDDQ T12
VDDQ VDDQ
VDDQ
L13
B14
For U60 VDDQ
G13
L13
+1.55VSG VDDQ D14 VDDQ B14
VDDQ F14 +1.55VSG VDDQ D14
VDDQ M14 VDDQ F14

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V
G1 VDDQ P14 VDDQ M14

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
VDD VDDQ 1 1 1 1 1 1 1 1 1 1 1 VDDQ
L1 T14 G1 P14

C2630

C2632

C2634

C2631

C2633

C2636

C2635

C2638

C2637

C2640

C2639
G4 VDD VDDQ L1 VDD VDDQ T14
+1.55VSG L4 VDD G4 VDD VDDQ
C5 VDD A1 2 2 2 2 2 2 2 2 2 2 2 L4 VDD
R5 VDD VSSQ C1 C5 VDD A1
C10 VDD VSSQ E1 R5 VDD VSSQ C1
VDD VSSQ VDD VSSQ
1

R10 N1 C10 E1
R910 D11 VDD VSSQ R1 R10 VDD VSSQ N1
B
G11 VDD VSSQ U1 Place near to VRAM Place under VRAM D11 VDD VSSQ R1 B
549_0402_1% VDD VSSQ VDD VSSQ
L11 H2 G11 U1
P11 VDD VSSQ K2 L11 VDD VSSQ H2
VDD VSSQ VDD VSSQ
2

G14 A3 P11 K2
FBD_VREFC L14 VDD VSSQ C3 G14 VDD VSSQ A3
VDD VSSQ E3 L14 VDD VSSQ C3
VSSQ N3 VDD VSSQ E3
VSSQ VSSQ
1

R3 N3
1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K
R909 R908 H1 VSSQ U3 VSSQ R3
VSS VSSQ VSSQ
1

1
K1 C4 H1 U3
C2648

C2650

C2647

C2649

C2625

C2624

C2623

C2622

C2628

C2629

C2626

C2627
931_0402_1% 1.33K_0402_1% VSS VSSQ VSS VSSQ
B5 R4 K1 C4
G5 VSS VSSQ F5 B5 VSS VSSQ R4
VSS VSSQ VSS VSSQ
2

2
L5 M5 G5 F5
T5 VSS VSSQ F10 L5 VSS VSSQ M5
B10 VSS VSSQ M10 T5 VSS VSSQ F10
6 VSS VSSQ VSS VSSQ
D10 C11 B10 M10
AO5804EL_SC89-6

G10 VSS VSSQ R11 D10 VSS VSSQ C11


Q84A L10 VSS VSSQ A12 G10 VSS VSSQ R11
3 VSS VSSQ VSS VSSQ
2 P10 C12 L10 A12
AO5804EL_SC89-6

T10 VSS VSSQ E12 P10 VSS VSSQ C12


Q84B H14 VSS VSSQ N12 T10 VSS VSSQ E12
5 K14 VSS VSSQ R12 H14 VSS VSSQ N12
1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K
1 VSS170-BALL VSSQ U12 K14 VSS VSSQ R12
63,64,65,66
VRAM_VREF_CTL

VSSQ VSS170-BALL VSSQ


1

H13 U12
C2642

C2644

C2641

C2643

C2645

C2646

SGRAM GDDR5 VSSQ K13 VSSQ H13


4 VSSQ A14 SGRAM GDDR5 VSSQ K13
VSSQ VSSQ
2

C14 A14
VSSQ E14 VSSQ C14
VSSQ N14 VSSQ E14
VSSQ R14 VSSQ N14
VSSQ U14 VSSQ R14
VSSQ Place under VRAM VSSQ U14
K4G41325FC-HC04_FBGA170~D VSSQ
K4G41325FC-HC04_FBGA170~D
+1.55VSG
For U20256
A A
10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

10U_0603_10V

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K

1U_0402_6.3V7K
LENOVO.CRDN
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1 1 1 1 1 1 1 1 1 1 1
1

1
C2651

C2652

C2654

C2653

C2656

C2655

C2658

C2660

C2657

C2659

C2661

C2672

C2674

C2670

C2671

C2664

C2665

C2662

C2663

C2668

C2669

C2666

C2667

C2677

C2676

C2673

C2675

C2679

C2678
Title
GPU VRAM D
2

2
2 2 2 2 2 2 2 2 2 2 2
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 67 of 96
Place near to VRAM Place under VRAM "PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

+3V

+1.8V_SW +1.8V_AON
PU8

1
Need confirm the sequence with NV PR3549
+3V R2185
10K_0402_5% To enable NVVDD A2
VIN VOUT
A1 1 2 0_0603_5%

1
1.8V_MAIN_EN_LS PC3567
1.8V_MAIN_EN_LS 69,80

2
1
DGPU_AON_EN 2A

0.1U_0402_25V6
R2184 69 DGPU_AON_EN
3

2
10K_0402_5% DGPU_PWR_EN 1 PR2187 210K_0402_5% B2 B1
Q85B VIH > 1.1V ON GND

1
AO5804EL_SC89-6 PC3566

2
5

1U_0402_6.3V7K
6 TPS22913CYZVR

2
Q85A
D 4 D
AO5804EL_SC89-6
1.8V_MAIN_EN 1 R2186 2 2
63,68,69 1.8V_MAIN_EN
1U_0402_16V6K +5V +1.8V_MAIN
0_0402_5% PC3579

0.1U_0402_16V7K
2 1 PU1607

C2221
1 1 @
@ 1 4 PJ1506
1.8V_MAIN_EN PR38 1 2 2 VDD S 2200P_0402_50V7K
2 ON

1
VIH > 0.85V 0_0402_5% 2 1PC3577 PC12
4A CAP 5 2 1PC3578

0.1U_0402_25V6
+3V +1.8V_SW 3
D

2
6 2200P_0402_50V7K
GND

0.1U_0402_25V6
1
@

PC13
+3V R2187 SLG59M301VTR_FC-TDFN8-6_1P5X2

2
10K_0402_5%
GC6_FB_EN_LS
GC6_FB_EN_LS 17

2
1

R2188 3
10K_0402_5%
Q86B +3V_GPU
AO5804EL_SC89-6 +1.8V_AON +3V
2

5
PU7 PR39
6

1
Q86A R2183 A2 A1 1 2 0_0603_5%
4 VIN VOUT
AO5804EL_SC89-6 10K_0402_5%

1
GC6_FB_EN 1 R2189 2 2 PC14
63 GC6_FB_EN
2A

1U_0402_6.3V7K
2
0_0402_5% VIH > 1.1V
0.1U_0402_16V7K

2
+1.8V_SW_PGOOD B2 B1
C2222

1 1 ON GND

0.1U_0402_25V6
1
@

PC15
D2007
2 DGPU_PWR_EN 1 2
23,69 DGPU_PWR_EN TPS22913CYZVR

2
C C

SDM10U45LP-7_DFN1006-2-2
+3V_GPU power on after +1.8V_AON;
+3V_GPU power off before +1.8V_AON

R2244 +3V_GPU
1 2 +3V_GPU
NVVDD power ok
10K_0402_5% To open NVVDDS and PEX_DVDD 68,87 NVVDDS_PWROK
1 2

2
DGPU_PWROK 1 2 NVVDDS_PEX_EN D71
17,52,68,80 DGPU_PWROK NVVDDS_PEX_EN 69,79,87
D2009 SDM10U45LP-7_DFN1006-2-2 R1006
SDM10U45LP-7_DFN1006-2-2 10K_0402_5%
DGPU_PWR_EN 1 2 1 2
17,52,68,80 DGPU_PWROK

1
D2010 D69
SDM10U45LP-7_DFN1006-2-2
SDM10U45LP-7_DFN1006-2-2

1 2
GC6_FB_EN_LS 1.55V_PWR_EN 68,79 +1.05V_DGPU_PGOOD
2 1 D70
D2012 1.55V_PWR_EN 69,79 SDM10U45LP-7_DFN1006-2-2
SDM10U45LP-7_DFN1006-2-2 To PCH GPIO
2 @ 1
68,79 +1.05V_DGPU_PGOOD
1

D51 R1007 1 2 0_0402_5% GPU_ALL_PGOOD


79 +1.55V_DGPU_PGOOD GPU_ALL_PGOOD 23
SDM10U45LP-7_DFN1006-2-2 R809
2 1 100K_0402_5%
68,87 NVVDDS_PWROK
D2017
SDM10U45LP-7_DFN1006-2-2
2

+3V_GPU
B B
NVVDD/NVVDDS POWER GOOD LOOPBACK
1

PR22
0_0402_5%
PU5
PC9 DGPU_PEX_RST_N
52,63 DGPU_PEX_RST_N H_THRMTRIP_N 6,20,63
0.1U_0402_25V6
2

10_0402_1% 1 2 PR29 12 4 2 1
79 B+_GPU_ALLP IN+1 VS
1

1
665K_0402_1%1 2 PC10 6 I2CC_SCL
SCL I2CC_SCL 63,80
FROM PR701,GPU ALL PR3553 R2261
10U_0603_10V 7 I2CC_SDA 10K_0402_5% 6
SDA I2CC_SDA 63,80
2

10_0402_1% 1 2 PR26 11 PR28 1 2 I2CC_SDA


79 B+_GPU_ALLN IN-1 10K_0402_5% @ PR23

0.1U_0402_16V7K
2
10_0402_1% 1 2 PR24 15 1 2 10K_0402_5% PR34 0_0402_5% SDM10U45LP-7_DFN1006-2-2

@ C2683
81 B+_GPU_COREP IN+2 +3V_GPU 1
5 1 @ 2 D2013 NVVDDS_PWROK_N 2
AO
1

665K_0402_1%1 2 PC11 DGPU_PWROK 1 2 AO5804EL_SC89-6


FROM PR901,+VGA_CORE PR3554 10 PS1_NVVDD_EN PR30 1 2 0_0402_5% Q98A
10U_0603_10V PV @ 1.8V_MAIN_EN 63,68,69 2
6
2

10_0402_1% 1 2 PR36 14 13 R2263 1 @ 2 0_0402_5% 1


81 B+_GPU_COREN IN-2 TC
10_0402_1% 1 2 PR3568 2 16
87 B+_NVVDDSP IN+3 VPU NVVDDS_PWROK 2 Q97A
1

665K_0402_1%1 2 PC3580
FROM PR3552,+NVVDDS PR3555 AO5804EL_SC89-6
10U_0603_10V
2

10_0402_1% 1 2 PR3569 1 1
87 B+_NVVDDSN IN-3 3
3
8 3 Q98B
WARN GND R2262 AO5804EL_SC89-6
9 17 GC6_FB_EN_LS 2 1 5
+1.8V_AON +1.8V_AON CRIT PAD 0_0402_5% AO5804EL_SC89-6 5

0.1U_0402_16V7K
Q97B

@ C2682
1
4
2

@
PR27 PR32 INA3221AIRGVR_QFN16_4X4 4
2
10K_0402_1% 10K_0402_1%
A I2C Address(0X84) A
1

PWR_SRC_WARN_N @
LENOVO.CRDN
PWR_SRC_CRTCAL_N Title
GPU Switch/Thermal
Size Document Number
PWR_SRC_WARN_N PR31 1 2 0_0402_5% C Rev V0.3
OC_WARN 63 Skylake-H
PWR_SRC_CRTCAL_N PR35 1 2 0_0402_5% Date: Thursday, May 26, 2016 Sheet 68 of 96
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
PR25 1 @ 2 0_0402_5% GPU_OVERT_N property to LENOVO PND and shall not be reproduced or transferred to other documents
GPU_OVERT_N 63 or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

D D

+NVVDDS
+PEX_VDD
3
+5VALW Q89B
+3V_GPU AO5804EL_SC89-6

2
+5VALW
R1008 5 R1011

1
220_0402_5% 220_0402_5%

2
R1010
R2270 100K_0402_5%

1
4

1
220_0402_5% 3 6
R2260 Q92B Q89A

2
100K_0402_5% AO5804EL_SC89-6 AO5804EL_SC89-6

1
3
Q94B NVVDDS_PEX_EN_N5 NVVDDS_PEX_EN_N 2

2
AO5804EL_SC89-6

+3V_GPU_EN_N 5
4 1
6 6
Q94A Q92A
AO5804EL_SC89-6 AO5804EL_SC89-6
4
DGPU_PWR_EN 1 R2259 2 0_0402_5%
2 NVVDDS_PEX_EN R1009 1 2 0_0402_5% 2

0.1U_0402_16V7K
23,68 DGPU_PWR_EN 68,79,87 NVVDDS_PEX_EN

@ C1341
0.1U_0402_16V7K 1
@ C2680

1 1 1
2

C C
+VGA_CORE
+1.8V_AON +5VALW
+5VALW

2
2
R1012

1
R2264 220_0402_5%
1

220_0402_5% R1014
R2265 100K_0402_5%

1
100K_0402_5% 3
1

3 Q90B

2
Q100B AO5804EL_SC89-6
2

AO5804EL_SC89-6
1.8V_MAIN_EN_LS_N 5
DGPU_AON_EN_N 5 6
6 Q90A
Q100A AO5804EL_SC89-6
AO5804EL_SC89-6 4
4 1.8V_MAIN_EN_LS 1 R1013 2 0_0402_5%
2
DGPU_AON_EN 68,80 1.8V_MAIN_EN_LS
1 R2266 2 0_0402_5%
2
68 DGPU_AON_EN

0.1U_0402_16V7K
@ C1342
0.1U_0402_16V7K

1 1
@ C2685

1 1

2
2

+1.8V_MAIN +5VALW +1.55VSG


+5VALW
B B

2
2

R972

1
R2267 100_0402_5%
1

220_0402_5% R810
R2268 100K_0402_5%

1
100K_0402_5% 3
1

3 Q91B

2
Q101B AO5804EL_SC89-6
2

AO5804EL_SC89-6
1.55V_PWR_EN_N 5
1.8V_MAIN_EN_N 5
6 6
Q101A
AO5804EL_SC89-6 4
4
1.8V_MAIN_EN 1 R2269 2 0_0402_5%
2 1.55V_PWR_EN R813 1 2 0_0402_5% 2
63,68 1.8V_MAIN_EN 68,79 1.55V_PWR_EN
AO5804EL_SC89-6
Q91A

@ C1338
0.1U_0402_16V7K

1
@ C2686

0.1U_0402_16V7K
1 1 1

2
2

A A

LENOVO.CRDN
Title
BLANK
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 69 of 99
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

LENOVO.CRDN
Title
BLANK
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 70 of 99
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

LENOVO.CRDN
Title
BLANK
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 71 of 99
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

LENOVO.CRDN
Title
BLANK
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 72 of 99
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

D D

BATT CONN.
JDCIN1 ADIN_1
BAT_R
1 PF102 VBAT PF101
1 2 25A_24V_F1206HB25V024T / M PL103 PL101 25A_24V_F1206HB25V024T / M
2 3 C8BBPH403025-1TAPING_2P C8BBPH403025-1TAPING_2P
3 4 APDIN 1 2 1 2 1 2 1 2
10 4
11 GND 5 ADAPTER_ID PL104 PL102

1000P_0402_50V7K
GND 5 C8BBPH403025-1TAPING_2P PC101 C8BBPH403025-1TAPING_2P

470P_0402_50V7K

470P_0402_50V7K
2

1
6 1 2 1 2

PC103
1000P_0402_50V7K

1000P_0402_50V7K
6 7

0.1U_0402_25V7K
PC102
7 1

1
8 47P_0402_50V8J JBAT1

PC104

PC105

PC106

PC107
8

2
9 1
9 1
1
2

2
2
3 2
ACES_50458-00901-001 4 3
ME@ 4 13
PR101 1 2 100_0402_5% BATT_SMB_CLK 5 GND 14
26,40,51,74 EC_SMB_CLK0 5 GND
26,40,51,74 EC_SMB_DAT0 PR102 1 2 100_0402_5% BATT_SMB_DAT 6 15
6 GND 16
MBAT_PRES_N_R 7 GND
+3VLP 8 7
C C
8
9
9

1
10
PR103 11 10
12 11
100K_0402_1% 12

2
26,51,74 MBAT_PRES_N PR104 1 2 100_0402_5% SUYIN_125022HB012M200ZL_12P

ME@

+3VALW ADIN_1
1

PR105 PR106
750_0603_1% 1M_0402_5%
2

2
2

PR107 D PQ101A
0_0402_5% 2
G
@
1

B S 2N7002KDWH_SOT363-6 B
1

26 ADAPTER_ID D
PR108 5
1M_0402_5% G EC_ADP_ID_ON_N 26
0.1U_0402_25V7K

S PQ101B
2

4
1

2N7002KDWH_SOT363-6
PC108

1
2

PD101
AZ5123-01F_DFN1006P2X
2
2

A A

LENOVO.CRDN
Title
DCIN/BATT
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 73 of 99
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

V_PATH

B+

ADIN_1 PQ201 PQ202 PQ203


AON6404A_DFN8-5 AON6404A_DFN8-5 AON6404A_DFN8-5
2W 0.005 +-1% 1206_LE 70PPM

1 1 PR201 1
2 2 0.005_1206_LE_1% 2
5 3 3 5 1 2 5 3

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
2

2
2.2_0805_5%

4
1

1
PQ205 PR233 PR232
PC203
AON6404A_DFN8-5
PR116

PC226

PC225

PC227
D
0_0603_5% 2.2_0603_5% D
1 2

2
1

1
1 PR235 0.1U_0402_25V7K
PC224
2

2
2 0_0402_5% @
5 3 1 2
10U_0805_25V6K
1

2
PC128

0.1U_0603_25V7K PR231

1
PC205 0_0402_5%
2

1
PC206
PC201 0.1U_0603_25V7K 0.1U_0603_25V7K

1
2

2
2200P_0402_50V7K @ @

1
@ PR237 PC202 PR236
1 0_0603_5% 0_0402_5% V_PATH BGATE
1

PR203 @ PR205

0.1U_0402_25V7K
2
100_0603_5%

4.02K_0603_1%
1

1
120K_0402_1% 2 1 VBAT

PR204
2

ACDET PQ204 VBAT

0.22U_0402_10V6K
2

1
@ 2W 0.005 +-1% 1206_LE 70PPM
1

1
2.633V/17.5V PC231 9
16A

VIN1
GND

1
PC207
4.02K_0603_1%

ASGATE
1

BGATE
PR206 0.1U_0402_25V7K CHG_DH_R 3 8 PR207
PR202

TG VSW3

2
1

20K_0402_1% PL201 0.005_1206_LE_1%

2
PC223 4 7 CHG_PAHSE 1 2 1 2
TGR VSW2
2

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
0.01U_0402_25V7K
2

1
PR209 5 6 3.3UH_PCMB104T-3R3MS_10A_20%
BG VSW1
2

1
PU201 2.2_0603_5%

32

31

30

29

28

27

26

25

PC208

PC209

PC210

PC228

PC211

PC229
PR210 PC212
ASGATE

CSD87350Q5D

CSIP

ASGATE

QPCP

BGATE
VBAT
CSIN

CMSRC

QPCN

2
0_0603_5% 0.22U_0402_10V6K

2
ACDET 1 24 1 2 1 2
ACIN BOOT PR211 PR212
OD 2 23 CHG_DH 2.2_0603_5% 0_0603_5%
26 ACOK ACOK UGATE
26,40,51,73 EC_SMB_DAT0 PR227 1 2 100_0402_5% CHG_SMB_DAT 3 22 CHG_TGR
SDA PHASE

1
C C
26,40,51,73 EC_SMB_CLK0 PR228 1 2 100_0402_5% CHG_SMB_CLK 4 21 CHG_DL
SCL ISL95521AHRTZ_TQFN32_4X4 LGATE
PR229 1 2 100_0402_5% CHG_PROCHOT_N OD 5 20 PR214 REGN
26,45,63 CHG_PROCHOT_N_R PROCHOT# VDDP 4.7_0603_5% PC213
PR213 1 2 0_0402_5% 6 19 1 2
26 AMON AMON VDD 1 2

1
PR215 1 2 0_0402_5% 7 18
26 BMON BMON DCIN PC214 PC215 0.1U_0402_25V7K

1
PR216 1 2 0_0402_5% 8 17 1U_0603_25V6M 1U_0603_25V6M PC216
26,83 PSYS PSYS NTC

2
PC217

BATGONE
0.1U_0402_25V7K 0.1U_0402_25V7K
2200P_0402_50V7K

2200P_0402_50V7K

2.67K_0402_1%
CCLIM

2
ACLIM
COMP
1

2
PROG

CSON

CSOP
33

FSET
GND
2

@ @
PC218

PC219

PR217
PR218 PD201
PR226

220K_0402_1%_TSM0A224F4051RZ
20K_0402_1% 1 2 1 2 ADIN_1
1

10

11

12

13

14

15

16
@

100K_0402_1%
2

1
4.7_0805_1%
RB751V-40_SOD323-2

1
100K_0402_1%
PD202

2
PC220
182K_0402_1%
2

2
PR220 1U_0603_25V6M 1 2 VBAT

2
2
PR219

PH201
RB751V-40_SOD323-2
1
1

1
PR208
1

26,51,73 MBAT_PRES_N

REGN REGN
B B
HW CC LIMIT seting to 11A
499_0402_1%

HW AC LIMIT seting to 11A


2
PR221

FSW=618KHZ
560P_0402_50V7-K

AC:230W/20V/11.5A
180K_0402_1%

180K_0402_1%
2

2
PC221

DC:90Wh/150W/16A
1

PR222

PR223
0.012U_0402_16V7K

1
2
PC222

1
1

100K_0402_1%

100K_0402_1%
2

2
PR224

PR225
1

A A

LENOVO.CRDN
Title
PWR Trubo charger ISL95520
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 74 of 99
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

PJ301
PR301 2 1
13K_0402_1% +3VALWP 2 1 +3VALW
1 2 @ JUMP_43X118

D D
PJ302
2 1
+5VALWP 2 1 +5VALW
+3VLP PR302 @ JUMP_43X118
30.9K_0402_1%
PR303 2 1
20K_0402_1%
1 2 PR305

1U_0603_6.3V7K
2
20K_0402_1%

1
1 2

PC303
PR304
0_0603_5%

2
1

2
ALW_B+

2
PR307
PR306 26.1K_0402_1%
26.1K_0402_1%
FB_3V FB_5V
ALW_B+

1
+3VLP

1
PJ303

2 1 PU301

47P_0402_50V8J

10U_0805_25V6K

10U_0805_25V6K
B+ 2 1

1
0.1U_0603_25V7K

1
@ JUMP_43X118 PR355

PC301

PC304

PC305
10U_0805_25V6K

10U_0805_25V6K

CS2

VFB2

VREG3

VFB1

CS1
21
PC307

10K_0402_5% PAD
1

3V5V_EN 6
PC308

PC306

EN2 2

2
14
VO1

1
2

C 7 C
41 5VALW_PG PGOOD 19
VCLK
PQ301 UG_3V 10 TPS51225CRUKR_QFN20_3X3
DRVH2
1

PC310 PR309 16 UG_5V PQ302


+3VALWP DRVH1 +5VALWP

1
9 0.1U_0603_25V7K 2.2_0603_5% PR308 PC309
VIN1

GND 1 2 1 2 BST_3V 9 2.2_0603_5% 0.1U_0603_25V7K 9

VIN1
8 3 VBST2 17 BST_5V 1 2 1 2 GND
PL301 VSW3 TG VBST1 3 8 10A
10A 1 2 SW2_3V 7
VSW2 TGR
4 TGR_3V 8
SW2
TG VSW3 PL302
18 TGR_5V 4 7 SW1_5V 1 2

VREG5
DRVL2

DRVL1
2.2UH_PCMC065T-2R2MN_11A_20% 6 5 SW1 TGR VSW2
VSW1 BG

EN1
VIN
5 6 2.2UH_PCMC065T-2R2MN_11A_20%
BG VSW1
1
4.7_1206_5%

CSD87350Q5D

11

12

13

20

15
PC321 1 PC320 1 PC319 1 PC318 1 PC312 1 PC322 1
PR310

CSD87350Q5D

1
LG_3V LG_5V

4.7_1206_5%
+ + + + + +

3V5V_EN
220U_B2_6.3VM_R35M

220U_B2_6.3VM_R35M

220U_B2_6.3VM_R35M

220U_B2_6.3VM_R35M

220U_B2_6.3VM_R35M

220U_B2_6.3VM_R35M
PR311
1 SNUB_3V 2

2 2 2 PR315 2 2 2

2
0_0603_5%
1 2
ALW_B+

1SNUB_5V
680P_0603_50V7K

1U_0603_6.3V7K
0.1U_0603_25V7K

2
PC313

680P_0603_50V7K
1

1
PR312

PC315

PC316

PC314
0_0603_5%
2

2
@ @

2
B B

OCP 18A
+5VLDO
PR313 OCP 18A
0_0402_5%
1 2 3V5V_EN
26,41,77,92 EC_ON
1
1

PR314
PC317
0.1U_0402_25V7K 1M_0402_5%
2

@
2

LENOVO.CRDN
A A
Title
PWR 3VALW/5VALW
Size Document Number
Custom Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 75 of 99
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

3A 1.2V_B+ 2
2 1
1
B+

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V7K
1
PR401 PC401 PJ401

PC402

1
PC403 2.2_0603_5% 0.1U_0603_25V7-M JUMP_43X79

PC404

PC405

PC418

PC417
10U_0603_6.3V6M +1.2V_BST 1 2 2 1 TGR_1.2V @

2
1 2

2
@
2A 20A

+1.2VDDQ
PR402 0_0402_5%
+1.2V_UG 2 1 +1.2V_UGR
+0.6VSP @ @ PJ402
JUMP_43X118
TGR_1.2V PQ401

22U_0805_6.3V6M

22U_0805_6.3V6M

1
2 1
2 1

1
9 @ +1.2V_VDDQ

PC406

PC407

VIN1
GND
+1.2VDDQ

20

19

18

17

16
3 8 PL401 PJ403
TG VSW3

2
0.47UH_PCMC065T-R47MN_20A_20% JUMP_43X118

UGATE

PHASE
VTT

BOOT
VLDOIN
D LX_1.2V D
@ 21 4 7 1 2 2 1
PAD TGR VSW2 2 1
1 15 +1.2V_LG 5 6 @
VTTGND LGATE BG VSW1

330U_B2_2VM_R15M

330U_B2_2VM_R15M
PR403 1 1
2 14 2.2_0805_5%
VTTSNS PGND CSD87350Q5D + +
PR404 @

PC408

PC409
PU401 95.3K_0402_1%

2
3 13 1 2

1.2V_SN
GND RT8231AGQW_WQFN20_3X3 CS PR405 2 2
5.1_0603_5%
4 12 2 1

1000P_0402_50V7K
+VTT_REFP VTTREF VDD +5VALW

1
PC411

PC412
PC410 5 11 1 2 1U_0402_16V6K
1U_0402_16V6K VDDQ VID

PGOOD
+1.2VDDQ
2

2
PR406 +1.2V_VDDQ

TON
100K_0402_1% @

FB

S3

S5
PJ404
JUMP_43X79 1 2
+3VALW PR440 PLACED CLOSE TO DIMM

10

2
2 1
+0.6V_VTT 2 1 +0.6VSP

2
PR407 @ PR440
@ 100K_0402_1% @ PR441

2+1.2V_TON
0_0402_5%

+1.2V_FB
PR411 0_0402_5%

0.01U_0402_25V7K
1
100K_0402_1%

1
1 2

PC820
+3VALW

1
590K_0402_1%

VDDQ_FB_R

2
PR412
VDDQ_PWRGD 26

+5VALW

1
1.2V_B+

470P_0402_50V7K

1
1
PR408

PC413
VDDQ_VTT_EN DDR_VREF_EN 12K_0402_1%

1.3K_0402_1%
1U_0402_16V6K

1U_0402_16V6K
C C
50 VDDQ_VTT_EN

1
FSW=450K

2
@

PC414

PC415

PR409
2
Vout=1.2V PR410 PU402

2
2

10K_0402_1%
PC439 VFb=0.75V@VID=0 +1.2V_FB 2 1 8
OUT VCC
1

2
@
0.1U_0402_25V7K OCP 24A
1

@
7 2
NC_2 BUS_SEL

3.92K_0402_1%
6 3

PR433
NC_1 GND
STATE SUSON MAINON +1.2V_VDDQ +0.6V_VTT Address 0X6A 0X68 0X66 0X64 0X62 0X60 PR413
20K_0402_1%
5 4
SCL SDA

1
S0 HI HI ON ON TOP R (Kohm) OPEN 3.9 3 2.3 1.3 10
uP1804A
HI LOW ON OFF(HighI‐Z) BOT R (Kohm) 10 1.3 2.3 3 3.9 OPEN
S3
Bus_sel Volt
S5 LOW LOW OFF(Discharge) OFF(Discharge) (% of VCC) 0% 25% 40% 60% 75% 100% PR426 2 1 0_0402_5% SMB_DATA 19
PR430 2 1 0_0402_5%
SMB_CLK 19

ADDR 0X62

B+
PJ405
JUMP_43X39
2 1 B+_2.5VP
2 1
10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V7K

PU403
1

@
PC419

B B
1

8 PR428 PC424
PC436

PC420

IN 0_0603_5% 0.1U_0603_25V7K +2.5V_MEM


2

2.5VP_BS 1
6 2 1 2 PL410
5A
SYX196DQNC_QFN10_3X3

BS
2

1.5UH_PCMB053T-1R5MS_6A_20%
+3VALW 9 10 2.5VP_LX 1 2
@ GND LX

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
@ 4 2.5VP_FB 0.6V
FB

1
PR427 1 2 100K_0402_5% 2.5VP_ILIM 3
ILMT
1

PC422

PC423

PC425

PC426

PC438
BYP +3VALW
PR418

2
1

CAD Note:ILIM 2.5V_MEM_EN 1 2.2_0805_5%


EN
1

PR431 @ 680P_0402_50V7K 1K_0402_1%


low:OCP=6A 2 5 3VLDO_2.5VP @
Floating:OCP=9A PG LDO
2

1M_0402_5%
PR429

2
Hi:OCP=12A +3VALW
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
2

PR438
2
PC437

PC434

1000P_0402_50V7K

95.3K_0402_1%
1

PR423
PC428

10K_0402_5%
1

PC435
2

FSW=800K
2

@
2

2.5V_MEM_PWRGD
Vout=2.5V
VFb=0.6
OCP 6A
2

PR439
30K_0402_1%
1

A A

PR451 LENOVO.CRDN
10K_0402_5%
PR425 2 1 0_0402_5% 2.5V_MEM_EN 2.5V_MEM_PWRGD 1 2 DDR_VREF_EN Title
26,41,48,49,90,92 SUSON
PWR-1.2VDDQ/VTT/2.5V
Size Document Number
0.1U_0402_25V7K

Rev V0.3
1

PC433 C
PC421

1 2 PD401 1000P_0402_50V7K
Skylake-H
19,26 SLP_S4_N
Date: Thursday, May 26, 2016 Sheet 76 of 99
2

SDM10U45LP-7_DFN1006-2-2 "PROPERTY NOTE: this document contains information confidential and


property to LENOVO PND and shall not be reproduced or transferred to other documents
@
or disclosed to others or used for any purpose other than that for which it was

WWW.AliSaler.Com
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

B+
PJ501
JUMP_43X39
2 1 B+_1.05VP
2 1

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V7K
PU501

1
+3VALW

PC501

1
@ 8 PR502 PC504

PC502

PC503
IN 0_0603_5% 0.1U_0603_25V7K +1.0VP

2
2
1.05VP_BS 1 +1.0VALW
6 2 1 2 PL501
6A

SYX198DQNC_QFN10_3X3
BS

2
PR501 1UH_PCMB053T-1R0MS_7A_20% @
100K_0402_5% 9 10 1.05VP_LX 1 2 PJ502
PR503 @ GND LX

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
@
1M_0402_5% 4 1.05VP_FB 0.6V
FB

1
1 2 1.05VP_ILIM 3
ILMT

1
7

PC505

PC506

PC507

PC510

PC508
BYP +3VALW
PR504

2
1 2 1.05VP_EN 1 2.2_0805_5%
D 26,41,75,92 EC_ON EN D

1
@

680P_0402_50V7K 1K_0402_1%
PR505 2 5 3VLDO_1.05VP @
PG LDO

2
1
20K_0402_1%

PR506
1

1
+3VALW

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1

1
PC511 PR507 PR508

2
0.1U_0402_25V7K 1M_0402_5% 90.9K_0402_1%

PC512

PC513
2

1
Control Bit Definitions

1
PR509
FSW=800K PC514

2
10K_0402_5% 1000P_0402_50V7K

1
Vout=1V @

PC515
2
VFb=0.6 LP# C1 C0 VOUT(V)

2
1.0VALW_PWRGD
OCP 8A
0 X X 0

2
PR511 1 0 0 0.8
133K_0402_1%

1 0 1 0.95

1
1 1 0 1
1 1 1 1.05

C C

B B

A A

LENOVO.CRDN
Title
PWR 1.0V/VCCEDRAM/EPIO
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 77 of 99
"PROPERTY NOTE: this document contains information confidential and
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

D D

PU605
+3VALW
PJ610
JUMP_43X39
2 1 GRM2103_PVIN 5 32 +1.8V
2 1 6 PVIN1 NC

22U_0805_6.3V6-M

22U_0805_6.3V6-M
0.1U_0402_25V7K
1 1 PVIN2

1
@ 7

PC675

PC680

PC679
8 PVIN3
9 PVIN4
PVIN5

2
2@ 2 10
PVIN6 2A PJ611
JUMP_43X39
29 GRM2103_OUT 2 1
10_0603_5% 11 VOUT8 28 2 1
VIN VOUT7

2
+3VALW 1 PR626 2 GRM2103_VIN 27
VOUT6 26 PR605 @
VOUT5

2
25 1K_0402_1%
VOUT4

1
PC626 1 2 15 GRM2103_QFN36_4X7 24 @
+3V PGD VOUT3
0.1U_0402_25V7K PR624 23 PR622

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M
0.1U_0402_25V7K
VOUT2 1 1 1

2 1

1
100K_0402_5% 22 20K_0603_1%

PC624

PC623

PC681
VOUT1 PC601 @

PC625
+3VALW 1 2 16 680P_0402_50V7K
TRK

2
12K_0402_1% PR649 2 2 2

1
PR623 0_0402_5% 30 GRM2103_FB @
MAINON 1 2 GRM2103_EN 13 FB
EN 0_0402_5%

1
14 1 PR648 2 +3VALW
MODE
1
@ @ PR621
PC622 PT602 1 3 10K_0603_1%
TP1

PGND10
PGND11
1U_0402_10V6K 1 4

PGND1
PGND2
PGND3
PGND4
PGND5
PGND6
PGND7
PGND8
PGND9
TP2
2

1
GND1
GND2
PT603

PAD

2
@ PR647
0_0402_5%

12
31

1
2
17
18
19
20
21
33
34
35
36

37

2
C C

@
@ PC416
PR417 1000P_0402_50V7K
AON7403L_DFN8-5 2.2_0805_5%
PQ904 1 212V_SN 1 2

1 PL602
600mA +12V_SWF_BOOST

+5VALW 2 2.2UH_PCMB053T-2R2MS_5.5A_20% PD601


3 5 1 2 2 1
10U_0805_25V6K

10U_0805_25V6K
1

DFLS240L-7 POWERDIR123
PC665

PC667
0.22U_0603_25V7K
1

10_0603_5%
100K_0402_1%

133K_0402_1%
0.1U_0603_25V7-M

4.7U_0805_25V6K

4.7U_0805_25V6K

4.7U_0805_25V6K
4

2
1

1
PR234

PC204

PR608
PC230

PR609

PC670

PC668

PC669
2

2
6

7
PU603
2

PC666 PC671

LX
LX1

2
PR230 1U_0402_16V6K 1U_0402_16V6K
B VSBP_2 VSBP_3 B
1 2 2 1 9 8 1 2
VIN VSUP
22K_0402_1% 3 2
EN FB 0.033U_0402_16V7K

1
4 10 2 1 PC678
GND1 SS
5 1 1 2 PR612
GND COMP
1

PQ206 D 15.4K_0402_1%

1000P_0402_50V7K
1 2 2 11 PR611
26,50,86,90,91,92 MAINON TP

2
1
G 56K_0402_1%

PC677
PR610 RT8509GQW
0_0402_5% S 2N7002KW_SOT323-3
3

2
1

PC676
0.1U_0402_25V7K
2

A A

LENOVO.CRDN
Title
PWR 1.8V/1.2V/12V Boost
Size Document Number
C Rev V0.3
Skylake-H
Date: Thursday, May 26, 2016 Sheet 78 of 99
"PROPERTY NOTE: this document contains information confidential and

WWW.AliSaler.Com
property to LENOVO PND and shall not be reproduced or transferred to other documents
or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

5 4 3 2 1
5 4 3 2 1

1.55V GPU Side


B+_GPU_ALL PR701 under GPU Near GPU
+5VALW 0.005_1206_LE_1%

1 2
24*1uF_0402_X6S 4*10uF_0603_X6S
B+
8*10uF_0603_X6S 9*22uF_0603_X6S

PC3401 EMC_NS@
4 3

2200P_0402_25V7-K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
1
PR3401

1
PC701

PC702

PC722

PC723
2_0603_5% B+_GPU_ALLP 68

2
FBVDDQ_PVCC 18
+3V_GPU PVCC 2 FBVDDQ_HG1 B+_GPU_ALLN 68
HG1

1
PC3407 PR3404 PC3409
1U_0402_6.3V6K 2.2_0603_5% 0.22U_0603_25V7K PQ701 PJ701

1
1 FBVDDQ_BS11 2 1 2 2 1

10K_0402_1%

10K_0402_1%
BST1 2 1

2
D D

1
9

VIN1
21 GND +1.55VG @ JUMP_43X118 +1.55VSG

PR3424

PR3589
@ THERM/GND 3 8 PL701
TG VSW3 0.22UH_PCMC065T-R22MN_30A_20% PJ702
20 FBVDDQ_TGR1 4 7 FBVDDQ_PH1 1 2 2 1
PH1 TGR VSW2 2 1

2
PR3423

1
10K_0402_1% 5 6 @ JUMP_43X118
2 1 FBVDDQ_PSI_R 4 BG VSW1 PR3405

330U_B2_2VM_R15M

330U_B2_2VM_R15M

330U_B2_2VM_R15M

330U_B2_2VM_R15M
PR703 PSI 4.7_0805_5% PJ1504
1 1 1 1
@ 10K_0402_1% CSD87350Q5D EMC_NS@ 2 1
1 2 + + + + 2 1

PC706

PC707

PC730

PC731
+3V_GPU

2
19 FBVDDQ_LG1 @ JUMP_43X118

FBVDDQ_SN1
PR704 2 1 0_0402_5% 13 LG1
68 +1.55V_DGPU_PGOOD PGOOD 2 2 2 2

68,69 1.55V_PWR_EN
2
PR3567 1 1K_0402_5% FBVDDQ_EN_R 3
EN
B+_GPU_ALL

1
PC3416

1
1000P_0402_50V9-J
Change to 1K ohm from 10Kohm
PC704
0.1U_0402_25V7K EMC_NS@ Need one more X63 to fine tune if need 1.5V

2
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
2

PC3426 EMC_NS@
2200P_0402_25V7-K
1

1
PC3501

PC3503

PC3504

PC3502
1 2 FBVDDQ_VID_R 5 14 FBVDDQ_HG2
63,79 VRAM_VDDQ_ADJ VID HG2

2
1
PR3408 PR3409 PC3425
0_0402_5% PC3424 @ 2.2_0603_5% 0.22U_0603_25V7K
@ 0.1U_0402_10V7K 15 FBVDDQ_BS2 1 2 1 2 PQ702
BST2

1
PU701
9

VIN1
NCP81278MNTXG_QFN20_3X3 GND
3 8 PL711

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM
TG VSW3 0.22UH_PCMC065T-R22MN_30A_20%

330U_B2_2VM_R15M
1 1 1 1
16 FBVDDQ_TGR2 4 7 FBVDDQ_PH2 1 2

PC726

PC727

PC728

PC729

330U_B2_2VM_R15M
PH2 TGR VSW2 1
FBVDDQ_VREF 8 1
VREF 5 6 +

PC724
BG VSW1 2 2 2 2

1
+

PC725
1
PC3434 PR3410
0.01U_0402_25V7K 4.7_0805_5% 2
CSD87350Q5D 2
C EMC_NS@ C

2
1

17 FBVDDQ_LG2

FBVDDQ_SN2
PR3411 LG2
5.76K_0402_1%
FBVDDQ_REFIN 7
REFIN
1.501V/1.35V:PR3411 6.65K SD03466518J
2

1
PR3412 PC3433
1000P_0402_50V9-J
PR415 45.3K SD03445328J 100_0402_1%
1 2 EMC_NS@

2
PR3413

+1.8V_AON +3V_GPU
18K_0402_1%
1 2FBVDDQ_VIDBUF 6
PR3414
0_0402_5%
Vboot=1.55V
VIDBUF FBVDDQ_FBRTN
@
FBRTN
10 1 2
FBVDD_VSS_SENSE 55 DC=±20mV AC=55mV
30K_0402_1%

20K_0402_1%
1

TDC=32A EDC=58A OCP>70A


10K_0402_1%
1

PC3435 VR Remote Sense - Tie to GPU sense points


10K_0402_1%

PR415

PR3415

FBVDDQ_FB
2200P_0402_50V7K 11
Vref=2V
PR3551

FB
PR712

1
@ PR3417 PC3438 PC3436 @ FUVP:Vfb=0.2V
2

124_0402_1% 1000P_0402_25V7-K 1000P_0402_25V7-K


2

FBVDDQ_FS 9 FBVDDQ_COMP
3 FS COMP/ILMT
12 PC196 1 2 82P_0402_50V8J 1 2 COMP32 1 2
SUVP:Vcomp=3V

2
2

PR3416 PR3419 PR3420 PR3421


OVP:Vfb=2V

1
PR414
6 5 39K_0402_1%
PR3418
23.7K_0402_1%
1 2 COMP31 1 2
10K_0402_1%
1 2
0_0402_5%
1 2
Fsw=400KHz
AO5804EL_SC89-6

FBVDD_VCC_SENSE 55
0_0402_5% 33.2K_0402_1% LL: NA
1

@ PC3439
PQ1409B

1 2 2 4 2200P_0402_25V7-K PR3422 CAD Note:VRAM_VDDQ_ADJ


AO5804EL_SC89-6

63,79 VRAM_VDDQ_ADJ

2
100_0402_1%

3.01K_0402_1%
L = 1.362V
1

1 2
PQ1409A

+1.55VSG
PR416 H = 1.55V

PR3572
100K_0402_1% 1 @

1
2

B B

+5VALW
CPU_B+

PJ704
2 1 B+_1.0VG
10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V7K

2 1

1.3K_0402_1%
2.2U_0402_6.3V6K
1

1
PC709

PU702
1

2
JUMP_43X79 @
PC710

PC711

PR3577
8 PR714 PC712 +PEX_VDD PR3574 PU1608

PC190
IN
2

0_0603_5% 0.1U_0603_25V7K +1.0VG 10K_0402_1%


2

1
1.0VG_BS FBVDDQ_FB
6 1 2 1 2
6A 2 1 8 1
SYX198DQNC_QFN10_3X3

BS PL702 OUT VCC

2
PJ703 @
9 10 1.05G_LX 1 2 2 1

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