A Fault Simulation Based Test Pattern Generator for Synchronous

Sequential Circuits
Ruifeng Guo Irith Pomeranz Sudhakar M. Reddy
Electrical & Computer Engineering Department
University of Iowa, Iowa City, IA 52242

Abstract minimal eort by using a fault simulator suitable for the

We describe a fault simulation based test generation proce-
dure for synchronous sequential circuits. Several techniques
are used to generate test sequences to achieve high fault
coverages at low computational complexity. Experimental
results presented demonstrate that the proposed procedure
achieves fault coverages which are in all cases the same or
higher than those achieved by existing procedures. The run
times of the procedure are considerably smaller compared to
the existing procedures.
1. Introduction
Generation of tests to detect faults in synchronous sequen-
tial circuits is a challenging problem. Scalable methods to
perform test generation have been under study for a large
new fault model and/or circuit description. The existence
of asynchronous elements in circuits can also be accommo-
dated. Recent eorts in developing fault simulation based
test generators have mostly used genetic optimization tech-
niques to engineer test sequences for target faults [9-12].
One such procedure has recently achieved high fault cover-
age, but requires large computational eort[12].
The property based test generator reported in [13] uses
only logic simulation in deriving a test sequence whose cov-
erage is determined by fault simulation. The run time of
this method is small but as of now has not achieved as high
a fault coverage as the genetic optimization based test gen-
eration procedures.
The procedure we propose achieves high fault coverage
with relatively low computational eort by taking advan-
tage of several techniques, including static test compaction.
number of years. The existing methods can be classied Since the procedure does not use deterministic test genera-
into four categories. The rst category of methods uses
the branch and bound technique to derive tests for target
faults[1-6]. The second category uses fault simulation to
direct the search for a test sequence for the target faults[7-
12]. Included in this category are genetic optimization based
test generation procedures. The third category uses certain
observed properties of test sequences in deriving input se-
quences that have similar properties, and are useful as test
sequences[13, 14]. The method of [13] does not target a
tion steps such as implication or branch and bound, it does
not identify undetectable faults. This drawback is the prop-
erty of test generators, including the simulation based test
generators, that do not use any deterministic test generation
procedures.
The paper is organized as follows: In Section 2, we de-
scribe the motivation for the proposed procedure. In Sec-
tion 3, we study several dierent methods to generate test
sequences that employ the observations made in Section 2.
specic fault but rather derives an input sequence that has
certain desirable properties. It uses only logic simulation of
the fault-free circuit to guide the inclusion of input vectors
in the test sequence [13]. The fourth type of methods are
based on pseudo-random or special purpose test generator
circuits that produce eective test sequences [15-17]. These
methods are often meant for use in BIST environments. The
test generation method we present in this work is a combi-
nation of fault simulation based and property based test
generation approaches. In Section 2, we discuss the rela-
tionship of the proposed procedure to these approaches and
discuss the observations that led to the development of the
proposed procedure.
Results of this study are used in designing the procedure
described in the later sections. In Section 4, we give an
overview of the procedure we implemented. A detailed de-
scription of this procedure is given in Section 5. In Section
6 we provide experimental results. Section 7 concludes the
paper.
2. Preliminaries
The proposed procedure is inspired by the following observa-
tions and recent results related to test sequence generation
for synchronous sequential circuits.
(i) The lengths of the test sequences generated by a va-
Fault simulation based test generators have the advan-
tage that they can be adapted to new fault models or dier-
ent circuit descriptions(e.g., RTL instead of gate level) with
 Research reported was supported in part by SRC Grant 98-
TJ-645 and NSF Grant MIP-9725053.
riety of test generators can be reduced quite signicantly
(over 50%) by omitting test vectors from a test sequence[18].
This reduction in test length is achieved without loss of fault
coverage [18-20]. The process of reducing the length of a
given test sequence is called static test compaction. Since

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 static test compaction reduces the test length without re-
ducing the fault coverage, one may argue that static test
compaction retains useful vectors while omitting other vec-
tors in order to reduce the test length. Thus, the compacted
test sequence can be regarded as being of \higher quality"
than the sequence before compaction. If the fault cover-
age of a given test sequence is not maximum, then static
compaction often results in a shorter test sequence with
fault coverage higher than that of the given sequence [18].
This happens in spite of the fact that the compacted se-
quence is obtained by omitting some input vectors from the
original test sequence. This again implies that static com-
paction enriches the quality of the test sequence. Thus, one
may argue that static compaction implicitly captures circuit
properties desirable to generate eective test sequences. It
should also be observed that test sequence compaction is
probably a necessary step to generate shorter test sequences
of sequential circuits if deterministic test generation is not
extensively employed. Only recently, an ecient test se-
quence compaction method called vector restoration based
static test compaction was proposed [19] and its eective-
ness demonstrated[20].
(ii) Genetic optimization has been used successfully to ob-
tain test sequences with high fault coverage[11, 12]. The ba-
sic steps in genetic optimization are mutation and crossover.
Mutation is the process of complementing bits in a given se-
quence. The earlier sequential circuit test generator of [7]
also used complementation of bits of a given sequence(e.g.,
a functional test sequence) to derive new sequences that de-
tect other faults and/or to improve the fault coverage of a
given sequence. We use mutation as a way to perturb a
given test vector in this work. Recent work reported in [16]
showed that tests for combinational circuits can be derived
from a small number of tests called centers by perturbing
the centers. These studies indicate that perturbation is a
useful technique to derive new tests from already derived
tests.
(iii) In [15], it was observed that holding the inputs of
(iv) Weighted random test pattern generation has been
demonstrated to be eective in achieving high fault cover-
ages for combinational logic circuits[21, 22]. A hill climb-
ing method where the input probabilities for new weighted
random vectors are determined from the set of test vectors
which detected the most recent faults was demonstrated to
achieve high fault coverages[23]. This work suggests that
the input probabilities of randomly generated vectors to
detect additional faults can be set according to the tests
generated for the detected faults. A similar idea was used
in [24] to derive weighted random test patterns from the
input probabilities computed over a deterministic test set.
For sequential circuits, the input probabilities of weighted
random sequences to detect additional faults can be derived
from the test sequence of the already detected faults. Given
the earlier observation (i), that compacted test sequences
may capture desired properties of test sequences, it can be
argued that input probabilities computed over compacted
test sequences may be more eective.
Summarizing, the experimental results presented in sev-
eral recent works indicate that static test compaction based
on omitting vectors from a test sequence to capture circuit
properties, perturbation, and holding of inputs constant in
a test sequence may lead to a more eective test sequence.
It should, however, be noted that an ATPG employing per-
turbation and/or input holding that achieves high fault cov-
erages has not been demonstrated earlier. Similarly, static
test sequence compaction has been used to reduce the length
of a given test sequence and not to improve the computa-
tional eciency of a test generator or to achieve a high fault
coverage.
In this work, we use static test compaction, perturba-
tion, and input holding together to produce an ATPG tool
that is highly ecient and eective in achieving a high fault
coverage.
3. Dierent Methods to Generate Test Se-
a sequential circuit at xed values for several clock cycles
improves the fault coverage obtained by a pseudo-random
sequence generated, for example, by an LFSR. In this ap-
proach, an input vector generated by a pseudo-random pat-
tern generator is held for a predetermined number of cy-
quences
In order to chose an ecient way to generate test sequences
based on the observations made in the previous section, we
conducted experiments to study the relative eectiveness of
several test sequence generation procedures.
cles. In terms of state traversal, holding the inputs con-
stant makes the circuit traverse potentially dierent states
appearing in the state table under the column correspond-
ing to the held input vector. Test sequences that traverse
large number of states were observed to be eective in de-
tecting faults in several works [12, 13]. In [15], the number
of clock cycles over which inputs are held are determined
by running a deterministic sequential circuit test generator
over a sample of faults. Thus, an eective deterministic se-
quential circuit test generator is necessary to supplement
the method of holding of pseudo-random input vectors in
[15]. In our use of input holding, we randomly determine
the number of cycles to hold an input vector, thus avoiding
the need for a deterministic sequential test generator.
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The rst experiment was conducted to determine whether
holding a random input vector a randomly selected number
of times improves the fault coverage of a random sequence
of a given length. We also wanted to determine if test se-
quence compaction further improves the fault coverage of
such a random sequence. The results of this experiment are
reported in Table 1. For the all benchmark circuits reported
in Table 1, we set the length of the test sequence used to
300,000. We report in Table 1 the number of faults detected
using various methods. The test sequence generation meth-
ods used are described below.
Method R: A random sequence of given length with the
probability of 1s on all primary inputs set at 1/2.
Method RH: A sequence of random vectors as in
 Method R, except that a vector is held for a number of
time units. The number of time units a vector is held is
randomly selected. We used holding of a vector for 2i time
units with probability 2,(i+1) , for 0 i 7, and holding
 
for 28 time units with probability 2,8 .
Method RHC(N): A sequence, say S, of length N is
generated using method RH. It is then compacted using the
method of [20] into a sequence Sc . Next, the sequence Sc
is extended to a sequence of length N again by concatenat-
ing a sucient number of vectors to Sc using the sequence
generation Method RH. These steps are repeated until the
total number of vectors generated reaches 300,000. We used
two values of N; viz., 3,000 and 5,000. These are reported
as RHC(3000) and RHC(5000) in Table 1.
In Table 1, we report the number of faults detected by
each method. The total number of faults detected in all the
circuits by each method is reported in the last row of Table
test sequence.
The various test sequence generation methods employed
dier in the manner the compacted test sequence Sc is ex-
tended into S in Step 3 given above. Note that the total
number of test vectors generated and simulated in all meth-
ods is less than or equal to 300,000.
Method E: Compute the proportions of ones and zeros
on each primary input among the vectors in the compacted
sequence Sc . Use these proportions as probabilities of 1s
and 0s on the primary inputs to generate new vectors to
extend Sc in Step 3 above.
Method EH: This method of generating new vectors to
extend Sc is the same as Method E, with the exception that
a vector generated to extend Sc is held a random number
of times as discussed for Method RH described earlier.
Method EPH: This method of generating new vectors
to extend Sc is the same as Method EH, except that a new
1. The following observations can be made by noting the
total number of faults.
(i) Comparing Methods R and RH, it can be observed
that holding a random vector a random number of times
improves the fault coverage over that obtained by a random
sequence of the same length.
(ii) Comparing Methods RH and RHC(N), it can be ob-
served that compacting a sequence after every N test vectors
helps increase the fault coverage. Furthermore, comparing
the results for RHC(3000) and RHC(5000) it can be noted
that increasing the value of N while keeping the total test
sequence length constant leads to the detection of additional
faults. One can argue that the reason for compaction im-
vector generated is rst perturbed before holding it a ran-
dom number of times. The method used to perturb a vector
is the same in all the methods reported in Table 2 and is
described in Section 5.
Methods En, EnH, and EnPH: These methods are
analogous to Methods E, EH and EPH, respectively, except
that the probabilities of 1s and 0s on the primary inputs are
computed over the subsequence of Sc over which the most
recently detected faults are detected. We set a limit of 100
on the subsequence used to compute input probabilities in
these methods.
Method VPH: The new vectors to extend Sc in Step
3 above are generated by randomly selecting a vector from
proving the fault coverage is that the compacted prex of a
test sequence of length N drives the sequential circuit into
states more eective for fault detection. The reason for the
increase in fault coverage with increased value of length N
is, we believe, due to the fact that longer subsequences are
more likely to detect harder to detect faults.
In all the methods reported in Table 1, additional test
vectors were randomly generated. In the next experiment,
we wanted to determine the relative eectiveness of dierent
methods that use the properties of the compacted test se-
quences to generate additional vectors. We evaluated eight
methods to generate test vectors, and we report the fault
coverages achieved by these methods in Table 2. The dif-
ferent methods used are described next.
Sc , followed by randomly perturbing it and then holding it
a random number of times.
Method SPH: The new vectors to extend Sc are gen-
erated similar to the Method VPH, except that we either
select a single vector with probability 5/6 or a subsequence
of length 5 with probability 1/6, before perturbing and hold-
ing. If a subsequence of length 5 is selected then we do not
hold it as is done for single vectors.
The number of faults in benchmark circuits detected by
the eight methods described above and the total number
of faults detected in all the circuits are given in Table 2.
Comparing the results reported we can make the following
observations:
(i) All the methods use some property of the compacted
The basic steps used in all the methods reported in Table
2 are the same as those used for RHC(N) with N=5,000 and
these are:
Step 1: Generate a random sequence of length 5,000. Set
iteration count I = 1.
Step 2: Compact the length 5,000 test sequence into a se-
quence Sc by using the test sequence compaction procedure
test sequence. In the rst six methods, the probabilities of
1s and 0s in new test vectors are set equal to the propor-
tions of 1s and 0s on each primary input in the compacted
sequence Sc or in a subsequence of Sc . In the last two meth-
ods, the vectors in Sc are used. All these methods detect
larger numbers of faults than the test sequences generated
randomly as in the methods reported in Table 1. Thus one
described in [20]. Simulate the compacted test sequence and
drop the faults detected from the fault list.
Step 3: If the iteration count I is less than 60, extend Sc
into a sequence S of length 5,000, using one of the dierent
extension techniques(described below) and go to Step 2.
can conclude that test sequence compaction identies prop-
erties or test vectors eective in fault detection. Further-
more, repeated use of test sequence compaction appears to
help update properties of the compacted sequence that are
eective in detecting additional faults.
Step 4: Return the number of faults detected by the nal (ii) Comparing the number of faults detected by methods

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 that use vector perturbation and holding with those that do obtain a compacted test sequence Sic whose fault coverage
not, one can conclude that vector perturbation and vector is the same as that of Si or higher, i.e., Sic detects all the
holding increase the number of faults detected. faults in Fi and possibly additional faults.
(iii) Comparing methods E, EH, and EPH to En, EnH,
and EnPH, respectively, it appears that deriving input prop-
erties based on the subsequences that detected most recently
detected faults is more eective than deriving input proba-
bilities on the entire compacted test sequence.
(iv) Comparing the results for Method SPH with those
for Method VPH, it appears that subsequences of already
generated test sequences help detect additional faults as was
also observed in [14].
(v) All the methods studied in Table 2 achieve similar
fault coverages and hence may have the potential to achieve
the highest achievable fault coverages if a test generator is
Step 4: Check the termination condition. If satised,
stop.
Step 5: Extend Sic by appending a sux Sisu to ob-
tain an input sequence Si+1 = Sic Sisu . The sux Sisu is


obtained by repeatedly using one of the following two pro-
cedures. In one procedure, a vector v in Sic is randomly
chosen. It is randomly perturbed to obtain a vector v', and
n copies of v' are included in consecutive positions of Sisu
(inclusion of n copies of v' corresponds to holding the inputs
constant at v' for n cycles). The value of n is randomly de-
termined. In the other procedure, a subsequence of length s
is randomly chosen from Sic . The subsequence is randomly
built using appropriate values for the various parameters perturbed and placed in Sisu . The rst procedure is used
used in each method. with probability p and the other with probability (1-p).
We report in the next two sections a test generator we The extension of Sic into Si+1 by adding vectors to the
built using Method SPH. sux Sisu continues until the length of Si reaches a prede-
termined value.
Table 1: Eect of Test Compaction on Fault Step 6: Set i = i +1 and go to Step 2
Coverage The example given next illustrates the steps in the pro-
RHC(N) posed procedure.
Ckt R RH 3000 5000 Example: Consider a sequential circuit with two pri-
s298 262 255 265 265 mary inputs. Assume that the length of the sequence S0
s344 329 329 329 329 in Step 1 above is chosen to be four and the lengths of the
s382 69 349 356 363
s400 73 381 372 381 extended sequences in Step 5 is chosen to be eleven. Let
s444 61 423 423 423 the random input sequence generated in Step 1 be S0 =
s526 63 430 443 451 (00, 01, 00, 11). Let the sequence obtained after applying
s641 404 404 404 404
s713 476 476 439 476 static compaction to S0 be S0c = (00, 01, 11). Static com-
s820 423 531 440 441 paction dropped one vector from S0 (the third vector in S0 )
s832 423 507 489 442 to obtain S0c . Next, we extend S0c into S1 by concatenat-
s1196 1235 1232 1228 1232
s1238 1279 1270 1268 1270 ing seven more vectors to S0c to obtain a sequence of the
s1423 999 1368 1346 1396 desired length eleven by executing Step 5. Suppose that in
s1488 1232 1431 1425 1431
s1494 1240 1438 1441 1440 the rst choice to extend S0c into S1 , input vector (11) is
s5378 3210 3436 3492 3457 picked randomly from S0c . Next, we randomly perturb it by
s35932 34077 34085 35101 35101 complementing the second bit to obtain (10). We then pick
am2910 2165 2163 2156 2158
div16 1724 1758 1741 1749 a random number of repetitions of (10), say two repetitions.
mult16 1472 1664 1665 1665 This will extend S0c = (00, 01, 11) into the sequence (00,
pcont2 6815 6798 6815 6815 01, 11, 10, 10). Next, suppose that we randomly pick the
piir8 18141 18127 18141 18141 subsequence (01, 11) from S0c . We randomly perturb each
piir8o 15048 15083 15088 15088
s3271 3262 3189 3248 3251 vector in the subsequence (01, 11). Let us perturb both bits
s3330 2121 2120 2108 2113 in (01) and the rst bit in (11) to obtain the subsequence
s3384 3124 2901 3083 3093 (10, 01). We concatenate this subsequence to (00, 01, 11,
s4863 4599 4574 4543 4576
s6669 6675 6675 6675 6675 10, 10) and obtain a length seven sequence (00, 01, 11, 10,
prolog 2323 2321 2312 2312 10, 10, 01). Next, let us again pick randomly a subsequence
Total 113324 115718 116836 116938 (00, 01) from S0c and perturb it to obtain (00, 10). We
concatenate this subsequence to (00, 01, 11, 10, 10, 10, 01)
to obtain the length nine sequence (00, 01, 11, 10, 10, 10,
4. Overview of the Proposed Procedure 01, 00, 10). Suppose that we next pick randomly the vec-
The following are the basic steps used in the proposed tor (00) from S0c and randomly perturb both bits to obtain
ATPG: (11). We randomly decide to hold this vector three times.
Step 1: Generate a random input sequence S0 of length However, since the extended sequence length is set to eleven,
L. Set i = 0. we concatenate only two copies of (11) to (00, 01, 11, 10, 10,
Step 2: Fault Simulate Si on the circuit under test. Let 10, 01, 00, 10) to obtain a length eleven sequence S1 =(00,
Fi be the set of faults detected by input sequence Si .
01, 11, 10, 10, 10, 01, 00, 10, 11, 11).
Step 3: Use static test sequence compaction on Si to Next, we fault simulate S1 and then apply static com-

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 Table 2: Dierent Test Generation Methods
Ckt E EH EPH En EnH EnPH VPH SPH
s298 265 265 265 265 265 265 265 265
s344 329 329 329 329 329 329 329 329
s382 357 364 364 357 363 364 328 364
s400 374 382 382 374 381 382 365 382
s444 416 424 424 416 424 424 372 424
s526 446 454 453 446 452 454 445 442
s641 404 404 404 404 404 404 404 404
s713 476 476 476 476 476 476 476 476
s820 547 561 692 507 681 698 741 792
s832 489 791 688 509 692 728 761 795
s1196 1235 1231 1231 1230 1232 1231 1237 1233
s1238 1280 1273 1275 1274 1274 1274 1281 1282
s1423 1384 1412 1415 1383 1415 1414 1405 1408
s1488 1444 1444 1444 1444 1443 1444 1443 1444
s1494 1453 1453 1452 1453 1453 1453 1453 1453
s5378 3229 3521 3507 3329 3543 3544 3625 3594
s35932 35100 35101 35101 35100 35101 35100 35101 35101
am2910 2175 2190 2182 2188 2171 2184 2195 2197
div16 1726 1737 1766 1728 1758 1746 1789 1788
mult16 1665 1665 1665 1665 1665 1665 1665 1666
pcont2 6815 6815 6815 6815 6815 6815 6815 6823
piir8 18141 18141 18141 18141 18141 18141 18141 18141
piir8o 15088 15088 15088 15088 15088 15088 15088 15088
s3271 3262 3261 3259 3262 3259 3256 3260 3262
s3330 2118 2124 2118 2118 2118 2118 2123 2124
s3384 3129 3106 3100 3104 3092 3104 3252 3287
s4863 4601 4578 4591 4608 4613 4600 4604 4607
s6669 6675 6675 6675 6675 6675 6675 6674 6675
prolog 2324 2325 2325 2314 2325 2314 2319 2325
Total 116947 117590 117627 117002 117648 117690 117956 118171

paction to it. Suppose that after this application of static Step 3: The sequence Si is compacted to obtain the se-
compaction, we obtain a test sequence S1c = (00, 11, 10, 11, quence Sic using the static compaction procedure described
11) by dropping six vectors from S1 . We extend S1c into S2 in [20].
and iterate compaction and extension until the procedure Step 5: In this step, a compacted sequence Sic is ex-
termination condition is met. tended to obtain a longer sequence Si+1 .
In order to insure the potential to generate vectors with
5. Detailed Description of the Test Generation few ones and also vectors with large number of ones in them
we append ve all-0 and ve all-1 vectors to Sic before it is
Procedure expanded into Si+1 . When these vectors are picked during
In this section, we give the details of the proposed test gen- sequence
few ones
extension, perturbation often creates vectors with
and large number of ones.
eration procedure. We extend Sic by randomly selecting vectors or subse-
As noted in the overview, we use test compaction and quences of length ve from Sic . The probability of selecting
test sequence extension (Steps 3 and 5 in the procedure a subsequence of length ve is set at 1/6 in our implemen-
overview given in Section 3) repeatedly to generate test se- tation.
quences. Let Si be an extended sequence and Sic be the In our implementation, we use lengths of 2,000, 5,000,
corresponding compacted sequence obtained by the appli- 10,000, 20,000 and 40,000 for the extended sequences. Ini-
cation of the static test compaction procedure. Next, we tially, the extended sequence length is set at 2,000. When-
give the parameters used in each step of the procedure to- ever two consecutive
gether with a detailed explanation of each step. We refer to yet undetected faultsextended
we
sequences do not detect any
increase the length to the next
the various steps in the overview in discussing these details. higher value (if one exists).
Step 4 (the termination condition) is described at the end. If a single vector is selected (and not a subsequence), we
Step 1: In this step we generate a sequence S0 of length perturb the vector in zero or one or two or three bits with
2,000. The initial part of this sequence is a synchronizing equal probability. Thus, the probability that a vector is
sequence for the fault-free circuit if one exists, and the rest actively perturbed by complementing some bits is 0.75 in
of the sequence is randomly generated.
Step 2: Assuming that the power up state of the circuit mutation used in geneticmuch
our procedure. This is higher than the probability of
is unknown, the sequence Si is fault simulated using the we do not perturb more than 3 bits inprocedures.
optimization
each
However,
vector. The bit
fault simulator HOPE [25, 26]. The fault simulator HOPE positions perturbed are determined randomly.
is used in our work whenever we need to fault simulate a After obtaining the perturbed vector, we decide on the
sequence.

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 number of times this vector is copied into consecutive posi- Table 4: Test Generation Results Under a
tions of the extended sequence. This step is used to achieve Multiple Observation Time Fault Simulator
holding of inputs constant at a specic value. In our imple- Total Proposed MIX[5]
mentation, an input vector is held for one of nine dierent Ckt Faults # t.det Time # t.det
numbers of time units, all powers of 2. These are 2 , i =i
s298 308 272 0.30 272
0, 1, ..., 8. The probability that an input vector is held for s344 342 335 0.09 335
2i time units is set to 2,(i+1) for 0 i 7, and 2,8 for s382 399 375 1.59 371
 
s400 424 394 2.14 394
i = 8. In the earlier work using the concept of holding in- s444 474 436 2.06 436
puts [15], the hold times were selected based on the results s526 555 464 4.33 464
of a deterministic test generator on a set of sampled faults. s641 467 408 0.14 408
s713 581 480 0.17 480
Our implementation avoids the use of a supplementary test s820 850 815 0.91 815
generation tool and achieves much higher fault coverages s832 870 819 0.80 819
compared to those reported in [15]. It should be noted that s1196 1242 1239 0.17 1239
s1238 1355 1283 0.24 1283
except for the initial sequence generated in Step 1, the ex- s1423 1515 1471 14.19 1455
tended sequences are constructed from (perturbed) vectors s1488 1486 1446 1.38 1446
of the compacted sequences. s1494 1506 1455 1.31 1455
s5378 4603 3665 12.30 3643
If a subsequence of length ve is selected from Sic , then s35932 39094 35110 90.57 35110
it is included after perturbation in the extended sequence s3271 3270 3262 3.70 3251
without holding it. s3330 2870 2124 2.01 2124
s3384 3380 3350 6.47 3346
Step 4(Procedure termination): The test generation pro- s4863 4764 4638 1.61 4638
cedure is terminated when three consecutive extended se- s6669 6684 6683 5.72 6683
quences do not detect any yet undetected faults. prolog 3305 2325 2.16 2325
am2910 2391 2211 5.48 2203
Additional details: Initial iterations of the procedure div16 2147 1853 5.84 1746
use a sample of 128 randomly selected faults as targets for mult16 1708 1687 2.29 1685
test generation. As faults are detected, the fault sample pcont2 11272 6838 12.22 6830
piir8 29689 18142 47.48 18125
is replenished by selecting additional undetected faults and piir8o 19936 15095 45.60 15083
the sample size is increased gradually, until all the yet un-
detected faults are targeted in the later iterations of the
procedure.
In the next section, we give results of running the pro-
posed test generation procedure on ISCAS89 and other fault three
coverages for the circuits studied, when conventional
value logic simulation is used. Three value simulation
benchmark circuits. is also used in HOPE[25, 26] and hence in the proposed
test generator that uses HOPE for fault simulation. In the
6. Experimental Results last three columns of Table 3, we give the number of faults
detected by the sequential circuit test generator STRATE-
The test pattern generator described in the previous sections GATE [12] followed by the run time for it and the length
was implemented in the C language. The run times reported of the test sequence it generated. The entries for STRATE-
for the proposed test generator are measured on a machine GATE are sometimes shown as `NA' as these are not given
with a 400MHZ Pentium II processor and using the LINUX in the published literature. The run times for STRATE-
operating system. Run times are given in seconds. The cir- GATE are for a HP J200 workstation.
cuits used in this study are the larger ISCAS89 benchmark From Table 3, it can be noted that compared to
circuits, the ISCAS93 addendum circuits, and the synthe- STRATEGATE, the proposed test generator detects the
sized circuits available from the University of Illinois. The same or larger numbers of faults in all the circuits. The
experimental results are reported in Table 3 given on the length of the test sequences generated by the proposed pro-
next page. After the circuit name, we show the total num- cedure are shorter than the STRATEGATE sequences for
ber of collapsed faults in the circuit followed by the number eighteen of the twenty-three circuits. Direct comparison of
of faults detected by the proposed test generator, the run run times between the two test generators is not possible
time and the length of the test sequence generated by the since they were run on two dierent machines. However, it
proposed test generator. Since we used a stopping criterion can be seen that the proposed test generator takes at most
of consecutive extended sequences not detecting new faults, a few minutes to generate the test sequences for all the cir-
a better measure of the eectiveness of the proposed proce- cuits.
dure is to note the time at which the last faults are detected. In Table 4, we compare the fault coverages achieved by
This time is shown in the column `FC Time'. the proposed test generator with those achieved by the test
In Table 3, we compare the performance of the pro- generator called MIX[5]. MIX uses several strategies in-
posed test generator with that of the test pattern generator cluding deterministic test generation to achieve the highest
STRATEGATE[12]. STRATEGATE [12] uses genetic opti- reported fault coverages for the circuits studied. Among
mization techniques and has achieved the highest reported the strategies it uses is the restricted multiple observation

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 Table 3: Test Generation Results of the Proposed Test Generator
Total Proposed STRATEGATE[12]
Ckt Faults # t.det Time Len FC Time # t.det Time Len
s298 308 265 3 156 1 265 NA 306
s344 342 329 4 112 2 329 NA 86
s382 399 364 99 641 78 364 486 1486
s400 424 382 92 617 75 382 NA 2424
s444 474 424 163 881 126 424 1206 1945
s526 555 454 323 1854 295 454 3270 2642
s641 467 404 30 182 24 404 NA 166
s713 581 476 37 205 32 476 79 176
s820 850 814 644 744 609 814 218 590
s832 870 818 303 588 267 818 NA 701
s1196 1242 1239 28 241 23 1239 89 574
s1238 1355 1283 43 334 37 1282 NA 625
s1423 1515 1416 277 1387 193 1414 4572 3943
s1488 1486 1444 119 549 66 1444 NA 593
s1494 1506 1453 126 508 90 1453 456 540
s5378 4603 3643 898 706 729 3639 136080 11571
s35932 39094 35101 676 255 597 35100 39240 257
am2910 2391 2198 178 577 132 2198 1704 2509
div16 2147 1840 251 1330 240 1814 29160 3476
mult16 1708 1666 16 337 10 1665 NA 1530
pcont2 11272 6823 134 144 106 6823 NA 197
piir8 29689 18141 289 351 121 18127 NA 443
piir8o 19936 15088 305 388 188 15071 NA 354
s3271 3270 3262 429 1622 400 NA NA NA
s3330 2870 2124 384 442 308 NA NA NA
s3384 3380 3324 716 1279 541 NA NA NA
s4863 4764 4638 101 483 90 NA NA NA
s6669 6684 6675 52 338 46 NA NA NA
prolog 3305 2325 224 392 148 NA NA NA

time test strategy[27]. The restricted multiple observation circuits studied and its run times are relatively small.
time strategy allows the use of conventional test application In Table 5, we give the results for large circuits of the pro-
where a single fault-free circuit response is compared with posed test generator when we suppress some of the heuristics
the response obtained from the circuit under test. However, used. We repeat the results for the proposed procedure in
it alleviates some of the deciencies of the conventional sin- the rst three columns after the circuit names. In the next
gle observation time test strategy and three value logic sim- three columns, we give the results for the case when subse-
ulation used in most of the test generators, including the
proposed test generator. In order to compare with MIX,
we simulated the test sequences generated by the proposed
test generator using a restricted multiple observation time
fault simulator made available to us by Dr. Xijiang Lin
quences of length ve are not chosen and only single vectors
are randomly chosen from the compacted sequences to ex-
tend them. In the next three columns, we give results for the
case when holding vectors is not used. It can be seen that
in general, using all heuristics allows the detection of more
who developed MIX. In Table 4, we rst report the num-
ber of faults detected by the test sequences generated by
the proposed test generator followed by the time for fault
simulating the test sequences using the restricted multiple
observation time fault simulator. In the last column we give
the number of faults detected by MIX. Even though the pro-
posed test generator used a conventional fault simulator in
generating the test sequences, additional faults are detected
when the test sequences generated by it are simulated us-
ing the restricted multiple observation time strategy. This
can be observed by comparing the number of faults detected
by the proposed test generator as reported in Table 3 and
Table 4. Comparing the proposed test generator and MIX,
it can be seen that the proposed test generator detects the
same number or more faults than MIX for all the circuits.
Summarizing, the experimental results presented in Ta-
bles 3 and 4 together show that the proposed test generator
achieves the highest overall fault coverage for the benchmark
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faults at reduced computational cost compared to dropping
some of the heuristics.
7. Conclusion
An automatic test pattern generation procedure for se-
quential circuits was described. The proposed procedure
uses a combination of static test sequence compaction
and sequence extension techniques. Sequence extension is
achieved by repeating perturbed input vectors or subse-
quences included in the compacted sequence. Single input
vectors are also held randomly, if selected. Experimental re-
sults presented show that the proposed procedure achieves
the highest overall fault coverages for the benchmark cir-
cuits studied, while requiring relatively short run times.
In deriving test sequences, no explicit information about
the structure or functional properties of the circuits under
test were used. It is expected that incorporating such circuit
 Table 5: Comparing the Eectiveness of Dierent Heuristics
Proposed w/o. Subsequence w/o. Holding
Ckt #
t.det Time Len #
t.det Time Len #
t.det Time Len
s1196 1239 28 241 1239 16 272 1239 52 268
s1238 1283 43 334 1283 25 310 1282 61 327
s1423 1416 277 1387 1413 295 1309 1359 230 588
s1488 1444 119 549 1443 87 474 1444 99 640
s1494 1453 126 508 1451 91 518 1453 39 805
s5378 3643 898 706 3627 1321 767 3393 1750 427
s35932 35101 676 255 35101 752 343 34355 1050 245
am2910 2198 178 577 2195 306 962 2198 184 596
div16 1840 251 1330 1821 216 1505 1769 126 340
mult16 1666 16 337 1666 20 254 1665 21 303
pcont2 6823 134 144 6823 227 149 6815 128 142
piir8 18141 289 351 18141 350 334 18138 283 349
piir8o 15088 305 388 15087 259 339 15088 281 371
s3271 3262 429 1622 3260 547 2424 3262 229 1037
s3330 2124 384 442 2119 258 571 2124 272 517
s3384 3324 716 1279 3221 795 2211 3335 680 1083
s4863 4638 101 483 4624 157 558 4621 208 419
s6669 6675 52 338 6669 40 336 6668 46 351
prolog 2325 224 392 2322 324 571 2323 204 450
Total 113684 5246 11663 113505 6068 14207 112531 5943 9258

information will help improve the eciency and eectiveness Activation," in Proc. 27th Fault-Tolerant Computing Symp.,
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[15] L. Nechman, K. K. Saluja, S. Upadhyaya and R. Reuse, \Ran-
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