130 nm and 90 nm CMOS Technologies

Università di Bergamo
1

Dipartimento di Ingegneria Industriale

Via Marconi 5, 24044 Dalmine (BG), Italy
for Detector Front-end Applications 3 INFN Sezione di Pavia

Via Bassi 6, 27100 Pavia, Italy

M. Manghisoni1,3, E. Baldi2,3, L. Ratti2,3, V. Re1,3, V. Speziali2,3, G. Traversi1,3

2 Università di Pavia

Dipartimento di Elettronica massimo.manghisoni@unibg.it, elia.baldi@unipv.it, lodovico.ratti@unipv.it, valerio.re@unibg.it, valeria.speziali@unipv.it, gianluca.traversi@unibg.it

Via Ferrata 1, 27100 Pavia, Italy

Introduction Experimental Details

CMOS commercial technologies of the quarter micron node have been extensively used for the implementation of
MOSFETs studied belong to two standard CMOS processes by STMicroelectronics with 130 nm and
radiation tolerant, low noise, low power readout circuits with very high channel density for analog and digital 90 nm minimum feature size. The oxide thickness tOX is 2.4 and 2.0 nm, and the gate capacitance per
processing in pixel and microstrip detectors. unit area COX is about 14.8 and 17.7 fF/µm2 respectively.

The IC designers’ effort is presently shifting to 130 nm CMOS technologies, or even to the next technology node, to
In the 130 nm process PMOS and NMOS devices with gate lengths L from 0.13 to 1 µm and gate
implement readout integrated circuits for silicon strip and pixel detectors, in view of future HEP applications widths W of 200, 600 and 1000 µm were investigated. In the 90 nm process devices of both polarities
(SLHC, Linear Collider, Super B-Factory) . with gate lengths L from 0.10 to 0.7 µm and gate widths W of 200 and 600 µm were characterized. In

In this work the results of noise measurements carried out on CMOS devices in 130 nm and 90 nm commercial both processes, transistors were laid out using a standard open structure configuration.
processes are analysed to provide an evaluation of the impact of technology scaling on the analog performances of
The device parameters were characterized at drain currents from several tens of µA to 1 mA, that is,
a future generation of front-end chips. The behavior of 1/f and channel thermal noise parameters is studied to the usual operating currents of input MOSFETs in integrated charge-sensitive amplifiers.
assess the effects of gate oxide quality and short-channel phenomena in CMOS processes with different gate oxide
thickness and minimum channel length.

Experimental Results
Transconductance and Device Operating Region Noise Equations

Transconductance behavior depends on the The noise performances of a MOS device can be characterized in terms of the gate referred noise voltage spectrum:
100
inversion region where the device is operating. The
Weak Inversion Law Strong Inversion Law
inversion level of a MOS transistor in saturation Kf 1
Se2 (f ) = S2W + 100

NMOS
can be expressed by means of its transconductance C OX WL f α f NMOS

Noise Voltage Spectrum (nV/Hz )

efficiency gm /ID as a function of the normalized

1/2
White noise 1/f noise
drain current IDL/W [1].
g /I [1/V]

1/f Slope (αf=1)

10 130 nm process Channel thermal noise (dominant at low current Kf = intrinsic process 10
m D

90 nm process
The boundary between weak and strong inversion density) and noise in parasitic resistors [2] parameter, αf = 1/f noise
is expressed by Iz*, located at the intersection of slope
weak and strong inversion asymptotes: Γ PMOS
PMOS S2W = 4k BT Γ = α W nγ
I* I* gm 1

1
Z,P 90 Z,N 90
I*Z = 2µCOX nVT2 αW ≥ 1 excess noise factor, γ ranging from 1/2 in
130 nm process
W/L=1000/0.2
10
-9
10
-8
10
-7
10
-6
10
-5 I =1 mA, |V |=0.6 V
µ=channel mobility, n=coeffcient proportional to the weak inversion to 2/3 in strong inversion D DS

I L/W [A]
D
invers of the subthreshold slope of ID as a function of 0.1
3 4 5 6 7 8
0.03 10 10 10 10 10 10
VGS, VT =thermal voltage.
130 nm process
Noise Measurement Frequency (Hz)

0.025
90 nm process NMOS
Iz* is larger in devices fabricated in 90 nm ⇒ weak
Transconductance [A/V]

0.02
W/L=600/0.35 and moderate inversion regions extend to higher
|V |=0.6 V
DS normalized drain currents. Noise voltage spectra were
100 100
0.015 measured for PMOS and
Noise Voltage Spectrum [nV/Hz ]

Id=0.10 mA

Noise Voltage Spectrum [nV/Hz ]

L=0.13 µm
1/2

1/2
Id=0.25 mA
Iz* [µA] NMOS with different gate L=0.35 µm
Id=1.00 mA
0.01 L=1.00 µm
PMOS Process 130 nm 90 nm widths and lengths and at
different drain currents for 10 10
0.005 NMOS 0.55 0.75
devices belonging to both the
PMOS 0.15 0.20
0 investigated technologies.
0 0.0002 0.0004 0.0006 0.0008 0.001 90 nm process
Drain Current [A]
All the investigated devices are operated in weak 1 130 nm process 1 PMOS W/L=600/0.2
NMOS W=1000 µm |V |=0.6 V
and moderate inversion region. Id=250 µA, V =0.6 V
DS
DS

3 4 5 6 7 8 2 3 4 5 6 7
10 10 10 10 10 10 10 10 10 10 10 10
Analysis of Noise Measurement Results Frequency [Hz] Frequency [Hz]

1/f noise coefficient Kf White noise

40
250 250
35
130 nm process For N-channel devices Kf is: White noise is evaluated in terms of the
NMOS W=1000 µm 90 nm process 90 nm process

independent of the drain equivalent noise resistance: PMOS W=600 µm
Equivalent Noise Resistance [Ω]

NMOS W=600 µm
Equivalent Noise Resistance [Ω]

30 90 nm process 200 200

Kf [J 10 -25 Hz (alpha-1)]

NMOS W=600 µm V =0.6 V |V |=0.6 V

25
current. DS DS

2
I varing from 0.1 to 1 mA
D

larger for deviced with SW nγ L=0.20 µm 150
L=0.13 µm
20 V =0.6 V R eq = = αW 150
L=0.35 µm
L=0.20 µm
DS
L<0.5 µm in the 130 nm 4k B T gm L=0.50 µm L=0.35 µm
15 L=0.70 µm L=0.50 µm
process and with L<0.2 µm 100 100 L=0.70 µm
10
in the 90 nm process.
White noise decreases with the increase
50
5

lower in the 90 nm process of ID due to the increase of gm. 50

0 by about a factor of 2.
White noise is not sizably affected by L

0 0.2 0.4 0.6 0.8 1 1.2
0 0
As-drawn Gate Length [µm] variations since devices are operated in 0 0.2 0.4 0.6 0.8 1 1.2 0 0.2 0.4 0.6 0.8 1 1.2
Drain Current [mA] Drain Current [mA]
120
weak and moderate inversion. 300 300

100 For P-channel devices Kf is:
αW≈1 is found for all the devices, except
Equivalent Noise Resistance [Ω]

250
Equivalent Noise Resistance [Ω]

250
for NMOS with L=0.13 µm in the
130 nm process
dependent of the overdrive
Kf [J 10 -25 Hz (alpha-1)]

80 PMOS 130 nm process where αW≈1.2. 200 200

voltage VGS-VTH
60

larger for deviced with 150 150

40
L<0.5 µm in the 130 nm 130 nm process 130 nm process
100 100
process and with L<0.2 µm NMOS L > 0.13 µm PMOS
Linear fit
20
90 nm process
in the 90 nm process 50 offset = 6.85 +/- 1.90 50
Linear fit
offset = 1.82 +/- 2.12
PMOS slope = 1.01 +/- 0.02 slope = 0.97 +/- 0.02

lower in the 90 nm process.
0 0 0
-0.05 0 0.05 0.1 0.15 0.2 0 50 100 150 200 250 300
0 50 100 150 200 250 300
Gate Overdrive Voltage [V] nγ/g [Ω] nγ/g [Ω]
m m

1/f noise slope

2
130 nm process αf is independent of the drain
W=1000 µm current and of the device
1.5 |V |=0.6 V
DS
PMOS
geometry.
References
1 αf
f
α

[1] V. Re, M. Manghisoni, L. Ratti, V. Speziali, G. Traversi, "Survey of noise performances and scaling effects inDeep Submicron
Process 130 nm 90 nm
0.5 CMOS devices from different foundries", IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 2733-2740, Dec. 2005.
NMOS
Id=0.10 mA
Id=0.25 mA
Id=0.75 mA
Id=1.00 mA
NMOS 0.85 0.85
Id=0.50 mA [2] G. De Geronimo , P. O'Connor, "MOSFET optimization in deep submicron technology for charge amplifiers", IEEE Trans. Nucl.
0
PMOS 1.19 1.09 Sci., vol. 52, no. 6, pp. 3223-3232, Dec. 2005.
0 0.2 0.4 0.6 0.8 1 1.2
As-drawn Gate Length [µm]

Frontier Detectors for Frontier Physics, 10th Pisa Meeting on Advanced Detectors, La Biodola, Isola d'Elba, Italy, May 21-27, 2006.