B.E. (Information Technology) Third Semester (C.B.S.

)
Digital Electronics & Fundamentals of Microprocessor
CAT-1 (2021-22)
Time : 1.5 Hours Max. Marks : 30
_____________________________________________________________________

Notes : 1. All questions carry marks as indicated.

2. Solve Question 1 OR Questions No. 2.
3. Solve Question 3 OR Questions No. 4.
4. Solve Question 5 OR Questions No. 6.

1. a) Perform the following operations. 6

i) (27)10=(?)2=(?)BCD ii) (27)10=(?)8=(?)16
iii) (27)10=(?)excess-3=(?)BCD

b) State and prove the De-Morgan's theorems. 4

OR

2. a) Simplify the following functions. 4

i) Y = A (B + 𝐶̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝐴 𝐵 + 𝐴 𝐶̅ ) )
ii) Y = A B 𝐶̅ + A 𝐵̅ 𝐶̅ + 𝐴̅ B C + A B C + A 𝐵̅ C

b) Realize all the basic gates using NAND gates as well as NOR gates. 6

3. a) Minimize the following logic function using k-map and realize the circuit using NOR 6
gates only.

f (A, B, C, D)  M(1, 4, 6,9,10,11,14)

b) Expand the following equations to get standard SOP form 4

i) f (a, b, c)  ab  a c  bc
ii) f (a, b, c, d)  ( a  bc) (b  cd)

OR

4. a) Simplify the following functions using k-map : 6

i) f(A, B,C, D)  m(1, 3, 5, 8, 9, 10, 11, 15)  d(2)
ii) f (A, B, C, D)  M(1, 4, 6, 9, 10, 11, 14, 15)

b) What do you mean by minterms and maxterms ? Express the following function in the form 4
of minterms as well as maxterms.
Y  ABCDABCD ABCD  ABCD ABCDABCD

5. a) Design an half adder using logic gates. 4

 b) Design full subtractor circuit using logic Gates 6

OR

6. a) Design an half subtractor using logic gates. 4

b) Design full adder circuit using logic Gates 6