SCHOLASTIC ACHIEVEMENTS

• Department Rank 6 among M.Tech TA students in Dept. of Electrical Engg., IIT Bombay.
• Secured All India Rank 23 with 99.98%ile in GATE (EC) among 1,04,782 appeared candidates
• Secured 3rd position in B.Tech. with 9.46 DGPA in Electronics and Communication Engineering
• Selected in INSPIRE program, DST Govt. of India for being in top 1% students in 10th board exam.
AREA OF INTEREST
• Digital VLSI design, Computer Architecture
ACADEMIC PROJECTS AND SEMINAR
• M.Tech Project: Designing a System for SD Card
Guide: Prof. Madhav P. Desai, Electrical Engineering Dept., IIT Bombay. (Jul’20 - Jun’21)
◦ Objective :
Designing a system in which a SD card can communicate with the AJIT processor core.
◦ Work done:
∗ Designed the host controller for the SD card which will be suitable for fast data transfer.
∗ Designed an sd-spi interface for testing the host controller with an SD break-out board.
∗ Tested the host controller with an spi interface on a Digilent Basys 3 FPGA board.
∗ Ran synthesis and implementation on the design, optimized the number of FFs and LUTs.
• B.Tech Project: Drunken Driving Detection with Car Ignition Locking
Guide: Prof. Siladitya Sen, Heritage Institute of Technology, Kolkata. (Aug’17 - May’18)
◦ Developed a low cost Drunk Driving detection system which can lock a car automatically.
◦ Implemented the system using Python language in Raspberry Pi utilizing data from the sensor.
◦ Detected the drunken condition and can be used to send messages to relevant authority.
◦ Tested the prototype successfully in multiple scenarios with good accuracy.
• M.Tech Seminar: SPARC Assembly Language and Memory Management Unit in SPARC
Guide: Prof. Madhav P. Desai, Electrical Engineering Dept., IIT Bombay. (Jan’20 - Jun’20)
◦ Studied and got familiarized with SPARC ISA basics like register windows, floating point regis-
ters, memory stack etc.
◦ Studied virtual memory of general processor architectures SPARC implementation of Memory
Management Unit.
◦ Learned to write assembly language program for a SPARC processor.
RELEVANT COURSES

o VLSI Design o Algorithmic Design of Digital Systemso Processor Design

o VLSI Design Labo Hardware Description o Systems Design

COURSE PROJECTS AND ASSIGNMENTS

• 16x16 Dadda Multiplier
Instructor: Prof. Dinesh Sharma, Electrical Engineering Dept., IIT Bomabay. EE671 (Oct’2019)
◦ Designed a Dadda multiplier using VHDL with adder for the final stage
◦ Identified the critical path & computed the critical path delay in VHDL simulation.
• 32 bit Logarithmic Adder Using Brent-Kung Architecture
Instructor: Prof. Dinesh Sharma, Electrical Engineering Dept., IIT Bomabay. EE671 (Oct’2019)
◦ Designed a Brent-Kung logarithmic adder using synthesizable VHDL code.
◦ Identified the critical path & computed the critical path delay in simulation using test bench.
◦ Implemented a layout of a 16-bit Brent-Kung adder and extracted delays in Cadence.
• Elevator Controller
Instructor: Prof. Sachin Patkar, Electrical Engineering Dept., IIT Bombay. EE721 (Nov’2019)
◦ Designed an Elevator controller for three floors in synthesizable VHDL code.
◦ Implemented an FSM with seven states for proper operation of the elevator.
• Shift-Add Multiplier Using State Machine
Instructor: Prof. Sachin Patkar, Electrical Engineering Dept., IIT Bombay. EE721 (Oct’2019)
◦ Designed an unconventional shift-add multiplier which is more efficient.
◦ Implemented using a separate datapath and a state machine for controller.
• Laser Based Snooping Device
Instructor: Prof. P.C. Pandey, Electrical Engineering Dept., IIT Bombay. EE616 (Nov’2019)
◦ Designed a simple circuit for listening to sound on the other side of a glass window.
◦ The circuit would faithfully reproduce only the human voice by filtering the other noise.

SKILLS
• Languages: Verilog, VHDL, C, C++, Python.
• Tools and Hardware Platforms: Altera Quartus Prime, GHDL, Linux, Vivado
POSITIONS OF RESPONSIBILITY
• Teaching Assistant, Electrical Department, IIT Bombay.
◦ Digital Electronics (EE221), IIT Bombay
∗ Assisted the instructor in smooth functioning of classes, conducting tests, crib session and
evaluation process.
∗ Assisted and mentored/evaluated the weekly lab work of 3 groups of three students each.
◦ Electronic Design Lab (EE344), IIT Bombay
∗ Assisted and mentored/evaluated the weekly lab work of 3 students.
◦ Hardware Description (EE721), IIT Bombay
∗ Assisting the instructor in smooth functioning of online classes and conducting online tests.

INTERESTS AND HOBBIES

• Stood 2nd in Electronic Circuit Fabrication workshop held at Heritage Institute of Technology
• Played in Inter-school football competitions.