ADAMA UNIVERSITY

DEPARTMENT OF INFORMATION TECHNOLOGIES

NUMBER SYSTEM, NEGATIVE NUMBER REPRESENTATION AND LOGIC GATES

1.1 Number System
 First, we have to distinguish the difference between numbers and the symbols we
use to represent numbers.
 A number is a mathematical quantity, usually correlated in electronics to a
physical quantity such as voltage, current, or resistance
 There are many different types of numbers. Here are just a few types, for example:

WHOLE NUMBERS: 1, 2, 3, 4, 5, 6, 7, 8, 9 . . .
INTEGERS: -4, -3, -2, -1, 0, 1, 2, 3, 4 . . .
IRRATIONAL NUMBERS: ¼ (approx. 3.1415927), e (approx. 2.718281828),
square root of any prime
REAL NUMBERS: (All one-dimensional numerical values, negative and positive,
including zero, whole, integer, and irrational numbers)
COMPLEX NUMBERS: 3 - j4 , 34.5 └20o
 Different types of numbers find different application in the physical world.
 Every computer stores numbers, letters, & other special characters in a coded form.
Before going to the details of these codes, it is essential to have a basic understanding
of the number system. So the goal of this topic is to familiarize you with the basic
fundamentals of number system.
 There are various number systems
1.1.1 The Decimal Number System
 Uses number 10 as its base or radix.
Base is defined as the total number of digits available in the number system
 Has 10 symbol or digits ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 )
 The largest single digit is 9(one less than the base)
 Uses positional notation(units, tens, hundreds, thousands, etc) for numbers greater
than numbers 9
For example, the decimal number 4 8 5 6 is equal to:

(4 * 103) + (8*102) + (5 * 101) + (6 * 100 )

The weight of the nth digit of the number from the left of the decimal point is equal to
nth digit * 10n-1
The weight of the nth digit of the number from the right of the decimal point is equal
to:
nth digit * 10-n
Example:
6543.286 = (6 * 104-1) + (5*103-1) + (4*102-1) + (3*101-1) + (2*10-1) + (8*10-2) +
(6*10-3)
= (6 * 103) + (5*102) + (4*101) + (3*100) + (2*10-1) + (8*10-2) +
(6*10-3)
= 6000 + 500 + 40 + 3 + 0.2 + 0.08 + 0.006
= 6543.286

1
By Abraham Tesso
 ADAMA UNIVERSITY
DEPARTMENT OF INFORMATION TECHNOLOGIES

1.1.2 Binary Number System

 The base or radix is 2
 Has two symbols(0&1)
 The largest single digit is 1(one less than the base)
 Each position in binary number represents a power of the base (2). The right most position is the units
(20) position, the second is the 2`s(2 1) position, & proceeding in this way we have 4`s(2 2) position,
8`s(23) position, 16`s (24) position, & so on.
Example: Binary number 10101 (written as 101012)
= (1*24) + (0*23) + (1*22) + (0*21) + (1*20)
= 16 + 0 + 4 + 0 + 1
= 21
1.1.3 Octal Number System
 The base is 8
 There are only 8 digits: 0,1,2,3,4,5,6,7
 The largest single digit is 7
 Each position on octal number represents a power of the base(8).
When we compare the octal with the decimal, 0-7 in octal is the same as 0-7 in decimal but 10 in octal is
not the same as 10 in decimal because 10 in octal holds the position of 8 in decimal, off course 10 in octal
is the same as 8 in decimal.

1.1.4 Hexadecimal Number System

 The base is 16
 Has 16 single-character digits: 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F(The letters A to F represent numbers 10
to 15)
 Each position in the hexadecimal system represents a power of the base(16).

When we compare the hexadecimal with decimal, 0-9 in hexadecimal is the same as 0-9 in decimal but 10
in hexadecimal is not the same as 10 in decimal, off course 10 in hexadecimal is equal to 16 in decimal
because it holds the position of 16 in decimal.

1.1.5 Relationship Among Decimal, Hexadecimal, Octal & Binary Number

System
Decimal Hexadecimal Octal Binary
0 0 0 0
1 1 1 1
2 2 2 10
3 3 3 11
4 4 4 100
5 5 5 101
6 6 6 110
7 7 7 111
8 8 10 1000
9 9 11 1001
10 A 12 1010
11 B 13 1011
12 C 14 1100
13 D 15 1101
14 E 16 1110
15 F 17 1111
16 10 20 10000
17 11 21 10001
18 12 22 10010
19 13 23 10011

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By Abraham Tesso
 ADAMA UNIVERSITY
DEPARTMENT OF INFORMATION TECHNOLOGIES

20 14 24 10100

1.1.6 Why Binary?

‘Why do we go for binary numbers instead of decimal numbers?’ The reasons are as
follows:
1. The 1st reason is that the electronic & electrical components, by their very nature,
operate in a binary mode. Information is handled in the computer by
electronic/electrical components such as transistors, semiconductors, wires, etc all
of which can only indicate 2 states or conditions – on(1) or off(0). Transistors are
either conducting (1) or non-conducting (0); a voltage is present (1) or absent (0)
in wire. The binary number system, which has only two digits (0&1), is most
suitable for expressing the two possible states.
2. The second reason is that the computer circuits only have to handle two binary
digits rather than ten decimal digits. This greatly simplifies the internal circuit
design of computers, resulting in less expensive & more reliable circuits.
3. Finally, the binary system is used because everything that can be done in decimal
number system (addition, subtraction, division & multiplication) can also be done
in binary number system.

1.1.7 Binary Arithmetic

Addition
Rules
0+0=0
0+1=1
1+0=1 implies1+1+1=1, with carry of 1
1 + 1 = 0 plus a carry 1 to the next higher column

Example 1 Example 2
Binary Decimal
100 4 10111
+10 +2 + 10011
110 6 101010

Subtraction
Rules
I. 0 – 0 = 0
II. 1 – 1 = 0
III. 1—0 = 1
IV. 0—1 = 1, with a borrow from the next column
Example
a. 1110 b. 101 c. 10100
- 100 - 10 - 1011
1010 11 1001

3
By Abraham Tesso
 ADAMA UNIVERSITY
DEPARTMENT OF INFORMATION TECHNOLOGIES

1.1.8 Converting from One Number System to Another

The values that numbers have with a given number systems are largely determined by their positional
notation. Positional notation means that the position of one symbol relative to other symbols in a given
number system determines the value of that symbol. For example, the symbols 1 & 7 can represent either
17 or 71 depending upon their relative position to one another.
The decimal number 135 may be expanded as:
(135) 10 = 1*102+3*101+5*100
 The subscript 10 is used to indicate 135 is in base 10 number system.
 The number 10 in binary is not the same as 10 in decimal because the value of 1 in the binary is not the
same as the value of the 1 in the decimal.
 The binary number 1101 may be expanded as
(1101)2 =1*23+1*22+0*21+1*20
= (1*8)+(1*4)+(0*2)+(1*1)
= 8+4+0+1
= 1310
*A number X1 X2 X3 …Xn in base M can be expanded as
(X0 X1 X2 X3 …..Xn)M=X0*mn-1+X1*mn-2X2*mn-3+ …Xn-1*m1+Xn*m0 in base 10

1.1.9 Converting to Decimal from Another Base

Steps
1. Determine the positional value of each digit & multiply the obtained positional
values by the digits in the corresponding position.
2. Sum the products calculated in step 1. The total is the equivalent value in decimal
Example: Convert the following numbers to the decimal form.
a. (1001)2 b. (1101.11)2 c. (4603)8 d. (1A81)16
Solutions
a. (1001)2 = 1*23 + 0*22 + 0*21 + 1*21
=8+0+0+1
=9
b. (1101.11)2 = 1*23 + 1*22 + 0*21 + 1*20 + 1*2-1 + 1*2-2
1 1
=8+4+0+1+ +
2 4
= 13.75
c.(4603)8 = 4*83 + 6*82 + 0*81 + 3*80
= 2048 + 384 + 0 + 3 = 2435
d. (1A81)16 = 1*163 + A*162 + 8*161 + 1*160
= 4096 + 2560 + 128 + 1 = 6785
Exercise Convert the following numbers to decimal form
a) (1110.01)2 b) (210)3 c) (413)5 d) (6352)8 e) (2C5F)16
f) (2CD.A5)16 g) (21.2)3 h) (13.1)9

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By Abraham Tesso
 ADAMA UNIVERSITY
DEPARTMENT OF INFORMATION TECHNOLOGIES

1.1.10 Converting from Decimal to Another Base (Division

Remainder Technique)
Steps
Step 1. Divide the decimal number to be converted by the value of the new base.
Step 2 Record the remainder from step 1 as the rightmost digit (least significant digit) of the new base
number.
Step 3. Divide the quotient of the previous divide by the new base3.
Step 4: Record the remainder from step 3 as the next digit(to the left) of the number base number.
Repeat step 3 & 4, recording remainder from right to left until the quotient become zero in step 3. Note that
the last remainder thus obtained will be the most significant digit of the new base number.

Example

a. 2510 = ?2
Quotient Reminder

Reading
25/2 12 1
12/2 6 0
6/2 3 0
3/2 1 1
1<2 1

Hence, 2510 = (11001)2

b. (675)10 = ?16
Quotient Reminder
Reading

675/16 42 3
42/16 2 10
2<16 2

Hence, (675)10 = (2A3)16

1.1.11 Converting a Decimal Fraction to a Fractional in Base B

Steps
Step 1: Multiply the given decimal fraction by the base B.
Step 2: Repeat step 1 using as the multiplicand at each step the remaining fraction part is
identically zero, or until as many digit as desired have been generated. The successive
integral parts are the successive digits of the number in base B starting from the most
significant end.
Example Convert a. 0.4410 to quinary(base 5) b. (0.65)10 to binary

Solutions
Fractional Part Integral Part
Reading

a. 0.44*5= .20 2
0.20*5= .00 1

Hence, (.44)10 = (.21)5

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By Abraham Tesso
 ADAMA UNIVERSITY
DEPARTMENT OF INFORMATION TECHNOLOGIES

b. Here B =2
Fractional Part Integral Part

0.65*2 .30 1
0.30*2 .60 0

Reading
0.60*2 .20 1
0.20*2 .40 0
0.40*2 .80 0
0.80*2 .60 1
0.60*2 .20 1

1.1.12 Converting Decimal Number with Fractions to Binary.

 First change the integer part to its equivalent binary.
 Multiply the fractional part by 2 and take out the integer value, and again multiply
the fractional part of the result by 2 and take out the integer part, continue this until
the product is 0.
 Collect the integer values from top to bottom & concatenate with the integer part.

Ex. A) Convert 12.2510 to binary 1100.01

B) Convert3.1875 to binary 11.0011
1.1.13 Converting Binary with fraction to Decimal.
To convert a binary number Y1Y2Y3Y4Yn.d1d2d3..dm to decimal first convert the integer part to decimal by using
y1 y2 y3 y4…yn=y1*2n-1+y2*2n-2+….yj*2n-j+….+yn-1*21+yn*20=Q and convert the fractional part to decimal by using

d1d2d3…dm=d1*2-1+d2*2-2+d3*2-3+…+dj*2-j+..+dm*2-m=R
then decimal equivalence of y1 y2 y3 y4…..yn.d1d2…dm will be Q+R where Q is the
integer part and R is the fractional part.

Ex1 : Convert 11001-0101 to decimal

11001 = 1x24 + 1x23
+0x22+0x21+1x20= 16+8+1= 25= Q

0101 =0x2-1+1x2-2+0x2-3+1x2-4

= 0+¼+0+1/16 = 0.3125 = R

=>11001.0101 = 25.3125.

Ex 2: Convert 1000.1 to decimal

1000 = 1+23 +0+0+0=8

1= 1x2-1=½ = 0.5

1000.1 = 8.510

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By Abraham Tesso
 ADAMA UNIVERSITY, July 2010

Department of Information Technologies 7

By Abraham Tesso
 ADAMA UNIVERSITY, July 2010

1.1.14 Conversion from Binary with fraction to Octal/hexadecimal

 Group three/four digits together starting from the last digit of the integer part, and if there is less
number of digits add some zeros in the beginning.
 Group three/ four digits together starting from the first digit of the fractional part, and if there is less
number of digits add some zeros to the end.
 Covert each group of the integer and the fractional part to their equivalent Octal/hexadecimal and
collect the results by adding point (.) to separate the integer part from the fractional part.
Ex 1:- Covert 1010.01112 to octal
Ex2:- Covert 1110101.101112 to hexadecimal

1.1.15 Conversion from Octal or Hexadecimal with Fraction to Binary.

 Convert each Octal/hexadecimal digit to its equivalent 3/4-bit binary digit.
 Collect the binary sequences by separating the integer part binaries from the fractional part binaries
with point (.)

1.1.16 Conversion from Octal with fraction to hexadecimal

 To convert from Octal to hexadecimal, first convert the Octal to binary and then the binary to
hexadecimal
1.1.17 Conversion from Hexadecimal with fraction to octal
 To convert from hexadecimal to Octal, first convert the hexadecimal to binary and then the binary to Octal.

1.1.18 Conversion from Octal/Hexadecimal with Fraction to Decimal.

 To convert from Octal/hexadecimal to decimal, first convert to binary and –then the binary to
decimal.
Remark: -
 BCD numbers are useful whenever decimal information is transferred into or out of a digital
system. Examples of BCD systems are electronic ousters, digital voltmeter, and digital clocks; their
circuits can work with BCD numbers.

 BCD’s are easy for conversion but slower for processing than binary. And they have limited
numbers because with BCD we can represent only numbers 0000 for 0 and 100 for 9 and ,
1010,1011,1100,1101,1110, 1111 can’t be used because 1010 represent 10 in decimal at 10 in
decimal is 1010 0000 in BCD.
 Hexadecimals are used for computation and memory addressing.

1.1.19 Conversion of Non-Decimal Base to Another Non-Decimal Base

Step 1: Convert the original number to a decimal number(base 10)
Step 2: Convert the decimal number so obtained to the new base number.
Example 3526 = ?2
Step 1: Convert from base 6 to base 10
352= 3*62 + 5*61+2*60
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 ADAMA UNIVERSITY, July 2010

=14010
Step 2: Convert 14010 to base 2
Quotient Reminder
140/2 70 0

Reading
70/2 35 1 Hence, 14010 = (10001100)2
35/2 17 1
… … …

Thus, 3526 = (10001100)2

Example 2 : (111010)2 = ?8
Solution : Step 1 Convert from base 2 to base 10: (111010)2 = (58)10
Step 2: Convert 5810 to base 8: (58)10 = (72)8
Thus, (111010)2 = (72)8
Short Cut Methods

a. For Binary to Octal

1011102 = ?8
Hence, (101110)2 = 568

5
6
For Octal to Binary
438
011 Hence, 438 = 1000112
100
Note: 3 bits(23=8)are sufficient to represent any octal number in binary.
b. For Binary to Hexadecimal
Example 1
101111002 = ?16
Hence, (10111100)2 = (BC)16

B C
Example 2
011010010010 = ?16
Hence, (011010010010)2 = (692)16

6 9 2

c. For Hexadecimal to Binary

Example
8C416 = ?2
Hence, (8C4)16 = (100011000100)2
1000
1100 0100

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Note: 4 bits(24 = 16) are sufficient to represent any hexadecimal number to binary.

1.1.20 Summary of Conversion From One Base to Another Base

From base To base Method

2 10 Expand binary number in powers of 2
10 2 Factor the decimal number by 2
2 8 Group 3 binary digits together
8 2 Each Octal digit is converted to 3 binary digits
2 16 Group 4 binary digits together
16 2 Each hexadecimal digit is converted to 4 binary digits
8 10 Go from 8…….2…….10
10 8 Go from 10 … ..2……..8
16 10 Go from 16 …….2…….10
10 16 Go from 10 …….2…….16
8 16 Go from 8 …….2…….16
16 8 Go from 16 …….2…….8

Binary Arithmetic
Computer understands only the language of binary numbers. Therefore, the machine performs what is
called binary arithmetic (binary computation).
Binary Addition
Binary addition operates by the same rule as decimal addition, except that it is simpler. A carry to the
next higher order (or more significant) position occurs when the sum is decimal 2, that is, binary 10.
Therefore, the binary addition rules may be written as follows:
0+0=0
0+1=1
1+0=1
1+1=0 plus a carry of 1 into the next position
1+1+1=1 plus a carry of 1 into the next position.

The last case occurs when the two binary digits in a certain position are 1s and there is a carry from the
previous position.
Example1:
6+7 =13 110+111=1101
Example2
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 ADAMA UNIVERSITY, July 2010

19+31+10=60 10011 +11111+1010=111100

Binary Subtraction
It operates by the same rule as decimal subtraction. The rule is as follows;
0-0=0
1-0=1
1-1=0
10-1=1
Example:

11100 28 101101 45 11001.011

- 11010 -26 - 111 -7 - 111.110
00010 =2 101100 =38 10001.101

Binary Multiplication:
- It is a very simple process that operates by the following obvious rulers:
(a) Multiplying any number by 1 rules the multiplicand unchanged
0x1=0
1x1=1
(b) Multiplying any number by 0 produces 0
0x0=0
1x0=0
Ex1

Binary Division

That is, the process for dividing one binary number (the dividend) by another (the divisor) is based on
the rules for binary subtraction and multiplication and Similar to decimal division
Ex 1111101 /11001

11001 101

11001
11001
00000
1111101 ÷ 11001 = 101

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1.1.21 Representation of Negative Numbers

There are different ways of representing negative numbers in a computer.

I. Sign- Magnitude Representation.

In signed binary representation, the left-most bit is used to indicate the sign of the number.
Traditionally, 0 is used to denote a positive number and 1 is used to denote a negative number. But the
magnitude part will be the same for the negative and positive values. For example 11111111
represents-127 while, 01111111 represents + 127. We can now represent positive and negative
numbers, but we have reduced the maximum magnitude of these numbers to 127.
In a 5- bit representation we use the first bit for sign and the remaining 4- bits for the magnitude. So
using this 5 bit representation the range of number that can be represented is from -15 (11111) to
+15(01111)
Ex1 represent -12 using 5-bi sign magnitude representation
- first we convert 12 to binary i. e 1100
Now -12 = 11100
Ex2 Represent –24 using 8-bits
24=00011000
-24 = 1001100
In general for n-bit sign –magnitude representation the range of values that can be represented are –(2
n-1
-1 ) to (2 n-1-1).
i.e. –(2 n-1 )+ 1 to 2 n-1 –1
Note:
In sign magnitude representation zero can be represented as 0 or -0

This representation has two problems one is it reduces the maximum size of magnitude, and the second
one is speed efficiency to perform arithmetic and other operations.
For sign magnitude representation, correct addition and subtraction are relatively complex, involving
the comparison of signs and relative magnitude of the two numbers.
The solution to this problem is called the two’s complement representation.

1.1.22 One’s Complement.

In one’s complement representation, all positive integers are represented in their correct binary format.
For example +3 is represented as usual by 00000011. However, its complement, -3, is obtained by
complementing every bit in the original representation. Each 0 is transformed into a1 and each 1 into
a0. In our example, the one’s complement representation of -3 is 11111100.

Ex: +2 is 00000010
-2 is 11111101

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Note that in this representation positive numbers start with a 0 on the left, and negative numbers start
with a 1 on the left most bit.
Ex1. add –3 and 3 with word size 4
3 = 0011
-3=1100
sum =1111 (=0)
Ex2. Add -4 and +6
- 4 is 11111011
+ 6 is 00000110
the sum is (1) 00000001 the one in the parenthesis is the external carry.

Where 1 indicates a carry. The correct result should be 2 or 00000010.

In one’s complement addition and subtraction, if there is an external carry it should be added to get the
correct result. This indicates it requires additional circuitry for implementing this operation.

1.1.23 Two’s Complement Representation

In two’s complement representation, positive numbers are represented, as usual, in singed binary, just
like in one’s complement. The difference lies in the representation of negative numbers. A negative
number represented in two’s complement is obtained by first computing the one’s complement and then
add one.

Ex: +3 is represented in signed binary as 00000011

Its one’s complement representation is 11111100.
The two’s complement is obtained by adding one. It is 11111101.
Ex let’s try addition.
(3) 00000011
+ (5) +00000101
(8) 00001000
The result is correct
Ex2. Let’s try subtraction
(3) 000000011
(-5) + 111111011
111111110
Ex2 add +4 and -3(the subtraction is performed by adding the two’s complement).
+4 is 000000100
-3 is 111111101
The result is [1] 000000001

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If we ignore the external carry the result is 00000001 ( i. e 1 In decimal). This is the correct result. In
two’s complement, it is possible to add or subtract signed numbers, regardless of the sign. Using the
usual rules of binary addition, the result comes out correct, including the sign. The carry is ignored.
One’s complement may be used, but if one’s complement is used, special circuitry is required to “
correct the result”.

Carry and overflow

Ex (128) 10000000
+(129) 10000001
[257] =(1) 00000001

Where 1 indicates a carry. The result requires a ninth bit (bit 8, since the right- most bit is 0). It is the
carry bit.

The two’s complement representation has one anomaly not found with sign magnitude or one’s
complement. The bit pattern 1 followed by N-1 zeros is its own 2’s complement. To maintain sign bit
N
consistency, this bit pattern is assigned the value –2 for example, for 8-bit word,
-128 = 10000000
its 1’s complement =01111111
+1
=100000000 = -128

Overflow will occur in four situations, including: -

1/ The addition of large positive numbers.
2/ The addition of large negative numbers.
3/ The subtraction of a large positive number from a large negative numbers.
4/ The subtraction of a large negative number from a large positive number.

Overflow indicates that the result of an addition or subtraction requires more bits than are available in
the standard 8-bit register used to contain the result.

Fixed format representation: We now know how to represent signed integers: however, we have not
yet resolved the problem of magnitude. If we want to represent large integers, we will need several
bytes. In order to perform arithmetic operations efficiently, it is necessary to use a fixed number of
bytes, rather than a variable number. Therefore, once the number of bytes is chosen, the maximum
magnitude of the number that can be represented is fixed.
1.1.24 Subtraction by Use of Complements.
 Complements are mainly used for representing negative numbers and subtraction.
 In performing binary subtraction or addition of negative number by use of binary complements
only one procedure, addition, is needed as one can subtract by adding its complements.
 To subtract any number, positive or negative, substitute the required complement for the numbers to
be subtracted and then add.
If the result is
An ( n+1)-bit number, and the arithmetic is in
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Ones complement the (n+1) th bit, a carry, is added to the right most bit of the result. This process is
called an end-around carry.
Two’s complement discard the (n+1) th bit.

An n-bit number and the arithmetic is in

Ones complement, to read the binary value calculate the ones complement of the magnitude bits and
place a minus sign front of it.
Two’s complement, to read the binary value calculate the two’s complement of the magnitude bits and
place a minus sign in front of it.
Example:
Perform the following in ones and two’s complements in 5-bits.
A. 12-6
B. 6-12
C. -12-6
A= 12 B=6, A=01100 B=00110
Ones complement of -A=10011 & -B=11001
Two’s complement of - A= 10100 & -B= 11010
Example C:
Is wrong this is because the occurrence of overflow. Arithmetic overflow is that part of the result of an
operation which is lost because of the resulting value exceeds the capacity of the intended storage
location.

* Arithmetic overflow occurs when the sign bits of A and B are the same but the sign bit of the result
is different.
1.1.25 Floating-Point Representation
In this representation decimal numbers are represented with a fixed length format. In order not to waste
bits, the representation will normalize all the numbers. For example, 0.000123 wastes three zeroes on
the left before non -zero digits. These zeroes have no meaning except to indicate the position of the
-3
Decimal point. Normalizing this number result in .123x10 .123 is the normalized mantissa; -3 is the
exponent. We have normalized this by eliminating all the meaningless zeroes to the left of the first
non-zero digit and by adjusting the exponent.
Ex1: 22.1 is normalized as .221x102.
The general form of floating point representation is Mx10E where M is the mantissa, and E is the
exponent. It can be seen that a normalized number is characterized by a mantissa less than 1 and
greater than or equal to.1 all cases when the number is not zero.
To represent floating numbers in the computer system it should be normalized after converting to
binary number representation system.

Ex2 111.01 is normalized as .11101x23.

The mantissa is 11101. The exponent is 3.

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The general structure of floating point is

Sign Exponent Mantissa (significant)

In representing a number in floating point we use 1 bit for sing, some bits for exponent and the
remaining bit for mantissa.
In floating point representation the exponent is represented by a biased exponent (Characteristics).
n-1
Biased exponent = true exponent + excess 2 , where n is the number of bits reserved for the exponent.
Ex1.
Represent –234.375 in floating point using 7 bit for exponent and 16 bit for mantissa.
First we have to change to normalized binary
i. e 234 = 11101010
0.375= 0.011
234.375 = 11101010.011 = 0.11101010011x28
true exponent = 8
excess 2 n-1 = 2 7-1= 26= 64
Biased exponent = 8+26 = 8+64 = 72
= 100 1000 2
Therefore –234.375 is represented as
1 1001000 1110101001100000
Sign 7-bits 16 bits

Ex2. Represent 34.25 in floating point using 7 bit for exponent and 24 bits
for mantissa.
34.25 = 100010.0 12
The normalized form of 34.25 = .10001001x 26
n-1 7-1 6
True exponent = 6 + 2 = 2 = 6+2 =6+64=70
70 = 10001102

Therefore, 34.25 is represented as

0 1000110 100010010000…..0

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Floating Point Overflows

If there are 1 bit for the sign, N bit for the exponent and M bit for the mantissa (significant) we can
represent numbers as shown bellow.
N-1
Let n=2
To represent a number in floating point:

 Represent the number in normalized binary form.

 Find the biased exponent
 Change the biased exponent to binary
 Write the sing, the exponent in the exponent part and the mantissa in the mantissa part
 If there are fewer digits in the exponent add zeros to the left and for mantissa add zeros to the right.

1.1.26 Floating-Point Arithmetic

To perform floating-point arithmetic:
 First correct the numbers to binary with the same exponent (the highest)
 Apply the operator on the mantissa and take one of the exponent
 Normalize the result

Ex1. Find 23.375+ 41.25 using 7-bit for exponent and 10 bit for mantissa.
5 6
23.375= 10111.011 = 0.10111011x2 = 0.010111011x2
41.25 = 101001.01 = 0.10100101x26 =0.101001010x26
23.37 + 41.25 = 0.010111011x26+ 0.101001010x26
= (0.010111011+ 0.101001010)x26
= 0.1000000101x27
true exponent = 7
excess 2 n-1 = 2 7-1= 26= 64
Biased exponent = 7+26 =7+64 = 71
= 100 0111 2
0 1000111 1000000101
Sign 7-bits 10-bits

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LOGIC GATES
Digital signals and gates
A logic gate is an electronic circuit/device which makes the logical decisions. To arrive at this decisions, the most common
logic gates used are OR, AND, NOT, NAND, and NOR gates. The NAND and NOR gates are called universal gates. The
exclusive-OR gate is another logic gate which can be constructed using AND, OR and NOT gate.
Logic gates have one or more inputs and only one output. The output is active only for certain input combinations. Logic
gates are the building blocks of any digital circuit. Logic gates are also called switches. With the advent of integrated
circuits, switches have been replaced by TTL (Transistor Transistor Logic) circuits and CMOS circuits. Here I give example
circuits on how to construct simples gates.

While the binary numeration system is an interesting mathematical abstraction, we haven't yet seen its practical application
to electronics. This chapter is devoted to just that: practically applying the concept of binary bits to circuits. What makes
binary numeration so important to the application of digital electronics is the ease in which bits may be represented in
physical terms. Because a binary bit can only have one of two different values, either 0 or 1, any physical medium capable
of switching between two saturated states may be used to represent a bit. Consequently, any physical system capable of
representing binary bits is able to represent numerical quantities, and potentially has the ability to manipulate those
numbers. This is the basic concept underlying digital computing.

Electronic circuits are physical systems that lend themselves well to the representation of binary numbers. Transistors, when
operated at their bias limits, may be in one of two different states: either cutoff (no controlled current) or saturation
(maximum controlled current). If a transistor circuit is designed to maximize the probability of falling into either one of
these states (and not operating in the linear, or active, mode), it can serve as a physical representation of a binary bit. A
voltage signal measured at the output of such a circuit may also serve as a representation of a single bit, a low voltage
representing a binary "0" and a (relatively) high voltage representing a binary "1." Note the following transistor circuit:

Transistor in saturation

In this circuit, the transistor is in a state of saturation by virtue of the applied input voltage (5 volts) through the two-position
switch. Because it's saturated, the transistor drops very little voltage between collector and emitter, resulting in an output
voltage of (practically) 0 volts. If we were using this circuit to represent binary bits, we would say that the input signal is a
binary "1" and that the output signal is a binary "0." Any voltage close to full supply voltage (measured in reference to
ground, of course) is considered a "1" and a lack of voltage is considered a "0."

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Alternative terms for these voltage levels are high (same as a binary "1") and low (same as a binary "0"). A general term for
the representation of a binary bit by a circuit voltage is logic level. Moving the switch to the other position, we apply a
binary "0" to the input and receive a binary "1" at the output:

Transistor in cutoff

What we've created here with a single transistor is a circuit generally known as a logic gate, or simply gate. A gate is a
special type of amplifier circuit designed to accept and generate voltage signals corresponding to binary 1's and 0's. As such,
gates are not intended to be used for amplifying analog signals (voltage signals between 0 and full voltage). Used together,
multiple gates may be applied to the task of binary number storage (memory circuits) or manipulation (computing circuits),
each gate's output representing one bit of a multi-bit binary number. Just how this is done is a subject for a later chapter.
Right now it is important to focus on the operation of individual gates. The gate shown here with the single transistor is
known as an inverter, or NOT gate, because it outputs the exact opposite digital signal as what is input. For convenience,
gate circuits are generally represented by their own symbols rather than by their constituent transistors and resistors. The
following is the symbol for an inverter:

Inverter, or NOT gate

An alternative symbol for an inverter is shown here:

Notice the triangular shape of the gate symbol, much like that of an operational amplifier. As was stated before, gate circuits
actually are amplifiers. The small circle, or "bubble" shown on either the input or output terminal is standard for
representing the inversion function. As you might suspect, if we were to remove the bubble from the gate symbol, leaving
only a triangle, the resulting symbol would no longer indicate inversion, but merely direct amplification. Such a symbol and
such a gate actually do exist, and it is called a buffer, the subject of the next section.

Like an operational amplifier symbol, input and output connections are shown as single wires, the implied reference point
for each voltage signal being "ground." In digital gate circuits, ground is almost always the negative connection of a single
voltage source (power supply). Dual, or "split," power supplies are seldom used in gate circuitry. Because gate circuits are
amplifiers, they require a source of power to operate. Like operational amplifiers, the power supply connections for digital

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gates are often omitted from the symbol for simplicity's sake. If we were to show all the necessary connections needed for
operating this gate, the schematic would look something like this:

Power supply conductors are rarely shown in gate circuit schematics, even if the power supply connections at each gate are.
Minimizing lines in our schematic, we get this:

"Vcc" stands for the constant voltage supplied to the collector of a bipolar junction transistor circuit, in reference to ground.
Those points in a gate circuit marked by the label "V cc" are all connected to the same point, and that point is the positive
terminal of a DC voltage source, usually 5 volts.

As we will see in other sections of this chapter, there are quite a few different types of logic gates, most of which have
multiple input terminals for accepting more than one signal. The output of any gate is dependent on the state of its input(s)
and its logical function.

One common way to express the particular function of a gate circuit is called a truth table. Truth tables show all
combinations of input conditions in terms of logic level states (either "high" or "low," "1" or "0," for each input terminal of
the gate), along with the corresponding output logic level, either "high" or "low." For the inverter, or NOT, circuit just
illustrated, the truth table is very simple indeed:

NOT gate truth table

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Truth tables for more complex gates are, of course, larger than the one shown for the NOT gate.
A gate's truth table must have as many rows as there are possibilities for unique input combinations. For a single-input gate
like the NOT gate, there are only two possibilities, 0 and 1. For a two input gate, there are four possibilities (00, 01, 10, and
11), and thus four rows to the corresponding truth table. For a three-input gate, there are eight possibilities (000, 001, 010,
011, 100, 101, 110, and 111), and thus a truth table with eight rows are needed. The mathematically inclined will realize that
the number of truth table rows needed for a gate is equal to 2 raised to the power of the number of input terminals.

REVIEW:

 In digital circuits, binary bit values of 0 and 1 are represented by voltage signals measured in reference to a
common circuit point called ground. An absence of voltage represents a binary "0" and the presence of full DC
supply voltage represents a binary "1."
 A logic gate, or simply gate, is a special form of amplifier circuit designed to input and output logic level voltages
(voltages intended to represent binary bits). Gate circuits are most commonly represented in a schematic by their
own unique symbols rather than by their constituent transistors and resistors.
 Just as with operational amplifiers, the power supply connections to gates are often omitted in schematic diagrams
for the sake of simplicity.² A truth table is a standard way of representing the input/output relationships of a gate
circuit, listing all the possible input logic level combinations with their respective output logic levels.

Multiple-input gates
Inverters and buffers exhaust the possibilities for single-input gate circuits. What more can be done with a single logic signal
but to buffer it or invert it? To explore more logic gate possibilities, we must add more input terminals to the circuit(s).
Adding more input terminals to a logic gate increases the number of input state possibilities. With a single-input gate such
as the inverter or buffer, there can only be two possible input states: either the input is "high" (1) or it is "low" (0). As was
mentioned previously in this chapter, a two input gate has four possibilities (00, 01, 10, and 11). A three-input gate has eight
possibilities (000, 001, 010, 011, 100, 101, 110, and 111) for input states. The number of possible input states is equal to two
to the power of the number of inputs:
Number of possible input states = 2n
Where,
n = Number of inputs

This increase in the number of possible input states obviously allows for more complex gate behavior. Now, instead of
merely inverting or amplifying (buffering) a single "high" or "low" logic level, the output of the gate will be determined by
whatever combination of 1's and 0's is present at the input terminals.

Since so many combinations are possible with just a few input terminals, there are many different types of multiple-input
gates, unlike single-input gates which can only be inverters or buffers. Each basic gate type will be presented in this section,
showing its standard symbol, truth table, and practical operation. The actual TTL circuitry of these different gates will be
explored in subsequent sections.

The AND gate

One of the easiest multiple-input gates to understand is the AND gate, so-called because the output of this gate will be
"high" (1) if and only if all inputs (first input and the second input and . . .) are "high" (1). If any input(s) are "low" (0), the
output is guaranteed to be in a "low" state as well.

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In case you might have been wondering, AND gates are made with more than three inputs, but this is less common than the
simple two-input variety.
A two-input AND gate's truth table looks like this:

What this truth table means in practical terms is shown in the following sequence of illustrations, with the 2-input AND gate
subjected to all possibilities of input logic levels. An LED (Light-Emitting Diode) provides visual indication of the output
logic level:

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It is only with all inputs raised to "high" logic levels that the AND gate's output goes "high," thus energizing the LED for
only one out of the four input combination states.

The NAND gate

A variation on the idea of the AND gate is called the NAND gate. The word "NAND" is a verbal contraction of the words
NOT and AND. Essentially, a NAND gate behaves the same as an AND gate with a NOT (inverter) gate connected to the
output terminal. To symbolize this output signal inversion, the NAND gate symbol has a bubble on the output line. The truth
table for a NAND gate is as one might expect, exactly opposite as that of an AND gate:

As with AND gates, NAND gates are made with more than two inputs. In such cases, the same general principle applies: the
output will be "low" (0) if and only if all inputs are "high" (1). If any input is "low" (0), the output will go "high" (1)

The OR gate
Our next gate to investigate is the OR gate, so-called because the output of this gate will be "high" (1) if any of the inputs
(frst input or the second input or . . .) are "high" (1). The output of an OR gate goes "low" (0) if and only if all inputs are
"low" (0).

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The following sequence of illustrations demonstrates the OR gate's function, with the 2-inputs experiencing all possible
logic levels. An LED (Light-Emitting Diode) provides visual indication of the gate's output logic level:

A condition of any input being raised to a "high" logic level makes the OR gate's output go "high," thus energizing the LED
for three out of the four input combination states.

The NOR gate

As you might have suspected, the NOR gate is an OR gate with its output inverted, just like a NAND gate is an AND gate
with an inverted output.

NOR gates, like all the other multiple-input gates seen thus far, can be manufactured with more than two inputs. Still, the
same logical principle applies: the output goes "low" (0) if any of the inputs are made "high" (1). The output is "high" (1)
only when all inputs are "low" (0).

The Negative-AND gate

A Negative-AND gate functions the same as an AND gate with all its inputs inverted (connected through NOT gates). In
keeping with standard gate symbol convention, these inverted inputs are signified by bubbles. Contrary to most peoples' first

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instinct, the logical behavior of a Negative-AND gate is not the same as a NAND gate. Its truth table, actually, is identical to
a NOR gate:

The Negative-OR gate

Following the same pattern, a Negative-OR gate functions the same as an OR gate with all its inputs inverted. In keeping
with standard gate symbol convention, these inverted inputs are signified by bubbles. The behavior and truth table of a
Negative-OR gate is the same as for a NAND gate:

The Exclusive-OR gate

The last six gate types are all fairly direct variations on three basic functions: AND, OR, and NOT. The Exclusive-OR gate,
however, is something quite different.

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Exclusive-OR gates output a "high" (1) logic level if the inputs are at different logic levels, either 0 and 1 or 1 and 0.
Conversely, they output a "low" (0) logic level if the inputs are at the same logic levels. The Exclusive-OR (sometimes
called XOR) gate has both a symbol and a truth table pattern that is unique:

There are equivalent circuits for an Exclusive-OR gate made up of AND, OR, and NOT gates, just as there were for NAND,
NOR, and the negative-input gates. A rather direct approach to simulating an Exclusive-OR gate is to start with a regular
OR gate, then add additional gates to inhibit the output from going "high" (1) when both inputs are "high" (1):

In this circuit, the final AND gate acts as a buffer for the output of the OR gate whenever the NAND gate's output is high,
which it is for the first three input state combinations (00, 01, and 10). However, when both inputs are "high" (1), the NAND
gate outputs a "low" (0) logic level, which forces the final AND gate to produce a "low" (0) output.

Another equivalent circuit for the Exclusive-OR gate uses a strategy of two AND gates with inverters, set up to generate
"high" (1) outputs for input conditions 01 and 10. A final OR gate then allows either of the AND gates' "high" outputs to
create a final "high" output:

Exclusive-OR gates are very useful for circuits where two or more binary numbers are to be compared bit-for-bit, and also
for error detection (parity check) and code conversion (binary to Grey and visa-versa).

The Exclusive-NOR gate

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Finally, our last gate for analysis is the Exclusive-NOR gate, otherwise known as the XNOR gate. It is
equivalent to an Exclusive-OR gate with an inverted output. The truth table for this gate is exactly opposite as for
the Exclusive-OR gate:

As indicated by the truth table, the purpose of an Exclusive-NOR gate is to output a "high" (1) logic level
whenever both inputs are at the same logic levels (either 00 or 11).

REVIEW:
 Rule for an AND gate: output is "high" only if first input and second input are both "high."
 Rule for an OR gate: output is "high" if input A or input B are "high."
 Rule for a NAND gate: output is not "high" if both the first input and the second input are "high."
 Rule for a NOR gate: output is not "high" if either the first input or the second input are "high."
 A Negative-AND gate behaves like a NOR gate.
 A Negative-OR gate behaves like a NAND gate.
 Rule for an Exclusive-OR gate: output is "high" if the input logic levels are different.
 Rule for an Exclusive-NOR gate: output is "high" if the input logic levels are the same.

Boolean Algebra and Logic Circuits

Symbolic Logic

Boolean algebra derives its name from the mathematician George Boole. Symbolic Logic
uses values, variables and operations :

 True is represented by the value 1.

 False is represented by the value 0.

Variables are represented by letters and can have one of two values, either 0 or 1. Operations
are functions of one or more variables.

 AND is represented by X.Y

 OR is represented by X + Y
 NOT is represented by X' . Throughout this lesson the X' form will be used and
sometime !X will be used.

These basic operations can be combined to give expressions.

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Example :

 X
 X.Y
 W.X.Y + Z

Precedence

As with any other branch of mathematics, these operators have an order of precedence. NOT
operations have the highest precedence, followed by AND operations, followed by OR
operations. Brackets can be used as with other forms of algebra. e.g.

X.Y + Z and X.(Y + Z) are not the same function.

Function Definitions

The logic operations given previously are defined as follows :

Define f(X,Y) to be some function of the variables X and Y.

f(X,Y) = X.Y
 1 if X = 1 and Y = 1
 0 Otherwise
f(X,Y) = X + Y
 1 if X = 1 or Y = 1
 0 Otherwise
f(X) = X'
 1 if X = 0
 0 Otherwise

Truth Tables

Truth tables are a means of representing the results of a logic function using a table. They are
constructed by defining all possible combinations of the inputs to a function, and then
calculating the output for each combination in turn. For the three functions we have just
defined, the truth tables are as follows.

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Truth tables may contain as many input variables as desired

F(X,Y,Z) = X.Y + Z

X Y Z F(X,Y,Z)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

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Logic Minimization and Karnaugh Maps

As we found above, given a truth table, it is always possible to write down a correct logic expression
simply by forming an OR of the ANDs of all input variables for which the output is true (Q = 1).
However, for an arbitrary truth table such a procedure could produce a very lengthy and cumbersome
expression which might be needlessly inefficient to implement with gates.

There are several methods for simplification of Boolean logic expressions. The process is usually called
\logic minimization", and the goal is to form a result which is efficient. Two methods we will discuss
are algebraic minimization and Karnaugh maps. For very compli- cated problems the former method
can be done using special software analysis programs. Karnaugh maps are also limited to problems
with up to 4 binary inputs.

Let's start with a simple example. The table below gives an arbitrary truth table involving 2 logic
inputs.
Table 1: Example of simple arbitrary truth table.

There are two overall stategies:

1. Write down an expression directly from the truth table. Use Boolean algebra, if desired, to simplify.
2. Use Karnaugh mapping (\K-map"). This is only applicable if there are _ 4 inputs. In our example
above, we can use two different ways of writing down a result directly from the truth table. We can
write down all TRUE terms and OR the result. This gives
Q = A’B’ + AB’ + AB
While correct, without further simplification this expression would involve 3 2-input AND gates, 2
inverters, and 1 3-input OR gate.

Alternatively, one can write down an expression for all of the FALSE states of the truth table. This is
simpler in this case:
Q’ = AB’ -> Q = (AB’)’ = A’ + B
where the last step results from Eqn. 3. Presumably, the two expressions can be found to be equivalent
with some algebra. Certainly, the 2nd is simpler, and involves only an inverter and one 2-input OR
gate.

Finally, one can try a K-map solution. The first step is to write out the truth table in the form below,
with the input states the headings of rows and columns of a table, and the corresponding outputs within,
as shown below.

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Table 2: K-map of truth table.

The steps/rules are as follows:

1. Form the 2-dimensional table as above. Combine 2 inputs in a “gray code" way
2. Form groups of 1's and circle them; the groups are rectangular and must have sides of length 2n X 2m,
where n and m are integers 0; 1; 2; : : :.
3. The groups can overlap.
4. Write down an expression of the inputs for each group.
5. OR together these expressions. That's it.
6. Groups can wrap across table edges.
7. As before, one can alternatively form groups of 0's to give a solution for Q’.
8. The bigger the groups one can form, the better (simpler) the result.
9. There are usually many alternative solutions, all equivalent, some better than others
depending upon what one is trying to optimize.

Table2 shown above is one way of doing it:

The two groups we have drawn are A’ and B. So the solution (as before) is:

Q = A’ + B

Exercise 1: Show K-Map, Boolean expression and Logic circuit for 3-digit prime finder

Exercise 2: Show K-Map, Boolean expression and Logic circuit for 4-digit prime finder.

The Karnaugh map

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The Karnaugh map, also known as a Veitch diagram (K-map or KV-map for short), is a tool to
facilitate management of Boolean algebraic expressions.

A Karnaugh map is unique in that only one variable changes value between squares, in other words, the
rows and columns are ordered according to the principles of Gray code.

History and nomenclature

The Karnaugh map was invented in 1953 by Maurice Karnaugh, a telecommunications engineer at Bell
Labs.
Usage in Boolean logic
Normally, extensive calculations are required to obtain the minimal expression of a Boolean function,
but one can use a Karnaugh map instead.

Problem solving uses

 Karnaugh maps make use of the human brain's excellent pattern-matching capability to decide
which terms should be combined to get the simplest expression.
 K-maps permit the rapid identification and elimination of potential race hazards, something that
boolean equations alone cannot do.
 A Karnaugh map is an excellent aid for simplification of up to six variables, but with more
variables it becomes hard even for our brain to discern optimal patterns.
 For problems involving more than six variables, solving the boolean expressions is more
preferred than the Karnaugh map.

Karnaugh maps also help teach about Boolean functions and minimization.
Properties

A mapping of minterms on a Karnaugh map

A Karnaugh map may have any number of variables, but usually works best when there are only a few -
between 2 and 6 for example. Each variable contributes two possibilities to each possibility of every
other variable in the system. Karnaugh maps are organized so that all the possibilities of the system are
arranged in a grid form and between two adjacent boxes only one variable can change value. This is
what allows it to reduce hazards.

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When using a Karnaugh map to derive a minimized function, one "covers" the ones on the map by
rectangular "coverings" that contain a number of boxes equal to a power of 2 (for example, 4 boxes in a
line, 4 boxes in a square, 8 boxes in a rectangle, etc). Once a person has covered the ones, a term of a
sum of products is produced by finding the variables that do not change throughout the entire covering,
and taking a 1 to mean that variable and a 0 as the complement of that variable. Doing this for every
covering gives you a matching function.

One can also use zeros to derive a minimized function. The procedure is identical to the procedure for
ones except that each term is a term in a product of sums - and a 1 means the complement of the
variable while 0 means the variable non-complemented.

Each square in a Karnaugh map corresponds to a minterm (and maxterm). The picture to the right
shows the location of each minterm on the map.

Size of map
In a Karnaugh map with n variables, a Boolean term mentioning k of them will have a corresponding
rectangle of area 2n − k. Common sized maps are of 2 variables which is a 2x2 map; 3 variables which is
a 2x4 map; and 4 variables which is a 4x4 map (shown below).

2 variable map 3 variable map 4 variable map

Example
Consider the following function of four variables (which, in binary, has a maximum number of
combinations of 16):
f(A,B,C,D) = E(6,8,9,10,11,12,13,14)
The values inside E lists the minterms to map (i.e., which rows have output 1 in the truth table).
Truth table

Using the defined minterms, the truth table can be created:

# A B C D f(A,B,C,D)
0 0 0 0 0 0
1 0 0 0 1 0
2 0 0 1 0 0
3 0 0 1 1 0
4 0 1 0 0 0
5 0 1 0 1 0
6 0 1 1 0 1
7 0 1 1 1 0
8 1 0 0 0 1

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9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 0

Map
K-map showing minterms and boxes covering the desired minterms. The input variables can be
combined in 16 different ways, so our Karnaugh map has to have 16 positions. The most convenient
way to arrange this is in a 4x4 grid.

The binary digits in the map represent the function's output for any given combination of inputs. We
write 0 in the upper leftmost corner of the map because f = 0 when A = 0, B = 0, C = 0, D = 0. Similarly
we mark the bottom right corner as 1 because A = 1, B = 0, C = 1, D = 0 gives f = 1. Note that the
values are ordered in a Gray code, so that precisely one variable flips between any pair of adjacent
cells.

f(A,B,C,D) = E(6,8,9,10,11,12,13,14)

After the Karnaugh map has been constructed our next task is to find the minimal terms to use in the
final expression. These terms are found by encircling groups of 1's in the map. The encirclings must be
rectangular and must have an area that is a power of two (i.e. 1, 2, 4, 8, …). The rectangles should be as
large as possible without containing any 0's. The optimal encirclings in this map are marked by the
green, red and blue lines.

For each of these encirclings we find those variables that have the same state in each of the fields in the
encircling. For the first encircling (the red one) we find that:

 The variable A maintains the same state (1) in the whole encircling, therefore it should be
included in the term for the red encircling.
 Variable B does not maintain the same state (it shifts from 1 to 0), and should therefore be
excluded.
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 C does not change: it is always 0.

 D changes.

Thus the first term in the Boolean expression is AC’. For the green encircling we see that A and B
maintain the same state, but C and D change. B is 0 and has to be negated before it can be included.
Thus the second term is AB’.

In the same way, the blue rectangle gives the term BCD’ and so the whole expression is:
AC’ + AB’+ BCD’

Toroidally connected

The grid is toroidally connected, which means that the rectangles can wrap around edges, so AD’ is a valid
term, although not part of the minimal set — this covers minterms 8, 10, 12, & 14.

Perhaps the hardest-to-visualize wrap-around term is B’D’ which covers the four corners — this covers
minterms 0, 2, 8, 10.

2 variable maps

The following are all the possible 2 variable, 2x2 Karnaugh maps. Listed with each is the minterms as a
function of E() and the race hazard free (see previous section) minimum equation.

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E(); K=0 E(1); K=A'B' E(2); K=AB' E(3); K=A'B

E(4); K=AB E(1,2); K=B' E(1,3); K=A' E(1,4); K=A'B' + AB

E(2,3); K=AB' + A'B E(2,4); K=A E(3,4); K=B E(1,2,3); K=A' + B'

E(1,2,4); K=A + B' E(1,3,4); K=A' + B E(2,3,4); K=A + B E(1,2,3,4); K=1

Problems with Karnaugh maps

Karnaugh maps generally become more cluttered and hard to interpret when adding more
variables. A general rule is that Karnaugh maps work well for up to four variables, and shouldn't
be used at all for more than six variables. For expressions with larger numbers of variables, the
Quine-McCluskey algorithm can be used. Nowadays in general the minimization process is
carried out by computer, for which the Espresso heuristic logic minimizer has become the
standard minimization program.

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Combinational Arithmetic Circuits

Introduction
Arithmetic circuits are the ones which perform arithmetic operations like addition,
subtraction, multiplication, division, parity calculation. Most of the time, designing these
circuits is the same as designing muxers, encoders and decoders.
In the next few pages we will see few of these circuits in detail.
Adders
Adders are the basic building blocks of all arithmetic circuits; adders add two binary
numbers and give out sum and carry as output. Basically we have two types of adders.
 Half Adder.
 Full Adder.

Half Adder
Adding two single-bit binary values X, Y produces a sum S bit and a carry out C-out bit. This
operation is called half addition and the circuit to realize it is called a half adder.
Truth Table
X Y SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Symbol Circuit

37
 ADAMA UNIVERSITY, July 2010

Kmap-CARRY

Tr
ut
h
Kmap-SUM T
a
S (X,Y) = (1,2) bl
S = X'Y + XY' e
S=X Y S CA
CARRY(X,Y) = (3) CARRY = XY X Y Z U RR
M Y
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
Full Adder 1 1 0 0 1
1 1 1 1 1
Full adder takes a three-bits input. Adding two single-bit binary values X, Y with a carry input bit C-in
produces a sum bit S and a carry out C-out bit.

SUM (X,Y,Z) = (1,2,4,7)

CARRY (X,Y,Z) = (3,5,6,7)

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SUM = X'Y'Z + XY'Z' + X'YZ' CARRY = XY + XZ + YZ
SUM = X Y Z

Full Adder using AND-OR

The below implementation shows implementing the full adder with AND-OR gates, instead of
using XOR gates. The basis of the circuit below is from the above Kmap.

Circuit-SUM Circuit-CARRY

Full Adder using AND-OR

Circuit-SUM Circuit-CARRY

Subtracter
Subtracter circuits take two binary numbers as input and subtract one binary number input from the
other binary number input. Similar to adders, it gives out two outputs, difference and borrow (carry-in
the case of Adder). There are two types of subtracters.
 Half Subtracter.
 Full Subtracter.

Half Subtracter
The half-subtracter is a combinational circuit which is used to perform subtraction of two bits. It has
two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow). The logic
symbol and truth table are shown below.

Symbol
Truth Table
X Y D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

From the above table we can draw the Kmap as shown below for "difference" and "borrow".
The boolean expression for the difference and Borrow can be written.

From the equation we can draw the half-subtracter as shown in the figure below.

Full Subtracter

A full subtracter is a combinational circuit that performs subtraction involving three bits,
namely minuend, subtrahend, and borrow-in. The
logic symbol and truth table are shown below. Truth Table
Bi Bou
Symbol X Y D
n t
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
From above table we can draw the Kmap as shown below for "difference" and "borrow". The
boolean expression for difference and borrow can be written.

D = X'Y'Bin + X'YBin' + XY'Bin' + XYBin

= (X'Y' + XY)Bin + (X'Y + XY')Bin'
= (X Y)'Bin + (X Y)Bin'
= X Y Bin
Bout = X'.Y + X'.Bin + Y.Bin

From the equation we can draw the half-subtracter as shown in figure below.

From the above expression, we can draw the circuit below. If you look carefully, you will see
that a full-subtracter circuit is more or less same as a full-adder with slight modification.