Page 1 of 8 2019-MIC-0981

Electrically safe variable speed drive for

underground mining applications
Galina Mirzaeva∗ , Senior Member, IEEE, Douglas Carter, Muslem Uddin, Student Member, IEEE, and Peter Stepien
School of Electrical Engineering and Computing, The University of Newcastle, Callaghan, NSW 2308, Australia
∗
e-mail: galina.mirzaeva@newcastle.edu.au

Abstract—Common-mode-voltage (CMV) is a well-known

Transformer AC Motor
source of bearing currents and electromagnetic interference Secondary
Line Diode
Inverter
Chokes Rectifier
(EMI) in industrial applications. In underground earthing and
protection environment, CMV is associated with potentially
undetectable fault currents, due to their diversion away from
the protection circuit. An ideal solution to these problems would DC link
Capacitor
be such a VSD that creates minimum or zero CMV and removes
the alternative paths for the fault currents. ICM = 0 VCM = 0
Previous study performed by the authors has suggested that,
amongst the existing drive topologies used by the industry, a
2-level Inverter with Active Front End (AFE) would be ideally
suited for CMV elimination. This paper develops a control strat-
egy for the VSD based on AFE Inverter such that it eliminates
CMV, minimises EMI and optimizes harmonic distortion at the
drive input and output sides.
To validate the proposed strategy, a laboratory prototype VSD
has been developed and the test environment has been set up to (a) Standard VSD and associated problems
represent an underground mining electrical system. Experiments
have confirmed that the prototype VSD generates practically no
Transformer
CMV, thus eliminating the EMI problem. Under an earth fault, Secondary
EMC Diode
AC Motor
Filter Inverter
the fault current flows into the designated protection circuit, thus Rectifier
providing the required electrical safety of the proposed VSD.
Index Terms—AC Motor Drives, AC motor protection, Com-
DC link
mon Mode Voltage, Electromagnetic Interference, Back to Back Capacitor
Converter, Modulation, Mining Industry, Mining Industry Safety. ICM = 0 VCM = 0

I. I NTRODUCTION
Variable Speed Drives (VSDs) are used in many under-
ground mining applications, including shuttle cars, haulers,
continuous miners, etc. One challenge associated with the
use of VSDs in underground environment is Common Mode
(b) The existing solution used in underground mining
Voltage (CMV) appearing at the floating star point of an
electrical motor fed from a VSD. It is responsible for a variety
Transformer
of issues, including electromagnetic interference (EMI) with Secondary Line Inverter
AC Motor

other devices [1] and bearing currents in electric machines Chokes

[2]. Additionally, the CMV forms capacitive coupling with the

frame and feeds Common Mode Current into the Earth cable. DC link
This current creates a notable voltage drop at the Neutral to Capacitor
R
Earth Resistor (NER) of the Feed Transformer, which creates NER

EMI with other underground equipment.

Fig.1a illustrates the problem. It shows a standard VSD
connected between the Transformer secondary and the AC
Motor. Note a significant noise pollution of the Input Voltage
(Vin ) causing EMI, and a significant Common Mode Voltage
(Vcm ), which is responsible for this pollution. It causes Icm
to flow into RN ER , creating the pollution component VN ER .
(c) Solution proposed in this paper
Also note a high distortion of the Input Current (Iin ), which
is due to the use of a Diode Rectifier as the VSD front end. Fig. 1: CMV problems and solutions in mining applications.
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The currently adopted solution for this problem is an Elec-

tromagnetic Compatibility (EMC) Filter connected between
the Transformer and the VSD. It improves the Input Current,
making it much more sinusoidal. To address the CMV prob-
lem, an additional capacitor is connected between the EMC
Filter star point and the Earth cable. This solution is illustrated (a) Standard (2 level) inverter
in Fig.1b. Note that the Common Mode Voltage (Vcm ) is
even higher than in the previous case. However, the EMC
Filter provides a low impedance path for the Common Mode
Current, effectively shorting it. The high frequency noise is
contained inside the drive and causes no voltage drop on the
NER (VN ER ≈ 0). Thus pollution of the Input Voltage (Vin )
is reduced. Also, due to the filter action, the input current (Iin )
(b) Standard (2 level) inverter with AFE
is much more sinusoidal than in the previous case.
Unfortunately, this solution has an undesirable side effect. Fig. 2: Candidate VSD inverter topologies.
The EMC Filter provides a low impedance path not only for
the Common Mode Current, but also for the Fault Current.
In case of an earth fault, the Fault Current, which is high used carrier-based PWM, this paper utilises Space Vector
frequency in nature, will flow along the same path shown in Modulation (SVM) and builds a new level of pulse pattern
Fig.1b by a red arrow. Only a small part of the Fault Current optimisation, based on minimisation of a given cost function.
will reach the NER. The current measured in the NER by a The remainder of the paper is organised as follows. Chapter
protection circuit may be below the fault threshold, so that the II discusses the fundamental principles of CMV mitigation in
fault remains undetected. This creates a Touch Potential hazard industrial drives and proposes a method to eliminate CMV
for an operator of the faulty unit and for operators of other in AFE Inverters. Chapter III presents results of detailed
equipment, connected to the same Transformer secondary [3]. simulations of the proposed method, and their discussion. Ex-
The safety problem associated with VSD applications in perimental setup and results of experimental validation of the
underground mining environment, and other environments proposed method are described in Chapter IV. These results
with earthing via a large NER, is summarised below: illustrate normal VSD operation, as well as VSD performance
under a ground fault. Chapter V presents conclusions.
VSD produces CMV
⇓
CMV creates Common Mode current II. C OMMON M ODE VOLTAGE MITIGATION IN VSD S
⇓ There is a potential for CMV reduction in practically any
CM current flowing through NER causes EMI
⇓ VSD topology, however, the associated trade-offs are different.
EMI is mitigated by EMC filter A number of options were initially considered in this study.
⇓ The choice then was made in favour of AFE Inverter. This
EMC filter creates a path for the earth fault current
⇓ choice was driven by a number of attractive qualities and the
Protection fails to detect the earth fault current fact that AFE inverters are one of the standard VSD tolpologies
⇓ already in use by the industry. The other commonly used VSD
Undetected fault may create a dangerous Touch Potential
topology, Standard 2-level Inverter, forms as a baseline for
comparison.
Various solutions for the VSD with improved safety have 1) Standard (2-level) inverter: shown in Fig.2a, is the most
been previously studied in literature [4], [5], [6]. Based on commonly used and cost effective, standard VSD inverter. It
its potential for CMV suppression and a number of other interfaces the AC input with a three-phase diode rectifier. For
attractive properties, an Active Front End (AFE) Inverter can that reason, it creates significant harmonics on the input side,
be recommended. AFE Inverters are widely used in mining and needs either input line reactors or harmonic filters. This
applications, for their regenerative braking and power factor type of VSD supports power flow only in one direction – from
correction advantages. However, their potential to provide the mains to the motor and is, therefore, non-regenerative.
CMV suppression has not been explored in practice. From the CMV mitigation perspective, it is not possible
In previous publications [3], [7] the authors utilised Model to completely eliminate CMV in the Standard Inverter. Only
Predictive Control (MPC) to achieve zero CMV in AFE 8 switching combinations of the 6 switches are allowed, and
Inverters. This paper proposes an effective CMV suppression
strategy, which utilises standard Field Orientation Control Table I: Switching states and CMV of Standard Inverter
(FOC), due to its numerous advantages and acceptance in Inverter Switching States CMV
Vdc
the industry [8]. Compared to standard drive applications, 111
2
modifications proposed in this paper are introduced only at the 110, 101, 011 Vdc
6
modulation level. The principle of pulse equilisation, which − V6dc
001, 010, 100
is necessary to achieve zero CMV in AFE Inverters, has
000 − V2dc
been previously developed in [9]. However, unlike [9], which
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TPWM TPWM

PhA tA PhU tU
PhB tB PhV tV
PhC tC PhW tW

V0 V1 V2 V7 V7 V1 V0 V0 V3 V7 V7 V3 V0
V2 V2
0.25t0 0.5t1 0.5t2 0.25t0 0.25t0 0.5t2 0.5t1 0.25t0 0.25t0 0.5t1 0.5t2 0.25t0 0.25t0 0.5t2 0.5t1 0.25t0
(a) SVM pattern at the AFE side (b) SVM pattern at the Inverter side

Fig. 3: Illustration of pulse equalisation between AFE and Inverter under SVM.

each one of them is associated with nonzero CMV, as shown in
Table I. However, it is possible to reduce the maximum CMV
from ± V2dc to ± V6dc by using only active vectors and avoiding
zero vectors, for example, by excluding them from the finite
set under Model Predictive Control (MPC) [10], [11].
Under regular PWM schemes, CMV reduction is achieved
by replacing zero vectors by two suitable active states. Such
replacement states should take equal (half and half) time and
be opposite of each other, so that their net result is zero
[12]. The unavoidable effect of restricting the number of
available switching state is an increase of the output (motor-
side) harmonic distortion.
2) Standard (2-level) inverter with Active Front End (AFE):
shown in Fig.2b, is a standard solution for dynamic electric
drive applications (shuttle cars, trucks, continuous miners,
etc.), which require regeneration of the braking power back
into the mains. The 2-level inverter with AFE is effectively
two converters connected back-to-back. Compared to Standard
Inverter, AFE Inverter requires 6 additional transistors. This
results in some cost increase, which is however outweighed
by distinct advantages, including the above mentioned regen-
erative braking, power factor correction and reduced level of
input harmonics. AFE drives can be connected to the mains
via relatively small line reactors.
From the CMV mitigation perspective, there is a possibility
to completely eliminate CMV. This is because of the symmetry
of the back-to-back arrangement, so that the same switching
state of either converter would produce the exactly same CMV
at its respective AC side, should the DC link mid-point voltage
be kept at zero. But, since the AFE side is earthed and the
DC link mid-point is floating, then this effect is reversed at
the AFE side. For example, if the same switching state (001)
is applied at both sides then the CMV at the Inverter side is
at −V3dc relative to the DC link mid-point, but the DC-link
mid-point is at +V3dc relative to the earthed star point at the
AFE side. As a result, the CMV at the Inverter side is zero
relative to the earthed star point. The CMV values for different (AFE controls the DC Link voltage and Inverter controls the
Table II: Switching states and CMV of an AFE-Inverter
AFE Switch. States → 000 001, 011, 111
Inverter Switch. States ↓ 010, 100 110, 101
000 0 −Vdc −2Vdc
−Vdc
3 3
001, 010, 100 +Vdc
0 −Vdc −2Vdc
3 3 3
+2Vdc +Vdc −Vdc
011, 110, 101 0
3 3
+2Vdc +Vdc
3 at the AFE
111 +Vdc 0
3 3
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switching states are given in Table II. The CMV at the Inverter
side can be calculated as:
VAO + VBO + VCO VU O + VV O + VW O
VCM V = − (1)
3 3
where VAO , VBO , VCO are AFE side phase voltages relative to
the DC link mid-point (O); and VU O , VV O , VW O are Inverter
side phase voltages relative to the same point.
As follows from Table II, if either of the states (001, 010,
100) on the AFE side is combined with either of the states
(001, 010, 100) on the Inverter side, then the CMV will be
zero. Same applies if either of the states (011, 110, 101) on the
AFE and the Inverter sides are combined together. Zero CMV
is also achieved when both sides apply the same zero vector
(000 or 111). In other words, a complete synchronization is
required between the switching at the two sides.
Under Finite Set MPC, such a synchronisation can be
achieved by either heavily penalising non-zero CMV in the
cost function, or by simply excluding from the available finite
set all the vectors with non-zero CMV [13], [14].
Under PWM approach, achieving switching synchronisation
is a non-trivial task. Say that initially the switching states on
both sides were 000. To keep CMV at zero, whenever any
switch turns ON at the AFE side, another switch needs to turn
ON at the Inverter side, and vice versa. Whenever a switch
turns OFF on one side, another switch turns OFF on the other
side. These conditions can be only satisfied if the total length
of the three phase pulses at the AFE side is equal to the total
length of the three phase pulses at the Inverter side [9], i.e.
tA + tB + tC = tU + tV + tW (2)
where tA,B,C is the duration of the respective phase ON-state
at the AFE side; and tU,V,W is the duration of the respective
phase ON-state at the Inverter side. These are illustrated in
Fig.3.
It should be noted that, since the AFE and the Inverter
create their pulses based on mutually independent conditions
motor currents), their total pulse lengths will not be naturally
equal. Therefore, a special algorithms is required to calculate
the pulse lengths and equalise them between the two sides,
while maintaining the correct average voltages at both sides
in accordance to their respective control objective.
3) Proposed algorithm of switching synchronisation under
SVM: In [9] it was proposed to calculate the total pulse lengths
and the Inverter sides; determine which side has a
longer total pulse duration; and either to shrink the pulses on
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1. Total pulse length calculation Example: 2. Total pulse length equalization 3. Two
Circular
sides pulse alignment

} }
a a' Total AFE side a a' Total AFE side alignment
b b' pulses are longer b b' pulse length of the pulses
c c' and need to shrink c c' is now equal to on both
sides

} }
u u' Total Inverter side u u' Total Inverter side
v v' pulses are shorter v v' pulse length
w w' and need to stretch w w'
There are 12 different options of such alignment
a a' a a' a a' a a'
b b' b b' b b' b b'
c c' c c' c c' c c'

u u' u u' u u' u u'

v v' v v' v v' v v'
w w' w w' w w' w w'
Option 1: AUBVCW Option 4: AUCVBW Option 7: AWBVCU Option 10: AWCVBU
a a' a a' a a' a a'
b b' b b' b b' b b'
c c' c c' c c' c c'

u u' u u' u u' u u'

v v' v v' v v' v v'
w w' w w' w w' w w'
Option 2: AUBWCV Option 5: AVCUBW Option 8: AWBUCV Option 11: AVCWBU
a a' a a' a a' a a'
b b' b b' b b' b b'
c' c' c c' c c' c c'

u u' u u' u u' u u'

v v' v v' v v' v v'
w w' w w' w w' w w'
Option 3: AUCWBV Option 6: AVBUCW Option 9: AWCUBV Option 12: AVBWCU

(a) Pulse synchronisation between AFE and Inverter sides under Space Vector Modulation (b) State Machine diagram for VSD

Fig. 4: Main algorithms forming the basis of the VSD software.

the “longer” side by the same amount, or stretch the pulses Similarly, the total “room” for adjustment of the Inverter
on the “shorter” side by the same amount. If the ON-state is side pulses is 6 × 0.25tInv
0 = 1.5tInv
0 . A further extension of
extended or reduced by the same amount of time in all three the pulses is not possible becaues Phase V pulse would take
phases, this would affect only the CMV and will not change the entire PWM cycle, and extending only Phases U and W
the average PWM voltage. pulses would affect duty cycles of the active vectors. Thus the
In this paper, based on the use of Space Vector Modulation, total “room” for both sides together is 1.5tAF 0
E
+ 1.5tInv
0 .
it is proposed to simultaneously shrink pulses on the “longer” If the total
pulse length difference ∆t ≤
side and stretch pulses on the “shorter” side, until the equal 1.5tAF
0
E
+ 1.5t Inv
0 then equilisation can be achieved.
total lengths are achieved. This is illustrated by Fig.3 which The pulse lengths at both sides will be adjusted in proportion
shows one possible instance of the SVM patterns at the AFE to the available “room” at the respective side: each pulse at the
and the Inverter sides. Assume that these SVM patterns were AFE side will shrink by ∆t AF E


3 ∗ 1.5t0 / 1.5tAF
0
E
+ 1.5tInv
0 ;
determined independent of one another by their respective and each pulse at the Inverter
side will stretch by
control algorithms. From Fig.3, the total pulse lengths for the ∆t Inv AF E
3 ∗ 1.5t0 / 1.5t0 + 1.5tInv
0 . Then the total pulse
two sides can be calculated as: length difference will vanish, and the available “room” for
adjustment will be utilised equitably, so that both sides would
tA + tB + tC = tAF 1
E
+ 2tAF
2
E
+ 1.5tAF
0
E
(3) reach the adjustment limit at the same time.
tU + tV + tW = tInv1 + 2tInv
2 + 1.5tInv
0 (4) Following the pulse equalisation, switching instants at the
AFE and the Inverter sides need to be aligned. This can be
where ’AF E’ and ’Inv’ superscipts correspond to the AFE
done in multiple ways. For example, one can align the falling
and the Inverter sides, respectively. It is also clear from Fig.3,
edge of pulse A with the falling edge of pulse U , V or W
that the total pulse lengths for the two sides are not equal and
(say pulse U ). Then the rising edge of pulse U can be aligned
need equalisation: the AFE side pulses need to be reduced
with the rising edge of either pulse B or pulse C, etc. Fig.4a
and/or the Inverter side pulses need to be extended. The total
shows how different alignment options can be obtained.
pulse length difference is denoted as:
In [9] it was argued that a large number of different
∆t = (tA + tB + tC ) − (tU + tV + tW ) (5) alignments exist, and amongst those the most “compact” one
was recommended. In this study the authors have proved
The total “room” for adjustment at the AFE side is 6 × that only 12 different alignments may possibly exist. Other
0.25tAF
0
E
= 1.5tAF
0
E
. That is, all three phase pulses can possibilities simply repeat the same 12 alignment options,
be potentially reduced by 0.25tAF 0
E
at each side. It is not albeit having different starting points. Furthermore, out of the
possible to further reduce the pulses because Phase C pulse 12 existing options, 6 are the mirrored images of the other 6.
would collapse, and reducing only Phases A and B pulses This can be observed in Fig.4a where the different alignment
would affect duty cycles of the active vectors. options are organised accordingly.
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Fig. 5: Standard Inverter, before and after CMV minimization. Fig. 6: AFE Inverter, before and after CMV minimization.

Since only a very limited number of the options exist, they
can be all determined and compared to each other in real time.
It is proposed in this paper to define a cost function, calculate
its value for each alignment option in each PWM cycle, and
choose the option which minimises the cost function. The
cost function can be determined, for example, as the distance
between the falling edge of the last pulse and the rising edge
of the first pulse, to give the most “compact” pattern as per
the recommendation from [9]. Alternatively, the cost function
can be determined, for example, as the quadratic current error
inside PWM cycle [15].
III. D ETAILED SIMULATIONS OF THE VSD ALTERNATIVES
After the CMV algorithm was implemented, it was tested
mitigation algorithms were applied, so that an easy “before”
and “after” comparison could be done.
Standard Inverter
Voltage and current waveforms illustrating performance of
the Standard Inverter, before and after the CMV minimization,
are shown in Fig.5. The effect of the CMV minimization on the
drive performance can be seen by comparing the waveforms
before (left half) and after (right half) the CMV minimization
algorithm was applied. Following the order in which the
waveforms are presented, the following observations can be
made:
• The output current (Iout ) remains sinusoidal, although the

via a detailed simulation. The models used in simulations high frequency noise becomes more pronounced after the
correspond to Figs 1a and 1c. They differ in the type of the CMV is minimized;
VSD and represent the following practical situation. • The output line-to-line voltage (VLL out ) shows a much
A 50kW Motor Drive, fed from the Feed Transformer with more intensive switching after the CMV is minimized;
NER, drives an Induction Motor (415VAC, 70A). The length • The input phase-to-neutral voltage (Vph inp ), that is mea-
of the cable from the Transformer to the Motor Drive is 200m. sured on the Feed Transformer, becomes less polluted
Parameters of a standard underground cable were used, with after the CMV is minimized;
resistance 216µΩ/m and inductance of 2.74µH/m for the line, • The input line current (Iinp ) is not sinusoidal, has a
and 417µΩ/m, 1.12µH/m - for the earth wires. The NER typical shape related to the use of diode rectifier, and
resistance is 140Ω. Other than the line impedance, no EMI does not seem to change;
filter or line reactor is used between the Feed Transformer • The voltage across the NER resistor (Vner ) becomes

and the Motor Drive. much smaller after the CMV is minimized;
Standard Inverter and AFE Inverter were substituted for the • The CMV (Vcm ), measured at the motor input relative to
Motor Drive and ran under the exactly same conditions. Simu- Earth, becomes 3 times smaller after the CMV minimiza-
lation of each VSD option initially ran under the corresponding tion than before. The CMV variation at 150Hz remains
standard control algorithms (without the CMV mitigation). unchanged. This variation is created by the diode rectifier
Half-way through the simulations, the corresponding CMV and cannot be eliminated in the Standard Inverter.
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Table III: Characteristics of the VSD alternatives. Isolation Transformer Isolated

Rectifier Inverter AC Motor DC Motor DC Source
N 5mH
1
Standard Inverter AFE Inverter A
B
Characteristic CMV mitigation CMV mitigation C 60
F
Line
No Yes No Yes Chokes DC link Mechanical
Capacitor 25 k
Coupling
RNER=150 
Input current THD, % 17.0% 17.0% 0.375% 2.67% E
VNER VCM

Isolation switch Rcable =1 ICM

Output current THD, % 0.174% 0.364% 0.097% 0.331%

(a) Electric diagram with measurement points
Switched CMV (rms), % 66.7% 25.3% 55.6% 0

150Hz CMV (pk-pk), % 24% 24% 0 0

PF correction No Yes
Regeneration No Yes
Size / Weight 100% 120%
Cost 100% 150%

AFE Inverter (b) Semikron power converters (c) Test bed with coupled motors
Performance of the AFE Inverter, before and after the
Fig. 7: Experimental Setup used for validation.
CMV minimization, is illustrated in Fig.6. When the CMV
is minimized:
• The output current (Iout ) remains sinusoidal, with slightly
that accounts for the largest proportion of the drive weight is
higher noise level; the DC Link capacitor. When moving from Standard Inverter
• The output line-to-line voltage (VLL out ) shows more
to AFE Inverter, this part of the weight remains unchanged.
vigorous switching; The weight of Power Electronics with heat sinks, which is
• The input phase-to-neutral voltage (Vph inp ) at the Trans-
typically around 20% of the drive weight, will approximately
former, becomes perfectly clean; double. The AFE Inverter is also a cost effective solution, as
• The input line current (Iinp ) was and remains nearly
it is based on mass produced standard hardware.
sinusoidal, with a slightly higher distortion;
• The voltage across the NER resistor (Vner ) becomes zero;
IV. E XPERIMENTAL VALIDATION
• The CMV (Vcm ) is completely eliminated.
To formally evaluate and compare the VSD alternatives, a An electric diagram of the experimental setup is shown in
set of performance characteristics have been determined, in- Fig.7a. Its main parts are:
cluding: the Total Harmonic Distortion (THD) of the output • Custom built VSD consisting of: two 20 kW IGBT stacks
current; the THD of the input current; the periodic component (AFE and Inverter) from Semikron, connected back-to-
of the CMV (peak-to-peak); and the switched component of back and sharing a common DC Link Capacitor, with a
the CMV (rms). The current THD and the voltage RMS custom-built drive controller from Denkinetic;
calculations were performed according to the expressions: • Test bed with two mechanically coupled motors: AC
v
∞
s (induction type) motor 10kW, 415VAC, 20A from TECO;
1 T
uX Z
1u ˆ 2 and 10kW DC motor representing a mechanical load;
T HDI = t Ij ; Vrms = V (t)2 dt (6)
Iˆ1 j6=1 T 0 Some elements of the experimental setup are illustrated by
photos. Fig.7b shows the Semikron power converters: AFE
where Iˆj is the peak value of the current harmonic number j; and Inverter, and the drive controller. Fig.7c shows a picture
Iˆ1 is the peak value of the fundamental current component; of the test bed with the two mechanically coupled motors.
V (t) is time varying voltage; and T is its period (typically, The VSD software was implemented in C code for real-time
the period of the fundamental frequency). TMS320F28377D processor. The basic software was orga-
The resulting values, together with other important prop- nized using the “State Machine” principle, which is illustrated
erties, are listed in Table III. It is clear from Table III that in Fig.4b. The VSD was operated under standard FOC-SVM
AFE Inverter offers exceptional performance with respect to algorithm. Novel elements including pulse equalisation, pulse
the majority of characteristics. Its input current THD is very alignement and cost function minimisation were included as
low, and can be further reduced by using larger line reactors. an optional Add-on.
It has zero switched CMV and no 150Hz CMV component. To validate performance of the proposed algorithm, a num-
Additionally, the AFE Inverter offers power factor correction ber of experiments were conducted. Their results are presented
and regenerative braking. These are both very valuable prop- in Fig.7 by the waveform plots obtained recorded by Pico-
erties in dynamic applications such as shuttle cars. They bring scope. The most important plots are those for VCM and VN ER ,
improved efficiency and energy savings. as the main purpose of this study was to eliminate them. These
The main trade-off to be made when opting for the AFE voltages are shown in greater detail by a “magnifying glass”.
Inverter is a slightly higher weight and size. The component The input frequency was 50Hz and the output frequency was
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(a) Standard 2-level Inverter: supply side (b) Standard AFE Inverter: supply side (c) AFE Inverter with CMV suppression: supply side

(d) Standard 2-level Inverter: motor side (e) Standard AFE Inverter: motor side (f) AFE Inverter with CMV suppression: supply side

Fig. 8: Experimental waveforms illustrating performance of the VSD options.

20Hz. The time scale in the plots is 10 millisecond / time a flat zero level with occasional very short pulses, which
division. Other scales are: are associated with dead time. Motor side voltage (VU V ) has
• 200 V /division for all the voltages (VAB , VU V , VN ER , also become more irregular. The motor current (IU ) is still
VCM ); sinusoidal, with a slightly higher noise. The CMV voltage
• 8 A /division for the motor side currents (IU ); (VCM ) has practically disappeared, except for the dead time
• 1.6 A / division for the input currents (IA ); pulses.
• ±135V and 80 milliseconds are the ranges for the “mag- The calculated THD and RMS values of the experimentally
nifying glass”; measured voltages and currents are shown in Table IV, for
comparison. The VCM and VN ER numbers in Table IV show
Standard Inverter configuration was used as a benchmark for
the dramatic reduction of the CMV and the associated NER
comparison. With reference to Fig.7a, if the AFE switches are
voltage, when the proposed CMV minimization strategy is
locked in the open state, then only the anti-parallel diodes are
applied. It is also clear from Table IV that there is a trade-
active. This turns the AFE Inverter into Standard Inverter with
off between the CMV suppression and the current THD,
the diode front end. With switches unblocked, but without the
particularly the THD of the output current. This trade-off
CMV Minimization Add-on, the VSD operates as a standard
can be controlled and optimised by using an appropriate cost
AFE Inverter.
function.
Figs.8a,d illustrate performance of Standard Inverter. Supply
side voltage (VAB ) and current (IA ) have low frequency Table IV: Experimentally obtained harmonic and noise char-
distortions. Voltage across NER (VN ER ) is significant. Motor acteristics
side voltage (VU V ) is switched at high frequency. Motor side
Input current Output current CMV NER volt.
current (IU ) is sinusoidal with some ripple. The CMV voltage Inverter (IA ) (IU ) (VCM ) (VN ER )
(VCM ) is significant. It includes high freqiency switching and type THD, % THD, % V V
150Hz variation. Simple
68.16% 4.72% 60.5 13.5
Figs.8b,e illustrate performance of AFE inverter without Inverter
CMV minimisation. Supply side voltage (VAB ) is switched at AFE Inverter 21.69% 4.86% 33.2 17.6
high frequency. Supply side current (IA ) is close to sinusoidal, AFE Inverter
29.51% 10.86% 8.4 7.8
with high frequency ripple. Voltage across NER (VN ER ) is still zero CMV
significant. Motor side voltage (VU V ) and current (IU ) are very
similar to those from the Standard Inverter. The CMV voltage In order to test the fault performance of the AFE Inverter
(VCM ) is still significant but mostly includes high freqiency with CMV minimization, a single phase fault was induced
switching and no obvious 150Hz variation. in the motor, as shown in Fig.9a. A switch was connected
Figs.8c,f illustrate performance of AFE inverter with CMV between one of the phases and earth. When the switch is
minimisation. Supply side voltage (VAB ) has become slightly closed, that phase is shorted to earth, producing exactly the
more irregular, still producing a nearly sinusoidal current same effect as if a solid single phase fault occurred in the
(IA ). Voltage VN ER has dramatically reduced. It looks like motor.
978-1-5386-4539-0/19/$31.00 © 2019 IEEE
 2019-MIC-0981
Transformer AFE
AC Motor
Secondary Rectifier Inverter
Line
Chokes DC link
Capacitor
RNER VNER ICM VCM
Rcable
(a) Ground fault emulation
(b) CM current (normal operation); (c) CM current (phase to ground
fault).
Fig. 9: Experimental fault testing of the proposed VSD.
The Common Mode current (ICM ) was measured, using a
LEM Hall effect current sensor, in the point marked in Fig.9a.
The measured currents before and after the fault are shown in
Figs.9b and 9c, respectively. Before the fault, the measured
Common Mode current ICM is very low, practically zero.
After the fault, a notable signal is measured in the fault path.
It has the fundamental harmonic amplititude of ∼0.5A and
maximum value up to 0.8A. Note that the experiment was
performed under 1/4 of the rated inverter voltage and 1/4 of
the DC Link voltage. Under normal inverter operation, this
current will be approximately 4 times higher.
Without the EMC filter, the fault current has no other path
rather than through the NER, as required. Therefore, the fault
protection based on sensing the NER current and comparing
it to the fault current threshold, will be effective.
V. C ONCLUSIONS
Based on a comprehensive appraisal of the available tech-
nical solutions, this paper has proposed a VSD solution,
which mitigates both safety and EMI problems in underground
mining applications. EMI is mitigated by elimination of its
root cause - the Common Mode Voltage. The safety problem
is addressed by removing the previously existing alternative
path for the fault current.
The proposed concepts have been first proved by extensive
simulations. Following that, a laboratory scale version of the
proposed VSD system has been built, and the software code
for the real-time drive control system has been developed. The
experiments have shown that the proposed strategy is effective.
Finally, the proposed VSD was tested under a single phase to
earth fault. The experiment has shown that the fault current
through NER is at an appropriate level for fault detection.
Future work may include development of advanced cost
functions, to achieve a desired trade-off between the VSD
input and output harmonic performance.
978-1-5386-4539-0/19/$31.00 © 2019 IEEE
Page 8 of 8
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