QoS Scheduling

Link Adaptation

Power Control

Beam Management & Massive

MIMO

MAC-PHY interface

Software Design
 Software Design

Flexible TDD Slot Configuration

Control Flow and Data Flow

1. In which aspects is your algorithm better than other scheduler? E.g: traffic, throughput. Please describe
more detail.

2. There are 100 UE which want to receive downlink data. However the gNB system can only support 8 UE
per TTI. Please write your solution to sort these 100 UE in descending order of priority and choose 8 UE to
allocate resource. Assuming that these UE use different kinds of service (different QCI requirement); their
channel conditions are also different. How to calculate priority depends on your solution.

3. Which KPI do you keep in track in order to satisfy QoS requirement and system performance?
1. There are 28 MCS index but only 15 CQI index. How can you map CQI to MCS effectively?
2. Based of which condition you decide to change MCS? E.g: channel condition, number of re-transmission
transport block etc. Please describe more detail.

3. Does your link adaptation algoritm satisfy spectral efficiency requirement suggested by 3GPP?
1. How many percentages in UE's power can your algoritm reduce? How can you prove that?

2. How can you verify the improvement of your solution? E.g: measure BLER, UE energy consumption
1. What is the role of Beam Scheduling in DU-L2? Can gNB switch UE from one beam to another or UE
decide when to switch beam?
2. How can gNB allocate same Resource Block to different UEs in massive -MIMO? What is the condition?
Resource Blocks are allocated to different UEs based on which criteria?
3. How many beams does your system form in one time slot? Do we have to select which beam to transmit
signal or we can transmit signal in all beam direction in one time slot?
4. What is the maximum number of UEs to which we can allocate the same PRB?
1. What is the interface between MAC and PHY in your system? MAC and PHY communicate via which IPC?
How many cells does 1 PHY entity suppport?
2. How can you ensure that PHY receive full control information from MAC in one time-slot before MAC
starts to send control information for the next slot.
1. Are you familiar with BBU pooling? How do we define the dependence of tasks? The relation between
each task is static or can be dynamically changed?
2. Which mechanism do you use to achieve high-performance packet processing (e.g reduce time
processing of data forwarding). Are you familiar with DPDK (Data Path Development Kit)?
3. Do you use thread pool or similar mechanism in your system? How can you control load balancing
betweens core?
4. Does your DU-L2 contain Scheduler Module and Resource Allocator Module? How many cells 1
Scheduler entity can support? What is the time processing of Scheduler and Resource Allocator? Do
Scheduler entity and Resource Allocator Entity have to finish their tasks within 1 time slot?

1. What is the pattern of TDD slot configuration do you use (e.g DDDSU or DDDDU). How many DL symbols
and UL symbols in slot S? Do you use Flexible symbols and what is the purpose of these symbols? Why we
need both DL and UL symbols in a slot and what is the use-case of this configuration?

1. Do you separate DU-L2 into control path and data path. Which mechanism do you use to ensure the
integrity of control message while maintain the fast path of user data? What kind of message do you
consider as user data (e.g data on DRB, SRB)

2. How do you synchronize control and data message? Lets assume that DU-L2 receives modification
message from CU-CP while data is still transfered, do you drop the data and apply the modification or
continue transferring data? In that case when do you apply the modification?