Direct Memory Access (DMA)

DMA I/O to Memory Transfer

DMA write operation
• DMA transfer from an I/O device (the
diskette drive) to memory
• The diskette driver receives a request to read
data from a specific sector and transfer the
information to a specific buffer.
Initialization
• The diskette drive uses DMA channel 2, which means
that the DMA buffer must fall within the first 1MB of
memory (newer controllers allow all eight channels
to access memory within the first 16MB) and cannot
exceed 64K, nor cross a 64K page.
– We will assume that the diskette driver has already
allocated a suitable DMA buffer as part of its initialization.
• The diskette driver now performs the necessary
operations to position its read/write head on the
correct sector and track before sending the
necessary information to the DMA controller
including the following:
 o The base address in memory where the DMA buffer is
located.
o The number of bytes to transfer minus one.
o The offset within the buffer.
o The DMA operation (in this case a write operation).
• The diskette driver updates the DMA mask to allow
recognition of DMA channel 2 requests before
sending the read command to the diskette
controller.
• In a multi-processing operating system, the kernel
will block the user process that requested the
diskette operation and schedule a new process for
execution.
Operation
• The diskette drive, under the supervision of its
controller card, will begin to read data from the
diskette surface before transferring it to its data
register.
• Once data becomes available, the diskette
controller will request DMA service by asserting
a high on DMA request line 2 (DREQ2).
• The DMA controller verifies that DREQ2 may be
allowed (by examining its mask register) and
requests the CPU to enter a hold mode.
• This is done by asserting the hold request line
(HOLD).
• The CPU will respond by asserting hold
acknowledge (HLDA) and now enters a bus
holding state.
• The DMA controller will generate an address
before passing it to the bus and activating the
memory write and I/O read control lines.
• The DMA acknowledge signal (DACK2) is
activated to inform the diskette controller that
the DMA transfer is in progress.
• The data is transferred from the diskette
controller's data register to memory without
passing through the DMA controller.
• After every transfer, the DMA controller will
decrement the countdown register associated
with channel 2.
• During the transfer, the CPU effectively shares
the bus with the diskette controller by
interleaving bus hold cycles and normal cycles
under the supervision of the DMA controller
(sometime referred to as cycle stealing).
• If the transfer completes, the DMA controller will
assert the terminal count line signal (TC).
 Note that the DMA controller may temporarily stop
the transfer by dropping DREQ2 if the transfer rate is
too fast to handle.
• The TC signal indicates to the diskette controller
that the operation has been completed and the
HOLD and DACK2 lines are deactivated before
dropping DREQ2.