Automatic Control–Homework 3

Deadline: 2021/12/17
PS：請以 A4 大小紙張撰寫裝訂；註明姓名學號；不需要封面。
1. Sketch the boundaries of the acceptance region in the s-plane of a second order system with finite
zero and (1) rise time of 5ms, (2) settling time of 20ms, (3) maximum percent overshoot is less
than 5%.
[成大機械]
2. If the poles of the second order closed-loop system locate at the four points A, B, C, D in the s-
plane shown in the Figure, you as an expert control engineer, are asked to pick up the desired poles
to satisfy the following specifications. (Explain)
(1) The fastest settle time
(2) The smallest maximum overshoot
(3) The biggest bandwidth
(4) The smallest oscillation
(5) The slowest response and biggest maximum overshoot

[交大電控]
3. The block diagram of a dc-servomotor driven control system is shown in the Figure.
(1) Determine the limiting gain for a stable system.
(2) Determine the suitable gain so that the overshoot to a step command is approximately 5%.

[成大工科]
4. Consider the system with unity feedback shown in Figure.
(1) Determine the steady-state error for a step and a ramp input when
10
G( s) =
s + 14s + 50
2

(2) Determine the steady-state error for a step and a ramp input when
s −5
G( s) =
s + 3s + 2
2

[台大電機]
5. Consider a PID control system in the form of the following Figure with H(s) as the feedback
10( s + 0.2) 0.5
block, and G(s ) = , H (s) = 3 + 10s +
s ( s + 1)( s + 8) s
(1) Determine the steady-state error of the system with a unit step input.
(2) Determine the steady-state error of the system with a unit step input.

[台大電機]

6. In the following block diagram, the reference input (R(s)) is zero. Find the control error due to
unit step disturbance D(s).

D(s)

+ 1 + 2 Y(s)
R(s) + (1 + 0.5s )
- 4s

7. Find the total steady-state error due to a unit-step input and a unit -step disturbance in the
following system.

[中正電機]