IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI-2017)

Implementation of IEEE 754 Compliant Single

Precision Floating-Point Adder Unit Supporting
Denormal Inputs on Xilinx FPGA

Milind Shirke*, Sajish Chandrababu, Yogindra Abhyankar

High Performance Computing Technology Group
Centre for Development of Advanced Computing
Pune, India
Email: milindshirke@gmail.com, sajishc@cdac.in, yogindra@cdac.in

Abstract—FPGA based reconfigurable computing
accelerators are increasingly being used in high performance and
scientific computing applications to achieve higher performance.
These applications demand high numerical stability and accuracy
and hence usually use floating-point arithmetic. The floating-
point arithmetic cores available from major FPGA vendors are
not fully IEEE 754 compliant. These cores do not support
denormal numbers. In this paper we describe our
implementation of IEEE 754 compliant single precision floating-
point adder that supports denormal inputs. Further, we compare
its performance and resource utilization against the Xilinx
floating-point adder IP core. Our implementation has eight
stages of pipeline, utilizing minimal FPGA resources; it can
operate at frequencies greater than 300 MHz.
Keywords—FPGA, IEEE 754, Floating-Point, single precision,
Reconfigurable Computing
I. INTRODUCTION
Floating-Point addition is one of the most frequently used
floating-point operation. An analysis of real time applications
indicate that signal processing algorithms require, on an
average 40% multiplication and 60% addition operations.
Therefore the floating-point addition forms an important
operation in math co-processors, DSP processors, embedded
arithmetic processors, and data processing units. Almost every
modern computer and compiler uses the IEEE 754 floating-
point standard. This standard has greatly improved both the
ease of porting floating-point programs and the quality of
computer arithmetic. When a program is moved from one
system to another, the results of the basic operations remains
the same if both systems are compliant to the IEEE 754
standard. This standard completely describes the behavior and
operations on floating-point data, including advanced options
such as the use of rounding modes and other computational
techniques and controls [1]. Many floating-point adder
algorithms and design approaches have been developed and
discussed by the VLSI community [2-10]. Leading One
Predictor (LOP) and Far and Close Path algorithms achieve
better overall latency, while the standard floating-point adder
algorithm is considered as an area efficient algorithm. The Far
and Close algorithm consumes 88% more slices than the
*Currently not working with C-DAC. The work was performed while the
author was with C-DAC.
standard adder algorithm implementation [7]. In our
implementation we use the standard floating-point adder
algorithm considering its area efficiency as the prime
objective.
Section 2 of this paper describes in brief the IEEE 754
single precision floating-point format, exceptions, special
numbers and rounding modes. Section 3 describes the standard
floating-point adder algorithm and Section 4 describes the
architecture and hardware modules developed to implement
the algorithm. Section 5 compares our implementation of
IEEE 754 compliant single precision floating-point adder unit
supporting denormal inputs with the Xilinx floating-point
adder core. Section 6 concludes the paper and highlights the
future work.
II. IEEE 754 STANDARD FOR FLOATING POINT
The IEEE 754 is an industry standard to represent floating
point numbers.
A. Single Precision Floating-Point format
The IEEE 754 single precision format is a 32 bit format.
This format uses 1-bit for sign, 8-bits for exponent and 23-bits
to represent the fraction as in fig. 1. The single precision
floating-point number is calculated as (-1) S × 1.F × 2(E-127).
The sign bit is 0 for non-negative number and 1 for negative
numbers. The exponent field can be used to represent both
positive and negative exponents. To do this, a bias is added to
the actual exponent. For IEEE single-precision format, this
value is 127. As an example, a stored value of 147 indicates an
exponent of (147-127), or 20. The mantissa (significand) is
composed of an implicit leading bit and the fraction bit, and
represents the precision bits of the number. Exponent values
of 0xFF and 0x00 are reserved for special numbers such as
zero, denormalized numbers, infinity, and Not a Number
(NaN).
Sign 8 bit Exponent 23 bit Fraction
(S) (E) (F)
Fig. 1. IEEE 754 Single Precision Floating-Point Format

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B. Normalized and Denormalized Numbers The implementer shall choose how tininess is detected, but
A floating-point number is said to be normalized if the shall detect tininess in the same way for all operations in radix
exponent field contains the real exponent plus the bias other two, including conversion operations under a binary rounding
than 0xFF and 0x00. For all the normalized numbers, the first attribute. In our implementation we are calculating underflow
bit just left of the decimal point is considered to be 1 and not after rounding.
encoded in the floating-point representation; this also called as The invalid operation exception is signalled if and only if
the implicit or the hidden bit. there is no useful definable result. In these cases the operands
To support very small numbers, IEEE introduced are invalid for the operation to be performed. These operations
denormalized numbers. The denormalized numbers represent are any general-computational or signalling-computational
numbers between zero and the lowest normalized number. A operation on a signalling NaN except for some conversions.
floating-point number is considered as denormalized, if the For example magnitude subtraction of infinities is considered
exponent field is 0x00 and the fraction field is not all 0’s. For as invalid operation.
the denormalized number, the implicit (hidden) bit is
considered to be a 0. III. STANDARD FLOATING-POINT ADDER ALGORITHM
The standard floating-point adder algorithm as shown in
C. Special Quantities fig. 2 is implemented for our design. This area efficient
In IEEE 754 standard, infinity and NaN are treated as algorithm is as described below.
special quantities. Without any special quantities, there was no
1) Compare two operands N1 and N2 and check for
good way to handle exceptional situations like calculating the
denormalization and infinity. If numbers are
square root of a negative number other than aborting the
denormalized, set the implicit bit to 0 otherwise it is
computation. In IEEE 754 arithmetic, a NaN is returned in the
Read Operand
above said situation [11]. N1 & N2
In single-precision representation, Infinity is represented
by exponent field of 0xFF and fraction field of all 0’s while
NaN is represented by exponent field of 0xFF and the fraction Denormalize Yes Set Implicit bit 0
operands?
field that is not all 0’s.
No
D. Rounding Mode and Exceptions
Three user-selectable rounding modes and a default Compare Yes
exponent Swap Operands
rounding mode are defined in the IEEE standard. The default (E1<E2)?
rounding mode (roundTiesToEven) of IEEE 754 is
implemented in our unit. In this mode the floating-point No
number nearest to the infinitely precise result is delivered; if Shift smaller operand by
|E1-E2|
the two nearest floating-point numbers bracketing an
un-representable infinitely precise result are equally near, the
one with an even least significant digit will be delivered [1]. Operation Yes Two’s Complement of smaller
Subtraction? operand
The IEEE 754 defines five types of exceptions: overflow,
underflow, invalid operation, inexact result, and division-by- No
zero. Exceptions are signalled by setting a flag. We have Add fraction parts f1 + f2
implemented overflow, underflow and invalid operation flags
in our designs.
The overflow exception is signalled if and only if the Negative Yes Two’s complement of result
Result?
destination format’s largest finite number is exceeded in
magnitudes by what would have been the rounded floating- No
point result were the exponent range unbounded. Leading One Detector

The underflow exception is signalled when a tiny non-zero

result is detected. For binary formats, this will be either: Normalization

a) After rounding — when a non-zero result computed as

though the exponent range were unbounded would lie strictly Rounding
between the smallest positive/negative normal floating-point
number ± bemin.
Final Exponent & Sign calculation
b) Before rounding — when a non-zero result computed as
though both the exponent range and the precision were Output & Exceptions
unbounded would lie strictly between ± bemin.
Fig. 2. Standard Floating-point Adder Algorithm

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set to 1. At this point, the fraction part is extended to

24 bits.
2) The two exponents E1 of N1 and E2 of N2 are
compared. If E1 is less than E2, N1 and N2 are
swapped, otherwise no change.
3) The smaller operand’s fraction part is shifted right by
the absolute difference of the two exponents. After
shifting both the numbers have the same exponent.
4) The sign bits of the two operands and input
(operation to be performed add/sub) are used to
determine whether the operation is a subtraction or an
addition.
5) If the operation is a subtraction, then two’s
complement of the F2, fraction part of N2 is used.
6) Now the two fractions are added using a 27 bit adder.
7) If the resulting sum is a negative number, it has to be
inverted and a 1 has to be added to the result.
8) The result is then passed to a Leading One Detector.
It gives the position of the first one in the result.
9) Based on the output of the leading one detector, the
result is then shifted left to get normalized. In some
cases, 1-bit right shift is needed.
10) The result is then rounded towards nearest even
number.
11) Using the results from the leading one detector, the Fig. 3. Floating-point Adder Architecture
exponent is adjusted. The sign is computed and after
that overflow and underflow check is performed and precision of the number, three extra bits, the guard (g), round
the result is sent out. (r), and sticky (s) are added to the significand. The g and r bits
are first and second bits that might be shifted out and s is the
bit computed by ORing all the other bits that are shifted out.
IV. FLOATING-POINT ADDER ARCHITECTURE AND The barrel shifter implementation is used for the right shifter
IMPLEMENTATIONS because of the lower combinational delay.
The standard floating-point adder as shown in fig. 3,
consists of a two’s complement 27-bit adder, right-shifter and C. Two’s Complement Adder
an exponent difference module. For post normalization, we This is a simple adder that adds or subtracts the pre-
need a Leading One Detector and a left-shifter. After normalized significands. Two 27 bit significands are the inputs
normalization, rounding is performed taking guard (g), round to this module. The signs of individual significand are
(r) and sticky (s) bits into consideration. In the following sub processed before it enters the adder module and determines
sections we describe all the modules that are developed to whether the operation is addition or subtraction. This signal is
implement the floating-point adder. used to select the two’s complement of the operands before
adding in case of subtraction. The generated carry out signal
A. Exponent Difference Module determines the sign of the result and also used to determine the
The exponent difference module computes absolute sign of the output.
difference of two 8-bit numbers and identifies if E1 is smaller
than E2. An 8-bit adder is used to subtract the exponents and D. Leading One Detector (LOD)
the carry out is used to identify if E1 is smaller than E2. If the After the addition, the next step is to normalize the result.
result is negative, two’s complement of the result is computed The first step is to identify the position of first one (leading
to find the absolute difference. one) in the result. Then shift left the adder result by the
number of zeros in front of the leading one. In order to
B. Right Shifter perform this operation, special hardware, called Leading One
The right shifter is used to shift right the significand of the Detector (LOD) has to be implemented. This design has low
smaller operand by the absolute exponent difference. This is fan-in and fan-out that leads to area and delay efficient design,
done so that the two numbers have the same exponent and first presented by Oklobdzija in 1994 [12] and later a low
normal integer addition can be implemented. To maintain the power design in [13].

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 IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI-2017)

TABLE I. A COMPARISON OF RESOURCE UTILIZATION & FREQUENCIES

BETWEEN OUR DESIGN IMPLEMENTATION VERSUS THE XILINX DESIGN ON
XC5VLX30-1 DEVICE.

LUT- Latency
Frequency
Method Register LUT Registers ( Clock
( MHz)
Pair Cycles)
Our 577 441 433 8 263

Xilinx 629 432 558 8 420

(a)
(b)
Fig. 4. Comparison of how denormal numbers are handled. (a)
Simulation waveform for Xilinx core (b) Simulation waveform for
our implementation of standard Floating-point Adder Algorithm
supporting denormal numbers.
We have implemented the above algorithm using Xilinx.
The frequency and the resource utilization for our
implementation are shown in the table I. The performance and
resource utilization of the Xilinx core implementation of 32
bits single precision floating-point adder without denormal
support [13] is also shown in table I for comparison.
From table I, we can observe that the resource utilization is
almost same for both the implementations; however there is a
difference in the maximum operating frequency. This is due
to the fact that the logic required for handling denormal
numbers increases the critical path that in turn reduces the
operating frequency.

E. Normalization (Left Shifter) VI. CONCLUSION

Using the LOD, the result from the adder is shifted left for
normalization. That means now the first bit is 1. The barrel
shifter implementation is used for the left shifter.
F. Rounding
The IEEE 754 default rounding scheme is implemented in
our design. Rounding is done using the guard, round and
sticky bit of the result. A 1 is added to the result if guard bit is
set and either s or r bit is 1. The exponent part of the result is
determined by subtracting the larger of the exponent by the
leading zero count from the leading one detector. The sign is
selected according to result of the sign bit calculation unit.
Overflow and underflow exceptions are flagged by comparing
the output exponent to the desired conditions.
V. COMPARISON
Our FPGA design is written in VHDL and thoroughly
simulated using Modelsim 6.5. The simulation results were
compared with the C program results and found to be correct
for both floating-point addition and subtraction. Apart from
normal cases, special conditions like addition of two denormal
numbers resulting in denormal number, subtraction of two
normal numbers resulting in denormal number, subtraction of
normal and denormal number resulting in denormal number
etc. were also verified and found to be correct.
As discussed earlier the Xilinx floating-point core does not
support the denormal numbers. The core considers denormal
numbers as zero. Fig. 4(a) shows the waveform of the
simulation run involving denormal numbers for the Xilinx
core. One can see that the result of addition of two denormal
numbers as zero. Fig. 4(b) shows the simulation waveform of
our design with same inputs and the corresponding expected
result.
Many of the high performance scientific computing
applications require fully compliant IEEE 754 arithmetic
units. The Xilinx implementation treats denormal numbers as
zero, hence it may not be directly useful in such applications.
In order to make it useful, one may require additional logic.
Our implementation of IEEE 754 compliant single precision
floating point adder unit supporting denormal inputs will work
fine with scientific applications that require high accuracy and
precision. In future we are planning to implement multi-path
and far-and-close data-path algorithms as they reduce critical
paths but at the cost of significant increase in hardware
resources [15].
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