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FALL SEMESTER 2021-2022

M.Tech. VLSI Design
MAT 5009 - Advanced Computer Arithmetic
Digital Assignment I

Submitted by:
Pramit Paul
21MVD0010

3.4. Addition with parallel carries

a. The redundant radix-2 representation with the digit set [0, 3], used in several
examples in Section 3.5, is known as the binary stored-double-carry number
system [Parh96]. Design a digit slice of a binary stored-double-carry adder based
on the addition scheme of Fig. 3.16.
b. Repeat part a with the addition scheme of Fig. 3.14.
c. Repeat part a with the addition scheme of Fig. 3.15.
d. Compare the implementations of parts a–c with respect to speed and cost.
a. Limited-carry addition of radix-2 numbers with the digit set [0, 3] by means of
the parallel-carries scheme.

Soln:

1 0 2 1 1 xi in [0,3]
+ 0 1 3 2 2 yi in [0,3]

1 1 5 3 3 pi in [0,6]

1 1 1 1 1 wi in [0,1]

0 0 0 1 1 t (1)i+1 in [0,1]

0 0 1 0 0 t (2)i+1 in [0,1]
0 0 2 1 2 2 1 si in [0,3]
b. Limited-carry addition of radix-2 numbers with the digit set [0, 3] by means
of carry estimates.

Soln:

1 0 2 1 1 xi in [0,3]
+ 0 1 3 2 2 yi in [0,3]

1 1 5 3 3 pi in [0,6]

low low high low low low ei in {low:[0,2], high:[1,3]}

1 -1 1 1 1 wi in [-1,1]

0 1 2 1 1 ti+1 in [0,3]
0 2 1 2 2 1 si in [0,3]
c. Limited-carry addition of radix-2 numbers with the digit set [0, 3] by means
of the repeated-carry scheme.

Soln:

1 0 3 2 0 xi in [0,3]
+ 0 1 2 1 3 yi in [0,3]

1 1 5 3 3 pi in [0,6]

1 1 1 1 1 wi in [0,1]

0 0 2 1 1 ti+1 in [0,3]
0 1 3 2 2 1 si in [0,4]

1 1 0 0 1 wi in [0,1]

0 1 1 1 0 ti+1 in [0,2]

0 2 2 1 0 1 si in [0,3]
d. Part a is the fastest among all the three parts having the least number of
intermediate steps, thus, reducing the cost. Part b also has same number of
intermediate steps but part a uses parallel-carries scheme which increases the
speed along with reducing the cost. Part c uses repeated-carries scheme, thus has
more steps to go through.