Digital Fundamentals QB ODD 2021

L.J.
Institute of Engineering & Technology Semester: III (2021)
Subject Name: DF Subject Code: 3130704
Faculty: Kinjal Parmar, Jay Paria, Shweta Shah, Zalak Bhatt, Sunita Kanojiya
QUESTIONS
UNIT NO- 1 :
Fundamentals of Digital Systems and Logic families
TOPIC:1 : Binary Systems
Sr. SHORT QUESTIONS (1 Mark) / MCQ / True-False/Fill in the blanks Marks
No
1 Fill in the Blanks: [LJIET] 01
1) The decimal 8 is represented as ________ using Gray Code. [LJIET] Answer : (1100) Marks
2) 10’s complement of 428 is ________.[LJIET] Answer : (572) Each
3) The decimal equivalent of hex number 1A53 is _______. [LJIET]Answer : (6739)
4) _________be the decimal equivalent of 111011.10[LJIET]Answer : (59.625)
5) The hexadecimal number ‘A0’ has the decimal value equivalent to ______.[LJIET]
Answer : (160)
6) The 2’s complement of the number 1101101 is _________. [LJIET]
Answer : (0010011)
7) -8 is equal to signed binary number ___________. [LJIET] Answer : (10001000)
8) The decimal equivalent of Binary number 11010 is _________.[LJIET]
Answer : (26)
9) The hexadecimal number for (95.5)10 is _________.[LJIET] Answer : (5F.8) 16
10) The octal equivalent of (247)10is _________.[LJIET]Answer : (367) 8
11) The decimal equivalent of ( 1100)2 is _______. [LJIET] Answer : (12)
12) The Extended ASCII Code (American Standard Code for Information Interchange) is a
_____ code [LJIET]Answer : (7- bit)
13) The excess-3 code of decimal 7 is represented by______.[LJIET]Answer : (1010).
2 Give True or False. Correct False statement with Justification:[LJIET] 01
1) 2's complement of any binary number can be calculated by adding 1's complement Marks
twice.[LJIET]Answer :(False- By adding 1 to 1's complement) Each
2) The 2’s complement of the number 1101110 is 0010001.[LJIET]Answer :(False –
0010010)
3 Answer the following: [LJIET] 01
1) Define Nibble and Byte.[LJIET] Marks
Answer : i). In binary number a group of four bits. ii). A group of 8 bits are called Each
Byte.
2) Define Digital Systems.[LJIET]
Answer :A system which processing discrete or digital signal is called as Digital
System
4 Define Nibble. (May’16 OLD)[LJIET] 01
5 Convert decimal number (43)10 to binary. (Dec’15 OLD)[LJIET] Answer : (101011)2 01
6 Convert octal number (234)8 to hexadecimal. (Dec’15 OLD)[LJIET] Answer : (9C)16 01
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L.J. Institute of Engineering & Technology Semester: III (2021)
7 Do as directed : (May’16 OLD)[LJIET] 03

I. Given that (16)10 = (100)x, find the value of x. Answer : 4 (01
II. Add (6E)16 and (C5)16 Answer : (133)16 Marks
III. (4433)5 = ( )10 = ( )2 Answer : (1118)10 , (10001011110)2 Each)
8 Select the most appropriate option(Dec’14 OLD)[LJIET] 03
(i) Convert the decimal number 187 to 8-bit binary. (01
(A) 101110112 (B) 110111012 (C) 101111012 (D) 101111002 Answer : (A) Marks
(ii)Convert the binary number 1001.00102 to decimal. Each)
(A) 90.125 (B) 9.125 (C) 125 (D) 12.5 Answer : (B)
(iii) The 2’s complement of the number 1101110 is
(A) 0010001. (C) 0010010. (C) 0000000 (D) None.Answer : (B)
9 Do as directed : (May’16 OLD)[LJIET] 04
I. (1011011101101110)2 = ( )16 Answer : (B76E)16 (01
II. Subtract (45)8 from (66)8 Answer : (21)8 Marks
III. Covert the Gray code 1101 to binary Answer : (1001)2 Each)
IV. Find the XS-3 code of 37 Answer : (01101010)XS3
10 (56)16 = (?)10(Jan’17 OLD)[LJIET] Answer : (86)10 01
11 (32)10 = (?)2(Jan’17 OLD)[LJIET] Answer : (100000)2 01
12 The digit F in Hexadecimal system is equivalent to —— in decimal system 01
(a)16 (b)15 (c)17 (d) 8(June’17 OLD)[LJIET]Answer : (b)
13 (734)8 = ( )16 (a) C1D (b) DC1 (c) 1CD (d) 1DC Answer : (d) (June’17 OLD)[LJIET] 01
14 1 Kb corresponds to _______ (June’17 OLD)[LJIET] 01
(a) 1024 bits (b) 1000 bytes (c)210 bytes (d) 210 bits Answer : (a)
15 (i) Define: Digital System(March’10 OLD) [LJIET] 07
(ii) Convert following Hexadecimal Number to Decimal (01
B28, FFF, F28 Answer : (2856,4095,3880)10 Marks
(iii) Convert following Octal Number to Hexadecimal and Binary 414, 574, 725.25 Answer : Each)
(10C,17C,1D5.54)16 , (100001100, 000101111100, 111010101.010101)2
16 Convert the following numbers to decimal(Dec’9 OLD) [LJIET] 07
(i) (1001.101)2 Answer : (17.625)10 (ii) (101011.11101)2 Answer : (43.90625)10 (iii) (01
(0.365)8 Answer : (0.47851563)10(iv) A3E5 Answer : (41957)10 (v) CDA4 Answer : Marks
(52644)10(vi) (11101.001)2 Answer : (29.125)10 (vii) B2D4 Answer : (126)10 Each)
17 Do as directed (Jan’17 OLD) [LJIET] 07
(i) (645.65625)10 = ( )2 Answer : (1000000000.10101)2 (01
(ii) (FACE.25)16 = ( )10 Answer : (64206.14453125)10 Marks
(iii) (11011)Gray = ( )10 Answer : (18)10 Each)
(iv) Subtract (45)10 from (93)10 using 1’s Complement Method Answer : (48)10
(v) (ABC.555)16 = ( )8 Answer :(5274.2525)8
(vi) (2493)10 = ( )Excess-3 CodeAnswer : (0101011111000110) Excess-3 Code
(vii) (1525)10 = ( )Gray codeAnswer :(11100001111)Gray code
18 Converts the following nos. 04 (01
(i) (52)10 = ( )2 (ii) (436)8 = ( )16 (iii) (5C7)16 = ( )10 (iv) (11011.101)2 = ( )10 (Nov’17 Marks
OLD)[LJIET] Each)
19 Do as directed: 1) (673.124)8 = ( )2 2) (4522.25)10 = ( )2 3) (FACE)16 = ( )10 4) 07(01
(10101010)2 = ( )8 = ( )16 5) Subtract using 2’s complement method. (10010)2 – (10011)2 Marks
6) (10101101)2 = ( )gray Each)
7) (8620)10 = ( ) BCD = ( )2421 (Nov’17 OLD) [LJIET]
20 Represent following numbers in 8 Bit Binary representation: (i) (126)10 (ii) (79)10 (iii) (-128)10 03
(Jun’19 OLD)[LJIET]
21 Do as directed. (Jun’19 OLD)[LJIET] 07
i. Find 8 bit representation of (-1)10=(_________)2
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ii. Find A+A'B =__________.

iii. _____ and _______ can work as universal gates.
iv. Define term: Propagation Delay
v. By keeping one input HIGH, NAND gate can work as Inverter to second input. (T/F)
vi. Convert (FFFF)16=(________)10.
vii. Convert (125.625)10=(________)2
DESCRIPTIVE QUESTIONS Marks
1 Add the two numbers (A3E5)16 + ( CDA4)16 (Dec’14 OLD) [LJIET] 02
2 Convert decimal number (0.252)10 to binary with an error less than 1 %. (Dec’15 OLD)[LJIET] 03
3 Perform addition in BCD format (79)BCD + (16)BCD(May’15 OLD)[LJIET] 03
4 Perform subtraction of (78)10 – (58)10 using 2’s complement addition method. (May’15 03
OLD)[LJIET]
5 (1) Represent the decimal number 8620 in BCD, Excess-3, and Gray code (Dec’11 OLD) 03
[LJIET]
(2) Convert decimal 8620 into BCD, excess-3 and Gray code.(May’11OLD) [LJIET]
6 Convert (96)10 to its equivalent Gray code and EX-3 code.(May’15 OLD)[LJIET] 04
7 What are the different types of the codes used in digital systems? Explain them. (May’16 OLD) 04
[LJIET]
8 Do as directed(May’15 OLD)[LJIET]
(i) Convert (75)10 = (____________)2 06
(ii) Convert (101011)2 = (_____)10
(iii)Convert (10101101)2 = (_____)16 = (______)8
(iv)What is self-complementing code? Represent (472)10 in 2421 self-complementing Code
9 Convert the following Hexadecimal numbers to Octal. (Dec’15 OLD) [LJIET] 06
(a) 4F7.A8 (b) BC70.OE (c) 42FD
10 Convert following 1. (4E7.2)16 = (?)8 2. (521.3)8 = (?)2(May’14 OLD) [LJIET] 06
11 Convert the decimal number 225.225 to binary, octal and hexadecimal (Dec’11 OLD) [LJIET] 06
Convert the decimal number 225.225 to binary, octal and hexadecimal (May’11 OLD) [LJIET]
03
12 Convert following numbers.(June’15 OLD) [LJIET] 07
(a)(4021.2)5 = ( )10. (b) (B65F)16= ( ) 10. (c) (630.4)8 = ( ) 10. (d) (41) 10 = ( )
13 Explain r’s complement with example in detail. (June’16 OLD) [LJIET] 07
14 Explain (r-1)’s complement with example in detail.(June’16 OLD) [LJIET] 07
15 (i) Using 10’s complement, subtract : (72532-3250) 10(June’15 OLD) [LJIET] 07
(ii) Using 10’s complement, subtract : (3250-72532) 10
(iii) Using 2’s complement, subtract : (1010100-1000100) 2
16 Explain error detection codes and the reflected code with examples.(June’15 OLD) [LJIET] 07
17 1.Do subtraction using 12-bit two’s complement addition method: 27.125 – 79.625 07
2. Do BCD addition for given numbers : 679.6 + 536.8 (Dec’14 OLD) [LJIET]
18 Write a brief note on Gray codes. Also discuss methods for conversion from gray to binary code 07
and vice versa.(May’14 OLD) [LJIET]
19 Convert the following numbers as directed: (1) (130)10 = ( )2 (2) (1011011)2 = ( )10 07
(3) (1011101111)2 = ( )8 (4) (110111011101111011)2 = ( )16 (Nov’13 OLD) [LJIET]
20 1. Convert the decimal number 250.5 to base 3, base 4, base 7 and base 16 (May’12 OLD) 04
[LJIET]
2. Convert the decimal number 250.5 to base 3, base 4, base 7 and base 16 (May’13 OLD) 07
[LJIET]
3. Convert the decimal number 250.5 to base 3, base 4, base 7 and base 8 and base 16 (Jan’13 14
OLD) [LJIET]
4. Convert the decimal number 250.5 to base 3, base 4, base 7 and base 8 (June’17 04
OLD)[LJIET]
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21 Perform the subtraction with the following decimal numbers using 1’s compliment and 2’s 07
compliments: (a) 11010-1101 , (b) 10010-10011(May’13 OLD) [LJIET]
22 Explain Excess 3 code and 2421 code in detail. (June’16 OLD) [LJIET] 07
23 Convert the following Numbers as directed: (1) (52)10 = ( )2 (2) (101001011)2 = ( )10 07
(3) (11101110)2 = ( )8 (4) (68)10 = ( )16 (Dec’10 OLD) [LJIET]
24 Perform the operation of subtractions with the following binary number using 2’s complement 07
(i) 10010 – 10011 (ii) 100 – 110000 (iii) 11010 – 10000 (Dec’9 OLD) [LJIET]
25 Find the 10’s complement of the following: (1) (935)11 (2) (6106)10(Jan’17 OLD)[LJIET] 04
26 Obtain the truth table of the function: F= xy + xyʹ + yʹz. (Jan’17 OLD)[LJIET] 03
27 Convert 4BAC16= ( )8 = ( )4 = ( )2 = ( )10. Show all steps of conversion (May’17 OLD) [LJIET] 07
28 Perform following subtraction using 2’s complement method. (11010)2 – (10000)2 (Nov’17 03
OLD) [LJIET]
29 Write a brief note on Gray codes. Also discuss methods for conversion from gray to binary 07
code and vice versa (May’18 OLD) [LJIET]
30 Explain (r-1)’s complement with example in detail. (May’18 OLD) [LJIET] 07
31 Convert 1000 0110 (BCD) to decimal, binary & octal (May’18 OLD)[LJIET] 03
32 Convert 33.4510 to binary. Result should be accurate to within 0.0110. (May’18 OLD)[LJIET] 04
33 Convert the following numbers form given base to the base indicates. (Dec’18 OLD)[LJIET] 03
1. (AEF2.B6)16 = (_____)2 2. (674.12)8 = (______)10 3. (110110.1011)2 = (______)16
34 Convert (4BAC)16 = (_____)8 = (_____)4 = (_____)2 = (_____)10 (Nov’18 OLD) [LJIET] 07
35 Convert following Decimal Number to Hex, Binary and octal Number. 07
1) 157.786 2) 937.125 (Nov’19 OLD) [LJIET]
36 (ADD)16= ( )10= ( )8 =( )4=( )2= ( ) binary =( )gray (Jun’19 OLD) [LJIET] 07
37 Explain the (r-1)’s complement method of operation using example (Jun’19 OLD) [LJIET] 07
38 Do as Directed 03
1. Given that (16)10 = (100)x. Find the value of x. 2. Add (6E)16 and (C5)16.
3. (1011011101101110)2 = (_____)8 = (_____)16 (Dec’19 NEW) [LJIET]
39 Explain Error Correcting codes [LJIET] 04
40 Define Following Terms. 03
1. Nibble 2. Negative Logic 3. Even Parity (Dec’19 OLD) [LJIET]
41 Convert the Decimal Number 412.5 to base 3, 4 and 7 (Mar’21 OLD) [LJIET] 03
42 Do as directed: 07
(a) (1111.11)2 = ( ? )8 = ( ? )10
(b) 23 – 48 using 2’s complement method
(c) (396)10 = ( ? )BCD = ( ? ) EX-3
(d) (11111)2 = ( ? )Gray (Mar’21 NEW) [LJIET]
43 Construct Hamming code for BCD 0110. Use even parity. (Mar’21 NEW) [LJIET] 04
44 Do as directed: 07
1. Express decimal number 60.875 into binary form.
2. One 8421 code word is transmitted in Hamming code with even parity checking. The
received word is 0101000. Find out the correct code word and write decimal equivalent.
(Nov’20 NEW) [LJIET]
TOPIC:2 : Logic Circuits

SHORT QUESTIONS (1 Mark) / MCQ / True-False/Fill in the blanks Marks
1 Fill in the Blanks: [LJIET] 01
1) NOR gate is formed by connecting ___ [LJIET] Answer: (OR Gate and then NOT Gate) marks
2) Tri-State Buffer is basically a/an _________ gate.[LJIET] Answer : (NOT) Each
3) The NAND gate output will be low if the two inputs are _____.[LJIET] Answer :(1&1)
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4) The output of a logic gate is 1 when all its inputs are at logic 0. the gate is either
____________. [LJIET] Answer : (a NOR or an EX-NOR)
5) In a positive logic system, logic state 1 corresponds to lower voltage level.[LJIET] Answer
: (higher voltage level)
6) _______ AND gates are required to realize Y = CD+EF+G [LJIET] Answer : (2)
7) The following waveform pattern is for a(n) _____[LJIET]Answer: (Exclusive-OR gate)
8) The following waveform pattern is for a(n) _______[LJIET] Answer : (2-input OR

gate)
9) The 8-input XOR circuit shown has an output of Y = 1. Correct input combination below
(ordered A – H) is _________.[LJIET] Answer : (10111100)
2 Give True or False. Correct False statement with Justification:[LJIET] 01

1) OR gate is known as Universal gate[LJIET] Marks
Answer :(False – NAND and NOR are universal Gate.) Each
2) AND logical operations is represented by the + sign in Boolean algebra.[LJIET]
Answer : (False-OR)
3) The inverter can be produced with 2 NAND gates.[LJIET]
Answer :(False – 1 NAND Gate)
4) Bidirectional means having two states. [LJIET] Answer :(False- Bistable)
“3” two-input AND and “3” OR gates are required to realize Y=CD+EF+G. Answer :(2,2)
4 Define Fan-out. (Dec’15 OLD ,May’16 OLD)[LJIET] 01
5 Which gates are called as universal gates? What are its advantages? (May’16 OLD)[LJIET] 01
Answer :NAND , NOR gates . Because we can construct all gates using them.
6 Do as directed :Find the logic required at R input. (May’15 OLD)[LJIET] Answer : R=1 01
7 Bubbled OR is also called _______________.(Dec’15 OLD)[LJIET] Answer : NAND 01

8 Which gates are also known as controlled NOT gate? (Dec’15 OLD)[LJIET] 01
Answer : XOR,XNOR
9 Define the following terms: Universal gate (Nov’13 OLD) [LJIET] 01
(i) If a 3-input NOR gate has eight input possibilities, how many of those possibilities will (01
result in a high output? Marks
(A) 1 (B) 2 (C) 7 (D) 8 Answer : (C) Each)
(ii) If a signal passing through a gate is inhibited by sending a LOW into one of the inputs,
and the output is HIGH, the gate is a(n):
(A) AND (B) NAND (C) NOR (D) OR Answer : (B)
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(iii) When used with an IC, what does the term “QUAD” indicate?
(A) 2 circuits (B) 4 circuits (C) 6 circuits (D) 8 circuits Answer : (B)
11 Define followings with respect to logic families.(May’15 OLD)[LJIET] 04
(i) Fan in (ii) Fan out (iii) Noise Margin (iv) Propagation delay
12 Define the followings.(Dec’14 OLD)[LJIET] (i) Propagation delay (ii) Fan in (iii) Noise 04
Margin (iv) Negative Logic
13 Explain briefly: propagation delay, fan out(Dec’11 OLD) [LJIET] 02
14 Define: Noise margin, Propagation delay (May’11 OLD) [LJIET] 02
15 Bubbled OR gate is also called_______ (Jan’17 OLD)[LJIET] Answer : NAND 01
16 Define: Fan in (Jan’17 OLD)[LJIET] 01
17 Define: Noise Margin (Jan’17 OLD)[LJIET] 01
18 Design a NOT gate using a two input Ex-OR gate (Jan’17 OLD)[LJIET] Answer : NOT gate 01
is designed by connecting any one input terminal to ‘1’ or ‘Vcc’ of Ex-OR gate
19 Which logic family is the fastest logic family? (Jan’17 OLD)[LJIET] Answer : TTL 01
20 Which logic family consumes the less power? (Jan’17 OLD)[LJIET] Answer : CMOS 01
21 Define : Negative Logic (Jan’17 OLD)[LJIET] 01
22 The output of a ____ gate is only 1 when all of its inputs are 1 (June’17 OLD)[LJIET] 01
(a) NOR (b) XOR (c) AND (d) NOT Answer : (c)
23 Which gate equivalent is to bubbled OR gate? (June’17 OLD)[LJIET] 01
(a) AND (b) XOR (c) NOT (d) NAND Answer : (d)
24 A NOT gate has… (June’17 OLD)[LJIET] 01
(a) Two inputs and one output (b) One input and one output
(c) One input and two outputs (d) none of above Answer : (b)
25 The digital logic family which has minimum power dissipation is (June’17 OLD)[LJIET] 01
(a) TTL (b) RTL (c) DTL (d) CMOS Answer : (d)
26 Define the following terms (June’17 OLD)[LJIET] 05
1.Positive Logic 2. Negative Logic 3. Fan In 4. Fan out 5. Noise Margin
27 Define: 1) Fan in 2) Noise Margin 3) Propagation Delay (Nov’17 OLD)[LJIET] 03
28 Define following: Figure of merit, Noise margin, and Power dissipation (Mar’21 03
NEW)[LJIET]

1 Answer the following(May’11 OLD) [LJIET] 02
Draw symbol and construct the truth table for three input Ex-OR gate
2 Implement Boolean expression for Ex-OR gate using NAND gates only (May’11 OLD) 04
[LJIET]
3 Discuss NAND gate as universal gate (implement NOT, AND OR & NOR gate using NAND 04
gate).(May’15 OLD)[LJIET]
4 Define and explain (i) fan out (ii) power dissipation and (iii) Propagation delay 07
(June’15 OLD) [LJIET]
5 Explain the digital IC Parameters.(Dec’14 OLD) [LJIET] 07
1. Fan in, Fan out 2. Propagation Delay 3. Power Dissipation 4. Noise Margin
6 Answer the following questions(Dec’14 OLD) [LJIET] 05
1. Find out Y, if B=1 and A=Square wave
2. explain SSI, MSI, LSI and VLSI

7 Define: Integrated Circuit and briefly explain SSI, MSI, LSI and VLSI (March’10 OLD) 07
[LJIET]
8 Draw symbol and truth table for four input EX-OR gate. Explain NAND and NOR as an 06
universal gate.(Dec’11 OLD) [LJIET]
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9 Draw the logic diagrams of NAND & NOR gates & explain why they are called as universal 07
gates.(Dec’15 OLD) [LJIET]
10 Draw and explain two input (i) AND (ii) OR and (iii) EX-OR gates.(June’15 OLD) [LJIET] 07
11 1. Give comparison for TTL and CMOS family.(Dec’14 OLD) [LJIET] 07
2. Implement basic gates using DTL logic.
12 What is positive and negative logic? Explain in detail. (June’16 OLD) [LJIET] 07
13 Show that 07
Also construct the corresponding logic diagrams. (May’16 OLD)[LJIET]
14 1. Explain NAND and NOR as an universal gates.(May’11 OLD) [LJIET] 04
2. Explain with figures how NAND gate and NOR gate can be used as Universal gate.(Dec’10 07
OLD) [LJIET]
3. Justify the statement: “NAND and NOR gates are universal gates.”(Jan’17 OLD) (Nov’19 07
OLD) [LJIET] 07
4. Discuss Universal gates. Obtain AND, OR gate using NAND and NOR gates.
(Nov’17 OLD)[LJIET] 07
5. Explain how NAND amd NOR gates can be utilized as universal gates to implement
all the basic gates. (Nov’17 OLD) [LJIET]
15 Draw the logic symbol and construct the truth table for each of the following gates. 07
[1] Two input NAND gate [2] Three input OR gate
[3] Three input EX-NOR gate [4] NOT gate (March’10 OLD) [LJIET]
16 Give classification of Logic Families and compare CMOS and TTL families (March’10 OLD) 07
[LJIET]
17 Explain with neat logic diagram and truth table the functioning of basic logic gates. (Jan’17 07
OLD) [LJIET]
18 With neat logical diagram and truth table explain all the basic gates including NAND, NOR, 07
EX-OR, and EX-NOR gate. (Nov’17 OLD) [LJIET]
19 Explain with neat logic diagram and truth table of the functioning of basic logic gates 07
(May’18 OLD) [LJIET]
20 Implement NOT, AND, & OR gates using NAND gates only (May’18 OLD)[LJIET] 03
21 Generate AND, OR, NOT, EXOR and EX-NOR gate using NAND as a universal gate 07
(Jun’19 OLD)[LJIET]
22 With neat logical diagram & truth table explain all the basic gates including NAND, NOR, EX- 07
OR, EX-NOR gate (Nov’18 OLD) [LJIET]
23 What is positive and negative logic? Give one example of each (Jun’19 OLD) [LJIET] 07
24 Use NOR gate as a universal gate and construct all basic gates from it (Jun’19 OLD) [LJIET] 07
25 Use NAND gate as a universal gate and construct all basic gates from it(Jun’19 OLD) 07
[LJIET]
26 Implement AND, OR, & EX-OR gates using NAND & NOR gates.(Dec’19 NEW)[LJIET] 07
27 Answer the following Questions: (Dec’19 OLD) [LJIET] 03
1. Find 2’s Complement Representation of (-52)10 .
2. Convert the binary number (1101110.0110)2 to decimal.
3. For a given logic circuit, if A=B=1, and C=D=0. Find output Y
28 Realize AND, OR and NOT gate using NAND gates only (Mar’21 NEW) [LJIET] 03
29 List out three basic logic operations. Realize these operations using NOR gates only. (Nov’20 04
NEW) [LJIET]
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Topic: 3 Logic Families

SHORT QUESTIONS (1 Mark) / MCQ / True-False/Fill in the blanks
1 Do as Directed [LJIET] 01
1.Fill in the Blanks: [LJIET] Marks
1) The digital logic family which has minimum power dissipation is_________ .[LJIET] Each
Answer :(CMOS)
2) In digital ICs, Schottky transistors are preferred over normal transistors because of their
___________. [LJIET] Answer :(Lower Propagation delay.)
2 Give True or False. Correct False statement with Justification:[LJIET]
(1) Power consumption of TTL is higher than of CMOS [LJIET] Answer :(True)
(2) DTL consume minimum power. [LJIET] Answer :False- CMOS
3 Answer the following: [LJIET]
1) List the characteristics of digital ICs[LJIET]
a. Propagation delay ii) Power dissipation iii) Fan-in iv) Fan-out v) Noise margin
2) Why totem pole outputs cannot be connected together.[LJIET]
Totem pole outputs cannot be connected together because such a connection might
produce excessive current and may result in damage to the devices.
3) State advantages and disadvantages of TTL[LJIET]
Advantage:
1. Easily compatible with other ICs
2. Low output impedance
Disadvantage:
1. Wired output capability is possible only with tristate and open collector types
2. Special circuits in Circuit layout and system design are required
2 Which TTL logic gate is used for wired ANDing? (May’16 OLD)[LJIET] 01
Answer :Open collector output
Which TTL logic gate is used for wired ANDing
(A) Open collector output (B) Totem Pole (C) Tri state output (D) ECL gates
Answer : (A)
4 Define the followings. Totem Pole output (Dec’14 OLD)[LJIET] 01
5 Which circuit is used to eliminate chattering? (Dec’15 OLD)[LJIET] 01
Answer : RC Low pass Filter or Shift register based debouncing switch

1 1. Compare the following in every aspect. TTL and CMOS (Dec’14 OLD)[LJIET] 3.5
2. Give comparison of TTL and CMOS family (Nov’17 OLD)[LJIET] 03
3. Compare the Following in every aspect: TTL and CMOS (Dec’19 OLD)[LJIET] 03
2 Explain two input CMOS NAND gate.(May’16 OLD)[LJIET] 07
3 Compare TTL, ECL, & CMOS logic families. (Dec’15 OLD)[LJIET] 07
Compare TTL, ECL, & CMOS logic families. (May’18 OLD)[LJIET] 07
4 Describe briefly TTL fanin, fanout& noise margin with suitable sketches (Dec’15 OLD) 07
[LJIET]
5 Give classification of logic families. Also list the characteristics of digital IC(Jan’17 03
OLD)[LJIET]
6 Explain wired logic with examples.(June’15 OLD) [LJIET] 07
7 Distinguish between micro program control and hard-wired control. (May’18 OLD) [LJIET] 07
DF (3130704) 2021 Page 8

8 List out various logic families. Also list the characteristics of digital ICs. (May’18 03
OLD)[LJIET]
9 Discuss the advantages and disadvantages of TTL Logic Family (Dec’18 OLD)[LJIET] 03
10 Explain following terms w.r.t Digital Logic Family.1. Fan-in 2.Noise Margin 3. Power 03
Dissipation (Dec’18 OLD)[LJIET]
11 Give comparison of TTL and CMOS family (Jun’19 OLD)[LJIET] 03
Define following parameters related to logic family and Compare all the logic families based 07
on these parameters :(i) Propagation Delay (ii) Fan-out (iii) Fan-in (iv) Noise margin (Nov’19
OLD)[LJIET]
12 Draw and explain the working operation of 2- INPUT TTL NAND gate (Dec’19 04
OLD)[LJIET]
13 Explain NAND and NOR gate using RTL and DTL circuit in detail with necessary diagram and 03
truth-table (Mar’21 OLD)[LJIET]
14 Explain TTL Circuit in Detail (Mar’21 OLD)[LJIET] 03
15 Define : Integrated Circuit and briefly explain SSI, MSI, LSI and VLSI (Mar’21 03
OLD)[LJIET]
16 Define Following Terms. (Mar’21 OLD)[LJIET] 04
1. Propagation delay 2. Fan-out.3. Fan-in. 4.Power Consumption
UNIT NO- 2 :
Combinational Digital Circuits
TOPIC:1 : Boolean Algebra
No
(1) The expression “AB+C = A+BC” is an example of Commutative Law for Marks
Multiplication.[LJIET] Answer :(False - AB=BA) Each
(2) State the associative property of Boolean algebra.[LJIET]
The associative property of Boolean algebra states that the OR ing of several variables
results in the same regardless of the grouping of the variables. The associative property
is stated as follows: Answer :i). A+ (B+C) = (A+B) +C ii). A (B C) = (A B) C
(3) State the commutative property of Boolean algebra.[LJIET]
The commutative property states that the order in which the variables are OR ed makes
no difference. The commutative property is Answer :i). A+B=B+Aii). AB = BA
(4) What are the 2 forms of Boolean expression?[LJIET]
The two forms of Boolean expressions are: Answer :Sum of Products Form and
Product of Sum Form
2 State the associative property of Boolean algebra (May’16 OLD)[LJIET] 01
Answer : (A*B)*C = A*(B*C) , (A+B)+C = A+(B+C)
3 Write D’Morgan’s Theorems (Dec’14 OLD)[LJIET] Answer : (A B )’ = A’ + B’ , (A+B)’ = 01
A’ B’
4 State the distributive property of Boolean algebra (Jan’17 OLD)[LJIET] 01
Answer : A(B+C) = AB + AC , A+BC = (A+B) (A+C)

1 Answer the following : What is the principle of Duality Theorem?(May’11 OLD) [LJIET] 02
2 Reduce the expression F = ((AB)’+A’+AB)’ (May’16 OLD)[LJIET] 03
DF (3130704) 2021 Page 9

3 Demonstrate by means of truth tables the validity of the following Theorems of Boolean 3.5
algebra:- The Distributive law of + over . (Dec’9 OLD) [LJIET]
4 Reduce following Boolean function and then realize the reduced one using NOR gate only. 04
X = A (B'+C') (A+D) (Dec’15 OLD)[LJIET]
5 Minimize the following Boolean expressions. (Dec’15 OLD)[LJIET] 04
1. X = ( (A'B'C')' + (A'B)' )' 2. Y = AB + ABC' + A'BC + A'BC'
6 State De-Morgan’s theorems and prove with the help of truth table.(May’15 OLD, Nov’17 04
OLD)[LJIET]
7 1. State and prove De-Morgan’s Theorems with the help of Truth tables. (Nov’13 OLD) 07
[LJIET]
2. Demonstrate by means of truth tables the validity of the following Theorems of Boolean 3.5
algebra : De Morgan’s theorems for three variables (Dec’9 OLD) [LJIET]
3. State & explain Demorgan’s theorem (Dec’15 OLD) [LJIET] 07
4. State and Prove D’Morgan Theorem for three variables (June’17 OLD)[LJIET] 03
5. State and Prove D’Morgan Theorem (June’17 OLD)[LJIET] 02
6. State & explain Demorgan’s theorem (May’18 OLD) [LJIET] 07
7. State & prove De Morgan’s theorems with the help of truth tables. (May’18 OLD)[LJIET] 04
8. Sate and prove DeMorgan Theorem (Dec’18 OLD)[LJIET] 03
9. State and explain De Morgan’s theorems with truth tables (May’16 OLD) (Jun’19 04
OLD)[LJIET]
10. State and prove Demorgan’s theorem (Nov’18 OLD) [LJIET] 07
11. State and explain De Morgan’s theorems with truth tables. (Dec’19 NEW)[LJIET] 04
8 Prove the following Boolean identities.(Dec’14 OLD)[LJIET] 07
(i) XY + YZ + Y’ Z = XY + Z (ii) A .B + A’ . B + A’ . B’ = A’ + B
9 Prove that (i) A[B+C(AB+AC)’] = AB(ii) AB’ (C+BD) + A’ B’= B’C (Dec’15 OLD) [LJIET] 08
10 Simplify using Boolean laws and draw the logic diagram for the given expression. 07
F = (ABC)’ + (AB)’ C + A’ B C’ + A (BC)’ + A B’ C(Dec’14 OLD)[LJIET]
11 Simplify 1. A’B + A’BC’ + A’BCD + A’BC’D’E(May’14 OLD) [LJIET] 08
2. (P+Q+R) (P’+ Q’+ R’) P
12 Prove that: 1. ((A’B+ABC)’ + A(B+AB’))’ = 0(May’14OLD) [LJIET] 07
2. AB’C + A’BC + ABC = AC + AB
13 Simplify the following Boolean function to minimum numbers of literals. 07
(a) xyz+x’y+xyz’ and (b) (A+B)’(A’+B’)’(May’13 OLD) [LJIET]
14 Obtain the truth table of the function F=xy+xy’+y’z OR Implement the Boolean 07
functions.(May’13 OLD) [LJIET]
15 Show that the dual of the exclusive-OR is equal to its compliment.(May’13 OLD) [LJIET] 07
16 Find the complement of the following Boolean function and reduce to a minimum number of 07
literals. B’D + A’BC’ + ACD + A’BC(Jan’13 OLD) [LJIET]
17 Listout and explain the most common postulates used to formulate various algebraic structures. 07
18 Reduce the expression: (1) A+B(AC+(B+C’)D) (2) (A+(BC)’)’(AB’+ABC) (Dec’10 OLD) 07
[LJIET]
19 Explain error detecting & correcting codes with the help of a suitable example. (Dec’15 OLD) 07
[LJIET]
20 Show that (A + C) (A + D) (B + C) (B + D) = AB + CD (Jan’17 OLD)[LJIET] 03
21 Simplify Using boolean laws and draw the logic diagram for the simplified expression. 04
F = (ABC)’+(AB)’C+A’BC’+A(BC)’+AB’C (June’17 OLD)[LJIET]
22 Show that AB’C + B + BD’ + ABD’ + A’C = B + C (Nov’17 OLD)[LJIET] 03
23 Simplify : 1. A’B + A’BC’ + A’BCD + A’BC’D’E 2. (P+Q+R) (P’ + Q’ + R’) P (May’18 07
OLD) [LJIET]
DF (3130704) 2021 Page 10

24 Express the Boolean function F=A+B’C a sum of min terms and in product of max terms. 07
25 i. Using laws of Boolean algebra prove that AB + BC + A'C = AB + A'C 07
ii. Minimize the logic function X = A(B' + C')(A + D). Also realize the reduced function using
NOR gates only. (May’18 OLD)[LJIET]
26 Simplify the following Boolean functions to a minimum numbers of literals. (Dec’18 04
OLD)[LJIET]
1. x + x’y 2. x (x’+y) 3. x’y’z + x’yz + xy’ 4. xy + x’z +yz
27 Simply Boolean Function : F=A'B'C+A'BC+AB' (Jun’19 OLD)[LJIET] 03
28 Find the Boolean Equation for following circuit and simplified Boolean equation (Jun’19 04
OLD)[LJIET]
29 Obtain canonical Sum of Product form of following function: F=AB+ACD (Jun’19 03

OLD)[LJIET]
30 Using the law of Boolean algebra prove that (Nov’18 OLD) [LJIET] 07
(i) AB + BC + A’C = AB + A’C (ii) A [ B + C (AB + AC)’] = AB
31 Expand A+BC’+ABD’+ABCD to minterm and maxterm. (Nov’19 OLD) [LJIET] 07
32 Discuss canonical and standard form of representation (Jun’19 OLD) [LJIET] 07
33 Explain Associative Laws (Mar’21 OLD) [LJIET] 03
34 Explain arithmetic, logic and shift micro operations (Mar’21 OLD) [LJIET] 04
35 Write a short note on Arithmetic, Logic and Shift operations (Jun’19 OLD) [LJIET] 07
36 Explain SOP and POS expression using suitable examples. (Mar’21 OLD) [LJIET] 04
37 State and prove De-Morgan’s theorems using truth-tables. (Mar’21 NEW) [LJIET] 04
38 Prove following using the Boolean algebraic theorems: 03
1. A + A’B + AB’ = A + B
2. AB + A’B + A’B’ = A’ + B (Nov’20 NEW) [LJIET]
39 List out various methods of simplifying a given Boolean function. Solve F = AB + AB’ using 03
any two methods. (Nov’20 NEW) [LJIET]
TOPIC:2 : Mapping Methods

1 Do the following [LJIET] 01
1.Fill in the blanks [LJIET] Marks
1) Half-Adder Logic circuit contains _____ XOR Gates [LJIET] Answer :(1) Each
2) The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms
[LJIET] Answer :(8)
3) The Boolean SOP expression obtained from the truth table below is
________.[LJIET]Answer : A’B’C+ABC’
2. Give True or False. Correct False statement with Justification:[LJIET]
DF (3130704) 2021 Page 11

1) Parallel adders are Sequential logic circuit. [LJIET]

Answer :(False- It is Combinational Logic Circuit.)
2) In half adder EX-OR gate O/P is Carry[LJIET] Answer :(False – Sum)
3) Karnaugh map is used for the purpose of To maximize the terms of a given a Boolean
expression. [LJIET] Answer :(False - To minimize the terms in a Boolean
expression.)
3. Answer the following: [LJIET]
1) Define Minterm&Maxterm.[LJIET]
Answer :The products of Boolean expression where all possible variables appear once
in complement or uncomplimentary variables are called Minterm.
A sum terms in a Boolean expression where all possible variables appear once,
incomplement or uncomplement form are called Maxterm
2) Define Duality Theorem.[LJIET]
Answer :The Duality theorem states that starting with a Boolean relation we can derive
another Boolean relation by: i). Changing OR (operation) i.e., + (Plus) sign to an AND
(operation) i.e., (dot) and Vice-versa .ii). Complement any 0 or 1 appearing in the
expression i.e., replacing contains 0 and 1by 1 and 0 respectively.
3) What are called don’t care conditions?[LJIET]
Answer :In some logic circuits certain input conditions never occur, therefore the
corresponding output never appears. In such cases the output level is not defined, it can
be either high or low. These output levels are indicated by ‘X’ or ‘d’ in the truth tablesand
are called don’t care conditions or incompletely specified functions.
4) What is tabulation method?[LJIET]
Answer :A method involving an exhaustive tabular search method for the minimum
expression to solve a Boolean equation for more variables is called as a tabulation
method.
5) What is a prime implicant?[LJIET]
Answer :A prime implicant is a product term obtained by combining the maximum
possible number of adjacent squares in the map. They cannot be reduced further.(Or)A
prime implicant is a group of minterms which cannot be combined with any other
minterm or groups.
6) Define Fan-in & Fan-out.[LJIET]
Answer :Fan-in: The fan-in of a gate is the number of inputs connected to the gate
without any degradation in the voltage levels.
Fan-out : It is defined as the maximum number of inputs of the same IC family hat a
gate can drive maintaining its output levels within the specified limits.
7) Define combinational logic.[LJIET]
Answer :When logic gates are connected together to produce a specified output for
certain specified combinations of input variables, with no storage involved, the resulting
circuit is called combinational logic
8) Define Half adder and full adder[LJIET]
Answer: Half Adder: The logic circuit that performs the addition of two bits
Full Adder: The circuit that performs the addition of three bits is a full adder.
2 What are called Don’t care conditions? (May’16 OLD)[LJIET] Answer :Don't care 01
conditions for a function is an input-sequence (a series of bits) for which the function
output does not matter.
3 What is prime implicant? (May’16 OLD)[LJIET] Answer : The prime implicant is a group 01
of minterms which can’t be combined with any other groups.
DF (3130704) 2021 Page 12
4 Define: combinational logic circuit(Nov’13 OLD) [LJIET] 01

5 Define the following terms: (1) Literal (2) Minterm (3) Maxterm(Nov’13 OLD) [LJIET] 03
6 Explain briefly: SOP & POS, minterm&maxterm, canonical form(Dec’11 OLD) [LJIET] 03

1 Express following Function in Product of Maxterms F(x,y,z)=( xy + z) (y + xz) 03
2 Given Boolean function F = xy + x’y’ + y’z Implement it with only OR & NOT 05
gates2.Implement it with only AND & NOT gates (May’12 OLD) [LJIET]
3 (1) Draw the logic circuit for following using only NAND gates: F = ABC+A’B+AC’D’ 07
(2) Draw the logic circuit for following using only NOR gates: F = ABC’ + AB(C+D) (Nov’13
OLD) [LJIET]
4 Implement the Boolean functions. (a) xyz+x’y+xyz’ (b) (A+B)’(A’+B’)’ and 07
(c) F= xy+xy’+y’z with logic gates.(May’13 OLD) [LJIET]
5 Simplify the Boolean function, F= A’B’C’+B’CD’+A’BCD’+AB’C’. (June’16 OLD) [LJIET] 07
6 Simplify the Boolean function, F=Σ(0,1,2,5,8,9,10). (June’16 OLD) [LJIET] 07
7 Simplify the Boolean function, F= A’C+A’B+AB’C+BC. (June’16 OLD) [LJIET] 07
8 Implement the function F=Σ(0,6) with NAND gates only. (June’16 OLD) [LJIET] 07
9 Implement the function F=Σ(0,6) with NOR gates only. (June’16 OLD) [LJIET] 07
10 Implement the following Boolean functions(Dec’9 OLD) [LJIET] 07
(i) F= A (B +CD) +BC’ with NOR gates(ii) F= (A + B’) (CD + E) with NAND gates
11 Convert F(A, B, C) = BC + A into standard minterm form.(May’15 OLD)[LJIET] 03
3 Answer the following: (i) Explain briefly: standard SOP and POS forms. (ii) What are Minterms 04
and Maxterms? (May’11 OLD) [LJIET]
4 Reduce the expression F = ∑m(0,2,3,4,5,6) using K-map and implement using NAND gates 07
only. (May’16 OLD)[LJIET]
5 Reduce the given function using K-map and implement the same using gates. F(A,B,C,D ) = 07
Σm (0,1,3,7,11,15) + Σd ( 2,4) (May’15 OLD)[LJIET]
6 Minimize the following multiple output functions using K-Map (Dec’15 OLD) [LJIET] 07
(i) F1 = Σm=(0,2,6,10,11,12,13) + d(3,4,5,14,15) (ii) F2 =πM(0,4,9,10,11,14,15)
7 Minimize following Boolean function using K-map & design the simplified function using logic 07
gates. F = Σ m(1, 2, 4, 6, 7, 11, 15) + Σ d(0, 3) (Dec’15 OLD)[LJIET]
8 Express the Boolean function F=A+B’C a sum of minterms and in sum of max terms. 07
9 Simplify the Boolean function F(X,Y,Z)= ∑(2,4,5,6) using K – map. Explain groups. 07
10 Minimize the following logic function using K-maps and realize using NAND and NOR 07
gates.F(A,B,C,D) =Σm(1,3,5,8,9,11,15) + d(2,13).(Dec’14 OLD)[LJIET]
11 Minimize the logic function F (A,B,C,D) = π M (1, 2, 3, 8, 9, 10, 11, 14) . d (7, 15) Use Karnaugh 07
map. Draw the logic circuit for simplified function using NOR gates only.
(Dec’14 OLD)[LJIET]
12 Reduce using K-map Σ m (0, 2, 6, 10, 11, 12, 13) + d (4, 5, 14, 15)(Dec’14 OLD) [LJIET] 07
13 Obtain the set of prime implicants for Σ m (0, 1, 6, 7, 8, 9, 13, 14, 15) (Dec’14 OLD) [LJIET] 07
14 Obtain the set of prime implicants for π M (2, 3, 8, 12, 13) . d (10, 14)(Dec’14 OLD) [LJIET] 07
15 Using K-map find the Boolean function and its complement for the following: F(A,B,C,D) = 07
∑(1,2,3,4,6,8,9,10,11,12,14)(May’14 OLD) [LJIET]
16 Derive Boolean function using Tabulation Method for the following: F(P,Q,R,S) = 07
∑(0,1,3,4,5,7,10,13,14,15)(May’14 OLD) [LJIET]
17 Attempt following: (May’14 OLD) [LJIET] 07
(1) Convert into Sum-of-Minterms: A’ + B + CA
DF (3130704) 2021 Page 13

(2) Convert into Product-of-Maxterms: A(A’+B)(C’)

18 1. Simplify the Boolean Function with Karnaugh map:(Nov’13 OLD) [LJIET] 07
(1) F(W,X,Y,Z) = ∑(0,1,2,4,5,6,8,9,12,13,14) and (2) F = A’B’C’ + B’CD’ +A’BCD’ +AB’C’
2. Simplify the Boolean function:(Dec’10 OLD, Nov’17 OLD) [LJIET]
(1) F(w,x,y,z) = ∑(0,1,2,4,5,6,8,9,12,13,14) (2) F(w,x,y) = ∑(0,1,3,4,5,7) 07
3. Simplify the Boolean function:(Dec’10 OLD) [LJIET]
(1) F = A’B’C’+B’CD’+A’BCD’+AB’C’ 07
(2) F =A’B’D’+A’CD+A’BC
d=A’BC’D+ACD+AB’D’ Where “d” indicate Don’t care conditions.
4.Simplify the following Boolean function using K-Map.(May’12 OLD) [LJIET] 04
F = A’B’C’+B’CD’+A’BCD’+AB’C’
19 1. Simply the Boolean Function:(Nov’13 OLD) [LJIET] 07
F(W,X,Y,Z) = ∑(1,3,7,11,15) and the Don’t care conditions : d(W,X,Y,Z) = ∑(0,2,5)
2. Implement the functions F=∑(1,3,7,11,15) with don’t care conditions d= ∑(0,2,5) 07
Discuss the effect of don’t care conditions.(May’13 OLD) [LJIET]
3. Simply the Boolean Function using K-map : F(W,X,Y,Z) = ∑(1, 3, 7, 11, 15) with don’t care 04
conditions d(W,X,Y,Z) = ∑(0, 2, 5)(May’11 OLD) [LJIET]
20 1. Simplify the Boolean Function by using tabulation method:F = ∑(0,1,2,8,10,11,14,15) 07
(Nov’13 OLD) [LJIET]
2. Simplify the Boolean Function by using tabulation method:F = ∑(0,1,2,8,10,11,14,15) 08
(Dec’11 OLD) [LJIET]
3. Simplify the following Boolean function using tabulation Method and draw logic diagram
using NOR gates only(May’11 OLD) [LJIET] 07
F(w,x,y,z ) = ∑(0, 1, 2, 8, 10, 11, 14, 15)
21 Obtain the simplified expression in sum of product for the following Boolean functions. 07
F= ∑(0,1,4,5,10,11,12,14) and F= ∑(11,12,13,14,15).(May’13 OLD) [LJIET]
22 Obtain the simplified expressions in sum of products using K-map: 07
x’z + w’xy’ + w(x’y+xy’)(Jan’13 OLD) [LJIET]
23 1. Simplify the following Boolean function by means of the tabulation method: 07
F(A,B,C,D,E,F,G) = ∑ (20,28,38,39,52,60,102,103,127)(Jan’13 OLD) [LJIET]
2. Determine the Prime Implicants of following Boolean Function using Tabulation Method.
F(A,B,C,D,E,F,G) = ∑(20,28,38,39,52,60,102,103,127)(May’12 OLD) [LJIET]
24 Convert the following to other canonical form.(Dec’15 OLD)[LJIET] 07
(i) F( x,y,z) = Σ( 1,3,7) (ii) F( A,B,C,D) = π ( 0,1,2,3,4,6,12)
25 Discuss canonical and standard forms in detail. (June’16 OLD)[LJIET] 07
26 1. Explain SOP and POS expression using suitable examples(March’10 OLD) [LJIET] 07
2. Explain SoP Expressions. How do they differ from PoS ? (May’17 OLD) [LJIET]
27 Obtain the simplified expressions in sum of products for the following Boolean 07
functions:(Dec’9 OLD) [LJIET] (i) F(A,B,C,D,E) = ∑(0,1,4,5,16,17,21,25,29)
(ii) A’B’CE’ + A’BCD’ + B’DE’ + BCD’
28 Simplify Boolean function F ( w,x,y,z ) = ∑( 0,1,2,4,5,6,8,9,12,13,14 ) using K-map and 08
Implement it using (i) NAND gates only (ii) NOR gates only(Dec’11 OLD) [LJIET]
29 Why NAND gate is known as universal gate? (Jan’17 OLD)[LJIET] 03
30 Convert the expression Y= A + BC into the standard SOP form (June’17 OLD)[LJIET] 03
31 Simplify following Boolean function by using the tabulation method F = Σ(0,1,3,7,8,9,11,15) 07
(June’17) [LJIET]
32 Prove that NAND gate as Universal gate (June’17 OLD)[LJIET] 04
33 Simplify Boolean function using K-Map F(W,X,Y,Z)=Σ(1,3,5,8,9,11,15) , d= Σ(2,13) (June’17 04
OLD)[LJIET]
34 Minimize the following function using K-map and implement the same. 07
F (w,x,y,z) = Σm (0,1,2,3,6,7,13,14) + Σd (8,9,10,12)(Jan’17 OLD) [LJIET]
DF (3130704) 2021 Page 14
35 Minimize the following function using K-map and implement the same. 07
F = A’B’C’ +B’CD’ + A’BCD’ + AB’C’(Jan’17 OLD) [LJIET]
36 Use Tabulation Method and Solve Σm (0,2,6,8) + d(12,13,14,15) (May’17 OLD) [LJIET] 07
37 Use Kmap and Solve Σm (0,2,6,8) + d(12,13,14,15). Write answer in SoP and PoS form 07
38 Express the Boolean function F = AB + A’C in a product of maxterm. (Nov’17 OLD)[LJIET] 03
39 Reduce the expression in SOP and POS form using K-map. F(A,B,C,D) = Σm (1,5,6,12,13,14) 07
+ d(2,4) (Nov’17 OLD)[LJIET]
40 Simplify the following Boolean function by means of the Tabulation Method. 07
F(A,B,C,D) = Σ(1,2,3,5,6,7,8,9,12,13,15) (Nov’17 OLD)[LJIET]
41 Using K-map find the Boolean function and its complement for the following: F(A,B,C,D) = 07
∑(1,2,3,4,6,8,9,10,11,12,14) (May’18 OLD) [LJIET]
42 Solve the following Boolean functions by using K-Map. Implement the simplified function by 04
using logic gates F = (w,x,y,z) = Σ (0,1,4,5,6,8,9,10,12,13,14) (Dec’18 OLD)[LJIET]
43 Implement the following function with NAND and NOR Gate. F(a,b,c) = Σ (0,6) (Dec’18 07
OLD) [LJIET]
44 Simply Boolean function for F(W,X,Y,Z) = Σ (0,1,2,4,5,6,8,9,12,13,14) (Jun’19 07
OLD)[LJIET]
45 Simplify the following Boolean function using k-map (i) F (w, x, y, z) = Σ m (0, 1, 2, 4, 5, 6, 07
8, 9, 12, 13, 14) (ii) F (x, y, z) = Σ m (0, 1, 3, 4, 5, 7) (Nov’18 OLD) [LJIET]
46 Simplify following Boolean function by using the tabulation method 07
F (w, x, y, z) = Σ m (0, 1, 2, 8, 10, 11, 14, 15) (Nov’18 OLD) [LJIET]
47 Obtain the simplified expressions in SOP for the following Boolean function using K-Map 07
method. And implement it using NAND gate.
F(A,B,C,D) = ABC+AB’C+BCD’+A’CD (Nov’19 OLD) [LJIET]
48 Simplify the following Boolean function by means of the tabulation method and implement it 07
using NAND gate. F(A,B,C,D) = Σ(0,1,4,7,13,14) +d(5,8,15) (Nov’19 OLD) [LJIET]
49 What is the significance of a Karnaugh map for solving combinational circuits? 07
Solve f(a,b,c,d) = (5,7,12,13,14,15) using a K map (Jun’19 OLD) [LJIET]
50 Express the Boolean function F = A + B’C in a sum of minterms.(Dec’19 NEW) [LJIET] 03
51 Reduce the expression F = A [ B + C’ (AB + AC’)’](Dec’19 NEW) [LJIET] 04
52 Simplify the following Boolean function by using the tabulation method. F (A, B, C, D) = Σ m 07
(0, 1, 2, 8, 10, 11, 14, 15) (Dec’19 NEW) [LJIET]
53 Using D & E as the MEV, Reduce F = A’B’C’ + A’B’CD + A’BCE’ + A’BC’E + AB’C + 07
ABC + ABC’D’ (Dec’19 NEW) [LJIET]
54 Simplify the Boolean function F (w, x, y, z) = Σ m (0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14) (Dec’19 03
NEW) [LJIET]
55 Simplify the Boolean function F = A’B’C’ + B’CD’ + A’BCD’ + AB’C’(Dec’19 NEW) 03
[LJIET]
56 Minimize the following Boolean expression using Karnaugh Map (K-MAP) and Draw the 04
draw the simplified logic circuit diagram.Y= ∑m(0,1,5,9,13,14,15) + d(3,4,7,10,11) (Dec’19
OLD) [LJIET]
57 Given a logic function: Z = ABC + BC’D + A’BC. 07
(i) Make a truth table.
(ii) Simplify using K-map.
(iii) Realize simplified function using NAND gates only. (Mar’21 NEW) [LJIET]
58 Minimize following Boolean function using K-map: Y(A,B,C,D) = Σ m(0, 1, 2, 3, 5, 7, 8, 9, 04
11, 14) (Mar’21 NEW) [LJIET]
DF (3130704) 2021 Page 15

59 Minimize following Boolean function using K-map: F(A,B,C,D) = Σ m(1, 3, 7, 11, 15) + d(0, 04
2, 5) (Mar’21 NEW) [LJIET]
60 Minimize following Boolean function using K-map: X(A,B,C,D) = Σ m(0, 1, 2, 3, 5, 7, 8, 9, 03
11, 15)(Nov’20 NEW) [LJIET]
61 1. Convert Y = AB + AC’ + BC into canonical SOP form. 04
2. Convert Z = (A+B)(A+C)(B+C’) into canonical POS form. (Nov’20 NEW) [LJIET]
62 Minimize the following logic function using K-map: F(A,B,C,D) = Σ m(1, 3, 5, 8, 9, 11, 15) + 03
d(2,13) (Nov’20 NEW) [LJIET]
Topic: 3 Combinational Digital Circuits

1.Fill in the Blanks: [LJIET] Marks
1) 8-bit parallel data can be converted into serial data by using ________ multiplexer Each
[LJIET] Answer : (8-to-1)
2) For a 3-to-8 decoder ________2-to-4 decoders will be required.[LJIET] Answer :(2)
3) The commercially available 8-input multiplexer integrated circuit in the TTL family is
___________. [LJIET] Answer :(MUX integrated circuit in TTL is 74153)
4) The device which changes from serial data to parallel data is _______.[LJIET] Answer
:(DEMULTIPLEXER.)
5) A device which converts BCD to Seven Segment is called [LJIET] Answer :(Decoder)
6) 16 to 1 multiplexer will have ________________ select lines.[LJIET] Answer : (4)
7) The number of control lines for a 8 – to – 1 multiplexer is ________[LJIET] Answer :(3)
1) BCD to 7-Segment decoder has 3 inputs and 7 outputs. [LJIET]
Answer :(False 7 inputs and 4 outputs)
3. Answer the following: [LJIET]
1) Define Decoder?[LJIET]
A decoder is a multiple - input multiple output logic circuit that converts coded
inputsinto coded outputs where the input and output codes are different.
2) What is binary decoder?[LJIET]
A decoder is a combinational circuit that converts binary information from n input lines
to a maximum of 2n outputs lines.
3) Define Encoder?[LJIET]
An encoder has 2n input lines and n output lines. In encoder the output lines generate the
binary code corresponding to the input value.
4) What is priority Encoder?[LJIET]
A priority encoder is an encoder circuit that includes the priority function. In priority
encoder, if 2 or more inputs are equal to 1 at the same time, the input having the highest
priority will take precedence.
5) Define multiplexer?[LJIET]
Multiplexer is a digital switch. If allows digital information from several sources to be
routed onto a single output line.
6) What is Demultiplexer?[LJIET]
A Demultiplexer is a circuit that receives information on a single line and transmits this
information on one of 2n possible output lines
7) What is code conversion?[LJIET]
DF (3130704) 2021 Page 16
If two systems working with different binary codes are to be synchronized inoperation,
then we need digital circuit which converts one system of codes to the other.The process
of conversion is referred to as code conversion.
8) Give the applications of Demultiplexer.[LJIET]
a. It finds its application in Data transmission system with error detection.
b. One simple application is binary to Decimal decoder
9) Application of Mux.[LJIET]
a. They are used as a data selector to select one output of many data inputs.
b. They can be used to implement combinational logic circuits
c. They are used in time multiplexing systems.
d. They are used in frequency multiplexing systems.
e. They are used in A/D & D/A Converter.
f. They are used in data acquisition system.
10) List out the applications of comparators?[LJIET]
a. Comparators are used as a part of the address decoding circuitry in computers to
select a specific input/output device for the storage of data.
b. They are used to actuate circuitry to drive the physical variable towards the
reference value.
c. They are used in control applications.
2 How many enable lines are there in 3X8 decoder IC 74138? (Dec’15 OLD)[LJIET] Answer : 01
3
3 How many selection lines are required in 32X1 MUX? (Dec’15 OLD)[LJIET] Answer : 5 01
4 How many inputs are required for a 1-of-16 decoder? (Jan’17 OLD)[LJIET] Answer : (b) 01
(a) 2 (b) 4 (c) 8 (d) 12
5 Define: [1] Comparator [2] Encoder [3] Decoder [4] Multiplexer [5] De-multiplexer 01
(March’10 OLD) [LJIET]

1 Explain the working of multiplexer.(May’16 OLD)[LJIET] 03
2 Give the applications of Decoder. (May’16 OLD)[LJIET] 03
3 Draw & explain in brief pin diagram of 7485 four-bit magnitude comparator. (Dec’15 OLD) 03
[LJIET]
4 Explain common cathode types seven segments displays.(May’12 OLD) [LJIET] 03
5 Implement the given function using multiplexer F (A, B, C) = ∑m (1,2,4,7) (May’16 04
OLD)[LJIET]
6 Design 4-to-16 Decoder from two 3-to-8 Decoders. (May’16 OLD)[LJIET] 04
7 Draw the logic diagram of 3 to 8 line decoder. Explain its operation with truth table. 07
8 Design a circuit for 2-bit magnitude comparator.(May’15 OLD)[LJIET] 07
9 Design 3-bit even parity generator circuit.(May’15 OLD)[LJIET] 07
10 Implement following logic function using 8X1 MUX. F = Σ m(0,1,3,5,7,11,13,14,15)(Dec’15 07
OLD) [LJIET]
11 1. Design 4 X 16 decoder using two 3 X 8 decoder.(May’15, Jan’13 OLD) [LJIET] 07
2. Design a 4-to-16 decoder by using only 2-4 decoder circuits.(May’14 OLD) [LJIET] 07
3. Construct 4 X 16 decoder with two 3 X 8 decoders.(Jan’13 OLD) [LJIET] 07
4. Construct 4*16 Decoder with help of 2*4 Decoder.(May’12 OLD) [LJIET] 05
12 Implement combinational logic using 8:1line MUX for F( A,B,C,D) = Σm( 0,2,4,5,7,9,12,15) 07
DF (3130704) 2021 Page 17
13 1. Design a BCD adder.(June’15 OLD) [LJIET] 07

2. Discuss 4 bit BCD adder in detail.(May’12 OLD) [LJIET] 05
14 1.Explain 3 to 8 line decoder.(Jan’17 OLD,June’15 OLD,Nov’17 OLD)[LJIET] 03
2. With logic circuit and truth table explain working of 3 to 8 line decoder. 07
3. What is meant by decoder? Explain 3-to-8 line decoder with diagram and truth table 07
4. With logic circuit and truth table explain working of 3 to 8 line decoder. (Dec’10 OLD) 07
[LJIET]
5. Describe a block diagram for decoder circuit. Implement 3 to 8 Decoder Circuit (May’17 07
OLD) [LJIET]
6. With logical diagram and functional table explain the operation of 3 to 8 line decoder. 07
7.Draw logic diagram of 3-line to 8-line decoder (May’18 OLD)[LJIET] 04
8. Design and explain a logic diagram of 3 to 8 Decoder (Nov’18 OLD) [LJIET] 07
15 Design a 8 to 1 multiplexer by using the four variable function given by 07
F(A,B,C,D) = ∑m(0,1,3,4,8,9,15) (Dec’14 OLD)[LJIET]
16 1.Implement F (A, B, C, D) = Σ m (0, 1, 3, 4, 8, 9, 15) using multiplexer, choose A as input 07
line.(Dec’14 OLD) [LJIET]
2. What is multiplexer? Implement the following function with a multiplexer
F(A,B,C,D) = ∑(0, 1, 3, 4, 8, 9, 15)(May’11 OLD) [LJIET]
17 Design a combinational circuit that accepts the decimal number in BCD and display it on seven 07
segment display.(Dec’14 OLD) [LJIET]
18 1. Write a brief note on parity checker/generator.(May’14 OLD) [LJIET] 05
2. Design and explain Odd parity generator (Jan’17 OLD) [LJIET] 07
3. Design and implement 3 bit odd parity generator circuit. (Nov’17 OLD) [LJIET] 07
19 What is encoder? With logic circuit and truth table explain the working of Octal to binary 07
Encoder.(Nov’13 OLD) [LJIET]
20 1. What is Multiplexer? With logic circuit and function table explain the working of 4 to 1 03
multiplexer.(June’17 OLD)[LJIET]
2. What is Multiplexer? With logic circuit and function table explain the working of 4 to 1 04
multiplexer. (Nov’17 OLD)[LJIET]
2. What is meant by multiplexer? Explain with diagram and truth table the Operation of 4-to-1 07
line multiplexer( Nov’13 OLD, Dec’11 OLD) [LJIET]
21 1. Explain a 4 to 1 line multiplexer in detail.(May’13 OLD) [LJIET] 07
2. With logic diagram and function table explain the operation of 4 to 1 line multiplexer. (Dec’10 07
OLD,Nov’17 OLD) [LJIET]
3. Design and explain 4x1 Multiplexer (Jan’17 OLD) [LJIET] 07
4. Draw logic circuit of 4:1 MUX (May’18 OLD)[LJIET] 03
5. Design and explain 4 X 1 Multiplexer (Nov’18 OLD) [LJIET] 07
22 1. With logic circuit explain the working of 4-bit magnitude comparator. (Nov’13 OLD) 07
[LJIET]
2. Explain 4 bit Magnitude Comparator.(May’12 OLD) [LJIET]
3. Design 4-bit magnitude comparator in detail.(Dec’9 OLD) [LJIET]
23 Design a BCD to decimal decoder (May’11 OLD) [LJIET] 07
24 Design a full adder circuit using decoder and multiplexer(March’10 OLD) [LJIET] 07
25 Design a full adder using 3X8 decoder followed by gates. (Dec’15 OLD)[LJIET] 07
26 Design a combinational circuit whose input is a four bit number & whose output is the 2’s 07
complement of the input number (Dec’15 OLD) [LJIET]
27 1. Draw & explain the operation of 4 bit binary parallel adder (Dec’15 OLD) [LJIET] 07
2. Explain 4 – bit parallel adder.(Dec’19 NEW) [LJIET] 04
DF (3130704) 2021 Page 18
28 Design 3-bit parity generator circuit using even parity bit (Jan’17 OLD)[LJIET] 07
29 Explain full adder and design a full adder circuit using 3 to 8 decoder and two OR gates 07
(Jan’17 OLD) [LJIET]
30 Design one bit magnitude comparator (Jan’17 OLD)[LJIET] 03
31 Implement the given function using multiplexer. F (A, B, C) = Ʃ (1, 3, 5, 6) (Jan’17 04
OLD)[LJIET]
32 Design BCD to Excess-3 code convertor circuit (Jan’17 OLD)[LJIET] 07
33 Explain Half Adder circuit with neat diagram (Jan’17 OLD)[LJIET] 04
34 Explain Full Subtractor with truth table and circuit diagram (June’17 OLD)[LJIET] 07
35 Explain magnitude comparator (June’17, Nov’17)[LJIET] 03
36 Design a combinational circuit with four input lines that represent decimal digit in BCD and 07
four output lines that generates 9’s Complement of the input digit. (June’17 OLD)[LJIET]
37 Implement following Boolean function using 8 : 1 multiplexer F = ∑(2,3,5,7,8,9,12,13,14,15) 07
(June’17 OLD)[LJIET]
38 Implement Full Subtractor Circuit with the help of Decoder and logic gates (June’17 07
OLD)[LJIET]
39 Design the Combinational Circuits for Binary to Gray Code Conversion. (May’12 OLD) 05
[LJIET]
40 1.Draw the truth table of full adder and implement using minimum number of logic 07
gates.(May’15, Nov’17)[LJIET]
2. Design a combinational circuits for a full adder.(May’12 OLD) [LJIET] 04
3. Design a full-adder using two half-adder and an OR gate(May’11 OLD) [LJIET] 07
4. With necessary sketch explain full adder in detail.(Dec’9 OLD) [LJIET] 07
5. Design a full adder circuit using two half adders and gates (May’17 OLD) [LJIET] 07
6. Design a 3 bit full adder circuit and implement it using a half adder circuit. (Nov’17 OLD) 07
[LJIET]
41 Draw the truth table of full subtractor and implement using minimum number of logic 07
gates.(May’15 OLD)[LJIET]
42 (i) Explain Full Adder in detail. (June’16 OLD) [LJIET] 07
(ii) Design and explain with truth table the logic circuit for full adder(Jan’17 OLD) [LJIET] 07
43 Write short note on half adder and full adder. (May’16 OLD)[LJIET] 07
44 Design half adders and explain various implementations.(June’15 OLD) [LJIET] 07
45 Explain design and functioning of half and full subtractors.(June’15 OLD) [LJIET] 07
46 Design converter to convert decimal 8,4,-2,-1 code to BCD.(June’15 OLD) [LJIET] 07
47 Design converter to convert decimal 2,4,2,1 code to 8,4,-2,-1 code.(June’15 OLD) [LJIET] 07
48 1. Design BCD to excess – 3 code converter.(June’15 OLD) [LJIET] 07
2. Design a BCD to Excess-3 code converter using minimum number of NAND gates 07
3. Design and implement BCD to excess 3 code converter.(May’13 OLD) [LJIET] 07
4. Design BCD to Excess-3 code converter using minimum number of NAND gates 08
5. Derive and draw logic circuit for BCD to Excess-3 Code converter(Jun’19 OLD)[LJIET] 07
49 Explain excess -3 code &gray code (Dec’15 OLD,Nov’17 OLD)[LJIET] 07
50 Prepare BCD to excess 3 code converter. (June’16 OLD) [LJIET] 07
51 A combinational circuit has 3 inputs A, B, C and output F. F is true for following input 07
combinations(Dec’14 OLD)[LJIET]
A is False, B is True
A is False, C is True
A, B, C are False
A, B, C are True
(i) Write the Truth table for F. Use the convention True = 1 and False = 0.
DF (3130704) 2021 Page 19
(ii) Write the simplified expression for F in SOP form.

(iii) Write the simplified expression for F in POS form.
(iv) Draw the logic circuit using minimum number of 2-input NAND gates.
52 Design a combinational circuit that multiplies BCD inputs by 5. Show that output can be 07
obtained from the inputs without using any logic gates.(Dec’14 OLD) [LJIET]
53 With logic circuit describe the function of :(Nov’13 OLD) [LJIET] 07
(1) Full adder (2) Full subtractor Write the simplified Boolean functions with their outputs.
54 Explain half and full adder in detail.(May’13 OLD) [LJIET] 07
55 Show how a full-adder can be converted to a full-subtractor with the help of addition of one 07
inverter circuit.(Jan’13 OLD) [LJIET]
56 1. Design a combinational circuit with the four input lines that represent a decimal digit in BCD 07
and four output line that generate the 9’s complement of the input digit. (Jan’13 OLD) [LJIET]
2.Design a combinational circuit that generates the 9’s complement of BCD digit. (Dec’9
OLD)[LJIET] 07
57 Design 4 bit binary to BCD code converter(March’10 OLD) [LJIET] 07
58 Design a combinational circuit that accepts a three bit binary number and generates an output 07
binary number equal to the square of the input number.(Dec’9 OLD) [LJIET]
59 1. Design a combinational circuit whose input is a four bit number and whose Output is the 2’s 08
complement of the input number.(Dec’11 OLD,May’11 OLD) [LJIET]
2. Design a combinational circuit whose input is a four bit number and whose Output is the 2’s 07
complement of the input number.( May’11 OLD) [LJIET]
60 1. Design 4 bit binary to BCD code converter. (March’10 OLD) [LJIET] 07
2. Design a circuit for binary to gray code conversion. Give Example(May’17 OLD) [LJIET]
61 Draw & explain the operation of 4 bit binary parallel adder (Dec’15 OLD) [LJIET] 07
62 Design a 4 bit binary to gray code converter and implement using EX-OR gates only. (Nov’17 07
OLD) [LJIET]
63 Explain Design Procedure for Combinational Circuit & Difference between C 07
ombinational Circuit & Sequential Circuit. (May’18 OLD) [LJIET]
64 Construct 4*16 Decoder with help of 2*4 Decoder (May’18 OLD) [LJIET] 07
65 Explain arithmetic micro operations with the help of a block diagram(May’18 OLD) [LJIET] 07
66 Design 3-bit even parity generator circuit using X-OR gates only (May’18 OLD)[LJIET] 04
67 Realize the expression Y(A, B, C, D) = Ʃ m(15, 7, 4, 6, 8, 9, 12, 14) using an 8:1 MUX. 07
(May’18 OLD)[LJIET]
68 1.Design 1-bit magnitude comparator circuit. (May’18 OLD)[LJIET] 03
2.Design 1 - bit Magnitude Comparator.(Dec’19 NEW)[LJIET] 04
69 Using suitable decoder & OR gates, design 4-bit binary to Gray code converter. (May’18 07
OLD)[LJIET]
70 With a neat block diagram explain the function of encoder. Explain priority encoder (Dec’18 07
OLD)[LJIET]
71 Implement the following Boolean functions with a multiplexer and Decoder. F(w, x, y, z) = Σ 07
(2, 3, 5, 6, 11, 14, 15) (Dec’18 OLD)[LJIET]
72 Design a combinational logic circuit whose output is high only when majority of inputs (A, B, 07
C, D) are low (Dec’18 OLD)[LJIET]
73 Design a 3-bit gray to binary code converter. Implement it using suitable PROM. Draw the 07
necessary diagrams and tables. (Dec’18 OLD)[LJIET]
74 Draw logic circuit of Full Adder and Full Subtractor with truth table (Jun’19 OLD)[LJIET] 07
75 Draw logic circuit of 2x4 Decoder (Jun’19 OLD)[LJIET] 04
76 Explain working of Half Adder circuit with diagram (Jun’19 OLD)[LJIET] 03
77 Draw logic circuit for 2-Bit Magnitude Comparator (Jun’19 OLD)[LJIET] 04
78 Design 1-Bit Full Adder using 3x8 Decoder (Jun’19 OLD)[LJIET] 07
79 How to generate 8x1 MUX using 4x1 MUX (Jun’19 OLD)[LJIET] 03
DF (3130704) 2021 Page 20
80 Design a 1:16 demultiplexer using 1:8 demultiplexer. (Nov’19 OLD) [LJIET] 07

81 Draw a truth table and logic circuit to realize the following Boolean function using multiplexer. 07
F(A,B,C,D)= Σ ( 0, 1, 3, 6, 8, 10, 12, 15) (Nov’19 OLD) [LJIET]
82 Design 4-bit BCD adder using two 4-bit binary parallel adders. (Nov’19 OLD) [LJIET] 07
83 1.Design a full adder circuit using two half adders & gates (Nov’18 OLD) [LJIET] 07
2. Construct a Full Adder from a Half Adder (Jun’19 OLD) [LJIET] 07
84 Realize the expression F (A, B, C, D) = Σ m (4, 6, 7, 8, 9, 12, 14, 15) using an 8:1 MUX 07
85 Implement Full Subtractor circuit with the help of Decoder & logic gates. (Nov’18 OLD) 07
[LJIET]
86 1. Design a circuit for Binary to Gray code conversion (Nov’18 OLD) [LJIET] 07
2. Implement a binary to Gray converter. State its significance. (Jun’19 OLD) [LJIET] 07
87 How does an encoder circuit work? Explain in terms of symbol, block diagram and truth table 07
(Jun’19 OLD) [LJIET]
88 Design a full adder and realize full adder using 3X8 Decoder and 2 OR gates.(Dec’19 NEW) 07
[LJIET]
89 Implement the following function using 8X1 MUX F (A, B, C, D) = Σ m (0, 1, 3, 4, 8, 9, 15) 07
(Dec’19 NEW) [LJIET]
90 Explain full subtractor and construct full subtractor using half subtractors. (Dec’19 OLD) 07
[LJIET]
91 Implement 16 X 1 multiplexer using 2 X 1 multiplexer (Dec’19 OLD) [LJIET] 04
92 With a neat block diagram explain the function of encoder. Explain priority encoder? (Dec’19 07
OLD) [LJIET]
93 Design a combinational logic circuit such that output is high, when four bit binary number is 07
greater than (0110)2. (Dec’19 OLD)[LJIET]
94 Design 3-bit Binary to Gray code Converter. (Dec’19 OLD)[LJIET] 03
95 Explain in detail binary adder with Boolean function, k-map and truth table. (Mar’21 OLD) 07
[LJIET]
96 Construct a 4×16 decoder constructed by using two 3×8 decoders (Mar’21 OLD) [LJIET] 04
97 Design a 4 bit binary to BCD code converter. (Mar’21 OLD) [LJIET] 07
98 Draw the logic diagram of 1-digit BCD adder (Mar’21 NEW)[LJIET] 03
99 Draw truth table of 2-bit digital comparator (Mar’21 NEW)[LJIET] 03
100 Write a brief note on full subtractor with the help of its TT. Also design full subtractor logic 07
circuit using 3 x 8 decoder and OR gates. Use X, Y, & Z as input variables and D & B as
output variables. (Nov’20 NEW)[LJIET]
101 Write a brief note on BCD-to-7-segment decoder/driver. Set up a single 7-segement LED 07
display using 7447 BCD-to-7-segment decoder/driver.(Nov’20 NEW)[LJIET]
102 Draw & explain the block diagram of ALU .(Nov’20 NEW)[LJIET] 04
UNIT NO- 3 :
Sequential Circuits and Systems
TOPIC:1 : Flipflops
No
1. Fill in the Blanks: [LJIET] Marks
1) A latch has _____ stable states[LJIET] Answer :(Two) Each
DF (3130704) 2021 Page 21
2) An SR latch can be implemented using ____ gate[LJIET] Answer :(NAND & NOR)
3) Generally, the Power dissipation of _______ devices remains constant throughout their
operation. [LJIET] Answer :(TTL)
4) __________ Flip-Flops are required for mod–16 counter.[LJIET] Answer :(4)
5) A ring counter consisting of five Flip-Flops will have ___[LJIET] Answer :(5 states)
6) ________ flip-flops are required to construct mod 30 counter.[LJIET]
Answer :(5- Mod - 30 counter +/- needs 5 Flip-Flop as 30 < 25)
7) For JK flipflop J = 0, K=1, the output after clock pulse will be ________.[LJIET]
Answer :(0 - J=0, K=1, these inputs will reset the flip-flop after the clock pulse. So
whatever be the previous output, the next state will be 0.)
8) _________flip flops are required to construct a decade counter.[LJIET] Answer :(4)
9) For JK flip flop with J=1, K=0, the output after clock pulse will be ______. [LJIET]
Answer :(1)
10) The output of SR flip flop when S=1, R=0 is ____________. [LJIET] Answer :(1)
2.Answer the following: [LJIET]
1) Define Flip flop.[LJIET]
The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1or
0 until directed by an input signal to change its state.
2) Define race around condition.[LJIET]
In JK flip-flop output is fed back to the input and change in the output results change in
the input. Due to this in the positive half of the clock pulse if both J and K are high then
output toggles continuously. This condition is called ‘race around condition’.
3) What is edge-triggered flip-flop?[LJIET]
The problem of race around condition can solved by edge triggering flip flop. Edge
triggering means the flip-flop changes state either at the positive edge or negative edge
of the clock pulse and it is sensitive to its inputs only at this transition of the clock.
4) What is a master-slave flip-flop?[LJIET]
A master-slave flip-flop consists of two flip-flops where one circuit serves as a master
and the other as a slave.
5) Define rise time.[LJIET]
The time required to change the voltage level from 10% to 90% known as risetime(tr).
6) Define fall time.[LJIET]
The time required to change the voltage level from 90% to 10% known as falltime(tf).
7) Define skew and clock skew.[LJIET]
The phase shift between the rectangular clock waveforms is referred to as skew and the
time delay between the two clock pulses is called clock skew.
8) Define sequential circuit?[LJIET]
In sequential circuits the output variables dependent not only on the present input
variables but they also depend up on the past output of these input variables.
9) What do you mean by present state?[LJIET]
The information stored in the memory elements at any given time defines the present
state of the sequential circuit.
10) What do you mean by next state?[LJIET]
Present state and external inputs determine outputs and next state of sequential circuit
11) Applications of Flip-Flop.[LJIET]
a. Used as a memory Element.
b. Used as a Delay Element.
c. Used as a basic building block in sequential circuits such as counters and registers.
DF (3130704) 2021 Page 22
d. Data Transfer.
e. Frequency Division & Counting.
12) Give some applications of clocked RS Flip-flop.[LJIET]
a. Clocked RS flip flops are used in Calculators & Computers.
b. It is widely used in modern electronic products
13) What are the problems involved in asynchronous circuits?[LJIET]
The asynchronous circuits have three problems namely, a. Cycles. b. Races. c. Hazards
2 What is difference between latch and flip-flop? (May’16 OLD)[LJIET] 01
Answer : Latch is level triggered , Flipflop is edge triggered
3 Which latch is also known as transparent latch? (Dec’15 OLD)[LJIET] Answer : D Latch 01
4 Which flip-flop is also known as ones-catching flip-flop? (Dec’15 OLD)[LJIET] 01
Answer : Master Slave Flipflop
5 What is the use of state diagram? (May’16 OLD)[LJIET] 01
Answer :To give graphical representation of state table
6 Define race around condition. (May’16 OLD)[LJIET] 01
7 What is a state equation? (May’16 OLD)[LJIET] Answer : It is the algebraic equation of 01
next state
8 Define the following terms: Flip Flop(Nov’13 OLD) [LJIET] 01
9 Define: sequential logic circuit(Nov’13 OLD) [LJIET] 01
10 Define: Flip-Flop(March’10 OLD) [LJIET] 01
11 What is the significance of the J and K terminals on the J-K flip-flop? 01
(a) There is no known significance in their designations.
(b) The J represents "jump," which is how the Q output reacts whenever the clock goes high
and the J input is also HIGH.
(c) The letters were chosen in honor of Jack Kilby, the inventory of the integrated circuit.
(d) All of the other letters of the alphabet are already in use. (Jan’17 OLD)[LJIET] Answer
: (c)
12 Define: state table, state equation, state diagram, input & output equations 04

1 Draw a frequency divider using JK FFs to divide input clock frequency by a factor of 8. (Dec’15 03
OLD)[LJIET]
2 Draw & explain in brief a high assertion input SR latch. (Dec’15 OLD)[LJIET] 03
3 Implement T flip flop using D flip flop. (May’16 OLD)[LJIET] 03
4 1. Draw logic diagram, graphic symbol, and Characteristic table for clocked D flip 03
flop(May’11 OLD,Nov’17)[LJIET]
2. Show the logic diagram of clocked D Flipflop(Dec’9 OLD) [LJIET] 02
5 Answer the following(May’11 OLD) [LJIET] 04
(i) Give comparison between combinational and Sequential circuits
(ii)What is race-around condition in JK flip-flop?
DF (3130704) 2021 Page 23

6 1.Fill in values for S & R to cause the Q values of the SR FF given in figure 4.(Dec’15 04
OLD)[LJIET]
2. Plot the output waveform for the inputs shown in figure 5, assuming the initial contents of
the FF is Q = 0. (Dec’15 OLD)[LJIET]
7 State & explain any four operating characteristics of a flip flop (Dec’15 OLD) [LJIET] 07
8 Convert D flip flop into SR flip flop.(May’15 OLD)[LJIET] 07
9 Discuss edge triggered flip flop in detail. (June’16 OLD) [LJIET] 07
10 1. With the help of function table and circuit diagram explain the working of clocked SR flip 07
flop.(May’15 OLD)[LJIET]
2. Convert J K Flip Flop to S R Flip flop.Show the logical diagram of clocked S R Flip flop 07
with AND and NOR gates.(Dec’14 OLD) [LJIET]
3.With neat sketch explain the operation of clocked RS flip-flop(Dec’9 OLD) [LJIET] 05
11 Draw the circuit diagrams and Truth table of all the Flip flops (SR, D, T and JK). (Dec’14 07
OLD)[LJIET]
12 Implement D flip flop using JK flip flop.(Dec’14 OLD)[LJIET] 07
13 1. Draw and explain Master – slave Flip flop.(Dec’14 OLD) [LJIET] 07
2. Write a note on Master-Slave Flip-Flop.(May’14 OLD) [LJIET] 07
3. With logic diagram explain the function of master-slave flip-flop.(Nov’13 OLD) [LJIET] 05
4. Explain Master Slave Flip Flop through J K Flip Flop.(May’12 OLD) [LJIET] 04
5. Explain the working of the Master Slave J K flip-flop (May’17 OLD) [LJIET] 07
Explain the working of the Master Slave J K flip-flop (Dec’11 OLD) [LJIET] 06
6. Explain working of master-slave JK flip-flop with necessary logic diagram, state equation
and state diagram(May’11 OLD,Nov’17 OLD)[LJIET] 07
7. Explain Master Slave JK flip-flop with truth table and circuit diagram (June’17
OLD)[LJIET] 03
8. Draw & explain Master-Slave J-K Flip Flop (Jan’17 OLD) [LJIET]
9. Explain in detail master slave J-K flip flop. (Nov’17 OLD) [LJIET] 07
10.Explain working of master-slave JK flip-flop with necessary logic diagram, state equation 07
and state diagram (Jun’19 OLD)[LJIET]
14 Write a brief note on edge-triggered SR and JK Flip-Flops.(May’14 OLD) [LJIET] 07
15 Design a sequential with JK flip-flops to satisfy the following state equations: 07
A(t+1) = A’B’CD+A’B’C+ACD+AC’D’ B(t+1) = A’C+CD’+A’BC’ C(t+1) = B D(t+1) =
D’ (Nov’13 OLD,May’12 OLD) [LJIET]
16 1. Explain D type positive edge triggered flip flop.(May’13 OLD) [LJIET] 07
2. Discuss D-type edge- triggered flip-flop in detail.(Dec’9 OLD) [LJIET]
17 1. Explain JK Flipflop. What is disadvantage of it and how it can be eliminated? (Jan’13 OLD) 07
[LJIET]
2. Explain JK flip flop with its characteristic table and excitation table. (June’17 OLD)[LJIET] 04
18 For the figures 1, 2, & 3, plot the output waveforms referenced to the clock signal assuming the 07
initial contents of all FFs is Q = 0. Assume all FFs are edge triggered. (Dec’15 OLD)[LJIET]
DF (3130704) 2021 Page 24

19 With logic diagram and truth table explain the working JK Flipflop. Also obtain its characteristic 07
equation. How JK flip-flop is refinement of RS flip-flop? (Dec’10 OLD) [LJIET]
20 Draw and explain working of following flip-flops.(March’10 OLD) [LJIET] 07
[1] Clocked RS [2] JK
21 Convert SR flip-flop into JK flip-flop(March’10 OLD) [LJIET] 07
22 Explain the procedure followed to analyse a clocked sequential circuit With suitable 10
example(Dec’11 OLD) [LJIET]
23 Explain Design Procedure for Combinational Circuit & Difference between Combinational 04
Circuit & Sequential Circuit.(May’12 OLD) [LJIET]
24 1. Distinguish between combinational and sequential logic circuits. Give the applications of flip- 07
flops. (May’16 OLD)[LJIET]
2. Distinguish between combinational and sequential logic circuits. (Nov’17 OLD)[LJIET] 03
3. Distinguish between combinational and Sequential logic circuits. (Dec’19 OLD)[LJIET] 03
25 Explain RS flip flop in detail. (Jan’17 OLD)[LJIET] 04
26 Explain edge triggering and level triggering (Jan’17 OLD)[LJIET] 03
27 What is race around condition in JK flip flop.(Jan’17 OLD)[LJIET] 03
28 Plot the out waveform referenced to the clock signal assuming the initial contents of the flip- 03
flops is q=0. Assume all flip-flops are edge triggered. (June’17 OLD)[LJIET]
29 1. Draw & explain T Flip Flop and D Flip Flop(Jan’17 OLD) [LJIET] 07
2. Explain the working of D Flipflop and T Flipflop using Truth Table (May’17 OLD) [LJIET]
30 What is a combinational circuit? Why it is required in digital circuits? Explain construction 07
and working of R-S flip flop in detail. (Nov’17 OLD) [LJIET]
31 Explain D type positive edge triggered flip flop (May’18 OLD) [LJIET] 07
32 Draw the truth tables for JK & T FF. Using these truth tables, derive & explain the excitation 07
tables of JK & T FF. (May’18 OLD)[LJIET]
33 Draw high assertion & low assertion input SR latches.(May’18 OLD)[LJIET] 03
34 Draw gated SR latch using NAND gates only. (May’18 OLD)[LJIET] 03
35 Draw the characteristics and excitation table of JK flip flop. Design Conversion circuit of JK 07
Flip flop to SR Flip flop (Nov’19 OLD)[LJIET]
36 Discuss Clocked R-S Flip-flop with Logic diagram, Symbol, Characteristic table and 04
Characteristic equation (Dec’18 OLD)[LJIET]
37 Draw the Characteristic tables of following Flip-flop. 1. R-S 2. J-K 3. T (Dec’18 OLD)[LJIET] 03
38 Draw the circuit diagrams and Truth table of all the Flip flops (SR, D). (Jun’19 OLD)[LJIET] 04
39 Draw logic diagram, graphical symbol and Characteristic table for clocked T flip-flop (Jun’19 03
OLD)[LJIET]
DF (3130704) 2021 Page 25
40 What is race around condition in JK flip flop? (Jun’19 OLD)[LJIET] 03

41 Draw & explain T Flip Flop & D Flip Flop (Nov’18 OLD) [LJIET] 07
42 Explain JK Flip Flop with its characteristic table (Nov’18 OLD) [LJIET] 07
43 Explain about any one Flip Flop circuit using its symbol, block diagram, truth table and 07
characteristics equation (Jun’19 OLD) [LJIET]
44 Explain SR flip-flop using characteristic table & characteristic equation(Dec’19 NEW) 03
[LJIET]
45 What is the race around condition in JK flip-flop?(Dec’19 NEW) [LJIET] 03
46 Design JK flip-flip using D flip-flip(Dec’19 NEW) [LJIET] 07
47 Explain T Flipflop with Excitation Table. Implement T flip flop using SR flip flop (Dec’19 07
OLD) [LJIET]
48 Write a brief note on Master-slave flip flop with logic symbols (Mar’21 OLD) [LJIET] 04
49 Explain the working of clocked J-K Flip Flop (Mar’21 OLD) [LJIET] 03
50 Draw the circuit diagrams and Truth table of all the Flip flops. (Mar’21 OLD) [LJIET] 07
51 Write a brief note on race around condition and its solution. Draw & explain the logic diagram 07
of master-slave JK flip-flop. (Mar’21 NEW) [LJIET]
52 Design D FF using SR FF. Write truth table of D FF (Mar’21 NEW) [LJIET] 03
53 Construct D FF using SR FF. Write truth table of D FF. (Nov’20 NEW) [LJIET] 03
54 Write a short note on the applications of the flip-flops. (Nov’20 NEW) [LJIET] 07
55 How SR FF can be converted into JK FF? Draw & explain in brief (Nov’20 NEW) [LJIET] 04
TOPIC:2 : Counters
1 Fill in the Blanks: [LJIET] A 4-bit synchronous counter uses flip-flops with propagation delay 01
times of 15 ns each. The maximum possible time required for change of state will be _______.
Answer :(15 ns ; In synchronous counter all flip-flops change state at the same time.)
2 Define the following terms: Counter (Nov’13 OLD) [LJIET] 01
3 How many flip flops are required to count the sequence from 0 to 63? (Jan’17 OLD)[LJIET] 01
Answer : 6

1 Design sequential counter as shown in the state diagram using JK flip-flops. 07
(March’10 OLD) [LJIET]
2 Design a 3-bit synchronous up counter using K-maps and positive edge-triggered JK FFs. 07
3 Design a sequential circuit using JK Flip-Flops and two states Q0 and Q1 such that, 09
1. It moves to the next state for input 0. (00 to 01, 01 to 10,…, 11 to 00)
2. It moves to the previous state for input 1. (reverse from the above mentioned steps)
4 Give the comparison between synchronous and asynchronous counters.(May’16 OLD, Nov’17 04
OLD) [LJIET]
DF (3130704) 2021 Page 26

5 1. Design 4-bit ripple counter using negative edge triggered JK flip flop. (May’15 OLD, Nov’17 07
OLD) [LJIET]
2. Write a note on Binary Ripple Counter.(May’14 OLD) [LJIET]
3. With logic diagram explain the operation of 4 bit binary ripple counter. How up counter can
be converted into down counter?(Nov’13 OLD) [LJIET]
4. Explain 4 bit binary ripple counter.(May’12 OLD) [LJIET]
5. Explain working of 4-bit binary ripple counter(Dec’11 OLD) [LJIET]
6. Give classification of counters and explain asynchronous 4-bit binary ripple counter
7. With logic diagram explain the operation of 4 bit binary ripple counter. Explain the count
Sequence. How up counter can be converted into down counter?(Dec’10 OLD) [LJIET]
8. Explain the working of 4 bit asynchronous counter(March’10 OLD) [LJIET]
9. Explain 4 bit ripple counter using timing diagrams (May’17 OLD) [LJIET]
6 Explain 3 bit binary counter with necessary diagrams. (June’16 OLD) [LJIET] 07
7 Design a mod-12 Synchronous up counter using D-flipflop.(Dec’14 OLD)[LJIET] 07
8 1. Design a synchronous BCD counter with JK Flipflop. (Dec’14 OLD,May’13 OLD,May’16 07
OLD)[LJIET]
2. Design BCD synchronous Counter (May’17 OLD) [LJIET]
9 Design and explain 4-bit Ripple UP/DOWN Counter using positive edge triggered Flip 07
flop.(Dec’14 OLD) [LJIET]
10 Design and implement a Modulo-6 Asynchronous counter using T Flip flop.(Dec’14 OLD) 07
[LJIET]
11 Design and Implement a Mod-10 asynchronous counter with T FF.(May’14 OLD) [LJIET] 07
12 1. Design a counter with the following binary sequence: 0, 1, 3, 7, 6, 4 and repeat. Use T flipflop. 07
(Jan’13 OLD) [LJIET]
2. Design a counter with following binary sequence: 0,1,3,7,6,4, and repeat. (Use T flip-flop)
13 1. Explain BCD Ripple counter and draw its logic diagram and timing diagram. (Jan’13 OLD) 07
[LJIET]
2. Draw the state diagram of BCD ripple counter, develop it’s logic diagram, and explain it’s
operation.(Dec’9 OLD) [LJIET]
3. Design BCD Ripple Counter (May’17 OLD) [LJIET]
14 Explain 4-bit up-down binary synchronous counter.(May’12 OLD) [LJIET] 07
15 1. Design counter with the following binary sequence: 0, 4,2,1,6 and repeat. Use JK flip-flops 07
2. Design a counter with following binary sequence: 0,4,2,1,6 and repeat (Use JK flip-flop)
16 Design Modulo-8 counter using T flip flop. (Jan’17 OLD)[LJIET] 07
17 Design 3-bit synchronous up counter using T flip flop. (Jan’17 OLD)[LJIET] 07
18 How does a counter works as frequency divider? Explain with suitable example. (Jan’17 04
OLD)[LJIET]
19 Design a counter to generate the repetitive sequence 0, 1, 2,4,3,6 (June’17 OLD)[LJIET] 07
20 Design and explain BCD Counter(Jan’17 OLD) [LJIET] 07
21 Design a synchronous Counter that goes 0,2,3,7,0,2,3,… (May’17 OLD) [LJIET] 07
22 Design a 4 bit binary up counter. (Nov’17 OLD) [LJIET] 07
23 Design and Implement a Mod-10 asynchronous counter with T FF. (May’18 OLD) [LJIET] 07
24 Write a note on Binary Ripple Counter (May’18 OLD) [LJIET] 07
25 Explain Johnson Counters. (May’18 OLD) [LJIET] 07
26 Design 3-bit ripple up-counter using negative edge triggered JK flip flops. Also draw the 04
waveforms. (May’18 OLD)[LJIET]
27 Design 3-bit binary synchronous counter using JK Flip Flop (Nov’19 OLD)[LJIET] 07
DF (3130704) 2021 Page 27
28 Draw the state diagram of BCD ripple counter, develop it’s logic diagram and explain the 07
operation of circuit. (Nov’19 OLD)[LJIET]
29 Design a counter to generate repetitive sequence 0, 3, 5, 7, 4 using D FFs. (May’18 07
OLD)[LJIET]
30 Design a counter for following binary sequence 0-1-3-4-6-0 (Dec’18 OLD)[LJIET] 07
31 What is “Lock out” condition in counter? How to avoid it (Dec’18 OLD)[LJIET] 03
32 Design a 3-bit binary counter (Dec’18 OLD)[LJIET] 07
33 Design synchronous counter for sequence: 0-1-3-4-5-7-0 using T flip-flop (Jun’19 07
OLD)[LJIET]
34 Write a note on Binary Ripple Counter (Nov’18 OLD) [LJIET] 07
35 Explain about a synchronous counter using 3 bits (Jun’19 OLD) [LJIET] 07
36 Design a counter with the following binary sequence: 0, 1, 3, 7, 6, 4 and repeat. Use T – flip- 07
flops.
37 Design 4-bit Ring counter using D flip-flip.(Dec’19 NEW) [LJIET] 04
38 Explain 3-bit synchronous Binary Up counter with timing diagram (Dec’19 OLD) [LJIET] 04
39 Differentiate the Asynchronous counter and Synchronous counter. Explain 3- bit up/down 07
Asynchronous counter in detail (Dec’19 OLD) [LJIET]
40 Design 4-bit ripple counter using negative edge triggered JK flip flop (Mar’21 OLD) [LJIET] 07
41 Explain 3 bit binary UP and DOWM counter using JK flip-flops (Mar’21 OLD) [LJIET] 07
42 Design a 4-bit synchronous down counter using T flip-flops (Mar’21 NEW) [LJIET] 07
43 Design a 4-bit ripple up counter using JK flip-flops. (Mar’21 NEW) [LJIET] 04
44 Design a 3-bit synchronous up counter using JK flip-flops. (Nov’20 NEW) [LJIET] 07
45 Construct a 3-bit ripple up counter with preset and clear facility using T FFs (Nov’20 NEW) 04
[LJIET]
TOPIC:3 : Registers
1 Do as Directed[LJIET] 01
1.Give True or False. Correct False statement with Justification:[LJIET] Marks
1) Data can be changed from special code to temporal code by using Counter.[LJIET] Each
Answer :(False - Shift registers)
2) A counter has a specified sequence of states, but a shift register does not.[LJIET]
Answer :(True)
3) A universal shift register has both serial and parallel input and output capacity. [LJIET]
Answer :(True)
2.Answer the following: [LJIET]
1) Define registers.[LJIET]
A register is a group of flip-flops; flip-flop can store one bit information. So ann-bit
register has a group of n flip-flops and is capable of storing any binary
information/number containing n-bits.
2) What are the two types of shift register counters?[LJIET]
There are 2 types of shift Register counters are:
i). Ring counter: A ring counter is a circular shift register with only one flip flop being
set, at any particular time, all others are cleared.
ii).Johnson counter: The Johnson counter is a K-bit switch-tail ring counter with 2k
decoding gates to provide outputs for 2k timing signals.
DF (3130704) 2021 Page 28

3) What is bi-directional shift register and unidirectional shift register?[LJIET]

A register capable of shifting both right and left is called bi-directional shift register. A
register capable of shifting only one direction is called unidirectional shift register.
2 Define the following terms: Register (Nov’13 OLD) [LJIET] 01
3 How many flip flops are required to build a shift register to store following numbers? 04
(i) Decimal 28 (ii)Binary 6 bits (iii) Octal 17 (iv) Hexadecimals A
Answer : (i) 5 (ii) 6 (iii) 6 (iv) 4 (May’12 OLD) [LJIET]

1 1. With neat sketch design 4-bit bidirectional shift register.(May’15 OLD)[LJIET] 07
2. Draw and Explain 4-bit bidirectional Shift Register. (Dec’19 OLD)[LJIET] 04
2 1. Write a short note on four bit Universal Shift Register.(Dec’14 OLD)[LJIET] 07
2. Explain in detail 4-bit bidirectional shit register with parallel load.
(Jan’13 OLD, Nov’17)[LJIET]
3.Draw and explain the block diagram of 4-bit bidirectional shit register with Parallel load.
4.With necessary sketch explain Bidirectional Shift Register with parallel load.
3 Design a circuit for 4-bits parallel register with load with D Flip-Flops. Load input decides 07
whether to load new input or to apply no change conditions.(May’14 OLD) [LJIET]
4 What is the difference between serial and parallel transfer? What type of registers are used in 07
each case.(May’13 OLD) [LJIET]
5 1. Explain Johnson Counters.(May’12 OLD) [LJIET] 07
2. Construct a Johnson counter with Ten timing signals.(Dec’9 OLD) [LJIET]
6 Define the different mode of operation of registers & explain any two in details. (May’12 OLD) 07
[LJIET]
7 What is the function of shift register? With the help of simple diagram explain its working. With 07
block diagram and timing diagram explain the serial transfer of information from register A to
register B.(Dec’10 OLD) [LJIET]
8 Explain 4 bit serial in serial out shift register (Jan’17 OLD)[LJIET] 07
9 1.Draw and explain Ring counter (June’17 OLD)[LJIET] 04
2. Draw and explain Ring counter (Jun’19 OLD)[LJIET] 04
10 With neat logic diagram, explain serial in parallel out shift register(Jan’17 OLD) [LJIET] 07
11 Classify Registers. Describe any one of them in details (May’17 OLD) [LJIET] 07
12 Discuss in detail shift registers. (Nov’17 OLD) [LJIET] 07
13 What is the difference between serial and parallel transfer? What types of registers are used in 07
each case? (May’18 OLD) [LJIET]
14 With neat logic diagram, explain Universal shift register. (Nov’19 OLD) [LJIET] 07
15 Draw and explain 4-bit serial-in serial-out shift register using D FF (May’18 OLD)[LJIET] 04
16 Explain Serial Transfer w.r.t Shift Register with suitable example (Dec’18 OLD)[LJIET] 04
17 Explain 4-Bit serial in serial out shift register (Jun’19 OLD)[LJIET] 04
18 Show the working of Shift Register using symbol, block diagram and truth table (Jun’19 07
OLD) [LJIET]
19 With neat sketch design 4-bit bidirectional shift register (Mar’21 OLD)[LJIET] 07
20 Explain the working of SISO shift register.(Dec’19 NEW)[LJIET] 04
21 Draw & explain in brief the logic diagram of 4-bit bidirectional shift register (Mar’21 04
NEW)[LJIET]
22 List out and explain any one application of the register (Mar’21 NEW)[LJIET] 03
23 Draw & explain in brief the logic diagram of 4-bit bidirectional shift register. (Nov’20 04
NEW)[LJIET]
DF (3130704) 2021 Page 29

24 List out various application of the shift register and explain any one. (Nov’20 NEW)[LJIET] 03
UNIT NO- 4 :
A/D and D/A Converters
No
1 Define: A/D Converter [LJIET] 01
2 Define: D/A Converter [LJIET] 01
1 Write a Short note on A/D Converter [LJIET] 07
2 Explain Classification of A/D Converter [LJIET] 04
3 Give specification for A/D Converters [LJIET] 03
4 Write a Short note on D/A Converter[LJIET] 05
5 Explain Classification of D/A Converter [LJIET] 04
6 Give specification for D/A Converters [LJIET] 03
7 Write a short note on D/A Converters ICs [LJIET] 05
8 Write a short note on Weighted Resistor converter [LJIET] 07
9 Explain R-2R ladder D/A Converter [LJIET] 07
10 Explain working of sample and Hold Circuit of A/D Converter [LJIET] 03
11 Write a short note on Quantization and encoding for A/D Converter [LJIET] 07
12 Write a short note on Parallel comparator A/D Converter [LJIET] 07
13 Write a short note on Successive approximation A/D [LJIET] 07
14 Write a short note on counting A/D Converter [LJIET] 07
15 Write a short note on dual slope A/D Converter [LJIET] 07
16 Explain A/D Converter using Voltage to frequency and voltage to time conversion [LJIET] 05
17 Write a short note on A/D Converters Ics [LJIET] 05
18 Explain the specification of D/A converter.(Dec’19 NEW)[LJIET] 03
19 Explain R-2R ladder type D/A converter.(Dec’19 NEW)[LJIET] 04
20 Explain Successive Approximation type A/D converter.(Dec’19 NEW)[LJIET] 07
21 List out various commonly used D/A converters. Draw & explain any one D/A converter. 07
(Mar’21 NEW) [LJIET]
22 List out various commonly used A/D converters. Draw & explain any one A/D converter. 07
(Mar’21 NEW)[LJIET]
23 Write a brief note on quantization and encoding.(Mar’21 NEW)[LJIET] 04
24 List out various characteristics of a D/A converter. Discuss any one (Mar’21 NEW)[LJIET] 03
25 Discuss any two characteristics of a D/A converter. (Nov’20 NEW)[LJIET] 04
26 Draw & explain weighted-resistor D/A converter with necessary equations (Nov’20 07
NEW)[LJIET]
27 Write a brief note on quantization and encoding. (Nov’20 NEW)[LJIET] 04
28 Draw & explain Flash A/D converter with necessary decoding table. Also mention pros & cons 07
of the same. (Nov’20 NEW)[LJIET]
UNIT NO- 5 :
Semiconductor Memories and Programmable Logic Devices
No
DF (3130704) 2021 Page 30

1 Do as Directed[LJIET] 01
2. Define FPGA.[LJIET] Mark
A field-programmable gate array ( FPGA) is an integrated circuit designed to be Each
configured by the customer or designer after manufacturing “field-programmable”. The
FPGA configuration is generally specified using a hardware description language(HDL).
FPGAs contain programmable logic components called “logic blocks”, and a hierarchy of
reconfigurable interconnects that allow the blocks to be “wired to gather “some what like a
one-chip programmable breadboard.
2. Fill in the Blanks: [LJIET]
(1) Program counter contains ________________. [LJIET] Answer The address of the
next instruction to be executed)
(2) Words having 8-bits are to be stored into computer memory. The number of lines
required for writing into memory is _______. [LJIET] Answer Because 8-bit words
required 8 bit data lines.)
(3) _______address bits are required to represent 4K memory.[LJIET] Answer 12 Bits)
(1) Accumulator is one type of Register [LJIET] Answer True)
(2) Data bus is Uni-directional[LJIET]Answer False – Bi-directional)
(3) Control bus Bi-directional [LJIET] Answer False – Uni-directional)
(4) RAM is fastest memory. [LJIET] Answer False – Cache)
(5) EPROM contents can be erased by exposing it to Infrared rays.[LJIET]
Answer False- Ultraviolet rays.)
(6) RAM is a volatile memory [LJIET] Answer True)
(7) The information in ROM is stored By the user any number of times.[LJIET]
Answer False- By the manufacturer during fabrication of the device.)
(8) The storage capacity of a register makes it an important type of memory.[LJIET]
Answer True)
4.Answer the following:[LJIET]
1) Define PLD.[LJIET]
Programmable Logic Devices consist of a large array of AND gates and OR gates that
can be programmed to achieve specific logic functions.
2) Define PLA[LJIET]
PLA is Programmable Logic Array (PLA). The PLA is a PLD that consists of a
programmable AND array and a programmable OR array.
3) Define PAL[LJIET]
PAL is Programmable Array Logic. PAL consists of a programmable AND array and a
fixed OR array with output logic.
4) Define hazards.[LJIET]
Hazards are unwanted switching transients that may appear at the output of a circuit
because different paths exhibit different propagation delays.
2 List the types of ROM. (May’16 OLD)[LJIET]Answer : PROM, EPROM, EEPROM 01
3 How many words a 16*8 memory can store? (May’16 OLD)[LJIET]Answer :8 01
4 Define the followings. EPROM (Dec’14 OLD)[LJIET] 01
5 Define: PLA(March’10 OLD) [LJIET] 01
6 Why ROMs are called nonvolatile memory? (Jan’17 OLD)[LJIET] 01
Answer : Because the contents of ROM cannot be erased
1 Write a short note on FPGA. (May’16 OLD)[LJIET] 03
DF (3130704) 2021 Page 31
2 Draw & explain in brief general architecture of Xilinx FPGA. (Dec’15 OLD)[LJIET] 03
3 Compare the Followings in every aspect. (i) TTL and CMOS (ii) RAM and ROM 07
4 1. Compare ROM, PLA and PAL.(May’15 OLD, Nov’17 OLD)[LJIET] 07
2. Make comparison: i. ROM vs PLA ii. PLA vs PAL (May’18 OLD)[LJIET] 04
3. Compare ROM, PLA and PAL (Dec’19 OLD)[LJIET] 07
5 1. Explain ROM and it’s types.(June’15 OLD) [LJIET] 07
2. Write short note on: Read Only Memory (ROM)(May’11 OLD,Jan’17 OLD)[LJIET]
3. Write short note on EEPROM, EPROM and PROM(March’10 OLD) [LJIET]
6 1. Explain PLA and it’s application.(June’15 OLD) [LJIET] 07
2. Write short note on Programmable Logic Arrays.(Dec’14 OLD)[LJIET] 07
3. Explain in brief: Programmable Logic Array(May’14 OLD)[LJIET] 07
4. Explain PLA in detail.(May’13 OLD) [LJIET] 07
5. Explain PLA with necessary diagrams.(Jan’13 OLD) [LJIET] 07
6. Write short note on Programmable Logic Arrays. (Jun’19 OLD, June’17 OLD)[LJIET] 04
7. Write short note on Programmable Logic Arrays (Dec’19 OLD)[LJIET] 07
7 Discuss PLA in detail. (June’16 OLD) [LJIET] 07
8 Implement following functions using ROM. (Dec’15 OLD)[LJIET] 07
F1 = Σ m(1, 3, 4, 6) F2 = Σ m(2, 4, 5, 7) F3 = Σ m(0, 1, 5, 7) F4 = Σ m(1, 2, 3, 4)
9 A combinational circuit is defined by functions. (May’11 OLD,Jan’17 OLD)[LJIET] 07
F1(A,B,C) = ∑(3, 5, 6, 7) F2(A,B,C) = ∑(0, 2, 4, 7)
Implement the circuit with PLA having three inputs, four product term and two outputs
10 1. Explain memory unit(March’10 OLD) [LJIET] 07
2. Write a note on Memory. (May’16 OLD)[LJIET]
11 1. Explain different types of random access memories. (June’16 OLD) [LJIET] 07
2. Explain different types of random access memories (May’18 OLD) [LJIET] 07
12 Write a detailed note on semiconductor memory and PLD (Nov’17 OLD) [LJIET] 07
13 Using 8x4 ROM, realize the expressions F1 = AB’C + ABC’ + A’BC, F2 = A’B’C + A’BC’ + 07
AB’C’, F3 = A’B’C’ + ABC. Show the contents of all locations. (May’18 OLD)[LJIET]
14 Write a short not on Memory Organization [LJIET] 04
15 Write a short not on classification Memories [LJIET] 04
16 Explain characteristic of Memories [LJIET] 04
17 Write a short not on Content addressable memory (CAM) [LJIET] 05
18 Write a short not on charge de coupled device memory (CCD) [LJIET] 04
19 Write a short not on Complex Programmable logic Devices (CPLDs) [LJIET] 07
20 List down the various types of ROMs and discuss and two of them. (Dec’18 OLD)[LJIET] 04
21 What is a PLA circuit? Explain in details about it (Jun’19 OLD) [LJIET] 07
22 Classify memories. Describe in details about any one type (Jun’19 OLD) [LJIET] 07
23 Explain classification of Memories.(Dec’19 NEW) [LJIET] 03
24 Explain the types of ROM.(Dec’19 NEW) [LJIET] 04
25 A combinational circuit is defined by the function 07
F1 (A, B, C,) = Σ m (4, 5, 7) F2 (A, B, C,) = Σ m (3, 5, 7)
Implement the circuit with a PLA having 3 inputs, 3 product term & 2 outputs.
26 Explain the working of ROM with suitable diagrams. (Mar’21 OLD)[LJIET] 04
27 Implement the following equation by using PLA. (Mar’21 OLD)[LJIET] 07
F1 = AB' +AC and F2 = AC + BC
28 Write a detailed note on various types of memories.(Mar’21 NEW) [LJIET] 07
29 Draw and explain in detail the block diagram of CPLD.(Mar’21 NEW) [LJIET] 07
DF (3130704) 2021 Page 32

30 Draw internal organization of a 16 x 4 memory chip. (Mar’21 NEW) [LJIET] 03

31 Obtain 2048 x 8 memory using 256 x 8 memory chips. (Mar’21 NEW) [LJIET] 04
32 Differentiate between RAM & ROM.(Nov’20 NEW) [LJIET] 03
33 Write a short note on ROM & its types. (Nov’20 NEW) [LJIET] 07
34 Compare SRAM with DRAM (Nov’20 NEW) [LJIET] 03
35 Draw and explain in brief block diagram of CPLD. Also compare CPLD with FPGA. (Nov’20 07
NEW) [LJIET]
DF (3130704) 2021 Page 33

Digital Fundamentals QB ODD 2021

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Digital Fundamentals QB ODD 2021

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L.J.

Institute of Engineering & Technology Semester: III (2021)

Subject Name: DF Subject Code: 3130704

DF (3130704) 2021 Page 1

7 Do as directed : (May’16 OLD)[LJIET] 03

ii. Find A+A'B =__________.

TOPIC:2 : Logic Circuits

8) The following waveform pattern is for a(n) _______[LJIET] Answer : (2-input OR

2 Give True or False. Correct False statement with Justification:[LJIET] 01

7 Bubbled OR is also called _______________.(Dec’15 OLD)[LJIET] Answer : NAND 01

DESCRIPTIVE QUESTIONS Marks

2. explain SSI, MSI, LSI and VLSI

DF (3130704) 2021 Page 6

DF (3130704) 2021 Page 7

Topic: 3 Logic Families

DESCRIPTIVE QUESTIONS Marks

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DESCRIPTIVE QUESTIONS Marks

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29 Obtain canonical Sum of Product form of following function: F=AB+ACD (Jun’19 03

TOPIC:2 : Mapping Methods

2. Give True or False. Correct False statement with Justification:[LJIET]

DF (3130704) 2021 Page 11

1) Parallel adders are Sequential logic circuit. [LJIET]

4 Define: combinational logic circuit(Nov’13 OLD) [LJIET] 01

DESCRIPTIVE QUESTIONS Marks

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(2) Convert into Product-of-Maxterms: A(A’+B)(C’)

DF (3130704) 2021 Page 15

Topic: 3 Combinational Digital Circuits

DESCRIPTIVE QUESTIONS Marks

13 1. Design a BCD adder.(June’15 OLD) [LJIET] 07

(ii) Write the simplified expression for F in SOP form.

80 Design a 1:16 demultiplexer using 1:8 demultiplexer. (Nov’19 OLD) [LJIET] 07

DESCRIPTIVE QUESTIONS Marks

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40 What is race around condition in JK flip flop? (Jun’19 OLD)[LJIET] 03

DESCRIPTIVE QUESTIONS Marks

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3) What is bi-directional shift register and unidirectional shift register?[LJIET]

DESCRIPTIVE QUESTIONS Marks

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30 Draw internal organization of a 16 x 4 memory chip. (Mar’21 NEW) [LJIET] 03

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