Computer System Overview: Operating Systems: Internals Principles

Operating
Systems:
Internals
and Design
Principles Chapter 1
Computer System Overview
Ninth Edition
By William Stallings
© 2017 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

CPU Main Memory
0
System 1
2
PC MAR Bus
Instruction
Instruction
Instruction
IR MBR
I/O AR
Data
Execution
unit Data
I/O BR Data
Data
I/O Module n-2

n-1
PC = Program counter
Buffers IR = Instruction register
MAR = Memory address register
MBR = Memory buffer register
I/O AR = Input/output address register
I/O BR = Input/output buffer register
Figure 1.1 Computer Components: Top-Level View

Fetch Stage Execute Stage
Fetch Next Execute

START HALT
Instruction Instruction
Figure 1.2 Basic Instruction Cycle

User Program Interrupt Handler
i
Interrupt
occurs here i+1
Figure 1.6 Transfer of Control via Interrupts

Fetch Stage Execute Stage Interrupt Stage
Interrupts
Disabled
Check for
Fetch next Execute interrupt;
START instruction instruction initiate interrupt
Interrupts
handler
Enabled
HALT
Figure 1.7 Instruction Cycle with Interrupts

Time
1 1
4 4
I/O operation; 2 I/O operation

processor waits concurrent with
processor executing;
then processor
waits
5
5
2
4
4
3 I/O operation
concurrent with
I/O operation; processor executing;
processor waits then processor
waits
5
5
3 (b) With interrupts
(a) Without interrupts
Figure 1.9 Program Timing: Long I/O Wait

T1 + T2
T2
Average access time

T1
0 1
Fraction of accesses involving only Level 1 (Hit ratio)
Figure 1.15 Performance of a Simple Two-Level Memory

Block Transfer
Word Transfer
CPU Cache Main Memory

Fast Slow
(a) Single cache
Level 1 Level 2 Level 3 Main

CPU
(L1) cache (L2) cache (L3) cache Memory
Fastest Fast
Less Slow
fast
(b) Three-level cache organization
Figure 1.16 Cache and Main Memory

©
© 2017
2017 Pearson
Pearson Education,
Education, Inc.,
Inc., Hoboken,
Hoboken, NJ.
NJ. All
All rights
rights reserved.
reserved.
Operating
Systems:
Internals
and Design
Principles Chapter 2
Operating System Overview
Ninth Edition

Application programs
Application
programming interface
Application Libraries/utilities Software
binary interface
Operating system
Instruction Set
Architecture
Execution hardware
Memory
System interconnect
translation Hardware
(bus)
I/O devices
Main
and
memory
networking
Figure 2.1 Computer Hardware and Software Structure

Computer System
I/O Devices
Memory
Operating I/O Controller Printers,
System keyboards,
Software digital camera,
I/O Controller etc.
Programs
and Data
I/O Controller
Processor Processor
Storage
OS
Programs
Data
Figure 2.2 The Operating System as Resource Manager

Process
◼ Fundamental to the structure of operating systems
A process can be defined as:
A program in execution
An instance of a running program

The entity that can be assigned to, and executed on, a processor
A unit of activity characterized by a single sequential thread of execution, a

current state, and an associated set of system resources

Memory Management
◼ The OS has five principal storage
management responsibilities:
Automatic
Support of Protection
Process allocation Long-term
modular and access
isolation and storage
programming control
management

Real
Memory Address
Processor Management
Virtual Unit
Address Main
Memory
Disk
Address
Secondary
Memory
Figure 2.10 Virtual Memory Addressing

Asynchronous Procedure Call Used to break into the execution of a specified thread and to
cause a procedure to be called in a specified processor mode.
Deferred Procedure Call Used to postpone interrupt processing to avoid delaying

hardware interrupts. Also used to implement timers and inter-
processor communication
Interrupt Used to connect an interrupt source to an interrupt service

routine by means of an entry in an Interrupt Dispatch Table
(IDT). Each processor has an IDT that is used to dispatch
interrupts that occur on that processor.
Process Represents the virtual address space and control information

necessary for the execution of a set of thread objects. A process
contains a pointer to an address map, a list of ready threads
containing thread objects, a list of threads belonging to the
process, the total accumulated time for all threads executing
within the process, and a base priority.
Thread Represents thread objects, including scheduling priority and

quantum, and which processors the thread may run on.
Profile Used to measure the distribution of run time within a block of

code. Both user and system code can be profiled.
Table 2.5 Windows Kernel Control Objects

Operating
Systems:
Internals
and Design Chapter 3
Principles Process Description and
Control
Ninth Edition

Identifier
State
Process Control Priority

Program counter
Block Memory pointers
Context data
▪Contains the process elements I/O status

information
▪It is possible to interrupt a running
Accounting
process and later resume execution as
information
if the interruption had not occurred
▪Created and managed by the

operating system
▪Key tool that allows support for

multiple processes
Figure 3.1 Simplified Process Control Block

Two-State Process Model
Dispatch
Enter Not Exit

Running Running
Pause
(a) State transition diagram

Pause
(a) State transition diagram
Queue
Enter Dispatch Exit
Processor
Pause
(b) Queuing diagram
Figure 3.5 Two-State Process Model

Five-State Process Model
Dispatch
Admit Release
New Ready Running Exit
Timeout
Event
Occurs Event
Wait
Blocked
Figure 3.6 Five-State Process Model

(a) With One Suspend State
New
Ad
t
Dispatch
mi
Admit Release
mi
Ad
New Ready Suspend Running Exit
t
Timeout
Activate Dispatch
Ready/ Release
it
Ready Running Exit
Occurs Occurs
a
e
Event Event
at
tW
Suspend
iv
Suspend Timeout
ct
t W ven
A
t
ai
Occurs
Event
Suspend
en
Suspend Blocked
Ev
Activate
Blocked/
Suspend (a)Blocked
With One Suspend State
Suspend
(b) With Two Suspend States

New
Figure 3.9 Process State Transition Diagram with Suspend States

Ad
t
mi
mi
Ad
Suspe
t
nd
(a) With One Suspend State
New
Ad
t
mi
mi
Ad
Suspe
t
nd
Activate Dispatch
Ready/ Release
Suspend Ready Running Exit
Suspend Timeout
t
ai
Occurs
Occurs
Event
Event
tW
en
Ev
Activate
Blocked/
Suspend
Blocked
Suspend
(b) With Two Suspend States
Figure 3.9 Process State Transition Diagram with Suspend States

◼ The process is not immediately ◼ The process may or may not be
available for execution waiting on an event
◼ The process was placed ◼ The process may not be

in a suspended state by removed from this state
an agent: either itself, a until the agent explicitly
parent process, or the orders the removal
OS, for the purpose of
preventing its execution

User Mode System Mode
◼ Less-privileged mode ◼ More-privileged mode

◼ User programs ◼ Also referred to as
typically execute in control mode or
this mode kernel mode
◼ Kernel of the
operating system

Table 3.8
Mechanisms for Interrupting the
Execution of a Process
Mechanism Cause Use
Interrupt External to the execution of the Reaction to an asynchronous

current instruction external event
Trap Associated with the execution of Handling of an error or an

the current instruction exception condition
Supervisor call Explicit request Call to an operating system

function

System Interrupts
Interrupt Trap
◼ Due to some sort of event ◼ An error or exception
that is external to and condition generated within
independent of the currently
the currently running process
running process
◼ Clock interrupt ◼ OS determines if the
◼ I/O interrupt
condition is fatal
◼ Memory fault ◼ Moved to the Exit state
◼ Time slice and a process switch

occurs
◼ The maximum amount of
time that a process can ◼ Action will depend on the
execute before being nature of the error the
interrupted design of the OS

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Operating

© 2017 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

I/O Module n-2

Figure 1.1 Computer Components: Top-Level View

Fetch Next Execute

Figure 1.2 Basic Instruction Cycle

© 2017 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Figure 1.6 Transfer of Control via Interrupts

Figure 1.7 Instruction Cycle with Interrupts

© 2017 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

I/O operation; 2 I/O operation

3 (b) With interrupts

(a) Without interrupts

Figure 1.9 Program Timing: Long I/O Wait

© 2017 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Average access time

Figure 1.15 Performance of a Simple Two-Level Memory

CPU Cache Main Memory

(a) Single cache

Level 1 Level 2 Level 3 Main

(b) Three-level cache organization

Figure 1.16 Cache and Main Memory

© 2017 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Figure 2.1 Computer Hardware and Software Structure

Figure 2.2 The Operating System as Resource Manager

A process can be defined as:

An instance of a running program

A unit of activity characterized by a single sequential thread of execution, a

© 2017 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

© 2017 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Figure 2.10 Virtual Memory Addressing

Deferred Procedure Call Used to postpone interrupt processing to avoid delaying

Interrupt Used to connect an interrupt source to an interrupt service

Process Represents the virtual address space and control information

Thread Represents thread objects, including scheduling priority and

Profile Used to measure the distribution of run time within a block of

Table 2.5 Windows Kernel Control Objects

© 2017 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

© 2017 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Process Control Priority

Block Memory pointers

▪Contains the process elements I/O status

▪Created and managed by the

▪Key tool that allows support for

Figure 3.1 Simplified Process Control Block

Enter Not Exit

(a) State transition diagram

© 2017 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

(a) State transition diagram

(b) Queuing diagram

Figure 3.5 Two-State Process Model

© 2017 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Figure 3.6 Five-State Process Model

(b) With Two Suspend States

Figure 3.9 Process State Transition Diagram with Suspend States

(b) With Two Suspend States

Figure 3.9 Process State Transition Diagram with Suspend States

© 2017 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

◼ The process was placed ◼ The process may not be

© 2017 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

◼ Less-privileged mode ◼ More-privileged mode

© 2017 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Mechanism Cause Use