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BUS
Common Bus System
I/O I
MRI
RRI
Instruction Set Completeness
input
D Q
clock ck
control
master
clock
The control signal is generated in the control unit
input
D Q
clock ck
Control
unit
control
H/W S/W
Differences between Hardwired and microprogrammed
CONTOL UNIT
INSTRUCTION CYCLE
PC address of 1st instruction
NoW: we will try to represent the previous register transfer
statements (i.e. T0 , T1, T2).
BUT
W should check if it is direct or indirect
INPR register
1 FGI 0
OUTR register
1 FGO 1
3 FGO 1
Input & Output Instruction
Controlling
Information to/and
Checking
from AC register
The flag bits
Input & Output Instruction
Program Interrupt
The computer keeps checking the flag bit, and when it finds it
set, it initiates an information transfer.
However, this is not an efficient way cause the information flow
Rate between the computer and I/O devices is different.
So we will use an
Interrupt facility
Interrupt
facility
However, when a flag is set, the computer will be interrupted and when
it is ready then it can respond to the interrupt.
IEN is an interrupt enable f/f
When (IEN = = 0)
Then
When (IEN = = 1)
Then
NOTE:
ION & IOF are instruction to set
(Pc can be interrupted) & reset the ION f/f
Interrupt Cycle
INT
Program Interrupt
Dev1
Dev3
Therefore,
Computer will not check
the flags every time
Dev4
Dev2
Modified Fetch Cycle
R
R
R
R T3: AR M[AR]
Instruction cycle
Interrupt
cycle
Derive the gate structure associated with the control inputs of AR ?