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UNIT-1:
8. How many capacitive components are present in transient analysis of NAND gate
a) 9
b) 7
c) 6
d) 5
10.How many transistors are required to implement y=(A(D+E)+BC)^ in NMOS only logic?
a) 4
b) 5
c) 6
d) 7
UNIT-4:
1. In dynamic logic when clock signal is high, PMOS turned OFF and single NMOS at PDN will
a) Turned OFF
b) Turned ON
c) Doesn’t change
d) Goes to breakdown region
UNIT-5: INTERCONNECTS
1. ________ should me monitored carefully which affects the performance of the gate;
Answer: Crosstalk
3. Each cell in the memory array is connected to one of the column lines, these column lines are
termed as:
a) Word lines
b) Digit lines
c) Dye lines
d) Selected lines
6. Minimum time allowed between two consecutive memory operations are called
a) Memory access time
b) Memory cycle time
c) Memory dynamic time
d) Memory static time