LOAD FLOW ANALYSIS PROGRAM FOR IEEE

6 BUS SYSTEM BY GAUSS SEIDEL

ALGORITHM
Submitted in partial fulfillment of the requirements

For the degree of

Bachelor of Technology
By

PRANAV KUMAR (U07EE559)

KARTHIK P S (U07EE578)
ANURAG TIWARI (U07EE577)
SRIVATSA B N (U07EE548)

Guided by:
Dr. RANJIT ROY

ELECTRICAL ENGINEERING
DEPARTMENT
S.V. NATIONAL INSTITUTE OF TECHNOLOGY
SURAT
DECEMBER 2010
 Approval Sheet

Project entitled “LOAD FLOW ANALYSIS PROGRAM FOR

IEEE 6 BUS SYSTEM BY GAUSS SEIDEL ALGORITHM” is
approved
Examiners

_______________________________
_

Supervisor

________________________________

Examiner: 1

_____________________________
___

Examiner: 2

_________________________

Examiner: 3

Date: ____________
Place: Surat
 ABSTRACT

Load flow study is the steady state solution of the power system
network. The power system is modeled by an electric network and
solved for steady state powers and voltages for various buses. Flexible
AC transmission systems (FACTS) devices are utilizing load flow
analysis for enhancing power system security and stability. Unified
Power Flow Controller (UPFC) is one of the most important FACTS
device utilized for providing uninterrupted power supply and power
system stability. To what extent the performance of UPFC can be
improved highly depends upon the location and parameter setting of
this device in the system. In this paper the concentration was given on
writing the load flow program for IEEE 6 bus system and the results
were shown.
 ACKNOWLEDGEMENT
It is my pleasure to take this opportunity to thank all those who helped
me directly or indirectly in completion of this Project.Not everything
that I have received can be acknowledged with a few words, not
everything that I acknowledge will relieve me from my indebtness.

I am grateful to Mrs. Varsha A. Shah, Head & Associate professor,

Electrical Engineering Department, SVNIT Surat for giving me the
opportunity of working on such a challenging topic and providing me
with all the necessary permissions .

I am heartily thankful to my project guide Dr. Ranjit Roy, Associate

Professor, Electrical Engineering Department, SVNIT Surat for
making this project a grand success for me. This would have been
impossible without his unwavering encouragement and trust in our
ideas. He was always available for discussion whenever I struggled
and always found a way to guide me out of any adverse situation. I
am indebted to him for the pristine and enlightening guidance given to
me throughout the process.

Finally I thank all the faculty members for providing me with all the
facilities on time and in good shape and have helped me with their
useful ideas at different points of time.

PRANAV KUMAR (U07EE559)

KARTHIK P S (U07EE578)

ANURAG TIWARI (U07EE577)

SRIVATSA B N (U07EE548)
 TABLE OF CONTENTS
LIST OF FIGURES

Figure 2.2.1 Variable structure control of second-order system

Figure 2.2.2 Phase Plane Portrait of Figure 2.1.1 with negative

feed back

Figure 2.2.3 Phase plain portrait with positive feedback.

Figure 2.2.4 Sliding Control in Phase plane

 CHAPTERS: page no

1. Introduction 1-2

1.1 Introduction
1.2 SLIDING MODE CONTROL BASIC CONCEPT

2. Sliding Mode Control 3-8

2.1 Control Principle

2.1 Derivation of Control Law

3. Advantages and Disadvantages of SMC 9-10

Conclusion 24

References 25

Acknowledgements 26
 1. INTRODUCTION

1.1 Introduction

The secure operation of power system has become an important and

critical issue in today’s large, complex, and load- increasing systems.
Security constraints such as thermal limits of transmission lines and
bus voltage limits must be satisfied under all system operation
conditions. One of the most important methods to improve the
security of power system is the flexible AC transmission systems
(FACTS) devices which is a concept proposed by Hingorani (1988)
[1].
To obtain the optimal location and parameter setting of UPFC
(Unified Power Flow Controller), first the understanding of load flow
analysis and its equations is must.
The main information obtained from the load flow study comprises of
magnitudes and phase angle of load bus voltages, reactive powers and
voltage phase angles at generator buses, real and reactive power flow
in transmission lines.
1.2 BASICS OF FLEXIBLE ALTERNATING CURRENT
TRANSMISSION SYSTEMS (FACTS)

FACTS Devices basically consist of a series and a shunt compensator.

Series compensation
In series compensation, the FACTS is connected in series with the
power system. It works as a controllable voltage source.
Series inductance occurs in long transmission lines, and when a large
current flow causes a large voltage drop. To compensate, series
capacitors are connected.

Shunt compensation
In shunt compensation, power system is connected in shunt (parallel)
with the FACTS. It works as a controllable current source. Shunt
compensation is of two types:
(i)Shunt capacitive compensation
This method is used to improve the power factor. Whenever an
inductive load is connected to the transmission line, power factor lags
because of lagging load current. To compensate, a shunt capacitor is
connected which draws current leading the source voltage. The net
result is improvement in power factor.
(ii)Shunt inductive compensation:This method is used either when
charging the transmission line, or, when there is very low load at the
receiving end. Due to very low, or no load – very low current flows
through the transmission line.
Shunt capacitance in the transmission line causes voltage
amplification (Ferranti Effect). The receiving end voltage may
become double the sending end voltage (generally in case of very
long transmission lines). To compensate, shunt inductors are
connected across the transmission line.

Examples of series compensation

 Static synchronous series compensator (SSSC)
 Thyristor-controlled series capacitor (TCSC):
A series capacitor bank is shunted by a thyristor-
controlled reactor.
 Thyristor-controlled series reactor (TCSR): a series reactor bank
is shunted by a thyristor-controlled reactor
 Thyristor-switched series capacitor (TSSC): a series capacitor
bank is shunted by a thyristor-switched reactor
 Thyristor-switched series reactor (TSSR): a series reactor bank
is shunted by a thyristor-switched reactor

Examples of shunt compensation

 Static synchronous compensator (STATCOM); previously

known as a static condenser (STATCON)
 Static VAR compensator (SVC). Most common SVCs are:
 Thyristor-controlled reactor (TCR): reactor is connected in
series with a bidirectional thyristor valve. The thyristor
valve is phase-controlled. Equivalent reactance is varied
continuously.
 Thyristor-switched reactor (TSR): Same as TCR but
thyristor is either in zero- or full- conduction. Equivalent
reactance is varied in stepwise manner.
 Thyristor-switched capacitor (TSC): capacitor is connected
in series with a bidirectional thyristor valve. Thyristor is
either in zero- or full- conduction. Equivalent reactance is
varied in stepwise manner.
 Mechanically-switched capacitor (MSC): capacitor is
switched by circuit-breaker. It aims at compensating
steady state reactive power. It is switched only a few times
a day.
2. PARAMETERS OF POWER FLOW SOLUTION

In solving a power flow problem, the system is assumed to be

operating under balanced conditions and a single phase model is used.
Four quantities are associated with each bus which are Voltage
magnitude |V|, Phase angle δ, Real power P and Reactive power Q.
The system buses are classified into three categories:
(i) Slack Bus: One bus known as slack or swing bus is taken as
reference where the magnitude and phase angle of the voltage are
specified.
(ii) Load Buses: At these buses, the active and reactive powers are
specified. The magnitude and phase angle of the bus voltage are
unknown. These buses are also known as P-Q buses.
(iii) Regulated Buses: These buses are the Generator buses or
Voltage Controlled Buses. At these buses, real power and voltage
magnitude are specified .Phase angle of the voltage and reactive
power are to be determined. These buses are also known as P-V
buses.

2.1 POWER FLOW SOLUTION BY GAUSS SEIDEL METHOD

A typical bus of power system network is shown in the given figure.
Transmission lines are represented by their equivalent π models
where impedances have been converted to per unit admittances on a
common MVA base.
Now,
Ii = y io*V(i) + y i 1*[V(i)-V(1)] + y i 2*[V(i)-V(2)]….
……+ y ¿*[V(i)-V(n)]
= [ y io+ y i 1+ y i 2+………+ y ¿]*V(i) - y i 1*V(1) – y i 2*V(2) - …….
- y ¿*V(n)…………………………………………………………
(2.1)

n n

Or Ii = V(i) ∑ yij – ∑ yij∗V j j≠i………………(2.2)

j=0 j=1

The real and reactive power at bus I is

Pi+ jQi=Vi I i¿

P i− jQ i
Or V i …………………...(2.3)
I i= ¿
 Substituting I in equation 2.2 yields
i

n n
P i− jQ i
=¿ V ∑ yij−∑ yij∗Vj ¿……………………(2.4)
V ¿i i j=0 j=1

From the above relation the mathematical formulation of the

power flow problem results in a system of algebraic nonlinear
equations which will be solved by iterative techniques.
In the power flow study, it is necessary to solve the set of
nonlinear equations represented by equation 2.4 for two
unknown variables at each node. In the Gauss Seidel method,
equation 2.4 is solved for V , and the iterative sequence
i

becomes

Pisch− j Qsch
V (k+1)
i =
[ V
i
¿( k)
i
]
+ ∑ y ij∗V (jk ) / ∑ y ij j≠i……(2.5)

Where y is the actual admittance in per unit,

ij Psch
i andQ are the
sch
i

net real and reactive powers expressed in per unit.In writing

the KCL, current entering bus I was assumed positive. Thus
for buses where real and reactive powers are injected into the
bus such as generator buses, P andQ have positive sch
i
sch
i

values.For load buses where real and reactive powers are

flowing away from the bus, P andQ have negative values and sch
i
sch
i

by solving equation 2.4

n n
P(k+1)
i =ℜ{V ¿i ( k ) [V ki ∑ y ij−∑ y ij∗V (jk )]} j ≠ i… …(2.6).
j=0 j=1

n n
Q (k+1)
i [ j=0 j=1
]
=−ℑ {V ¿i (k ) V ki ∑ y ij −∑ y ij∗V (jk ) j ≠i … …(2.7).

The power flow equation is usually expressed in terms of elements of

bus admittance matrix.

Therefore Y ij =− y ij

Y ii =∑ y ij

Substituting these values, equations 2.5, 2.6 and 2.7 will be modified

Pisch− j Qsch
V (k+1)
i =
[ V
i
¿( k)
i j ≠i ]
−∑ Y ij∗V (jk ) /¿Y ¿ ii
…………………(2.8)

P(k+1)
i =ℜ{V ¿i ( k ) ¿