EE19BTECH11014

Inverter
Mythri Varshitha

1)Large Signal Iout Vs vin of CMOS Inverter

SCHEMATIC
 SIMULATION

Since we do not have an ammeter, to find current,

(Voltage_output (Opamp)- Voltage_output (inverter))/R, I out is same as Current through R.

Self-Bias voltage of Inverter

We connect V_input and V_output of Opamp.

The self-biased voltage for Inverter at Vdd=6V is 2.5626299V
All current flows through the inverter and hence no output current, so from simulation result of I out vs Vin, the voltage at which current is zero is nothing but
self-Biased voltage.

The self-biased voltage through graph is almost same, some fluctuations may occur due to non-ideal nature of op-amp.

Transconductance at Vbias

Transconductance is d(Iout)/d(Vgs) at Vbias which is 0.00187ohm-1.

2) Large-signal Vout vs Vin of a CMOS inverter

SCHEMATIC

SIMULATION

Input is swept from 0 to 9V, Vdd takes 5V,6V,9V values.

Small-signal resistance of the self-biased inverter

SCHEMATIC

Small signal resistance = delta(V)/delta(I)

Initially when no additional bias is applied, the output current through inverter is 0.
After applying a small signal we find that current entering the inverter is same as through resistor.
Vbias gets altered due to the small signal alternating input.
Small signal resistance= (Vbias_final - Vbias_initial)/-(IR1)

SIMULATION
Green represents for Vdd=5V, Red represents for Vdd=6,9V they get close enough due to scaling.

For Vdd=5V

For Vdd=6V
For Vdd=9V

For large Vdd we find that we need to place lesser small signal resistance.
3) V_threshold of Inverter

V_threshold of NMOS is the point where the Vout starts drifting from 6V, Vtn=2.098V.
Vin<VTn NMOS->OFF PMOS->On

(Vdd +V_threshold of PMOS)is the point where the Vout starts approaching from 6V, Vtp= - 2.883V.
Vin>Vdd+VTp NMOS->ON PMOS->OFF

Transconductance(Gm) at Vbias for Vdd=6V

It is same from first experiment that is 0.00187ohm-1.
We find that Bn> Bp.It means that width of NMOS is greater than PMOS.
If both widths are equal, we find that saturation point occurs at V=3V.
Because of NMOS width is higher, hence V_threshold of NMOS decreases
thereby graph shifts left.