A B C D E

Page Index
===============
P01-Cover Page
P02-Block Diagram
P03-Notes List
P04-Dothan(1/2)
P05-Dothan(2/2)
1 1
P06-Alviso HOST(1/5)
P07-Alviso DDR(2/5)
P08-Alviso PCI-E(3/5)
P09-Alviso POWER(4/5)
P10-Alviso POWER(5/5)
P11-DDRI-SODIMM0
P12-DDRI-SODIMM1
P13-DDR Decoupling
P14-Clock Generator
P15-CRT Conn.
P16-VGA / LCD Conn.

Dunlin LA-2601 Schematics Document

P17-ICH6(1/4)_HUB,PCI,HOST
P18-ICH6(2/4)_CPU,AC97,IDE,LPC
P19-ICH6(3/4)_USB,PM,LAN,GPIO
2 P20-ICH6(4/4)_POWER&GND 2

P21-HDD/CDROM

Intel Dothan / Alviso GM(PM) / DDR-2 / ICH6-M P22-DVI / TV_Out Conn

P23-PCMCIA ENE CB1410 & CB714
P24-PCMCIA SOCKET

(NV43/44M) P25-TI 1394A TSB43AB21A

P26-LAN BCM5788M
P27-LAN Magnetic & RJ45/RJ11
P28-Mimi-PCI Slot
2005 / 03 / 14 P29-AC97 Codec_ALC250D
P30-Audio Line in Switch
P31-AMP & Audio Jack
Rev:1.0 P32-Super IO SMC217
P33-ENE-KB910
3
P34-MDC / BT / KBD / TP Conn. 3

P35-BIOS & I/O Port & SATA HDD

P36-RJ11/LID Switch / Fan / FIR
P37-USB2.0 Conn
P38-Docking Conn.
P39-PWR_OK / RTC
P40-DC INTERFACE
P41-Screws
P42-PWR-DCIN / Precharge
P43-PWR-Charger
P44-PWR-Battery Select
P45-PWR-3V/5V/12V
P46-PWR-GMCH_CORE/1.8V/0.9V
P47-PWR-1.5V/2.5V
P48-PWR-CPU_CORE
4 4
P49-PWR-OTP
P50-PWR-PIR

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401336 C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 1 of 51
A B C D E
 A B C D E

Compal confidential
File Name : LA-2601 Intel Dothan CPU Thermal Sensor Clock Generator
ADM1032ARM ICS954226AGT
page 4,5
CRT/TV-OUT
page 4 page 14
page 15
1
H_A#(3..31) FSB H_D#(0..63)
1

400 / 533 Mhz

MV43 / MV44
VGA Board
page 16
Intel Alviso GM(PM) DDR-2 DDR-SO-DIMM X2
BANK 0, 1, 2, 3page 11,12,13
PCBGA 1257
LCD CONN page 6,7,8,9,10 Signal Channel DDR-1
page 16 Two Channel DDR-2

DMI

PCI-E BUS USB 2.0 USB conn x 4

2
RJ11 CONN 2
page 37 page 36

Intel ICH6-M USB 2.0 BT Conn

page 34
PCI BUS mBGA-609
AC-LINK Audio CKT
AMP & Audio Jack
ALC250-D
page 17,18,19,20 page 29 page 31
Mini PCI BROADCOM 1394 Controller
BC M5788M ENE Controller
socket BCM4401 CB714 TSB43AB21
page 28 page 26 page 25
page 23,24
SATA PATA HDD
conn
SATA HDD
page 21
5in1 CardReader LPC BUS
3
RJ45 CONN 13 94 3

page 27 Slot 0 Slot page 24 Conn.

page 24 page 25 PATA MODULE
Connector Docking CONN.
page 21 *RJ-11 / 45(LED*2)
Power On/Off CKT. *COMPOSITE Video Out
*TVOUT
page 39
*LINE IN / OUT
SMsC LPC47N217 ENE KB910/910L *PS/2
page 32 page 33 *Print port
DC/DC Interface CKT. RTC CKT.
page 40 page 39
*1394
*USB
*DC JACK
Int. KBD
Power Circuit DC/DC Power OK CKT. Parellel Port Serial Port page 34
DOCKING CONN DOCKING CONN Touch Pad
4 page 42~49 page 39 page 38 page 38 page 39 4
CONN. page 34
BIOS
page 35

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401336 C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 2 of 51
A B C D E
 A B C D E

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
1 B+ AC or battery power rail for power circuit. N/A N/A N/A 1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+CPU_CORE Core voltage for CPU ON OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+DDRVTT 1.25V switched power rail for DDR terminator ON OFF OFF
+1.5VALW 1.5V always on power rail ON ON ON*
+1.5VS 1.5V switched power rail ON OFF OFF Board ID / SKU ID Table for AD channel
+1.8VS 1.8V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+DDRVCC 2.5V power rail for DDR ON ON OFF Ra / Rc 100K +/- 5%
+2.5VS 2.5V switched power rail ON OFF OFF Board ID Rb / Rd V AD_BID min V AD_BID typ V AD_BID max
+3VALW 3.3V always on power rail ON ON ON* 0 0 0 V 0 V 0 V
+3V 3.3V power rail ON ON OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3VS 3.3V switched power rail ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+5VALW 5V always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+5VS 5V switched power rail ON OFF OFF 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VMOD 5V switched power rail for Module Bay ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
2 2
+12VALW 12V always on power rail ON ON ON* 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+RTCVCC RTC power ON ON ON 7 NC 2.500 V 3.300 V 3.300 V

BOARD ID Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Board ID PCB Revision
External PCI Devices 0 0.1
Device IDSEL# REQ#/GNT# Interrupts 1
C ardB us AD20 2 PIRQA/PIRQB 2
1 3 94 AD16 0 PI RQE 3
SD AD20 2 PIRQA/PIRQB 4
Mini-PCI AD18 1 PIRQG/PIRQH 5
LAN AD17 3 PIRQF 6
7
3 3

EC SM Bus1 address EC SM Bus2 address

Device Address Device Address
Smart Battery 0001 011X b ADM1032 1001 110X b
EEPROM(24C16/02) 1010 000X b 2'nd Battery 1001 011X b
(24C04) 1011 000Xb

ICH6M SM Bus address

Device Address
4 4
Clock Generator 1101 001Xb
( ICS 952623)

DDR DIMM0 1010 000Xb

DDR DIMM2 1010 010Xb
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401336
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 3 of 51
A B C D E
 5 4 3 2 1

H_D#[0..63]
H_D#[0..63] <6>
+3VS
JP7A

H_A #[3..31] H_A#3 P4 A19 H _D#0

<6> H_A#[3..31]
H_A#4
H_A#5
U4
A3#
A4#
Dothan D0#
D1# A25 H _D#1
H _D#2
V3 A5# D2# A22 1

1
H_A#6 R3 B21 H _D#3
H_A#7 A6# D3# H _D#4 C12 R20
V2 A7# D4# A24
D H_A#8 W1 B26 H _D#5 0.1U_0402_16V4Z @ 10K_0402_5% D
H_A#9 A8# D5# H _D#6 2
T4 A9# D6# A21 1
H_A#10 W2 B20 H _D#7 C17

2
H_A#11 A10# D7# H _D#8 U3
Y4 A11# D8# C20
H_A#12 Y1 B24 H _D#9 2200P_0402_50V7K THERMDA 2 1
H_A#13 A12# D9# H_D#10 2 D+ VDD1
U1 A13# D10# D24
H_A#14 AA3 E24 H_D#11 THERMDC 3 6
H_A#15 A14# D11# H_D#12 D- ALERT#
Y3 A15# D12# C26
H_A#16 AA2 B23 H_D#13 8 4
A16# D13# <33,44> EC_SMB_CK2 SCLK THERM#
H_A#17 AF4 E23 H_D#14
H_A#18 A17# D14# H_D#15
AC4 A18# D15# C25 <33,44> EC_SMB_DA2 7 SDATA GND 5
H_A#19 AC7 H23 H_D#16
H_A#20 A19# D16# H_D#17
AC3 A20# D17# G25
H_A#21 AD3 L23 H_D#18 ADM1032ARM_RM8
H_A#22 A21# D18# H_D#19
AE4 A22# D19# M26
H_A#23 AD2 H24 H_D#20
H_A#24 A23# D20# H_D#21
AB4 A24# D21# F25
H_A#25 AC6 ADDR GROUP DATA GROUP G24 H_D#22
H_A#26 A25# D22# H_D#23
AD5 A26# D23# J23
H_A#27 AE2 M23 H_D#24
H_A#28 A27# D24# H_D#25
AD6 A28# D25# J25
H_A#29 AF3 L26 H_D#26
H_A#30 A29# D26# H_D#27
AE1 A30# D27# N24
H_A#31 AF1 M25 H_D#28
A31# D28# H_D#29
D29# H26
H_REQ #[0..4] H_REQ#0 R2 N25 H_D#30
<6> H_REQ#[0..4] REQ0# D30#
H_REQ#1 P3 K25 H_D#31
H_REQ#2 REQ1# D31# H_D#32 +1.05VS
T2 REQ2# D32# Y26
H_REQ#3 P1 AA24 H_D#33
C H_REQ#4 REQ3# D33# H_D#34 C
T1 REQ4# D34# T25
U23 H_D#35
D35# H_D#36
<6> H_ADSTB#0 U3 ADSTB0# D36# V23
AE5 R24 H_D#37 ITP_TDI R508 2 1 150_0402_5%
<6> H_ADSTB#1 ADSTB1# D37#
R26 H_D#38
D38# H_D#39 ITP_TDO R29
D39# R23 2 1 @ 54.9_0402_1%
A16 AA23 H_D#40
ITP_CLK0 D40# H_D#41 H_CPURST# R28
A15 ITP_CLK1 D41# U26 2 1 @ 54.9_0402_1%
V24 H_D#42
D42# H_D#43 ITP_TMS R27 40.2_0402_1%
<14> CLK_CPU_BCLK B15 BCLK0 D43# U25 2 1
B14 HOST CLK V26 H_D#44
<14> CLK_CPU_BCLK# BCLK1 D44#
Y23 H_D#45 PRO_CHOT# R31 2 1 56_0402_5%
D45# H_D#46
D46# AA26
Y25 H_D#47 H_PW RGOOD R24 2 1 200_0402_5%
D47# H_D#48
<6> H_ADS# N2 ADS# D48# AB25
L1 AC23 H_D#49 H_IER R# R23 2 1 56_0402_5%
<6> H_BNR# BNR# D49#
J3 AB24 H_D#50
<6> H_BPRI# BPRI# D50# H_D#51
<6> H_BR0# N4 BR0# D51# AC20
L4 AC22 H_D#52
<6> H_DEFER# DEFER# D52# H_D#53 +3VS
<6> H _ D R DY# H2 DRDY# D53# AC25
K3 AD23 H_D#54
<6> H_HIT# HIT# D54#
K4 CONTROL GROUP AE22 H_D#55
<6> H_HITM# HITM# D55#
H_IER R# A4 AF23 H_D#56 ITP_DBRRESET# R26 2 1 150_0402_5%
IERR# D56# H_D#57
<6> H_LOCK# J2 LOCK# D57# AD24
H_CPURST# B11 AF20 H_D#58
<6> H_CPURST# RESET# D58# H_D#59
D59# AE21
AD21 H_D#60
H_RS# [0..2] H_RS#0 D60# H_D#61 ITP_TRST# R509 680_0402_5%
<6> H_RS#[0..2] H1 RS0# D61# AF25 2 1
H_RS#1 K1 AF22 H_D#62
B H_RS#2 RS1# D62# H_D#63 ITP_TCK R30 27.4_0402_1% B
L2 RS2# D63# AF26 2 1
<6> H_TRDY# M3 TRDY# TEST1 R25 2 1 @ 1K_0402_5%
DINV0# D25 H_DINV#0 <6>
J26 TEST2 R46 2 1 @ 1K_0402_5%
DINV1# H_DINV#1 <6>
C8 BPM0# DINV2# T24 H_DINV#2 <6>
B8 BPM1# DINV3# AD20 H_DINV#3 <6>
A9 BPM2#
C9 BPM3#
DSTBN0# C23 H_DSTBN#0 <6>
ITP_DBRRESET# A7 K24
DBR# DSTBN1# H_DSTBN#1 <6>
<6> H_DBSY# M2 DBSY# DSTBN2# W25 H_DSTBN#2 <6>
<18> H_DPSLP# B7 DPSLP# DSTBN3# AE24 H_DSTBN#3 <6>
<18> H_DPRSTP# G1 DPRSTP# DSTBP0# C22 H_DSTBP#0 <6>
<6> H_DPW R# C19 DPWR# DSTBP1# L24 H_DSTBP#1 <6>
A10 PRDY# MISC DSTBP2# W24 H_DSTBP#2 <6>
B10 PREQ# DSTBP3# AE25 H_DSTBP#3 <6>
PRO_CHOT# B17 PROCHOT#
H_PW RGOOD E4
<18> H_PW RGOOD PWRGOOD
H_CPUSLP# A6
<6,18> H_CPUSLP# SLP#
ITP_TCK A13
ITP_TDI TCK
C12 TDI A20M# C2 H_A20M# <18>
ITP_TDO A12 D3
TDO FERR# H_FERR# <18>
TEST1 C5 A3
TEST1 IGNNE# H_IGNNE# <18>
TEST2 F23 B5
TEST2 INIT# H_INIT# <18>
ITP_TMS C11 D1
TMS LINT0 H_INTR <18>
ITP_TRST# B13 D4
TRST# LINT1 H_NMI <18>
A LEGACY CPU A
THERMAL
THERMDA B18 C6
THERMDC THERMDA DIODE STPCLK# H_STPCLK# <18>
A18 THERMDC SMI# B4 H_SMI# <18>
<6,18> H_THERMTRIP# C17 THERMTRIP#

TYCO_1612365-1_Dothan Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2601
THERMDA & THERMDC Trace / Space = 10 / 10 mil THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
401336
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: ¬P 期四, 三月 17, 2005 Sheet 4 of 51
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE +CPU_CORE
JP7B JP7C
220U_D2_4VM_R12 220U_D2_4VM_R12
R85 1 2 @ 54.9_0402_1% V CCSENSE AE7 A2 1 1 1 1 F20 T26
R84 @ 54.9_0402_1% VSSSENSE VCCSENSE VSS VCC VSS
1 2 AF6 VSSSENSE VSS A5 F22 VCC VSS U2
A8 + + C472 + + C460 G5 U6
VSS VCC VSS
VSS A11 G21 VCC VSS U22
F26 A14 C441 C427 H6 U24
VCCA0 VSS 2 2 2 2 VCC VSS
B1 VCCA1 VSS A17 H22 VCC VSS V1
+VCCA N1 A20 220U_D2_4VM_R12 220U_D2_4VM_R12 J5 V4
VCCA2 VSS VCC VSS
AC26 VCCA3 VSS A23 J21 VCC VSS V5
VSS A26 K22 VCC VSS V21
D
+1.05VS P23 VCCQ0 VSS B3 U5 VCC VSS V25 D
+CPU_CORE
1.8V FOR DOTHAN-A W4 VCCQ1 VSS B6 V6 VCC VSS W3
VSS B9 V22 VCC VSS W6
1 2 B12 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z W5 W22
+1.8VS R63 @ 0_1206_5% D10 VCCP
Dothan VSS
VSS B16 1
C47
1
C46
1
C45
1
C48
1
C30
1
C31
1
C32
W21
VCC
VCC
VSS
VSS W23
D12 B19 Y6 W26
D14
VCCP
VCCP
VSS
VSS B22 Y22
VCC
VCC
Dothan VSS
VSS Y2
D16 VCCP VSS B25 AA5 VCC VSS Y5
2 2 2 2 2 2 2
1.5V FOR DOTHAN-B E11 VCCP VSS C1
10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z
AA7 VCC VSS Y21
E13 C4 AA9 Y24

POWER, GROUNG, RESERVED SIGNALS AND NC

VCCP VSS VCC VSS
+1.5VS 1 2 E15 VCCP VSS C7 AA11 VCC VSS AA1
R56 0_1206_5% F10 C10 AA13 AA4
VCCP VSS +CPU_CORE VCC VSS
F12 VCCP VSS C13 AA15 VCC VSS AA6
F14 VCCP VSS C15 AA17 VCC VSS AA8
1 1 F16 C18 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z AA19 AA10
C26 VCCP VSS VCC VSS
K6 VCCP VSS C21 1 1 1 1 1 1 1 AA21 VCC VSS AA12
L5 C24 C33 C42 C40 C41 C39 C444 C443 AB6 AA14
C25 VCCP VSS VCC VSS
L21 VCCP VSS D2 AB8 VCC VSS AA16
2 2
M6 VCCP VSS D5 AB10 VCC VSS AA18
0.01U_0402_16V7K 2 2 2 2 2 2 2
M22 VCCP VSS D7 AB12 VCC VSS AA20
10U_0805_10V4Z N5 D9 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z AB14 AA22
VCCP VSS VCC VSS
N21 VCCP VSS D11
+CPU_CORE
AB16 VCC POWER, GROUND VSS AA25
P6 VCCP VSS D13 AB18 VCC VSS AB3
P22 VCCP VSS D15 AB20 VCC VSS AB5
R5 D17 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z AB22 AB7
VCCP VSS VCC VSS
R21 VCCP VSS D19 1 1 1 1 1 1 1 AC9 VCC VSS AB9
T6 D21 C454 C455 C64 C65 C66 C67 C68 AC11 AB11
VCCP VSS VCC VSS
T22 VCCP VSS D23 AC13 VCC VSS AB13
U21 VCCP VSS D26 AC15 VCC VSS AB15
C 2 2 2 2 2 2 2 C
VSS E3 AC17 VCC VSS AB17
E6 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z AC19 AB19
VSS VCC VSS
+CPU_CORE D6 VCC VSS E8 AD8 VCC VSS AB21
D8 E10 +CPU_CORE AD10 AB23
VCC VSS VCC VSS
D18 VCC VSS E12 AD12 VCC VSS AB26
D20 E14 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z AD14 AC2
VCC VSS VCC VSS
D22 VCC VSS E16 1 1 1 1 1 1 1 AD16 VCC VSS AC5
E5 E18 C69 C70 C429 C470 C430 C471 C516 AD18 AC8
VCC VSS VCC VSS
E7 VCC VSS E20 AE9 VCC VSS AC10
E9 VCC VSS E22 AE11 VCC VSS AC12
2 2 2 2 2 2 2
E17 VCC VSS E25 AE13 VCC VSS AC14
E19 F1 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z AE15 AC16
VCC VSS VCC VSS
E21 VCC VSS F4 AE17 VCC VSS AC18
F6 VCC VSS F5 AE19 VCC VSS AC21
F8 F7 +CPU_CORE AF8 AC24
VCC VSS VCC VSS
F18 VCC VSS F9 AF10 VCC VSS AD1
F11 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z AF12 AD4
VSS VCC VSS
VSS F13 1 1 1 1 1 1 1 AF14 VCC VSS AD7
<48> PSI# E1 F15 C509 C510 C511 C512 C513 C514 C515 AF16 AD9
PSI# VSS VCC VSS
VSS F17 AF18 VCC VSS AD11
+1.05VS <48> CPU_VID0 E2 F19 AD13
VID0 VSS 2 2 2 2 2 2 2 VSS
<48> CPU_VID1 F2 VID1 VSS F21 VSS AD15
<48> CPU_VID2 F3 F24 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z AD17
VID2 VSS VSS
1

<48> CPU_VID3 G3 VID3 VSS G2 VSS AD19

R75 <48> CPU_VID4 G4 G6 AD22
1K_0402_1% VID4 VSS VSS
<48> CPU_VID5 H4 VID5 VSS G22 M4 VSS VSS AD25
VSS G23 M5 VSS VSS AE3
G26 M21 AE6
2

GTL_REF0 VSS VSS VSS

1 2 AD26 GTLREF VSS H3 M24 VSS VSS AE8
B R78 2K_0402_1% B
VSS H5 Vcc-core C,uF ESR, mohm ESL,nH N3 VSS VSS AE10
H21 N6 AE12
C16
VSS
H25
Decoupling N22
VSS VSS
AE14
<14> CPU_BSEL0 BSEL0 VSS VSS VSS
<14> CPU_BSEL1 C14 BSEL1 VSS J1 SPCAP,Polymer 3X330uF 9m ohm/3 3.5nH/4 N23 VSS VSS AE16
VSS J4 N26 VSS VSS AE18
COMP0 P25 J6 MLCC 0805 X5R 35X10uF 5m ohm/35 0.6nH/35 P2 AE20
COMP1 COMP0 VSS VSS VSS
P26 COMP1 VSS J22 P5 VSS VSS AE23
COMP2 AB2 J24 P21 AE26
COMP3 COMP2 VSS VSS VSS
AB1 COMP3 VSS K2 P24 VSS VSS AF2
VSS K5 R1 VSS VSS AF5
VSS K21 R4 VSS VSS AF9
VSS K23 R6 VSS VSS AF11
B2 RSVD VSS K26 R22 VSS VSS AF13
C3 RSVD VSS L3 R25 VSS VSS AF15
E26 L6 +1.05VS T3 AF17
RSVD VSS VSS VSS
AF7 RSVD VSS L22 T5 VSS VSS AF19
AC1 L25 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z T21 AF21
RSVD VSS VSS VSS
VSS M1 1 T23 VSS VSS AF24
1 1 1 1 1 1 1 1 1 1
+
TYCO_1612365-1_Dothan C435 C445 C16 C458 C13 C15 C14 C461 C453 C448 C442 TYCO_1612365-1_Dothan
2 2 2 2 2 2 2 2 2 2 2

150U_D2_6.3VM 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

R69 1 2 27.4_0402_1% COMP0

A A
R70 1 2 54.9_0402_1% COMP1

R83 1 2 27.4_0402_1% COMP2

R82 1 2 54.9_0402_1% COMP3

Compal Electronics, Inc.
TRACE CLOSELY CPU < 0.5' Title
SCHEMATIC, M/B LA-2601
COMP0, COMP2 layout : Width 18mils and Space 25mils THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
COMP1, COMP3 layout : Space 25mils Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401336 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 5 of 51
5 4 3 2 1
 5 4 3 2 1

H_RS# [0..2] +1.5VS

H_RS#[0..2] <4>
H_A #[3..31]
<4> H_A#[3..31] CL K_DREF_SSC R51 1 2 PM@ 0_0402_5%
H_REQ #[0..4] H_D#[0..63]
<4> H_REQ#[0..4] H_D#[0..63] <4>
C LK_DREF_SSC# R52 1 2 PM@ 0_0402_5%
U5A
U5B
H_A#3 G9 E4 H _D#0
H_A#4 C9
HA3#
HA4#
Alviso HD0#
HD1# E1 H _D#1
<19> DMI_ITX_MRX_N0
DMI_ITX_MRX_N0 AA31 DMIRXN0 CFG0 G16 CF G0
H_A#5 E9 F4 H _D#2 DMI_ITX_MRX_N1 AB35 H13 MCH_CLKSEL1
HA5# HD2# <19> DMI_ITX_MRX_N1 DMIRXN1 CFG1 MCH_CLKSEL1 <14>
H_A#6 B7 H7 H _D#3 DMI_ITX_MRX_N2 AC31 G14 MCH_CLKSEL0
HA6# HD3# <19> DMI_ITX_MRX_N2 DMIRXN2 CFG2 MCH_CLKSEL0 <14>
D H_A#7 A10 E2 H _D#4 DMI_ITX_MRX_N3 AD35 F16 D
HA7# HD4# <19> DMI_ITX_MRX_N3 DMIRXN3 CFG3
H_A#8 F9 F1 H _D#5 F15
H_A#9 HA8# HD5# H _D#6 DMI_ITX_MRX_P0 CFG4 CF G5
D8 HA9# HD6# E3 <19> DMI_ITX_MRX_P0 Y31 DMIRXP0 CFG5 G15
H_A#10 B10 D3 H _D#7 DMI_ITX_MRX_P1 AA35 E16 CF G6
HA10# HD7# <19> DMI_ITX_MRX_P1 DMIRXP1 CFG6 +1.05VS
H_A#11 E10 K7 H _D#8 DMI_ITX_MRX_P2 AB31 D17 CF G7
HA11# HD8# <19> DMI_ITX_MRX_P2 DMIRXP2 CFG7
H_A#12 G10 F2 H _D#9 DMI_ITX_MRX_P3 AC35 J16
HA12# HD9# <19> DMI_ITX_MRX_P3 DMIRXP3 CFG8
H_A#13 D9 J7 H_D#10 D15 CF G9 CF G0 R40 1 2 10K_0402_5%
H_A#14 HA13# HD10# H_D#11 DMI_MTX_IRX_N0 CFG9
E11 HA14# HD11# J8 <19> DMI_MTX_IRX_N0 AA33 DMITXN0 CFG10 E15
H_A#15 F10 H6 H_D#12 DMI_MTX_IRX_N1 AB37 D14
<19> DMI_MTX_IRX_N1

DMI
H_A#16 HA15# HD12# H_D#13 DMI_MTX_IRX_N2 DMITXN1 CFG11 C FG12 CF G5 R413 1
G11 HA16# HD13# F3 <19> DMI_MTX_IRX_N2 AC33 DMITXN2 CFG12 E14 2 @ 1K_0402_5%
H_A#17 G13 K8 H_D#14 DMI_MTX_IRX_N3 AD37 H12 C FG13
HA17# HD14# <19> DMI_MTX_IRX_N3 DMITXN3 CFG13
H_A#18 C10 H5 H_D#15 C14
H_A#19 HA18# HD15# H_D#16 DMI_MTX_IRX_P0 CFG14

CFG/RSVD
C11 HA19# HD16# H1 <19> DMI_MTX_IRX_P0 Y33 DMITXP0 CFG15 H15
H_A#20 D11 H2 H_D#17 DMI_MTX_IRX_P1 AA37 J15 C FG16 CF G6 R407 1 2 1K_0402_5%
HA20# HD17# <19> DMI_MTX_IRX_P1 DMITXP1 CFG16
H_A#21 C12 K5 H_D#18 DMI_MTX_IRX_P2 AB33 H14
HA21# HD18# <19> DMI_MTX_IRX_P2 DMITXP2 CFG17
H_A#22 B13 K6 H_D#19 DMI_MTX_IRX_P3 AC37 G22 C FG18 CF G7 R408 1 2 @ 1K_0402_5%
HA22# HD19# <19> DMI_MTX_IRX_P3 DMITXP3 CFG18
H_A#23 A12 J4 H_D#20 G23 C FG19
H_A#24 HA23# HD20# H_D#21 CFG19 CF G9 R404 1
F12 HA24# HD21# G3 CFG20 D23 2 @ 1K_0402_5%
H_A#25 G12 H3 H_D#22 AM33 G25
HA25# HD22# <11> M_CLK_DDR0 SM_CK0 RSVD21
H_A#26 E12 J1 H_D#23 AL1 G24 C FG12 R409 1 2 @ 1K_0402_5%
HA26# HD23# <11> M_CLK_DDR1 SM_CK1 RSVD22
H_A#27 C13 L5 H_D#24 AE11 J17
H_A#28 HA27# HD24# H_D#25 SM_CK2 RSVD23 C FG13 R412 1
B11 HA28# HD25# K4 <12> M_CLK_DDR3 AJ34 SM_CK3 RSVD24 A31 2 @ 1K_0402_5%
H_A#29 D13 J5 H_D#26 AF6 A30
HA29# HD26# <12> M_CLK_DDR4 SM_CK4 RSVD25
H_A#30 A13 P7 H_D#27 AC10 D26 C FG16 R417 1 2 @ 1K_0402_5%
H_A#31 HA30# HD27# H_D#28 SM_CK5 RSVD26
F13 HA31# HD28# L7 RSVD27 D25
J3 H_D#29 AN33 CFG[17:3]: internal pull-up
HD29# <11> M_CLK_DDR#0 SM_CK0#

DDR MUXING
A11 P5 H_D#30 AK1
HOST

HPCREQ# HD30# <11> M_CLK_DDR#1 SM_CK1#

H_REQ#0 A7 L3 H_D#31 AE10
H_REQ#1 HREQ#0 HD31# H_D#32 SM_CK2# +2.5VS
D7 HREQ#1 HD32# U7 <12> M_CLK_DDR#3 AJ33 SM_CK3#
C H_REQ#2 B8 V6 H_D#33 AF5 C
HREQ#2 HD33# <12> M_CLK_DDR#4 SM_CK4#
H_REQ#3 C7 R6 H_D#34 AD10 C FG18 R41 1 2 @ 1K_0402_5%
H_REQ#4 HREQ#3 HD34# H_D#35 SM_CK5#
A8 HREQ#4 HD35# R5
B9 P3 H_D#36 DDR_CKE0_DIMMA AP21 C FG19 R42 1 2 @ 1K_0402_5%
<4> H_ADSTB#0 HADSTB#0 HD36# <11> DDR_CKE0_DIMMA SM_CKE0
E13 T8 H_D#37 DDR_CKE1_DIMMA AM21
<4> H_ADSTB#1 HADSTB#1 HD37# <11> DDR_CKE1_DIMMA SM_CKE1
R7 H_D#38 DDR_CKE2_DIMMB AH21 CFG[19:18]: internal pull-down
HD38# <12> DDR_CKE2_DIMMB SM_CKE2
AB1 R8 H_D#39 DDR_CKE3_DIMMB AK21
<14> CLK_MCH_BCLK# HCLKN HD39# <12> DDR_CKE3_DIMMB SM_CKE3
AB2 U8 H_D#40 J23
<14> CLK_MCH_BCLK HCLKP HD40# BM_BUSY# PM_BMBUSY# <19>
R4 H_D#41 DDR_CS0_DIMMA# AN16 J21 EXT_TS#0
HD41# <11> DDR_CS0_DIMMA# SM_CS0# EXT_TS0#
G4 T4 H_D#42 DDR_CS1_DIMMA# AM14 H22 EXT_TS#1
<4> H_DSTBN#0 HDSTBN#0 HD42# <11> DDR_CS1_DIMMA# SM_CS1# EXT_TS1#
K1 T5 H_D#43 DDR_CS2_DIMMB# AH15 F5 H_THERMTRIP#
<4> H_DSTBN#1 HDSTBN#1 HD43# <12> DDR_CS2_DIMMB# SM_CS2# THRMTRIP# H_THERMTRIP# <4,18>
R3 R1 H_D#44 DDR_CS3_DIMMB# AG16 AD30
<4> H_DSTBN#2 HDSTBN#2 HD44# <12> DDR_CS3_DIMMB# SM_CS3# PWROK VGATE <14,19,48>
V3 T3 H_D#45 AE29

CLK PM
<4> H_DSTBN#3 HDSTBN#3 HD45# RSTIN# PLT_RST# <17,19,21,32,33>
G5 V8 H_D#46 R426 1 2 40.2_0402_1% M_OCDCOMP0 AF22
<4> H_DSTBP#0 HDSTBP#0 HD46# H_D#47 R427 1 SM_OCDCOMP0
<4> H_DSTBP#1 K2 HDSTBP#1 HD47# U6 2 40.2_0402_1% M_OCDCOMP1 AF16 SM_OCDCOMP1
R2 W6 H_D#48 M_ODT0 AP14 A24 CLK_DREF_96M#
<4> H_DSTBP#2 HDSTBP#2 HD48# <11> M_ODT0 SM_ODT0 DREF_CLKN CLK_DREF_96M# <14>
W4 U3 H_D#49 M_ODT1 AL15 A23 CLK_DREF_96M
<4> H_DSTBP#3 HDSTBP#3 HD49# <11> M_ODT1 SM_ODT1 DREF_CLKP CLK_DREF_96M <14>
H8 V5 H_D#50 M_ODT2 AM11 D37 CL K_DREF_SSC
<4> H_DINV#0 HDINV#0 HD50# <12> M_ODT2 SM_ODT2 DREF_SSCLKP CLK_DREF_SSC <14>
K3 W8 H_D#51 M_ODT3 AN10 C37 C LK_DREF_SSC#
<4> H_DINV#1 HDINV#1 HD51# <12> M_ODT3 SM_ODT3 DREF_SSCLKN CLK_DREF_SSC# <14> +2.5VS
T7 W7 H_D#52
<4> H_DINV#2 HDINV#2 HD52# H_D#53 R429 1
<4> H_DINV#3 U5 HDINV#3 HD53# U2 +DDRVCC 2 80.6_0402_1% M_RCOMPN AK10 SMRCOMPN
U1 H_D#54 R430 1 2 80.6_0402_1% M_RCOMPP AK11 AP37 EXT_TS#0 R416 1 2 10K_0402_5%
HD54# H_D#55 SMVREF SMRCOMPP NC1
HD55# Y5 AF37 SMVREF0 NC2 AN37
H10 Y2 H_D#56 AD1 AP36 EXT_TS#1 R411 1 2 10K_0402_5%
<4> H_CPURST# HCPURST# HD56# SMVREF1 NC3
V4 H_D#57 M_XSLEW AE27 AP2
HD57# H_D#58 SMXSLEWIN NC4
<4> H_ADS# F8 HADS# HD58# Y7 AE28 SMXSLEWOUT NC5 AP1
B5 W1 H_D#59 M_YSLEW AF9 AN1
<4> H_TRDY# HTRDY# HD59# H_D#60 SMYSLEWIN NC6
<4> H_DPW R# G6 HDPWR# HD60# W3 AF10 SMYSLEWOUT NC7 B1
F7 Y3 H_D#61 A2
B <4> H _ D R DY# HDRDY# HD61# H_D#62 NC8 B
<4> H_DEFER# E6 HDEFER# HD62# Y6 NC9 B37 Refer to sheet 6 for FSB
H_D#63

NC
F6 HEDRDY# HD63# W2
+1.05VS NC10 A36 CFG[2:0] frequency select
<4> H_HITM# D6 HHITM# NC11 A37
D4 J11 H_ VREF Low = DMI x 2
<4> H_HIT# HHIT# HVREF H_XRCOMP R50 2 24.9_0402_1%
B3 C1 1 (10mil:20mil) CFG5 High = DMI x 4
<4>
<4>
H_LOCK#
H_BR0# E7
HLOCK#
HBREQ0#
HXRCOMP
HXSCOMP C2 H_XSCOMP
H_YRCO MP
R47 1
R72 2
2 54.9_0402_1%
24.9_0402_1%
ALVISO_BGA1257 *
<4> H_BNR# A5 HBNR# HYRCOMP T1 1 Low = DDR-II
D5 L1 H_YSCOMP R68 1 2 54.9_0402_1% CFG6 High = DDR-I
<4>
<4>
H_BPRI#
H_DBSY# CPU_SLP#
C6
HBPRI#
HDBSY#
HYSCOMP
HXSWING D1 H_XSW ING
H _YSW ING +DDRVCC
*
G8 HCPUSLP# HYSWING P1 Low = DT/Transportable CPU
H_RS#0 A4 CFG7 High = Mobile CPU
H_RS#1 C5
HRS0#
HRS1#
*

1
H_RS#2 B4 H_XRCOMP & H_YRCOMP Trace / Space = 10 / 20 mil CFG9 Low = Reverse Lane
HRS2# R423 High = Normal Operation
ALVISO_BGA1257 1K_0402_1%
*
Un-pop for Dothan-A 00 = Reserved
CFG[13:12] 01 = XOR Mode Enabled
2
R54 1 2 0_0402_5% CPU_SLP# 0.1U_0402_16V4Z SMVREF 10 = All Z Mode Enabled
<4,18> H_CPUSLP#
11 = Normal Operation (Default)
R421
1

C488
1 1 *
CFG16
C489 Low = Disabled
+1.05VS +1.05VS +1.05VS 1K_0402_1% 0.1U_0402_16V4Z (FSB Dynamic High = Enabled
2 2
ODT) *
2
1

R388 R406 R420

CFG18
Low = 1.05V (Default)
100_0603_1% 221_0603_1% 221_0603_1% (VCC Select) High = 1.5V *
A A
(5mil:15mil) (12mil:10mil) CFG19
2

Low = 1.05V (Default)

H_ VREF H_XSW ING H _YSW ING (12mil:10mil) (VTT Select) High = 1.2V *
1

1 1 1
C436 R387 C423 R405 C459
R419 Compal Electronics, Inc.
0.1U_0402_16V4Z 200_0603_1% 0.1U_0402_16V4Z 100_0603_1% 0.1U_0402_16V4Z 100_0603_1% Title
2 2 2
SCHEMATIC, M/B LA-2601
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401336 C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 6 of 51
5 4 3 2 1
 5 4 3 2 1

D D

U 5C U 5D
DDR_A_D[0..63] <11> DDR_B_D[0..63] <12>
AK15 AG35 DDR _A_D0 AJ15 AE31 DDR _B_D0
<11> DDR_A_BS#0 SA_BS0# SADQ0 <12> DDR_B_BS#0 SB_BS0# SBDQ0
AK16 AH35 DDR _A_D1 AG17 AE32 DDR _B_D1
<11> DDR_A_BS#1 SA_BS1# SADQ1 <12> DDR_B_BS#1 SB_BS1# SBDQ1
AL21 AL35 DDR _A_D2 AG21 AG32 DDR _B_D2
<11> DDR_A_BS#2 SA_BS2# SADQ2 <12> DDR_B_BS#2 SB_BS2# SBDQ2
<11> DDR_A_DM[0..7] AL37 DDR _A_D3 <12> DDR_B_DM[0..7] AG36 DDR _B_D3
DDR_A_DM0 SADQ3 DDR _A_D4 DDR_B_DM0 SBDQ3 DDR _B_D4
AJ37 SA_DM0 SADQ4 AH36 AF32 SB_DM0 SBDQ4 AE34
DDR_A_DM1 AP35 AJ35 DDR _A_D5 DDR_B_DM1 AK34 AE33 DDR _B_D5
DDR_A_DM2 SA_DM1 SADQ5 DDR _A_D6 DDR_B_DM2 SB_DM1 SBDQ5 DDR _B_D6
AL29 SA_DM2 SADQ6 AK37 AK27 SB_DM2 SBDQ6 AF31
DDR_A_DM3 AP24 AL34 DDR _A_D7 DDR_B_DM3 AK24 AF30 DDR _B_D7
DDR_A_DM4 SA_DM3 SADQ7 DDR _A_D8 DDR_B_DM4 SB_DM3 SBDQ7 DDR _B_D8
AP9 SA_DM4 SADQ8 AM36 AJ10 SB_DM4 SBDQ8 AH33
DDR_A_DM5 AP4 AN35 DDR _A_D9 DDR_B_DM5 AK5 AH32 DDR _B_D9
DDR_A_DM6 SA_DM5 SADQ9 DD R_A_D10 DDR_B_DM6 SB_DM5 SBDQ9 DD R_B_D10
AJ2 SA_DM6 SADQ10 AP32 AE7 SB_DM6 SBDQ10 AK31
DDR_A_DM7 AD3 AM31 DD R_A_D11 DDR_B_DM7 AB7 AG30 DD R_B_D11
SA_DM7 SADQ11 DD R_A_D12 SB_DM7 SBDQ11 DD R_B_D12
<11> DDR_A_DQS[0..7] SADQ12 AM34 <12> DDR_B_DQS[0..7] SBDQ12 AG34
D DR_A_DQS0 AK36 AM35 DD R_A_D13 D DR_B_DQS0 AF34 AG33 DD R_B_D13
D DR_A_DQS1 SA_DQS0 SADQ13 DD R_A_D14 D DR_B_DQS1 SB_DQS0 SBDQ13 DD R_B_D14
AP33 SA_DQS1 SADQ14 AL32 AK32 SB_DQS1 SBDQ14 AH31
D DR_A_DQS2 AN29 AM32 DD R_A_D15 D DR_B_DQS2 AJ28 AJ31 DD R_B_D15
D DR_A_DQS3 SA_DQS2 SADQ15 DD R_A_D16 D DR_B_DQS3 SB_DQS2 SBDQ15 DD R_B_D16
AP23 SA_DQS3 SADQ16 AN31 AK23 SB_DQS3 SBDQ16 AK30
D DR_A_DQS4 AM8 AP31 DD R_A_D17 D DR_B_DQS4 AM10 AJ30 DD R_B_D17
D DR_A_DQS5 SA_DQS4 SADQ17 DD R_A_D18 D DR_B_DQS5 SB_DQS4 SBDQ17 DD R_B_D18
AM4 SA_DQS5 SADQ18 AN28 AH6 SB_DQS5 SBDQ18 AH29
D DR_A_DQS6 AJ1 AP28 DD R_A_D19 D DR_B_DQS6 AF8 AH28 DD R_B_D19
D DR_A_DQS7 SA_DQS6 SADQ19 DD R_A_D20 D DR_B_DQS7 SB_DQS6 SBDQ19 DD R_B_D20
AE5 SA_DQS7 SADQ20 AL30 AB4 SB_DQS7 SBDQ20 AK29
<11> DDR_A_DQS#[0..7] AM30 DD R_A_D21 <12> DDR_B_DQS#[0..7] AH30 DD R_B_D21
DDR_A_DQS#0 SADQ21 DD R_A_D22 DDR_B_DQS#0 SBDQ21 DD R_B_D22
AK35 SA_DQS0# SADQ22 AM28 AF35 SB_DQS0# SBDQ22 AH27
C DDR_A_DQS#1 AP34 AL28 DD R_A_D23 DDR_B_DQS#1 AK33 AG28 DD R_B_D23 C

DDR SYSTEM MEMORY B

DDR_A_DQS#2 SA_DQS1# SADQ23 DD R_A_D24 DDR_B_DQS#2 SB_DQS1# SBDQ23 DD R_B_D24
AN30 AP27 AK28 AF24
DDR MEMORY SYSTEM A

DDR_A_DQS#3 SA_DQS2# SADQ24 DD R_A_D25 DDR_B_DQS#3 SB_DQS2# SBDQ24 DD R_B_D25

AN23 SA_DQS3# SADQ25 AM27 AJ23 SB_DQS3# SBDQ25 AG23
DDR_A_DQS#4 AN8 AM23 DD R_A_D26 DDR_B_DQS#4 AL10 AJ22 DD R_B_D26
DDR_A_DQS#5 SA_DQS4# SADQ26 DD R_A_D27 DDR_B_DQS#5 SB_DQS4# SBDQ26 DD R_B_D27
AM5 SA_DQS5# SADQ27 AM22 AH7 SB_DQS5# SBDQ27 AK22
DDR_A_DQS#6 AH1 AL23 DD R_A_D28 DDR_B_DQS#6 AF7 AH24 DD R_B_D28
DDR_A_DQS#7 SA_DQS6# SADQ28 DD R_A_D29 DDR_B_DQS#7 SB_DQS6# SBDQ28 DD R_B_D29
AE4 SA_DQS7# SADQ29 AM24 AB5 SB_DQS7# SBDQ29 AH23
<11> DDR_A_MA[0..13] AN22 DD R_A_D30 <12> DDR_B_MA[0..13] AG22 DD R_B_D30
DDR_A_MA0 SADQ30 DD R_A_D31 DDR_B_MA0 SBDQ30 DD R_B_D31
AL17 SA_MA0 SADQ31 AP22 AH17 SB_MA0 SBDQ31 AJ21
DDR_A_MA1 AP17 AM9 DD R_A_D32 DDR_B_MA1 AK17 AG10 DD R_B_D32
DDR_A_MA2 SA_MA1 SADQ32 DD R_A_D33 DDR_B_MA2 SB_MA1 SBDQ32 DD R_B_D33
AP18 SA_MA2 SADQ33 AL9 AH18 SB_MA2 SBDQ33 AG9
DDR_A_MA3 AM17 AL6 DD R_A_D34 DDR_B_MA3 AJ18 AG8 DD R_B_D34
DDR_A_MA4 SA_MA3 SADQ34 DD R_A_D35 DDR_B_MA4 SB_MA3 SBDQ34 DD R_B_D35
AN18 SA_MA4 SADQ35 AP7 AK18 SB_MA4 SBDQ35 AH8
DDR_A_MA5 AM18 AP11 DD R_A_D36 DDR_B_MA5 AJ19 AH11 DD R_B_D36
DDR_A_MA6 SA_MA5 SADQ36 DD R_A_D37 DDR_B_MA6 SB_MA5 SBDQ36 DD R_B_D37
AL19 SA_MA6 SADQ37 AP10 AK19 SB_MA6 SBDQ37 AH10
DDR_A_MA7 AP20 AL7 DD R_A_D38 DDR_B_MA7 AH19 AJ9 DD R_B_D38
DDR_A_MA8 SA_MA7 SADQ38 DD R_A_D39 DDR_B_MA8 SB_MA7 SBDQ38 DD R_B_D39
AM19 SA_MA8 SADQ39 AM7 AJ20 SB_MA8 SBDQ39 AK9
DDR_A_MA9 AL20 AN5 DD R_A_D40 DDR_B_MA9 AH20 AJ7 DD R_B_D40
DDR_A_MA10 SA_MA9 SADQ40 DD R_A_D41 DDR_B_MA10 SB_MA9 SBDQ40 DD R_B_D41
AM16 SA_MA10 SADQ41 AN6 AJ16 SB_MA10 SBDQ41 AK6
DDR_A_MA11 AN20 AN3 DD R_A_D42 DDR_B_MA11 AG18 AJ4 DD R_B_D42
DDR_A_MA12 SA_MA11 SADQ42 DD R_A_D43 DDR_B_MA12 SB_MA11 SBDQ42 DD R_B_D43
AM20 SA_MA12 SADQ43 AP3 AG20 SB_MA12 SBDQ43 AH5
DDR_A_MA13 AM15 AP6 DD R_A_D44 DDR_B_MA13 AG15 AK8 DD R_B_D44
SA_MA13 SADQ44 DD R_A_D45 SB_MA13 SBDQ44 DD R_B_D45
SADQ45 AM6 SBDQ45 AJ8
AN15 AL4 DD R_A_D46 AH14 AJ5 DD R_B_D46
<11> DDR_A_CAS# SA_CAS# SADQ46 <12> DDR_B_CAS# SB_CAS# SBDQ46
AP16 AM3 DD R_A_D47 AK14 AK4 DD R_B_D47
<11> DDR_A_RAS# SA_RAS# SADQ47 <12> DDR_B_RAS# SB_RAS# SBDQ47
AF29 AK2 DD R_A_D48 AF15 AG5 DD R_B_D48
SA_RCVENIN# SADQ48 DD R_A_D49 SB_RCVENIN# SBDQ48 DD R_B_D49
AF28 SA_RCVENOUT# SADQ49 AK3 AF14 SB_RCVENOUT# SBDQ49 AG4
AP15 AG2 DD R_A_D50 AH16 AD8 DD R_B_D50
<11> DDR_A_W E# SA_WE# SADQ50 <12> DDR_B_W E# SB_WE# SBDQ50
AG1 DD R_A_D51 AD9 DD R_B_D51
B SADQ51 DD R_A_D52 SBDQ51 DD R_B_D52 B
SADQ52 AL3 SBDQ52 AH4
AM2 DD R_A_D53 AG6 DD R_B_D53
SADQ53 DD R_A_D54 SBDQ53 DD R_B_D54
SADQ54 AH3 SBDQ54 AE8
AG3 DD R_A_D55 AD7 DD R_B_D55
SADQ55 DD R_A_D56 SBDQ55 DD R_B_D56
SADQ56 AF3 SBDQ56 AC5
AE3 DD R_A_D57 AB8 DD R_B_D57
SADQ57 DD R_A_D58 SBDQ57 DD R_B_D58
SADQ58 AD6 SBDQ58 AB6
AC4 DD R_A_D59 AA8 DD R_B_D59
SADQ59 DD R_A_D60 SBDQ59 DD R_B_D60
SADQ60 AF2 SBDQ60 AC8
AF1 DD R_A_D61 AC7 DD R_B_D61
SADQ61 DD R_A_D62 SBDQ61 DD R_B_D62
SADQ62 AD4 SBDQ62 AA4
AD5 DD R_A_D63 AA5 DD R_B_D63
SADQ63 SBDQ63

ALVISO_BGA1257 ALVISO_BGA1257

A A

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401336 C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 7 of 51
5 4 3 2 1
 5 4 3 2 1

+3VS +2.5VS

PCIE_MTX_C_GRX_N[0..15]
<16> PCIE_MTX_C_GRX_N[0..15]

1
PCIE_MTX_C_GRX_P[0..15]
<16> PCIE_MTX_C_GRX_P[0..15]
R402
GM@ 2.2K_0402_5% PCEI_GTX_C_MRX_N[0..15]
<16> PCEI_GTX_C_MRX_N[0..15]

2
G
2
PCEI_GTX_C_MRX_P[0..15]
<16> PCEI_GTX_C_MRX_P[0..15]
1 3 LBKLT_EN
<16,33> GMCH_ENBKL

S
D D
Q44
GM@ BSS138_SOT23 U5G
SDVO_SDAT H24 D36 PEG_COMP 1 2 +1.5VS
<16> SDVO_SDAT SDVOCTRL_DATA EXP_COMPI
SDVO_SCLK H25 D34 R48 24.9_0402_1%
<16> SDVO_SCLK SDVOCTRL_CLK EXP_ICOMPO
AB29

MISC
<14> CLK_MCH_3GPLL# GCLKN
AC29 PCEI_GTX_C_MRX_N0
<14> CLK_MCH_3GPLL GCLKP EXP_RXN0/SDVO_TVCLKIN# E30 PCEI_GTX_C_MRX_N1
EXP_RXN1/SDVO_INT# F34 PCEI_GTX_C_MRX_N2
GMCH_TV_COMPS EXP_RXN2/SDVO_FLDSTALL# G30 PCEI_GTX_C_MRX_N3
<22> GMCH_TV_COMPS A15 TVDAC_A EXP_RXN3 H34
GMCH_TV_LUMA C16 PCEI_GTX_C_MRX_N4
<22> GMCH_TV_LUMA
GMCH_TV_CRMA TVDAC_B EXP_RXN4 J30 PCEI_GTX_C_MRX_N5
<22> GMCH_TV_CRMA A17 TVDAC_C EXP_RXN5 K34
2 1 TV_REFSET J18 PCEI_GTX_C_MRX_N6
R418 4.99K_0603_1% TV_REFSET EXP_RXN6 L30 PCEI_GTX_C_MRX_N7
2 1 B15 TV_IRTNA EXP_RXN7 M34
R399 0_0402_5% B16 PCEI_GTX_C_MRX_N8
TV_IRTNB EXP_RXN8 N30 PCEI_GTX_C_MRX_N9
B17 EXP_RXN9 P34

TV
TV_IRTNC PCEI_GTX_C_MRX_N10
EXP_RXN10 R30 PCEI_GTX_C_MRX_N11
EXP_RXN11 T34 PCEI_GTX_C_MRX_N12
EXP_RXN12 U30 PCEI_GTX_C_MRX_N13
EXP_RXN13 V34 PCEI_GTX_C_MRX_N14
GMCH_CRT_CLK EXP_RXN14 W30 PCEI_GTX_C_MRX_N15
<15> GMCH_CRT_CLK E24 DDCCLK EXP_RXN15 Y34
GMCH_CRT_DATA E23
<15> GMCH_CRT_DATA DDCDATA
E21 D30 PCEI_GTX_C_MRX_P0
<15> GMCH_CRT_B BLUE EXP_RXP0/SDVO_TVCLKIN
2 1 D21 E34 PCEI_GTX_C_MRX_P1
R384 150_0402_5% BLUE# EXP_RXP1/SDVO_INT PCEI_GTX_C_MRX_P2
<15> GMCH_CRT_G C20 GREEN EXP_RXP2/SDVO_FLDSTALL F30
2 1 B20 G34 PCEI_GTX_C_MRX_P3
R385 150_0402_5% GREEN# EXP_RXP3 PCEI_GTX_C_MRX_P4
<15> GMCH_CRT_R A19 RED EXP_RXP4 H30
2 1 B19 J34 PCEI_GTX_C_MRX_P5
C R386 150_0402_5% RED# EXP_RXP5 PCEI_GTX_C_MRX_P6 C
H21 K30

VGA
<15> GMCH_CRT_VSYNC VSYNC EXP_RXP6
G21 L34 PCEI_GTX_C_MRX_P7
<15> GMCH_CRT_HSYNC HSYNC EXP_RXP7

PCI - EXPRESS GRAPHICS

1 2 REFSET J20 REFSET EXP_RXP8 M30 PCEI_GTX_C_MRX_P8
R414 255_0402_1% N34 PCEI_GTX_C_MRX_P9
EXP_RXP9 PCEI_GTX_C_MRX_P10
EXP_RXP10 P30
R34 PCEI_GTX_C_MRX_P11
EXP_RXP11 PCEI_GTX_C_MRX_P12
EXP_RXP12 T30
U34 PCEI_GTX_C_MRX_P13
EXP_RXP13 PCEI_GTX_C_MRX_P14
EXP_RXP14 V30
W34 PCEI_GTX_C_MRX_P15
EXP_RXP15
E25 LBKLT_CTL
LBKLT_EN F25 E32 PCIE_MTX_GRX_N0 C57 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N0
LCTLA_CLK LBKLT_EN EXP_TXN0/SDVOB_RED# PCIE_MTX_GRX_N1 C59
C23 LCTLA_CLK EXP_TXN1/SDVOB_GREEN# F36 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N1
+2.5VS LCTLB_DATA C22 G32 PCIE_MTX_GRX_N2 C62 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N2
LDD C_CLK LCTLB_DATA EXP_TXN2/SDVOB_BLUE# PCIE_MTX_GRX_N3 C71
F23 LDDC_CLK EXP_TXN3/SDVOB_CLKN H36 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N3
R381 1 2 4.7K_0402_5% GMCH_CRT_CLK LDDC_DATA F22 J32 PCIE_MTX_GRX_N4 C74 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N4
GM CH_ENVDD LDDC_DATA EXP_TXN4/SDVOC_RED# PCIE_MTX_GRX_N5 C76
<16> GMCH_ENVDD F26 LVDD_EN EXP_TXN5/SDVOC_GREEN# K36 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N5
R382 1 2 4.7K_0402_5% GMCH_CRT_DATA L IBG C33 L32 PCIE_MTX_GRX_N6 C78 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N6
LIBG EXP_TXN6/SDVOC_BLUE# PCIE_MTX_GRX_N7 C80
C31 LVBG EXP_TXN7/SDVOC_CLKN M36 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N7
R400 1 2 2.2K_0402_5% LCTLB_DATA F28 N32 PCIE_MTX_GRX_N8 C87 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N8
LVREFH EXP_TXN8 PCIE_MTX_GRX_N9 C91
F27 LVREFL EXP_TXN9 P36 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N9
R39 1 2 2.2K_0402_5% LCTLA_CLK R32 PCIE_MTX_GRX_N10 C97 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N10
GMCH_TXCLK- EXP_TXN10 PCIE_MTX_GRX_N11 C100 1
<16> GMCH_TXCLK- B30 LACLKN EXP_TXN11 T36 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N11
GMCH_TXCLK+ B29 U32 PCIE_MTX_GRX_N12 C104 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N12
<16> GMCH_TXCLK+ LACLKP EXP_TXN12

LVDS
GMCH_TZCLK- C25 V36 PCIE_MTX_GRX_N13 C109 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N13
<16> GMCH_TZCLK- LBCLKN EXP_TXN13
R398 1 2 100K_0402_5% LBKLT_EN GMCH_TZCLK+ C24 W32 PCIE_MTX_GRX_N14 C114 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N14
<16> GMCH_TZCLK+ LBCLKP EXP_TXN14
Y36 PCIE_MTX_GRX_N15 C116 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N15
R403 1.5K_0402_1% L IBG GMCH_TXOUT0- EXP_TXN15
1 2 <16> GMCH_TXOUT0- B34 LADATAN0
GMCH_TXOUT1- B33
B <16> GMCH_TXOUT1- LADATAN1 B
R44 1 2 150_0402_5% GMCH_TV_COMPS GMCH_TXOUT2- B32 D32 PCIE_MTX_GRX_P0 C56 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P0
<16> GMCH_TXOUT2- LADATAN2 EXP_TXP0/SDVOB_RED
E36 PCIE_MTX_GRX_P1 C58 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P1
R515 150_0402_5% GMCH_TV_LUMA EXP_TXP1/SDVOB_GREEN PCIE_MTX_GRX_P2 C60
1 2 EXP_TXP2/SDVOB_BLUE F32 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P2
GMCH_TXOUT0+ A34 G36 PCIE_MTX_GRX_P3 C63 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P3
<16> GMCH_TXOUT0+ LADATAP0 EXP_TXP3/SDVOB_CLKP
R516 1 2 150_0402_5% GMCH_TV_CRMA GMCH_TXOUT1+ A33 H32 PCIE_MTX_GRX_P4 C73 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P4
<16> GMCH_TXOUT1+ LADATAP1 EXP_TXP4/SDVOC_RED
GMCH_TXOUT2+ B31 J36 PCIE_MTX_GRX_P5 C75 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P5
<16> GMCH_TXOUT2+ LADATAP2 EXP_TXP5/SDVOC_GREEN
K32 PCIE_MTX_GRX_P6 C77 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P6
EXP_TXP6/SDVOC_BLUE PCIE_MTX_GRX_P7 C79 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P7
EXP_TXP7/SDVOC_CLKP L36 1 2
M32 PCIE_MTX_GRX_P8 C83 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P8
GMCH_TZOUT0- EXP_TXP8 PCIE_MTX_GRX_P9 C89
<16> GMCH_TZOUT0- C29 LBDATAN0 EXP_TXP9 N36 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P9
GMCH_TZOUT1- D28 P32 PCIE_MTX_GRX_P10 C92 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P10
<16> GMCH_TZOUT1- LBDATAN1 EXP_TXP10
GMCH_TZOUT2- C27 R36 PCIE_MTX_GRX_P11 C98 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P11
<16> GMCH_TZOUT2- LBDATAN2 EXP_TXP11
T32 PCIE_MTX_GRX_P12 C101 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P12
+2.5VS EXP_TXP12 PCIE_MTX_GRX_P13 C105 1
EXP_TXP13 U36 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P13
+3VS V32 PCIE_MTX_GRX_P14 C110 1 2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P14
GMCH_TZOUT0+ EXP_TXP14 PCIE_MTX_GRX_P15 C115 1 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P15
<16> GMCH_TZOUT0+ C28 LBDATAP0 EXP_TXP15 W36 2
GMCH_TZOUT1+ D27
<16> GMCH_TZOUT1+ LBDATAP1
2

GMCH_TZOUT2+ C26
<16> GMCH_TZOUT2+ LBDATAP2
R45 R49
4.7K_0402_5% GM@ 4.7K_0402_5%
2
G

ALVISO_BGA1257
1

LDD C_CLK 3 1 GMCH_LCD_CLK

GMCH_LCD_CLK <16>
S

Q6
GM@ 2N7002_SOT23

A A
+2.5VS
+3VS
2

R397 R401
4.7K_0402_5% GM@ 4.7K_0402_5% Compal Electronics, Inc.
2
G

Title
SCHEMATIC, M/B LA-2601
1

LDDC_DATA 3 1 GMCH_LCD_DATA
GMCH_LCD_DATA <16> THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
S

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Q43 401336 C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
GM@ 2N7002_SOT23
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 8 of 51
5 4 3 2 1
 5 4 3 2 1

+1.05VS
4000mA
U 5F C519
U5E 0.1U_0402_16V4Z C505 2.2U_0603_6.3V6K
0.1U_0402_16V4Z 0.1U_0402_16V4Z
120mA +1.05VS K13 AM37 V 1.8_DDR_CAP1 2 1 0.1U_0402_16V4Z
VTT0 VCCSM0 V 1.8_DDR_CAP2
+1.05VS T29 VCC0 VCCA_TVDACA0 F17 +3VS_TVDAC J13 VTT1 VCCSM1 AH37 2 1 1 1 1 1 1 1
R29 E17 1 K12 AP29 V 1.8_DDR_CAP5 2 1 C457 C451 C452
VCC1 VCCA_TVDACA1 VTT2 VCCSM2 C520
N29 VCC2 VCCA_TVDACB0 D18 W11 VTT3 VCCSM3 AD28 +DDRVCC
M29 C18 + V11 AD27 0.1U_0402_16V4Z C450 C456 C447
VCC3 VCCA_TVDACB1 C871 VTT4 VCCSM4 2 2 2 2 2 2
K29 VCC4 VCCA_TVDACC0 F18 U11 VTT5 VCCSM5 AC27
J29 E18 T11 AP26 22U_1206_16V4Z_V1
VCC5 VCCA_TVDACC1 TV@ 2 150U_D2_6.3VM VTT6 VCCSM6 2.2U_0603_6.3V6K 0.1U_0402_16V4Z
D V28 R11 AN26 D
U28
T28
VCC6
VCC7
VCC8 POWER VCCA_TVBG
VSSA_TVBG
H18
G18
P11
N11
VTT7
VTT8
VTT9
POWER VCCSM7
VCCSM8
VCCSM9
AM26
AL26 +DDRVCC
2200mA
R28 VCC9 M11 VTT10 VCCSM10 AK26
P28 D19 L11 AJ26 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VCC10 VCCD_TVDAC VTT11 VCCSM11
N28 VCC11 VCCDQ_TVDAC H17 24mA K11 VTT12 VCCSM12 AH26 1
M28 VCC12 W10 VTT13 VCCSM13 AG26 1 1 1 1 1 1 1 1
L28 B26 V10 AF26 + C494 C86 C81 C483
VCC13 VCCD_LVDS0 +1.5VS VTT14 VCCSM14
K28 VCC14 VCCD_LVDS1 B25 U10 VTT15 VCCSM15 AE26
J28 A25 60mA T10 AP25 C88 C487 C498 C481 C486
VCC15 VCCD_LVDS2 VTT16 VCCSM16 330U_D2E_2.5VM 2 2 2 2 2 2 2 2 2
H28 VCC16 R10 VTT17 VCCSM17 AN25
G28 VCC17 VCCA_LVDS A35 +2.5VS P10 VTT18 VCCSM18 AM25
V27 10mA N10 AL25 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VCC18 VTT19 VCCSM19
U27 VCC19 VCCHV0 B22 M10 VTT20 VCCSM20 AK25
T27 VCC20 VCCHV1 B21 2mA K10 VTT21 VCCSM21 AJ25
R27 VCC21 VCCHV2 A21 J10 VTT22 VCCSM22 AH25
P27 VCC22 Y9 VTT23 VCCSM23 AG25
+2.5VS
N27 VCC23 VCCTX_LVDS0 B28 W9 VTT24 VCCSM24 AF25 VCCHV(Ball A21,B21,B22)
M27 VCC24 VCCTX_LVDS1 A28 60mA U9 VTT25 VCCSM25 AE25
L27 VCC25 VCCTX_LVDS2 A27 R9 VTT26 VCCSM26 AE24
K27 VCC26 P9 VTT27 VCCSM27 AE23
J27 VCC27 VCCA_SM0 AF20 +1.5VS_DDRDLL N9 VTT28 VCCSM28 AE22 1 1 1 1 1 1
H27 AP19 M9 AE21 C417 C419 C413 C416 C21 C414
VCC28 VCCA_SM1 VTT29 VCCSM29
K26 VCC29 VCCA_SM2 AF19 L9 VTT30 VCCSM30 AE20
H26 VCC30 VCCA_SM3 AF18 J9 VTT31 VCCSM31 AE19
2 0.1U_0402_16V4Z 2 0.01U_0402_16V7K 2 4.7U_0805_10V4Z 2 0.1U_0402_16V4Z 2 4.7U_0805_10V4Z 2 0.1U_0402_16V4Z
K25 VCC31 N8 VTT32 VCCSM32 AE18
J25 VCC32 VCC3G0 AE37 +1.5VS_PEG M8 VTT33 VCCSM33 AE17
K24 VCC33 VCC3G1 W37 N7 VTT34 VCCSM34 AE16
K23 VCC34 VCC3G2 U37 M7 VTT35 VCCSM35 AE15
C K22 VCC35 VCC3G3 R37 1500mA N6 VTT36 VCCSM36 AE14 VCCA_LVDS (Ball A35) VCCTX_LVDS(Ball A27,A28,B28) C
K21 VCC36 VCC3G4 N37 M6 VTT37 VCCSM37 AP13
W20 VCC37 VCC3G5 L37 A6 VTT38 VCCSM38 AN13
+2.5VS
U20 VCC38 VCC3G6 J37
C23
N5 VTT39 VCCSM39 AM13 VCCA_CRTDAC(Ball F19,E19)
T20 VCC39 1 M5 VTT40 VCCSM40 AL13
K20 0.47U_0603_16V4Z N4 AK13
VCC40 VTT41 VCCSM41
V19 VCC41 M4 VTT42 VCCSM42 AJ13
U19 VCC42 VCCA_3GPLL0 Y29 +1.5VS_3GPLL N3 VTT43 VCCSM43 AH13 1 1 1 1
2 C22 C434 C424 C431
K19 VCC43 VCCA_3GPLL1 Y28 M3 VTT44 VCCSM44 AG13
W18 VCC44 VCCA_3GPLL2 Y27 N2 VTT45 VCCSM45 AF13
V18 VCC45 M2 VTT46 VCCSM46 AE13
2 4.7U_0805_10V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.022U_0402_16V7K
T18 VCC46 B2 VTT47 VCCSM47 AP12
K18 VCC47 VCCA_3GBG F37 0.15mA +2.5VS_3GBG V1 VTT48 VCCSM48 AN12
K17 VCC48 VSSA_3GBG G37 N1 VTT49 VCCSM49 AM12
70mA 1 M1 VTT50 VCCSM50 AL12
+1.5VS AC1 VCCD_HMPLL1 VCC_SYNC H20 +2.5VS G1 VTT51 VCCSM51 AK12 VCC_SYNC(Ball H20)
AC2 VCCD_HMPLL2 VCCSM52 AJ12
+1.5VS_DPLLA +1.5VS_DPLLA B23 F19 C24 AH12
+1.5VS_DPLLB VCCA_DPLLA VCCA_CRTDAC0 0.47U_0603_16V4Z 2 VCCSM53
+1.5VS_DPLLB
+1.5VS_HPLL
C35 VCCA_DPLLB VCCA_CRTDAC1 E19 VCCSM54 AG12
+1.5VS VCCD_TVDAC (Ball D19)
+1.5VS_HPLL AA1 VCCA_HPLL VSSA_CRTDAC G19 1 VCCSM55 AF12
+1.5VS_MPLL +1.5VS_MPLL AA2 AE12 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VCCA_MPLL VCCSM56
VCCSM57 AD11
1 C49 AC11
ALVISO_BGA1257 0.22U_0402_10V4Z 2 VCCSM58
VCCSM59 AB11 1 1 1 1 1 1
+ AB10 C82 C20 C415 C421 C425 C440 C437
1 VCCSM60
C872 AB9 0.1U_0402_16V4Z C517
150U_D2_6.3VM VCCSM61
VCCSM62 AP8 V 1.8_DDR_CAP6 2 1 0.1U_0402_16V4Z
2 C34 4.7U_0805_10V4Z 2 2 2 2 2 2
VCCSM63 AM1 V 1.8_DDR_CAP4 2 1
0.22U_0402_10V4Z 2
VCCSM64 AE1 V 1.8_DDR_CAP3 2 1
B C490 0.1U_0402_16V4Z 0.022U_0402_16V7K 0.022U_0402_16V7K B
0.1U_0402_16V4Z
ALVISO_BGA1257 VCCD_LVDS(Ball A25,B25,B26) VCCDQ_TVDAC (Ball H17)
+1.05VS
+1.5VS_PEG
950mA
R415 470U_D2_2.5VM
1 2 +1.5VS
1 1 1 1 1
+1.5VS_DPLLA L6 +1.5VS_DPLLB L25 +1.5VS_DDRDLL R86 0_0805_5% C462 C463 C474 C469
1 1 1
CHB1608U301_0603 CHB1608U301_0603 0_0603_5% C446 C449 C439 + C53
60mA 60mA
1 2 +1.5VS 1 2 +1.5VS 1 2 +1.5VS 2 2.2U_0603_6.3V6K 2 2.2U_0603_6.3V6K 2 2.2U_0603_6.3V6K 2 2.2U_0603_6.3V6K
2 22U_1206_16V4Z_V1 2 4.7U_0805_10V4Z 2 4.7U_0805_10V4Z 2
1 1 1 1 1 1
C412 C418 C426 C420 C84 C496

2 22U_1206_16V4Z_V1 2 0.1U_0402_16V4Z 2 22U_1206_16V4Z_V1 2 0.1U_0402_16V4Z 2 22U_1206_16V4Z_V1 2 0.1U_0402_16V4Z

+3VS_TVDAC L49 +3VS VCCA_TVDAC VCCA_TVBG (Ball H18)

CHB1608U301_0603
1 2

1 1 1 1
C432 C422 C433 C438
+1.5VS_HPLL L7 +1.5VS_MPLL L8 +1.5VS_3GPLL R79 L9 +2.5VS_3GBG
60mA CHB1608U301_0603 60mA CHB1608U301_0603 0.5_0603_1% CHB1608U301_0603
2 0.1U_0402_16V4Z 2 0.022U_0402_16V7K 2 0.1U_0402_16V4Z 2 0.022U_0402_16V7K
A 1 2 +1.5VS 1 2 +1.5VS 1 2+3GPLL 1 2 +1.5VS 1 2 +2.5VS A
R410 0_0603_5%
1 1 1 1 1 1 1
C50 C478 C52 C482 C55
C475 C428 120mA
0.1U_0402_16V4Z
2 22U_1206_16V4Z_V1 2 0.1U_0402_16V4Z 2 22U_1206_16V4Z_V1 2 0.1U_0402_16V4Z 2 10U_1206_16V4Z 2 0.1U_0402_16V4Z 2
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401336 C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 9 of 51
5 4 3 2 1
 5 4 3 2 1

U 5H
U5I U5J
+1.05VS L12 VTT_NCTF17 VCCSM_NCTF31 AB12 +DDRVCC
M12 VTT_NCTF16 VCCSM_NCTF30 AC12 Y1 VSS271 AL24 VSS267
N12 VTT_NCTF15 VCCSM_NCTF29 AD12 D2 VSS270 VSSALVDS B36 AN24 VSS266 VSS67 AC32
P12 VTT_NCTF14 VCCSM_NCTF28 AB13 G2 VSS269 A26 VSS265 VSS66 AD32
R12 VTT_NCTF13 VCCSM_NCTF27 AC13 J2 VSS268 VSS195 AA11 E26 VSS264 VSS65 AJ32
T12 VTT_NCTF12 VCCSM_NCTF26 AD13 L2 VSS260 VSS194 AF11 G26 VSS263 VSS64 AN32
U12 VTT_NCTF11 VCCSM_NCTF25 AC14 P2 VSS259 VSS193 AG11 J26 VSS262 VSS63 D33
D V12 VTT_NCTF10 VCCSM_NCTF24 AD14 T2 VSS258 VSS192 AJ11 B27 VSS261 VSS62 E33 D
W12 VTT_NCTF9 VCCSM_NCTF23 AC15 V2 VSS257 VSS191 AL11 E27 VSS129 VSS61 F33
L13 VTT_NCTF8 VCCSM_NCTF22 AD15 AD2 VSS256 VSS190 AN11 G27 VSS128 VSS60 G33
M13 VTT_NCTF7 VCCSM_NCTF21 AC16 AE2 VSS255 VSS189 B12 W27 VSS127 VSS59 H33
N13
P13
R13
T13
U13
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
AD16
AC17
AD17
AC18
AD18
AH2
AL2
AN2
A3
C3
VSS254
VSS253
VSS252
VSS251
VSS
VSS188
VSS187
VSS186
VSS185
D12
J12
A14
B14
F14
AA27
AB27
AF27
AG27
AJ27
VSS126
VSS125
VSS124
VSS123
VSS VSS58
VSS57
VSS56
VSS55
J33
K33
L33
M33
N33
VTT_NCTF2 VCCSM_NCTF16 VSS250 VSS184 VSS122 VSS54
V13 VTT_NCTF1 VCCSM_NCTF15 AC19 AA3 VSS249 VSS183 J14 AL27 VSS121 VSS53 P33
W13 VTT_NCTF0 VCCSM_NCTF14 AD19 AB3 VSS248 VSS182 K14 AN27 VSS120 VSS52 R33
VCCSM_NCTF13 AC20 AC3 VSS247 VSS181 AG14 E28 VSS119 VSS51 T33
VCCSM_NCTF12 AD20 AJ3 VSS246 VSS180 AJ14 W28 VSS118 VSS50 U33
Y12 VSS_NCTF68 VCCSM_NCTF11 AC21 C4 VSS245 VSS179 AL14 AA28 VSS117 VSS49 V33
AA12 VSS_NCTF67 VCCSM_NCTF10 AD21 H4 VSS244 VSS178 AN14 AB28 VSS116 VSS48 W33
Y13 VSS_NCTF66 VCCSM_NCTF9 AC22 L4 VSS243 VSS177 C15 AC28 VSS115 VSS47 AD33
AA13 VSS_NCTF65 VCCSM_NCTF8 AD22 P4 VSS242 VSS176 K15 A29 VSS114 VSS46 AF33
L14 VSS_NCTF64 VCCSM_NCTF7 AC23 U4 VSS241 VSS175 A16 D29 VSS113 VSS45 AL33
M14 VSS_NCTF63 VCCSM_NCTF6 AD23 Y4 VSS240 VSS174 D16 E29 VSS112 VSS44 C34
N14 VSS_NCTF62 VCCSM_NCTF5 AC24 AF4 VSS239 VSS173 H16 F29 VSS111 VSS43 AA34
P14 VSS_NCTF61 VCCSM_NCTF4 AD24 AN4 VSS238 VSS172 K16 G29 VSS110 VSS42 AB34
R14 VSS_NCTF60 VCCSM_NCTF3 AC25 E5 VSS237 VSS171 AL16 H29 VSS109 VSS41 AC34
T14 VSS_NCTF59 VCCSM_NCTF2 AD25 W5 VSS236 VSS170 C17 L29 VSS108 VSS40 AD34
U14 VSS_NCTF58 VCCSM_NCTF1 AC26 AL5 VSS235 VSS169 G17 P29 VSS107 VSS39 AH34
V14 VSS_NCTF57 VCCSM_NCTF0 AD26 AP5 VSS234 VSS168 AF17 U29 VSS106 VSS38 AN34
W14 VSS_NCTF56 B6 VSS233 VSS167 AJ17 V29 VSS105 VSS37 B35
Y14 VSS_NCTF55 VCC_NCTF78 L17 +1.05VS J6 VSS232 VSS166 AN17 W29 VSS104 VSS36 D35
AA14 VSS_NCTF54 VCC_NCTF77 M17 L6 VSS231 VSS165 A18 AA29 VSS103 VSS35 E35
AB14 VSS_NCTF53 VCC_NCTF76 N17 P6 VSS230 VSS164 B18 AD29 VSS102 VSS34 F35
C L15 P17 T6 U18 AG29 G35 C
VSS_NCTF52 VCC_NCTF75 VSS229 VSS163 VSS101 VSS33
M15 T17 AA6 AL18 AJ29 H35
NCTF

VSS_NCTF51 VCC_NCTF74 VSS228 VSS162 VSS100 VSS32

N15 VSS_NCTF50 VCC_NCTF73 U17 AC6 VSS227 VSS161 C19 AM29 VSS99 VSS31 J35
P15 VSS_NCTF49 VCC_NCTF72 V17 AE6 VSS226 VSS160 H19 C30 VSS98 VSS30 K35
R15 VSS_NCTF48 VCC_NCTF71 W17 AJ6 VSS225 VSS159 J19 Y30 VSS97 VSS29 L35
T15 VSS_NCTF47 VCC_NCTF70 L18 G7 VSS224 VSS158 T19 AA30 VSS96 VSS28 M35
U15 VSS_NCTF46 VCC_NCTF69 M18 V7 VSS223 VSS157 W19 AB30 VSS95 VSS27 N35
V15 VSS_NCTF45 VCC_NCTF68 N18 AA7 VSS222 VSS156 AG19 AC30 VSS94 VSS26 P35
W15 VSS_NCTF44 VCC_NCTF67 P18 AG7 VSS221 VSS155 AN19 AE30 VSS93 VSS25 R35
Y15 VSS_NCTF43 VCC_NCTF66 R18 AK7 VSS220 VSS154 A20 AP30 VSS92 VSS24 T35
AA15 VSS_NCTF42 VCC_NCTF65 Y18 AN7 VSS219 VSS153 D20 D31 VSS91 VSS23 U35
AB15 VSS_NCTF41 VCC_NCTF64 L19 C8 VSS218 VSS152 E20 E31 VSS90 VSS22 V35
L16 VSS_NCTF40 VCC_NCTF63 M19 E8 VSS217 VSS151 F20 F31 VSS89 VSS21 W35
M16 VSS_NCTF39 VCC_NCTF62 N19 L8 VSS216 VSS150 G20 G31 VSS88 VSS20 Y35
N16 VSS_NCTF38 VCC_NCTF61 P19 P8 VSS215 VSS149 V20 H31 VSS87 VSS19 AE35
P16 VSS_NCTF37 VCC_NCTF60 R19 Y8 VSS214 VSS148 AK20 J31 VSS86 VSS18 C36
R16 VSS_NCTF36 VCC_NCTF59 Y19 AL8 VSS213 VSS147 C21 K31 VSS85 VSS17 AA36
T16 VSS_NCTF35 VCC_NCTF58 L20 A9 VSS212 VSS146 F21 L31 VSS84 VSS16 AB36
U16 VSS_NCTF34 VCC_NCTF57 M20 H9 VSS211 VSS145 AF21 M31 VSS83 VSS15 AC36
V16 VSS_NCTF33 VCC_NCTF56 N20 K9 VSS210 VSS144 AN21 N31 VSS82 VSS14 AD36
W16 VSS_NCTF32 VCC_NCTF55 P20 T9 VSS209 VSS143 A22 P31 VSS81 VSS13 AE36
Y16 VSS_NCTF31 VCC_NCTF54 R20 V9 VSS208 VSS142 D22 R31 VSS80 VSS12 AF36
AA16 VSS_NCTF30 VCC_NCTF53 Y20 AA9 VSS207 VSS141 E22 T31 VSS79 VSS11 AJ36
AB16 VSS_NCTF29 VCC_NCTF52 L21 AC9 VSS206 VSS140 J22 U31 VSS78 VSS10 AL36
R17 VSS_NCTF28 VCC_NCTF51 M21 AE9 VSS205 VSS139 AH22 V31 VSS77 VSS9 AN36
Y17 VSS_NCTF27 VCC_NCTF50 N21 AH9 VSS204 VSS138 AL22 W31 VSS76 VSS8 E37
AA17 VSS_NCTF26 VCC_NCTF49 P21 AN9 VSS203 VSS137 H23 AD31 VSS75 VSS7 H37
AB17 VSS_NCTF25 VCC_NCTF48 T21 D10 VSS202 VSS136 AF23 AG31 VSS74 VSS6 K37
AA18 VSS_NCTF24 VCC_NCTF47 U21 L10 VSS201 VSS135 B24 AL31 VSS73 VSS5 M37
B B
AB18 VSS_NCTF23 VCC_NCTF46 V21 Y10 VSS200 VSS134 D24 A32 VSS72 VSS4 P37
AA19 VSS_NCTF22 VCC_NCTF45 W21 AA10 VSS199 VSS133 F24 C32 VSS71 VSS3 T37
AB19 VSS_NCTF21 VCC_NCTF44 L22 F11 VSS198 VSS132 J24 Y32 VSS70 VSS2 V37
AA20 VSS_NCTF20 VCC_NCTF43 M22 H11 VSS197 VSS131 AG24 AA32 VSS69 VSS1 Y37
AB20 VSS_NCTF19 VCC_NCTF42 N22 Y11 VSS196 VSS130 AJ24 AB32 VSS68 VSS0 AG37
R21 VSS_NCTF18 VCC_NCTF41 P22
Y21 VSS_NCTF17 VCC_NCTF40 R22
AA21 VSS_NCTF16 VCC_NCTF39 T22
AB21 U22 ALVISO_BGA1257 ALVISO_BGA1257
VSS_NCTF15 VCC_NCTF38
Y22 VSS_NCTF14 VCC_NCTF37 V22
AA22 VSS_NCTF13 VCC_NCTF36 W22
AB22 VSS_NCTF12 VCC_NCTF35 L23
Y23 VSS_NCTF11 VCC_NCTF34 M23
AA23 VSS_NCTF10 VCC_NCTF33 N23
AB23 VSS_NCTF9 VCC_NCTF32 P23
Y24 VSS_NCTF8 VCC_NCTF31 R23
AA24 VSS_NCTF7 VCC_NCTF30 T23
AB24 VSS_NCTF6 VCC_NCTF29 U23
Y25 VSS_NCTF5 VCC_NCTF28 V23
AA25 VSS_NCTF4 VCC_NCTF27 W23
AB25 VSS_NCTF3 VCC_NCTF26 L24
Y26 VSS_NCTF2 VCC_NCTF25 M24
AA26 VSS_NCTF1 VCC_NCTF24 N24
AB26 VSS_NCTF0 VCC_NCTF23 P24
VCC_NCTF22 R24
+1.05VS V25 VCC_NCTF10 VCC_NCTF21 T24
W25 VCC_NCTF9 VCC_NCTF20 U24
L26 VCC_NCTF8 VCC_NCTF19 V24
A M26 VCC_NCTF7 VCC_NCTF18 W24 A
N26 VCC_NCTF6 VCC_NCTF17 L25
P26 VCC_NCTF5 VCC_NCTF16 M25
R26 VCC_NCTF4 VCC_NCTF15 N25
T26 VCC_NCTF3 VCC_NCTF14 P25
U26 VCC_NCTF2 VCC_NCTF13 R25
V26 T25
W26
VCC_NCTF1 VCC_NCTF12
U25 Compal Electronics, Inc.
VCC_NCTF0 VCC_NCTF11 Title
SCHEMATIC, M/B LA-2601
ALVISO_BGA1257
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401336 C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 10 of 51
5 4 3 2 1
 5 4 3 2 1

+DDRVCC +DDRVCC +DIMM_VREF +DDRVCC

DDR_A_D [0..63]
<7> DDR_A_D[0..63]
DDR_A_ DM[0..7]
<7> DDR_A_DM[0..7]

1
0.1U_0402_16V4Z
JP24 R92
1 2 C840 DDR_A_D QS[0..7]
VREF VSS DDR _A_D4 <7> DDR_A_DQS[0..7]
3 VSS DQ4 4 1 1
DDR _A_D0 5 6 DDR _A_D5 1K_0402_1% DD R_A_MA[0..13]
DQ0 DQ5 <7> DDR_A_MA[0..13]

4.7U_0805_10V4Z

C121
DDR _A_D1 7 8

2
DQ1 VSS DDR_A_DM0 DDR_A_ DQS#[0..7]
9 VSS DM0 10 <7> DDR_A_DQS#[0..7]
DDR_A_DQS#0 2 2
11 DQS0# VSS 12
D DR_A_DQS0 13 14 DDR _A_D6
DQS0 DQ6 DDR _A_D7
15 VSS DQ7 16

1
D DDR _A_D2 17 18 R91 D
DDR _A_D3 DQ2 VSS DD R_A_D12
19 DQ3 DQ12 20
21 22 DD R_A_D13 +DDRVCC
DDR _A_D8 VSS DQ13 1K_0402_1%
23 DQ8 VSS 24
DDR _A_D9 25 26 DDR_A_DM1 Layout Note:

2
DQ9 DM1
27 28
DDR_A_DQS#1 29
VSS VSS
30 M_CLK_DDR0 Place near DIMM
DQS1# CK0 M_CLK_DDR0 <6>
D DR_A_DQS1 31 32 M_CLK_DDR#0 1 1 1 1 1
DQS1 CK0# M_CLK_DDR#0 <6>
33 34 C795 C796 C797 C798 C799
DD R_A_D10 VSS VSS DD R_A_D14
35 DQ10 DQ14 36

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z
DD R_A_D11 37 38 DD R_A_D15
DQ11 DQ15 2 2 2 2 2
39 VSS VSS 40

41 VSS VSS 42
DD R_A_D16 43 44 DD R_A_D20
DD R_A_D17 DQ16 DQ20 DD R_A_D21
45 DQ17 DQ21 46
47 VSS VSS 48

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_A_DQS#2 49 50
D DR_A_DQS2 DQS2# NC DDR_A_DM2
51 DQS2 DM2 52 1 1 1 1

C800

C801

C802

C803
53 VSS VSS 54
DD R_A_D18 55 56 DD R_A_D22
DD R_A_D19 DQ18 DQ22 DD R_A_D23
57 DQ19 DQ23 58
2 2 2 2
59 VSS VSS 60
DD R_A_D24 61 62 DD R_A_D28
DD R_A_D25 DQ24 DQ28 DD R_A_D29
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# D DR_A_DQS3
69 NC DQS3 70
C 71 72 C
DD R_A_D26 VSS VSS DD R_A_D30
73 DQ26 DQ30 74
DD R_A_D27 75 76 DD R_A_D31 +0.9V_DDR_VTT
DQ27 DQ31
77 VSS VSS 78
DDR_CKE0_DIMMA 79 80 DDR_CKE1_DIMMA
<6> DDR_CKE0_DIMMA CKE0 NC/CKE1 DDR_CKE1_DIMMA <6>
81 VDD VDD 82

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
83 NC NC/A15 84
DDR_A_BS#2 85 86
<7> DDR_A_BS#2 BA2 NC/A14
87 VDD VDD 88 1 1 1 1 1 1 1 1 1 1 1 1 1
DDR_A_MA12 89 90 DDR_A_MA11
DDR_A_MA9 A12 A11 DDR_A_MA7
91 A9 A7 92
DDR_A_MA8 93 94 DDR_A_MA6
A8 A6 2 2 2 2 2 2 2 2 2 2 2 2 2
95 VDD VDD 96

C804

C805

C806

C807

C808

C809

C810

C811

C812

C813

C814

C815

C816
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS#1 Layout Note:
A10/AP BA1 DDR_A_BS#1 <7>
DDR_A_BS#0 107 108 D DR_A_RAS#
<7> DDR_A_BS#0
DDR_A_W E# 109
BA0 RAS#
110 DDR_CS0_DIMMA#
DDR_A_RAS# <7> Place one cap close to every 2 pullup
<7> DDR_A_W E# WE# S0# DDR_CS0_DIMMA# <6>
111 VDD VDD 112 resistors terminated to +0.9V_DDR_VTT
D DR_A_CAS# 113 114 M_ODT0
<7> DDR_A_CAS# CAS# ODT0 M_ODT0 <6>
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
<6> DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
M_ODT1 119 120
<6> M_ODT1 NC/ODT1 NC
121 VSS VSS 122
DD R_A_D32 123 124 DD R_A_D36 +0.9V_DDR_VTT
DD R_A_D33 DQ32 DQ36 DD R_A_D37
125 DQ33 DQ37 126
127 128 RP30 RP59
B DDR_A_DQS#4 VSS VSS DDR_A_DM4 DDR_A_MA8 DDR_CKE0_DIMMA B
129 DQS4# DM4 130 1 4 4 1
D DR_A_DQS4 131 132 DDR_A_MA5 2 3 3 2 DDR_A_BS#2
DQS4 VSS DD R_A_D38 56_0404_4P2R_5% 56_0404_4P2R_5%
133 VSS DQ38 134
DD R_A_D34 135 136 DD R_A_D39 RP29 RP58 Layout Note:
DD R_A_D35 DQ34 DQ39 DDR_A_MA3 DDR_A_MA7
137 DQ35 VSS 138 1 4 4 1 Place these resistor
139 140 DD R_A_D44 DDR_A_MA1 2 3 3 2 DDR_A_MA6
DD R_A_D40 VSS DQ44 DD R_A_D45 56_0404_4P2R_5% 56_0404_4P2R_5% closely DIMM0,all
141 DQ40 DQ45 142
DD R_A_D41 143 144 RP28 RP57 trace length<750 mil
DQ41 VSS DDR_A_DQS#5 D DR_A_RAS# DDR_A_MA12
145 VSS DQS5# 146 1 4 4 1
DDR_A_DM5 147 148 D DR_A_DQS5 DDR_CS0_DIMMA# 2 3 3 2 DDR_A_MA9
DM5 DQS5 56_0404_4P2R_5% 56_0404_4P2R_5%
149 VSS VSS 150
DD R_A_D42 151 152 DD R_A_D46 RP27 RP35
DD R_A_D43 DQ42 DQ46 DD R_A_D47 DDR_A_MA10 DDR_A_MA4
153 DQ43 DQ47 154 1 4 4 1
155 156 DDR_A_BS#0 2 3 3 2 DDR_A_MA2
DD R_A_D48 VSS VSS DD R_A_D52 56_0404_4P2R_5% 56_0404_4P2R_5%
157 DQ48 DQ52 158
DD R_A_D49 159 160 DD R_A_D53 RP26 RP34
DQ49 DQ53 DDR_A_W E# DDR_A_MA0
161 VSS VSS 162 1 4 4 1
163 164 M_CLK_DDR1 D DR_A_CAS# 2 3 3 2 DDR_A_BS#1
NC,TEST CK1 M_CLK_DDR1 <6>
165 166 M_CLK_DDR#1 56_0404_4P2R_5% 56_0404_4P2R_5%
VSS CK1# M_CLK_DDR#1 <6>
DDR_A_DQS#6 167 168 RP33
D DR_A_DQS6 DQS6# VSS DDR_A_DM6 M_ODT0
169 DQS6 DM6 170 4 1
171 172 3 2 DDR_A_MA13
DD R_A_D50 VSS VSS DD R_A_D54 56_0404_4P2R_5%
173 DQ50 DQ54 174
DD R_A_D51 175 176 DD R_A_D55
DQ51 DQ55
177 VSS VSS 178 RP31 RP32 Layout Note:
DD R_A_D56 179 180 DD R_A_D60 M_ODT1 2 3 4 1 DDR_CKE1_DIMMA Place these resistor
DD R_A_D57 DQ56 DQ60 DD R_A_D61 DDR_CS1_DIMMA# 1 DDR_A_MA11
181 DQ57 DQ61 182 4 3 2 closely DIMM0,all
183 184 56_0404_4P2R_5% 56_0404_4P2R_5%
DDR_A_DM7 VSS VSS DDR_A_DQS#7 trace length
A 185 DM7 DQS7# 186 A
187 188 D DR_A_DQS7 Max=1.3"
DD R_A_D58 VSS DQS7
189 DQ58 VSS 190
DD R_A_D59 191 192 DD R_A_D62
DQ59 DQ62 DD R_A_D63
193 VSS DQ63 194
D_CK_SDATA 195 196
<12,14,38> D_CK_SDATA SDA VSS
D_CK_SCLK 197 198 R692 1 2 10K_0402_5%
<12,14,38> D_CK_SCLK
+3VS 199
SCL SAO
200 R693 1 2 10K_0402_5% Compal Electronics, Inc.
VDDSPD SA1 Title
1
C857
2 SCHEMATIC, M/B LA-2601
JAE_MM50-200B1-1R~D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
0.1U_0402_16V4Z Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401336 C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 11 of 51
5 4 3 2 1
 A B C D E

+DDRVCC +DDRVCC +DIMM_VREF DDR_B_D [0..63]

<7> DDR_B_D[0..63]
DDR_B_ DM[0..7]
<7> DDR_B_DM[0..7]
JP25

0.1U_0402_16V4Z
1 2 DDR_B_D QS[0..7]
VREF VSS DDR _B_D4 <7> DDR_B_DQS[0..7]
3 VSS DQ4 4
DDR _B_D0 5 6 DDR _B_D5 1 1 DD R_B_MA[0..13]
DQ0 DQ5 <7> DDR_B_MA[0..13]
DDR _B_D1 7 8 C841
DQ1 VSS

C843
9 10 DDR_B_DM0 DDR_B_ DQS#[0..7]
VSS DM0 <7> DDR_B_DQS#[0..7]

4.7U_0805_10V4Z
DDR_B_DQS#0 11 12
D DR_B_DQS0 DQS0# VSS DDR _B_D6 2 2
13 DQS0 DQ6 14
1 15 16 DDR _B_D7 1
DDR _B_D2 VSS DQ7 +DDRVCC
17 DQ2 VSS 18
DDR _B_D3 19 20 DD R_B_D12
DQ3 DQ12 DD R_B_D13
21 VSS DQ13 22
DDR _B_D8 23 24
DDR _B_D9 DQ8 VSS DDR_B_DM1
25 DQ9 DM1 26
27 VSS VSS 28 1 1 1 1 1
DDR_B_DQS#1 29 30 M_CLK_DDR3 C817 C818 C819 C820 C821 Layout Note:
DQS1# CK0 M_CLK_DDR3 <6>
D DR_B_DQS1 31 32 M_CLK_DDR#3
DQS1 CK0# M_CLK_DDR#3 <6> Place near DIMM

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z
33 VSS VSS 34
DD R_B_D10 DD R_B_D14 2 2 2 2 2
35 DQ10 DQ14 36
DD R_B_D11 37 38 DD R_B_D15
DQ11 DQ15
39 VSS VSS 40

41 VSS VSS 42
DD R_B_D16 43 44 DD R_B_D20
DQ16 DQ20

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DD R_B_D17 45 46 DD R_B_D21
DQ17 DQ21
47 VSS VSS 48 1 1 1 1 1

C822

C823

C824

C825

C826
DDR_B_DQS#2 49 50
D DR_B_DQS2 DQS2# NC DDR_B_DM2
51 DQS2 DM2 52
53 VSS VSS 54
DD R_B_D18 DD R_B_D22 2 2 2 2 2
55 DQ18 DQ22 56
DD R_B_D19 57 58 DD R_B_D23
DQ19 DQ23
59 VSS VSS 60
DD R_B_D24 61 62 DD R_B_D28
DD R_B_D25 DQ24 DQ28 DD R_B_D29
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
2 DM3 DQS3# D DR_B_DQS3 2
69 NC DQS3 70
71 72 +0.9V_DDR_VTT
DD R_B_D26 VSS VSS DD R_B_D30
73 DQ26 DQ30 74
DD R_B_D27 75 76 DD R_B_D31
DQ27 DQ31
77 VSS VSS 78
DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB
<6> DDR_CKE2_DIMMB CKE0 NC/CKE1 DDR_CKE3_DIMMB <6>

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
81 VDD VDD 82
83 NC NC/A15 84
DDR_B_BS#2 85 86 1 1 1 1 1 1 1 1 1 1 1 1 1
<7> DDR_B_BS#2 BA2 NC/A14
87 VDD VDD 88
DDR_B_MA12 89 90 DDR_B_MA11
DDR_B_MA9 A12 A11 DDR_B_MA7
91 A9 A7 92
DDR_B_MA8 DDR_B_MA6 2 2 2 2 2 2 2 2 2 2 2 2 2
93 A8 A6 94

C827

C828

C829

C830

C831

C832

C833

C834

C835

C836

C837

C838

C839
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
DDR_B_MA1 101 102 DDR_B_MA0
A1 A0
103 VDD VDD 104 Layout Note:
DDR_B_MA10 105 106 DDR_B_BS#1
DDR_B_BS#0 107
A10/AP BA1
108 D DR_B_RAS#
DDR_B_BS#1 <7> Place one cap close to every 2 pullup
<7> DDR_B_BS#0 BA0 RAS# DDR_B_RAS# <7>
<7> DDR_B_W E#
DDR_B_W E# 109 WE# S0# 110 DDR_CS2_DIMMB#
DDR_CS2_DIMMB# <6> resistors terminated to +0.9V_DDR_VTT
111 VDD VDD 112
D DR_B_CAS# 113 114 M_ODT2
<7> DDR_B_CAS# CAS# ODT0 M_ODT2 <6>
DDR_CS3_DIMMB# 115 116 DDR_B_MA13
<6> DDR_CS3_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
M_ODT3 119 120
<6> M_ODT3 NC/ODT1 NC
121 VSS VSS 122
DD R_B_D32 123 124 DD R_B_D36 +0.9V_DDR_VTT
DD R_B_D33 DQ32 DQ36 DD R_B_D37
125 DQ33 DQ37 126
3 3
127 128 RP71 RP66
DDR_B_DQS#4 VSS VSS DDR_B_DM4 DDR_B_MA3 DDR_B_MA12
129 DQS4# DM4 130 1 4 4 1
D DR_B_DQS4 131 132 DDR_B_MA1 2 3 3 2 DDR_B_MA9
DQS4 VSS DD R_B_D38 56_0404_4P2R_5% 56_0404_4P2R_5%
133 VSS DQ38 134
DD R_B_D34 135 136 DD R_B_D39 RP70 RP65
DD R_B_D35 DQ34 DQ39 DDR_B_MA10 DDR_CKE3_DIMMB
137 DQ35 VSS 138 1 4 4 1
139 140 DD R_B_D44 DDR_B_BS#0 2 3 3 2 DDR_B_MA11
DD R_B_D40 VSS DQ44 DD R_B_D45 56_0404_4P2R_5% 56_0404_4P2R_5%
141 DQ40 DQ45 142 Layout Note:
DD R_B_D41 143 144 RP69 RP64 Place these resistor
DQ41 VSS DDR_B_DQS#5 DDR_B_MA0 DDR_B_MA8
145 VSS DQS5# 146 1 4 4 1 closely DIMM0,all
DDR_B_DM5 147 148 D DR_B_DQS5 DDR_B_BS#1 2 3 3 2 DDR_B_MA5
DM5 DQS5 56_0404_4P2R_5% 56_0404_4P2R_5% trace length<750 mil
149 VSS VSS 150
DD R_B_D42 151 152 DD R_B_D46 RP68 RP63
DD R_B_D43 DQ42 DQ46 DD R_B_D47 D DR_B_RAS# DDR_B_MA7
153 DQ43 DQ47 154 1 4 4 1
155 156 DDR_CS2_DIMMB# 2 3 3 2 DDR_B_MA6
DD R_B_D48 VSS VSS DD R_B_D52 56_0404_4P2R_5% 56_0404_4P2R_5%
157 DQ48 DQ52 158
DD R_B_D49 159 160 DD R_B_D53 RP67 RP62
DQ49 DQ53 DDR_B_W E# DDR_B_MA4
161 VSS VSS 162 1 4 4 1
163 164 M_CLK_DDR4 D DR_B_CAS# 2 3 3 2 DDR_B_MA2
NC,TEST CK1 M_CLK_DDR4 <6>
165 166 M_CLK_DDR#4 56_0404_4P2R_5% 56_0404_4P2R_5%
VSS CK1# M_CLK_DDR#4 <6>
DDR_B_DQS#6 167 168 RP61
D DR_B_DQS6 DQS6# VSS DDR_B_DM6 M_ODT2
169 DQS6 DM6 170 4 1
171 172 3 2 DDR_B_MA13
DD R_B_D50 VSS VSS DD R_B_D54
173 DQ50 DQ54 174
DD R_B_D51 175 176 DD R_B_D55 56_0404_4P2R_5%
DQ51 DQ55
177 VSS VSS 178
DD R_B_D56 179 180 DD R_B_D60 RP56 RP60 Layout Note:
DD R_B_D57 DQ56 DQ60 DD R_B_D61 M_ODT3 DDR_CKE2_DIMMB
181 DQ57 DQ61 182 2 3 4 1 Place these resistor
183 184 DDR_CS3_DIMMB# 1 4 3 2 DDR_B_BS#2
4
DDR_B_DM7 VSS VSS DDR_B_DQS#7 56_0404_4P2R_5% closely DIMM0,all 4
185 DM7 DQS7# 186
187 188 D DR_B_DQS7 56_0404_4P2R_5% trace length
DD R_B_D58 VSS DQS7 Max=1.3"
189 DQ58 VSS 190
DD R_B_D59 191 192 DD R_B_D62
DQ59 DQ62 DD R_B_D63
193 VSS DQ63 194
D_CK_SDATA 195 196
<11,14,38> D_CK_SDATA
<11,14,38> D_CK_SCLK
D_CK_SCLK 197
SDA VSS
198 R695 1 2 10K_0402_5% Compal Electronics, Inc.
SCL SAO R694 1
+3VS 199 VDDSPD SA1 200 2 10K_0402_5% +3VS Title
SCHEMATIC, M/B LA-2601
1 2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
C858 JAE_MM50-200B1-1~D Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1U_0402_16V4Z 401336 C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 12 of 51
A B C D E
 A B C D E

Layout note :
Distrib ute as close as possible
to DDR-SODIMM.

+DDRVCC

1 1
1 1 1 1 1 1 1 1 1
C117 C103 C122 C102 C99 C118 C136 C119 C138
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2

+DDRVCC +DDRVCC

1 1
C137
0.1U_0402_16V4Z
2 2
1 1 1 1
C135 C124 C123 + +
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C85 C139
2 2 150U_D2_6.3VM 150U_D2_6.3VM
2 2

2 2

3 3

4 4

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401336 C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 13 of 51
A B C D E
 A B C D E F G H

L10
KC FBM-L11-201209-221LMAT_0805 40mil
+CLK_VDD1
Clock Generator
+CLK_VDD48 + CLK_VDDREF +3VS 1 2
FSC FSB FSA CPU SRC PCI 1
C555
1
C157
1 1 1 1 1 1

CLKSEL0 CLKSEL1 CLKSEL2 C156 C144 C149 C145 C147 C152

MHz MHz MHz 0.047U_0402_16V7K 2.2U_0603_6.3V6K 0.047U_0402_16V7K 0.047U_0402_16V7K 0.047U_0402_16V7K 0.047U_0402_16V7K
2 2.2U_0603_6.3V6K 2 0.047U_0402_16V7K 2 2 2 2 2 2
1 0 1 100 100 33.3
*
0 0 1 133 100 33.3
1 1

0 1 1 166 100 33.3 +CLK_VCCA 1 2 +CLK_VDD1

+CLK_VDD1 R449
U8
40mil 2.2_0402_5% L11 +CLK_VDD2
0 1 0 200 100 33.3 1 1
KC FBM-L11-201209-221LMAT_0805
+CLK_VDD2 40mil
21 VDDPCIEX_0 +3VS 1 2
28 37 C553 C150
VDDPCIEX_1 VDDA 2 2.2U_0603_6.3V6K 2 0.047U_0402_16V7K
+3VS Table : ICS 954206B 34 VDDPCIEX_2 1 1 1
GNDA 38
1 VDDPCI_0
7 C165 C159 C163
CLKSEL2 VDDPCI_1 STP_PCI# 2 2.2U_0603_6.3V6K 2 0.047U_0402_16V7K 2 0.047U_0402_16V7K
1 2 PCI/SRC_STOP# 55 PM_STP_PCI# <19>
R139 10K_0402_5% +CLK_VDD1
CLK_PCI2 = 1, Pin 32,33
54 STP_CPU#
are PEREQ# pin CPU_STOP# PM_STP_CPU# <19,48>
1 2 CL K_PCI2
R153 10K_0402_5% 42
C162 Y1 VDDCPU
1 2 + CLK_VDDREF 48 VDDREF
1 2 CL K_PCI0 33P_0402_50V8J 14.318MHZ_16PF_DSX840GA R135 1_0402_5% 15mil
R145 10K_0402_5% 1 2 41 C LK_CPU1 R124 1 2 33_0402_5% CLK_MCH_BCLK
CPUCLKT1 CLK_MCH_BCLK <6>
1 1 2 +CLK_VDD48 11 VDD48
1 2 CL K_PCI1 R455 2.2_0402_5% 15mil 40 CLK_CPU1# R120 1 2 33_0402_5% CLK_MCH_BCLK#
CPUCLKC1 CLK_MCH_BCLK# <6>
R141 10K_0402_5% CLK_MCH_BCLK 1 2
C161 XTALIN 50 R123 49.9_0402_1%
33P_0402_50V8J X1 CLK_MCH_BCLK# 1 2
2

1 2 XTALOUT 49 44 C LK_CPU0 R134 1 2 33_0402_5% CLK_CPU_BCLK R119 49.9_0402_1%

X2 CPUCLKT0 CLK_CPU_BCLK <4>
CLK_ICH_48M R143 1 2 12_0402_5% CLK_CPU_BCLK 1 2
<19> CLK_ICH_48M
43 CLK_CPU0# R128 1 2 33_0402_5% CLK_CPU_BCLK# R133 49.9_0402_1%
CPUCLKC0 CLK_CPU_BCLK# <4>
2 CLK_SD_48M R147 1 2 12_0402_5% CLKSEL2 12 CLK_CPU_BCLK# 1 2 2
<23> CLK_SD_48M FS_A/USB_48MHz
CLK_14M_CODEC 2 1 CLKSEL0 53 R127 49.9_0402_1%
<29> CLK_14M_CODEC REF1/FSLC/TEST_SEL
R151 12_0402_5% CLK_EZ_CLK1 1 2
CLK_PCI0 = 0, Pin 35,36 R112 49.9_0402_1%
CLKSEL1 16 36 C LK_SRC3 R106 1 2 33_0402_5% CLK_MCH_3GPLL CLK_EZ_CLK1# 1 2
are PCIe CLK pair FSLB/TEST_MODE CPUCLKT2_ITP/PCIEXT6 CLK_MCH_3GPLL <8>
R108 49.9_0402_1%
R77 1 2 12_0402_5% 35 CLK_SRC3# R102 1 2 33_0402_5% CLK_MCH_3GPLL#
<23> CLK_PCI_PCM CPUCLKC2_ITP/PCIEXC6 CLK_MCH_3GPLL# <8>
CLK_PCI1 = 0, Pin 17,18
C LK_PCI_LAN 1 2 CL K_PCI5 5
are 96Mhz <26> CLK_PCI_LAN PCICLK5
R71 12_0402_5%
CLK_PC I_MINI 1 2 CL K_PCI4 4 33 PEREQ1# R684 1 2 0_0402_5% PE_REQ1# CLK_PCIE_SATA 1 2
<28> CLK_PCI_MINI PCICLK4 PEREQ1#/PCIEXT5 PE_REQ1# <33>
R150 33_0402_5% R101 49.9_0402_1%
CLK _PCI_SIO 1 2 CL K_PCI3 3 32 PEREQ2# R685 1 2 0_0402_5% PE_REQ2# CLK_PCIE_SATA# 1 2
<32> CLK_PCI_SIO PCICLK3 PEREQ2#/PCIEXC5 PE_REQ2# <33>
R149 33_0402_5% R97 49.9_0402_1%
CLK_PCI_1394 1 2 CL K_PCI2 56 CLK_MCH_3GPLL 1 2
<25> CLK_PCI_1394 PCICLK2/REQ_SEL
R154 33_0402_5% 31 C LK_SRC2 R114 1 2 33_0402_5% CLK_PCIE_VGA R107 49.9_0402_1%
PCIEXT4 CLK_PCIE_VGA <16>
C LK_PCI_LPC 1 2 CL K_PCI1 9 CLK_MCH_3GPLL# 1 2
<33> CLK_PCI_LPC SELPCIEX_LCDCLK#/PCICLK_F1
R142 33_0402_5% 30 CLK_SRC2# R110 1 2 33_0402_5% CLK_PCIE_VGA# R103 49.9_0402_1%
PCIEXC4 CLK_PCIE_VGA# <16>
CLK_PCIE_VGA 1 2
R115 49.9_0402_1%
CLK_PCI_ICH 1 2 CL K_PCI0 8 26 C LK_SRC4 R100 1 2 33_0402_5% CLK_PCIE_SATA CLK_PCIE_VGA# 1 2
<17> CLK_PCI_ICH ITP_EN/PCICLK_F0 SATACLKT CLK_PCIE_SATA <18>
R146 33_0402_5% R111 49.9_0402_1%
D_CK_SCLK 46 27 CLK_SRC4# R96 1 2 33_0402_5% CLK_PCIE_SATA# CLK_PC IE_ICH 1 2
<11,12,38> D_CK_SCLK SCLK SATACLKC CLK_PCIE_SATA# <18>
R122 49.9_0402_1%
CLK_P CIE_ICH# 1 2
D_CK_SDATA 47 24 C LK_SRC6 R678 1 2 33_0402_5% CLK_EZ_CLK2 R118 49.9_0402_1%
<11,12,38> D_CK_SDATA SDATA PCIEXT3 CLK_EZ_CLK2 <38>
CL K_DREF_SSC 1 2
25 CLK_SRC6# R679 1 2 33_0402_5% CLK_EZ_CLK2# R130 49.9_0402_1%
PCIEXC3 CLK_EZ_CLK2# <38>
1 2 CLKIR EF 39 IREF
C LK_DREF_SSC# 1 2
3 R452 475_0402_1% 15mil R126 49.9_0402_1% 3

22 C LK_SRC7 R113 1 2 33_0402_5% CLK_EZ_CLK1 CLK_DREF_96M 1 2

PCIEXT2 CLK_EZ_CLK1 <38>
R137 49.9_0402_1%
23 CLK_SRC7# R109 1 2 33_0402_5% CLK_EZ_CLK1# CLK_DREF_96M# 1 2
+3VS PCIEXC2 CLK_EZ_CLK1# <38>
R132 49.9_0402_1%
R462 CLK_EZ_CLK2 1 2
4.7K_0402_5% 19 C LK_SRC1 R121 1 2 33_0402_5% CLK_PC IE_ICH R680 49.9_0402_1%
PCIEXT1 CLK_PCIE_ICH <19>
2

CLK_EZ_CLK2#
G

1 2 +3VS 1 2
20 CLK_SRC1# R117 1 2 33_0402_5% CLK_P CIE_ICH# R681 49.9_0402_1%
PCIEXC1 CLK_PCIE_ICH# <19>
1 3 D_CK_SCLK 13
<19> CK_SCLK GND_0
D

Q16 29 17 C LK_SRC0 R129 1 2 33_0402_5% CL K_DREF_SSC

GND_1 LCDCLK_SS/PCIEX0T CLK_DREF_SSC <6>
2N7002_SOT23
2 18 CLK_SRC0# R125 1 2 33_0402_5% C LK_DREF_SSC#
GND_2 LCDCLK_SS/PCIEX0C CLK_DREF_SSC# <6>
45 GND_3
+3VS 14 CLK_DOT R136 1 2 33_0402_5% CLK_DREF_96M
DOTT_96MHz CLK_DREF_96M <6>
R461 51 15 CLK_DOT# R131 1 2 33_0402_5% CLK_DREF_96M#
GND_4 DOTC_96MHz CLK_DREF_96M# <6>
4.7K_0402_5%
2
G

1 2 +3VS 6 GND_5
1 3 D_CK_SDATA +3VS 1 2
<19> CK_SDATA VGATE <6,19,48>
R138 10K_0402_5%
D

2
Q17

G
2N7002_SOT23
10 VTT_POWERGD# 1 3
VTT_PWRGD#/PD

S
52 C LK_REF 1 2 CLK_14M_SIO Q14
+1.05VS +1.05VS REF0 CLK_14M_SIO <32>
4
R144 12_0402_5% 2N7002_SOT23 4

ICS954226AGT_TSSOP56 1 2 CLK_ICH_14M
CLK_ICH_14M <19>
2

R456 R454 R148 12_0402_5%

@ 1K_0402_5% @ 1K_0402_5%

R460 R457 R453 R450

4.7K_0402_5% 0_0402_5% 4.7K_0402_5% 0_0402_5% Compal Electronics, Inc.
1

CLKSEL0 1 2 1 2 CLKSEL1 1 2 1 2 Title

MCH_CLKSEL0 <6> MCH_CLKSEL1 <6>
SCHEMATIC, M/B LA-2601
1 2 2 1 CPU_BSEL0 <5> 1 2 2 1 CPU_BSEL1 <5> THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
R458 R459 R451 R448 Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
@ 0_0402_5% 0_0402_5% @ 0_0402_5% 0_0402_5% 401336 C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 14 of 51
A B C D E F G H
 A B C D E

CRT Connector D23 D22

@ DAN217_SC59 @ DAN217_SC59
+5VS +R_CRT_VCC
W=40mils
+CRT_VCC

D1 W=40mils

1
2 1 F1
+5VS
RB411D_SOT23 POLYSW ITCH_1A
1
1 2 0.1U_0402_16V4Z D21
C18 @ DAN217_SC59 C4

3
U4 0.1U_0402_16V4Z
2
VCC 16 +3VS
DOCKIN# 1
<22,27,33,38> DOCKIN# SEL
1 15 2 D_ CRT_R 1
OE# 1B1 D_CRT_G D_CRT_R <38>
2B1 5 D_CRT_G <38>
11 D_CRT_B JP1
CRT_R_1 3B1 D_CRT_B <38> CRT-15P
4 1A 4B1 14
R34 1 2 PM@ 0_0402_5% CRT_G_1 7 C RT_R 1 2 CRT_R_L 6
<16> VGA_CRT_R 2A
1 2 CRT_B_1 9 L3 11
<8> GMCH_CRT_R 3A
R33 GM@ 0_0402_5% 12 3 FCM2012C-800_0805 1
R32 4A 1B2
<16> VGA_CRT_G 1 2 PM@ 0_0402_5%
2B2 6 CRT_G 1 2 CRT_G_L 7
1 2 10 L4 12
<8> GMCH_CRT_G 3B2
R21 GM@ 0_0402_5% 13 FCM2012C-800_0805 2
R19 4B2
<16> VGA_CRT_B 1 2 PM@ 0_0402_5% 8 GND
CRT_B 1 2 CRT_B_L 8
1 2 L5 13
<8> GMCH_CRT_B
R18 GM@ 0_0402_5% FSAV330MTC_TSSOP16 FCM2012C-800_0805 3

1
1 1 1 1 1 DDC_MD2 9
R1 R2 R3 C9 C8 C7 1 14
C1 C2 C3 4
8P_0402_50V8K 8P_0402_50V8K 10
150_0402_5% 150_0402_5% 150_0402_5% 2 8P_0402_50V8K 2 8P_0402_50V8K 2 2 2
15

2
8P_0402_50V8K 2 C408 5
10P for GMCH 8P_0402_50V8K
100P_0402_25V8K
+CRT_VCC H S YNC_L
1 2 (CL55)
L1 FCM1608C-121T_0603
1 2 2 1 DSUB_12
C10 0.1U_0402_16V4Z R6 10K_0402_5% 1 2 VSYNC_L
L2 FCM1608C-121T_0603 1

5
1
1 1

OE#
P
1 2 C RT_HSYNC 2 4 D_CRT_HSYNC C6
<16> VGA_CRT_HSYNC A Y
2 R8 PM@ 0_0402_5% C5 C409 2 2

G
1 2 U1 10P_0402_50V8J 10P_0402_50V8J 68P_0402_50V8K DSUB_15
<8> GMCH_CRT_HSYNC 2 2
R7 GM@ 39_0402_5% SN74AHCT1G125GW_SOT353-5

3
+CRT_VCC 33P for GMCH 1
C407
1 2 68P_0402_50V8K
C410 0.1U_0402_16V4Z 2
D_CRT_HSYNC <38>

5
1
OE#
P
1 2 CRT_VS YNC 2 4 D_CRT_V SYNC
<16> VGA_CRT_VSYNC A Y D_CRT_VSYNC <38>
R377 PM@ 0_0402_5%

G
1 2 U35
<8> GMCH_CRT_VSYNC
R378 GM@ 39_0402_5% SN74AHCT1G125GW_SOT353-5

3
3 CRT_R_1 R712 1 +CRT_VCC 3
2 2@0_0402_5% C RT_R
R9 1 2 PM@ 0_0402_5% +3VS
CRT_G_1 R713 1 2 2@0_0402_5% CRT_G

CRT_B_1 R714 1 2 2@0_0402_5% CRT_B R10 1 2 GM@ 0_0402_5% +2.5VS

1
R4 R11 GM@ 0_0402_5%
4.7K_0402_5% R5 2 1
GMCH_CRT_DATA <8>

2
G
4.7K_0402_5%
DSUB_12 1 3 VGA_DDC_DATA
<38> D_DDC_DATA VGA_DDC_DATA <16>

S
Q1

2
BSS138_SOT23

G
DSUB_15 1 3 V GA_DDC_CLK
<38> D_DDC_CLK VGA_DDC_CLK <16>

S
Q2
BSS138_SOT23
2 1 GMCH_CRT_CLK <8>
R12
GM@ 0_0402_5%

4 4

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401336
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 15 51
D ate: ¬P 期四, 三月 17, 2005 Sheet of
A B C D E
 5 4 3 2 1

LCD POWER CIRCUIT B+ PCEI_GTX_C_MRX_N[0..15]

<8> PCEI_GTX_C_MRX_N[0..15]
GM CH_ENVDD PCEI_GTX_C_MRX_P[0..15]
<8> GMCH_ENVDD <8> PCEI_GTX_C_MRX_P[0..15]
@ 0.1U_0402_25V4K @ 0.1U_0402_25V4K @ 0.1U_0402_25V4K
PCIE_MTX_C_GRX_N[0..15]
<8> PCIE_MTX_C_GRX_N[0..15]
+3VALW 1 1 1 1 1
U33 PCIE_MTX_C_GRX_P[0..15]
<8> PCIE_MTX_C_GRX_P[0..15]

5
1
GM@ SN74AHCT1G125GW_SOT353-5 C866 C867 C868 C869 C870

OE#
P
2 2 2 2 2
2 A Y 4
1

G
+LCDVDD C860 @ 0.1U_0402_25V4K @ 0.1U_0402_25V4K
D
VGA BOARD Conn. D

2
3
GM@ 0.01U_0402_16V7K
1

2
R53 R62 Bypass CAP under B+ trace(+25V) JP11
+3VS
B+ B+

1
GM@ 301_0402_1% 1 2
GM@ 100_0402_5% 3 4
1 2

5 6
7 8

3
D DAC_B RIG V GA_DDC_CLK
9 10 VGA_DDC_CLK <15>
Q8 2 2 Q9 DISP OFF# VGA_DDC_DATA VGA_DDC_DATA <15>
GM@ 2N7002_SOT23 G GM@ SI2301DS_SOT23 INVT_PWM 11 12
13 14 VGA_TV_LUMA
S 1 VGA_TV_LUMA <22>
3

15 16
2

+LCDVDD VGA_CRT_R
<15> VGA_CRT_R 17 18 VGA_TV_CRMA VGA_TV_CRMA <22>

1
R55 C27 VGA_CRT_G 19 20
2 <15> VGA_CRT_G 21 22 VGA_TV_COMPS VGA_TV_COMPS <22>
GM@ 100K_0402_5% GM@ 0.047U_0402_16V7K VGA_CRT_B 23 24 VGA_C RT_HSYNC
1 1 <15> VGA_CRT_B VGA_CRT_HSYNC <15>
1

C28 C29 25 26 SUSP#

27 28 SUSP# <33,35,40,47>
+3VALW VGA _CRT_VSYNC VGA_CRT_VSYNC <15>
GM@ 4.7U_0805_10V4Z GM@ 0.1U_0402_16V4Z 29 30
2 2 31 32
+2.5VS 33 34 +1.5VS
35 36 DVI_DET <22>
<22> DVI_TXC+ 37 38 DVI_SCLK <22>
<22> DVI_TXC- 39 40 DVI_SDATA <22>
41 42
<22> DVI_TXD0+ 43 44 +3VS
<22> DVI_TXD0- 45 46
47 48 +5VS
C C
+3VS <22> DVI_TXD1+ 49 50
<22> DVI_TXD1- 51 52
53 54 +5VALW
<22> DVI_TXD2+ 55 56
1 SDVO_SCLK SDVO_SCLK <8>
<22> DVI_TXD2- 57 58 SDVO_SDAT SDVO_SDAT <8>
C19 R510 1DVI@ 2 0_0402_5% 59 60
<19> PLTRST_VGA# 61 62 CLK_PCIE_VGA <14>
@ 0.1U_0402_16V4Z GMCH_ENBKL CLK_PCIE_VGA# <14>
2 <8,33> GMCH_ENBKL 63 64
PCIE_MTX_C_GRX_P0 65 66 PCEI_GTX_C_MRX_P0
PCIE_MTX_C_GRX_N0 67 68 PCEI_GTX_C_MRX_N0
69 70
PCIE_MTX_C_GRX_P1 71 72 PCEI_GTX_C_MRX_P1
PCIE_MTX_C_GRX_N1 73 74 PCEI_GTX_C_MRX_N1
+3VS 75 76
PCIE_MTX_C_GRX_P2 77 78 PCEI_GTX_C_MRX_P2
PCIE_MTX_C_GRX_N2 79 80 PCEI_GTX_C_MRX_N2
81 82
1

R477 PCIE_MTX_C_GRX_P3 83 84 PCEI_GTX_C_MRX_P3

PCIE_MTX_C_GRX_N3 85 86 PCEI_GTX_C_MRX_N3
4.7K_0402_5% 87 88
D32 PCIE_MTX_C_GRX_P4 89 90 PCEI_GTX_C_MRX_P4
2

BKOFF# 91 92
<33> BKOFF# 1 2 RB751V_SOD323 DISP OFF# PCIE_MTX_C_GRX_N4
93 94
PCEI_GTX_C_MRX_N4

PCIE_MTX_C_GRX_P5 95 96 PCEI_GTX_C_MRX_P5
PCIE_MTX_C_GRX_N5 97 98 PCEI_GTX_C_MRX_N5
99 100
PCIE_MTX_C_GRX_P6 101 102 PCEI_GTX_C_MRX_P6
PCIE_MTX_C_GRX_N6 103 104 PCEI_GTX_C_MRX_N6
B 105 106 B
PCIE_MTX_C_GRX_P7 107 108 PCEI_GTX_C_MRX_P7
PCIE_MTX_C_GRX_N7 109 110 PCEI_GTX_C_MRX_N7
111 112
PCIE_MTX_C_GRX_P8 113 114 PCEI_GTX_C_MRX_P8
PCIE_MTX_C_GRX_N8 115 116 PCEI_GTX_C_MRX_N8
LCD/PANEL BD. Conn. PCIE_MTX_C_GRX_P9
117
119
118
120 PCEI_GTX_C_MRX_P9
PCIE_MTX_C_GRX_N9 121 122 PCEI_GTX_C_MRX_N9
JP6 123 124
DAC_B RIG PCIE_MTX_C_GRX_P10 125 126 PCEI_GTX_C_MRX_P10
B+ 1 1 2 2 DAC_BRIG <33> 127 128
3 4 INVT_PWM PCIE_MTX_C_GRX_N10 PCEI_GTX_C_MRX_N10
3 4 INVT_PWM <33> 129 130
5 6 DISP OFF#
5 6 PCIE_MTX_C_GRX_P11 131 132 PCEI_GTX_C_MRX_P11
+3VS 7 7 8 8 133 134
<8> GMCH_LCD_CLK GMCH_LCD_CLK 9 10 +LCDVDD PCIE_MTX_C_GRX_N11 PCEI_GTX_C_MRX_N11
GMCH_LCD_DATA 9 10 135 136
<8> GMCH_LCD_DATA 11 11 12 12 137 138
13 14 PCIE_MTX_C_GRX_P12 PCEI_GTX_C_MRX_P12
GMCH_TZOUT0- 13 14 GMCH_TXOUT0- PCIE_MTX_C_GRX_N12 139 140 PCEI_GTX_C_MRX_N12
<8> GMCH_TZOUT0- 15 15 16 16 GMCH_TXOUT0- <8> 141 142
GMCH_TZOUT0+ 17 18 GMCH_TXOUT0+
<8> GMCH_TZOUT0+ 17 18 GMCH_TXOUT0+ <8> 143 144
19 20 PCIE_MTX_C_GRX_P13 PCEI_GTX_C_MRX_P13
GMCH_TZOUT1+ 19 20 GMCH_TXOUT1- PCIE_MTX_C_GRX_N13 145 146 PCEI_GTX_C_MRX_N13
<8> GMCH_TZOUT1+ 21 21 22 22 GMCH_TXOUT1- <8> 147 148
GMCH_TZOUT1- 23 24 GMCH_TXOUT1+
<8> GMCH_TZOUT1- 23 24 GMCH_TXOUT1+ <8> 149 150
GMCH_TZOUT2+ 25 26 GMCH_TXOUT2+ PCIE_MTX_C_GRX_P14 PCEI_GTX_C_MRX_P14
<8> GMCH_TZOUT2+ 25 26 GMCH_TXOUT2+ <8> 151 152
GMCH_TZOUT2- 27 28 GMCH_TXOUT2- PCIE_MTX_C_GRX_N14 PCEI_GTX_C_MRX_N14
<8> GMCH_TZOUT2- 27 28 GMCH_TXOUT2- <8> 153 154
29 29 30 30 155 156
GMCH_TZCLK- 31 32 GMCH_TXCLK- PCIE_MTX_C_GRX_P15 PCEI_GTX_C_MRX_P15
<8> GMCH_TZCLK- 31 32 GMCH_TXCLK- <8> 157 158
GMCH_TZCLK+ 33 34 GMCH_TXCLK+ PCIE_MTX_C_GRX_N15 PCEI_GTX_C_MRX_N15
<8> GMCH_TZCLK+ 33 34 GMCH_TXCLK+ <8> 159 160
35 35 36 36
A 37 38 DVI@ ACES_88081-1600 A
37 38
39 39 40 40

GM@ ACES_87216-4012

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-2601
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401336 C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 16 of 51
5 4 3 2 1
 5 4 3 2 1

RP89
1 8 PCI_SERR#
+3VS
2 7 PCI_TRD Y#
3 6 P CI_FRAME#
D 4 5 PCI_STOP# U17B D
<23,25,26,28> PCI_AD[0..31]
PCI_AD0 E2 L5 P CI_REQ#0 Internal Pull-up.
AD[0] REQ[0]# PCI_REQ#0 <25>
8.2K_0804_8P4R_5% PCI_AD1 E5 C1 PCI_GNT#0
PCI_AD2 C2
AD[1] PCI GNT[0]#
B5 P CI_REQ#1
PCI_GNT#0 <25> Sample high destination is LPC.
AD[2] REQ[1]# PCI_REQ#1 <28>
PCI_AD3 F5 B6 PCI_GNT#1
AD[3] GNT[1]# PCI_GNT#1 <28>
PCI_AD4 F3 M5 P CI_REQ#2 PCI_GNT#5
AD[4] REQ[2]# PCI_REQ#2 <23>
RP88 PCI_AD5 E9 F1 PCI_GNT#2
AD[5] GNT[2]# PCI_GNT#2 <23>
1 8 PCI_PLOCK# PCI_AD6 F2 B8 P CI_REQ#3
+3VS AD[6] REQ[3]# PCI_REQ#3 <26>

1
2 7 P C I_ I RDY# PCI_AD7 D6 C8 PCI_GNT#3
AD[7] GNT[3]# PCI_GNT#3 <26>
3 6 PCI_PERR# PCI_AD8 E6 F7 P CI_REQ#4 R231
PCI_DEVSEL# PCI_AD9 AD[8] REQ[4]#/GPI[40] @ 0_0402_5%
4 5 D3 AD[9] GNT[4]#/GPO[48] E7
PC I_AD10 A2 E8 D_USB_SMI#1
AD[10] REQ[5]#/GPI[1] D_USB_SMI#1 <38>
8.2K_0804_8P4R_5% PC I_AD11 D2 F6 PCI_GNT#5

2
PC I_AD12 AD[11] GNT[5]#/GPO[17] D_USB_SMI#2
D5 AD[12] REQ[6]#/GPI[0] B7 D_USB_SMI#2 <38>
PC I_AD13 H3 D8
PC I_AD14 AD[13] GNT[6]#/GPO[16]
B4 AD[14]
RP91 PC I_AD15 J5 J6 P CI_CBE#0 PCI_C/BE#0 <23,25,26,28>
PCI_PIRQD# PC I_AD16 AD[15] C/BE[0]# P CI_CBE#1
+3VS 1 8 K2 AD[16] C/BE[1]# H6 PCI_C/BE#1 <23,25,26,28>
2 7 PCI_ PIRQB# PC I_AD17 K5 G4 P CI_CBE#2
AD[17] C/BE[2]# PCI_C/BE#2 <23,25,26,28>
3 6 PCI_PIRQC# PC I_AD18 D4 G2 P CI_CBE#3
AD[18] C/BE[3]# PCI_C/BE#3 <23,25,26,28>
4 5 PCI_ PIRQA# PC I_AD19 L6
PC I_AD20 AD[19] P C I_ I RDY#
G3 AD[20] IRDY# A3 P C I_ IRDY# <23,25,26,28>
8.2K_0804_8P4R_5% PC I_AD21 H4 E1 PCI_PAR
PC I_AD22 AD[21] PAR PCI_RST# PCI_PAR <23,25,26,28>
H2 AD[22] PCIRST# R2 PCI_RST# <23,25,26,28,32,33>
PC I_AD23 H5 C3 PCI_DEVSEL#
RP92 PC I_AD24 AD[23] DEVSEL# PCI_PERR# PCI_DEVSEL# <23,25,26,28>
B3 AD[24] PERR# E3 PCI_PERR# <23,25,26,28>
1 8 PCI_ PIRQE# PC I_AD25 M6 C5 PCI_PLOCK#
+3VS AD[25] PLOCK#
2 7 PCI_PIRQF# PC I_AD26 B2 G5 PCI_SERR#
AD[26] SERR# PCI_SERR# <23,25,26,28>
3 6 D_USB_SMI#2 PC I_AD27 K6 J1 PCI_STOP#
AD[27] STOP# PCI_STOP# <23,25,26,28>
C 4 5 PCI_ PIRQG# PC I_AD28 K3 J2 PCI_TRD Y# C
AD[28] TRDY# PCI_TRDY# <23,25,26,28>
PC I_AD29 A5
8.2K_0804_8P4R_5% PC I_AD30 AD[29]
L1 AD[30]
PC I_AD31 K4 AD[31] PLT_RST#
PLTRST# R5 PLT_RST# <6,19,21,32,33>
RP87 G6 CLK_ICH _PCI CLK_PCI_ICH
PCICLK CLK_PCI_ICH <14>
1 8 P CI_REQ#3 P CI_FRAME# J3 P6
+3VS <23,25,26,28> PCI_FRAME# FRAME# PME#
2 7 D_USB_SMI#1

2
3 6 P CI_REQ#4 Interrupt I/F
4 5 P CI_REQ#1 PCI_ PIRQA# N2 D9 PCI_ PIRQE#
<23> PCI_PIRQA# PIRQ[A]# PIRQ[E]#/GPI[2] PCI_PIRQE# <25>
PCI_ PIRQB# L2 C7 PCI_PIRQF# R177
<23> PCI_PIRQB# PIRQ[B]# PIRQ[F]#/GPI[3] PCI_PIRQF# <26>
8.2K_0804_8P4R_5% PCI_PIRQC# M1 C6 PCI_ PIRQG# @ 10_0402_5%
PIRQ[C]# PIRQ[G]#GPI[4] PCI_PIRQG# <28>
PCI_PIRQD# L3 M3 PCI_PIRQH#
PCI_PIRQH# <28>

1
PIRQ[D]# PIRQ[H]#/GPI[5]

RP90 AC5
RESERVED 1
C192
SATA[1]RXN/RSVD[1] @ 10P_0402_50V8J
+3VS 1 8 AD5 SATA[1]RXP/RSVD[2]
2 7 P CI_REQ#0 AF4
P CI_REQ#2 SATA[1]TXN/RSVD[3] 2
3 6 AG4 SATA[1]TXP/RSVD[4]
4 5 PCI_PIRQH# AC9 SATA[3]RXN/RSVD[5]
AD9 SATA[3]RXP/RSVD[6]
8.2K_0804_8P4R_5% AF8 SATA[3]TXN/RSVD[7]
AG8 SATA[3]TXP/RSVD[8]
U3 TP[3]/RSVD[9]
ICH6_BGA609

B B

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-2601
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401336
D ate: ¬P 期四, 三月 17, 2005 Sheet 17 of 51
5 4 3 2 1
 5 4 3 2 1

C269
12P_0402_50V8J
2 1 ICH_RTCX1
+RTCVCC

10M_0402_5%
Y3

1
3 NC OUT 4
1

R246
R244 32.768KHZ_12.5P_1TJS125DJ2A073 2 1
NC IN U17A
1M_0402_1% C270 +1.05VS

2
D 12P_0402_50V8J Y1 P2 LPC_LAD0 D
LPC_AD0 <32,33>
2

RTCX1 LAD[0]/FWH[0]

RTC
2 1 ICH_RTCX2 Y2 N3 LPC_LAD1
RTCX2 LAD[1]/FWH[1] LPC_AD1 <32,33>
INTRUD ER# N5 LPC_LAD2
LAD[2]/FWH[2] LPC_AD2 <32,33>
1 2 IC H_RTCRST# AA2 N4 LPC_LAD3 H_FE RR# 1 2

LPC
+RTCVCC RTCRST# LAD[3]/FWH[3] LPC_AD3 <32,33>
R439 R186 56_0402_5%
20K_0402_5% INTRUD ER# AA3 N6 H_DPRSTP# 1 2
INTRUDER# LDRQ[0]# LPC_DRQ#1 R176 @ 56_0402_5%
AA5 INTVRMEN LDRQ[1]#/GPI[41] P4 LPC_DRQ#1 <32>
2 1 P3 LPC_FRAME#
LFRAME#/FWH[4] LPC_FRAME# <32,33>
close to RAM door J1 JOPEN D12
+3VS EE_CS R190 1
B12 EE_SHCLK 2 10K_0402_5% +3VS
D11 AF22 EC_GA20
EE_DOUT A20GATE EC_GA20 <33>
C271 F13 AF23 H_A20M#
EE_DIN A20M# H_A20M# <4>
1

1U_0402_6.3V4Z

LAN
R706 R520 1 @ 0_0402_5% H_CPUSLP#

CPU
1 2 F12 LAN_CLK CPUSLP# AE27 2 H_CPUSLP# <4,6>
10K_0402_5% B11 AE24 R180 1 2 @ 0_0402_5% H_DPRSTP# H_DPRSTP# <4>
LAN_RSTSYNC DPRSLP#/TP[4]
AD27 H_DPSLP# <4>
2

DPSLP#/TP[2]
E12 LANRXD[0]
E11 AF24 R696 1 2 56_0402_5% H_FE RR# H_FERR# <4>
PH DD_LED# LANRXD[1] FERR#
C13 LANRXD[2]
AG25 H_PW RGOOD H_PW RGOOD <4>
CPUPWRGD/GPO[49] MAINPW ON <42,45,49>
C12 LANTXD[0]
C11 AG26 H_IG NNE# H_IGNNE# <4> R181
LANTXD[1] IGNNE#

1
C224 R207 E13 AE22 @ 330_0402_5% C
@ 10P_0402_50V8J @ 10_0402_5% LANTXD[2] INIT3_3V# H_IN IT# Q22
INIT# AF27 H_INIT# <4> +1.05VS 1 2 2
1 2 2 1 AG24 H_IN TR R188 B @ 2SC2411K_SC59
INTR H_INTR <4>
10K_0402_5% E

3
AC97_BITCLK C10 1 2 +3VS
<29,34> ICH_AC_BITCLK ACZ_BIT_CLK

AC-97/AZALIA
C
<29,34> IC H _AC_SYNC 2 1 AC97_S YNC_R B9 AD23 KB_RST# C
ACZ_SYNC RCIN# EC_KBRST# <33>
R215 33_0402_5%
1 2 AC97_RST_R# A10 AF25 H_N MI H_NMI <4> +1.05VS 1 2 2 1 THRMTRIP#
<29,34> ICH_AC_RST# ACZ_RST# NMI
R210 33_0402_5% AG27 H_SMI# H_SMI# <4> R182 75_0402_1% R187
AC_S DIN0 SMI# 56_0402_5%
<29> ICH_AC_SDIN0 F11 ACZ_SDIN[0]
<34> ICH_AC_SDIN1 F10 AE26 H_STPCLK# H_STPCLK# <4>
ACZ_SDIN[1] STPCLK# H_THERMTRIP#
B10 ACZ_SDIN[2] H_THERMTRIP# <4,6>
AE23 THRMTRIP#
AC97_SDOUT_R THRMTRIP#
<29,34> ICH_AC_SDOUT 2 1 C9 ACZ_SDO
R206 33_0402_5% IDE_DA[0..2] <21>
AC16 IDE _DA0
PH DD_LED# DA[0] IDE _DA1
<33> PHDD_LED# AC19 SATALED# DA[1] AB17
AC17 IDE _DA2
DA[2]
SATA_DTX_IRX_N0 AE3 AD16 IDE _DCS1# IDE_DCS1# <21>
SATA_DTX_IRX_P0 SATA[0]RXN DCS1# IDE _DCS3#
AD3 SATA[0]RXP DCS3# AE17 IDE_DCS3# <21>
SATA_ITX_DRX_N0 AG2
SATA_ITX_DRX_P0 SATA[0]TXN
AF2 SATA[0]TXP IDE_DD[0..15] <21>
AD14 IDE_D D0
DD[0]

SATA
SATA_DTX_C_IRX_N2 AD7 AF15 IDE_D D1
<21> SATA_DTX_C_IRX_N2 SATA[2]RXN DD[1]

PIDE
SATA_DTX_C_IRX_P2 AC7 AF14 IDE_D D2
<21> SATA_DTX_C_IRX_P2 SATA_ITX_DRX_N2 SATA[2]RXP DD[2] IDE_D D3
AF6 SATA[2]TXN DD[3] AD12
SATA_ITX_DRX_P2 AG6 AE14 IDE_D D4
SATA[2]TXP DD[4] IDE_D D5
DD[5] AC11
CLK_PCIE_SATA# AC2 AD11 IDE_D D6
<14> CLK_PCIE_SATA# CLK_PCIE_SATA AC1 SATA_CLKN DD[6] IDE_D D7
<14> CLK_PCIE_SATA SATA_CLKP DD[7] AB11
AE13 IDE_D D8
DD[8] IDE_D D9
AG11 SATARBIAS# DD[9] AF13
R209 1 2 24.9_0402_1% SATARBIAS AF11 AB12 IDE_ DD10
B SATARBIAS DD[10] IDE_ DD11 B
DD[11] AB13
AC13 IDE_ DD12
DD[12] IDE_ DD13
DD[13] AE15
R201 1 2 4.7K_0402_5% ID E _ D I ORDY AG15 IDE_ DD14
+3VS DD[14]
ID E _ D I ORDY AF16 AD13 IDE_ DD15
<21> ID E _ D IORDY IORDY DD[15]
I DE_IRQ AB16
<21> IDE_IRQ IDEIRQ
R203 1 2 8.2K_0402_5% I DE_IRQ IDE_D DACK# AB15
<21> IDE_DDACK# DDACK#
IDE_ DIOW # AC14 AB14 IDE_DD REQ
<21> IDE_DIOW # DIOW# DDREQ IDE_DDREQ <21>
IDE_DIO R# AE16
<21> IDE_DIOR# DIOR#

ICH6_BGA609

Place near ICH6 side.

SATA_DTX_IRX_N0 2 1 SATA_DTX_C_IRX_N0
C845 @ 0.01U_0402_16V7K SATA_DTX_C_IRX_N0 <36>

SATA_DTX_IRX_P0 2 1 SATA_DTX_C_IRX_P0
C846 @ 0.01U_0402_16V7K SATA_DTX_C_IRX_P0 <36>

SATA_ITX_DRX_N0 2 1 SATA_ITX_C_DRX_N0
C256 @ 0.01U_0402_16V7K SATA_ITX_C_DRX_N0 <36>

SATA_ITX_DRX_P0 2 1 SATA_ITX_C_DRX_P0
C257 @ 0.01U_0402_16V7K SATA_ITX_C_DRX_P0 <36>

A A

SATA_ITX_DRX_N2 2 1 SATA_ITX_C_DRX_N2
C847 0.01U_0402_16V7K SATA_ITX_C_DRX_N2 <21>

SATA_ITX_DRX_P2 2 1 SATA_ITX_C_DRX_P2
C848 0.01U_0402_16V7K SATA_ITX_C_DRX_P2 <21>
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-2601
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401336
D ate: ¬P 期四, 三月 17, 2005 Sheet 18 of 51
5 4 3 2 1
 5 4 3 2 1

+3VALW
U17C
1 2 ICH _SMLINK0 EC_SW I# T2 H25 EZ_PCIE_RXN1
<33> EC_SW I# RI# PERn[1] EZ_PCIE_RXN1 <38>
R259 10K_0402_5% H24 EZ_PCIE_RXP1
PERp[1] EZ_PCIE_RXP1 <38>
1 2 ICH _SMLINK1 GPI26 AF17 G27 EZ_PCIE_C_TXN1 C791 1 2 1@ 0.1U_0402_16V4Z EZ_PCIE_TXN1
SATA[0]GP/GPI[26] PETn[1] EZ_PCIE_TXN1 <38>
R257 10K_0402_5% GPI27 AE18 G26 EZ_PCIE_C_TXP1 1 2 EZ_PCIE_TXP1
SATA[1]GP/GPI[29] PETp[1] EZ_PCIE_TXP1 <38>
1 2 CK_SCLK GPI28 AF18 C792 1@ 0.1U_0402_16V4Z
R464 2.2K_0402_5% GPI29 SATA[2]GP/GPI[30] EZ_PCIE_RXN2
AG18 SATA[3]GP/GPI[31] PERn[2] K25 EZ_PCIE_RXN2 <38>
1 2 CK_SDATA K24 EZ_PCIE_RXP2
PERp[2] EZ_PCIE_RXP2 <38>
D R465 2.2K_0402_5% CK_SCLK Y4 J27 EZ_PCIE_C_TXN2 C793 1 2 1@ 0.1U_0402_16V4Z EZ_PCIE_TXN2 D
<14> CK_SCLK SMBCLK PETn[2] EZ_PCIE_TXN2 <38>

PCI-EXPRESS
1 2 LINKALERT# CK_SDATA W5 J26 EZ_PCIE_C_TXP2 1 2 EZ_PCIE_TXP2
<14> CK_SDATA SMBDATA PETp[2] EZ_PCIE_TXP2 <38>
R260 10K_0402_5% LINKALERT# Y5 C794 1@ 0.1U_0402_16V4Z
EC_LID_OUT# ICH _SMLINK0 LINKALERT#
1 2 W4 SMLINK[0] PERn[3] M25

GPIO
R255 10K_0402_5% ICH _SMLINK1 U6 M24
EC_SW I# MCH_SYN C# SMLINK[1] PERp[3]
1 2 AG21 MCH_SYNC# PETn[3] L27
R256 10K_0402_5% SB_SPKR F8 L26
PM_BATLOW# <29> SB_SPKR SPKR PETp[3]
1 2
R249 8.2K_0402_5% W3 P24
<35> SUS_STAT# SUS_STAT#/LPCPD# PERn[4]
1 2 PE_WAKE# P23
R258 1K_0402_5% S YSRST# PERp[4] +3VALW
U2 SYS_RESET# PETn[4] N27
1 2 S YSRST# N26
R261 10K_0402_5% PM_BMBUSY# PETp[4]
<6> PM_BMBUSY# AD19 BM_BUSY#/GPI[6]
T25 DMI_MTX_IRX_N0 RP83
DMI[0]RXN DMI_MTX_IRX_N0 <6>
D39 1 2 ICH_GP I7 AE19 T24 DMI_MTX_IRX_P0 USB_OC#5 4 5
<33,38> EZ_PE_REQ2# GPI[7] DMI[0]RXP DMI_MTX_IRX_P0 <6>
RB751V_SOD323 <33> EC_SMI# EC_SMI# R1 R27 DMI_ITX_MRX_N0 USB_OC#4 3 6
GPI[8] DMI[0]TXN DMI_ITX_MRX_N0 <6>
R26 DMI_ITX_MRX_P0 USB_OC#6 2 7
DMI[0]TXP DMI_ITX_MRX_P0 <6>

DIRECT MEDIA INTERFACE

A C IN W6 USB_OC#7 1 8
<33,42,45> A C IN SMBALERT#/GPI[11]
V25 DMI_MTX_IRX_N1
DMI[1]RXN DMI_MTX_IRX_N1 <6>
D35 1 2 RB751V_SOD323 LID_OUT# M2 V24 DMI_MTX_IRX_P1 10K_1206_8P4R_5%
<33> EC_LID_OUT# GPI[12] DMI[1]RXP DMI_MTX_IRX_P1 <6>
EC_ SCI# R6 U27 DMI_ITX_MRX_N1
<33> EC_SCI# GPI[13] DMI[1]TXN DMI_ITX_MRX_N1 <6>
U26 DMI_ITX_MRX_P1
DMI[1]TXP DMI_ITX_MRX_P1 <6>
PM_STP_PCI# AC21
<14> PM_STP_PCI# STP_PCI#/GPO[18]
R711 2 1 @ 0_0402_5% Y25 DMI_MTX_IRX_N2 RP82
DMI[2]RXN DMI_MTX_IRX_N2 <6>
AB21 Y24 DMI_MTX_IRX_P2 USB_OC#3 4 5
<35> SB_INT_FLASH_SEL# GPO[19] DMI[2]RXP DMI_MTX_IRX_P2 <6>
W27 DMI_ITX_MRX_N2 USB_OC#0 3 6
DMI[2]TXN DMI_ITX_MRX_N2 <6>
PM_STP_CPU# AD22 W26 DMI_ITX_MRX_P2 USB_OC#1 2 7
<14,48> PM_STP_CPU# STP_CPU#/GPO[20] DMI[2]TXP DMI_ITX_MRX_P2 <6>
USB_OC#2 1 8
AB24 DMI_MTX_IRX_N3
DMI[3]RXN DMI_MTX_IRX_N3 <6>
C AD20 AB23 DMI_MTX_IRX_P3 10K_1206_8P4R_5% C
GPO[21] DMI[3]RXP DMI_MTX_IRX_P3 <6>
PLTRST_VGA# AD21 AA27 DMI_ITX_MRX_N3
+3VS <16> PLTRST_VGA# GPO[23] DMI[3]TXN DMI_ITX_MRX_N3 <6>
AA26 DMI_ITX_MRX_P3
DMI[3]TXP DMI_ITX_MRX_P3 <6>
IDE_HRESET# V3
<21> IDE_HRESET# GPIO[24]
1 2 ICH_GP I7 AD25 CLK_P CIE_ICH#
DMI_CLKN CLK_PCIE_ICH# <14>
R197 10K_0402_5% P5 AC25 CLK_PC IE_ICH
GPIO[25] DMI_CLKP CLK_PCIE_ICH <14>
1 2 PM_CLKRUN# SATA_DET# R3
<36> SATA_DET# GPIO[27]
R196 8.2K_0402_5% <35> EC_FLASH# EC_FLASH# T3
ICH_VGATE PM_CLKRUN# GPIO[28]
1 2 <25,26,28,32,33> PM_CLKRUN# AF19 CLKRUN#/GPIO[32] DMI_ZCOMP F24
R193 10K_0402_5% CD_ DK_ON AF20
<21> CD_DK_ON GPIO[33]
1 2 MCH_SYN C# <21> SIDE_RSET# SIDE_RSET# AC18 F23 DMI_IRCOMP R472 1 2 24.9_0402_1% +1.5VS
R195 10K_0402_5% GPIO[34] DMI_IRCOMP
1 2 SERIRQ PE_WAKE# R676 2 1 0_0402_5% U5 C23 USB_OC#4
WAKE# OC[4]#/GPI[9] USB_OC#4 <37>
R198 10K_0402_5% D23 USB_OC#5
LID_OUT# SERIRQ OC[5]#/GPI[10] USB_OC#6
1 2 <23,32,33> SERIRQ AB20 SERIRQ OC[6]#/GPI[14] C25 USB_OC#6 <37>
R60 10K_0402_5% C24 USB_OC#7
EC_THERM# OC[7]#/GPI[15]
<33> EC_THERM# AC20 THRM#
C27 USB_OC#0
OC[0]# USB_OC#0 <37>
1 2 SYS_PW ROK 2 1 ICH_VGATE AF21 B27 USB_OC#1
R248 10K_0402_5% <6,14,48> VGATE R194 0_0402_5% VRMPWRGD OC[1]# USB_OC#2
OC[2]# B26 USB_OC#2 <37>
1 2 EC_RSMRST# CLK_14M_ICH E10 C26 USB_OC#3
R262 10K_0402_5% CLK14 OC[3]#

CLOCK
CLK_48M_ICH A27 C21 USB20_N0
CLK48 USBP[0]N USB20_N0 <37>
RP85 D21 USB20_P0
USBP[0]P USB20_P0 <37>
4 5 GPI29 RTC_CLK V6 A20
GPI28 <33> RTC_CLK SUSCLK USBP[1]N
3 6 USBP[1]P B20
2 7 GPI27 SLP_S3# T4 D19 USB20_N2
<33> PM_SLP_S3# SLP_S3# USBP[2]N USB20_N2 <37>
1 8 GPI26 SLP_S4# T5 C19 USB20_P2
SLP_S4# USBP[2]P USB20_P2 <37>

USB
SLP_S5# T6 A18
B 100_1206_8P4R_5% SLP_S5# USBP[3]N B
USBP[3]P B18
SYS_PW ROK AA1 E17 USB20_N4
<39> SYS_PW ROK PWROK USBP[4]N USB20_N4 <37>

POWER MGT
1 2 PM_DPRSLPVR D17 USB20_P4
USBP[4]P USB20_P4 <37>
R705 100K_0402_5% PM_DPRSLPVR AE20 B16 USB20_N5
<48> PM_DPRSLPVR DPRSLPVR/TP[1] USBP[5]N USB20_N5 <34>
A16 USB20_P5
USBP[5]P USB20_P5 <34>
PM_BATLOW# V2 C15 USB20_N6
BATLOW#/TP[0] USBP[6]N USB20_N6 <37>
D15 USB20_P6
USBP[6]P USB20_P6 <37>
PBTN_OUT# U1 A14
<33> PBTN_OUT# PWRBTN# USBP[7]N
USBP[7]P B14
PLT_RST# V5
<6,17,21,32,33> PLT_RST# LAN_RST# US BRBIAS
USBRBIAS# A22 1 2
EC_RSMRST# Y3 B22 R189 22.6_0402_1%
<33> EC_RSMRST# RSMRST# USBRBIAS
ICH6_BGA609

+3VALW C275
0.1U_0402_16V4Z
1 2
5

U21
1 SLP_S4#
P

CLK_48M_ICH CLK_14M_ICH IN1

<14> CLK_ICH_48M <14> CLK_ICH_14M <33> PM_SLP_S5# 4 O
2 SLP_S5#
IN2
G
1
1

A
R218 SN74AHC1G08DCKR_SC70 A
R470 @ 10_0402_5%
@ 10_0402_5%
2
2

1
1
C235
C559
2
@ 10P_0402_50V8J Compal Electronics, Inc.
@ 10P_0402_50V8J Title
2
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401336
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: ¬P 期四, 三月 17, 2005 Sheet 19 of 51
5 4 3 2 1
 5 4 3 2 1

+1.5VS
Near PIN F27(C155), +1.5VS C204
P27(C154), AB27(C157) U17E +RTCVCC 0.1U_0402_16V4Z U17D
1 2 E27 VSS[172] VSS[86] F4
+1.5VS AA22 VCC1_5[1] VCC1_5[98] F9 Y6 VSS[171] VSS[85] F22

220U_D2_4VM_R12

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 AA23 U17 0.1U_0402_16V4Z C562 Y27 F19
VCC1_5[2] VCC1_5[97] 0.1U_0402_16V4Z VSS[170] VSS[84]
2 2 2 AA24 VCC1_5[3] VCC1_5[96] U16 Y26 VSS[169] VSS[83] F17

C242
+ AA25 U14 1 2 Y23 E25
VCC1_5[4] VCC1_5[95] 2 2 VSS[168] VSS[82]

C193

C194

C561
AB25 U12 C278 W7 E19
VCC1_5[5] VCC1_5[94] C199 VSS[167] VSS[81]
AB26 VCC1_5[6] VCC1_5[93] U11 W25 VSS[166] VSS[80] E18
2 1 1 1 0.1U_0402_16V4Z
AB27 VCC1_5[7] VCC1_5[92] T17 W24 VSS[165] VSS[79] E15
D F25 T11 C2771 1
1 2 W23 E14 D
VCC1_5[8] VCC1_5[91] VSS[164] VSS[78]
F26 VCC1_5[9] VCC1_5[90] P17 W1 VSS[163] VSS[77] D7
F27 P11 0.1U_0402_16V4Z C564 V4 D22
VCC1_5[10] VCC1_5[89] 0.1U_0402_16V4Z VSS[162] VSS[76]
G22 M17 V27 D20

CORE
VCC1_5[11] VCC1_5[88] VSS[161] VSS[75]
G23 VCC1_5[12] VCC1_5[87] M11 1 2 V26 VSS[160] VSS[74] D18
G24 VCC1_5[13] VCC1_5[86] L17 V23 VSS[159] VSS[73] D14
G25 L16 C201 U25 D13
+5VS +3VS VCC1_5[14] VCC1_5[85] 0.1U_0402_16V4Z VSS[158] VSS[72]
H21 VCC1_5[15] VCC1_5[84] L14 U24 VSS[157] VSS[71] D10
H22 VCC1_5[16] VCC1_5[83] L12 1 2 U23 VSS[156] VSS[70] D1
J21 VCC1_5[17] VCC1_5[82] L11 U15 VSS[155] VSS[69] C4
2

2
J22 AA21 C200 U13 C22
R214 D10 VCC1_5[18] VCC1_5[81] 0.1U_0402_16V4Z VSS[154] VSS[68]
K21 VCC1_5[19] VCC1_5[80] AA20 T7 VSS[153] VSS[67] C20
K22 VCC1_5[20] VCC1_5[79] AA19 1 2 T27 VSS[152] VSS[66] C18

PCIE
10_0402_5% RB751V_SOD323 L21 T26 C14
VCC1_5[21] C203 VSS[151] VSS[65]
L22 T23 B25
1

VCC1_5[22] 0.1U_0402_16V4Z +3VS 0.1U_0402_16V4Z VSS[150] VSS[64]

M21 VCC1_5[23] VCC3_3[21] AA10 T16 VSS[149] VSS[63] B24
ICH_V5REF _RUN M22 AG19 1 2 T15 B23
VCC1_5[24] VCC3_3[20] VSS[148] VSS[62]
2 2 2 N21 VCC1_5[25] VCC3_3[19] AG16 T14 VSS[147] VSS[61] B21
N22 AG13 2 2 C202 T13 B19
C243 C233 VCC1_5[26] VCC3_3[18] 0.1U_0402_16V4Z VSS[146] VSS[60]
N23 VCC1_5[27] VCC3_3[17] AD17 T12 VSS[145] VSS[59] B15
1U_0603_10V4Z C237 0.1U_0402_16V4Z N24 AC15 C226 Near PIN 1 2 T1 B13
1 1 1 VCC1_5[28] VCC3_3[16] VSS[144] VSS[58]
N25 AA17 R4 AG7

IDE
0.1U_0402_16V4Z P21
VCC1_5[29] VCC3_3[15]
AA15 C2231 1 AG13, AG16 C567 R25
VSS[143] VSS[57]
AG3
VCC1_5[30] VCC3_3[14] 0.1U_0402_16V4Z VSS[142] VSS[56]
P25 VCC1_5[31] VCC3_3[13] AA14 R24 VSS[141] VSS[55] AG22
P26 VCC1_5[32] VCC3_3[12] AA12 1 2 R23 VSS[140] VSS[54] AG20
P27 0.1U_0402_16V4Z R17 AG17
VCC1_5[33] C565 VSS[139] VSS[53]
R21 VCC1_5[34] R16 VSS[138] VSS[52] AG14
R22 P1 +3VS 0.1U_0402_16V4Z R15 AG12
VCC1_5[35] VCC3_3[11] VSS[137] VSS[51]
T21 VCC1_5[36] VCC3_3[10] M7 2 2 2 1 2 R14 VSS[136] VSS[50] AG1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C T22 L7 R13 AF7 C
VCC1_5[37] VCC3_3[9] VSS[135] VSS[49]

C240

C266

C265
U21 L4 C563 R12 AF3
VCC1_5[38] VCC3_3[8] 0.01U_0402_16V7K VSS[134] VSS[48]
U22 VCC1_5[39] VCC3_3[7] J7 R11 VSS[133] VSS[47] AF26
1 1 1
V21 VCC1_5[40] VCC3_3[6] H7 1 2 P22 VSS[132] VSS[46] AF12

GROUND
PCI
V22 VCC1_5[41] VCC3_3[5] H1 P16 VSS[131] VSS[45] AF10
W21 VCC1_5[42] VCC3_3[4] E4 Near PIN A25 P15 VSS[130] VSS[44] AF1
W22 VCC1_5[43] VCC3_3[3] B1 Near PIN P14 VSS[129] VSS[43] AE7
Y21 A6 C566 P13 AE6
Y22
VCC1_5[44] VCC3_3[2] A2-A6, D1-H1 0.01U_0402_16V7K P12
VSS[128] VSS[42]
AE25
VCC1_5[45] VSS[127] VSS[41]
VCCSUS1_5[3] U7 +1.5VALW 1 2 N7 VSS[126] VSS[40] AE21
+1.5VS AA6 VCC1_5[46] VCCSUS1_5[2] R7 N17 VSS[125] VSS[39] AE2
AB4 VCC1_5[47] Near PIN AA19 N16 VSS[124] VSS[38] AE12

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
AB5 VCC1_5[48] 2 2 2 N15 VSS[123] VSS[37] AE11

USB
2 AB6 VCC1_5[49] VCCSUS1_5[1] G19 N14 VSS[122] VSS[36] AE10

C569

C570
C571
AC4 VCC1_5[50] N13 VSS[121] VSS[35] AD6
Near PIN AG5 C232 AD4 G20 N12 AD24
0.1U_0402_16V4Z VCC1_5[51] VCC1_5[78] 1 1 1 VSS[120] VSS[34]
AE4 VCC1_5[52] VCC1_5[77] F20 N11 VSS[119] VSS[33] AD2
1
AE5 VCC1_5[53] VCC1_5[76] E24 N1 VSS[118] VSS[32] AD18

SATA
AF5 VCC1_5[54] VCC1_5[75] E23 M4 VSS[117] VSS[31] AD15

USB CORE
AG5 VCC1_5[55] VCC1_5[74] E22 M27 VSS[116] VSS[30] AD10
VCC1_5[73] E21 +3VALW M26 VSS[115] VSS[29] AD1
+1.5VS AA7 VCC1_5[56] VCC1_5[72] E20 M23 VSS[114] VSS[28] AC6
AA8 D27 C574 M16 AC3
VCC1_5[57] VCC1_5[71] 0.1U_0402_16V4Z VSS[113] VSS[27]
AA9 VCC1_5[58] VCC1_5[70] D26 M15 VSS[112] VSS[26] AC26
2 AB8 VCC1_5[59] VCC1_5[69] D25 1 2 M14 VSS[111] VSS[25] AC24
AC8 VCC1_5[60] VCC1_5[68] D24 +1.5VS M13 VSS[110] VSS[24] AC23
+5VALW +3VALW C234 C573
Near PIN AG9 0.1U_0402_16V4Z
AD8 VCC1_5[61] +2.5VS 0.1U_0402_16V4Z
M12 VSS[109] VSS[23] AC22
AE8 VCC1_5[62] VCC1_5[67] G8 L25 VSS[108] VSS[22] AC12
1
AE9 VCC1_5[63] 1 2 L24 VSS[107] VSS[21] AC10
2

B B
AF9 VCC1_5[64] VCC2_5[4] AB18 L23 VSS[106] VSS[20] AB9
R191 D9 AG9 PCI/IDE RBP P7 C267 L15 AB7
VCC1_5[65] VCC2_5[2] 0.1U_0402_16V4Z VSS[105] VSS[19]
L13 VSS[104] VSS[18] AB2

0.1U_0402_16V4Z
10_0402_5% RB751V_SOD323 ICH6 _VCCPLL AC27 AA18 ICH_V5REF _RUN 2 1 2 K7 AB19
VCCDMIPLL V5REF[2] VSS[103] VSS[17]
+3VS E26 A8 K27 AB10
1

VCC3_3[1] V5REF[1] VSS[102] VSS[16]

C572
ICH_ V5REF_SUS C210 K26 AB1
ICH_ V5REF_SUS 0.1U_0402_16V4Z VSS[101] VSS[15]
2 2 +1.5VS AE1 VCCSATAPLL V5REF_SUS F21 K23 VSS[100] VSS[14] AA4
C213 1
2 +3VS AG10 VCC3_3[22] 1 2 K1 VSS[99] VSS[13] AA16
C568 Near PIN A25 +1.5VS J4 AA13
1U_0603_10V4Z 0.1U_0402_16V4Z VCCUSBPLL VSS[98] VSS[12]
1 1 C560 E26, E27
A13 VCCLAN3_3/VCCSUS3_3[1] VCCSUS3_3[20] A24 +3VALW Near PIN A24 J25 VSS[97] VSS[11] AA11
+3VS F14 VCCLAN3_3/VCCSUS3_3[2] J24 VSS[96] VSS[10] A9
0.1U_0402_16V4Z 1 G13 AB3 +RTCVCC J23 A7
VCCLAN3_3/VCCSUS3_3[3] VCCRTC VSS[95] VSS[9]
G14 VCCLAN3_3/VCCSUS3_3[4] Near PIN AB18 H27 VSS[94] VSS[8] A4
VCCLAN1_5/VCCSUS1_5[2] G11 H26 VSS[93] VSS[7] A26
+3VALW A11 VCCSUS3_3[1] VCCLAN1_5/VCCSUS1_5[1] G10 +1.5VS H23 VSS[92] VSS[6] A23
U4 VCCSUS3_3[2] G9 VSS[91] VSS[5] A21
V1 VCCSUS3_3[3] V_CPU_IO[3] AG23 G7 VSS[90] VSS[4] A19
+3VS
V7 VCCSUS3_3[4] V_CPU_IO[2] AD26 +1.05VS G21 VSS[89] VSS[3] A15
W2 AB22 C228 G12 A12
VCCSUS3_3[5] V_CPU_IO[1] 0.1U_0402_16V4Z VSS[88] VSS[2]
Y7 VCCSUS3_3[6] G1 VSS[87] VSS[1] A1

0.1U_0402_16V4Z
VCCSUS3_3[19] G16 2 1 2
+3VALW A17 VCCSUS3_3[7] VCCSUS3_3[18] G15 C212 Near PIN AG23 ICH6_BGA609
B17 VCCSUS3_3[8] VCCSUS3_3[17] F16
0.1U_0402_16V4Z

0.1U_0402_16V4Z

2 2 C17 VCCSUS3_3[9] VCCSUS3_3[16] F15

L15 R179 1 C230
F18 VCCSUS3_3[10] VCCSUS3_3[15] E16
C221

C229

CHB1608U301_0603 0.5_0603_1% G17 D16 0.1U_0402_16V4Z

VCCSUS3_3[11] VCCSUS3_3[14]
+1.5VS 1 2 ICH6_ VCCDMIPLL1 2 ICH6 _VCCPLL G18 VCCSUS3_3[12] VCCSUS3_3[13] C16 1 2
1 1
A A
2 1 ICH6_BGA609 Near PIN AG10
Near PIN A17
C195
0.1U_0402_16V4Z 1 C205 2
0.01U_0402_16V7K
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-2601
Near PIN THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AC27 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401336 C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: ¬P 期四, 三月 17, 2005 Sheet 20 of 51
5 4 3 2 1
 5 4 3 2 1

HDD CONN
+5VS

HOT CDROM CONN(DCL55) <18> IDE_DD[0..15]

IDE_DD[0..15]

1
+5VS
IDE_DA[0 ..2] R638
<18> IDE_DA[0..2] +5VS
JP49 100K_0402_5%
D 10U_0805_10V4Z 0.1U_0402_16V4Z D
+5VMOD 1 2 JP36

2
3 4
5 6 80mils 1 2 80mils 1 1 1 1
C749
7 8 +5VS 3 4 C747 C748
ID E_LED# C746
9 10 5 6 IDE_LED# <33>
IDE _DCS3# IDE _DCS1#
+3VMOD 11 12 <18> IDE_DCS3#
IDE _DA2 7 8 IDE _DA0
IDE_DCS1# <18> 2 2 2 2
13 14 PD IAG# 9 10 IDE _DA1
15 16 11 12 I DE_IRQ 1U_0603_10V4Z 1000P_0402_50V7K
+1.8VMOD 17 18 13 14 IDE_D DACK#
IDE_IRQ <18>
19 20 15 16 IDE_DDACK# <18>
21 22 2 1 ID E_CSEL 17 18
ID E _ D I ORDY
ID E _ D IORDY <18>
R637 470_0402_5% IDE_DIO R#
23 24 19 20 IDE_DIOR# <18>
IDE_ DIOW #
25 26 21 22 IDE_DIOW # <18>
IDE_DD REQ
27 28 23 24 IDE_DDREQ <18>
29 30 IDE_ DD15 25 26 IDE_D D0
CD _DK# 31 32 IDE_ DD14 27 28 IDE_D D1
<33> CD_DK# 33 34 29 30
CD_RESET# IDE_ DD13 IDE_D D2
35 36 IDE_ DD12 31 32 IDE_D D3
37 38 IDE_ DD11 33 34 IDE_D D4
SATA_DTX_C_IRX_P2 39 40 IDE_ DD10 35 36 IDE_D D5
<18> SATA_DTX_C_IRX_P2 41 42 37 38
SATA_DTX_C_IRX_N2 IDE_D D9 IDE_D D6
<18> SATA_DTX_C_IRX_N2 43 44 39 40
IDE_D D8 IDE_D D7
SATA_ITX_C_DRX_P2 45 46 41 42 IDE_RESET#
<18> SATA_ITX_C_DRX_P2 47 48 43 44
SATA_ITX_C_DRX_N2
<18> SATA_ITX_C_DRX_N2 49 50
1@ FOXCONNQL11253-A606

SUYIN_200138FR044G272ZU_44P
C C

Q63 +5VMOD +3VS

1@ AOS 3401_SOT23

+5VS 3 1

5
U64
2 1 1

P
+3VMOD B CD_RESET#
4
2

C850 C865 Y +3VS

+5VALW 1 2 <19> SIDE_RSET# 2 A

G
R686 1@ 240K_0402_5% @ 10U_1206_16V4Z 1@ 0.1U_0402_16V4Z 1
1 2 R688 1@ TC7SH08FU_SSOP5 C750

3
1@ 200K_0402_5% C851 1 2 0.1U_0402_16V4Z
2 1 2 1 CDR_ PSW ITCH
1

C849 1@ 1U_0805_25V4Z R687 1@ 10K_0402_5% 2

5
1@ 0.1U_0402_16V4Z U56
IDE_HRESET# 1

P
<19> IDE_HRESET# B
4 IDE_RESET#
22K PLT_RST# Y
<19> CD_DK_ON 2 <6,17,19,32,33> PLT_RST# 2 A

G
22K
TC7SH08FU_SSOP5

3
Q64
CDROM CONN
3

1@ DTC124EK_SOT23

JP4
+3VS CDROM_L 1 2 CD ROM_R
<29> INT_CD_L 1 2 INT_CD_R <29>
+12VALW CD_A GND 3 4
<29> CD_AGND 3 4
IDE_RESET# 5 6 IDE_D D8
B IDE_D D7 5 6 IDE_D D9 B
1 7 7 8 8
R702 IDE_D D6 9 10 IDE_ DD10
C862 IDE_D D5 9 10 IDE_ DD11
11 11 12 12
1@ 100K_0402_5% 1@ 0.1U_0402_16V4Z IDE_D D4 13 14 IDE_ DD12
13 14
1

1@ 0.1U_0402_16V4Z D Q65 2 IDE_D D3 IDE_ DD13 +5VS

15 15 16 16
2 IDE_D D2 17 18 IDE_ DD14
G 1@ SI2302DS_SOT23 IDE_D D1 17 18 IDE_ DD15
19 19 20 20
C861 1 S IDE_D D0 21 22 IDE_DD REQ 10U_0805_10V4Z 0.1U_0402_16V4Z
3

+3VMOD 21 22 IDE_DIO R#
23 23 24 24
R703 IDE_ DIOW # 25 26 1 1 1 1
25 26
1

D Q56 ID E _ D I ORDY IDE_D DACK#

27 27 28 28 C751
CDR_ PSW ITCH 2 1@ 200K_0402_5%2 I DE_IRQ 29 30 C752 C753 C754
G IDE _DA1 29 30 PD IAG#
31 31 32 32
S C852 C853 IDE _DA0 IDE _DA2 2 2 2 2
33 34
3

@ 4.7U_0805_10V4Z IDE _DCS1# 33 34 IDE _DCS3#

35 35 36 36
1@ 2N7002_SOT23 1@ 0.1U_0402_16V4Z ID E_LED# 37 38 0.1U_0402_16V4Z 1000P_0402_50V7K
37 38 +5VS
+5VS
39 39 40 40 80mils
41 41 42 42
43 44 <BOM Structure>
+1.8VS 43 44
45 45 46 46
2 1 SD_CSEL 47 48
+5VS 47 48
R639 @ @470_0402_5% 49 50 1 2
49 50 +5VS
1 R640
2@ OCTEK_CDR-50DC1 @ @100K_0402_5%
C863
1@ 0.1U_0402_16V4Z
1

D Q66 2
2
G 1@ SI2302DS_SOT23
A A
S
3

+1.8VMOD

C854 C855 Compal Electronics, Inc.

@ 4.7U_0805_10V4Z Title
1@ 0.1U_0402_16V4Z
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-2601
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401336
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 21 of 51
5 4 3 2 1
 5 4 3 2 1

P I_PW R R531 1 2 @ 0_1206_5% +3VALW

R532 1 2 1@ 0_1206_5%
+3VS
+DVI_VCC
JP41
M_DVI_TXD0- 17 14
M_DVI_TXD0+ TMDS_DATA0- +5V

56
50
38
27
18
10
18 TMDS_DATA0+

4
U61
M_DVI_TXD1- 9

VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
VDD0
D_DVI_TXD2- +DVI_VCC +3VS M_DVI_TXD1+ TMDS_DATA1-
0B1 48 D_DVI_TXD2- <38> 10 TMDS_DATA1+
D 47 D_DVI_TXD2+ D
DVI_TXD2- 1B1 D_DVI_TXD2+ <38> M_DVI_TXD2-
<16> DVI_TXD2- 2 A0 1 TMDS_DATA2-

2
43 D_DVI_TXD1- M_DVI_TXD2+ 2 6 I2 CB_SLC
DVI_TXD2+ 2B1 D_DVI_TXD1+ D_DVI_TXD1- <38> R652 TMDS_DATA2+ DDC_CLOCK
<16> DVI_TXD2+ 3 A1 3B1 42 D_DVI_TXD1+ <38> D VI@ 0_0402_5% 12 TMDS_DATA3-

1
37 D_DVI_TXD0- 13 7 I2 CB_SDA
DVI_TXD1- 4B1 D_DVI_TXD0+ D_DVI_TXD0- <38> TMDS_DATA3+ DDC_DATA
<16> DVI_TXD1- 7 36

1
A2 5B1 D_DVI_TXD0+ <38> R650 4 TMDS_DATA4-
DVI_TXD1+ 8 32 D_DVI_TXC+ DVI@ 4.7K_0402_5% R651 R653 DVI@ 6.8K_0402_5% 5
<16> DVI_TXD1+ A3 6B1 D_DVI_TXC+ <38> TMDS_DATA4+
31 D_DVI_TXC- 2 1 +3VS

2
7B1 D_DVI_TXC- <38>

2
G
20 TMDS_DATA5-
DVI_TXD0- 11 22 D _DVI_DET DVI@ 4.7K_0402_5% 21 16
<16> DVI_TXD0- A4 0LED1 D_DVI_DET <38> TMDS_DATA5+ Hot Plug Detect
23 D_DVI_SDATA I2 CB_SDA 1 3 M_DVI_SDATA
1LED1 D_DVI_SDATA <38>
DVI_TXD0+ 12 52 D_ DVI_SCLK

S
<16> DVI_TXD0+ A5 2LED1 D_DVI_SCLK <38> Q10 M_DVI_TXC+ 23 TMDS_Clock+

2
M_DVI_TXD2- DVI@ BSS138_SOT23 M_DVI_TXC-

G
0B2 46 24 TMDS_Clock-
DVI_TXC+ 14 45 M_DVI_TXD2+
<16> DVI_TXC+ A6 1B2 I2 CB_SLC 1 3 M_DVI_SCLK 3
DVI_TXC- M_DVI_TXD1- TMDS_DATA2/4 shield
15 41 C1 11

S
<16> DVI_TXC- A7 2B2 Analog Red TMDS_DATA1/3 shield
40 M_DVI_TXD1+ Q11 19
3B2 DVI@ BSS138_SOT23 TMDS_DATA0/5 shield
2 1 +3VS C2 Analog Green TMDS_Clock shield 22
DOCKIN# 17 35 M_DVI_TXD0- R654
SEL 4B2 M_DVI_TXD0+ DVI@ 6.8K_0402_5%
5B2 34 C3 Analog Blue Analog GND C5
Analog GND(C5) C6
D VI_DET 19 30 M_DVI_TXC+ C4
<16> DVI_DET LED0 6B2 Analog HSYNC
DVI_SDATA 20 29 M_DVI_TXC-
<16> DVI_SDATA LED1 7B2
DV I_SCLK 54 8 15
<16> DVI_SCLK LED2 Analog VSYNC GND
25 M_DVI_DET
0LED2 M_DVI_SDATA
1LED2 26
C 51 M_DVI_SCLK +5VS DVI@ TYCO_1470881-1 C
2LED2
5 NC
GND10
GND11
GND12
GND13

2
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9

D37 R648
D VI@ RB411D_SOT23 M_DVI_DET 1 2
1@ PI3L500E_TQFN56~D +DVI_VCC
1
6
9
13
16
21
24
28
33
39
44
49
53
55

DVI@ 20K_0603_5%

1
R649
1 D38
@ SKS10-04AT_TSMA DVI@ 100K_0603_5%
C758

2
DVI@ 0.1U_0402_16V4Z
2

RP120
DVI_TXD2+ 1 4 M_DVI_TXD2+

1
DVI_TXD2- 2 3 M_DVI_TXD2-
B B
2@ 0_0404_4P2R_5%
+5VS RP121
U58 D25 D2 D36 DVI_TXD1+ M_DVI_TXD1+
1 4

3
16 @ @DAN217_SOT23 @ @DAN217_SOT23 @ @DAN217_SOT23 DVI_TXD1- 2 3 M_DVI_TXD1-
DOCKIN# VCC
<15,27,33,38> DOCKIN# 1 SEL +3VS
15 2 D_TV_LUMA 2@ 0_0404_4P2R_5%
OE# 1B1 D_TV_CRMA D_TV_LUMA <38>
2B1 5 D_TV_CRMA <38>
11 D_TV_COMPS RP122
LUMA_1 3B1 D_TV_COMPS <38> DVI_TXD0+ M_DVI_TXD0+
<16> VGA_TV_LUMA 1 2 4 1A 4B1 14 1 4
R422 PM@ 0_0402_5% CRMA_1 7 DVI_TXD0- 2 3 M_DVI_TXD0-
COMPS_1 2A JP10
<8> GMCH_TV_LUMA 1 2 9 3A
R424 GM@ 0_0402_5% 12 3 LUMA L27 1 2 LUMA_L 2@ 0_0404_4P2R_5%
4A 1B2 TV@ FBM-11-160808-121T_0603 1
<16> VGA_TV_CRMA 1 2 2B2 6 2
R434 PM@ 0_0402_5% 10 RP123
3B2 CRMA L28 1 3 DVI_TXC- M_DVI_TXC-
<8> GMCH_TV_CRMA 1 2 4B2 13 2 4 1 4
R433 GM@ 0_0402_5% 8 TV@ FBM-11-160808-121T_0603 DVI_TXC+ 2 3 M_DVI_TXC+
GND CRMA_L 5
COMPS L41 1 COMPS_L 6
<16> VGA_TV_COMPS 1 2 2 2@ 0_0404_4P2R_5%
R644 PM@ 0_0402_5% TV@ FBM-11-160808-121T_0603 7
1 2 TV@FSAV330MTC_TSSOP16 D VI_DET 2 1 M_DVI_DET
<8> GMCH_TV_COMPS
1

R645 GM@ 0_0402_5% TV@S C O NN._SUYIN R682 2@ 0_0402_5%

R643 R432 R428 RP124

1 1 1 1 1 1 (CL55) DVI_SDATA 1 4 M_DVI_SDATA
C518 C495 C506 C485 C44 C54 DV I_SCLK 2 3 M_DVI_SCLK
2

2 2 2 TV@270P_0402_50V7K 2 2 2 2@ 0_0404_4P2R_5%
A A

TV@150_0402_5% TV@150_0402_5% TV@270P_0402_50V7K TV@330P_0402_50V7K TV@330P_0402_50V7K

LUMA_1 R715 1 2 2@0_0402_5% LUMA TV@150_0402_5% TV@270P_0402_50V7K TV@330P_0402_50V7K

CRMA_1 R716 1 2 2@0_0402_5% CRMA

COMPS_1 R717 1 2 2@0_0402_5% COMPS Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401336 C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 22 of 51
5 4 3 2 1
 5 4 3 2 1

+3VS
<24> VPPD0 +S1_VCC
<24> VPPD1 +3VS
<24> VCCD0#
<24> VCCD1# 1 1 1 2

M13

M12

G13
N13

N12

D12
H11

G1
C8

N4
CLK_PCI_PCM

A7

B4

K2
C692 C693 C694 C695

F3
L9
L6
U52 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1

S1_A[0..25] 2 2 2 1

VCCD1#
VCCD0#

VPPD1
VPPD0

VCCA2
VCCA1

VCC10
VCC9
VCC8
VCC7
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1
S1_A[0..25] <24>
D
R583 D
@ 10_0402_5% S1_D[0..15]
PCI_AD[0..31] S1_D[0..15] <24>
<17,25,26,28> PCI_AD[0..31] +3VS
2

1 PCI_AD31 C2 B2 S1_D10
PCI_AD30 AD31 CAD31/D10 S1_D9
C1 AD30 CAD30/D9 C3
C704 PCI_AD29 D4 B3 S1_D1 1 1 1 1
@ 18P_0402_50V8K PCI_AD28 AD29 CAD29/D1 S1_D8
D2 AD28 CAD28/D8 A3
2 PCI_AD27 S1_D0 C696 C697 C698 C699
D1 AD27 CAD27/D0 C4
PCI_AD26 E4 A6 S1_A0 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
PCI_AD25 AD26 CAD26/A0 S1_A1 2 2 2 2
E3 AD25 CAD25/A1 D7
PCI_AD24 E2 C7 S1_A2
PCI_AD23 AD24 CAD24/A2 S1_A3
F2 AD23 CAD23/A3 A8
PCI_AD22 F1 D8 S1_A4
PCI_AD21 AD22 CAD22/A4 S1_A5
G2 AD21 CAD21/A5 A9
PCI_AD20 G3 C9 S1_A6
PCI_AD19 AD20 CAD20/A6 S1_A25
H3 AD19 CAD19/A25 A10
PCI_AD18 H4 B10 S1_A7
PCI_AD17 AD18 CAD18/A7 S1_A24
J1 AD17 CAD17/A24 D10
PCI_AD16 J2 E12 S1_A17
PCI_AD15 AD16 CAD16/A17 S1_IOW R#
N2 AD15 CAD15/IOWR# F10 S1_IOW R# <24>
PCI_AD14 M3 E13 S1_A9
PCI_AD13 AD14 CAD14/A9 S1_IORD#
Close chip termenal N3 AD13 CAD13/IORD# F13 S1_IORD# <24>
+VCC_5IN1 PCI_AD12 K4 F11 S1_A11
PCI_AD11 AD12 CAD12/A11 S1_OE#
M4 AD11 CAD11/OE# G10 S1_OE# <24>
PCI_AD10 K5 G11 S1_CE2#
AD10 CAD10/CE2# S1_CE2# <24>
2

PCI_AD9 L5 G12 S1_A10

R589 PCI_AD8 AD9 CAD9/A10 S1_D15
M5 AD8 CAD8/D15 H12
@ 0_0805_5% PCI_AD7 K6 H10 S1_D7
PCI_AD6 AD7 CAD7/D7 S1_D13
M6 AD6 CAD6/D13 J11
PCI_AD5 N6 J12 S1_D6
1

SD_PULLHIGH PCI_AD4 AD5 CAD5/D6 S1_D12

1 2 M7 AD4 CAD4/D12 K13
C R591 51@ 0_0603_5% PCI_AD3 S1_D5 C
N7 J10

PCI Interface
SDCM_XDALE PCI_AD2 AD3 CAD3/D5 S1_D11
1 2 L7 AD2 CAD2/D11 K10

CARDBUS
R592 51@ 43K_0402_5% PCI_AD1 K7 K12 S1_D4
SDDA0_XDD7 PCI_AD0 AD1 CAD1/D4 S1_D3
1 2 N8 AD0 CAD0/D3 L13
R594 51@ 43K_0402_5%
1 2 SDDA1_XDD0 E1 B7 S1_REG#
<17,25,26,28> PCI_C/BE#3 CBE3# CCBE3#/REG# S1_REG# <24>
R597 51@ 43K_0402_5% J3 A11 S1_A12
<17,25,26,28> PCI_C/BE#2 CBE2# CCBE2#/A12
1 2 SDDA2_XDCL N1 E11 S1_A8
<17,25,26,28> PCI_C/BE#1 CBE1# CCBE1#/A8
R599 51@ 43K_0402_5% N5 H13 S1_CE1#
<17,25,26,28> PCI_C/BE#0 CBE0# CCBE0#/CE1# S1_CE1# <24>
1 2 SDDA3_XDD4
R601 51@ 43K_0402_5% PCI_RST# G4 B9 S1_RST
<17,25,26,28,32,33> PCI_RST# PCIRST# CRST#/RESET S1_RST <24>
J4 B11 S1_A23
<17,25,26,28> PCI_FRAME# FRAME# CFRAME#/A23
K1 A12 S1_A15
+3VS <17,25,26,28> PC I_IRDY# IRDY# CIRDY#/A15
K3 A13 S1_A22
<17,25,26,28> PCI_TRDY# TRDY# CTRDY#/A22
L1 B13 S1_A21
<17,25,26,28> PCI_DEVSEL# DEVSEL# CDEVSEL#/A21
1 2 SDCD# L2 C12 S1_A20
@ 43K_0402_5% <17,25,26,28> PCI_STOP# STOP# CSTOP#/A20
R604 L3 C13 S1_A14
<17,25,26,28> PCI_PERR# PERR# CPERR#/A14
1 2 SDWP M1 A5 S1_WAIT#
<17,25,26,28> PCI_SERR# SERR# CSERR#/WAIT# S1_WAIT# <24>
R605 @ 43K_0402_5% M2 D13 S1_A13
<17,25,26,28> PCI_PAR PAR CPAR/A13
1 2 MSINS# A1 B8 S1_INPACK#
<17> PCI_REQ#2 PCIREQ# CREQ#/INPACK# S1_INPACK# <24>
R606 @ 43K_0402_5% B1 C11 S1_WE#
<17> PCI_GNT#2 PCIGNT# CGNT#/WE# S1_WE# <24>
CLK_PCI_PCM H1 B12 A16_CLK 1 2 S1_A16
<14> CLK_PCI_PCM PCICLK CCLK/A16 R584 33_0402_5%
L8 C5 S1_BVD1
+3VS +3VS RIOUT#_PME# CSTSCHG/BVD1_STSCHG# S1_BVD1 <24>
+3VS 1 23V_PCM_SUSP L11 SUSPEND# CCLKRUN#/WP_IOIS16# D5 S1_WP
S1_WP <24>
R585 10K_0402_5%
PCI_AD20 1 2 PCM_ID F4 D11 S1_A19
IDSEL CBLOCK#/A19
2

R586 100_0402_5%
R587 PCI_PIRQA# K8 D6 S1_RDY# S1_CD1# S1_CD2#
<17> PCI_PIRQA# MFUNC0 CINT#/READY_IREQ# S1_RDY# <24>
51@ 43K_0402_5% R588 SD_PULLHIGH N9
PCI_PIRQB# MFUNC1 PCM_SPK#
<17> PCI_PIRQB# K9 MFUNC2 SPKROUT M9 PCM_SPK# <29> 1 1
B N10 B5 S1_BVD2 C705 C706 B
1

<19,32,33> SERIRQ MFUNC3 CAUDIO/BVD2_SPKR# S1_BVD2 <24>

<24> SM_CD# L10 MFUNC4
51@ 10K_0402_5% N11 A4 S1_CD2# 10P_0402_50V8J 10P_0402_50V8J
<33> CARD_LED# MFUNC5 CCD2#/CD2# S1_CD2# <24> 2 2
M11 L12 S1_CD1#
MFUNC6 CCD1#/CD1# S1_CD1# <24>
SDOC# J9 D9 S1_VS2
<24> SDOC# MFUNC7 CVS2/VS2# S1_VS2 <24>
C6 S1_VS1
CVS1/VS1 S1_VS1 <24>
A2 S1_D2 Closed to Pin L12 Closed to Pin A4
PCI_RST# M10 CRSV3/D2 S1_A18
GRST# CRSV2/A18 E10
J13 S1_D14
CRSV1/D14

E7
SD/MMC/MS/SM H7
+VCC_5IN1 VCC_SD MSINS# XD_MS_PWREN#
MSINS# <24>
MSPWREN#/SMPWREN# J8 XD_MS_PWREN# <24>
SDCD# E8 H8 MSBS_XDD1
<24> SDCD# SDCD# MSBS/SMDATA1 MSBS_XDD1 <24>
SDWP F8 E9 1 2 Close chip termenal
<24> SDWP SDWP/SMWPD# MSCLK/SMRE# MSCLK_XDRE# <24>
SDPW REN# G7 G9 MSD0_XDD2 R590 51@ 33_0402_5%
<24> SDPW REN# SDPWREN33# MSDATA0/SMDATA2 MSD0_XDD2 <24>
H9 MSD1_XDD6
MSDATA1/SMDATA6 MSD1_XDD6 <24>
H5 G8 MSD2_XDD5 MSD0_XDD2 1 2
<14> CLK_SD_48M SDCLKI MSDATA2/SMDATA5 MSD2_XDD5 <24>
F9 MSD3_XDD3 R593 @ 43K_0402_5%
MSDATA3/SMDATA3 MSD3_XDD3 <24>
R595 1 2 51@ 22_0402_5% F6 MSD1_XDD6 1 2
<24> SDCK SDCLK/SMWE#
SDCM_XDALE E5 R596 @ 43K_0402_5%
<24> SDCM_XDALE SDCMD/SMALE
R200 1 2 SDDA0_XDD7 E6 H6 MSD2_XDD5 1 2
<24> XDWE1# <24> SDDA0_XDD7 SDDAT0/SMDATA7 SMBSY# XDBSY# <24>
SDDA1_XDD0 F7 J7 R598 @ 43K_0402_5%
<24> SDDA1_XDD0 SDDAT1/SMDATA0 SMCD# XDCD# <24>
51@ 22_0402_5% SDDA2_XDCL F5 J6 MSD3_XDD3 1 2
<24> SDDA2_XDCL SDDAT2/SMCLE SMWP# XDWP# <24>
SDDA3_XDD4 G6 J5 R600 @ 43K_0402_5%
<24> SDDA3_XDD4 SDDAT3/SMDATA4 SMCE# XDCE# <24>
MSBS_XDD1 1 2
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

G5 R602 @ 43K_0402_5%
GND_SD
2

R603
CB714_LFBGA169 51@ 2.2K_0402_5%
D3
H2
L4
M8
K11
F12
C10
B6

A IDSEL: A
1

PCI_AD20

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-2601
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401336
Date: 星期四, 三月 17, 2005 Sheet 23 of 51
5 4 3 2 1
PCMCIA Power Controller
CardBus Socket
JP33

S1_A[0..25] 1 35
<23> S1_A[0..25] GND GND
S1_D3 2 36 S1_CD1#
+5VS U53 +S1_VCC S1_D[0..15] S1_D4 D3 CD1# S1_D11 S1_CD1# <23>
1 2 <23> S1_D[0..15] 3 D4 D11 37
13 40mil C707 0.1U_0402_16V4Z S1_D5 4 38 S1_D12
VCC S1_D6 D5 D12 S1_D13
VCC 12 5 D6 D13 39
9 11 C708 0.1U_0402_16V4Z S1_D7 6 40 S1_D14
0.1U_0402_16V4Z C709 12V VCC S1_CE1# D7 D14 S1_D15
1 2 <23> S1_CE1# 7 CE1# D15 41
C710 10U_0805_10V4Z Close to S1_A10 8 42 S1_CE2#
+S1_VPP +S1_VCC S1_OE# A10 CE2# S1_VS1 S1_CE2# <23>
1 2 9 43
20mil C711 0.01U_0402_16V7K CardBus Conn. <23> S1_OE# S1_A11 10
OE# VS1#
44 S1_IORD# S1_VS1 <23>
+5VS S1_A9 A11 IORD# S1_IOW R# S1_IORD# <23>
VPP 10 1 2 11 A9 IOWR# 45 S1_IOW R# <23>
C712 1U_0603_10V4Z 1 1 S1_A8 12 46 S1_A17
0.1U_0402_16V4Z C713 S1_A13 A8 A17 S1_A18
5 5V 13 A13 A18 47
6 C715 C716 S1_A14 14 48 S1_A19
4.7U_0805_10V4Z C714 5V 10U_0805_10V4Z 0.1U_0402_16V4Z S1_WE# A14 A19 S1_A20
<23> S1_WE# 15 WE# A20 49
2 2 S1_RDY# S1_A21
VCCD0 1 VCCD0# <23> <23> S1_RDY# 16 IREQ# A21 50
VCCD1 2 VCCD1# <23> +S1_VCC 17 VCC VCC 51 +S1_VCC
VPPD0 15 VPPD0 <23> +S1_VPP 18 VPP1 VPP2 52 +S1_VPP
+3VS 14 S1_A16 19 53 S1_A22
VPPD1 VPPD1 <23> A16 A22
S1_A15 20 54 S1_A23
0.1U_0402_16V4Z C717 S1_A12 A15 A23 S1_A24
3 3.3V 21 A12 A24 55
4 8 +S1_VPP S1_A7 22 56 S1_A25
3.3V OC A7 A25

SHDN
4.7U_0805_10V4Z C718 S1_A6 23 57 S1_VS2

GND
S1_A5 A6 VS2# S1_RST S1_VS2 <23>
24 A5 RESET 58 S1_RST <23>
2

1 1 S1_A4 25 59 S1_WAIT#
R607 CP-2211_SSOP16 C719 C720 S1_A3 A4 WAIT# S1_INPACK# S1_WAIT# <23>
26 60
7

16
10K_0402_5% S1_A2 A3 INPACK# S1_REG# S1_INPACK# <23>
27 A2 REG# 61 S1_REG# <23>
4.7U_0805_10V4Z 0.01U_0402_16V7K S1_A1 28 62 S1_BVD2
2 2 S1_A0 A1 SPKR# S1_BVD1 S1_BVD2 <23>
29 63
1

S1_D0 A0 STSCHG# S1_D8 S1_BVD1 <23>

30 D0 D8 64
S1_D1 31 65 S1_D9
S1_D2 D1 D9 S1_D10
32 D2 D10 66
S1_WP 33 67 S1_CD2#
<23> S1_WP IOIS16# CD2# S1_CD2# <23>
34 GND GND 68

SUPER_AC4-3000-250-3_RT

+3VS

1 2 XDCD#
XDCD# <23>
R608 @ 43K_0402_5%

SD CLK +VCC_5IN1
SDCK xD PU and PD. Close to Socket
<23> SDCK
JP34

1
SDDA1_XDD0 34 11 SDDA3_XDD4 1 2 MSCLK_XDRE#
SM-D0 SD-DAT3 SDDA3_XDD4 <23>
MSBS_XDD1 33 12 SDDA2_XDCL R610 R609 51@ 43K_0402_5%
MSD0_XDD2 SM-D1 / XD-D1 SD-DAT2 SDDA1_XDD0 SDDA2_XDCL <23> @ 0_0402_5%
32 SM-D2 / XD-D2 SD-DAT1 6 SDDA1_XDD0 <23> 1 2 XDWE1#
MSD3_XDD3 31 5 IN 1 CONN SD-DAT0 7 SDDA0_XDD7 R611 51@ 2.2K_0402_5%
SM-D3 / XD-D3 SDDA0_XDD7 <23>
SDDA3_XDD4 21 5 SDWP 1 2
SDWP <23>

2
SM-D4 / XD-D4 SD-WP-SW XDCE# <23>
MSD2_XDD5 22 10 SDCM_XDALE 1 R612 51@ 43K_0402_5%
SM-D5 / XD-D5 SD-CMD SDCM_XDALE <23>
MSD1_XDD6 23 8 SDCK C721
SDDA0_XDD7 SM-D6 / XD-D6 SD_CLK @ 10P_0402_50V8K
24 SM-D7 / XD-D7 SD-VCC 9 +VCC_5IN1
4 1 2 XDBSY#
NC 2 XDBSY# <23>
XDWP# 35 42 SDCD# R613 51@ 43K_0402_5%
<23> XDWP# SM_WP-IN / XD_WP-IN SD-CD-SW SDCD# <23>
SDWP 43 41
XDWE1# SM-WP-SW SD-CD-COM
<23> XDWE1# 36 #SM_-WE / XD_-WE
SDCM_XDALE 37 15 MSD0_XDD2
#SM-ALE / XD-ALE MS-DATA0 MSD0_XDD2 <23>
14 MSD1_XDD6
MS-DATA1 MSD1_XDD6 <23>
25 16 MSD2_XDD5 MS CLK
<23> SM_CD# SM-LVD MS-DATA2 MSD2_XDD5 <23> +S1_VCC
SM_CD# 3 18 MSD3_XDD3 MSCLK_XDRE# Reserve for Debug.
SM-CD-SW MS-DATA3 MSD3_XDD3 <23> <23> MSCLK_XDRE#
29 19 MSCLK_XDRE#
+VCC_5IN1 SM_-VCC / XD_-VCC MS-SCLK MSCLK_XDRE# <23>

1
XDBSY# 26 17 MSINS# S1_WP 2 1
MSCLK_XDRE# #SM_R/-B / XD_R/-B MS-INS MSBS_XDD1 MSINS# <23> R615 43K_0402_5% R614
27 #SM_-RE / XD_-RE MS-BS 13
XDCE# 28 20 MSBS_XDD1 <23> @ 0_0402_5% S1_OE# 2 1
XDCD# #SM_-CE / XD_-CE MS-VCC +VCC_5IN1 47K_0402_5% R617
30 #SM_-CD
2 40 S1_RST 2 1
+VCC_5IN1

2
SDDA2_XDCL SM-CD-COM XD-VCC XDCD# 47K_0402_5% R618
38 SM-CLE / XD-CLE XD-CD 39 1
1 C722 S1_CE1# 2 1
GND
2

44 @ 10P_0402_50V8K 47K_0402_5% R619

GND R710 S1_CE2# 2 1
51@ TAITN _R007-N3P-15-S 51@ 100K_0402_5% 2 47K_0402_5% R620
1

+3VS
SD PWR Control +3VS

+VCC_5IN1

2
+3VS U54
R621 R622
51@ 10K_0402_5% 1 8
GND OUT
2 IN OUT 7
+VCC_5IN1 3 6 51@ 10K_0402_5%

1
IN OUT
<23> SDPW REN# 4 EN# OC# 5 SDOC# <23>
51@ 10U_0805_10V4Z 51@ 0.1U_0402_16V4Z 51@ 0.1U_0402_16V4Z
1 <23> XD_MS_PWREN#
51@ TPS2041ADR_SO8
C723 C724 C725 C726 C727
2
51@ 0.1U_0402_16V4Z
51@ 0.1U_0402_16V4Z

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-2601
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401336
Date: 星期四, 三月 17, 2005 Sheet 24 of 51
 5 4 3 2 1

+3VS
+3VS
1394@ 0.1U_0402_16V4Z 1394@ 0.1U_0402_16V4Z
1 1 1 1
1 2 C728 C729 C730 C731
R623 1394@ 4.7K_0402_5%
1 2
R624 1394@ 10K_0402_5% 2 2 2 2
+3VS 1 2 1394@ 0.1U_0402_16V4Z 1394@ 0.1U_0402_16V4Z
R625 1394@ 4.7K_0402_5%
1 2
D R626 1394@ 4.7K_0402_5% D
2 1 +3VS
R627 1394@ 4.7K_0402_5%
U55 1394@ 1000P_0402_50V7K 1394@ 1000P_0402_50V7K
PCI_AD[0..31] TSB43AB21_PQFP128

20
35
48
62
78

87

86
96
10
11
<17,23,26,28> PCI_AD[0..31] 1 1 1 1
C732 C733 C734 C735

TEST17
TEST16
CYCLEIN
VDDP
VDDP
VDDP
VDDP
VDDP

CNA
CYCLEOUT/CARDBUS
DVDD 15 +3VS
PCI_AD0 2 2 2 2
84 PCI_AD0 DVDD 27
PCI_AD1 82 39 1394@ 1000P_0402_50V7K 1394@ 1000P_0402_50V7K
PCI_AD2 PCI_AD1 DVDD
81 PCI_AD2 DVDD 51
PCI_AD3 80 59
PCI_AD4 PCI_AD3 DVDD
79 PCI_AD4 DVDD 72
PCI_AD5 77 88
PCI_AD6 PCI_AD5 DVDD L39
76 PCI_AD6 DVDD 100
PCI_AD7 74 7 +1394_PLLVDD 1394@ 0.01U_0402_16V7K 1 2 +3VS
PCI_AD8 PCI_AD7 PLLVDD 1394@ BLM21A601SPT_0805
71 1 1 1
PCI_AD9
PC I_AD10
70
69
PCI_AD8
PCI_AD9
TSB43AB21 AVDD
AVDD 2
107
+3VS
C736 C737

PC I_AD11
PC I_AD12
67
66
PCI_AD10
PCI_AD11
/(TSB43AB22) AVDD
AVDD 108
120
2 2
PC I_AD13 PCI_AD12 AVDD 1394@ 4.7U_0805_10V4Z
65 PCI_AD13
PC I_AD14 63 PCI_AD14
PCI BUS INTERFACE
PC I_AD15 61 106 1 2
PC I_AD16 PCI_AD15 CPS R628 1394@ 1K_0402_5%
46 PCI_AD16
PC I_AD17 45
PC I_AD18 PCI_AD17
43 PCI_AD18 NC/(TPBIAS1) 125
PC I_AD19 42 124
PC I_AD20 PCI_AD19 NC/(TPA1+)
41 PCI_AD20 NC/(TPA1-) 123
C PC I_AD21 40 122 C
PC I_AD22 PCI_AD21 NC/(TPB1+)
38 PCI_AD22 NC/(TPB1-) 121
PC I_AD23 37
PC I_AD24 PCI_AD23
32 PCI_AD24 BIAS CURRENT R0 118 1 2
PC I_AD25 31 R629
PC I_AD26 PCI_AD25 1394@ 6.34K_0402_1%
IDSEL:PCI_AD16 29 PCI_AD26
PC I_AD27 28
PC I_AD28 PCI_AD27
26 PCI_AD28
PC I_AD16 1 2 1394_IDSEL PC I_AD29 25 119
R630 1394@ 100_0402_5% PC I_AD30 PCI_AD29 R1 C738 1
24 PCI_AD30 2 1394@ 22P_0402_50V8J
PC I_AD31 22 6
PCI_AD31 OSCILLATOR X0

2
PCI_C/BE#3 34
<17,23,26,28> PCI_C/BE#3 PCI_C/BE3
PCI_C/BE#2 47 X5
<17,23,26,28> PCI_C/BE#2 PCI_C/BE2
PCI_C/BE#1 60 1394@ 24.576MHz_16P_3XG-24576-43E1
<17,23,26,28> PCI_C/BE#1 PCI_C/BE1
PCI_C/BE#0 73 5
<17,23,26,28> PCI_C/BE#0

1
CLK_PCI_1394 PCI_C/BE0 X1 C739 1
<14> CLK_PCI_1394 16 PCI_CLK 2
PCI_GNT#0 18 1394@ 22P_0402_50V8J
<17> PCI_GNT#0 PCI_GNT
P CI_REQ#0 19 3 C740 1 2
<17> PCI_REQ#0
1394_IDSEL PCI_REQ FILTER FILTER0
36 PCI_IDSEL
P CI_FRAME# 49 4 1394@ 0.1U_0402_16V4Z
<17,23,26,28> PCI_FRAME# PCI_FRAME FILTER1
P C I_ I RDY# 50
<17,23,26,28> P C I_ IRDY# PCI_IRDY
PCI_TRD Y# 52 92 1394_SDA
<17,23,26,28> PCI_TRDY#
PCI_DEVSEL# PCI_TRDY EEPROM 2 WIRE BUS SDA
<17,23,26,28> PCI_DEVSEL# 53 PCI_DEVSEL
PCI_STOP# 54 91 1394_SCL 1
<17,23,26,28> PCI_STOP# PCI_STOP SCL

1
PCI_PERR# 56
<17,23,26,28> PCI_PERR# PCI_PERR
PCI_ PIRQE# 13 POWER CLASS 99 R631 R632 C741
<17> PCI_PIRQE# PCI_INTA/CINT PC0
1394_PME# 21 98 1394@ 56.2_0402_1% 1394@ 56.2_0402_1% 1394@ 0.33U_0603_16V4Z
<26,28,32,33> 1394_PME# PCI_PME/CSTSCHG PC1 2
PCI_SERR# 57 97
<17,23,26,28> PCI_SERR# PCI_SERR PC2
PCI_PAR 58
<17,23,26,28> PCI_PAR

2
B PCI_PAR TPBIAS0 JP35 B
<19,26,28,32,33> PM_CLKRUN# 12 PCI_CLKRUN PHY PORT 1 TPBIAS0 116
PCI_RST# 85 115 TPA0+
<17,23,26,28,32,33> PCI_RST# PCI_RST TPA0+ 4 5
114 TPA0-
TPA0- TPB0+ 3 6
TPB0 + 113 2
112 TPB0-
TPB0 - 1

1
1394@ SUYIN8004A-04G5T
94 R633 R634
TEST9 1394@ 56.2_0402_1% 1394@ 56.2_0402_1%
TEST8 95
14 G_RST
101 (CL56)

2
1394_GPIO3 TEST3
PLLGND1

89 102
REG_EN

1394_GPIO2 GPIO3 TEST2

90 104
REG18

REG18

GPIO2 TEST1
DGND
DGND

DGND
DGND
DGND
DGND
DGND
DGND
DGND

DGND

1
AGND
AGND
AGND
AGND
AGND
AGND
AGND

TEST0 105 1
RP119 C742 R635
5 4 1394_GPIO3 1394@ 5.11K_0402_1%
6 3 1394_GPIO2 1394@ 220P_0402_50V7K
8
9
109
110
111
117
126
127
128
17
23
30
33
44
55
64
68
75
83
93
103

1394_SCL 2
7 2

2
8 1 1394_SDA

1394@ 220_1206_8P4R_5%

1394@
1 1
C743 C744

CLK_PCI_1394
2 2 1394@ 0.1U_0402_16V4Z
A A
1

R636
@ 10_0402_5% 1394@ 0.1U_0402_16V4Z
2

1
C745 Compal Electronics, Inc.
Title
@ 10P_0402_50V8K
2 SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C ustom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401336
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 25 of 51
5 4 3 2 1
 5 4 3 2 1

LAN_CTRL_2.5V unpop when use BCM4401 LAN_CTRL_1.2V

+3VALW +3V_LAN Q61
EN_WOL# = Low, 80mils

1
Q60 1@ BCP69_SOT223
System can wake on LAN 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1@ BCP69_SOT223 +2.5V_LAN +1.2V_LAN
60mils
( keep Low when Power On) 1 1 1 1 1 1 1 +3V_LAN

1
S
G C642 C643 3 2 10U_0805_10V4Z 0.1U_0402_16V4Z 3 2 0.1U_0402_16V4Z
2 R551 C644 C645 C646 C647 C648 4 1 1 1 1 1 4 1 1
<33> EN_WOL# @ 0_1206_5% C649 C650 C651 C652 C653 C654
Q62 D 2 2 2 2 2 2 2 C655

1
VGS(th) = -0.45V SI2301DS_SOT23 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

2
2 2 2 2 2 2 2
IDmax = 2.3A 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z
+3V_LOM_PCI
D
+3V_LAN
20mils +1.2V_LAN
D

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

60mils
+3V_LAN 1 2
L33 2@ 0_0603_5% 1 1 1 1 1 1 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+3VS for BCM5788 C656 C657 C658 C659 C660 C661 C662 1 1 1 1 1 1 1 1
+3VS 1 2
+3V_LAN for BCM4401 L34 1@ 0_0603_5% C663 C664 C665 C666 C667 C668 C669 C670
2 2 2 2 2 2 2
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
PCI_AD[0..31]
<17,23,25,28> PCI_AD[0..31]
U49A U49B
PC I_AD31 B8 E13 LAN_MDI3+
AD31 TRD3+/(NC_E13) LAN_MIDI3+ <27>
PC I_AD30 A8 E14 LAN_MDI3- +1.2V_LAN E12 B7
AD30 TRD3-/(NC_E14) LAN_MIDI3- <27> VDDC_E12 VSS_B7
PC I_AD29 C7 D13 LAN_MDI2+ H5 D4
AD29 TRD2+/(NC_D13) LAN_MIDI2+ <27> VDDC_H5 VSS_D4
PC I_AD28 C6 D14 LAN_MDI2- H6 D5
AD28 TRD2-/(NC_D14) LAN_MIDI2- <27> VDDC_H6 VSS_D5
PC I_AD27 B6 C13 LAN_MDI1+ H7 D6 5788 4401
AD27 TRD1+/(RDP) LAN_MIDI1+ <27> VDDC_H7 VSS_D6
PC I_AD26 B5 C14 LAN_MDI1- H8 D7
AD26 TRD1-/(RDN) LAN_MIDI1- <27> VDDC_H8 VSS_D7
PC I_AD25 A5 B13 LAN_MDI0+ J5 D8 L33 Pop
AD25 TRD0+/(TDP) LAN_MIDI0+ <27> VDDC_J5 VSS_D8
PC I_AD24 B4 B14 LAN_MDI0- J6 D9
AD24 TRD0-/(TDN) LAN_MIDI0- <27> VDDC_J6 VSS_D9/(NC_D9)
PC I_AD23 B2 J7 E2 L34 Pop
PC I_AD22 AD23 VDDC_J7 VSS_E2
B1 AD22 J8 VDDC_J8 VSS_E5 E5
PC I_AD21 C1 B9 +2.5V_LAN (Output 3.3V for BCM4401) J9 E6 Q61 Pop
PC I_AD20 AD21 REGSUP12/(NC_B9) LAN_CTRL_1.2V VDDC_J9 VSS_E6
D3 AD20 REGCTL12/(NC_B10) B10 J10 VDDC_J10 VSS_E7 E7
PC I_AD19 D2 A9 +1.2V_LAN (Output 1.8V for BCM4401) K5 E8 Q60 Pop
PC I_AD18 AD19 REGSEN12/(REG18OUT) VDDC_K5 VSS_E8
D1 AD18 K6 VDDC_K6 VSS_E9 E9
C LK_PCI_LAN PC I_AD17 E3 B11 +3V_LAN K7 F5 R560 1.24K 1.27K
PC I_AD16 AD17 REGSUP25/(REGSUP18) LAN_CTRL_2.5V VDDC_K7 VSS_F5
K1 AD16 REGCTL25/(NC_C11) C11 K8 VDDC_K8 VSS_F6 F6
1

C PC I_AD15 L2 C10 +2.5V_LAN K9 F7 U50 Pop C

PC I_AD14 AD15 REGSEN25/(REGSUP18) VDDC_K9 VSS_F7
L1 AD14 K10 VDDC_K10 VSS_F8 F8
R552 PC I_AD13 M3 P1 +3V_LAN L5 F9 C678 Pop
@ 10_0402_5% PC I_AD12 AD13 VESD1 VDDC_L5 VSS_F9
M2 AD12 VESD2 G2 L10 VDDC_L10 VSS_F10 F10
PC I_AD11 M1 A1 M14 G4 U51 Pop
2

PC I_AD10 AD11 VESD3 VDDC_M14 VSS_G4

N2 N14 G5
1
PCI_AD9 N3
AD10
AD9 EEDATA/(SPROM_CS) P10 LAN_EEDA P8
VDDC_N14
VDDC_P8
BCM5788M VSS_G5
VSS_G6 G6 R561 Pop
C671 PCI_AD8 P3 M10 LAN_EECLK P12 G7
@ 18P_0402_50V8K PCI_AD7 N4
AD8
AD7
EECLK/(SPROM_CLK)
P13
VDDC_P12
VDDC_P13
/(BCM4401) VSS_G7
VSS_G8 G8 C677 Pop
2 PCI_AD6 P4 AD6 GPIO0/(NC_H12) H12 P14 VDDC_P14 VSS_G9 G9
PCI_AD5 M5 K13 LAN_EEWP 1 2 +3V_LAN G10 R562 Pop
PCI_AD4 AD5 GPIO1/(NC_K13) R553 10K_0402_5% VSS_G10
N5 J13 H9
PCI_AD3 P5
AD4
AD3
BCM5788M GPIO2/(NC_J13) VSS_H9
VSS_K2 K2
PCI_AD2 P6 A7 L6
PCI_AD1 M7
AD2
AD1
/(BCM4401) unpop R554 when use BCM4401
+3V_LOM_PCI
B3
VDDIO-PCI_A7
VDDIO-PCI_B3
VSS_L6
VSS_L9 L9
PCI_AD0 N7 C5 M6
AD0 VDDIO-PCI_C5 VSS_M6
LINKLED/(LINKLED10) G13 LAN_LINK# <27> E1 VDDIO-PCI_E1 VSS_M12 M12
SPD100LED/(LINKLED100) H13 E4 VDDIO-PCI_E4 VSS_M13/(NC_M13) M13
G12 R554 1 1@ 2 0_0402_5% G1 N1
PCI_C/BE#3 SPD1000LED/(COL_LED) LAN _ACTIVITY# VDDIO-PCI_G1 VSS_N1
<17,23,25,28> PCI_C/BE#3 C4 CBE3 TRAFFICLED/(ACT_LED) G14 LAN_ACTIVITY# <27> K3 VDDIO-PCI_K3 VSS_N12 N12
PCI_C/BE#2 F3 L4 N13
<17,23,25,28> PCI_C/BE#2 CBE2 +1.2V_LAN_PLLVDD VDDIO-PCI_L4 VSS_N13
PCI_C/BE#1 L3 20mils N6
<17,23,25,28> PCI_C/BE#1 CBE1 VDDIO-PCI_N6
PCI_C/BE#0 M4 H14 +1.2V_LAN_PLLVDD 1 2 +1.2V_LAN P2
<17,23,25,28> PCI_C/BE#0 CBE0 PLLVDD2/(PLLVDD) VDDIO-PCI_P2
P7 0.1U_0402_16V4Z
1 1 L35
NC_P7 C673 0_0603_5% +2.5V_LAN K14 VDDP_K14/(NC_K14)AVDDL_F12/(AVDD_F12) F12 +1.2V_LAN_AVDD 1 2 +1.2V_LAN 20mils
100_0402_5% C672 L13 F13 L36
PC I_AD17 R555 1 L AN_IDSEL 4.7U_0805_10V4Z VDDP_L13/(NC_L13)AVDDL_F13/(AVDD_F13)
2 A4 IDSEL TCK C12 P11 VDDP_P11/(NC_P11) AVDD_F14/(NC_F14) F14 +2.5V_LAN_AVDD 0_0603_5%
1 2 +2.5V_LAN 20mils
2 2 L37
<17,23,25,28> PCI_FRAME# F2 FRAME TDI D12 AVDD_A13/(NC_A13) A13 1
F1 B12 +3V_LAN A11 1 0_0603_5%
B <17,23,25,28> P C I_ IRDY# IRDY TDO VDDIO_A11 B
G3 A12 F11 C674
<17,23,25,28> PCI_TRDY# TRDY TMS VDDIO_F11
H3 D11 LAN_TRST# 1 2 K12 C675
<17,23,25,28> PCI_DEVSEL# DEVSEL TRST VDDIO_K12 2
H1 R556 4.7K_0402_5% L12 0.1U_0402_16V4Z 0.1U_0402_16V4Z
<17,23,25,28> PCI_STOP# STOP VDDIO_L12 2
<17,23,25,28> PCI_PERR# J2 PERR
<17,23,25,28> PCI_SERR# A2 SERR C8 NC_C8
J1 PM_CLKRUN# H4 L11
<17,23,25,28> PCI_PAR PAR <19,25,28,32,33> PM_CLKRUN# CLKRUN NC_L11/(VSS_L11)
C LK_PCI_LAN A3 H10 L14
<14> CLK_PCI_LAN PCI_CLK NC_H10 NC_L14/(VSS_L14)
J4 NC_J4 NC_M8 M8
XTALVDD J14 +2.5V_LAN K4 NC_K4 NC_M9/(VREF) M9
N10 LAN_X1 J11 M11 1 2
XTALO LAN_X2_R 1 NC_J11/(GPIO_1)LOW_POWER/(TESTMODE)
<17> PCI_PIRQF# H2 INTA XTALI N11 2 LAN_X2 K11 NC_K11/(GPIO_0) NC_N8/(EXT_POR) N8 R557 10K_0402_5%
C2 R558 200_0402_1% L7 N9 LA N_EEDI
<17,23,25,28,32,33> PCI_RST# PCI_RST NC_L7 NC_N9/(DOUT)
J3 L8 P9 LAN_EEDO
<17> PCI_GNT#3 GNT NC_L8 NC_P9/(DIN)
<17> PCI_REQ#3 C3 REQ NC_G11 G11 1.24K for BCM5788 BCM5788M_FBGA196
NC_E10/(EEDATA_PXE) E10
E11 1.27K for BCM4401
NC_E11/(EECLK_PXE) +3V_LAN
NC_H11 H11 C677
C676 1 2 1000P_0402_50V7K
1 2 LAN_AUXPWR J12 10mils 1 2
+3V_LAN
R559 1K_0402_5% F4
VAUXPRSNT
A14 +LAN_BIASVDD 1 2 +2.5V_LAN
AT93C46 for BCM4401
M66EN/(NC_F4) BIASVDD

2
A6 D10 LAN _RDAC 1 2 L38
<25,28,32,33> ONBD_LAN_PME# PME RDAC 1@ 0.1U_0402_16V4Z
10mils R560 0_0603_5%
1.24K_0402_1% R561 R562
+3V_LAN 1@ 4.7K_0402_5% 1@ 4.7K_0402_5%
U50 U51
A10 1 2 +3V_LAN LAN_EEDA 1 8 8 VCC 1

1
NC_A10 R563 @ 10K_0402_5% LAN_EECLK CS VCC LAN_EEWP A0
NC_C9 C9 1 2 2 SK NC 7 1 7 WP A1 2
R564 @ 10K_0402_5% LA N_EEDI 3 6 LAN_EECLK 6 SCL 3
Y4 LAN_EEDO DI NC C678 LAN_EEDA NC
4 DO GND 5 5 SDA GND 4
A
LAN_X1 LAN_X2 BCM5788M_FBGA196 2@ 0.1U_0402_16V4Z A
2@ AT93C46-10SI-2.7_SO8 2
1 25MHZ_20P 1
24C256 for BCM5788 1@ AT24C256_SO8~D
C679 C680
Unpop when use BCM4401
27P_0402_50V8J 27P_0402_50V8J
2 2
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-2601
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401336
D ate: ¬P 期四, 三月 17, 2005 Sheet 26 of 51
5 4 3 2 1
 5 4 3 2 1

1 1
C681 C682

0.1U_0402_16V4Z 0.1U_0402_16V4Z +3V_LAN

2 2

1
R567
RP125 49.9_0402_1%

56
50
38
27
18
10
4
LA N_MIDI3- 1 4 L_LAN_MDI3- R566 R568 R569 U62
L AN_MIDI3+ 2 3 L_LAN_MDI3+ 49.9_0402_1% 49.9_0402_1% 49.9_0402_1%

VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
VDD0
48 D_LAN_MDI0+
D_LAN_MDI0+ <38>

2
2@ 0_0404_4P2R_5% 0B1 D_LAN_MDI0-
D
1B1 47 D_LAN_MDI0- <38> D
<26> LAN_MIDI0+ L AN_MIDI0+ 2 A0 D_LAN_MDI1+
RP126 43 D_LAN_MDI1+ <38>
LA N_MIDI2- L_LAN_MDI2- LA N_MIDI0- 2B1 D_LAN_MDI1-
1 4 <26> LAN_MIDI0- 3 A1 3B1 42 D_LAN_MDI1- <38>
L AN_MIDI2+ 2 3 L_LAN_MDI2+
37 D_LAN_MDI2+
2@ 0_0404_4P2R_5% 4B1 D_LAN_MDI2+ <38>
<26> LAN_MIDI1+ L AN_MIDI1+ 7 36 D_LAN_MDI2-
A2 5B1 D_LAN_MDI2- <38>
RP127 <26> LAN_MIDI1- LA N_MIDI1- 8 32 D_LAN_MDI3+
A3 6B1 D_LAN_MDI3+ <38>
LA N_MIDI1- 1 4 L_LAN_MDI1- 31 D_LAN_MDI3-
7B1 D_LAN_MDI3- <38>
L AN_MIDI1+ 2 3 L_LAN_MDI1+
<26> LAN_MIDI2+ L AN_MIDI2+ 11 22 D_L AN_ACTIVITY#
A4 0LED1 D_LAN_ACTIVITY# <38>
2@ 0_0404_4P2R_5% 23 D _LAN_LINK#
1LED1 D_LAN_LINK# <38>
<26> LAN_MIDI2- LA N_MIDI2- 12 52
A5 2LED1
RP128
LA N_MIDI0- 1 4 L_LAN_MDI0- 46 L_LAN_MDI0+
L AN_MIDI0+ L_LAN_MDI0+ L AN_MIDI3+ 0B2 L_LAN_MDI0-
2 3 <26> LAN_MIDI3+ 14 A6 1B2 45

2@ 0_0404_4P2R_5% <26> LAN_MIDI3- LA N_MIDI3- 49.9_0402_1% 15 41 L_LAN_MDI1+

A7 2B2 L_LAN_MDI1-
3B2 40

1
RP129 R574
L AN_LINK# 1 4 L_LAN_LINK# R571 R572 R573 DOCKIN# 17 35 L_LAN_MDI2+
<15,22,33,38> DOCKIN# SEL 4B2
LAN _ACTIVITY# 2 3 L _LAN_ACTIVITY# 1@ 49.9_0402_1% 34 L_LAN_MDI2-
1@ 49.9_0402_1% 5B2
2@ 0_0404_4P2R_5% 1@ 49.9_0402_1% 1@ LAN _ACTIVITY# 19 30 L_LAN_MDI3+

2
<26> LAN_ACTIVITY# L AN_LINK# LED0 6B2 L_LAN_MDI3-
<26> LAN_LINK# 20 LED1 7B2 29
1 1 54 LED2
25 L _LAN_ACTIVITY#
C687 C688 0LED2 L_LAN_LINK#
1LED2 26
C 1@ 0.1U_0402_16V4Z 1@ 0.1U_0402_16V4Z 51 C
2 2 2LED2
5 NC

GND10
GND11
GND12
GND13
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
+2.5V_LAN unpop when use BCM4401(10/100) 1@ PI3L500E_TQFN56~D

1
6
9
13
16
21
24
28
33
39
44
49
53
55
24ST0023-3(SP050004200) for BCM4401(10/100)
24HST1041A-3(SP050002110) for BCM5788M(GbE) T1

1 TCT1 MCT1 24
L_LAN_MDI0+ 2 23 RJ45_MDI0+
TD1+ MX1+
L_LAN_MDI0- 3 TD1- MX1- 22 RJ45_MDI0- 零 件 有 誤 , LED 燈要對調
4 21 JP32
L_LAN_MDI1+ TCT2 MCT2 RJ45_MDI1+ L_LAN_LINK#
5 TD2+ MX2+ 20 12 Amber LED-
L_LAN_MDI1- 6 19 RJ45_MDI1-
TD2- MX2- R565
+3V_LAN 2 1 301_0402_1% 11 Amber LED+
7 TCT3 MCT3 18 SHLD4 16
L_LAN_MDI2+ 8 17 RJ45_MDI2+ RJ45_MDI3- 8
L_LAN_MDI2- TD3+ MX3+ RJ45_MDI2- PR4-
9 TD3- MX3- 16 SHLD3 15
RJ45_MDI3+ 7 PR4+
10 TCT4 MCT4 15
L_LAN_MDI3+ 11 14 RJ45_MDI3+ RJ45_MDI1- 6
L_LAN_MDI3- TD4+ MX4+ RJ45_MDI3- PR2-
12 TD4- MX4- 13
RJ45_MDI2- 5
B PR3- B
RJ45_MDI2+ 4 PR3+
1

0.01U_0402_16V7K 24HST1041A-3
RJ45_MDI1+ 3
R575 R576 PR2+
1 1 1 1 75_0402_1% 75_0402_1% RJ45_MDI0- 2
C683 C684 C685 C686 PR1-
14
2

RJ45_MDI0+ SHLD2
1 PR1+
0.01U_0402_16V7K 13
2 2 0.01U_0402_16V7K
2 2 L _LAN_ACTIVITY# SHLD1
10 Green LED-
0.01U_0402_16V7K R570 2 1 301_0402_1% 9
+3V_LAN Green LED+
TYCO_1566597-1

(AL50)

RJ45_MDI3+ R577 1 2 2@ 0_0402_5%

RJ45_MDI3- R578 1 2 2@ 0_0402_5% RJ4 5_GND 1 2 LAN GND
1 1
RJ45_MDI2+ R579 1 2 2@ 0_0402_5% C689
RJ45_MDI2- R580 1 2 2@ 0_0402_5% 1000P_1206_2KV7K C690 C691
4.7U_0805_10V4Z
1

2 2
reseved for BCM4401(10/100)
R581 R582 0.1U_0402_16V4Z
A
75_0402_1% 75_0402_1% A
2

RJ4 5_GND

LAN BCM5788M/BCM4401KFB Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-2601
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401336
D ate: ¬P 期四, 三月 17, 2005 Sheet 27 of 51
5 4 3 2 1
 A B C D E

1 1

PCI_AD[0..31]
PCI_AD[0..31] <17,23,25,26>

MINI_PCI SOCKET

JP28

TIP 1 2 RING
1 2
3 3 4 4
LAN RESERVED 5 6
5 6
7 7 8 8
D6 9 10 LAN RESERVED
RB751V_SOD323 9 10
11 11 12 12
+3VS_MINIPCI <33> WL_ON 1 2 13 13 14 14
15 15 16 16
L13 PCI_PIRQH# 17 18 W=30mils
<17> PCI_PIRQH# 17 18 +5VS_MINIPCI
1 2 19 20 PCI_ PIRQG#
+3VS 0_0603_5% 19 20 PCI_PIRQG# <17>
W= 40mils 21 21 22 22 +3VS_MINIPCI
23 24 W=40mils
23 24 +3V
CLK_PC I_MINI 25 26 PCI_RST# L14
<14> CLK_PCI_MINI 25 26 PCI_RST# <17,23,25,26,32,33>
27 27 28 28 1 2 +3VS
29 30 W= 40mils 0_0603_5%
<17> PCI_REQ#1 29 30 PCI_GNT#1 <17>
31 31 32 32
PC I_AD31 33 34
2 CLK_PC I_MINI PC I_AD29 33 34 WLANPME# <25,26,32,33> 2
35 35 36 36 W LAN_BT_CLK <34>
37 38 PC I_AD30
37 38
1

PC I_AD27 39 40
R156 PC I_AD25 39 40 PC I_AD28
41 41 42 42
@ 33_0402_5% 43 44 PC I_AD26
<34> WLAN_BT_DATA 43 44
45 46 PC I_AD24
<17,23,25,26> PCI_C/BE#3 45 46
PC I_AD23 47 48 MINI_ IDSEL1 2 PC I_AD18 IDSEL : PCI_AD18
2

47 48 R162 100_0402_5%
49 49 50 50
1 PC I_AD21 51 52 PC I_AD22
PC I_AD19 51 52 PC I_AD20
53 53 54 54
C174 55 56
55 56 PCI_PAR <17,23,25,26>
@ 10P_0402_50V8J PC I_AD17 57 58 PC I_AD18
2 57 58 PC I_AD16
<17,23,25,26> PCI_C/BE#2 59 59 60 60
<17,23,25,26> P C I_ IRDY# 61 61 62 62
63 63 64 64 PCI_FRAME# <17,23,25,26>
<19,25,26,32,33> PM_CLKRUN# 65 65 66 66 PCI_TRDY# <17,23,25,26>
<17,23,25,26> PCI_SERR# 67 67 68 68 PCI_STOP# <17,23,25,26> +5VS_MINIPCI
69 69 70 70
<17,23,25,26> PCI_PERR# 71 71 72 72 PCI_DEVSEL# <17,23,25,26> 1 2 2 1
<17,23,25,26> PCI_C/BE#1 73 73 74 74
PC I_AD14 75 76 PC I_AD15 C178 C181 C173 C175
75 76 PC I_AD13 1000P_0402_50V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_1206_16V4Z
77 77 78 78
PC I_AD12 PC I_AD11 2 1 1 2
79 79 80 80
PC I_AD10 81 82
81 82 PCI_AD9
83 83 84 84
PCI_AD8 85 86
PCI_AD7 85 86 PCI_C/BE#0 <17,23,25,26>
87 87 88 88
89 90 PCI_AD6
PCI_AD5 89 90 PCI_AD4
91 91 92 92
3 PCI_AD2 3
93 93 94 94
PCI_AD3 95 96 PCI_AD0
W=30mils 95 96
+5VS_MINIPCI 97 97 98 98
PCI_AD1 99 100
99 100 +3VS_MINIPCI
101 101 102 102
103 103 104 104 2 2 2 2 2 1
105 105 106 106
107 108 C182 C176 C171 C172 C177 C184
107 108 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_1206_16V4Z
109 109 110 110
1 1 1 1 1 2
111 111 112 112
113 113 114 114
115 115 116 116
117 117 118 118
119 119 120 120
121 121 122 122
1 2 W=30mils 123 124 W=20mils
+5VS 123 124 +3V
L12 0_0603_5% 2
0603 QTC_C102A-040B31-4 C183
0.1U_0402_16V4Z
+5VS_MINIPCI 1

4 4

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401336 C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 28 of 51
A B C D E
 A B C D E F G H

+3V +VDDA
C296
1 2 0.1U_0402_16V4Z

1
28.7K for Module Design (VDDA = 4.702)
R501
U25A 10K_0402_5%
(output = 250 mA)

14
SN74LVC14APWLE_TSSOP14 +5VS +5VAMP
C602 C603 U24
60mil 40mil

2
R495 1U_0402_6.3V4Z L43
<33> BEEP# 1 I O 2 2 1 1 2 1 2 4 VIN VOUT 5 +VDDA
560_0402_5% 2 1 KC FBM-L11-201209-221LMAT_0805

2
1U_0402_6.3V4Z L44 1 2 2 6 1 4.85V
DELAY SENSE or ADJ

1
1 KC FBM-L11-201209-221LMAT_0805 1

7
1 R498 C308 C312 7 1 R496 C313 1
10K_0402_5% ERROR CNOISE 150K_0603_1% 10U_0805_10V4Z
10U_0805_10V4Z 2
8 3 1

1
2 2 SD GND C599

2
+3V C604 22U_1206_16V4Z_V1 SI9182DH-AD_MSOP8

1
1 2 MO NO_IN
2
14

1U_0402_6.3V4Z R497

1
C601 C 1 2 0.1U_0402_16V4Z 51K_0603_1%
P

R494 Q28
3 4 2 1 1 2 2 R502

2
<23> PCM_SPK# I O B
560_0402_5% 2SC2411K_SC59 2.4K_0402_5%
G

U25B 1U_0402_6.3V4Z E

3
SN74LVC14APWLE_TSSOP14
7

C600
R493
2 1 1 2
560_0402_5%

1
1U_0402_6.3V4Z
+3V D12 +AUD_VREF 1 2
R279 RB751V_SOD323 R307 0_0603_5%
10K_0402_5%
14

10mil

2
1 1 1 2
P

5 6 R306 0_0603_5%
<19> SB_SPKR I O C765 C766
G

U25C 1U_0603_10V4Z 0.1U_0402_16V4Z

SN74LVC14APWLE_TSSOP14 2 2
1 2
AC97 Codec
7

R284 0_0603_5%

2 2

+AVDD_AC97
0.1U_0402_16V4Z
GND GNDA
+3VS
L21
1 2 0.1U_0402_16V4Z 1 1 1
+VDDA
FBM-L10-160808-301-T_0603 1 1 1 C317
C369 C366 C316 C314
C348 10U_1206_16V4Z
10U_0805_10V4Z 2 2 2

25

38

9
2 2 2
1 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z

AVDD1

AVDD2

DVDD1

DVDD2
C760 C761
1000P_0402_50V7K 1000P_0402_50V7K
2 2
C608 1 2 1U_0603_10V4Z 14 35 C762 1 2 4.7U_0805_10V4Z
AUX_L LINE_OUT_L LINE_OUTL <31>
C609 1 2 1U_0603_10V4Z 15 36 C763 1 2 4.7U_0805_10V4Z
AUX_R LINE_OUT_R LINE_OUTR <31>
16 JD2 MONO_OUT/VREFOUT3 37

<31> NBA_PLUG 17 JD1 HP_OUT_L 39

27P_0402_50V8J
LINE _IN_L_AC 23 41 C764 1 2
<30> LINE_IN_L_AC LINE_IN_L HP_OUT_R
<30> LINE_IN_R_AC
LINE_IN_R_AC 24 R289
R323 20K_0402_5% CD _R_L LINE_IN_R
<21> INT_CD_L 2 1 BIT_CLK 6 1 2 22_0402_5% ICH_AC_BITCLK <18,34>
R309 2 1 6.8K_0402_5% C332 1 2 1U_0402_6.3V4Z CD_R C_L 18
3 R329 6.8K_0402_5% CD_L R288 3
2 1 SDATA_IN 8 1 2 22_0402_5% ICH_AC_SDIN0 <18>
R328 2 1 20K_0402_5% CD_R_R C339 1 2 1U_0402_6.3V4Z CD_RC_R 20
<21> INT_CD_R CD_R
XTL_IN 2 1 2 CLK_14M_CODEC <14>

1
CD_ GNA C334 1 2 1U_0603_10V4Z CD_G NDA 19 R291
CD_GND R521 0_0402_5%
1 2 C_M IC 21 @ 1M_0402_1% X4 1 2
<31> MIC MIC1
C344 1U_0603_10V4Z
1 2 22 3 1 @ 24.576MHz_16P_3XG-24576-43E1 1

2
C349 1U_0603_10V4Z MIC2 XTL_OUT
1 2 MDC_RC_SPK 13 29 C373 1 2 1000P_0402_50V7K C610 C611
C318 0.1U_0402_16V4Z PHONE AFILT1 @ 22P_0402_50V8J @ 22P_0402_50V8J
MO NO_IN C388 1 2 2
12 PC_BEEP AFILT2 30 2 1000P_0402_50V7K

VREFOUT 28 +AUD_VREF
R522 1 2 22_0402_5% 11
<18,34> ICH_AC_RST# RESET#
27 1U_0402_6.3V4Z
R287 1 VREF
<18,34> IC H _AC_SYNC 2 22_0402_5% 10 SYNC
32 C389 1 2 0.01U_0402_16V7K
R290 1 DCVOL
<18,34> ICH_AC_SDOUT 2 22_0402_5% 5 SDATA_OUT
C612 1 2 1U_0603_10V4Z
1 1
45 31 C641 1 2 1U_0603_10V4Z C368
SDA NC R523 1
46 XTLSEL VREFOUT2 33 2 @ 0_0402_5% C367
34 0.1U_0402_16V4Z
VAUX 2 2
<31,33> EAPD 47 SPDIFI/EAPD DISABLE# 43
2

SCK 44
R321 48
0_0402_5% <31> SPDIFO SPDIFO
NC 40
4 DVSS1 AVSS1 26
1

R315 2 1 CD_ GNA 7 42

<21> CD_AGND
1

4 DVSS2 AVSS2 4
20K_0402_5% R704
U27 ALC250-VD_LQFP48 @ 20K_0402_5%
1

R282 R324
2

0_0402_5% 6.8K_0402_5%
DGND AGND
Compal Electronics, Inc.
2

Title
SCHEMATIC, M/B LA-2601
With 14.318Mhz : R321 POP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
With 24.576Mhz : R321 DEPOP DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401336 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 29 of 51
A B C D E F G H
 5 4 3 2 1

R336 2 1 @ 6.8K_0402_5%

D R349 2 1 @ 6.8K_0402_5% D

LINE _IN_L R342 2 1 6.8K_0402_5% 1 2 C354 LINE _IN_L_AC

<31> LINE_IN_L LINE_IN_L_AC <29>
1U_0402_6.3V4Z

LINE_IN _R R345 2 1 6.8K_0402_5% 1 2 C359 LINE_IN_R_AC

<31> LINE_IN_R LINE_IN_R_AC <29>
1U_0402_6.3V4Z
1 1
C639 C640
@ 1U_0402_6.3V4Z @ 1U_0402_6.3V4Z
<31> AUD_INL 2 2

<31> A U D_INR

C C

B B

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND SCHEMATIC, M/B LA-2601
PROPRIETARY NOTE TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE C
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401336
D ate: ¬P 期四, 三月 17, 2005 Sheet 30 of 51
5 4 3 2 1
 A B C D E

+5VAMP

1
R318
100K_0402_5%

+5VAMP
Speaker Conn.

2
W=40mil SHUTDOW N# JP8
+5VAMP Q29 SPKL+
4

1
D 2N7002_SOT23 SPKL-
SPKR+ 3
1 1 1 2 EC_MUTE <33> 2 1
1

G SPKR-
R657 C346 C347 1
S

3
0.1U_0402_16V4Z 4.7U_0805_10V4Z ACES_85204-0400
10K_0402_5% 2 2

1
D Q31
2

VOL_AMP 2 EAPD
EAPD <29,33>
(0.65V -> 10dB ) HIGH PIN 6,20 ACTIVE G
1

Pin 2 S 2N7002_SOT23

3
R658 LOW PIN 5,23 ACTIVE
1.5K_0402_1% U29
7 22 R348 1 2 100K_0402_5% +AUD_VREF
PVDD SHUTDOWN# +5VAMP
18 15 NBA_PLUG
2

PVDD SE/BTL#
19 VDD PC-BEEP 14 1 2

1
11 BYPASS C364 0.1U_0402_16V4Z MIC_S -->ON Channel
NBA_PLUG BYPASS SPKL- -------------------------
<29> NBA_PLUG 2 HP/LINE# LOUT- 9
VOL_AMP 3 16 SPKR- R708 L -->B1
SPKL+ VOLUME ROUT- 1@ 2.2K_0402_5%
4 LOUT+ LIN 10 H --->B2
SPKR+ 21 8 Docking MIC

2
LINE_OUTL LEFT_2 ROUT+ RIN U66
<29> LINE_OUTL 1 2 5 LLINEIN
C327 0.47U_0603_16V4Z R IGHT_2 23 1 AU D_MIC2 1 6 D OCK_MIC_S
L INE_OUTR RLINEIN GND B2 S
<29> LINE_OUTR 1 2 6 LHPIN GND 12 2 GND VCC 5 +5VAMP
C328 0.47U_0603_16V4Z 20 13 2 2 2 1 AU D_MIC1 3 4
RHPIN GND B1 A MIC <29>
GND 24
17 C361 C356 C873 1@ SN74LVC1G3157
HP_L CLK 1U_0402_6.3V4Z C351 1U_0402_6.3V4Z 1@ 220P_0402_50V7K
1 2
C338 0.47U_0603_16V4Z TPA0232PWP_TSSOP24 1 1 1 2 R699 1 2 2@0_0402_5%
1 2 HP _R 1 1U_0402_6.3V4Z
C335 0.47U_0603_16V4Z 1 C353 Docking : MIC plug ---> HIGH
2 Docking : MIC Unplug ---> LOW 2
C333 0.01U_0402_16V7K
2
0.1U_0402_16V4Z 2

HeadPhone JACK
JP5 JP22
A UD_INR 1 5
<30> A UD_INR 1
AUD_INL 2
<30> AUD_INL 2
AG ND 3 FBM-11-160808-700T_0603 NBA_PLUG_S 4
AU D_MIC2 3 150U_D2_6.3VM 47_0402_5% L22
4 4
AG ND 5 SPKR+ C352 1 2 INTSPK_R1-2 1 2 INTSPK_R1-3 1 2 INTSPK_R1-4 3
D_AUD_OR SPKR+ 5 R356
6 6

+
D_AUD_OL SPKL+ 6 SPKL+ C399 1 INTSPK_L1-2 INTSPK_L1-3
7 7 2 1 2 1 2 INTSPK_L1-4 2
HP_S 8 R362 L24 1

+
D OCK_MIC_S 8 150U_D2_6.3VM 47_0402_5% FBM-11-160808-700T_0603
9 9
SPDIFO 10 FOX_JA6033L-5S3-TR
<29> SPDIFO 10 C376 C370
1@ ACES_87213-1000 330P_0402_50V7K 330P_0402_50V7K
2

R709
1@ 100K_0402_5%
3 3
1

L45 1 2 LINE_ IN_R-1

<30> LINE_IN_R FBM-11-160808-700T_0603
L46 1 2 LIN E_IN_L-1
<30> LINE_IN_L FBM-11-160808-700T_0603

+AUD_VREF

+5VAMP +5VAMP JP17

INT_MIC1 1 MIC JACK

C789 2
2

1
JP21
1 2 R662 5
MOLEX_53398-0290 R352 R351
100K_0402_5%
0.1U_0402_16V4Z 2.2K_0402_5% @ 2.2K_0402_5% 4
1

2
5

U38 LINE_ IN_R-1 3

2 NBA_PLUG_S INT_MIC1 6
P

NBA_PLUG I0 AU D_MIC1 LIN E_IN_L-1

4 O 1 2 2
1 HP_S 1 L23 1
I1
G

FBM-11-160808-700T_0603 1 1
TC7SH32FU_SSOP5 C395 FOX_JA6033L-5S3-TR
3

220P_0402_50V7K C377 C767

R663 2 220P_0402_50V7K 220P_0402_50V7K
2 2
100K_0402_5%
1

4 4

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401336
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B
D ate: ¬P 期四, 三月 17, 2005 Sheet 31 of 51
A B C D E
 A B C D E

SUPER I/O SMsC LPC47N217 +3VS

IR @ 0.1U_0402_16V4Z IR @ 0.1U_0402_16V4Z

1 1 1 1
LPC_A D[0..3] C220 C236 C216 C227
+3VS <18,33> LPC_AD[0..3]
2 2 2 2
R224 1 2 S IO_PD#
IR @ 10K_0402_5% IR @ 4.7U_0805_10V4Z IR @ 0.1U_0402_16V4Z
1 R211 1 2 SIO_SMI# 1
IR @ 10K_0402_5%
U18
LPC_AD0 10 62 RXD1
LAD0 RXD1 RXD1 <36>
LPC_AD1 TXD1

SERIAL I/F
12 LAD1 TXD1 63 TXD1 <36>
LPC_AD2 13 64 D SR#1
LAD2 DSR1# DSR#1 <36>
LPC_AD3 14 1 RTS#1
LAD3 RTS1# RTS#1 <36>
2 CTS#1
CTS1# CTS#1 <36>
LPC_FRAME# 15 3 DTR#1
<18,33> LPC_FRAME# LFRAME# DTR1# DTR#1 <36>
LPC_DRQ#1 16 4 RI#1 +3VS
<18> LPC_DRQ#1 LDRQ# RI1# RI#1 <36>

LPC I/F
5 DCD #1
DCD1# DCD#1 <36>
R545 1 2 17
<17,23,25,26,28,33> PCI_RST# R546 1 PCI_RESET#
2 @ 0_0402_5% S IO_PD# 18 LPCPD# IRRX2 37 IRRX
IRRX <36>

2
<6,17,19,21,33> PLT_RST# IR @ 0_0402_5% FIR 38 IRTXOUT
IRTX2 IRTXOUT <36>
PM_CLKRUN# 19 39 IR MODE R216
<19,25,26,28,33> PM_CLKRUN# CLKRUN# IRMODE/IRRX3 IRMODE <36>
CLK _PCI_SIO 20 @ 10K_0402_5%
<14> CLK_PCI_SIO PCI_CLK
SIO_IRQ R208 2 1 SERIRQ 21 41 INIT#
<19,23,33> SERIRQ SER_IRQ INIT#
IR @ 10K_0402_5% SIO_PME# 6 42 S LCTIN# Base I/O Address
<25,26,28,33> SIO_PME#

1
IRRX R204 1 IO_PME# SLCTIN# LPD0
2 PD0 44
IR @ 10K_0402_5% CLK_SIO_14M 9 46 LPD1 0 *= 02Eh
<14> CLK_14M_SIO CLK14 PD1 LPD2 SIO_GPIO11
CLOCK PD2 47 1 = 04Eh
23 48 LPD3
GPIO40 PD3

2
PARALLEL I/F
24 49 LPD4
GPIO41 PD4 LPD5 R219
25 GPIO42 PD5 50
27 51 LPD6 IR @ 1K_0402_5%
GPIO43 PD6 LPD7

GPIO
28 GPIO44 PD7 53
29 55 LPTSLCT
LPTSLCT <38>

1
GPIO45 SLCT LPTPE
30 GPIO46 PE 56 LPTPE <38>
31 57 L PTBUSY
GPIO47 BUSY LPTBUSY <38>
2 32 58 LPTACK# 2
GPIO10 ACK# LPTACK# <38>
SIO_GPIO11 33 59 LPTERR#
GPIO11/SYSOPT ERROR# LPTERR# <38>
CLK_SIO_14M CLK _PCI_SIO SIO_SMI# 34 60 LPTAFD#
SIO_IRQ GPIO12/IO_SMI# ALF# LPTSTB#
35 GPIO13/IRQIN1 STROBE# 61
2

36 GPIO14/IRQIN2
R202 40
@ 10K_0402_5% R225 GPIO23
@ 10_0402_5% 8 7 +3V
VSS VTR
22 11 1
1

VSS VCC
1 1 43 VSS POWER VCC 26
C225 52 45 C222
@ 15P_0402_50V8J C239 VSS VCC
VCC 54 +3VS
@ 15P_0402_50V8J 2
2 2 IR @ LPC47N217_STQFP64
IR @ 0.1U_0402_16V4Z

+5V_PRN

Close to Docking
+5VS 2 1
3 D5 LPTSTB# R43 1@ 2 33_0402_5% R_LPTSTB# 3
1 R_LPTSTB# <38>
1@ RB420D_SOT23
LPTAFD# R36 1 1@ 2 33_0402_5% AFD#/3M#
AFD#/3M# <38>
+5V_PRN INIT# R22 1 1@ 2 33_0402_5% LPTINIT#
LPTINIT# <38>
+5V_PRN
S LCTIN# R35 1@
1 2 33_0402_5% LPTSLCTIN#
LPTSLCTIN# <38>
LPTSLCT F D4
LPTPE F D5
L PTBUSY F D6
LPTACK# F D7
RP3
RP6 LPD0 F D0
10

1 8 FD0 <38>
9
8
7
6

RP5 LPD1 F D1
10

2 7 FD1 <38>
9
8
7
6

LPD2 3 6 F D2
FD2 <38>
LPD3 4 5 F D3
FD3 <38>
1@ 68_1206_8P4R_5%

RP2
1
2
3
4
5

1@ 2.7K_10P8R_1206_5% LPD7 4 5 F D7
FD7 <38>
1
2
3
4
5

1@ 2.7K_10P8R_1206_5% LPD6 3 6 F D6
FD6 <38>
+5V_PRN LPD5 2 7 F D5
FD5 <38>
LPD4 1 8 F D4
FD4 <38>
+5V_PRN F D3
F D2 1@ 68_1206_8P4R_5%
AFD#/3M# F D1
4
LPTERR# F D0 4
LPTINIT#
LPTSLCTIN#

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401336 C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 32 of 51
A B C D E
 5 4 3 2 1

+RTCVCC +3VALW
+3VALW

2
KBA[0..19] R469 R199
KBA[0..19] <35> L29 @ 0_0402_5% 0_0402_5% For EC Tools
ADB[0..7] 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2
ADB[0..7] <35> +5VALW
1 1 C215 1 1 2 2 FBM-L11-160808-800LMT_0603

1
C238 1
C206 C219 C241 C231 JP27
1000P_0402_50V7K 1000P_0402_50V7K C557 1 1 1
L16 2 2 2 2 1 1 C218 C217 1
2 2

ECAGND
ECAGND 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z
1 2 3 3
FBM-L11-160808-800LMT_0603 0.1U_0402_16V4Z 1U_0603_10V4Z EC_TDO 4
2 2 4
D 5 5 D
6 6
7

123
136
157
166

161

159
7

16
34
45

95

96
8 8
U15 9
LPC_AD0 KSI[0..7] 9
15 10

VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCCA

AGND

VCCBAT

BATGND
<18,32> LPC_AD0 LAD0 KSI[0..7] <34> 10
C577 LPC_AD1 14 49 KSO0
<18,32> LPC_AD1 LAD1 GPOK0/KSO0 KSO[0..15]
@ 22P_0402_50V8J LPC_AD2 13 50 KSO1 @ @96212-1011S
<18,32> LPC_AD2 LAD2 GPOK1/KSO1 KSO[0..15] <34>
2 1 R482 2 1 @ 33_0402_5% LPC_AD3 10 51 KSO2
<18,32> LPC_AD3 LAD3 GPOK2/KSO2 KSO3
<18,32> LPC_FRAME#
LRST#
9 LFRAME# LPC Interface GPOK3/KSO3 52
KSO4
165 LRST#/GPIO2C GPOK4/KSO4 53

ENE-KB910-B4
18 56 KSO5
<14> CLK_PCI_LPC LCLK GPOK5/KSO5
7 57 KSO6 Analog Board ID definition,
<19,23,32> SERIRQ SERIRQ GPOK6/KSO6
25 58 KSO7
<19,25,26,28,32> PM_CLKRUN#
24
CLKRUN#/GPIO0C * GPOK7/KSO7
59 KSO8 Please see page 3.
+3VALW LPCPD#/GPIO0B * GPOK8/KSO8 KSO9
GPOK9/KSO9 60
FR D# 150 61 KSO10 +3VALW
<35> F RD# RD# GPOK10/KSO10
FW R# KSO11

Internal Keyboard
<35> FW R# 151 WR# GPOK11/KSO11 64
2

FSEL# 173 65 KSO12

<35> FSEL# MEMCS# GPOK12/KSO12
R205 SELIO# 152 66 KSO13
IOCS# GPOK13/KSO13

2
10K_0402_5% ADB0 138 67 KSO14
ADB1 D0 GPOK14/KSO14 KSO15 R170
139 D1 GPOK15/KSO15 68
ADB2 140 153 KSO16 Ra 100K_0402_5%
1

D2 GPOK16/KSO16 KSO16 <34>

ADB3 141 154
<25,26,28,32> 1394_PME# D3 GPOK17/KSO17
ADB4 144
<25,26,28,32> ONBD_LAN_PME#

1
ADB5 D4 KSI0 AD_BID0
<25,26,28,32> WLANPME# 145 D5 GPIK0/KSI0 71

X-BUS Interface
EC_PME# ADB6 146 72 KSI1
<25,26,28,32> LAN_PME# D6 GPIK1/KSI1

2
ADB7 147 73 KSI2 1
<25,26,28,32> SIO_PME# KBA0 D7 GPIK2/KSI2 KSI3 R168 C186
124 A0 GPIK3/KSI3 74
KBA1 125 77 KSI4 Rb
R478 1 0_0402_5% ENBKL KBA2 A1/XIOP_TP GPIK4/KSI4 KSI5 0_0402_5% 0.1U_0402_16V4Z
<8,16> GMCH_ENBKL 2 126 A2 GPIK5/KSI5 78
KBA3 KSI6 2
127 79

1
C KBA4 A3 GPIK6/KSI6 KSI7 C
128 A4/DMRP_TP GPIK7/KSI7 80
R547 1 2 @ 0_0402_5% LRST# KBA5 131
<17,23,25,26,28,32> PCI_RST# KBA6 A5/EMWB_TP INVT_PWM +3VALW
132 A6 GPOW0/PWM0 32 INVT_PWM <16>
R548 1 2 0_0402_5% KBA7 133 33 BEEP#
<6,17,19,21,32> PLT_RST# A7 GPOW1/PWM1 BEEP# <29>
KBA8 143 36 TRICKLE
A8 FAN2PWM/GPOW2/PWM2 TRICKLE <44>

2
KBA9 142 37 ACOFF
A9 GPOW3/PWM3 ACOFF <43>
KBA10 135 Pulse Width GPOW4/PWM4 38 A/B#USE R479
A10 A/B#USE <44> 10K_0402_5%
KBA11 134 39 EC_ON
A11 GPOW5/PWM5 EC_ON <39>
+3VALW KBA12 130 40 EC_LID_OUT#
A12 GPOW6/PWM6 EC_LID_OUT# <19>
SKU ID definition, KBA13 129 43 EC_MUTE
EC_MUTE <31>

1
KBA14 A13 FAN1PWM/GPOW7/PWM7 D33
121
Please see page 3. KBA15 120
A14
2 ON/O FF
A15 GPWU0 ON/OFF <39>
2

KBA16 113 26 2 1
A16 GPWU1 AC IN <19,42,45>
R183 KBA17 112 29
100K_0402_5% KBA18 A17 GPWU2 PM_SLP_S3#
Rc 104 A18 GPWU3 30 PM_SLP_S3# <19>
KBA19 103 Wake Up Pin 44 PM_SLP_S5# CH751H-40_SC76
A19 GPWU4 PM_SLP_S5# <19>
CD_DK# 108 76 EN_BT#
1

<21> CD_DK# A20/GPIO23 GPWU5 EN_BT# <34>

SKU_ID +3VALW 2 1 105 172 EC_PME#
R467 100K_0402_5% E51CS#/GPIO20/ISPEN TIN1/GPWU6
TIN2/FANFB2/GPWU7 176
2

1 KB_CLK 110 2 1 ECAGND

<38> KB_CLK PSCLK1
R184 C207 KB_DATA 111 81 BATT_TEMP C209 0.01U_0402_16V7K
<38> KB_DATA PSDAT1 GPIAD0/AD0 BATT_TEMPA <44>
Rd PS_CLK 114 82 SKU_ID
<38> PS_CLK PSCLK2 GPIAD1/AD1
0_0402_5% 0.1U_0402_16V4Z PS_DATA BATT_OVP ECAGND
2 <38> PS_DATA
TP_CLK
115 PSDAT2PS2 Interface GPIAD2/AD2 83
BATT_TEMPB
BATT_OVP <43> 2 1
C844 0.01U_0402_16V7K
116 84
1

<34> TP_CLK PSCLK3 GPIAD3/AD3 BATT_TEMPB <44>

TP_DATA 117 Analog To Digital 87
<34> TP_DATA PSDAT3 GPIAD4/AD4
88 DOCKIN#
EC_SMB_CK1 GPIAD5/AD5 AD_BID0 DOCKIN# <15,22,27,38>
<35,44> EC_SMB_CK1 163 SCL1 GPIAD6/AD6 89
EC_SMB_DA1 164 90
<35,44> EC_SMB_DA1 SDA1 GPIAD7/AD7
+5VS EC_SMB_CK2 169 SMBus
<4,44> EC_SMB_CK2 SCL2
RP81 EC_SMB_DA2 170 99 DAC_BRIG
<4,44> EC_SMB_DA2 SDA2 GPODA0/DA0 DAC_BRIG <16>
1 8 KB_CLK 100
GPODA1/DA1 EZ_SUSON <38>
B 2 7 KB_DATA 8 101 IR EF B
<38> EZ_SMBUS_ON# GPIO04 GPODA2/DA2 IR EF <43>
3 6 PS_CLK EC_SCI# 20 102 EN_DFAN1#
<19> EC_SCI# GPIO07 GPODA3/DA3 EN_DFAN1 <36>
4 5 PS_DATA 21 Digital To Analog 1 W L_ON
<38> EZ_PE_REQ1# GPIO08 GPODA4/DA4 W L_ON <28>
22 42 CRY11 R476 2 CRY2
<19,38> EZ_PE_REQ2# GPIO09 GPODA5/DA5
4.7K_0804_8P4R_5% ENBKL 27 47 @ 20M_0603_5%
GPIO0D GPODA6/DA6 EZ_MAINON <38>

2
+3VALW BKOFF# 28 174
<16> BKOFF# GPIO0E GPODA7/DA7 EZ_PERST# <38>
RP84 FSTCHG 48 R475
<43,44> FSTCHG GPIO10
1 8 EC_SMI# EC_SMI# 62 85 PW R_LED#
<19> EC_SMI# GPIO13 *GPIO18/XIO8CS# PW R_LED# <34>
2 7 FR D# 63 86 PW R_SUSP_LED# 0_0402_5%
<21> IDE_LED# GPIO14 *GPIO19/XIO9CS# PW R_SUSP_LED# <34>
3 6 SELIO# 69 91 BATT_FULL_LED#
<34> EN_WL# BATT_FULL_LED# <34>

1
FSEL# GPIO15 *GPIO1A/XIOACS# BATT_CHGI_LED#
4 5 <19> EC_SW I# 70 GPIO16 GPIO *GPIO1B/XIOBCS# 92 BATT_CHGI_LED# <34>
75 Expanded I/O * GPIO1C/XIOCCS# 93 W L_ON_LED#
<26> EN_W OL# GPIO17 W L_ON_LED# <34>
10K_0804_8P4R_5% PE_REQ1# 109 94 BT_ON_LED# 1 1
+5VALW <14> PE_REQ1# GPIO24 *GPIO1D/XIODCS# BT_ON_LED# <34>
LID_SW # 118 97 E_MAIL_LED# C576 C575
<36> LID_SW # GPIO25 *GPIO1E/XIOECS# E_MAIL_LED# <34>

4
RP86 BT_ON# 119 98 MEDIA_LED#
<34> BT_ON# GPIO26 * GPIO1F/XIOFCS# MEDIA_LED# <34>

10P_0402_50V8J

10P_0402_50V8J
1 8 EC_SMB_CK1 SYSON 148 X1

IN

OUT
<40,46> SYSON GPIO27 2 2
2 7 EC_SMB_DA1 SUSP# 149 171 FAN_SPEED1
<16,35,40,47> SUSP# GPIO28 GPIO2E/TOUT1/FANFB1 FAN_SPEED1 <36>
3 6 EC_SMB_CK2 VR_ON 155 12 DPLL_TP
<46,48> VR_ON GPIO29 DPLL_TP/GPIO06/FANFB3
4 5 EC_SMB_DA2 156 FANTEST_TP/GPIO05/FAN3PWM 11 TEST_TP
<23> CARD_LED# GPIO2A
PE_REQ2#

NC

NC
<14> PE_REQ2# 162 GPIO2B
4.7K_0804_8P4R_5% PBTN_OUT# 168 175 EC_THERM#
<19> PBTN_OUT# GPIO2D EC_THERM# <19>
Timer PinTOUT2/GPIO2F

3
+5VS
55 FnLock#/GPIO12* E51IT0/GPIO00 3 EC_RSMRST# <19>
0.1U_0402_16V4Z CAPSLED# 54 4
<34> CAPSLED# CapLock#/GPIO011* E51IT1/GPIO01
2 1 TP_CLK 2 1 <34> NUMLED#
NUMLED# 23 NumLock#/GPIO0A * E51RXD/GPIO21/ISPCLK 106 EAPD
EAPD <29,31>
4.7K_0402_5% R172 C578 41 107 EC_TDO 32.768KHZ_12.5P_1TJS125DJ2A073
<18> PHDD_LED# ScrollLock#/GPIO0F * E51TXD/GPIO22/ISPDAT
2 1 TP_DATA +3VALW 2 1 19 ECRST# MISC CRY2
4.7K_0402_5% R171 47K_0402_5% R480 5 158 R474 1 2 @ 0_0402_5% RTC_CLK
<18> EC_GA20 GA20/GPIO02 XCLKI RTC_CLK <19>
6 160 CRY1
<18> EC_KBRST# KBRST#/GPIO03 XCLKO
31
GND
GND
GND
GND
GND
GND

ECSCI#
+3VALW
A A
KB910Q B4_LQFP176
17
35
46
122
137
167

2 1 KBA1 1 2 ENBKL
1K_0402_5% R175 R481 @ 120K_0402_5%
2 1 KBA4 1 2 DPLL_TP
1K_0402_5% R174 R229 1K_0402_5%
2 1 KBA5 1 2 TEST_TP
1K_0402_5% R173 R228 1K_0402_5%
2 1 LID_SW # Compal Electronics, Inc.
20K_0402_5% R473 Title
2 1 DOCKIN# SCHEMATIC, M/B LA-2601
10K_0402_5% R683 PROPRIETARY NOTE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE 401336 C
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期四, 三月 17, 2005 Sheet 33 of 51
5 4 3 2 1
 JP3
1 2 ON/OFFBTN# <39>
CAPSLED#
3 4 NUMLED# CAPSLED# <33>
5 6 MEDIA_LED# NUMLED# <33>
7 8 E_MAIL_LED# MEDIA_LED# <33>
9 10 KSO16 E_MAIL_LED# <33>
+5VALW 11 12 KSO16 <33>
K SI0
13 14 K SI1
15 16 K SI2
MDC CONN. +3V
17
19
18
20
K SI3

1 SUYIN_80065AR-020G2T
JP30 (CL56)
C253
1 2 1U_0805_25V4Z
GND1 RES0 2
<18,29> ICH_AC_SDOUT 3 IAC_SDATA_OUT RES1 4
5 GND2 3.3V 6 +3V
IC H_AC_SYNC 7 8
<18,29> IC H_AC_SYNC
<18> ICH_AC_SDIN1 1
R486
2 ICHAC_SDIN1_MDC
22_0402_5%
9
IAC_SYNC
IAC_SDATA_IN
GND3
GND4 10
ICHA C_BITCLK_MDC 1
TO M/B
<18,29> ICH_AC_RST# 11 IAC_RESET# IAC_BITCLK 12 2 ICH_AC_BITCLK <18,29>
R485 22_0402_5% JP9
+5VALW 1 1
2 2
3

13
14
15
16
17
18
19
20
3
+5VS 4 4
FOX_QT8A0121-4011~D 5

13
14
15
16
17
18
19
20
5
6 6
TP_CLK 7
<33> TP_CLK 7
Connector for MDC Rev1.5 TP_DATA 8
<33> TP_DATA 8
(EMW80) 9 9
EN_WL# 10
<33> EN_WL# 10
EN_BT# 11
<33> EN_BT# 11
W L_ON_LED# 12
<33> W L_ON_LED# 12
BT_ON_LED# 13
<33> BT_ON_LED# 13
<33> PW R_SUSP_LED# 14 14
<33> PW R_LED# 15 15
<33> BATT_FULL_LED# 16 16
<33> BATT_CHGI_LED# 17 17
18 18
19 19
20 20

ACES_85201-2005

KSI[0..7]
KSI[0..7] <33> INT_KBD CONN. BlueTooth Interface
KS O[0..15]
KSO[0..15] <33>
(Right)
+3VALW
JP14
KSO7 C625 100P_0402_25V8K KSO15 C613 100P_0402_25V8K KSO15 1 2 KSO15
KSO14 1 2 KSO14
3 3 4 4

3
S
KSO6 C626 100P_0402_25V8K KSO14 C614 100P_0402_25V8K KSO13 5 6 KSO13
KSO12 5 6 KSO12
G
7 7 8 8 <33> BT_ON# 2
KSO5 C627 100P_0402_25V8K KSO13 C615 100P_0402_25V8K K SI0 9 10 K SI0
KSO11 9 10 KSO11 Q12
11 12 D

1
KSO4 C628 100P_0402_25V8K KSO12 C616 100P_0402_25V8K KSO10 11 12 KSO10 BT@SI2301DS_SOT23
13 13 14 14
K SI1 15 16 K SI1
KSO3 C629 100P_0402_25V8K K SI0 C617 100P_0402_25V8K K SI2 15 16 K SI2
17 17 18 18
KSO9 19 20 KSO9
K SI4 C630 100P_0402_25V8K KSO11 C618 100P_0402_25V8K K SI3 19 20 K SI3
21 21 22 22
KSO8 23 24 KSO8 JP13
KSO2 C631 100P_0402_25V8K KSO10 C619 100P_0402_25V8K KSO7 23 24 KSO7 BT_VCC
25 25 26 26 1
KSO6 27 28 KSO6
KSO1 C632 100P_0402_25V8K K SI1 C620 100P_0402_25V8K KSO5 27 28 KSO5 USB20_P5 R95 BT@0_0402_5% USB5+ 2
29 29 30 30 <19> USB20_P5 3
KSO4 31 32 KSO4 USB20_N5 R94 BT@0_0402_5% USB5-
31 32 <19> USB20_N5 4
KSO0 C633 100P_0402_25V8K K SI2 C621 100P_0402_25V8K KSO3 33 34 KSO3
K SI4 33 34 K SI4 R116 1 5
35 35 36 36 <28> WLAN_BT_DATA 2 BT@0_0402_5% 6
K SI5 C634 100P_0402_25V8K KSO9 C622 100P_0402_25V8K KSO2 37 38 KSO2 <28> W LAN_BT_CLK R226 1 2 BT@0_0402_5%
KSO1 37 38 KSO1 7
39 39 40 40 8
K SI6 C635 100P_0402_25V8K K SI3 C623 100P_0402_25V8K KSO0 41 42 KSO0
K SI5 41 42 K SI5 BT_VCC BT@ACES_87212-0800
43 43 44 44
K SI7 C636 100P_0402_25V8K KSO8 C624 100P_0402_25V8K K SI6 45 46 K SI6 Bluetooth Connector
K SI7 45 46 K SI7
47 47 48 48 1 1
C140 C151

ACES_85203-2402 BT@10U_0805_10V4Z
2 2 BT@0.1U_0402_16V4Z
(Left) (CL56)

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401336 C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 34 of 51
 SB_INT_FLASH_SEL# <19>

13
KB A[0..19] U10D
<33> KBA[0..19]

OE#
ADB[0 ..7] INT_FLASH_SEL 11 12
<33> ADB[0..7] O I SUS_STAT# <19>

SN74LVC125APWLE_TSSOP14
+3VALW

2
U16 C638 +3VALW
0.1U_0402_16V4Z +3VALW +3VALW 0.1U_0402_16V4Z
KBA18 1 C153 1
1 NC VCC 32 C214 2

2
KBA16 2 31 FWE#
A16 WE*

1
KBA15 3 30 KBA17 1 2 R192 R533
KBA12 A15 A17 KBA14 100K_0402_5% INT_FLASH_EN# R503 1
4 A12 A14 29 SUSP# <16,33,40,47> 10K_0402_5% 2
KBA7 5 28 KBA13 0.1U_0402_16V4Z
A7 A13

2
KBA6 KBA8 100K_0402_5%

G
6 27

1
A6 A8

5
KBA5 KBA9 U14

10
7 26

2
KBA4 A5 A9 KBA11 U10C
8 25 2 1 3

P
A4 A11 I0 EC_FLASH# <19>
KBA3 9 24 F RD# FWE# 4

OE#
KBA2 A3 OE* KBA10 F RD# <33> O INT_FSEL# 1 FSEL#
10 A2 A10 23 I1 1 2 8 O I 9

G
KBA1 11 22 FSEL# Q23 R504 22_0402_5%
KBA0 A1 CE* ADB7 FSEL# <33> TC7SH32FU_SSOP5 2N7002_SOT23
12 21

3
ADB0 A0 DQ7 ADB6
13 DQ0 DQ6 20
ADB1 14 19 ADB5 SN74LVC125APWLE_TSSOP14
DQ1 DQ5 FW R# <33>
ADB2 15 18 ADB4
DQ2 DQ4 ADB3
16 VSS DQ3 17

29F040/SST39VF040_PLCC

(CL55)

1MB Flash ROM

U28
+3VALW 1MB ROM Socket
KBA0 21 31
KBA1 A0 VCC0 +5VALW +5VALW
20 A1 VCC1 30 1
KBA2 19 C155
KBA3 A2 JP15
18 A3

1
KBA4 17 25 ADB0 @ 0.1U_0402_16V4Z KBA16 KBA17
KBA5 A4 D0 ADB1 2 KBA15 1 2 C187 1
16 A5 D1 26 3 4 2 0.1U_0402_16V4Z R164
KBA6 15 27 ADB2 KBA14
KBA7 A6 D2 ADB3 KBA13 5 6 KBA19 100K_0402_5%
14 A7 D3 28 7 8
KBA8 8 32 ADB4 KBA12 KBA10

2
KBA9 A8 D4 ADB5 KBA11 9 10 ADB7 U11
7 A9 D5 33 11 12
KBA10 36 34 ADB6 KBA9 ADB6 8 1
KBA11 A10 D6 ADB7 KBA8 13 14 ADB5 VCC A0
6 A11 D7 35 15 16 7 WP A1 2
KBA12 5 FWE# ADB4 6 3
A12 17 18 <33,44> EC_SMB_CK1 SCL A2
KBA13 4 RESET# +3VALW 5 4
A13 19 20 <33,44> EC_SMB_DA1 SDA GND
KBA14 3 10 RESET# 1 2 +3VALW INT_FLASH_EN#
KBA15 A14 RP# R505 INT_FLASH_SEL 21 22 AT24C16N10SC-2.7_SO8
2 A15 NC 11 23 24
KBA16 1 12 @ 100K_0402_5% KBA18 ADB3
KBA17 A16 READY/BUSY# KBA7 25 26 ADB2
40 A17 NC0 29 27 28
KBA18 13 38 KBA6 ADB1
KBA19 A18 NC1 KBA5 29 30 ADB0
37 A19 31 32
KBA4 F RD#
33 34

1
INT_FSEL# 22 KBA3
F RD# CE# KBA2 35 36 FSEL# R167
24 OE# GND0 23 37 38
FWE# 9 39 KBA1 KBA0
WE# GND1 39 40 100K_0402_5%
@ SUYIN_80065AR-040G2T

2
@ SST39VF080-70_TSOP40

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401336
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 35 of 51
 FAN Conn
+12VALW +5VS
Close to Docking
1 2
C522 R664 1 1@ 2 0_0402_5% DTR#
<32> DTR#1 DTR# <38>
0.1U_0402_16V4Z R665 1 1@ 2 0_0402_5% RTS#
<32> RTS#1 RTS# <38>
R666 1 1@ 2 0_0402_5% TXD
<32> TXD1 TXD <38>

8
R667 1 1@ 2 0_0402_5% CTS#
<32> CTS#1 CTS# <38>

1
R668 1 1@ 2 0_0402_5% R I#

P
<32> RI#1 R I# <38>

1
EN_ DFAN1 3 C Q46 D3 C108 R669 1 1@ 2 0_0402_5% RXD
<33> EN_DFAN1 +IN <32> RXD1 RXD <38>
1 E N_FAN1 1 2 2 FMMT619_SOT23 1SS355_SOD323 10U_1206_16V4Z R670 1 1@ 2 0_0402_5% D CD#
<32> DCD#1 D C D# <38>

2
OUT B R671 1@ 0_0402_5% DS R#
2 1 2 -IN <32> DSR#1 1 2 DSR# <38>
R441 2 E

2
G
R435 U37A 100_0402_5%
10K_0402_5% LM358A_SO8 C523 FA N1

4
@ 0.1U_0402_16V4Z JP12

1
1
D26 3
1N4148_SOT23 2
1 2 1
R440 8.2K_0402_5%
ACES_85205-0300

2
+3VS R88 1 2 10K_0402_5%
FOXCONN_JM34613-L002-TR

<33> FAN_SPEED1 JP48

2 2 3 3 5 5
4 6 SW1
C107 C106 4 6
2 1 LID_SW # <33>

1
2
@ 1000P_0402_50V7K @ 1000P_0402_50V7K
1 1

1
2
4 3

3
SATA HDD CONN ESE11MV9_4P

1
1
JP50 L47 L48
0_0603_5% 0_0603_5% (ELW80)
1 D30 @ PSOT03C
SATA_ITX_C_DRX_P0 GND
2

2
2
<18> SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_N0 HTX+
<18> SATA_ITX_C_DRX_N0 3 HTX-
4 JP47
SATA_DTX_C_IRX_N0 GND TIP
<18> SATA_DTX_C_IRX_N0 5 HRX- 1
SATA_DTX_C_IRX_P0 6 MRING
<18> SATA_DTX_C_IRX_P0 HRX+ 2
7 GND
MOLEX_53398-0290
(ELW80)
8
+3VS 9
VCC3.3
VCC3.3
10 VCC3.3
11 GND
12 GND
13 GND
+5VS 14 VCC5
15 VCC5
16 VCC5
17 GND
18 RESERVED
19 GND
20 VCC12
21
22
VCC12
VCC12 FIR Module
@ @OCTEK_STA-22RD1_22P
R366
IR @ 4.7_1206_5%
+3VS 1 2 +IR_ANODE
C396
+3VALW +5VS 1 1 2 1 2
R365

+
C385 IR @ 4.7_1206_5% @ 150U_D2_6.3VM
1

+3VS IR @ 22U_1206_16V4Z_V1
1 2
R689 C856
43K_0402_5% +

2
R368 IR 1
2

@ 150U_D2_6.3VM 2 IR @ 47_1206_5%
IRED_A 1
2 3 IRTXOUT
<19> SATA_DET# IRED_C TXD IRTXOUT <32>
IRRX 4 5 IR MODE
<32> IRRX IRMODE <32>

1
IR_3VS RXD SD/MODE R316 1
6 VCC MODE 7 2
2

1 1 8 GND
R690 Close to SATA HDD C401 @ 0_0402_5%
RA C402 IR @ IR_VISHAY_TFDU6101E-TR4_8P
@ 0_0402_5% IR @ 0.1U_0402_16V4Z
IR @ 10U_1206_16V4Z 2 2
1

SD/MODE: SHUTDOWN MODE, HIGH ACTIVE

MODE: HIGH/LOW SPEED SELECT

SATA Device Status RA

Presence POP Compal Electronics, Inc.
Removed NO POP
Title
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401336
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 36 of 51
 5 4 3 2 1

+USB_AS +USB_AS

470P_0402_50V7K 470P_0402_50V7K
1 1
1 C771 1
D
+ C770 + C769 D
C768
150U_D2_6.3VM 150U_D2_6.3VM
+5VALW +USB_AS 2 2 2 2
U59
1 GND OUT 8
2 IN OUT 7
3 6 JP43
IN OUT
1 4 EN# FLG 5 USB_OC#0 <19> 1 VCC VCC 5
C776 USB20_N0 2 6 USB20_N6
R659 <19> USB20_N0 D0- D1- USB20_N6 <19>
4.7U_0805_10V4Z G528_SO8 USB20_P0 3 7 USB20_P6
<19> USB20_P0 D0+ D1+ USB20_P6 <19>
1 2 USB_OC#6 <19> 4 VSS VSS 8
2

10K_0402_5% 1 10 G2 G1 9 1
1 1 12 11 1 C775
SYSON# C773 G4 G3 C774
C874 C772 @ 10P_0402_50V8J
0.1U_0402_16V4Z @ 10P_0402_50V8J 2 @ 10P_0402_50V8J SUYIN_020122MR008S540ZU @ 10P_0402_50V8J 2
2 2 2
(CL55)

+USB_BS

C C
470P_0402_50V7K
1
1
+ C778
C777
150U_D2_6.3VM
2 2
+5VALW +USB_BS U67
U60 USB20_N0 1 6 USB20_P0
AS SDA
1 GND OUT 8
2 7 JP44 2 5 +USB_AS
IN OUT GND ALERT
3 IN OUT 6 1
1 4 5 USB20_N2 USB20_P6 3 4 USB20_N6
EN# FLG <19> USB20_N2 2 VDD SCL
C781 USB20_P2
R660 <19> USB20_P2 3
4.7U_0805_10V4Z G528_SO8 TOP
4 @ IP4220CZ6_SOT23-6
1 2 USB_OC#2 <19> 1
2 suyin_020167mr004s511zu_4p
1
C779 C780
10K_0402_5% @ 10P_0402_50V8J @ 10P_0402_50V8J
1 2
(ELW80) (Left)
SYSON# U68
<40> SYSON# 2
C875 1 6
0.1U_0402_16V4Z AS SDA
2
2 GND ALERT 5 +USB_BS
USB20_P2 3 4 USB20_N2
VDD SCL
BOT
@ IP4220CZ6_SOT23-6
B B

U69
1 AS SDA 6

2 GND ALERT 5 +USB_CS

2 2 USB20_N4 3 4 USB20_P4
+5VALW +USB_CS C784 C785 VDD SCL
U65 TOP
1 8 @ 10P_0402_50V8J @ 10P_0402_50V8J @ IP4220CZ6_SOT23-6
GND OUT 1 1 JP45
2 IN OUT 7
3 IN OUT 6 1
1 4 5 USB20_P4
EN# FLG <19> USB20_P4 2
C859 USB20_N4
<19> USB20_N4 3
4.7U_0805_10V4Z G528_SO8 R700 +USB_CS 4
1 2 USB_OC#4 <19> 1
2 SUYIN_2569A-04G3T
1
10K_0402_5% +
1 C782 C783
SYSON# 150U_D2_6.3VM 470P_0402_50V7K
<40> SYSON# 2 2
C876
0.1U_0402_16V4Z (EAX00) (Top)
2

A A

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401336
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 37 of 51
5 4 3 2 1
 A B C D E

+5VS
+3VALW +3VALW
D14 +3VS
1@ 0.1U_0402_16V4Z R525
C11 2 1 2 1
D _DVI_DET 1 2
<22> D_DVI_DET

2
1@ 10K_0402_5% U2 1@ RB411D_SOT23
R13 2 1 1 1@ 100K_0402_5% R528

P
B DOCKIN#
4 DOCKIN# <15,22,27,33> 1@ 0_0402_5%
Y

1
1 2 MZIN_EM# 2 A

G
R17

1
1@ 10K_0402_5% 1@ TC7SH08FU_SSOP5 R526

3
1@ 4.7K_0402_5% R527 R529 1@ 6.8K_0402_5%
1
Docking Conn. 2 1 +3VS
1

2
JP23

G
D_LAN_MDI0+ 1 63 1@ 4.7K_0402_5%
<27> D_LAN_MDI0+ LAN0+ GND DE_DVI_SDATA 1 3 D_DVI_SDATA
D_LAN_MDI0- D _DVI_DET D_DVI_SDATA <22>
2 64

S
<27> D_LAN_MDI0- LAN0- DVI_DET
3 65 DE_DVI_SDATA Q20
GND DVI_DAT

2
D_LAN_MDI1+ 1@ BSS138_SOT23

G
<27> D_LAN_MDI1+ 4 LAN1+ GND 66
D_LAN_MDI1- 5 67 DE _DVI_SCLK
<27> D_LAN_MDI1- LAN1- DVI_CLK
6 68 MZIN_EM# DE _DVI_SCLK 1 3 D_ DVI_SCLK
GND EZIN_EM# D _MIC_S D_DVI_SCLK <22>
7 69

S
D _LAN_LINK# GND MIC_S D_AUD_INR Q21
<27> D_LAN_LINK# 8 LAN_LINK# AUD_INR 70
R_LPTSTB# 9 71 D_AUD _INL 1@ BSS138_SOT23 2 1
<32> R_LPTSTB# PP_STB# AUD_INL +3VS
AFD#/3M# 10 72 D_A GND R530
<32> AFD#/3M# PP_AFD# AGND
F D0 11 73 D_A UD_MIC2 1@ 6.8K_0402_5%
<32> FD0 PP_D0 AUD_MIC
LPTERR# 12 74 D_A UD_OR
<32> LPTERR# PP_ERR# AUD_OR
F D1 13 75 D _AUD_OL
<32> FD1 PP_D1 AUD_OL
LPTINIT# 14 76 D_A GND
<32> LPTINIT# PP_INIT# AGND
F D2 15 77
<32> FD2 PP_D2 GND
LPTSLCTIN# 16 78 D_CRT_HSYNC
<32> LPTSLCTIN# PP_SLIN# VGA_HS D_CRT_HSYNC <15>
F D3 17 79 D_CRT_V SYNC
<32> FD3 PP_D3 VGA_VS D_CRT_VSYNC <15>
F D4 18 80 D _DDC_DATA
<32> FD4 PP_D4 VGA_DAT D_DDC_DATA <15>
F D5 19 81 D_DD C_CLK
<32> FD5 PP_D5 VGA_CLK D_DDC_CLK <15>
F D6 20 82 +5VS 30mil
<32> FD6 PP_D6 SERIRQ
F D7 21 83 EZ_SMB_CLK
<32> FD7 PP_D7 PE_CLK
LPTACK# 22 84 MZIN_ME# R661 1 1@ 2 1K_0402_5%
<32> LPTACK# PP_ACK# EZIN_ME#
L PTBUSY 23 85
<32> LPTBUSY PP_BUSY PE_REQ2# EZ_PE_REQ2# <19,33>
D8 LPTPE 24 86 EZ_SMB_DAT
<32> LPTPE PP_PE PE_DAT
LPTSLCT 25 87
2
<32> LPTSLCT PP_SLCT PE_REQ1# EZ_PE_REQ1# <33> 2
<17> D_USB_SMI#1 2 1 26 PE_WAKE# GND 88
27 89 EZ_PCIE_RXP1
GND PCIERX1+ EZ_PCIE_RXP1 <19>
28 90 EZ_PCIE_RXN1
1@ RB751V_SOD323 GND PCIERX1- EZ_PCIE_RXN1 <19>
CLK_EZ_CLK1 29 91 D_DVI_TXD1-
<14> CLK_EZ_CLK1 PCIECLK1+ DVI1- D_DVI_TXD1- <22>
D40 CLK_EZ_CLK1# 30 92 D_DVI_TXD1+
<14> CLK_EZ_CLK1# PCIECLK1- DVI1+ D_DVI_TXD1+ <22>
D_L AN_ACTIVITY# 31 93
<27> D_LAN_ACTIVITY# LAN_ACT# GND
2 1 32 94 D_DVI_TXD0-
<17> D_USB_SMI#2 RESERVE DVI0- D_DVI_TXD0- <22>
33 95 D_DVI_TXD0+
GND DVI0+ D_DVI_TXD0+ <22>
D_LAN_MDI2+ 34 96
1@ RB751V_SOD323 <27> D_LAN_MDI2+ LAN2+ GND
D_LAN_MDI2- 35 97 D_DVI_TXC+
<27> D_LAN_MDI2- LAN2- DVICLK+ D_DVI_TXC+ <22>
36 98 D_DVI_TXC-
GND DVICLK- D_DVI_TXC- <22>
D_LAN_MDI3+ 37 99 JP2
<27> D_LAN_MDI3+ LAN3+ GND
D_LAN_MDI3- 38 100 D_AUD_INR 1
<27> D_LAN_MDI3- LAN3- GND 1
39 101 D_TV_COMPS D_AUD _INL 2
D_HP_S GND TV_COMP D_TV_LUMA D_TV_COMPS <22> D_A GND 2
40 HP_S TV_Y 102 D_TV_LUMA <22> 3 3
D_SP DIFO 41 103 D_TV_CRMA D_A UD_MIC2 4
R I# SPDIF TV_C D_TV_CRMA <22> D_A GND 4
<36> R I# 42 COM_RI# GND 104 5 5
DTR# 43 105 D_A UD_OR 6
<36> DTR# COM_DTR# GND 6
CTS# 44 106 R535 1 1@ 2 0_0603_5% D_ CRT_R D _AUD_OL 7
<36> CTS# COM_CTS# VGA_R D_CRT_R <15> 7
TXD 45 107 R536 1 1@ 2 0_0603_5% D_CRT_G D_HP_S 8
<36> TXD COM_SOUT VGA_G D_CRT_G <15> 8
RTS# 46 108 R537 1 1@ 2 0_0603_5% D_CRT_B D _MIC_S 9
<36> RTS# COM_RTS# VGA_B D_CRT_B <15> 9
RXD 47 109 D_SP DIFO 10
<36> RXD COM_SIN GND 10
DS R# 48 110
<36> DSR# COM_DSR# GND
D CD# 49 111 EZ_PCIE_RXP2
<36> D CD# COM_DCD# PCIERX2+ EZ_PCIE_RXP2 <19>
50 112 EZ_PCIE_RXN2 1@ ACES_87213-1000
GND PCIERX2- EZ_PCIE_RXN2 <19>
KB_DATA R672 1 2 1@ 0_0603_5% 51 113
<33> KB_DATA PS2_KBDT GND
KB_CLK R673 1 2 1@0_0603_5% 52 114
<33> KB_CLK PS2_KBCK GND
PS_DATA R674 1 2 1@ 0_0603_5% 53 115 EZ_PCIE_TXP2
<33> PS_DATA PS2_MSDT PCIETX2+ EZ_PCIE_TXP2 <19>
PS_CLK R675 1 2 1@ 0_0603_5% 54 116 EZ_PCIE_TXN2
3 <33> PS_CLK PS2_MSCK PCIETX2- EZ_PCIE_TXN2 <19> 3
<33> EZ_SUSON 55 SUSON GND 117
<33> EZ_MAINON 56 MAINON GND 118
57 119 CLK_EZ_CLK2
<33> EZ_PERST# PE_RST# PCIECLK2+ CLK_EZ_CLK2 <14>
58 120 CLK_EZ_CLK2#
GND PCIECLK2- CLK_EZ_CLK2# <14>
EZ_PCIE_TXP1 59 121
<19> EZ_PCIE_TXP1 PCIETX1+ VCC
EZ_PCIE_TXN1 60 122
<19> EZ_PCIE_TXN1 PCIETX1- VCC
D_DVI_TXD2- 61 123
<22> D_DVI_TXD2-
D_DVI_TXD2+ 62
DVI2- GND
124 PJP23 DKN_B+
<22> D_DVI_TXD2+ DVI2+ GND @ JUMP_43X118
1 1 V IN
+3VS FOX_QL10303-C44441-4F_120P 2 2 VIN

PJP24 @ 0.1U_0402_25V4K @ 0.1U_0402_25V4K @ 0.1U_0402_25V4K

2

@ JUMP_43X118
EZ_SMBUS_ON# <33>
R15 1 1
@ 100K_0402_5% 2 2 1 1 1 1 1
2

C381 C382 C383 C384 C386

G
1

2 2 2 2 2
1 3 Q3
@ 2N7002_SOT23
D

@ 0.1U_0402_25V4K @ 0.1U_0402_25V4K

1 2 +3VS
2

R16 @ 4.7K_0402_5%
G

Q5
1 3 EZ_SMB_CLK
<11,12,14> D_CK_SCLK
@ 2N7002_SOT23
D

4 1 2 4
R98 1@ 0_0603_5% 1 2 +3VS
2

R14 @ 4.7K_0402_5%
G

<11,12,14> D_CK_SDATA 1 3 Q4 EZ_SMB_DAT

@ 2N7002_SOT23
D

1 2 Compal Electronics, Inc.

R99 1@ 0_0603_5% Title
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401336
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 38 of 51
A B C D E
 A B C D E

TOP Side +3VALW

2 1
J2 JOPEN Power Button RTC Battery

2
2 1 R468
J3
Button Side
JOPEN
100K_0402_5%
- BATT1 + +RTCBATT

2 1 +RTCBATT

1
1 D29 1
2 O N/OFF <33>
ON /OFFBTN# 1
<34> ON/OFFBTN#
3 51ON# RTCBATT
51ON# <42>

1
DAN202U_SC70 D28

+3VALW BAS40-04_SOT23

1
2 +RTCVCC

2
2

C556 D27

1
R466 1000P_0402_50V7K RLZ20A_LL34
4.7K_0402_5% 1
+CHGRTC

2
1
1

E C_ON 1 2 2 C558
<33> EC_ON 0.1U_0402_16V4Z
R463
33K_0402_5% 2

Q49

3
DTC124EK_SC59
1

D
Q50 2
G
2N7002_SOT23 S
3

2 2

Power ON Circuit
+3VS

+3V +3V
1

U25D U25E
R269 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
14

14

180K_0402_5%
P

P
2

9 I O 8 11 I O 10 SYS_PW ROK <19>

G

2 +3V POWER +3V POWER

7

C289 R271
1U_0805_25V4Z
3 1 100K_0402_5% 3

4 4

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401336 C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 39 of 51
A B C D E
 A B C D E

+3V +1.8VS
+3VALW TO +3V +5VALW TO +5VS
+3V

2
+5VALW +5VS R161 R431
U32 470_0402_5% 470_0402_5%
1 1 8 D S 1
C196 C190 7 2

1
D S
6 D S 3 1 1
10U_1206_16V4Z 1U_0805_25V4Z 5 4 C404 C403
D G

1
+3VALW 2 2 D D
1 U12 1 SI4800DY_SO8 4.7U_0805_10V4Z 1U_0805_25V4Z 2 SYSON# 2 SUSP 1
2 2 G G
8 D S 1
7 2 R157 C380 S Q18 S Q45

3
D S 100K_0402_5% 4.7U_0805_10V4Z 2N7002_SOT23 2N7002_SOT23
6 D S 3
SYSON_ALW 2
5 D G 4 1 2 +12VALW

1
SI4800DY_SO8 2

1
C180 R159 D 5VS_GATE
1
C189 @ 1M_0402_1% 2 SYSON#
0.1U_0402_16V4Z G
10U_1206_16V4Z 1 S Q19
2

3
2 2N7002_SOT23

+3VS +5VS

2
R340 R341
470_0402_5% @ 470_0402_5%

1
1

1
D D
+3VALW TO +3VS 2 SUSP 2 SUSP
G G
+3VS S Q37 S Q38

3
2N7002_SOT23 @ 2N7002_SOT23

2 2
+3VALW
1
C596
1
C592 +1.5VALW TO +1.5VS
U40 10U_1206_16V4Z 1U_0805_25V4Z
2 2 +1.5VALW +1.5VS
8 D S 1
7 2 R490 U13
D S 100K_0402_5%
6 D S 3 8 D S 1
5 4 5VS_GATE 1 2 +12VALW 7 2
D G D S
6 D S 3 1 1
SI4800DY_SO8 5 4 C211 C208
D G +1.5VS +DDRVCC
1

1 2 1 SI4800DY_SO8 4.7U_0805_10V4Z 1U_0805_25V4Z

1

C598 C594 R484 D 2 2

2
@ 1M_0402_1% 2 SUSP C191
10U_1206_16V4Z 0.1U_0402_16V4Z G 4.7U_0805_10V4Z R489 R707
2 1 S Q53 2 @ 470_0402_5% 470_0402_5%
2

2N7002_SOT23

1
5VS_GATE

1
D D
2 SUSP 2 SYSON#
G G
S Q54 S Q67

3
@ 2N7002_SOT23 2N7002_SOT23

3 3

+5VALW +5VALW

2
+DDRVCC
R338 R339
U6 10K_0402_5% 10K_0402_5%
8 1 1@ 4.7U_0805_10V4Z +1.8VS
D S
7 2

1
D S SUSP SYSON#
6 3
5
D S
4 1 1
+1.8V TO +1.8VS (DDR2) <46> SUSP <37> SYSON#
D G

1
C61 C72
1@ SI4800DY_SO8
1 1@ 1U_0805_25V4Z
2 2
100K 100K
2 S Y SON 2
<16,33,35,47> SUSP# <33,46> S YSON
2
DTC115EKA_SOT23 100K DTC115EKA_SOT23 100K
C90 Q35 Q34

3
1@ 4.7U_0805_10V4Z 5VS_GATE

4 4

Compal Electronics, Inc.

Title

PROPRIETARY NOTE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND SCHEMATIC, M/B LA-2601
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE B C
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401336
D ate: ¬P 期四, 三月 17, 2005 Sheet 40 of 51
A B C D E
 5 4 3 2 1

C F9 C F4 CF10 C F5 C F6 CF14 +3V

SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80

14
1

1
U25F
CF11 C F7 C F2 C F1 CF15 CF16

P
SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 +3VALW 13 12
I O
D D

G
1 2
SN74LVC14APWLE_TSSOP14
1

7
C170 0.1U_0402_16V4Z

14

1
U10A
F D6 F D3 F D5 F D4 F D1 F D2

OE#
P
F IDUCAL F IDUCAL F IDUCAL F IDUCAL F IDUCAL F IDUCAL 2 3
I O

G
1

7
SN74LVC125APWLE_TSSOP14

+12VALW

U37B
5 +IN
H1 H2 H3 H4 H5 7
SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 OUT
6 -IN

4
U10B LM358A_SO8

OE#
5 I O 6
1

1
C SN74LVC125APWLE_TSSOP14 C

H6 H7 H8 H9 H10
SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8
1

H11 H12 H13 H14 H15

SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8
1

H16 H17 H18 H19 H20

SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8

B B
1

H21 H22 H23 H24 H25

SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8
1

H26 H27 H28 H29 H30

SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8
1

A A

M1 H31
SCREW 8.5X2.8 SCREW 8.5X2.8

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2601
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE C
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401336
D ate: ¬P 期四, 三月 17, 2005 Sheet 41 of 51
5 4 3 2 1
 5 4 3 2 1

Detector
VIN
ADPIN PL1 PD1
PCN1 FBM-L18-453215-900LMA90T_1812 SBM1040-13_POWERMITE3
2
1 2 AD IN 1
1
3
Vin Detector
2 18.234 17.841 17.449
G
D
G 17.597 17.210 16.813 D

1000P_0402_50V7K
3

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
1

1
PC2

PC4
SINGA_2DC-S756B200

PC1

PC3
2

2
PR1
1M_0603_0.5%
1 2

VIN VS VIN

0.01U_0402_25V7Z
1

1
PR2 PR3 PR4

1
82.5K_0603_0.1% 10K_0805_5% 1K_0603_5%

PC5
1 2
ACIN <19,33,45>

2
PR5

2
8
22K_0603_1%
N9 1 2 N8 3

P
+ PACIN
O 1 PACIN <43,44>

19.6K_0603_0.1%
0.1U_0402_16V7K
N7 2 -

G
1
1

1
1000P_0402_50V7K
PR6
PU1A

1
VIN

PC6

PC7
LM393M_SO8 PR7
PZD1 10K_0603_5%

2
2
2
PD2 RLZ4.3B_LL34

2
1N4148_SOD80

2
PD3 PR8
2 1 1N4148_SOD80 10K_0603_5%
VMBA
2 1
RTCVREF

1
C C

N11
PD4 3.3V
1N4148_SOD80
2 1 PR9
VMBB
1 1 2
PR10 B+
VS 1K_1206_5%
33_1206_5% PD5
PQ1 1N4148_SOD80
2

TP0610K_SOT23 PR11
CHGRTCP 3 1 2 1 VSB+ 1 2

1K_1206_5%
1

0.1U_0603_25V7K
2
1

PR12 PC8
PC9

PR13
100K_0402_5% 0.22U_1206_25V7K 1 2 PR14 PR15
2

10K_0603_5% 1M_0603_0.5%
2

PR16 1K_1206_5% 1 2 2 1
N6 VL
1 2 B+
<39> 51ON#
22K_0402_5% PD6
RB715F_SOT323

1
2
<18,45,49> MAINPWON 1 VS PR17
1

3 280K_0603_1%
RTCVREF PR18 <43,44> ACON
PU1B

2
8
200_0603_5% LM393M_SO8
PU2 G920AT24U_SOT89 2 5 N3
3.3V

P
<44> GA
2

PR19 PR20 +

1000P_0402_50V7K
1 N4 7
O

200K_0603_1%
B N12 N10 B
1 2 1 2 3 2 3 6
+CHGRTC OUT IN <43,44> GB -

1.5M_0603_1%
1

1
1000P_0402_50V7K

PR21

PR22

PC11
PC10 PD7

4
200_0603_5% 200_0603_5%
1

1
GND RB715F_SOT323

PC14
PC12 1U_0805_50V4Z
2

2
10U_0805_10V4Z 1
2

2
N5
0.1U_0603_25V7K
1

1
VL D PR23

PC13
PR24 2 N2 1 2 PACIN
10K_0603_5% G 47K_0603_5%

1
N1 PQ2
ACIN 2 1 S

3
2N7002_SOT23
PJP1 PJP2 +5VALWP
@ JUMP_43X118 @ JUMP_43X118
Precharge detector 2
+5VALWP
1 1
2 2 +5VALW +1.8VP
1 1
2 2 +DDRVCC 14.724 14.333 13.945 PQ3

PJP3 PJP4
13.280 12.933 12.531 DTC115EUA_SC70

3
@ JUMP_43X118 @ JUMP_43X118
1 1
2 2
1 1
2 2
BATT
PJP5 PJP6
@ JUMP_43X118 @ JUMP_43X118
Precharge detector
+3VALWP
1 1
2 2 +3VALW +0.9VSP
1 1
2 2 +0.9V_DDR_VTT 7.558 7.333 7.112
A
6.108 5.933 5.704 A
PJP7
@ JUMP_43X118 PJP8
1 1 @ JUMP_43X118
+1.5VALWP 2 2 +1.5VALW
1 1 2 2 +1.05VS
+GMCH_COREP

PJP9 PJP16 Compal Electronics, Inc.

1 2 @ JUMP_43X118 Title
+12VALWP 1 2 +12VALW
@ JUMP_43X39 +2.5VSP
1 1 2 2 +2.5VS SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401336
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期四, 三月 17, 2005 Sheet 42 of 9
5 4 3 2 1
 5 4 3 2 1

PJP20
Charger
@ JUMP_43X118
1 1
Iadp=0~3.0A 2 2
D D
PQ4 P2 PQ5 P3 B+ B++ PQ6
VIN AO4407_SO8 AO4407_SO8 PJP18 AO4407_SO8
8 1 1 8 PR25 @ JUMP_43X118 1 8
7 2 2 7 2 1 1 1
2 2
2 7
1

6 3 3 6 3 6

2200P_0402_50V7K
4.7U_1206_25V6K

4.7U_1206_25V6K

0.1U_0603_25V7K
PR26 5 5 0.02_2512_1% 5
15K_0603_5%

1
VIN

200K_0402_5%
4

4
PR29
1

1
0.1U_0603_25V7K
2

PR28

PC15

PC16

PC17

PC18
1 2 N25

2
3
PR27
47K_0402_5% PQ7
47K 47K_0402_5%

1
DTA144EUA_SC70
2

1
PC19
2 47K
PR30

2
10K_0402_5%
N23

2
1
N24

N21
1

2
PU3 PQ57
1 24 PR31 @ 2N7002_SOT23
-INC2 +INC2

1
0_0402_5% D
2 2 N24

1
2 1 2 23 G
OUTC2 GND
1
PQ8 1.202V PR32 S

3
1

D DTC115EUA_SC70 100K_0402_1% PC20 2200P_0402_50V7K

2 PR33 +INE2 3 22 CS 1 2
3

+INE2 CS
2N7002_SOT23

31.6K_0603_1%
G 150K_0603_1% ACOFF#

1
S
3

3
2
1
PQ10

C -INE2 N14 PQ9 C

4 -INE2 VCC(o) 21 1 2

10K_0402_1%

PR34
0.1U_0402_16V7K
N22

DTC115EUA_SC70

PR35
PD8 PC23 PR36 PC21
PC22

1SS355_SOD323 1 2 1 2 5 20 0.1U_0603_25V7K N13 4 2 ACOFF ACOFF <33>

FB2 OUT
1

D 2

2
ACOFF# 1 2 2 2200P_0603_50V7K 10K_0402_1% PC24
ACOFF#
2
2N7002_SOT23

G MB3887VREF 6 19 N15 1 2
VREF VH
S
3

3
1
PQ12

0.1U_0402_16V7K
PACIN 1 2 PC26 PR38 0.1U_0603_25V7K PC27 0.1U_0603_25V7K
<42,44> PACIN

PC25
1 2 1 2 7 18 1 2 PQ11

5
6
7
8
PR37 1K_0402_1% FB1 VCC AO4407_SO8
2
3K_0603_5% 1500P_0603_50V7K PR39
-INE1 8 17 1 2
-INE1 RT 68K_0402_5% LXCHRG
<42,44> ACON
PR40
+INE1 9 16 -INE3 PL3 0.02_2512_1%
+INE1 -INE3 15U_PLFC1045P-150A_3.7A_20%
PR41 PR42 PC28 1 2 1 2
IREF=1.048*Icharge 2 1 OUTC1 10 15 1 2 N27 1 2
BATT+
OUTC1 FB3

4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K
10K_0402_1%
IREF=0.419~3.132V

1
47K_0402_1% 1500P_0603_50V7K

PC29

PC30

PC31
OUTD 11 14
PR43 OUTD CTL

2
1 2 PD9 PD30
<33> IREF FSTCHG
12 13 SKS30-04AT_TSMA @ SKS30-04AT_TSMA
162K_0603_1% -INC1 +INC1 <33,44>

2
0.1U_0402_16V7K
1

MB3887_SSOP24
1

PR44
PC32

+INC1
Battery OVP voltage : 100K_0402_1%
2

4S2P : 18V--> BATT_OVP= 2.0V

2

B B
BATT+
(BAT_OVP=0.1112*VMB) PR45 PR46
2 1
4.2V 2 1
1

3S2P : 13.5V--> BATT_OVP= 2.0V VS PR47 PQ13 150K_0603_0.1% 300K_0603_0.1%

340K_0603_1% 2N7002_SOT23
(BAT_OVP=0.14753 *BATT+)
0.01U_0402_25V7Z

PR48
S

3 1 N16 2 1
2
PC33

N26

300K_0603_0.1%
1

G
2
1
2

PR49
499K_0603_1% PR50
100K_0402_5% +3VALWP
8

PU4A N18 1 2 VL
2

LM358A_SO8 3 N17 CS
P

1
0.1U_0402_16V7K

1 0
<33> BATT_OVP
1

2 PR51
-
G

1
22K_0603_5%

105K_0603_0.5%

PC34 @ 47K_0603_5%
1

PC35

0.01U_0402_25V7Z
4

1
D
CC=0.4~3.0A
2

2
PR52

PR53

N20 2 PQ14
1

G
CV=16.8V(8 CELLS LI-ION)

1
PQ15 S @ 2N7002_SOT23
2

3
N19 DTC115EUA_SC70
CV=12.6V(6 CELLS LI-ION)
2 GB <42,44>
40.2K_0603_1%

<33,44> FSTCHG 2
1

A D PQ16 A
PR54

2
3

G @ DTC115EUA_SC70

3
S PQ17
2

5 2N7002_SOT23
+
7 0
- 6
PU4B
LM358A_SO8 Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401336
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期四, 三月 17, 2005 Sheet 43 of 9
5 4 3 2 1
 5 4 3 2 1

PJP14 @ JUMP_43X118 BATT+

1 1 2 2

1000P_0402_50V7K

1000P_0402_50V7K
VMBA
PJP15 @ JUMP_43X118
1 1 2 2 VMBB Battery Select

1
PC36

PC37
PQ18 PQ19 PQ20 P4 PQ21
PCN2 PL4 AO4407_SO8 P5 AO4407_SO8 AO4407_SO8 AO4407_SO8 PL5
SUYIN_200275MR007G113ZL FBM-L18-453215-900LMA90T_1812 FBM-L18-453215-900LMA90T_1812 PCN3

2
8 1 1 8 8 1 1 8 SUYIN_200275MR007G113ZL
1 1 2 VMBAA 7 2 2 7 7 2 2 7 VMBBB 2 1 7 BATT+ G 8
BATT+
ID 2 6 3 3 6 6 3 3 6 6 BATT+ G 9
3 AB/I 5 5 5 5 TSB 5 TS
B/I TSA SMC2
4 4 SMC
TS

39K_0603_5%
5 SMD1 SMD2 3 SMD

4
SMD

39K_0603_5%
0.01U_0402_25V7Z

0.01U_0402_25V7Z
D SMC1 D
9 6 2 GND
G SMC

1
8 7 1 GND
G GND

PC38

PR57

PR58

PC39
PR55
1K_0603_5%

2
1

2
BATTA_ON BATTB_ON

1 2 1 2
PR59 PR60
22K_0603_5% 22K_0603_5%
2 1 +3VALWP

1
C C
PR61 N28 2 N30 2 +3VALWP 1 2
6.49K_0603_1% B B
E E PR62

3
2

6.49K_0603_1%
2

2
PR65 PQ22 PQ23
2

2
100_0603_5% PR66 PR63 HMBT2222A_SOT23 HMBT2222A_SOT23
100_0603_5% 1K_0402_5% PR64
PD10 PD11 1K_0402_5%
1

1N4148_SOD80 1N4148_SOD80
1

1
BATT_TEMPA <33>
1

1
2 1 N29 2 1 N31
PR67 <33> BATT_TEMPB

1
10K_0603_5% PR68
EC_SMB_DA1 <33,35> 10K_0603_5%

2
EC_SMB_CK1 <33,35> PR70 PR69
GA 2 GB 2 100_0603_5% 100_0603_5%
<42> GA <42,43> GB
1

1
C PR71 PQ24 PR72 PQ25 C

10K_0402_5% DTC115EUA_SC70 10K_0402_5% DTC115EUA_SC70

3

3
<4,33> EC_SMB_CK2 EC_SMB_CK2
2

2
EC_SMB_DA2
<4,33> EC_SMB_DA2
74HC253_Y1

74HC253_Y2

0.01U_0402_25V7Z
VL VS VMBB

PU5
VL
7

74HC253
2

2
1Y

2Y

GND

PC40
16 PR73 PR74

2
PR75 VCC 100K_0402_5% PU6A PR76 649K_0603_1%

8
0.1U_0402_16V7K

@ 270K_0402_5% LM393M_SO8 100K_0603_1%

1

1
1EN
2EN
1

1C0
1C1
1C2
1C3

2C0
2C1
2C2
2C3

1 2 3 N34 2 1 N38
S0
S1

P
<42,43> ACON +
PC41

2 1 N431
O Second Battery Detector

100P_0402_50V8J
2
2

6
5
4
3

10
11
12
13

14
2
1
15

1
PR77
1 2 High:8.67V

PC42
4.7K_0402_5% 4 PR78
PD12 442K_0603_1% Low :7.87V

2
@ 1SS355_SOD323

1
N32 2 1
2
0_0402_5%

@ 4700P_0603_50V7K

PR79
2

5.6M_0603_5%
PR218

PC43

1 2 N41
B PR80 RTCVREF B
1

100K_0402_5%
1

1 2
PR81 VL VMBA
100K_0402_5%
2

PR82
2

2
VS 10K_0402_5%
PR83
100K_0402_5% PR84
1

PU6B PR85 1M_0603_0.5%

1
8

FSTCHG LM393M_SO8 100K_0603_1%

1

1
PR212 5 N35 2 1 N37
P

<33,43> +
@ 0_0402_5% N33 2 1 N457
O
2

100P_0402_50V8J
1 2 2 6 N36
- Main Battery Detector
G

1
PR86
1

PC44
4.7K_0402_5% PR87 High:10.68V
4

PQ26 PC45 499K_0603_1%

2
1 2 DTC115EUA_SC70 1000P_0402_50V7K Low :9.52V
3

ACON
<42,43> PR213 2 1
1

@ 0_0402_5%
PR88
5.6M_0603_5%
1

2
<33> A/B#USE PR89
47K_0603_5%
PQ27 2 N39 1 2 PACIN <42,43>
DTC115EUA_SC70
3

PQ28 PD13
A DTC115EUA_SC70 A
2 1 TRICKLE <33>
3

1N4148_SOD80

A/B#USE
High: Main Battery (A)
Low : Second Battery (B) Title
Compal Electronics, Inc.
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401336
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期四, 三月 17, 2005 Sheet 44 of 9
5 4 3 2 1
 A B C D

+3VALWP/+5VALWP/+12VALWP
B+
1

1 1

PJP10 PC46
1

4.7U_1206_25V6K
@ JUMP_43X118 2 1
2

1
2

2
PC48
0.1U_0603_25V7K PC47 PD14
2 1 BST3A BST5A 470P_0805_100V7K EC11FS2_SOD106

1
B+++

2
2

3
N53 2 1 N52
PD15

2
CHP202U_SC70 PR90
22_1206_5%
2200P_0402_50V7K

4.7U_1206_25V6K

4.7U_1206_25V6K

VL PT1
PQ29 PC52

1
1

1
P C49

P C50

P C51

AO4912_SO8 VS 0.1U_0603_25V7K 9U_SDT-1204P-9R0-120_4.5A_20%

2 1

3
4.7U_1206_25V6K
1 8 DH 31
2

D2 G2 +12VALWP B+++
2 D2 D1/S2/K 7

2
1SS355_SOD323
3 G1 D1/S2/K 6

1
0_0402_5%
4 S1/A D1/S2/K 5
PR92 PR94

P R91

P C53

2.7K_1206_5%

4.7U_1206_25V6K

4.7U_1206_25V6K

2200P_0402_50V7K
0_0402_5% 0_0402_5% PQ30

1
AO4912_SO8

1
P D16

P R93

P C54

P C55

P C56
1

1
1 2 DH 51 8 1
G2 D2

4.7U_1206_25V6K
7 2

2
D1/S2/K D2

1
1.54K_0603_1%

0_0402_5%
MAX1902_V+ PR97 6 3

1N 54 2
D1/S2/K G1

P R95
47P_0402_50V8J

2 0_0402_5% 5 4 2
D1/S2/K S1/A

P R96
0.1U_0603_25V7K

47P_0402_50V8J
1

1
P C57
D

P C58

P C60
2

2
A C IN 2
N 46 2

2
P C59

PL6 G
10U_SPC-1204P-100_4.5A_20% PQ32 S

N 47
2N7002_SOT23
2

22

21
1 2 PU7

1
PR98 BST3 25 4

VL
V+
BST3 12OUT
2

2
1M_0402_1%

0.47U_0603_16V7K

1.27K_0603_1% 5 MAX1902_VDD
VDD
1
PR100

D H3 27 18 BST5
DH3 BST5
P C61

2M_0402_1%
PR101 16 D H5
1.27K_0603_1% LX3 DH5 LX5
26 17
2

2
LX3 LX5

P R99
+3VALWP DL3 24 19 DL5
1

CSL3A DL3 DL5

1 2 20
PR102 MAX1902EAI_SSOP28 PGND 14 CS H5
0_0402_5% CS H3 CSH5 CSL5
1 CSH3 CSL5 13

2
1 PR1032 CSL3 2 12 FB5
CSL3 FB5

1
FB3 620_0402_5% 3 15
FB3 SEQ
SKUL30-02AT_SMA

100P_0402_50V8J

1 1 2 N51 10 9 2.5VREF
<19,33,42> A C IN SKIP# REF
1

2
P D17
150U_D2_6.3VM

3.32K_0603_1%

PR105 23 6 PC62 PR104

2
SHDN# SYNC
1

1
P C63

PR106

+ 10K_0402_5% 11 0.47U_0603_16V7K 698_0402_1%

1
RST#

MAX1902_SYNC
7 TIME/ON5

1
P C64

PR107 +5VALWP
2

2
N 50

@ 300K_0402_5% 28
GND
2

RUN/ON3 PC65
2

SKUL30-02AT_SMA
4.7U_1206_25V6K 1
1

P D18

150U_D2_6.3VM
3 3
8

P C68
VS PC66 1 2 1 2 PR108 +
VL
2

680P_0402_50V7K PR109 PR110 10.2K_0603_1% PC67

2

2
@ 0_0402_5% 0_0402_5% 100P_0402_50V8J

2
PR111 2

2
1

10K_0402_1%
PR112
1

47K_0402_5%

1
VL
2

N49 PR113
PR114 10K_0402_1%

2
806K_0603_1%
1

PC69
@ 0.047U_0603_25V7M
2
2

MAINPW ON <18,42,49>
1

PC70
0.47U_0603_16V7K
2

4 4

Title
Compal Electronics, Inc.
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401336 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 45 of 9
A B C D
 5 4 3 2 1

+GMCH_COREP/+1.8VP/0.9VSP

D D

B+
PJP11
@ JUMP_43X118
MAX8743_B+ 1 1 2 2

2200P_0402_50V7K

4.7U_1206_25V6K

4.7U_1206_25V6K
1

1
PC71

PC72

PC73

2
PR115
0_0603_5% +5VALWP

2200P_0402_50V7K

4.7U_1206_25V6K

4.7U_1206_25V6K
1

1
PD19 PC74

MAX8743A_V+

1
CHP202U_SC70 4.7U_1206_25V6K

PC75

PC76

PC77
2

2
1
PQ34 PR117

2
AO4912_SO8 20_0603_1% PC78

5
6
7
8
4.7U_0805_6.3V6K

2
C C
1 8

D
D
D
D
D2 G2 BST1.8A
2 7

BST1.05A
D2 D1/S2/K
3 G1 D1/S2/K 6
4 5 PQ35
S1/A D1/S2/K

G
S
S
S
MAX8743_VCCA SI4800BDY-T1_SO8

0.1U_0603_25V7K

V+ 1U_0603_16V6K
+1.8VP

VDDA

4
3
2
1
1

1
+GMCH_COREP PL8 PC81 PR119 PL14

PC79

PC80
4.7UH_PLFC1045P-4R7A_5.5A_30% 0.1U_0603_25V7K 0_0402_5% 4.7UH_PLFC1045P-4R7A_5.5A_30%
2 1 2 1 1 2 BST1.05 BST1.8 1 2 2 1 1 2

2
4.7U_0805_6.3V6K

1
1

5
6
7
8
@SKS10-04AT_TSMA

4.7U_0805_6.3V6K

@SKS10-04AT_TSMA
220U_D2_4VM

PR118 PC82

22
1

9
PD20

5.1K_0402_1%

220U_D2_4VM_R25
+ 0_0402_5% PU8 0.1U_0603_25V7K 1

D
D
D
D
1

1
PC84

PR121 25 21

UVP
VCC
BST1 VDD

1
PR120

0_0402_5% PR122 PQ55 +

2

1
2
PC83

DH1.05A 1 2 DH1.05 26 19 0_0402_5% SI4810BDY_SO8

2

DH1 BST2

G
S
S
S

PC86

PD21

PC147
8.06K_0402_1%
18 D H1.8 1 2 DH1.8A

2
LX1.05 DH2 LX1.8 2
27 17
2

4
3
2
1

2
DL1.05 LX1 LX2 DL1.8
24 20
DL1 DL2

PR123
16

2
28 MAX8743EEI_QSOP28 CS2
CS1
1 15
OUT1 OUT2 FB1.8
14
FB1.05 FB2 N56
2 12 2 1 SYSON
FB1 ON2

@ 100P_0402_50V8K
PR124
@ 100P_0402_50V8K

7 0_0402_5%
PGOOD

1
100K_0402_1%

10K_0402_1%
5
TON
1

PC87
1 2 N57 11
VR_ON ON1
1
PR127

PC88

13 2V MAX8743A_ILIM2
ILIM2

PR126
PR125 3 1.936V MAX8743A_ILIM1

SKIP
GND
OVP

REF

2
0_0402_5% ILIM1
2

2
2

PR129

23

MAX8743A_REF 10
B 0_0603_5% B
2 1

2 1

100K_0603_1%
MAX8743_VCCA 1 2 MAX8743A_SKIP PR130

1
3.3K_0603_1%
+DDRVCC

PR133
0.22U_0603_16V7K
+1.8VP PR131

1
@ 0_0402_5% PR132

1
100K_0603_1%
PR134

2
0_0402_5%
2

PC89
2
2

PJP13
2

@ JUMP_43X118
1
1

PU10
VIN0.9 1 6
VIN VCNTL +3VALW
1U_0603_16V6K

2 5
GND NC
1

2
1

PC101

PC100 3 7
PR141 VREF NC
2

10U_1206_6.3V7K 1K_0402_1% 4 8
VOUT NC
9
2

TP
VREF0.9 APL5331KAC-TR_SO8
A PR142 A
1

0_0402_5% D
+0.9VSP
1 2 N55 2 PQ39 PC102
<40> SUSP G 2N7002_SOT23 PR143 0.1U_0402_16V7K
2

10U_1206_6.3V7K

S 1K_0402_1%
3
1

1
2

PC104

PC103
@ 0.1U_0402_16V7K Compal Electronics, Inc.
2

Title
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401336
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期四, 三月 17, 2005 Sheet 46 of 9
5 4 3 2 1
 5 4 3 2 1

+2.5VSP/+1.5VALWP

D D

B+
PJP17
@ JUMP_43X118
MAX8743_B++ 1 1
2 2

2200P_0402_50V7K

4.7U_1206_25V6K

4.7U_1206_25V6K
1

1
PC133

PC134

PC135

2
PR188
0_0603_5% +5VALWP

2200P_0402_50V7K

4.7U_1206_25V6K

4.7U_1206_25V6K
1

1
PD27 PC136

1
CHP202U_SC70 4.7U_1206_25V6K

MAX8743B_V+

PC137

PC138

PC139
2

2
1
PQ51 PR190 PQ52

2
AO4912_SO8 20_0603_1% PC140 AO4912_SO8

2
4.7U_0805_6.3V6K

BST1.5A

2
1 D2 G2 8 8 G2 D2 1
2 7 BST2.5A 7 2
D2 D1/S2/K D1/S2/K D2
3 G1 D1/S2/K 6 6 D1/S2/K G1 3
C C
4 S1/A D1/S2/K 5 5 D1/S2/K S1/A 4
MAX8743_VCCB

0.1U_0603_25V7K

V+ 1U_0603_16V6K
PL13 PL7 +2.5VSP

VDDB
1

1
+1.5VALWP 4.7UH_PLFC1045P-4R7A_5.5A_30% PR191 PR192 5UH_SPC-06704-5R0_2.9A_30%

PC141

22 PC142
0_0402_5% 0_0402_5%
1 2 2 1 1 2 BST2.5 1 2 2 1 1 2

2
4.7U_0805_6.3V6K

1
1

220U_D2_4VM
@SKS10-04AT_TSMA

4.7U_0805_6.3V6K

@SKS10-04AT_TSMA
PC143 PC144
1

220U_D2_4VM
PD28

+ 0.1U_0603_25V7K PU13 0.1U_0603_25V7K 1

1
PC146

5.36K_0402_1%

PR194 BST1.5 25 21

UVP
VCC
BST1 VDD
1

1
0_0402_5% PR195 +
2

1
2
PC145

PR193

DH1.5A 1 2 D H1.5 26 19 0_0402_5%

2

DH1 BST2

15K_0402_1%

PC148

PD29

PC85
18 D H2.5 1 2 DH2.5A

2
LX1.5 DH2 LX2.5 2
27 17

2
DL1.5 LX1 LX2 DL2.5
24 20
2

DL1 DL2

PR196
16

2
28 MAX8743EEI_QSOP28 CS2
CS1
1 15
OUT1 OUT2 FB2.5
14
FB1.5 FB2 N59
2 12 2 1 SUSP#
FB1 ON2

@ 100P_0402_50V8K
PR197
@ 100P_0402_50V8K

7 0_0402_5%
PGOOD

1
10K_0402_1%

10K_0402_1%
5
TON
1

PC149
+3VALWP 1 2 N58 11
ON1
1
PR200

PC150

13 0.844V MAX8743B_ILIM2
ILIM2
1

PR199
PR198 3 1.936V MAX8743B_ILIM1

SKIP
GND
OVP

2
REF
ILIM1
@ 0_0402_5%

0_0402_5%
2

2
2

PR201

PR202

23

10
137K_0603_1%
2

2 1

1MAX8743B_REF
B B
2 1

100K_0603_1%
MAX8743_VCCB 1 2 MAX8743B_SKIP PR203

1
3.3K_0603_1%

PR206
PR204

0.22U_0603_16V7K
@ 0_0402_5% PR205
100K_0603_1%
PR207

2
0_0402_5%

PC151

A A

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401336
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期四, 三月 17, 2005 Sheet 47 of 9
5 4 3 2 1
 5 4 3 2 1

CPU CORE
CPU_B+ PL15
+5VS B+
FBM-L18-453215-900LMA90T_1812

PR144 10_0402_5%
2 1

4.7U_1206_25V6K

4.7U_1206_25V6K

0.1U_0603_25V7K

2200P_0402_50V7K

100U_25V_M
1

PC108

PC109
PC107
+

PC105

PC106
2

2
D D
2

2
1532VCC

2
PC112 PC111

0.01U_0402_25V7Z
1U_0603_16V6K
2.2U_0603_6.3V4Z BSTMA

5
6
7
8
PC113
1

0.22U_0603_16V7K
PQ40

1
AO4408_SO8

PC114
10 VCC VDD 30
PR145 0_0402_5%

2
1 2 D0 24 36 DHMA 4
<5> CPU_VID0 PR146 0_0402_5% D0 V+
1 2 D1 23 26 BSTM 1 2 PR149 PL11
<5> CPU_VID1 PR148 0_0402_5% D1 BSTM PR147 2.2_0402_5% 0_0402_5%
1 2 D2 22 28 D HM 1 2 0.56UH_MPC1040LR56_23A_20% +CPU_CORE

3
2
1
<5> CPU_VID2 PR150 0_0402_5% D2 DHM PR151
1 2 D3 21 27 LXM 1 2 1 2
<5> CPU_VID3 PR152 0_0402_5% D3 LXM

5
6
7
8

1
AO4410_SO8
1 2 D4 20 PU11 29 DLM 0.001_2512_5%
<5> CPU_VID4 D4 DLM

SKS30-04AT_TSMA
PR153 0_0402_5% PR216

1
1 2 D5 19 31 4.7_1206_5%
<5> CPU_VID5 D5 PGND

P D24
PQ41

909_0402_1%
PR154 0_0402_5%

1
<6,14,19> VGATE 1 2 1532VROK 25 MAX1532 37 CMP

2
VROK CMP

PR156

499_0603_1%

499_0603_1%
4 CPU VCC SENSE

3K_0603_1%
4 38 C MN

2
S0 CMN

1
PR159 1532VCC 5 17 OA IN+ PC155 PC115

2
S1 OAIN+

@1000P_0402_50V7K
C 0_0402_5% 680P_0603_50V8J C

3
2
1

2
1 2 1532SHDN 6 16 OAIN- 1 2

2
SHDN# OAIN-

PC116
PR162 30.1K_0402_1%

PR157

PR158
1 2 2 1 1532TIME 1 15 FB
<33,46> VR_ON

1
TIME FB

PR160
PR161 0.47U_0603_16V7K

1
@ 100K_0402_5% PC117 1 2 1532CCV 12 14 CCI 1 2 PR163 909_0402_1%
CCV CCI PC118 470P_0402_50V8J N60
1 2
1 2 270P_0402_50V7K 2 35 BSTS
PR166 TON BSTS
78.7K_0402_1% PR164 200K_0402_1% PC119 1 2 1532REF 8 33 D HS PR165
REF DHS
1 2
1 2 0.22U_0603_16V7K 1532ILIM 9 34 LXS PD25
ILIM LXS CHP202U_SC70 3K_0603_1%
+5VS
FB 1 2 1532OFS 7 32 D LS BSTMA 3
OFS DLS N61
1 2 1 2

2
10.7K_0402_1%

PR167 100K_0402_1% 1532SUS 3 40 C SP 1 PC152

SUS CSP
2
PR169

100P_0402_50V8J

4.7U_0805_6.3V6K PC120 PR168

1

1532SKIP 18 39 C SN BSTSA 2 0.022U_0603_16V7K 0_0603_5%

1
SKIP CSN
PC121
RHU002N06_SOT323

PR170
1

2
D CPU_B+
RHU002N06_SOT323

2.2_0402_5%
27P_0402_50V8J

0_0402_5% 11 13
2

GND GNDS
1

PR171
1 2 N63 2
1

PC122

G 2
PM_STP_CPU#

2200P_0402_50V7K
S G
<14,19>
3

1
PQ43

4.7U_1206_25V6K

4.7U_1206_25V6K
S
3

1
PQ44

0.1U_0603_25V7K
5
6
7
8

2
AO4408_SO8

PC123

PC126
PQ45

PC124

PC125
2

1
0.22U_0603_16V7K
1 2 PR173
PM_DPRSLPVR

1
B 0_0402_5% B
<19>

PC127
PR172 1 2 DH SA 4
0_0402_5% +5VS 1 2

2
PR175 PL12
2

20K_0402_1% 0.56UH_MPC1040LR56_23A_20%

3
2
1
2

PR176
PR177 10K_0402_1% 1 2
100K_0402_1%

AO4410_SO8

909_0402_1%
1

5
6
7
8

1
1

SKS30-04AT_TSMA
PR217

P D26
PQ46
N 65

4.7_1206_5%
RHU002N06_SOT323

2
1

D
4

2
PQ48

N62 2

PR178
G 1 2
S PC156
3
HMBT2222A_SOT23

PR179 680P_0603_50V8J PC128

3
2
1

2
1

0_0402_5% C 0.47U_0603_16V7K
PQ49

1 2 N64 2
<5> PSI# B
E
3

PR180 909_0402_1%
1 2

A
PC153 1000P_0402_50V7K A
1 2 OA IN+

PC154 1000P_0402_50V7K
1 2 OA IN+

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C ustom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401336
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 48 of 9
5 4 3 2 1
 A B C D

OTP

1
PH1 under CPU botten side : 1

CPU thermal protection at 90 +-3 degree C

Recovery at 50 +-3 degree C

VL VS

CPU
1

PC130

2
0.1U_0603_25V7K
PH1 <18,42,45> MAINPWON
10KB_0603_1%_TH11-3H103FT

1
2 VL 2
2
N 71

PR181
47K_0402_1%

2
1 2
1

PR215
PR183 47K_0402_1%
0_0402_5%
PR184

1
8
16.9K_0402_1% PU14A
2

1
N72 OTPFB2 D
1 2 3

P
+ OTP 2N7002_SOT23
O 1 2
1 2 OTPREF2 2 G PQ56
-

G
1

VL S

3
PR185 LM393M_SO8

4
100K_0402_1%
PR214
1

2.74K_0603_1%
2
1

PC132 PR187
2

0.22U_0603_16V7K 100K_0402_1%
2

PC131
2

1000P_0402_50V7K

VS

3 3
8

PU14B
5
P

+
O 7
6 -
G

LM393M_SO8
4

4 4

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B 401336 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 49 of 9
A B C D
 5 4 3 2 1

Version change list (P.I.R. List) Power section Page 1 of 2

Item Reason for change PG# Modify List Date B.Ver#

1 Change DC JAck and second battery connect. 42,44 Change DC JAck from DC231105200 to DC231000500. 2004.10.28
D Change second battery connect from D

2 Modify OTP schematic. 45,49 Change PR114 from 47K_0402_5% to 806K_0603_1%; 2004.11.30
Change PR183 from 0_0402_5% to 1.37K_0402_1%;
Change PR184 from 16.9K_0402_1% to 10K_0402_1%;
Change PC132 from 0.22u_0603_16V to 1U_0603_16V;
Change PC70 from 0.047uF to 0.47uF;
Delete PR186, PR182, PU12 and PQ50.

3 To increase the pre-charge current. 42 Change PR21 from 169K_0603_1% to 200K_0603_1%; 2004.12.28
Change PR10 from 47_1206_5% to 33_1206_5%;
Change PR9,PR11 and PR13 from 1.5K_1206_5%
to 1K_1206_5%.

4 Change OTP schematic to EVT design. 49 Change PR183 from 1.37K_0402_1% to 0_0402_5%; 2005.01.05
Change PR184 from 10K_0402_1% to 16.9K_0402_1%;
Change PC132 from 1U_0603_16V to 0.22u_0603_16V;
Add PR215 47K_0402_1%;
C Add PR214 2.74K_0603_1%; C

Add PU14 LM393 and PQ56 2N7002.

5 For EMI request. 48 Add PR216 and PR217, 4.7_1206_5%; 2005.01.10

Add P155 and PC156, 680P_0603_50V;
Add PL15, FBM-L18-453215-900LMA90T.

6 To increase 1.5V power plan to 1.57V by H/W request. 47 Delete PR201; 2005.01.10
Add PR200 10K_0402_1%;
Add PR193 5.36K_0402_1%.

B B

A A

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B 401336 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期四, 三月 17, 2005 Sheet 50 of 9
5 4 3 2 1
 5 4 3 2 1

EAT10 PIR List

********** Rev:0.2 PIR List 2004/08/10 Writer by Jason **********
P05 : Add @ in R63
Del @ in R56
P06：Del @ in R54
D Del JP9 D

P18: New add R512

P21 : New add R513
New add X3
New add C607
P21 : New add R534, R535

C C

B B

A A

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2601
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401336 C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期四, 三月 17, 2005 Sheet 51 of 51
5 4 3 2 1