Microelectronics Journal 90 (2019) 117–122

Contents lists available at ScienceDirect

Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

A 0.6-V pseudo-differential OTA with switched-opamp technique for low

power applications
Jingyu Wang, Yongyuan Li, Zhangming Zhu *
Shaanxi Key Lab. of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi'an, 710071, China

A R T I C L E I N F O A B S T R A C T

Keywords: A low-voltage, pseudo-differential OTA is presented in this study for power-effective applications. The cross-
Pseudo-differential OTA coupled common-mode feedforward (CMFF) technique is proposed to improve the CMRR performance and
Low power double transconductance of pseudo-differential OTA with the same power consumption as the conventional one.
Low voltage
Implemented under the supply voltage of 0.6 V, the designed OTA, which converts the single-ended signal into the
Switched-opamp
fully differential signal, is used as the input buffer of ADC. Considering the particularity of ADC application,
switched-opamp (SO) technology is designed to turn off amplifier partly for compromising high power efficiency
and short start time. Implemented in the 0.18-μm standard CMOS process, the OTA occupies an active chip area of
0.05 mm2 and provides the settling time of 310 ns with 0.1% accuracy for 0.6 Vpp output step. The measured input
pffiffiffiffiffiffi pffiffiffiffiffiffi
noise spectrum density is
147 dBv/ Hz (45 nv = Hz) @ 25 MHz. The output-referred integrated noise voltage
is 485 μV from 20 Hz to 25 MHz.

1. Introduction
The trend toward smaller channel-length CMOS transistors operating
under a single low-voltage power supply has escalated in recent years.
According to recent semiconductor roadmaps, the supply voltages being
aimed at high-performance processor and low-power application are set
to be less than 0.6 V and 0.54 V in 2026, respectively [1]. At the same
time, wireless sensor networks, portable diagnosing equipment and
implanted biomedical devices have emerged as new exciting application
domains [2–5], such as the bio-potential recording or sensor device
application. These applications are highly energy constrained and
require flexible, integrated, energy-efficient analog modules that can
ideally operate at the same supply voltage as digital circuits.
In recent years, many researchers have shown most interests in
reducing ADC power for low-power application [7,8], for example, the
great success and popularity of SAR ADC. But an important power con-
sumption contributor generally lacks of enough attentions. Input drivers
are essential to drive the sampling capacitor load presented by the ADC
while maintaining distortion and noise levels that are lower than that of
the ADC.
In comparison with the power consumption of ADC itself, the driver
takes up the majority, which is particularly severe for low-voltage ones.
When the supply voltage approaches the threshold voltage, transistors
operating in weak inversion region bring a higher distortion and a lower
bandwidth [3]. Thus conventional analog circuit techniques encounter
difficulties in this situation [9]. However, if a higher supply voltage is
used specially for the driver, the overall power of chip would increase
obviously, and additional reference circuit is required. Therefore it is
required to design a driver operating under the same low supply voltage.
In this paper, a low-voltage OTA is proposed and its implementation of an
input driver achieving the single-ended to differential conversion is ob-
tained. Operating from the supply of 0.6 V, the designed OTA provides
the satisfying output signal for the ADC. Additionally, considering that
the outputs of OTA are just sampled by ADC in the sampling phase, which
occupies a small fraction of the whole quantization period for ADC, the
switched-opamp technology is designed to save the static power and
guarantee the fast starting up by turning off the output stage instead of
the entire amplifier in the quantization phase.
The paper is organized as follows. Section II describes and analyzes
key technologies for the proposed OTA. The experimental results
measured from the prototype are presented in Section III. Section IV
presents the conclusions.
2. Architecture of proposed PD OTA with SO technique
The architecture of proposed low-voltage, pseudo-differential OTA

* Corresponding author.
E-mail addresses: wangjingyu@xidian.edu.cn (J. Wang), liyongyuan@xidian.edu.cn (Y. Li), zmyh@263.net (Z. Zhu).

https://doi.org/10.1016/j.mejo.2019.06.002
Received 23 March 2019; Received in revised form 4 June 2019; Accepted 7 June 2019
Available online 8 June 2019
0026-2692/© 2019 Elsevier Ltd. All rights reserved.
J. Wang et al. Microelectronics Journal 90 (2019) 117–122

VDD
R3 R2
R1
Vin _
VIP + Von
1ST 2ND Vout
VIN _ + Vop
VCM
R1 R

R3 R2
VDD
(a)
Class-AB Output Stage CMFF Class-AB Output Stage

MS4 R V1 R
MS5
M15 M9 M10 M1 M2 M12 M13 M17
R5 R6
M19 M21
Iosn M3 VB1 Iosp
Von Vop
Rc Cc Cc Rc
M18 M20
R VQ R
MS2 R M14 MB1MS1 M8 M4 M 5 M6 M 7 M11 M16 MS3
VQ VIN VIP

Gate-Input OTA with Cross-coupled Pair

(b)

Fig. 1. The proposed fully differential driver and low-voltage pseudo-differential OTA. (a) The fully differential driver for the conversion from single-end signal to the
differential ones. (b) The structure of proposed low-voltage pseudo-differential OTA with SO technique.

with switched-opamp technique and its application in the fully differ-
ential driver is shown in Fig. 1. In the most cases, for better common
mode interference and even harmonic suppression, the single-ended
biopotential signal [13] or sensor signal [14,15] Vin is received and
transformed into the fully differential signal by input driver in the
inverting feedback architecture. In this paper, the gain settings of 0 dB
and 6 dB could be chosen for various signal swing of Vin. The resistance
R1 in Fig. 1 is equal to R2 or R2/2, depending on the value of the voltage
gain (0 dB and 6 dB respectively). The dc common-mode voltage of input
signal Vin is equal to VDD/2. The common-mode voltage of output signals
Von and Vop are typically set to be VCM¼VDD/2, and VDD is equal to 0.6 V.
In order to push the virtual ground point voltage VIP and VIN to reach
0.45 V (which allows proper biasing of the input transistors), additional
resistance R3 is inserted from virtual grounds to VDD, where
R3¼(R1//R2). The voltage VIN and VIP experience swings that are
0.5VCM*R1/(R1þR2) ¼ (1/6)VCM or (1/4)VCM, equaling 50 mV or
75 mV for different gain settings, respectively. Thus the input terminals
of OTA vary in a maximum voltage range from 0.375 to 0.525 V. In the
most low-power applications of bio-potential recording or sensor device
signal quantization, the outputs of the fully differential driver are
sampled by the followed ADC, such as SAR ADC. To further reduce the
static power consumption of amplifier, the switched-opamp technique is
designed in the driver. As shown in Fig. 1, a control signal ΦR is used to
turn off the output stage of driver amplifier instead of the entire amplifier
in most time of ADC quantization phase.
Operating from a low supply voltage of 0.6 V, the conventional low-
voltage amplifier techniques, such as the sub-threshold transistors and
bulk-driven MOSFETs, should be adopted. However, the OTA with
transistors biased in sub-threshold region has a low bandwidth character
of a few kilohertz and low slew rate values in spite that the power
consumed by the OTA is just only a few nanowatts [3]. As said above,
bulk-driven has also been adopted extensively for low voltage
applications [2] due to the elimination of the threshold voltage
requirement and the extension of the allowed operating range. But for the
single-stage OTA, the bulk-driven structure [19] suffers from the poor DC
gain and gain-bandwidth performance with larger noise and offset [10],
due to the usage of gmb instead of gate transconductance gm.
The proposed OTA uses gate inputs with the body terminal biasing
[18] to meet design requirements. The circuits adopt two-stage topology.
Miller compensating capacitors and resistances are employed between
input stage and output stage to ensure stability. In the standard 0.18 μm
CMOS process, the typical threshold voltage is 0.4 V–0.5 V, resulting
incorrect operation in ultra-low supply voltage. Therefore for the lower
threshold voltage, the bodies of transistors in the designed circuits are
generally forward-biased across the body-source junctions. The body
terminals of nmos transistor are connected to the bias voltage of 500 mV,
while the body terminals of pmos transistor are connected their gates.
The pseudo-differential pair, shown in Fig. 1 (b), removes the tail
current source, enabling a differential stage with a maximum transistor
stack-up of two. By eliminating the constraint of the tail current source,
the pseudo-differential pair can achieve wider input range for reduced
power-supply applications [6]. However, the main drawback of the
pseudo-differential pair is the severe deterioration in common-mode
rejection; the CMRR equals 1 if no any technology is used to modify. In
order to ameliorate this degradation, a common-mode feedforward
(CMFF) replica circuit, as shown in Fig. 1 (b), can be used to sense the
input voltage. The CMFF structure consists of transistors M8, M9, M10 and
M11, M12, M13. Superior to the previous CMFF structure [6], a new one is
proposed here with the two cross-coupled branches in the feed-forward
path. For the input stage with proposed CMFF structure, the small
signal equivalent circuit is presented in Fig. 2 below. Assuming that the
VIN¼VCM þ Vin, VIP¼VCM þ Vip, and Vin and Vip are variations in inputs of
OTA, equaling to ΔVcmþ0.5*ΔVdm and ΔVcm-0.5*ΔVdm, respectively.
The sizes of M9, M10, M12, M13 are equal, therefore the

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J. Wang et al. Microelectronics Journal 90 (2019) 117–122

gm12VY gm10VX
the OTA is considered as a single-pole system. Therefore the unity-gain
1/gm9 ro12 ro1 R5 r r 1/gm13
VX gm8/gm9Vin Vosn VospR6 o2 o10 VY gm11/gm13Vip bandwidth of designed driver is high enough that sufficiently sup-
Vin V1 gm8V1 ro8 gm4V1 ro4 ro5 -1/gm5 -1/gm6 ro6 ro7 gm7V2 ro11 gm11V2 V2 Vip presses the distortion to low levels for satisfying the linearity
requirement.
The noise is another important parameter and the total integrated
Fig. 2. Small signal equivalent circuit of proposed input stage.
output noise of driver, which is what would be sampled on sampling
transconductance gm10 ¼ gm9, gm13 ¼ gm12. The input pairs M4 and M7 capacitance in ADC, is required to be lower than 677 μV. Therefore an
pffiffiffiffiffiffi
have the same size as the transistors M8 and M11 in the CMFF. Thus input-referred white noise spectral density of 68 nv= Hz should be ob-
gm4 ¼ gm8 ¼ gm7 ¼ gm11 ¼ gmn. The cross-coupled pair M5, M6 in the first tained through 25 MHz bandwidth, which consists of the noise compo-
stage acts as a negative conductance and increases the output impedance. nents introduced by input resistance R1, feedback resistance R2 and
The node voltage VX and VY are gate voltages of M9 and M13, which equal additional resistance R3 substantially. We use R1 ¼ 50 kΩ, R2 ¼ 100 kΩ
VX ¼ gm8V1*(ro8//1/gm9)Vin*(gm8/gm9) and VY ¼ gm11V2*(ro11//1/ and R3 ¼ 11.2 kΩ. The noise model of the proposed driver is shown in
gm13)Vip*(gm11/gm13). Additionally, the output impedances of Vosn and Fig. 3. The total input referred noise can be obtained in Equation (6).
Vosp are 1/(gds12þgds1þgds4þgds5þ1/R5-gm5) and 1/
2
(gds10þgds2þgds6þgds7þ1/R6-gm6), where gds ¼ 1/ro. The current in V 2in;tot ¼ V 2n;in;op þ 4kTR1 þ 4kTR3 þ 4kTR2 =ðR2 =R1 Þ (6)
points Vosn and Vosp would be obtained as follows.
where V2n;in;op is contributed by the differential amplifier. The other three
iosn ¼ gm4 V1
gm12 VY¼gm4 *ðΔVcm þ 0:5 * ΔVdm Þ
gm12 *ðgm11 =gm13 Þ*ðΔVcm
terms are introduced by resistances R1, R2 and R3, respectively. Accord-

0:5 * ΔVdm Þ ing to Equation (6), it is obvious that resistances have a negative effect on
(1) the total input inferred noise. The thermal noise of R1, R2, and R3 are
pffiffiffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffi
equal to 29nv = Hz, 41nv = Hz, and 19.5 nv = Hz. The input-referred
iosp ¼ gm7 V2
gm10 VX ¼ gm7 *ðΔVcm
0:5 * ΔVdm Þ noise analysis of proposed OTA can be obtained as following. The

gm10 *ðgm8 =gm9 Þ*ðΔVcm þ 0:5 * ΔVdm Þ (2) noise of the amplifier is mainly determined by the input transistors. In
fact, noise contribution of the class AB output stage is divided by the gain
The sizes of M4, M7, M8 and M11 are equal, thus of input stage. So the impact caused by output stage in total noise is small.
gm4 ¼ gm7 ¼ gm8 ¼ gm11. Meanwhile, the sizes of M9, M10, M12 and M13 It is possible to calculate the noise without the contribution of output
are equal. Therefore, the following equation could be obtained by stage.
combining Equation (1) and (2).
 
2  4kT V n;outstage
2
1 gm1 gm10 gm5
iout ¼ iosn
iosp ¼ 2gm4 *ΔVdm (3) V 2n;in;op ¼ 8kTγ 1þ þ þ þ 2 þ 2 (7)
gm4 gm4 gm4 gm4 gm4 R5 Afirst
stage
The transconductance of input stage is
  where k is the Boltzmann's constant (1.38*10
23 JK
1), the factor γ is
Gm ¼ iout Vin
Vip ¼ 2gm4 (4)
equal to 2/3, Afirst-stage is the gain of input stage, and V2n;outstage is the noise
As observed from above equations, by means of the proposed CMFF component of the class AB output stage. Input differential pairs are
method with a simple cross connection, the overall transconductance is supposed to provide a thermal noise voltage inversely proportional to the
doubled and consequently a 6-dB enhancement of CMRR is obtained in transconductance gm4. The widths and lengths of all transistors as well as
comparison with the previous work [18]. But the CMRR of proposed OTA other component values are give in Table I. The resistors R5 and R6,
is still inferior to the fully differential one due to the lack of tail current.
The designed class-AB output stage in Fig. 1, included transistors
M18~M21, is driven by the output of the previous stage and a voltage
R3
shifter, M14~M17. A biased NMOS transistor is used as a voltage shifter,
which allows low supply voltage, avoiding the stacking of two VR23 R2
gate-to-source voltages. The overall differential gain of the described
amplifier is Vn2,in ,op
Vin
+ _
2gm4 ðgm19 þ gm18 Þ
vp V on VR2
2
ADM ¼  (5)
gds4 þ gds5 þ gds1 þ gds12 þ R15
gm5 ðgds19 þ gds18 Þ R1 2
Vout
2 ,tot
V R1
For a sufficient phase margin, the low-voltage OTA is designed using
two-stage structure with Miller compensation capacitor. Thus the OTA vn _ +
can be analyzed as a single-pole system with the second pole locating V op
above the unity-gain bandwidth. The proposed OTA is designed as the
core amplifier of an input driver for low-power ADC. Taking 10-bit 1 MS/
s SAR ADC application as an example, the sampling phase takes up 1/3 of Fig. 3. The noise model of differential driver using resistance feedback.
one quantization period. It is required that the input driver could settle to
Table 1
a 10 bit accuracy (0.1%) in 0.3 μs through a step response. The settling Transistor sizes and element values for amplifier.
time of OTA depends on many factors, for example, GBW, SR, etc. But for
Input stage Output stage
simplifying the analysis, we take the unity-gain bandwidth of OTA as a
major factor to provide a guide in our design. Therefore, the unity-gain Transistors w (μm) l (μm) Transistors w (μm) l (μm)
bandwidth of proposed OTA is needed to be over 50 MHz in the M1 M2 270 0.36 M14 M16 60 0.36
design. The total harmonic distortion (THD) better than
56 dB is M3 64 0.36 M15 M17 336 1.50
required in the driver for full-scale inputs at the frequency ranging from M4 M7 72 0.36 M18 M20 84 0.36
M5 M6 9 0.36 M19 M21 200 0.36
0 to 500 KHz. Considering that the OTA has a unity-gain bandwidth of M8 M11 18 0.36 Resistors and Capacitors
50 MHz, the loop gain is higher than 40 dB in the frequency range below M9 M13 67.5 0.36
500 KHz (corresponding to the Nyquist sampling fs.max>2fin.max) when M10 M12 270 0.36 Rc 750 Ω Cc 1.5 pF

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J. Wang et al. Microelectronics Journal 90 (2019) 117–122

0.4 2500
TT 27 SS 85 FF -40
0.3
-0.25 mu=261 ns
2000

Number of Samples
0.2
-0.3
sd =18.7 ns
Voltage (V)

0.1 -0.35
1500
31.0 31.2 31.4
0
0.35 1000
-0.1

-0.2 0.3
500
-0.3 0.25
33.0 33.2 33.4
-0.4 0
30.8 31.2 31.6 32.0 32.4 32.8 33.2 33.6 34.0 34.4 227 237 247 257 267 277 287
Time (us) Settling time (ns)

(a) (b)
Fig. 4. Step response of the proposed input driver and Monte-Carlo simulation results of settling time. (a)Step response of the proposed input driver under different
corners. (b) MC simulation results.

which are equal to 25 kΩ, make a local CMFB and can be used as trans-
conductance boosting resistors [16,17]. The use of long-channel tran-
sistors (360 nm) in input differential pairs improve the device matching
and relieve the influence of short-channel effect.
To further improve power efficiency, a switched class AB output stage
is designed in this paper, enabling the proposed amplifier to achieve
power saving. By only turning off the output stage instead of the entire
amplifier during the quantization phase, a fast recovery from the off state

could be guaranteed. In the sampling phase of ADC, a low clock signal ΦR
makes the conductivity of MS1 equal to 0 and MB1 will act normally as if
MS1 is not present. After the sampling operation, a high clock signal ΦR
enables the switch transistor MS1 to short the bias transistor MB1, making
no current flows through M14 and M16. Additionally, switches MS2~MS5
controlled by the clock signals ΦR , ΦR are used to cut off the output stage
current for reducing power consumption. A small switchable resistor of
MS2~MS5 should be chosen for low VDS voltage which decreases the
output swing directly. Therefore gds,MS2~5 must be much higher than
gm,M18~21. Due to the proposed switched-opamp technique, the settling
time of designed OTA, Tso ¼ ton þ tsettling, which is a little longer than the
one of traditional opamps due to an added time of ton. Switching-on time
ton is limited by the structure of switched opamp, and ton of proposed
amplifier is shorter than the one with the whole opamp turning off
entirely. Fig. 4 (a) shows the simulated step response of the proposed
amplifier in the closed-loop operation and the output voltage reaches
0.3 V in different temperature and corner variations. In the TT corner,
the proposed amplifier achieves a settling time tsettling of 260 ns with 0.1%
accuracy at room temperature. To illustrate the process variation
robustness of the proposed driver, Monte Carlo analysis was run for
10000 samples while the settling time (the output swing of 0.3 V with
0.1% accuracy) of the driver was observed. Fig. 4(b) shows the expected
distribution. The settling time has a normal distribution with an average
value near 261 ns and standard deviation of less than 18.7 ns. The
maximum value of settling time is less than 290 ns. It indicates that the
provided driver could settle in the 0.3 μs with required precision.
Considering the switching-on time ton, however, Tso should be more than
0.407 μs according to the simulated result. In the real application, if the
ADC sampling rate is set to be the maximum value of 1 MS/s, the sam-
pling phase time could not satisfy Tso. Targeting this issue, a feedback
signal ΦR is adopted as the control signal of switched-opamp, which is
enabled after the data bit D4 is obtained. ΦR closes the SO switch
MS1~MS5 of output stage in advance for stabilizing the OTA before the
sampling phase. Therefore, the TSO is long enough to ensure the ADC
sampling accuracy. And the average 27% power saving is achieved
through the designed SO input buffer.
Input driver
ADC
Fig. 5. Microphotograph of the proposed OTA in input buffer implementation.
3. Experimental results
Implemented in the 0.18 μm standard CMOS process, the proposed
circuits occupy an active die area of 0.05 mm2and were found to perform
as expected in the required operational conditions. The chip micropho-
tograph is shown in Fig. 5. The measurement result of step response is
given in Fig. 6. The settling time is 0.31 μs when an input signal with the
magnitude of 300 mVpp and the frequency of 500 kHz is used. It is longer
than the simulation results (shown in Fig. 4) due to the parasitic capac-
itance. But it is normal and could satisfy the real application through
modulating the sampling time of the followed ADC. Additionally, the
frequency response of proposed OTA in closed loop configuration is
shown in Fig. 7. Under the closed loop gain of 6 dB, the input signals with
different frequencies are provided, and the corresponding outputs are
measured to verify the frequency characteristic. According to the sum-
marized results of discrete frequencies, it is observed that the designed
work keeps the stable closed gain characteristic below 30 MHz in spite of
some slight gain degradations.
In addition, the measured input noise spectrum density of the input
pffiffiffiffiffiffi pffiffiffiffiffiffi
buffer is
147 dBv/ Hz (45 nv = Hz) @ 25 MHz, shown in Fig. 8. The
output-referred integrated noise voltage is 485 μV from 20 Hz to 25 MHz.
It could satisfy the quantization noise requirement of the subsequent
ADC. The main performance of proposed OTA is summarized in Table II.
It is indicated that the proposed OTA has good FOM in comparison with

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J. Wang et al. Microelectronics Journal 90 (2019) 117–122

Ch1 (200mV)
Ch2 (500mV)

X (800ns)

Fig. 6. Measurement results of step response @ input signal of 500 kHz, 300mVpp

7 Table 2
Performance summary and comparison.
6
Parameter [1] [2] [10] [11] [12] This
work
5
Magnitude (dB)

Process (μm) 0.065 0.35 0.35 0.18 0.18 0.18

4 Supply Voltage (V) 0.5 1 0.9 1.8 0.7 0.6
Power dissipation (μW) 182 197 24.3 11900 25.2 259.8
Open-Loop Gain (dB) 46 88 65 72 57.5 51**
3
Unity-Gain Bandwidth 38 11.67 1 86.5 3 58**
(MHz)
2
Phase Margin (deg) 57 66 60 50 60 86**
Load Capacitance (pF) 3 15 10 200 20 8
1 Settling Time (300 mV NA NA NA NA NA 310
in 0.1%) (ns)
0 Input Ref Noise @ 938 NA 65 <0.8 100 45
0 1E7 2E7 3E7 4E7 5E7 pffiffiffiffiffiffi
500 KHz (nv = Hz)
Frequency (Hz)
CMRR (dB)@10 kHz 35 40 45 NA 19 44
PSRR (dB)@ 10 kHz 37 46.8 NA NA 52.1 32
Fig. 7. Measurement results of frequency response @ closed gain of 6 dB.
THD @ 500 KHz, NA NA NA NA NA
67
300 mV output (dB)
FOM* 31.3 88.9 37 262 166 107.1

FOM* ¼ 100  (fUGB  CL)/Idc, where Idc is the current consumption of OTA **
-120
indicates the simulation results.

-125
Noise Spectral Density

the most previous OTAs, satisfying the requirement of low power

application.
(dBvrms/rtHz)

-130

-135 4. Conclusion
Noise Density 45nv/rtHz
-140 A 0.6-V pseudo-differential OTA with transconductance-improved
technique using cross-coupled CMFF structure and switched-opamp
-145 technique is presented in this paper. Through analyzing the require-
ment of low-power ADC application, the OTA is modified and imple-
-150
10
3
10
4
10
5
10
6
10
7 mented in the input driver to satisfies the specification demand.
Frequency (Hz) According to the experimental results, the designed OTA achieves a good
performance in comparison with others.
Fig. 8. The input-referred voltage noise spectrum.

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J. Wang et al.
Acknowledgements
This work was supported by the National Natural Science Foundation
of China (61625403, 61804110) and Postdoctoral Science Foundation of
China (2018M643579).
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