A B C D E

ZZZ8

DAZ@
DAZ04300100
PCB

1 1

ZZZ1
DA2@
MAIN BOARD

DA600007E10
PCB

ZZZ2
DA2@
E board

DA40000A910
PCB

ZZZ3

DA2@
FP board

DA600007D10
Compal Confidential
PCB

ZZZ4

JAT10 M/B Schematics Document

2 DA2@ 2
Function board

DA40000AA10
PCB

ZZZ5
DA2@
USB board

DA40000AB10
Intel Penryn Processor with Cantiga + DDRII + ICH9M
PCB

ZZZ6

DA2@
IO board

DA40000AC10
PCB

ZZZ7

3
DA2@
Power board

DA40000AD10
2008-04-07 3
PCB

REV:1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 1 of 42
A B C D E
 A B C D E

Compal confidential Docking CONN

File Name : LA-4271P Montevina PAGE 24

Fan Control
LED page 4 CRT
page 34
1 1
Thermal Sensor CK505

RTC CKT. EMC1402-1 Mobile Penym Clock Generator

Docking cable DVI-D Conn.
page 4
page 19 uFCPGA-478 CPU SLG8SP553V
page 15

page 4,5,6
10/100 LAN
Power On/Off CKT.
page 31 LVDS conn
page 17
USB 2.0
H_A#(3..35) FSB
H_D#(0..63)
667/800/1066MHz 1.05V
CRT Headphone
DC/DC Interface CKT. page 16
page 33 Intel Cantiga GM DDR2 800MHz 1.8V
DDR2-SO-DIMM X2
BANK 0, 1, 2, 3 page 13,14 MIC
FCBGA 1329 Dual Channel
2 2

page 7,8,9,10,11,12
BT Conn USB x 1 Line in Jack
Docking CONN CH7318 page28
PAGE 24
page 17
Finger printer x1
page 31
DMI X4
USB conn x 3(For I/O)
USB2.0 page28
Card reader(XD/SD Card Reader
HD
MMC/MS/MS-Pro
SD) JMB385 Intel ICH9-M Azalia
USB x1(Camara) Line in Jack
page 26
page27 page27 SATA0 page17
PCI-E mBGA-676
SATA1
page 18,19,20,21 Audio AMP Headphone
page 26 SPDIF Jack
page 26
HD Codec
3
ALC888 3
page 25
New Card LAN(GbE) LPC BUS MIC ARRAY
Mini-Card X 1 SM BUS page 25
page28
RTL8111C SLOT1 : PCIE
page 23
page 22

MDC CONN MIC JACK

EnE KB926 page 26
RJ45 Ver 1.5 page 31

page 30
page 24

Int.KBD
page 30 2.5" SATA HDD Connector
Touch Pad CONN. page 22
page 31

4
BIOS page 29
SATA ODD Connector 4

page 22

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 2 of 42
A B C D E
 A

O MEANS ON X MEANS OFF

Voltage Rails

Symbol Note :
+5VS
+3VS
+1.5VS
: means Digital Ground
power
plane +0.75V
+VCCP
+5VALW +1.5V +CPU_CORE : means Analog Ground
+B
+3VALW @ : means just reserve , no build
DEBUG@ : means just reserve for debug.
State +1.8VS

S0
O O O O
S1
O O O O
S3
O O O X
S5 S4/AC
O O X X
S5 S4/ Battery only
O X X X
S5 S4/AC & Battery
1
don't exist X X X X SMBUS Control Table
1

THERMAL
SERIAL SENSOR
SOURCE INVERTER BATT EEPROM (CPU) SODIMM CLK CHIP MINI CARD LCD

SMB_EC_CK1
SMB_EC_DA1
KB926 X V V X X X X X
SMB_EC_CK2
SMB_EC_DA2
KB926 X X X V X X X X
SMB_CK_CLK1
SMB_CK_DAT1 ICH9 X X X X V V V X
LCD_CLK
LCD_DAT Cantiga
X X X X X X X V

I2C / SMBUS ADDRESSING

DEVICE HEX ADDRESS

DDR SO-DIMM 0 A0 10100000
DDR SO-DIMM 1 A4 10100100
CLOCK GENERATOR (EXT.) D2 11010010
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 3 of 42
A
 5 4 3 2 1

D D
+VCCP

XDP_TDI R60 1 2 150_0402_1%

<BOM Structure>
XDP_TMS R50 1 2 39_0402_1%
CONN@
(7) H_A#[3..16]
JCPU1A
H_A#3 J4 H1 H_ADS#
A[3]# ADS# H_ADS# (7)

ADDR GROUP_0
H_A#4 L5 E2 H_BNR#
A[4]# BNR# H_BNR# (7)
H_A#5 L4 G5 H_BPRI#
A[5]# BPRI# H_BPRI# (7)
H_A#6 K5 XDP_TRST# R62 1 2 56_0402_5%
H_A#7 A[6]# H_DEFER#
M3 A[7]# DEFER# H5 H_DEFER# (7)
H_A#8 N2 F21 H_DRDY# XDP_TCK R49 1 2 54.9_0402_1%
A[8]# DRDY# H_DRDY# (7)
H_A#9 J1 E1 H_DBSY# <BOM Structure>
A[9]# DBSY# H_DBSY# (7)
H_A#10 N3
H_A#11 A[10]# H_BR0#
P5 A[11]# BR0# F1 H_BR0# (7)
H_A#12 P2 A[12]#

CONTROL
H_A#13 L2 D20 H_IERR# T1
H_A#14 A[13]# IERR# H_INIT#
P4 A[14]# INIT# B3 H_INIT# (19)
H_A#15 P1
H_A#16 A[15]# H_LOCK#
R1 A[16]# LOCK# H4 H_LOCK# (7)
H_ADSTB#0 M1
(7) H_ADSTB#0 ADSTB[0]#
C1 H_RESET#
RESET# H_RESET# (7)
H_REQ#0 K3 F3 H_RS#0
(7) H_REQ#0 REQ[0]# RS[0]# H_RS#0 (7)
H_REQ#1 H2 F4 H_RS#1
(7) H_REQ#1 REQ[1]# RS[1]# H_RS#1 (7)
H_REQ#2 K2 G3 H_RS#2
(7) H_REQ#2 REQ[2]# RS[2]# H_RS#2 (7)
H_REQ#3 J3 G2 H_TRDY#
(7) H_REQ#3 REQ[3]# TRDY# H_TRDY# (7)
H_REQ#4 L1
(7) H_REQ#4 REQ[4]#
G6 H_HIT#
(7) H_A#[17..35] HIT# H_HIT# (7)
H_A#17 Y2 E4 H_HITM#
C A[17]# HITM# H_HITM# (7) C
H_A#18 U5
H_A#19 A[18]#
R3 A[19]# BPM[0]# AD4
ADDR GROUP_1

H_A#20 W6 AD3
H_A#21 A[20]# BPM[1]#
U4 A[21]# BPM[2]# AD1
H_A#22 Y5 AC4
A[22]# BPM[3]#
XDP/ITP SIGNALS

H_A#23 U1 AC2
H_A#24 A[23]# PRDY# XDP_BPM#5 T120
R4 A[24]# PREQ# AC1
H_A#25 T5 AC5 XDP_TCK +3VS
H_A#26 A[25]# TCK XDP_TDI
T3 A[26]# TDI AA6
H_A#27 W2 AB3
H_A#28 A[27]# TDO XDP_TMS
W5 A[28]# TMS AB5

0.1U_0402_16V4Z
H_A#29 Y4 AB6 XDP_TRST# 1
H_A#30 A[29]# TRST# XDP_DBRESET#
U2 A[30]# DBR# C20 XDP_DBRESET# (20)
H_A#31 V4 C2
H_A#32 A[31]# SA00001Z700
W3 A[32]#
H_A#33 2
AA4 A[33]# THERMAL
H_A#34 AB2 H_PROCHOT# R13 1 2 68_0402_5% U1
H_A#35 A[34]# +VCCP SMB_EC_CK2
AA3 A[35]# PROCHOT# D21 1 VDD SCLK 8 SMB_EC_CK2 (30)
H_ADSTB#1 V1 A24 H_THERMDA_R R14 1 2 0_0402_5% H_THERMDA
(7) H_ADSTB#1 ADSTB[1]# THERMDA
B25 H_THERMDC_R R15 1 2 0_0402_5% H_THERMDC H_THERMDA 2 7 SMB_EC_DA2
THERMDC D+ SDATA SMB_EC_DA2 (30)
H_A20M# A6 C3
(19) H_A20M# A20M#
ICH

H_FERR# A5 C7 H_THERMTRIP# 1 2 H_THERMDC 3 6 1 R195 2 +3VS

(19) H_FERR# FERR# THERMTRIP# H_THERMTRIP# (7,19) D- ALERT/THERM2
H_IGNNE# C4 2200P_0402_50V7K 10K_0402_5%
(19) H_IGNNE# IGNNE#
4 THERM GND 5
H_STPCLK# D5
(19) H_STPCLK# STPCLK#
H_INTR C6 H CLK
(19) H_INTR LINT0 ADT7421ARMZ-REEL_MSOP8
H_NMI B4 A22 CLK_CPU_BCLK Address:100_1100
(19) H_NMI LINT1 BCLK[0] CLK_CPU_BCLK (15)
H_SMI# A3 A21 CLK_CPU_BCLK#
(19) H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# (15)
M4 RSVD[01]
N5 RSVD[02] H_THERMDA, H_THERMDC routing together,
T2
B
V3
RSVD[03]
RSVD[04]
Trace width / Spacing = 10 / 10 mil 2007/09/011 FAN1 Conn B
RESERVED

B2 RSVD[05]
D2 RSVD[06]
D22 +5VS
RSVD[07] C638 +5VS
D3 RSVD[08]
F6 RSVD[09] 1 2

1
10U_0805_10V4Z
U19 D53
1 VEN 8 1SS355_SOD323-2
Penryn GND
2 VIN GND 7
+VCC_FAN1 3 VO 6 <BOM Structure>

2
EN_FAN11 GND
(30) EN_FAN1 2 0_0402_5%
4 VSET GND 5 D54
1 1 2
+VCCP R1007 C949 G993P1UF_SOP8
0.1U_0402_16V4Z BAS16_SOT23-3
SA00002GW00 <BOM Structure>
2 C639
1

@ 1 2
R17 @ 10U_0805_10V4Z
56_0402_5% +3VS C640
1000P_0402_50V7K
1 2
2 2

1
B

R538
10K_0402_5%
E

H_PROCHOT# 3 1 OCP# 40mil

OCP# (20)
C

@ Q2 JP32

2
MMBT3904_SOT23 +VCC_FAN1
1
(30) FAN_SPEED1 2
+VCCP 3
1
A C641 ACES_85205-03001 A
1000P_0402_50V7K CONN@
2

R18 2
56_0402_5%
<BOM Structure>
1

H_IERR# Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 4 of 42
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE +VCC_CORE
(7) H_D#[0..15] CONN@ CONN@
H_D#[32..47] (7)
JCPU1B JCPU1C
H_D#0 E22 Y22 H_D#32 A7 AB20
H_D#1 D[0]# D[32]# H_D#33 VCC[001] VCC[068]
F24 D[1]# D[33]# AB24 A9 VCC[002] VCC[069] AB7
H_D#2 E26 V24 H_D#34 A10 AC7
D[2]# D[34]# VCC[003] VCC[070]

DATA GRP 0
H_D#3 G22 V26 H_D#35 A12 AC9

DATA GRP 2
D H_D#4 D[3]# D[35]# H_D#36 VCC[004] VCC[071] D
F23 D[4]# D[36]# V23 A13 VCC[005] VCC[072] AC12
H_D#5 G25 T22 H_D#37 A15 AC13
H_D#6 D[5]# D[37]# H_D#38 VCC[006] VCC[073]
E25 D[6]# D[38]# U25 A17 VCC[007] VCC[074] AC15
H_D#7 E23 U23 H_D#39 A18 AC17
H_D#8 D[7]# D[39]# H_D#40 VCC[008] VCC[075]
K24 D[8]# D[40]# Y25 A20 VCC[009] VCC[076] AC18
H_D#9 G24 W22 H_D#41 B7 AD7
H_D#10 D[9]# D[41]# H_D#42 VCC[010] VCC[077]
J24 D[10]# D[42]# Y23 B9 VCC[011] VCC[078] AD9
H_D#11 J23 W24 H_D#43 B10 AD10
H_D#12 D[11]# D[43]# H_D#44 VCC[012] VCC[079]
H22 D[12]# D[44]# W25 B12 VCC[013] VCC[080] AD12
H_D#13 F26 AA23 H_D#45 B14 AD14
H_D#14 D[13]# D[45]# H_D#46 VCC[014] VCC[081]
K22 D[14]# D[46]# AA24 B15 VCC[015] VCC[082] AD15
H_D#15 H23 AB25 H_D#47 B17 AD17
H_DSTBN#0 D[15]# D[47]# H_DSTBN#2 VCC[016] VCC[083]
(7) H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 (7) B18 VCC[017] VCC[084] AD18
H_DSTBP#0 H26 AA26 H_DSTBP#2 B20 AE9
(7) H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 (7) VCC[018] VCC[085]
H_DINV#0 H25 U22 H_DINV#2 C9 AE10
(7) H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 (7) VCC[019] VCC[086]
(7) H_D#[16..31] H_D#[48..63] (7) C10 VCC[020] VCC[087] AE12
C12 VCC[021] VCC[088] AE13
H_D#16 N22 AE24 H_D#48 C13 AE15
H_D#17 D[16]# D[48]# H_D#49 VCC[022] VCC[089]
K25 D[17]# D[49]# AD24 C15 VCC[023] VCC[090] AE17
H_D#18 P26 AA21 H_D#50 C17 AE18
H_D#19 D[18]# D[50]# H_D#51 VCC[024] VCC[091]
R23 D[19]# D[51]# AB22 C18 VCC[025] VCC[092] AE20
H_D#20 L23 AB21 H_D#52 D9 AF9
D[20]# D[52]# VCC[026] VCC[093]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D10 AF10

DATA GRP 3
H_D#22 D[21]# D[53]# H_D#54 VCC[027] VCC[094]
L22 D[22]# D[54]# AD20 D12 VCC[028] VCC[095] AF12
H_D#23 M23 AE22 H_D#55 D14 AF14
H_D#24 D[23]# D[55]# H_D#56 VCC[029] VCC[096]
P25 D[24]# D[56]# AF23 D15 VCC[030] VCC[097] AF15
H_D#25 P23 AC25 H_D#57 D17 AF17
H_D#26 D[25]# D[57]# H_D#58 VCC[031] VCC[098]
P22 D[26]# D[58]# AE21 D18 VCC[032] VCC[099] AF18
H_D#27 T24 AD21 H_D#59 E7 AF20 +VCCP
H_D#28 D[27]# D[59]# H_D#60 VCC[033] VCC[100]
R24 D[28]# D[60]# AC22 E9 VCC[034]
H_D#29 L25 AD23 H_D#61 E10 G21 R19 1 2 0_0402_5%
H_D#30 D[29]# D[61]# H_D#62 VCC[035] VCCP[01]
T25 D[30]# D[62]# AF22 E12 VCC[036] VCCP[02] V6 R20 1 2 0_0402_5%
C H_D#31 H_D#63 C
N25 D[31]# D[63]# AC23 E13 VCC[037] VCCP[03] J6
H_DSTBN#1 L26 AE25 H_DSTBN#3 E15 K6 1
(7) H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 (7) VCC[038] VCCP[04]
H_DSTBP#1 M26 AF24 H_DSTBP#3 E17 M6
(7) H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 (7) VCC[039] VCCP[05] + C6
H_DINV#1 N24 AC20 H_DINV#3 E18 J21
(7) H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 (7) VCC[040] VCCP[06]
E20 K21 330U_D2E_2.5VM_R15
V_CPU_GTLREF COMP0 VCC[041] VCCP[07]
AD26 GTLREF COMP[0] R26 F7 VCC[042] VCCP[08] M21
@ R21
@R21 2
1 2 1K_0402_5% TEST1 C23 TEST1 MISC COMP[1] U26 COMP1 F9 VCC[043] VCCP[09] N21
@R22
@ R22 1 2 1K_0402_5% TEST2 D25 AA1 COMP2 F10 N6 0814 Change to 220uF
TEST3 TEST2 COMP[2] COMP3 VCC[044] VCCP[10]
T2 C24 TEST3 COMP[3] Y1 F12 VCC[045] VCCP[11] R21
TEST4 AF26 F14 R6 0819 Change to C_D2E
T3 TEST4 VCC[046] VCCP[12]
TEST5 AF1 E5 H_DPRSTP# R23 R24 R25 R26 F15 T21
T4 TEST5 DPRSTP# H_DPRSTP# (7,19,40) VCC[047] VCCP[13]

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%
TEST6 A26 B5 H_DPSLP# F17 T6
T5 TEST6 DPSLP# H_DPSLP# (19) VCC[048] VCCP[14]

1
TEST7 C3 D24 H_DPWR# F18 V21
T6 TEST7 DPWR# H_DPWR# (7) VCC[049] VCCP[15]
CPU_BSEL0 B22 D6 H_PWRGOOD F20 W21
(15) CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGOOD (19) VCC[050] VCCP[16]
CPU_BSEL1 B23 D7 H_CPUSLP# AA7
(15) CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# (7) VCC[051]
CPU_BSEL2 C21 AE6 H_PSI# AA9 B26
(15) CPU_BSEL2 BSEL[2] PSI# H_PSI# (40) VCC[052] VCCA[01] +1.5VS
AA10 C26

2
VCC[053] VCCA[02]

10U_0805_6.3V6M

0.01U_0402_16V7K
Penryn AA12 VCC[054]
AA13 VCC[055] VID[0] AD6 CPU_VID0 (40)
AA15 VCC[056] VID[1] AF5 CPU_VID1 (40) 1 1
AA17 VCC[057] VID[2] AE5 CPU_VID2 (40)
AA18 AF4 C7 C8
VCC[058] VID[3] CPU_VID3 (40)
AA20 VCC[059] VID[4] AE3 CPU_VID4 (40)
Resistor placed within AB9 AF3 CPU_VID5 (40) <BOM2 Structure><BOM2 Structure>
VCC[060] VID[5]
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs 0.5" of CPU pin.Trace AC10 VCC[061] VID[6] AE2 CPU_VID6 (40)
AB10 VCC[062]
should be at least 25 AB12 VCC[063]
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 AB14 AF7 VCCSENSE VCCSENSE (40)
mils away from any other AB15
VCC[064] VCCSENSE
Near pin B26
VCC[065]
toggling signal. AB17 VCC[066]
AB18 AE7 VSSSENSE VSSSENSE (40)
COMP[0,2] trace width is VCC[067] VSSSENSE
166 0 1 1
B 18 mils. COMP[1,3] trace Penryn B

width is 4 mils. .

200 0 0
Length match within 25 mils.
1
The trace width/space/other is
20/7/25.
266 0 0 0
+VCCP
1

R27
1K_0402_1%
<BOM Structure> +VCC_CORE
2

V_CPU_GTLREF
R28 1 2 100_0402_1% VCCSENSE
1

R29 R30 1 2 100_0402_1% VSSSENSE

2K_0402_1%
<BOM Structure>
2

Close to CPU pin AD26

Close to CPU pin
within 500mils.
within 500mils.
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 5 of 42
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE

1 1
C9
Place these capacitors on L8
(North side,Secondary Layer) 10U_0805_6.3V6M
2 2
1 1 1 1 1 1
C10 C11 C12 C13 C14 C15 C16
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2

D D
CONN@ +VCC_CORE
JCPU1D
A4 VSS[001] VSS[082] P6
A8 VSS[002] VSS[083] P21 1 1 1 1 1 1 1 1
A11 P24 C17 C18 C19 C20 C21 C22 C23 C24
VSS[003] VSS[084] Place these capacitors on L8
A14 VSS[004] VSS[085] R2
A16 R5 (North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[005] VSS[086] 2 2 2 2 2 2 2 2
A19 VSS[006] VSS[087] R22
A23 VSS[007] VSS[088] R25
AF2 VSS[008] VSS[089] T1
B6 VSS[009] VSS[090] T4
+VCC_CORE
B8 VSS[010] VSS[091] T23
B11 VSS[011] VSS[092] T26
B13 VSS[012] VSS[093] U3
B16 VSS[013] VSS[094] U6 1 1 1 1 1 1 1 1
B19 U21 C25 C26 C27 C28 C29 C30 C31 C32
VSS[014] VSS[095] Place these capacitors on L8
B21 VSS[015] VSS[096] U24
B24 V2 (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[016] VSS[097] 2 2 2 2 2 2 2 2
C5 VSS[017] VSS[098] V5
C8 VSS[018] VSS[099] V22
C11 VSS[019] VSS[100] V25
C14 VSS[020] VSS[101] W1
+VCC_CORE
C16 VSS[021] VSS[102] W4
C19 VSS[022] VSS[103] W23
C2 VSS[023] VSS[104] W26
C22 VSS[024] VSS[105] Y3 1 1 1 1 1 1 1 1
C25 Y6 C33 C34 C35 C36 C37 C38 C39 C40
VSS[025] VSS[106] Place these capacitors on L8
D1 VSS[026] VSS[107] Y21
D4 Y24 (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[027] VSS[108] 2 2 2 2 2 2 2 2
D8 VSS[028] VSS[109] AA2
D11 VSS[029] VSS[110] AA5
C C
D13 VSS[030] VSS[111] AA8
D16 VSS[031] VSS[112] AA11
D19 VSS[032] VSS[113] AA14 Mid Frequence Decoupling
D23 VSS[033] VSS[114] AA16
D26 VSS[034] VSS[115] AA19
E3 VSS[035] VSS[116] AA22
E6 VSS[036] VSS[117] AA25
E8 VSS[037] VSS[118] AB1
E11 VSS[038] VSS[119] AB4
E14 VSS[039] VSS[120] AB8
E16 VSS[040] VSS[121] AB11
E19 VSS[041] VSS[122] AB13
E21 VSS[042] VSS[123] AB16
E24 VSS[043] VSS[124] AB19
F5 VSS[044] VSS[125] AB23
F8 VSS[045] VSS[126] AB26
F11 VSS[046] VSS[127] AC3
F13 VSS[047] VSS[128] AC6
+VCC_CORE
F16 VSS[048] VSS[129] AC8
F19 VSS[049] VSS[130] AC11
F2 AC14 330U_D2E_2.5VM_R9
VSS[050] VSS[131]
F22 VSS[051] VSS[132] AC16
F25 VSS[052] VSS[133] AC19
G4 VSS[053] VSS[134] AC21
G1 VSS[054] VSS[135] AC24 1 1 1 1
G23 VSS[055] VSS[136] AD2
G26 AD5 C41 + C42 + C43 + C44 +
VSS[056] VSS[137] 330U_D2E_2.5VM_R9
H3 VSS[057] VSS[138] AD8
H6 VSS[058] VSS[139] AD11
2 2 2 2
H21 VSS[059] VSS[140] AD13
H24 VSS[060] VSS[141] AD16
J2 VSS[061] VSS[142] AD19
B 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 B
J5 VSS[062] VSS[143] AD22
J22 VSS[063] VSS[144] AD25
J25 VSS[064] VSS[145] AE1
K1 VSS[065] VSS[146] AE4
K4 VSS[066] VSS[147] AE8 0814 Change to C_D2E
K23 VSS[067] VSS[148] AE11
K26 VSS[068] VSS[149] AE14
L3 VSS[069] VSS[150] AE16 Place these inside
L6 VSS[070] VSS[151] AE19 socket cavity on L8
L21 VSS[071] VSS[152] AE23 (North side
L24 VSS[072] VSS[153] AE26
M2 A2
Secondary)
VSS[073] VSS[154]
M5 VSS[074] VSS[155] AF6
M22 AF8 +VCCP
VSS[075] VSS[156]
M25 VSS[076] VSS[157] AF11
N1 VSS[077] VSS[158] AF13
N4 VSS[078] VSS[159] AF16 1 1 1 1 1 1
N23 AF19 C45 C46 C47 C48 C49 C50
VSS[079] VSS[160]
N26 VSS[080] VSS[161] AF21
P3 A25 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
VSS[081] VSS[162] 2 2 2 2 2 2
VSS[163] AF25

Penryn
.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 6 of 42
5 4 3 2 1
 5 4 3 2 1

H_A#[3..35] (4) U2B

(5) H_D#[0..63] U2A
A14 H_A#3 M36
H_D#0 H_A#_3 H_A#4 RSVD1 M_CLK_DDR0

DDR CLK/ CONTROL/COMPENSATION

F2 H_D#_0 H_A#_4 C15 N36 RSVD2 SA_CK_0 AP24 M_CLK_DDR0 (13)

0.01U_0402_25V7K
H_D#1 H_A#5 M_CLK_DDR1

2.2U_0603_6.3V4Z
G8 H_D#_1 H_A#_5 F16 R33 RSVD3 SA_CK_1 AT21 M_CLK_DDR1 (13)
H_D#2 F8 H13 H_A#6 T33 AV24 M_CLK_DDR2 M_CLK_DDR2 (14)
H_D#3 H_D#_2 H_A#_6 H_A#7 +1.8V RSVD4 SB_CK_0 M_CLK_DDR3
E6 H_D#_3 H_A#_7 C18 AH9 RSVD5 SB_CK_1 AU20 M_CLK_DDR3 (14)
H_D#4 G2 M16 H_A#8 AH10
H_D#5 H_D#_4 H_A#_8 H_A#9 RSVD6 M_CLK_DDR#0
H6 H_D#_5 H_A#_9 J13 1 1 AH12 RSVD7 SA_CK#_0 AR24 M_CLK_DDR#0 (13)

1
C51

C52
H_D#6 H2 P16 H_A#10 AH13 AR21 M_CLK_DDR#1
H_D#_6 H_A#_10 RSVD8 SA_CK#_1 M_CLK_DDR#1 (13)
H_D#7 F6 R16 H_A#11 R31 K12 AU24 M_CLK_DDR#2
H_D#_7 H_A#_11 RSVD9 SB_CK#_0 M_CLK_DDR#2 (14)
H_D#8 D4 N17 H_A#12 1K_0402_1% AL34 AV20 M_CLK_DDR#3
H_D#_8 H_A#_12 2 2 RSVD10 SB_CK#_1 M_CLK_DDR#3 (14)
H_D#9 H3 M13 H_A#13 AK34
H_D#10 H_D#_9 H_A#_13 H_A#14 RSVD11 DDR_CKE0_DIMMA
M9 E17 AN35 BC28 DDR_CKE0_DIMMA (13)

2
H_D#11 H_D#_10 H_A#_14 H_A#15 SMRCOMP_VOH RSVD12 SA_CKE_0 DDR_CKE1_DIMMA
M11 H_D#_11 H_A#_15 P17 AM35 RSVD13 SA_CKE_1 AY28 DDR_CKE1_DIMMA (13)
D H_D#12 H_A#16 DDR_CKE2_DIMMB D
J1 H_D#_12 H_A#_16 F17 T24 RSVD14 SB_CKE_0 AY36 DDR_CKE2_DIMMB (14)

1
H_D#13 J2 G20 H_A#17 BB36 DDR_CKE3_DIMMB
H_D#_13 H_A#_17 SB_CKE_1 DDR_CKE3_DIMMB (14)

RSVD
H_D#14 N12 B19 H_A#18 R32 B31
H_D#15 H_D#_14 H_A#_18 H_A#19 3.01K_0402_1% RSVD15 DDR_CS0_DIMMA#
J6 H_D#_15 H_A#_19 J16 B2 RSVD16 SA_CS#_0 BA17 DDR_CS0_DIMMA# (13)
H_D#16 P2 E20 H_A#20 M1 AY16 DDR_CS1_DIMMA#
H_D#_16 H_A#_20 RSVD17 SA_CS#_1 DDR_CS1_DIMMA# (13)
H_D#17 L2 H16 H_A#21 NA lead free AV16 DDR_CS2_DIMMB#
DDR_CS2_DIMMB# (14)

2
H_D#18 H_D#_17 H_A#_21 H_A#22 SMRCOMP_VOL SB_CS#_0 DDR_CS3_DIMMB#
R2 H_D#_18 H_A#_22 J20 SB_CS#_1 AR13 DDR_CS3_DIMMB# (14)
H_D#19 N9 L17 H_A#23 AY21
H_D#_19 H_A#_23 RSVD20

1
0.01U_0402_25V7K
H_D#20 H_A#24 M_ODT0

2.2U_0603_6.3V4Z
L6 H_D#_20 H_A#_24 A17 SA_ODT_0 BD17 M_ODT0 (13)
H_D#21 M5 B17 H_A#25 1 1 R33 AY17 M_ODT1 M_ODT1 (13)
H_D#22 H_D#_21 H_A#_25 H_A#26 1K_0402_1% SA_ODT_1 M_ODT2 +1.8V
J3 H_D#_22 H_A#_26 L16 SB_ODT_0 BF15 M_ODT2 (14)

C53

C54
H_D#23 N2 C21 H_A#27 <BOM Structure> BG23 AY13 M_ODT3 M_ODT3 (14)
H_D#24 H_D#_23 H_A#_27 H_A#28 RSVD22 SB_ODT_1
R1 J17 BF23

2
H_D#25 H_D#_24 H_A#_28 H_A#29 2 2 RSVD23 SMRCOMP R34
N5 H_D#_25 H_A#_29 H20 BH18 RSVD24 SM_RCOMP BG22 1 2 80.6_0402_1%
H_D#26 N6 B18 H_A#30 BF18 BH21 SMRCOMP# R35 1 2 80.6_0402_1%
H_D#27 H_D#_26 H_A#_30 H_A#31 RSVD25 SM_RCOMP#
P13 H_D#_27 H_A#_31 K17
H_D#28 N8 B20 H_A#32 BF28 SMRCOMP_VOH
H_D#29 H_D#_28 H_A#_32 H_A#33 SM_RCOMP_VOH SMRCOMP_VOL
L7 H_D#_29 H_A#_33 F21 SM_RCOMP_VOL BH28
H_D#30 N10 K21 H_A#34
H_D#31 H_D#_30 H_A#_34 H_A#35 +V_DDR2_MCH_REF
M3 H_D#_31 H_A#_35 L20 SM_VREF AV42
H_D#32 Y3 +3VS AR36 DDR2_SM_PWROK R975 1 2 10K_0402_1%
H_D#33 H_D#_32 H_ADS# R38 SM_PWROK SM_REXT R37
AD14 H_D#_33 H_ADS# H12 H_ADS# (4) SM_REXT BF17 1 2 499_0402_1%
H_D#34 Y6 B16 H_ADSTB#0 PM_EXTTS#0 1 2 BC36
H_D#_34 H_ADSTB#_0 H_ADSTB#0 (4) SM_DRAMRST#
H_D#35 Y10 G17 H_ADSTB#1
H_D#_35 H_ADSTB#_1 H_ADSTB#1 (4)
H_D#36 Y12 A9 H_BNR# 10K_0402_5% B38 CLK_MCH_DREFCLK
H_D#_36 H_BNR# H_BNR# (4) DPLL_REF_CLK CLK_MCH_DREFCLK (15)
H_D#37 Y14 F11 H_BPRI# A38 CLK_MCH_DREFCLK#
H_D#_37 H_BPRI# H_BPRI# (4) DPLL_REF_CLK# CLK_MCH_DREFCLK# (15)
H_D#38 Y7 G12 H_BR0# R39 E41 MCH_SSCDREFCLK
HOST
H_D#_38 H_BREQ# H_BR0# (4) DPLL_REF_SSCLK MCH_SSCDREFCLK (15)
H_D#39 W2 E9 H_DEFER# PM_EXTTS#1 1 2 F41 MCH_SSCDREFCLK#
H_D#_39 H_DEFER# H_DEFER# (4) DPLL_REF_SSCLK# MCH_SSCDREFCLK# (15)
H_D#40 AA8 B10 H_DBSY#
H_D#_40 H_DBSY# H_DBSY# (4)
H_D#41 CLK_MCH_BCLK 10K_0402_5% CLK_MCH_3GPLL

CLK
Y9 H_D#_41 HPLL_CLK AH7 CLK_MCH_BCLK (15) PEG_CLK F43 CLK_MCH_3GPLL (15)
H_D#42 AA13 AH6 CLK_MCH_BCLK# E43 CLK_MCH_3GPLL#
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# (15) PEG_CLK# CLK_MCH_3GPLL# (15)
H_D#43 AA9 J11 H_DPWR# R40
C H_D#_43 H_DPWR# H_DPWR# (5) C
H_D#44 AA11 F9 H_DRDY# CLKREQ#_7 1 2
H_D#_44 H_DRDY# H_DRDY# (4)
H_D#45 AD11 H9 H_HIT#
H_D#_45 H_HIT# H_HIT# (4)
H_D#46 AD10 E12 H_HITM# 10K_0402_5% AE41 DMI_TXN0
H_D#_46 H_HITM# H_HITM# (4) DMI_RXN_0 DMI_TXN0 (20)
H_D#47 AD13 H11 H_LOCK# AE37 DMI_TXN1
H_D#_47 H_LOCK# H_LOCK# (4) DMI_RXN_1 DMI_TXN1 (20)
H_D#48 AE12 C9 H_TRDY# AE47 DMI_TXN2
H_D#_48 H_TRDY# H_TRDY# (4) DMI_RXN_2 DMI_TXN2 (20)
H_D#49 AE9 AH39 DMI_TXN3
H_D#_49 DMI_RXN_3 DMI_TXN3 (20)
H_D#50 AA2
H_D#51 H_D#_50 DMI_TXP0
AD8 H_D#_51 DMI_RXP_0 AE40 DMI_TXP0 (20)
H_D#52 AA3 MCH_CLKSEL0 T25 AE38 DMI_TXP1
H_D#_52 (15) MCH_CLKSEL0 CFG_0 DMI_RXP_1 DMI_TXP1 (20)
H_D#53 AD3 J8 H_DINV#0 MCH_CLKSEL1 R25 AE48 DMI_TXP2
H_D#_53 H_DINV#_0 H_DINV#0 (5) (15) MCH_CLKSEL1 CFG_1 DMI_RXP_2 DMI_TXP2 (20)
H_D#54 AD7 L3 H_DINV#1 MCH_CLKSEL2 P25 AH40 DMI_TXP3
H_D#_54 H_DINV#_1 H_DINV#1 (5) (15) MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_TXP3 (20)
H_D#55 AE14 Y13 H_DINV#2 P20
H_D#_55 H_DINV#_2 H_DINV#2 (5) CFG_3
H_D#56 AF3 Y1 H_DINV#3 P24 AE35 DMI_RXN0
H_D#_56 H_DINV#_3 H_DINV#3 (5) CFG_4 DMI_TXN_0 DMI_RXN0 (20)
H_D#57 AC1 CFG5 C25 AE43 DMI_RXN1
H_D#_57 T75 CFG_5 DMI_TXN_1 DMI_RXN1 (20)
H_D#58 AE3 L10 H_DSTBN#0 CFG6 N24 AE46 DMI_RXN2
H_D#_58 H_DSTBN#_0 H_DSTBN#0 (5) T76 CFG_6 DMI_TXN_2 DMI_RXN2 (20)
H_D#59 AC3 M7 H_DSTBN#1 CFG7 M24 AH42 DMI_RXN3
H_D#_59 H_DSTBN#_1 H_DSTBN#1 (5) T77 CFG_7 DMI_TXN_3 DMI_RXN3 (20)
H_D#60 AE11 AA5 H_DSTBN#2 E21
H_D#_60 H_DSTBN#_2 H_DSTBN#2 (5) CFG_8

DMI
CFG
H_D#61 AE8 AE6 H_DSTBN#3 CFG9 C23 AD35 DMI_RXP0
H_D#_61 H_DSTBN#_3 H_DSTBN#3 (5) T79 CFG_9 DMI_TXP_0 DMI_RXP0 (20)
H_D#62 AG2 CFG10 C24 AE44 DMI_RXP1
H_D#_62 T80 CFG_10 DMI_TXP_1 DMI_RXP1 (20)
H_D#63 AD6 L9 H_DSTBP#0 N21 AF46 DMI_RXP2
H_D#_63 H_DSTBP#_0 H_DSTBP#0 (5) CFG_11 DMI_TXP_2 DMI_RXP2 (20)
M8 H_DSTBP#1 CFG12 P21 AH43 DMI_RXP3
H_DSTBP#_1 H_DSTBP#1 (5) T82 CFG_12 DMI_TXP_3 DMI_RXP3 (20)
AA6 H_DSTBP#2 CFG13 T21
H_DSTBP#_2 H_DSTBP#2 (5) T83 CFG_13
H_SWNG C5 AE5 H_DSTBP#3 R20
H_SWING H_DSTBP#_3 H_DSTBP#3 (5) CFG_14
H_RCOMP E3 M20
H_RCOMP H_REQ#0 CFG16 CFG_15
H_REQ#_0 B15 H_REQ#0 (4) T86 L21 CFG_16
K13 H_REQ#1 H21
H_REQ#_1 H_REQ#1 (4) CFG_17
H_REQ#2 VGATE GMCH_PWROK

GRAPHICS VID
H_REQ#_2 F13 H_REQ#2 (4) P29 CFG_18 (20,40) VGATE 1 2
B13 H_REQ#3 CFG19 R28 R55 @ 0_0402_5%
H_REQ#_3 H_REQ#3 (4) T89 CFG_19
(4) H_RESET# H_RESET# C12 B14 H_REQ#4 CFG20 T28 B33 ICH_PWROK 1 2
H_CPURST# H_REQ#_4 H_REQ#4 (4) T90 CFG_20 GFX_VID_0 (20) ICH_PWROK
(5) H_CPUSLP# H_CPUSLP# E11 B32 R66 0_0402_5%
H_CPUSLP# H_RS#0 GFX_VID_1
H_RS#_0 B6 H_RS#0 (4) GFX_VID_2 G33
F12 H_RS#1 H_RS#1 (4) F33
B H_RS#_1 H_RS#2 PM_BMBUSY# GFX_VID_3 B
H_RS#_2 C8 H_RS#2 (4) (20) PM_BMBUSY# R29 PM_SYNC# GFX_VID_4 E33
H_VREF A11 H_DPRSTP# B7
H_AVREF (5,19,40) H_DPRSTP# PM_DPRSTP#
B11 PM_EXTTS#0 N33
H_DVREF (13) PM_EXTTS#0 PM_EXT_TS#_0
PM_EXTTS#1 P32
(14) PM_EXTTS#1 PM_EXT_TS#_1

PM
CANTIGA_1p0 GMCH_PWROK AT40 C34
PLT_RST# PLT_RST#_NB PWROK GFX_VR_EN +VCCP
(18,20,22,23,27) PLT_RST# 1 2 AT11 RSTIN#
(4,19) H_THERMTRIP# 1 2 R520 100_0402_5% THERMTRIP# T20
R41 0_0402_5% DPRSLPVR THERMTRIP#
(20,40) DPRSLPVR R32 DPRSLPVR CL_CLK0 (20)

1
Layout Note: CL_DATA0 (20)
AH37 CL_CLK0 R42
H_RCOMP / H_VREF / H_SWNG +1.8V CL_CLK

0.1U_0402_16V4Z
Layout Note: AH36 CL_DATA0 1K_0402_1%
CL_DATA ICH_PWROK
trace width and spacing is 10/20 V_DDR_MCH_REF 1 @ BG48 NC_1 CL_PWROK AN36 1 2 R51
C55 BF48 AJ35 CL_RST# 0_0402_5%
CL_RST# (20)

2
NC_2 CL_RST#
1

ME
trace width and BD48 AH34 CL_VREF
+VCCP R44 NC_3 CL_VREF
spacing is 20/20. BC48 NC_4

1
+VCCP 1K_0402_1% 2
BH47 NC_5 1
BG47 C56
NC_6 511_0402_1%
1K_0402_1%

221_0603_1%

BE47 N28 0.1U_0402_16V4Z

T36
2

NC_7 DDPC_CTRLCLK
1

+V_DDR2_MCH_REF BH46 M28 R43

NC_8 DDPC_CTRLDATA T37 2
R45 R46 BF46 G36 SDVO_SCLK (17)

2
NC_9 SDVO_CTRLCLK
1

NC
0.1U_0402_16V4Z

BG45 E36 SDVO_SDAT

NC_10 SDVO_CTRLDATA SDVO_SDAT (17)
1 R47 BH44 K36 CLKREQ#_7
NC_11 CLKREQ# CLKREQ#_7 (15)
C57 1K_0402_1% BH43 H36 MCH_ICH_SYNC#
MCH_ICH_SYNC# (20)
2

H_VREF H_RCOMP H_SWNG NC_12 ICH_SYNC#

BH6

MISC
NC_13
BH5
change logic
2

2 NC_14
24.9_0402_1%

0.1U_0402_16V4Z

<BOM Structure> BG4 B12 MCH_TSATN#

NC_15 TSATN#
1

1
100_0402_1%
0.1U_0402_16V4Z

1 1 BH3
define by EC NC_16
2K_0402_1%

R52 C58 R53 R54 C59 BF3 NC_17

BH2 NC_18
BG2 NC_19 HDA_BCLK B28 T99
2 2 +3VS BE2 B30 T100
2

NC_20 HDA_RST#
BG1 NC_21 HDA_SDI B29 T101
A A
BF1 NC_22 HDA_SDO C29 T102
1

+VCCP

HDA
normal:low BD1 NC_23 HDA_SYNC A28 T103
R63 over temp:high BC1
1K_0402_5% NC_24
within 100 mils from NB Near B3 pin F1 NC_25
1

A47 NC_26
R64
2

54.9_0402_1% MCH_TSATN_EC# (30) CANTIGA_1p0

R68 Security Classification Compal Secret Data Compal Electronics, Inc.
1

C
2

MCH_TSATN# 1 2 2 Q5 2007/09/29 2007/09/29 Title

B Issued Date Deciphered Date
MMBT3904_SOT23-3
330_0402_5% E
<BOM Structure>
SCHEMATICS,MB A4271
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 7 of 42
5 4 3 2 1
 5 4 3 2 1

D D

(13) DDR_A_D[0..63] (14) DDR_B_D[0..63]

U2D U2E
DDR_A_D0 AJ38 BD21 DDR_A_BS0 DDR_B_D0 AK47 BC16 DDR_B_BS0
SA_DQ_0 SA_BS_0 DDR_A_BS0 (13) SB_DQ_0 SB_BS_0 DDR_B_BS0 (14)
DDR_A_D1 AJ41 BG18 DDR_A_BS1 DDR_B_D1 AH46 BB17 DDR_B_BS1
SA_DQ_1 SA_BS_1 DDR_A_BS1 (13) SB_DQ_1 SB_BS_1 DDR_B_BS1 (14)
DDR_A_D2 AN38 AT25 DDR_A_BS2 DDR_B_D2 AP47 BB33 DDR_B_BS2
SA_DQ_2 SA_BS_2 DDR_A_BS2 (13) SB_DQ_2 SB_BS_2 DDR_B_BS2 (14)
DDR_A_D3 AM38 DDR_B_D3 AP46
DDR_A_D4 SA_DQ_3 DDR_A_RAS# DDR_B_D4 SB_DQ_3
AJ36 SA_DQ_4 SA_RAS# BB20 DDR_A_RAS# (13) AJ46 SB_DQ_4
DDR_A_D5 AJ40 BD20 DDR_A_CAS# DDR_B_D5 AJ48 AU17 DDR_B_RAS#
SA_DQ_5 SA_CAS# DDR_A_CAS# (13) SB_DQ_5 SB_RAS# DDR_B_RAS# (14)
DDR_A_D6 AM44 AY20 DDR_A_WE# DDR_A_WE# (13) DDR_B_D6 AM48 BG16 DDR_B_CAS#
SA_DQ_6 SA_WE# SB_DQ_6 SB_CAS# DDR_B_CAS# (14)
DDR_A_D7 AM42 DDR_B_D7 AP48 BF14 DDR_B_WE# DDR_B_WE# (14)
DDR_A_D8 SA_DQ_7 DDR_B_D8 SB_DQ_7 SB_WE#
AN43 SA_DQ_8 AU47 SB_DQ_8
DDR_A_D9 AN44 DDR_B_D9 AU46
SA_DQ_9 DDR_A_DM[0..7] (13) SB_DQ_9
DDR_A_D10 AU40 DDR_B_D10 BA48
DDR_A_D11 SA_DQ_10 DDR_A_DM0 DDR_B_D11 SB_DQ_10
AT38 SA_DQ_11 SA_DM_0 AM37 AY48 SB_DQ_11 DDR_B_DM[0..7] (14)
DDR_A_D12 AN41 AT41 DDR_A_DM1 DDR_B_D12 AT47 AM47 DDR_B_DM0
DDR_A_D13 SA_DQ_12 SA_DM_1 DDR_A_DM2 DDR_B_D13 SB_DQ_12 SB_DM_0 DDR_B_DM1
AN39 SA_DQ_13 SA_DM_2 AY41 AR47 SB_DQ_13 SB_DM_1 AY47
DDR_A_D14 AU44 AU39 DDR_A_DM3 DDR_B_D14 BA47 BD40 DDR_B_DM2
DDR_A_D15 SA_DQ_14 SA_DM_3 DDR_A_DM4 DDR_B_D15 SB_DQ_14 SB_DM_2 DDR_B_DM3
AU42 SA_DQ_15 SA_DM_4 BB12 BC47 SB_DQ_15 SB_DM_3 BF35
DDR_A_D16 AV39 AY6 DDR_A_DM5 DDR_B_D16 BC46 BG11 DDR_B_DM4
DDR_A_D17 SA_DQ_16 SA_DM_5 DDR_A_DM6 DDR_B_D17 SB_DQ_16 SB_DM_4 DDR_B_DM5
AY44 SA_DQ_17 SA_DM_6 AT7 BC44 SB_DQ_17 SB_DM_5 BA3

A
DDR_A_D18 BA40 AJ5 DDR_A_DM7 DDR_B_D18 BG43 AP1 DDR_B_DM6

B
DDR_A_D19 SA_DQ_18 SA_DM_7 DDR_B_D19 SB_DQ_18 SB_DM_6 DDR_B_DM7
BD43 SA_DQ_19 DDR_A_DQS[0..7] (13) BF43 SB_DQ_19 SB_DM_7 AK2
DDR_A_D20 AV41 AJ44 DDR_A_DQS0 DDR_B_D20 BE45
SA_DQ_20 SA_DQS_0 SB_DQ_20 DDR_B_DQS[0..7] (14)
DDR_A_D21 AY43 AT44 DDR_A_DQS1 DDR_B_D21 BC41 AL47 DDR_B_DQS0
DDR_A_D22 SA_DQ_21 SA_DQS_1 DDR_A_DQS2 DDR_B_D22 SB_DQ_21 SB_DQS_0 DDR_B_DQS1
BB41 SA_DQ_22 SA_DQS_2 BA43 BF40 SB_DQ_22 SB_DQS_1 AV48
DDR_A_D23 BC40 MEMORY BC37 DDR_A_DQS3 DDR_B_D23 BF41 DDR_B_DQS2

MEMORY
SA_DQ_23 SA_DQS_3 SB_DQ_23 SB_DQS_2 BG41
DDR_A_D24 AY37 AW12 DDR_A_DQS4 DDR_B_D24 BG38 BG37 DDR_B_DQS3
DDR_A_D25 SA_DQ_24 SA_DQS_4 DDR_A_DQS5 DDR_B_D25 SB_DQ_24 SB_DQS_3 DDR_B_DQS4
BD38 SA_DQ_25 SA_DQS_5 BC8 BF38 SB_DQ_25 SB_DQS_4 BH9
DDR_A_D26 AV37 AU8 DDR_A_DQS6 DDR_B_D26 BH35 BB2 DDR_B_DQS5
DDR_A_D27 SA_DQ_26 SA_DQS_6 DDR_A_DQS7 DDR_B_D27 SB_DQ_26 SB_DQS_5 DDR_B_DQS6
AT36 SA_DQ_27 SA_DQS_7 AM7 DDR_A_DQS#[0..7] (13) BG35 SB_DQ_27 SB_DQS_6 AU1
DDR_A_D28 AY38 AJ43 DDR_A_DQS#0 DDR_B_D28 BH40 AN6 DDR_B_DQS7
C SA_DQ_28 SA_DQS#_0 SB_DQ_28 SB_DQS_7 DDR_B_DQS#[0..7] (14) C
DDR_A_D29 BB38 AT43 DDR_A_DQS#1 DDR_B_D29 BG39 AL46 DDR_B_DQS#0
DDR_A_D30 SA_DQ_29 SA_DQS#_1 DDR_A_DQS#2 DDR_B_D30 SB_DQ_29 SB_DQS#_0 DDR_B_DQS#1
AV36 SA_DQ_30 SA_DQS#_2 BA44 BG34 SB_DQ_30 SB_DQS#_1 AV47
DDR_A_D31 AW36 BD37 DDR_A_DQS#3 DDR_B_D31 BH34 BH41 DDR_B_DQS#2
DDR_A_D32 SA_DQ_31 SA_DQS#_3 DDR_A_DQS#4 DDR_B_D32 SB_DQ_31 SB_DQS#_2 DDR_B_DQS#3
BD13 SA_DQ_32 SA_DQS#_4 AY12 BH14 SB_DQ_32 SB_DQS#_3 BH37
DDR_A_D33 AU11 BD8 DDR_A_DQS#5 DDR_B_D33 BG12 BG9 DDR_B_DQS#4
DDR_A_D34 SA_DQ_33 SA_DQS#_5 DDR_A_DQS#6 DDR_B_D34 SB_DQ_33 SB_DQS#_4 DDR_B_DQS#5
BC11 SA_DQ_34 SA_DQS#_6 AU9 BH11 SB_DQ_34 SB_DQS#_5 BC2
DDR_A_D35 BA12 AM8 DDR_A_DQS#7 DDR_B_D35 BG8 AT2 DDR_B_DQS#6
SYSTEM

SA_DQ_35 SA_DQS#_7 DDR_A_MA[0..14] (13) SB_DQ_35 SB_DQS#_6

DDR_A_D36 DDR_B_D36 DDR_B_DQS#7

SYSTEM
AU13 SA_DQ_36 BH12 SB_DQ_36 SB_DQS#_7 AN5
DDR_A_D37 AV13 BA21 DDR_A_MA0 DDR_B_D37 BF11 DDR_B_MA[0..14] (14)
DDR_A_D38 SA_DQ_37 SA_MA_0 DDR_A_MA1 DDR_B_D38 SB_DQ_37 DDR_B_MA0
BD12 SA_DQ_38 SA_MA_1 BC24 BF8 SB_DQ_38 SB_MA_0 AV17
DDR_A_D39 BC12 BG24 DDR_A_MA2 DDR_B_D39 BG7 BA25 DDR_B_MA1
DDR_A_D40 SA_DQ_39 SA_MA_2 DDR_A_MA3 DDR_B_D40 SB_DQ_39 SB_MA_1 DDR_B_MA2
BB9 SA_DQ_40 SA_MA_3 BH24 BC5 SB_DQ_40 SB_MA_2 BC25
DDR_A_D41 BA9 BG25 DDR_A_MA4 DDR_B_D41 BC6 AU25 DDR_B_MA3
DDR_A_D42 SA_DQ_41 SA_MA_4 DDR_A_MA5 DDR_B_D42 SB_DQ_41 SB_MA_3 DDR_B_MA4
AU10 SA_DQ_42 SA_MA_5 BA24 AY3 SB_DQ_42 SB_MA_4 AW25
DDR_A_D43 AV9 BD24 DDR_A_MA6 DDR_B_D43 AY1 BB28 DDR_B_MA5
DDR_A_D44 SA_DQ_43 SA_MA_6 DDR_A_MA7 DDR_B_D44 SB_DQ_43 SB_MA_5 DDR_B_MA6
BA11 SA_DQ_44 SA_MA_7 BG27 BF6 SB_DQ_44 SB_MA_6 AU28
DDR_A_D45 BD9 BF25 DDR_A_MA8 DDR_B_D45 BF5 AW28 DDR_B_MA7
DDR_A_D46 SA_DQ_45 SA_MA_8 DDR_A_MA9 DDR_B_D46 SB_DQ_45 SB_MA_7 DDR_B_MA8
AY8 SA_DQ_46 SA_MA_9 AW24 BA1 SB_DQ_46 SB_MA_8 AT33
DDR_A_D47 BA6 BC21 DDR_A_MA10 DDR_B_D47 BD3 BD33 DDR_B_MA9
DDR_A_D48 SA_DQ_47 SA_MA_10 DDR_A_MA11 DDR_B_D48 SB_DQ_47 SB_MA_9 DDR_B_MA10
DDR

AV5 SA_DQ_48 SA_MA_11 BG26 AV2 SB_DQ_48 SB_MA_10 BB16

DDR_A_D49 DDR_A_MA12 DDR_B_D49 DDR_B_MA11

DDR
AV7 SA_DQ_49 SA_MA_12 BH26 AU3 SB_DQ_49 SB_MA_11 AW33
DDR_A_D50 AT9 BH17 DDR_A_MA13 DDR_B_D50 AR3 AY33 DDR_B_MA12
DDR_A_D51 SA_DQ_50 SA_MA_13 DDR_A_MA14 DDR_B_D51 SB_DQ_50 SB_MA_12 DDR_B_MA13
AN8 SA_DQ_51 SA_MA_14 AY25 AN2 SB_DQ_51 SB_MA_13 BH15
DDR_A_D52 AU5 DDR_B_D52 AY2 AU33 DDR_B_MA14
DDR_A_D53 SA_DQ_52 DDR_B_D53 SB_DQ_52 SB_MA_14
AU6 SA_DQ_53 AV1 SB_DQ_53
DDR_A_D54 AT5 DDR_B_D54 AP3
DDR_A_D55 SA_DQ_54 DDR_B_D55 SB_DQ_54
AN10 SA_DQ_55 AR1 SB_DQ_55
DDR_A_D56 AM11 DDR_B_D56 AL1
DDR_A_D57 SA_DQ_56 DDR_B_D57 SB_DQ_56
AM5 SA_DQ_57 AL2 SB_DQ_57
DDR_A_D58 AJ9 DDR_B_D58 AJ1
DDR_A_D59 SA_DQ_58 DDR_B_D59 SB_DQ_58
AJ8 SA_DQ_59 AH1 SB_DQ_59
DDR_A_D60 AN12 DDR_B_D60 AM2
B DDR_A_D61 SA_DQ_60 DDR_B_D61 SB_DQ_60 B
AM13 SA_DQ_61 AM3 SB_DQ_61
DDR_A_D62 AJ11 DDR_B_D62 AH3
DDR_A_D63 SA_DQ_62 DDR_B_D63 SB_DQ_62
AJ12 SA_DQ_63 AJ3 SB_DQ_63
CANTIGA_1p0 CANTIGA_1p0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 8 of 42
5 4 3 2 1
 5 4 3 2 1

+3VS DPST_PWM U2C

(17) DPST_PWM

R227
100K_0402_5% PEGCOMP trace width Strap Pin Table
R56 +VCC_PEG and spacing is 20/25 mils.
2 1 L32 L_BKLT_CTRL 000 = FSB 1066MHz

2
(30) ENABLT ENABLT G32 T37 1 2 CFG[2:0] FSB Freq select
R570 R571 R57 L_BKLT_EN PEG_COMPI 010 = FSB 800MHz
+3VS 1 2 10K_0402_5% M32 L_CTRL_CLK PEG_COMPO T36 49.9_0402_1%
2.2K_0402_5% 2.2K_0402_5%
R58 1 2 10K_0402_5% M33
011 = FSB 667MHz
DDC2_CLK L_CTRL_DATA
(17) DDC2_CLK K33 H44 Others = Reserved
1

1 L_DDC_CLK PEG_RX#_0
DDC2_CLK DDC2_DATA J33 J46
(17) DDC2_DATA L_DDC_DATA PEG_RX#_1
DDC2_DATA L44
PEG_RX#_2
PEG_RX#_3 L40 CFG[4:3] Reserved
(17) ENAVDD ENAVDD M29 N41
R59 1 L_VDD_EN PEG_RX#_4
2 2.37K_0402_1% C44 LVDS_IBG PEG_RX#_5 P48 0 = DMI x 2
D <BOM Structure> D
For Crestline:2.4kohm B43 LVDS_VBG PEG_RX#_6 N44 CFG5 (DMI select) 1 = DMI x 4
For Calero: 1.5Kohm
For Cantiga: 2.37Kohm
E37
E38
LVDS_VREFH
LVDS_VREFL
PEG_RX#_7
PEG_RX#_8
T43
U43
*
0 = The iTPM Host Interface is enable

LVDS
(17) LVDS_A_C- LVDS_A_C- C41 Y43 CFG6
LVDS_A_C+ LVDSA_CLK# PEG_RX#_9
C40 Y48 1 = The iTPM Host Interface is disable
(17) LVDS_A_C+
B37
A37
LVDSA_CLK
LVDSB_CLK#
PEG_RX#_10
PEG_RX#_11 Y36
AA43 0 =(TLS)chiper suite with no confidentiality
*
LVDSB_CLK PEG_RX#_12
PEG_RX#_13 AD37 CFG7 (Intel Management
LVDS_A_0- H47 AC47 1 =(TLS)chiper suite with confidentiality
(17) LVDS_A_0-
(17) LVDS_A_1-
(17) LVDS_A_2-
LVDS_A_1-
LVDS_A_2-
E46
G40
LVDSA_DATA#_0
LVDSA_DATA#_1
PEG_RX#_14
PEG_RX#_15 AD39
Engine Crypto strap)
*
LVDSA_DATA#_2
A40 H43

GRAPHICS
LVDSA_DATA#_3 PEG_RX_0
PEG_RX_1 J44 CFG8 Reserved
(17) LVDS_A_0+ LVDS_A_0+ H48 L43 R147
LVDS_A_1+ LVDSA_DATA_0 PEG_RX_2 DVI_HPDT#
(17) LVDS_A_1+ D45 LVDSA_DATA_1 PEG_RX_3 L41 1 2 DVI_HPDT# (17)
(17) LVDS_A_2+ LVDS_A_2+ F40 N40 0_0402_5% CFG9 0 = Reverse Lane,15->0, 14->1
LVDSA_DATA_2 PEG_RX_4
B40 LVDSA_DATA_3 PEG_RX_5 P47
PEG_RX_6 N43 (PCIE Graphics Lane Reversal) 1 = Normal Operation,Lane Number in order
A41 T42
H38
G37
LVDSB_DATA#_0
LVDSB_DATA#_1
PEG_RX_7
PEG_RX_8 U42
Y42 0 = Enable
*
LVDSB_DATA#_2 PEG_RX_9
J37 LVDSB_DATA#_3 PEG_RX_10 W47 CFG10 (PCIE Lookback enable)
Y37 1 = Disable
B42
G38
LVDSB_DATA_0
PEG_RX_11
PEG_RX_12 AA42
AD36 CFG11 Reserved
*
LVDSB_DATA_1 PEG_RX_13
F37 LVDSB_DATA_2 PEG_RX_14 AC48

PCI-EXPRESS
K37 LVDSB_DATA_3 PEG_RX_15 AD40 CFG[13:12] (XOR/ALLZ) 00 = Reserved
01 = XOR Mode Enabled
J41 PCIE_MTX_GRX_N0 10 = All Z Mode Enabled
PEG_TX#_0 PCIE_MTX_GRX_N1
M46 11 = Normal Operation(Default)
R880 2
R881 2
1 75_0402_1%GMCH_TV_COMPS
1 75_0402_1%GMCH_TV_LUMA
F25
H25
TVA_DAC
PEG_TX#_1
PEG_TX#_2 M47
M40
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3 CFG[15:14] Reserved
*
C TVB_DAC PEG_TX#_3 C
R882 2 1 75_0402_1%GMCH_TV_CRMA K25 TVC_DAC PEG_TX#_4 M42

TV
PEG_TX#_5 R48
H24 TV_RTN PEG_TX#_6 N38 CFG16 (FSB Dynamic ODT) 0 = Disabled
PEG_TX#_7 T40
U37 1 = Enabled
R87 0_0402_5%
TV_DCONSEL_0 C31
PEG_TX#_8
PEG_TX#_9 U40
Y40
*
R88 0_0402_5%
TV_DCONSEL_1 TV_DCONSEL_0 PEG_TX#_10
E32 TV_DCONSEL_1 PEG_TX#_11 AA46 CFG[18:17] Reserved
PEG_TX#_12 AA37
(16) M_BLUE M_BLUE AA40
M_GREEN PEG_TX#_13
AD43 CFG19 (DMI Lane Reversal) 0 = Normal Operation
(16) M_GREEN
(16) M_RED M_RED
R552
PEG_TX#_14
PEG_TX#_15 AC46
(Lane number in Order)
*
1 2 E28 J42 PCIE_MTX_GRX_P0
R553 150_0402_1% CRT_BLUE PEG_TX_0 PCIE_MTX_GRX_P1
PEG_TX_1 L46 1 = Reverse Lane
1 2 G28 M48 PCIE_MTX_GRX_P2
R554 150_0402_1% CRT_GREEN PEG_TX_2 PCIE_MTX_GRX_P3
M39
1 2 J28 CRT_RED
PEG_TX_3
PEG_TX_4 M43 CFG20 (PCIE/SDVO concurrent) 0 = Only PCIE or SDVO is operational. *
150_0402_1%
G29 CRT_IRTN
VGA PEG_TX_5
PEG_TX_6
R47
N37 1 = PCIE/SDVO are operating simu.
PEG_TX_7 T39
3VDDCCL H32 U36
(16) 3VDDCCL CRT_DDC_CLK PEG_TX_8
3VDDCDA J32 U39
(16) 3VDDCDA CRT_DDC_DATA PEG_TX_9
(16) CRT_HSYNC CRT_HSYNC R75 1 2 HSYNC J29 Y39
30.1_0402_1% CRT_HSYNC PEG_TX_10
E29 CRT_TVO_IREF PEG_TX_11 Y46
(16) CRT_VSYNC CRT_VSYNC R76 1 2 VSYNC L29 AA36
30.1_0402_1% CRT_VSYNC PEG_TX_12
PEG_TX_13 AA39
AD42 0.1U_0402_16V7K
PEG_TX_14 0.1U_0402_16V7K
PEG_TX_15 AD46
0.1U_0402_16V7K
2

0.1U_0402_16V7K
R81 CANTIGA_1p0
B 1.02K_0402_1% PCIE_MTX_GRX_N0 C224 1 TMDS_B_DATA2# B
2 TMDS_B_DATA2# (17)
PCIE_MTX_GRX_N1 C212 1 2 TMDS_B_DATA1#
TMDS_B_DATA1# (17)
PCIE_MTX_GRX_N2 C247 1 2 TMDS_B_DATA0#
TMDS_B_DATA0# (17)
1

PCIE_MTX_GRX_N3 C240 1 2 TMDS_B_CLK#

TMDS_B_CLK# (17)

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_MTX_GRX_P0 C239 1 2 TMDS_B_DATA2
TMDS_B_DATA2 (17)
PCIE_MTX_GRX_P1 C241 1 2 TMDS_B_DATA1
TMDS_B_DATA1 (17)
PCIE_MTX_GRX_P2 C246 1 2 TMDS_B_DATA0
TMDS_B_DATA0 (17)
PCIE_MTX_GRX_P3 C234 1 2 TMDS_B_CLK
TMDS_B_CLK (17)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 9 of 42
5 4 3 2 1
 5 4 3 2 1

+3VS_DAC_BG +3VS
L47
1 2 +1.05VS_DPLLA
+VCCP +VCCP

0.022U_0402_16V7K
BLM18PG181SN1D_0603
+VCCP
4.7U_0805_10V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z
+V1.05VS_AXF
1 1 1 1 U2H 1 2 R99
C60

C61

C62
220U_D2_4VM_R15 L48 1 2

0.1U_0402_16V4Z

10U_0805_10V4Z

10U_0805_10V4Z

1U_0603_10V4Z
C655

852mA U13 1 0_1210_5% 0_0603_5%

VTT_1

4.7U_0805_10V4Z

C65

C66

<BOM Structure>
73mA T13 1 1 1
2 2 2 2 VTT_2 C63 +
B27 VCCA_CRT_DAC_1 VTT_3 U12 1 1 1

C67

C68

C69
A26 T12 C64 +
+3VS_DAC_CRT VCCA_CRT_DAC_2 VTT_4
VTT_5 U11
2.68mA T11 220U_D2_4VM_R15 2 2 2
VTT_6 2 2 2 2
A25 U10

CRT
+3VS_DAC_BG VCCA_DAC_BG VTT_7
B25 VSSA_DAC_BG VTT_8 T10
D U9 <BOM Structure> D
+3VS_DAC_CRT +3VS VTT_9
VTT_10 T9
L49 U8
64.8mA VTT_11
1 2 +1.05VS_DPLLA F47 VCCA_DPLLA VTT_12 T8
0.022U_0402_16V7K

0.47U_0603_10V7K

4.7U_0805_10V4Z

2.2U_0805_16V4Z
BLM18PG181SN1D_0603 U7

VTT
VTT_13 +1.8V_SM_CK
4.7U_0805_10V4Z

0.1U_0402_16V4Z

+1.05VS_DPLLB L48 64.8mA T7 1 1 1 +1.8V

VCCA_DPLLB VTT_14 +1.05VS_DPLLB +VCCP
C73

C74

1 1 1 VTT_15 U6

0.1U_0402_16V4Z
C70

C71

C72
AD1 24mA T6 1 2

PLL
+1.05VS_HPLL VCCA_HPLL VTT_16

10U_0805_10V4Z
C871

U5 1 2 L50
VTT_17 2 2 2

0.1U_0402_16V4Z
+1.05VS_MPLL AE1 139.2mA T5 L51 1 1 MBK1608121YZF_0603
VCCA_MPLL VTT_18

2
2 2 2

C78

C79

10U_0805_10V4Z

C77
V3 0_1210_5%
13.2mA VTT_19 @ R883
VTT_20 U3 1 1

C75
+1.8V_TXLVDS J48 VCCA_LVDS VTT_21 V2 1_0402_1%
2 2
1 U2

A LVDS
C80 VTT_22
J47 T2

1
VSSA_LVDS VTT_23 2 2

10U_0805_10V4Z
VTT_24 V1
@ R104 1000P_0402_50V7K 414uA U1 1
2 VTT_25

C76
+3VS 1 2
0_0603_5% AD48
+1.5VS_PEG_BG VCCA_PEG_BG
R105 2 <BOM Structure>
1 2

A PEG
+1.5VS +1.05VS_HPLL +VCCP +1.5VS_TVDAC +1.5VS
0_0603_5% 50mA
1 +1.05VS_PEGPLL AA48 L52 R107
VCCA_PEG_PLL
<BOM Structure>

C81 1 2 1 2

0.022U_0402_16V7K

0.1U_0402_16V4Z
MBK2012121YZF_0805 0_0805_5%
0.1U_0402_16V4Z DDR3:747.5mA AR20
2 VCCA_SM_1

0.1U_0402_16V4Z

10U_0805_10V4Z
AP20 VCCA_SM_2 1 1 1 1

C82

C83
AN20 VCCA_SM_3
POWER

C84

C85
AR17 VCCA_SM_4
AP17 VCCA_SM_5
+VCCP 2 2 2 2
+1.05VS_A_SM AN17 VCCA_SM_6
AT16 VCCA_SM_7
220U_D2_4VM_R15 R108 AR16

A SM
VCCA_SM_8
C
1 2 AP16 VCCA_SM_9 C
1 0_0805_5%
1 1 1
C86 + C800 C88 C89
+VCC_PEG +VCCP
J1
4.7U_0805_10V4Z DDR3:37.95mA JUMP_43X79
2 2 2 2 321.35mA +1.05VS_MPLL +VCCP @
22U_0805_6.3V6M <BOM Structure>
1U_0603_10V4Z AP28 L53 1
VCCA_SM_CK_1 1 2 2
AN28 VCCA_SM_CK_2 VCC_AXF_1 B22 +V1.05VS_AXF 1 2

10U_0805_10V4Z
AP25 B21 MBK2012121YZF_0805 220U_D2_4VM_R15 1

AXF
VCCA_SM_CK_3 VCC_AXF_2

1
R111 +1.05VS_A_SM_CK

4.7U_0805_10V4Z
AN25 VCCA_SM_CK_4 VCC_AXF_3 A21 1 1

C91
1 2 AN24 R884 C90 + C801
VCCA_SM_CK_5 1
1U_0603_10V4Z

0.1U_0402_16V4Z

0_0603_5% AM28 124mA C92 0.5_0603_1%

VCCA_SM_CK_NCTF_1
AM26
A CK
VCCA_SM_CK_NCTF_2 0.1U_0402_16V4Z 2 2 2
1 1 1 1 AM25

2
VCCA_SM_CK_NCTF_3 2
C96

C97

C94 C802 AL25 BF21 +1.8V_SM_CK 1

VCCA_SM_CK_NCTF_4 VCC_SM_CK_1
AM24 BH20

SM CK
1U_0603_10V4Z VCCA_SM_CK_NCTF_5 VCC_SM_CK_2 C803
AL24 VCCA_SM_CK_NCTF_6 VCC_SM_CK_3 BG20
2 2 2 2
AM23 VCCA_SM_CK_NCTF_7 VCC_SM_CK_4 BF20 22U_0805_6.3V6M
22U_0805_6.3V6M 2
AL23 VCCA_SM_CK_NCTF_8 DDR3:149.5mA
TVA 24.15mA
+1.05VS_PEGPLL +VCCP +1.05VS_DMI +VCC_PEG
TVB 39.48mA VCC_TX_LVDS K47 +1.8V_TXLVDS
B24 TVX 24.15mA L1 R112
VCCA_TV_DAC_1 +3VS_HV
+3VS_TVDAC A24 VCCA_TV_DAC_2 VCC_HV_1 C35 1 2 1 2
TV

105.3mA B35 BLM18PG121SN1D_0603 0_0603_5%

VCC_HV_2

0.1U_0402_16V4Z

10U_0805_10V4Z

0.1U_0402_16V4Z
A35
HV

R525 VCC_HV_3
1 1

0.1U_0402_16V4Z

C98

C99
+1.5VS 1 2 VCC_HDA A32 50mA 1
VCC_HDA

C100
HDA

0_0402_5% V48 +VCC_PEG 1

VCC_PEG_1
0.1U_0402_16V4Z

C101
1732mA U48
VCC_PEG_2 2 2
V47
PEG

VCC_PEG_3 2
0814 Add R,C 1 VCC_PEG_4 U47
2
C475

D TV/CRT

+1.5VS_TVDAC M25 58.67mA U46

VCCD_TVDAC VCC_PEG_5
B +1.5VS_QDAC L28 48.363mA B
2 VCCD_QDAC
VCC_DMI_1 AH48 +1.05VS_DMI
+1.05VS_HPLL AF1 157.2mA AF48
VCCD_HPLL VCC_DMI_2
AH47
DMI

50mA VCC_DMI_3
+1.05VS_PEGPLL AA47 VCCD_PEG_PLL VCC_DMI_4 AG47
+VCCP_D
456mA
M38 VCCD_LVDS_1
LVDS

+1.8V_LVDS L37 A8 D3 R113 R114

VCCD_LVDS_2 VTTLF1
VTTLF2 L1 +VCCP 2 1 1 2 1 2 +3VS_HV
VTTLF

60.31mA AB2 10_0402_5% 0_0402_5%

VTTLF3 CH751H-40PT_SOD323-2
0.47U_0603_10V7K

0.47U_0603_10V7K

0.47U_0603_10V7K

+3VS
1 1 1
C102

C103

C104

CANTIGA_1p0

2 2 2

+1.8V_LVDS +1.8V_TXLVDS
40 mils
R115 R116
1 2 +1.8V 1 2 +1.8V

10U_0805_10V4Z

1000P_0402_50V7K
0_0603_5% 0_0603_5%

10U_0805_10V4Z
+1.5VS_QDAC 1 1
+1.5VS

C105

C106

1U_0603_10V4Z

C108
+3VS_TVDAC 1 1
+3VS

C107
L54 R120
2 2
1 2 1 2
2 2
0.022U_0402_16V7K

0.022U_0402_16V7K

BLM18PG181SN1D_0603 100_0603_1%
A A
0.1U_0402_16V4Z

0.1U_0402_16V4Z
C110

C111

C112

C113

1 1 1 1

2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 10 of 42
5 4 3 2 1
 5 4 3 2 1

U2G +VCCP

AP33 VCC_SM_1 VCC_AXG_NCTF_1 W28

DDR3:4140mA AN33 V28
VCC_SM_2 VCC_AXG_NCTF_2 0.1U_0402_16V4Z 4.7U_0603_6.3V6M
+1.8V BH32 VCC_SM_3 VCC_AXG_NCTF_3 W26
U2F BG32 V26
+VCCP VCC_SM_4 VCC_AXG_NCTF_4

0.01U_0402_16V7K
BF32 VCC_SM_5 VCC_AXG_NCTF_5 W25 1 1 1

10U_0805_10V4Z

10U_0805_10V4Z
1 BD32 V25 C114 C115 C116
C117 VCC_SM_6 VCC_AXG_NCTF_6
1 1 2 BC32 VCC_SM_7 VCC_AXG_NCTF_7 W24

C118

C119

C120
D
AG34 + BB32 V24 D
VCC_1 VCC_SM_8 VCC_AXG_NCTF_8 2 2 2
AC34 VCC_2 BA32 VCC_SM_9 VCC_AXG_NCTF_9 W23
AB34 330U_D2E_2.5VM_R15 AY32 V23
VCC_3 2 2 2 1 VCC_SM_10 VCC_AXG_NCTF_10 0.22U_0402_10V4Z
AA34 VCC_4 AW32 VCC_SM_11 VCC_AXG_NCTF_11 AM21
Y34 VCC_5 AV32 VCC_SM_12 VCC_AXG_NCTF_12 AL21
V34 VCC_6 AU32 VCC_SM_13 VCC_AXG_NCTF_13 AK21
U34 VCC_7 AT32 VCC_SM_14 VCC_AXG_NCTF_14 W21
AM33 0317 change value AR32 V21
VCC_8 VCC_SM_15 VCC_AXG_NCTF_15

POWER
AK33 VCC_9 AP32 VCC_SM_16 VCC_AXG_NCTF_16 U21
AJ33 VCC_10 AN32 VCC_SM_17 VCC_AXG_NCTF_17 AM20
0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.1U_0402_16V4Z
AG33 VCC_11 BH31 VCC_SM_18 VCC_AXG_NCTF_18 AK20
10U_0805_10V4Z

220U_D2_4VM_R15 1 AF33 BG31 W20

VCC_12 VCC_SM_19 VCC_AXG_NCTF_19
1 1 1 1 BF31 VCC_SM_20 VCC_AXG_NCTF_20 U20
C122

C123

C124

C121 + C125
AE33 VCC_13 BG30 VCC_SM_21 VCC_AXG_NCTF_21 AM19

VCC CORE
AC33 VCC_14 BH29 VCC_SM_22 VCC_AXG_NCTF_22 AL19
AA33 VCC_15 BG29 VCC_SM_23 VCC_AXG_NCTF_23 AK19
2 2 2 2 2
Y33 VCC_16 BF29 VCC_SM_24 VCC_AXG_NCTF_24 AJ19
W33 VCC_17 BD29 VCC_SM_25 VCC_AXG_NCTF_25 AH19

VCC SM
V33 VCC_18 BC29 VCC_SM_26 VCC_AXG_NCTF_26 AG19
U33 VCC_19 BB29 VCC_SM_27 VCC_AXG_NCTF_27 AF19
AH28 VCC_20 BA29 VCC_SM_28 VCC_AXG_NCTF_28 AE19
AF28 VCC_21 AY29 VCC_SM_29 VCC_AXG_NCTF_29 AB19
AC28 VCC_22 AW29 VCC_SM_30 VCC_AXG_NCTF_30 AA19
AA28 VCC_23 AV29 VCC_SM_31 VCC_AXG_NCTF_31 Y19
AJ26 VCC_24 AU29 VCC_SM_32 VCC_AXG_NCTF_32 W19
AG26 VCC_25 AT29 VCC_SM_33 VCC_AXG_NCTF_33 V19
AE26 VCC_26 AR29 VCC_SM_34 VCC_AXG_NCTF_34 U19
AC26 VCC_27 AP29 VCC_SM_35 VCC_AXG_NCTF_35 AM17
AH25 VCC_28 VCC_AXG_NCTF_36 AK17
AG25 VCC_SM_BA36 BA36 AH17
VCC_29 VCC_SM_BB24 VCC_SM_36/NC VCC_AXG_NCTF_37
AF25 VCC_30 BB24 VCC_SM_37/NC VCC_AXG_NCTF_38 AG17
AG24 VCC_SM_BD16 BD16 AF17
C VCC_31 +VCCP VCC_SM_38/NC VCC_AXG_NCTF_39 C
AJ23 VCC_32 BB21 VCC_SM_39/NC VCC_AXG_NCTF_40 AE17
AH23 VCC_SM_AW16 AW16 AC17
VCC_33 POWER VCC_SM_40/NC VCC_AXG_NCTF_41
AF23 VCC_34 AW13 VCC_SM_41/NC VCC_AXG_NCTF_42 AB17
AM32 VCC_SM_AT13 AT13 Y17
VCC_NCTF_1 VCC_SM_42/NC VCC_AXG_NCTF_43
T32 VCC_35 VCC_NCTF_2 AL32 VCC_AXG_NCTF_44 W17
AK32 6326.84mA V17

VCC GFX NCTF

VCC_NCTF_3 VCC_AXG_NCTF_45
VCC_NCTF_4 AJ32 VCC_AXG_NCTF_46 AM16
VCC_NCTF_5 AH32 Y26 VCC_AXG_1 VCC_AXG_NCTF_47 AL16
VCC_NCTF_6 AG32 AE25 VCC_AXG_2 VCC_AXG_NCTF_48 AK16
VCC_NCTF_7 AE32 AB25 VCC_AXG_3 VCC_AXG_NCTF_49 AJ16
AC32 +VCCP AA25 AH16
VCC_NCTF_8 VCC_AXG_4 VCC_AXG_NCTF_50
VCC_NCTF_9 AA32 AE24 VCC_AXG_5 VCC_AXG_NCTF_51 AG16
Y32 10U_0805_10V4Z 0.1U_0402_16V4Z AC24 AF16
VCC_NCTF_10 VCC_AXG_6 VCC_AXG_NCTF_52
VCC_NCTF_11 W32 AA24 VCC_AXG_7 VCC_AXG_NCTF_53 AE16
VCC_NCTF_12 U32 1 Y24 VCC_AXG_8 VCC_AXG_NCTF_54 AC16
VCC_NCTF_13 AM30 1 1 1 1 AE23 VCC_AXG_9 VCC_AXG_NCTF_55 AB16
AL30 C126 + C128 C129 C130 AC23 AA16
VCC_NCTF_14 VCC_AXG_10 VCC_AXG_NCTF_56
VCC_NCTF_15 AK30 AB23 VCC_AXG_11 VCC_AXG_NCTF_57 Y16
AH30 1U_0603_10V4Z C127 AA23 W16
VCC_NCTF_16 2 2 2 2 2 VCC_AXG_12 VCC_AXG_NCTF_58
VCC_NCTF_17 AG30 AJ21 VCC_AXG_13 VCC_AXG_NCTF_59 V16
VCC_NCTF_18 AF30 AG21 VCC_AXG_14 VCC_AXG_NCTF_60 U16
AE30 10U_0805_10V4Z AE21
VCC_NCTF_19 330U_D2E_2.5VM_R15 VCC_AXG_15
VCC_NCTF_20 AC30 AC21 VCC_AXG_16
VCC_NCTF_21 AB30 AA21 VCC_AXG_17
VCC_NCTF_22 AA30 Y21 VCC_AXG_18
VCC_NCTF_23 Y30 AH20 VCC_AXG_19
VCC_NCTF_24 W30 AF20 VCC_AXG_20
VCC NCTF

VCC_NCTF_25 V30 AE20 VCC_AXG_21

VCC_NCTF_26 U30 AC20 VCC_AXG_22
VCC_NCTF_27 AL29 AB20 VCC_AXG_23
VCC_NCTF_28 AK29 AA20 VCC_AXG_24
VCC_NCTF_29 AJ29 T17 VCC_AXG_25
B B
VCC_NCTF_30 AH29 T16 VCC_AXG_26
VCC_NCTF_31 AG29 AM15 VCC_AXG_27
VCC_NCTF_32 AE29 AL15 VCC_AXG_28
VCC_NCTF_33 AC29 AE15 VCC_AXG_29
VCC_NCTF_34 AA29 AJ15 VCC_AXG_30
VCC_NCTF_35 Y29 AH15 VCC_AXG_31
VCC_NCTF_36 W29 AG15 VCC_AXG_32
VCC_NCTF_37 V29 AF15 VCC_AXG_33
VCC_NCTF_38 AL28 AB15 VCC_AXG_34
VCC_NCTF_39 AK28 AA15 VCC_AXG_35

VCC GFX
VCC_NCTF_40 AL26 Y15 VCC_AXG_36
VCC_NCTF_41 AK26 V15 VCC_AXG_37
VCC_NCTF_42 AK25 U15 VCC_AXG_38
VCC_NCTF_43 AK24 AN14 VCC_AXG_39
VCC_NCTF_44 AK23 AM14 VCC_AXG_40
U14 VCC_AXG_41 VCC_SM_LF1 AV44 VCCSM_LF1

VCC SM LF
T14 VCC_AXG_42 VCC_SM_LF2 BA37 VCCSM_LF2
VCC_SM_LF3 AM40 VCCSM_LF3
VCC_SM_LF4 AV21 VCCSM_LF4
VCC_SM_LF5 AY5 VCCSM_LF5
VCC_SM_LF6 AM10 VCCSM_LF6
CANTIGA_1p0
VCC_SM_LF7 BB13 VCCSM_LF7

C131 0.1U_0402_16V4Z

C132 0.1U_0402_16V4Z

C133

C134

C135

C136

C137
1 1 1 1 1 1 1
VCC_SM_BA36
VCC_SM_BB24 PAD T42 AJ14
VCC_SM_BD16 VCC_AXG_SENSE
PAD T43 AH14 VSS_AXG_SENSE 2 2 2 2 2 2 2

0.22U_0603_10V7K

0.22U_0603_10V7K

0.47U_0402_6.3V6K

1U_0603_10V4Z

1U_0603_10V4Z
VCC_SM_AW16
VCC_SM_AT13

1 1 1 1 1
C875 C876 C877 C878 C879
@ @ @ @ @
A 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K A
2 2 2 2 2
0.1U_0402_16V7K 0.1U_0402_16V7K CANTIGA_1p0

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 11 of 42
5 4 3 2 1
 5 4 3 2 1

U2J
U2I BG21 AH8
VSS_199 VSS_297
L12 VSS_200 VSS_298 Y8
AU48 VSS_1 VSS_100 AM36 AW21 VSS_201 VSS_299 L8
AR48 VSS_2 VSS_101 AE36 AU21 VSS_202 VSS_300 E8
AL48 VSS_3 VSS_102 P36 AP21 VSS_203 VSS_301 B8
BB47 VSS_4 VSS_103 L36 AN21 VSS_204 VSS_302 AY7
AW47 VSS_5 VSS_104 J36 AH21 VSS_205 VSS_303 AU7
AN47 VSS_6 VSS_105 F36 AF21 VSS_206 VSS_304 AN7
AJ47 VSS_7 VSS_106 B36 AB21 VSS_207 VSS_305 AJ7
AF47 VSS_8 VSS_107 AH35 R21 VSS_208 VSS_306 AE7
D D
AD47 VSS_9 VSS_108 AA35 M21 VSS_209 VSS_307 AA7
AB47 VSS_10 VSS_109 Y35 J21 VSS_210 VSS_308 N7
Y47 VSS_11 VSS_110 U35 G21 VSS_211 VSS_309 J7
T47 VSS_12 VSS_111 T35 BC20 VSS_212 VSS_310 BG6
N47 VSS_13 VSS_112 BF34 BA20 VSS_213 VSS_311 BD6
L47 VSS_14 VSS_113 AM34 AW20 VSS_214 VSS_312 AV6
G47 VSS_15 VSS_114 AJ34 AT20 VSS_215 VSS_313 AT6
BD46 VSS_16 VSS_115 AF34 AJ20 VSS_216 VSS_314 AM6
BA46 VSS_17 VSS_116 AE34 AG20 VSS_217 VSS_315 M6
AY46 VSS_18 VSS_117 W34 Y20 VSS_218 VSS_316 C6
AV46 VSS_19 VSS_118 B34 N20 VSS_219 VSS_317 BA5
AR46 VSS_20 VSS_119 A34 K20 VSS_220 VSS_318 AH5
AM46 VSS_21 VSS_120 BG33 F20 VSS_221 VSS_319 AD5
V46 VSS_22 VSS_121 BC33 C20 VSS_222 VSS_320 Y5
R46 VSS_23 VSS_122 BA33 A20 VSS_223 VSS_321 L5
P46 VSS_24 VSS_123 AV33 BG19 VSS_224 VSS_322 J5
H46 VSS_25 VSS_124 AR33 A18 VSS_225 VSS_323 H5
F46 VSS_26 VSS_125 AL33 BG17 VSS_226 VSS_324 F5
BF44 VSS_27 VSS_126 AH33 BC17 VSS_227 VSS_325 BE4
AH44 VSS_28 VSS_127 AB33 AW17 VSS_228
AD44 P33 AT17 BC3
AA44
Y44
VSS_29
VSS_30
VSS_31
VSS_128
VSS_129
VSS_130
L33
H33
R17
M17
VSS_229
VSS_230
VSS_231
VSS VSS_327
VSS_328
VSS_329
AV3
AL3
U44 VSS_32 VSS_131 N32 H17 VSS_232 VSS_330 R3
T44 K32 C17 P3
M44
F44
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
F32
C32 BA16
VSS_233

VSS_235
VSS_331
VSS_332
VSS_333
F3
BA2
BC43 VSS_36 VSS_135 A31 VSS_334 AW2
AV43 VSS_37 VSS_136 AN29 AU16 VSS_237 VSS_335 AU2
AU43 VSS_38 VSS_137 T29 AN16 VSS_238 VSS_336 AR2
AM43 VSS_39 VSS_138 N29 N16 VSS_239 VSS_337 AP2
J43 VSS_40 VSS_139 K29 K16 VSS_240 VSS_338 AJ2
C C
C43 VSS_41 VSS_140 H29 G16 VSS_241 VSS_339 AH2
BG42 VSS_42 VSS_141 F29 E16 VSS_242 VSS_340 AF2
AY42 VSS_43 VSS_142 A29 BG15 VSS_243 VSS_341 AE2
AT42 VSS_44 VSS_143 BG28 AC15 VSS_244 VSS_342 AD2
AN42 VSS_45 VSS_144 BD28 W15 VSS_245 VSS_343 AC2
AJ42 VSS_46 VSS_145 BA28 A15 VSS_246 VSS_344 Y2
AE42 VSS_47 VSS_146 AV28 BG14 VSS_247 VSS_345 M2
N42 VSS_48 VSS_147 AT28 AA14 VSS_248 VSS_346 K2
L42 VSS_49 VSS_148 AR28 C14 VSS_249 VSS_347 AM1
BD41 VSS_50 VSS_149 AJ28 BG13 VSS_250 VSS_348 AA1
AU41 VSS_51 VSS_150 AG28 BC13 VSS_251 VSS_349 P1
AM41 VSS_52 VSS_151 AE28 BA13 VSS_252 VSS_350 H1
AH41 VSS_53 VSS_152 AB28
AD41 VSS_54 VSS_153 Y28 VSS_351 U24
AA41 VSS_55 VSS_154 P28 AN13 VSS_255 VSS_352 U28
Y41 VSS_56 VSS_155 K28 AJ13 VSS_256 VSS_353 U25
U41 VSS_57 VSS_156 H28 AE13 VSS_257 VSS_354 U29
T41 VSS_58 VSS_157 F28 N13 VSS_258
M41 VSS_59 VSS_158 C28 L13 VSS_259
G41 VSS_60 VSS_159 BF26 G13 VSS_260 VSS_NCTF_1 AF32
B41 VSS_61 VSS_160 AH26 E13 VSS_261 VSS_NCTF_2 AB32
BG40 VSS_62 VSS_161 AF26 BF12 VSS_262 VSS_NCTF_3 V32
BB40 VSS_63 VSS_162 AB26 AV12 VSS_263 VSS_NCTF_4 AJ30
AV40 VSS_64 VSS_163 AA26 AT12 VSS_264 VSS_NCTF_5 AM29
AN40 VSS_65 VSS_164 C26 AM12 VSS_265 VSS_NCTF_6 AF29
H40 B26 AA12 AB29

VSS NCTF
VSS_66 VSS_165 VSS_266 VSS_NCTF_7
E40 VSS_67 VSS_166 BH25 J12 VSS_267 VSS_NCTF_8 U26
AT39 VSS_68 VSS_167 BD25 A12 VSS_268 VSS_NCTF_9 U23
AM39 VSS_69 VSS_168 BB25 BD11 VSS_269 VSS_NCTF_10 AL20
AJ39 VSS_70 VSS_169 AV25 BB11 VSS_270 VSS_NCTF_11 V20
AE39 VSS_71 VSS_170 AR25 AY11 VSS_271 VSS_NCTF_12 AC19
N39 VSS_72 VSS_171 AJ25 AN11 VSS_272 VSS_NCTF_13 AL17
B B
L39 VSS_73 VSS_172 AC25 AH11 VSS_273 VSS_NCTF_14 AJ17
B39 VSS_74 VSS_173 Y25 VSS_NCTF_15 AA17
BH38 VSS_75 VSS_174 N25 Y11 VSS_275 VSS_NCTF_16 U17
BC38 VSS_76 VSS_175 L25 N11 VSS_276
BA38 VSS_77 VSS_176 J25 G11 VSS_277
AU38 G25 C11 BH48

VSS SCB
VSS_78 VSS_177 VSS_278 VSS_SCB_1
AH38 VSS_79 VSS_178 E25 BG10 VSS_279 VSS_SCB_2 BH1
AD38 VSS_80 VSS_179 BF24 AV10 VSS_280 VSS_SCB_3 A48
AA38 VSS_81 VSS_180 AD12 AT10 VSS_281 VSS_SCB_4 C1
Y38 VSS_82 VSS_181 AY24 AJ10 VSS_282 VSS_SCB_5 A3
U38 VSS_83 VSS_182 AT24 AE10 VSS_283
T38 VSS_84 VSS_183 AJ24 AA10 VSS_284 NC_26 E1
J38 VSS_85 VSS_184 AH24 M10 VSS_285 NC_27 D2
F38 VSS_86 VSS_185 AF24 BF9 VSS_286 NC_28 C3
C38 VSS_87 VSS_186 AB24 BC9 VSS_287 NC_29 B4
BF37 VSS_88 VSS_187 R24 AN9 VSS_288 NC_30 A5
BB37 VSS_89 VSS_188 L24 AM9 VSS_289 NC_31 A6
AW37 VSS_90 VSS_189 K24 AD9 VSS_290 NC_32 A43
AT37 VSS_91 VSS_190 J24 G9 VSS_291 NC_33 A44
AN37 G24 B9 B45

NC
VSS_92 VSS_191 VSS_292 NC_34
AJ37 VSS_93 VSS_192 F24 BH8 VSS_293 NC_35 C46
H37 VSS_94 VSS_193 E24 BB8 VSS_294 NC_36 D47
C37 VSS_95 VSS_194 BH23 AV8 VSS_295 NC_37 B47
BG36 VSS_96 VSS_195 AG23 AT8 VSS_296 NC_38 A46
BD36 VSS_97 VSS_196 Y23 NC_39 F48
AK15 VSS_98 VSS_197 B23 NC_40 E48
AU36 VSS_99 VSS_198 A23 NC_41 C48
VSS_199 AJ6 NC_42 B48

CANTIGA_1p0 CANTIGA_1p0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 12 of 42
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V +1.8V

+DIMM_VREF
JDIMM1 20mils

1
+DIMM_VREF 1 VREF VSS 2
3 4 DDR_A_D4 R976
VSS DQ4 (8) DDR_A_DQS#[0..7]
DDR_A_D0 5 6 DDR_A_D5 1
DDR_A_D1 DQ0 DQ5 C880 1K_0402_1%
7 DQ1 VSS 8
DDR_A_DM0
20mils (8) DDR_A_D[0..63]
9 10 To SODIMM

2
DDR_A_DQS#0 VSS DM0 0.1U_0402_16V4Z
11 DQS0# VSS 12 +DIMM_VREF (8) DDR_A_DM[0..7]
DDR_A_DQS0 DDR_A_D6 2
13 DQS0 DQ6 14

1
15 16 DDR_A_D7 (8) DDR_A_DQS[0..7]
D DDR_A_D2 VSS DQ7 R977 D
17 DQ2 VSS 18
DDR_A_D3 19 20 DDR_A_D12 (8) DDR_A_MA[0..14]
DQ3 DQ12 DDR_A_D13 1K_0402_1%
21 VSS DQ13 22
DDR_A_D8 23 24 3/3 EMI ADD

2
DDR_A_D9 DQ8 VSS DDR_A_DM1
25 DQ9 DM1 26
27 VSS VSS 28
DDR_A_DQS#1 29 30 M_CLK_DDR0 +3VS +1.8V +VCCP
DQS1# CK0 M_CLK_DDR0 (7)
DDR_A_DQS1 31 32 M_CLK_DDR#0 C944
DQS1 CK0# M_CLK_DDR#0 (7)
33 34 1 2 0.1U_0402_16V4Z
DDR_A_D10 VSS VSS DDR_A_D14 C945
35 DQ10 DQ14 36
DDR_A_D11 37 38 DDR_A_D15 1 1 1 2 0.1U_0402_16V4Z
DQ11 DQ15 C881 C882 +1.8V
39 VSS VSS 40

0.1U_0402_16V4Z +1.8V +3VS

2
2.2U_0603_6.3V6K 2 C946 0.1U_0402_16V4Z
41 VSS VSS 42 1
DDR_A_D16 43 44 DDR_A_D20 1 2
DDR_A_D17 DQ16 DQ20 DDR_A_D21 + C947
45 DQ17 DQ21 46
47 48 330U_D2E_2.5VM_R15 1 2 0.1U_0402_16V4Z
DDR_A_DQS#2 VSS VSS PM_EXTTS#0 C930
49 DQS2# NC 50 PM_EXTTS#0 (7)
DDR_A_DQS2 DDR_A_DM2 2 +1.8V +0.9VS
51 DQS2 DM2 52
53 54 C948
DDR_A_D18 VSS VSS DDR_A_D22 @ 0.1U_0402_16V4Z
55 DQ18 DQ22 56 1 2
DDR_A_D19 57 58 DDR_A_D23
DQ19 DQ23
59 VSS VSS 60
DDR_A_D24 61 62 DDR_A_D28
DDR_A_D25 DQ24 DQ28 DDR_A_D29
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 72 +1.8V
DDR_A_D26 VSS VSS DDR_A_D30
73 DQ26 DQ30 74
DDR_A_D27 75 76 DDR_A_D31
C DQ27 DQ31 +0.9VS C
77 VSS VSS 78
DDR_CKE0_DIMMA 79 80 DDR_CKE1_DIMMA 1 1 1 1 1
(7) DDR_CKE0_DIMMA CKE0 NC/CKE1 DDR_CKE1_DIMMA (7)
81 82 DDR_CKE0_DIMMA 1 4 C883 C884 C885 C886 C887
VDD VDD DDR_A_BS2
83 NC NC/A15 84 2 3
DDR_A_BS2 85 86 DDR_A_MA14 RP36 56_0404_4P2R_5% 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K
(8) DDR_A_BS2 BA2 NC/A14 2 2 2 2 2
87 VDD VDD 88
DDR_A_MA12 89 90 DDR_A_MA11 DDR_A_MA12 1 4 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K
DDR_A_MA9 A12 A11 DDR_A_MA7 DDR_A_MA9
91 A9 A7 92 2 3
DDR_A_MA8 93 94 DDR_A_MA6 RP37 56_0404_4P2R_5%
A8 A6
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4 DDR_A_MA8 1 4
DDR_A_MA3 A5 A4 DDR_A_MA2 DDR_A_MA5 +1.8V
99 A3 A2 100 2 3
DDR_A_MA1 101 102 DDR_A_MA0 RP38 56_0404_4P2R_5%
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS1 DDR_A_MA3 1 4
A10/AP BA1 DDR_A_BS1 (8)
DDR_A_BS0 107 108 DDR_A_RAS# DDR_A_MA1 2 3 1 1 1 1
(8) DDR_A_BS0 BA0 RAS# DDR_A_RAS# (8)
DDR_A_WE# 109 110 DDR_CS0_DIMMA# RP39 56_0404_4P2R_5% C888 C889 C890 C891
(8) DDR_A_WE# WE# S0# DDR_CS0_DIMMA# (7)
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0 DDR_A_MA10 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z
(8) DDR_A_CAS# CAS# ODT0 M_ODT0 (7) 2 2 2 2
DDR_CS1_DIMMA# 115 116 DDR_A_MA13 DDR_A_BS0 2 3
(7) DDR_CS1_DIMMA# NC/S1# NC/A13 RP40 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
117 VDD VDD 118
M_ODT1 119 120
(7) M_ODT1 NC/ODT1 NC
121 122 DDR_A_WE# 1 4
DDR_A_D32 VSS VSS DDR_A_D36 DDR_A_CAS#
123 DQ32 DQ36 124 2 3
DDR_A_D33 125 126 DDR_A_D37 RP41 56_0404_4P2R_5%
DQ33 DQ37
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4 DDR_CS1_DIMMA# 1 4
DDR_A_DQS4 DQS4# DM4 M_ODT1 +0.9VS
131 DQS4 VSS 132 2 3
133 134 DDR_A_D38 RP42 56_0404_4P2R_5%
DDR_A_D34 VSS DQ38 DDR_A_D39
135 DQ34 DQ39 136
DDR_A_D35 137 138
DQ35 VSS DDR_A_D44
139 VSS DQ44 140 1 1 1 1 1
B DDR_A_D40 DDR_A_D45 DDR_A_MA11 C892 C893 C894 C895 C896 B
141 DQ40 DQ45 142 1 4
DDR_A_D41 143 144 DDR_A_MA14 2 3
DQ41 VSS DDR_A_DQS#5 RP43 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
145 VSS DQS5# 146
DDR_A_DM5 DDR_A_DQS5 2 2 2 2 2
147 DM5 DQS5 148
149 150 DDR_A_MA6 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDR_A_D42 VSS VSS DDR_A_D46 DDR_A_MA7
151 DQ42 DQ46 152 2 3
DDR_A_D43 153 154 DDR_A_D47 RP44 56_0404_4P2R_5%
DQ43 DQ47
155 VSS VSS 156
DDR_A_D48 157 158 DDR_A_D52 DDR_A_MA2 1 4 +0.9VS
DDR_A_D49 DQ48 DQ52 DDR_A_D53 DDR_A_MA4
159 DQ49 DQ53 160 2 3
161 162 RP45 56_0404_4P2R_5%
VSS VSS M_CLK_DDR1
163 NC,TEST CK1 164 M_CLK_DDR1 (7)
165 166 M_CLK_DDR#1 DDR_A_BS1 1 4 1 1 1 1 1
VSS CK1# M_CLK_DDR#1 (7)
DDR_A_DQS#6 167 168 DDR_A_MA0 2 3 C897 C898 C899 C900 C901
DDR_A_DQS6 DQS6# VSS DDR_A_DM6 RP46 56_0404_4P2R_5%
169 DQS6 DM6 170
171 172 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDR_A_D50 VSS VSS DDR_A_D54 DDR_CS0_DIMMA# 1 2 2 2 2 2
173 DQ50 DQ54 174 4
DDR_A_D51 175 176 DDR_A_D55 DDR_A_RAS# 2 3 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DQ51 DQ55 RP47 56_0404_4P2R_5%
177 VSS VSS 178
DDR_A_D56 179 180 DDR_A_D60
DDR_A_D57 DQ56 DQ60 DDR_A_D61 DDR_A_MA13
181 DQ57 DQ61 182 1 4
183 184 M_ODT0 2 3 +0.9VS
DDR_A_DM7 VSS VSS DDR_A_DQS#7 RP48 56_0404_4P2R_5%
185 DM7 DQS7# 186
187 188 DDR_A_DQS7
DDR_A_D58 VSS DQS7 DDR_CKE1_DIMMA 1
189 DQ58 VSS 190 2
DDR_A_D59 191 192 DDR_A_D62 R978 56_0402_5% 1 1 1
DQ59 DQ62 DDR_A_D63 C902 C903 C904
193 VSS DQ63 194
CLK_SMBDATA 195 196
(14,15) CLK_SMBDATA SDA VSS
CLK_SMBCLK 197 198 R979 1 2 10K_0402_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
(14,15) CLK_SMBCLK SCL SAO 2 2 2
+3VS 199 200 R980 1 2 10K_0402_5%
VDDSPD SA1 0.1U_0402_16V4Z
203 GND GND 204
A FOX_AS0A426-N2RN-7F A
CONN@

DIMM0 REV H:5.2mm (BOT)

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 13 of 42
5 4 3 2 1
 5 4 3 2 1

(8) DDR_B_DQS#[0..7]

(8) DDR_B_D[0..63]

+1.8V +1.8V (8) DDR_B_DM[0..7]

(8) DDR_B_DQS[0..7]
JDIMM2
+DIMM_VREF 1 VREF VSS 2 (8) DDR_B_MA[0..14]
3 4 DDR_B_D4
DDR_B_D0 VSS DQ4 DDR_B_D1
5 DQ0 DQ5 6
DDR_B_D5 7 8
D DQ1 VSS DDR_B_DM0 D
9 VSS DM0 10
DDR_B_DQS#0 11 12
DDR_B_DQS0 DQS0# VSS DDR_B_D6
13 DQS0 DQ6 14
15 16 DDR_B_D7
DDR_B_D2 VSS DQ7
17 DQ2 VSS 18
DDR_B_D3 19 20 DDR_B_D12
DQ3 DQ12 DDR_B_D13
21 VSS DQ13 22
DDR_B_D8 23 24 +1.8V
DDR_B_D9 DQ8 VSS DDR_B_DM1 +DIMM_VREF
25 DQ9 DM1 26
27 VSS VSS 28
DDR_B_DQS#1 29 30 M_CLK_DDR2 1
DQS1# CK0 M_CLK_DDR2 (7)
DDR_B_DQS1 31 32 M_CLK_DDR#2
DQS1 CK0# M_CLK_DDR#2 (7) +
33 VSS VSS 34 1 1
DDR_B_D10 35 36 DDR_B_D14 C906 C907 330U_D2E_2.5VM_R15
DDR_B_D11 DQ10 DQ14 DDR_B_D15 C905
37 DQ11 DQ15 38
2.2U_0603_6.3V6K 2
39 VSS VSS 40
2 2
0.1U_0402_16V4Z

41 VSS VSS 42
DDR_B_D16 43 44 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
45 DQ17 DQ21 46
47 VSS VSS 48
DDR_B_DQS#2 49 50 PM_EXTTS#1
DQS2# NC PM_EXTTS#1 (7)
DDR_B_DQS2 51 52 DDR_B_DM2
DQS2 DM2
53 VSS VSS 54
DDR_B_D18 55 56 DDR_B_D22
DDR_B_D19 DQ18 DQ22 DDR_B_D23
57 DQ19 DQ23 58
59 VSS VSS 60
DDR_B_D24 61 62 DDR_B_D28
DDR_B_D25 DQ24 DQ28 DDR_B_D29
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
C DM3 DQS3# DDR_B_DQS3 C
69 NC DQS3 70
71 VSS VSS 72
DDR_B_D26 73 74 DDR_B_D30 +1.8V
DDR_B_D27 DQ26 DQ30 DDR_B_D31
75 DQ27 DQ31 76
77 VSS VSS 78
DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB
(7) DDR_CKE2_DIMMB CKE0 NC/CKE1 DDR_CKE3_DIMMB (7)
81 VDD VDD 82 1 1 1 1 1
83 84 C908 C909 C910 C911 C912
DDR_B_BS2 NC NC/A15 DDR_B_MA14
(8) DDR_B_BS2 85 BA2 NC/A14 86
87 88 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K
DDR_B_MA12 VDD VDD DDR_B_MA11 +0.9VS 2 2
2.2U_0603_6.3V6K 2 2
2.2U_0603_6.3V6K 2
89 A12 A11 90
DDR_B_MA9 91 92 DDR_B_MA7
DDR_B_MA8 A9 A7 DDR_B_MA6
93 A8 A6 94
95 96 DDR_CKE2_DIMMB 1 4
DDR_B_MA5 VDD VDD DDR_B_MA4 DDR_B_BS2
97 A5 A4 98 2 3
DDR_B_MA3 99 100 DDR_B_MA2 RP49 56_0404_4P2R_5% +1.8V
DDR_B_MA1 A3 A2 DDR_B_MA0
101 A1 A0 102
103 104 DDR_B_MA12 1 4
DDR_B_MA10 VDD VDD DDR_B_BS1 DDR_B_MA9
105 A10/AP BA1 106 DDR_B_BS1 (8) 2 3
DDR_B_BS0 107 108 DDR_B_RAS# RP50 56_0404_4P2R_5% 1 1 1 1
(8) DDR_B_BS0 BA0 RAS# DDR_B_RAS# (8)
DDR_B_WE# 109 110 DDR_CS2_DIMMB# C913 C914 C915 C916
(8) DDR_B_WE# WE# S0# DDR_CS2_DIMMB# (7)
111 112 DDR_B_MA8 1 4
DDR_B_CAS# VDD VDD M_ODT2 DDR_B_MA5 0.1U_0402_16V4Z 0.1U_0402_16V4Z
(8) DDR_B_CAS# 113 CAS# ODT0 114 M_ODT2 (7) 2 3
DDR_CS3_DIMMB# DDR_B_MA13 RP51 56_0404_4P2R_5% 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2
(7) DDR_CS3_DIMMB# 115 NC/S1# NC/A13 116
117 VDD VDD 118
M_ODT3 119 120 DDR_B_MA3 1 4
(7) M_ODT3 NC/ODT1 NC
121 122 DDR_B_MA1 2 3
DDR_B_D32 VSS VSS DDR_B_D36 RP52 56_0404_4P2R_5%
123 DQ32 DQ36 124
DDR_B_D33 125 126 DDR_B_D37
DQ33 DQ37 DDR_B_MA10
127 VSS VSS 128 1 4
DDR_B_DQS#4 129 130 DDR_B_DM4 DDR_B_BS0 2 3
DDR_B_DQS4 DQS4# DM4 RP53 56_0404_4P2R_5% +0.9VS
131 DQS4 VSS 132
B DDR_B_D38 B
133 VSS DQ38 134
DDR_B_D34 135 136 DDR_B_D39 DDR_B_WE# 1 4
DDR_B_D35 DQ34 DQ39 DDR_B_CAS#
137 DQ35 VSS 138 2 3
139 140 DDR_B_D44 RP54 56_0404_4P2R_5% 1 1 1 1 1
DDR_B_D40 VSS DQ44 DDR_B_D45 C917 C918 C919 C920 C921
141 DQ40 DQ45 142
DDR_B_D41 143 144 DDR_CS3_DIMMB# 1 4
DQ41 VSS DDR_B_DQS#5 M_ODT3 0.1U_0402_16V4Z 0.1U_0402_16V4Z
145 VSS DQS5# 146 2 3
DDR_B_DM5 DDR_B_DQS5 RP55 56_0404_4P2R_5% 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z
147 DM5 DQS5 148
149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
153 DQ43 DQ47 154
155 156 DDR_B_MA11 RP562 356_0404_4P2R_5%
DDR_B_D48 VSS VSS DDR_B_D52 DDR_B_MA14 +0.9VS
157 DQ48 DQ52 158 1 4
DDR_B_D49 159 160 DDR_B_D53
DQ49 DQ53
161 VSS VSS 162
163 164 DDR_B_MA6 RP572 356_0404_4P2R_5%
NC,TEST CK1 M_CLK_DDR3 (7)
165 166 DDR_B_MA7 1 4 1 1 1 1 1
VSS CK1# M_CLK_DDR#3 (7)
DDR_B_DQS#6 167 168 C922 C923 C924 C925 C926
DDR_B_DQS6 DQS6# VSS DDR_B_DM6
169 DQS6 DM6 170
171 172 DDR_B_MA2 RP582 356_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDR_B_D50 VSS VSS DDR_B_D54 DDR_B_MA4 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2
173 DQ50 DQ54 174 1 4
DDR_B_D51 175 176 DDR_B_D55
DQ51 DQ55
177 VSS VSS 178
DDR_B_D56 179 180 DDR_B_D60 DDR_B_BS1 RP592 356_0404_4P2R_5%
DDR_B_D57 DQ56 DQ60 DDR_B_D61 DDR_B_MA0 +0.9VS
181 DQ57 DQ61 182 1 4
183 VSS VSS 184
DDR_B_DM7 185 186 DDR_B_DQS#7
DM7 DQS7# DDR_CS2_DIMMB#RP602
187 VSS DQS7 188 DDR_B_DQS7 356_0404_4P2R_5%
DDR_B_D58 189 190 DDR_B_RAS# 1 4 1 1 1
DDR_B_D59 DQ58 VSS DDR_B_D62 C927 C928 C929
191 DQ59 DQ62 192
193 194 DDR_B_D63
VSS DQ63 RP612
(13,15) CLK_SMBDATA
CLK_SMBDATA 195 SDA VSS 196 DDR_B_MA13 356_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
A CLK_SMBCLK R981 1 2 2 2 A
(13,15) CLK_SMBCLK 197 SCL SAO 198 2 10K_0402_5% M_ODT2 1 4 0.1U_0402_16V4Z
+3VS 199 200 R982 1 2 10K_0402_5% +3VS
VDDSPD SA1
201 GND GND 202
DDR_CKE3_DIMMB 1 2
FOX_AS0A426-NARN-7F R983 56_0402_5%
CONN@

DIMM1 REV H:9.2mm (BOT) Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 14 of 42
5 4 3 2 1
 5 4 3 2 1

+3VS_CK505
Routing the trace at least 10mil R129
FSC FSB FSA CPU SRC PCI REF DOT_96 USB 1 2
+3VS
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz CLK_XTAL_OUT 0_0805_5% 1
C191
1
C192
1
C193
1
C194
1
C195
1
C196
1
C197
CLK_XTAL_IN
0 0 0 266 100 33.3 14.318 96.0 48.0 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 <BOM Structure> 2 <BOM Structure> 2 <BOM Structure> 2 <BOM Structure> 2 <BOM Structure> 2 <BOM Structure>
<BOM Structure>

0 0 1 133 100 33.3 14.318 96.0 48.0 14.31818MHZ_16P

Y1
+VCCP +1.05VS_CK505
0 1 0 200 100 33.3 14.318 96.0 48.0 2 1
Place close to U3
D R130 D
0 1 1 166 100 33.3 14.318 96.0 48.0 2 2
C205 C206 1 2 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
18P_0402_50V8J 18P_0402_50V8J 0_0805_5% 1 1 1 1 1 1 1
1 0 0 333 100 33.3 14.318 96.0 48.0 C198 C199 C200 C201 C202 C203 C204
1 1
<BOM Structure> <BOM Structure>
2 2 2
<BOM Structure> 2
<BOM Structure> 2 2 2
<BOM Structure>
1 0 1 100 100 33.3 14.318 96.0 48.0
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 0 400 100 33.3 14.318 96.0 48.0

CLK_PCIE_READER (27)
CLK_PCIE_READER# (27)
1 1 1 Reserved +3VS_CK505 +1.05VS_CK505

R131
CLK_MCH_3GPLL (7)
1 2 +VCCP CLK_MCH_3GPLL# (7) 3G_PLL
R155 1 2 475_0402_1% R_CLKREQ#_7
(7) CLKREQ#_7
@ 56_0402_5% R875 1 2 +3VS
(7) CLK_MCH_BCLK#
NB R_CLKREQ#_6 R154 1 2 10K_0402_5%
(7) CLK_MCH_BCLK MCARD_CLKREQ# (22)
475_0402_1%
(4) CLK_CPU_BCLK# CLK_PCIE_MCARD1 (22)
R132 CPU MiniCard
(4) CLK_CPU_BCLK CLK_PCIE_MCARD1# (22)
FSA 1 2 1 2 +3VS_CK505
MCH_CLKSEL0 (7)
2.2K_0402_5% R133
R134 1K_0402_5%

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
(5) CPU_BSEL0 1 2
<BOM Structure>
0_0402_5% <BOM Structure> U3
+1.05VS_CK505
1

+3VS_CK505

SRC_8/CPU_ITP
VDD_CPU

CPU_0#
VSS_CPU

CPU_1#
VDD_CPU_IO

VDD_SRC_IO

VDD_SRC
CPU_0

CPU_1

CLKREQ_7#

SRC_8#/CPU_ITP#

SRC_7
SRC_7#
VSS_SRC
CLKREQ_6#
SRC_6
SRC_6#
@
R137
1K_0402_5%
C C
2

R138 1 2 0_0402_5% R_CKPWRGD 1 54 H_STP_PCI#

(20) CK_PWRGD CKPWRGD/PD# PCI_STOP# H_STP_PCI# (20)
FSB 2 53 H_STP_CPU#
FS_B/TEST_MODE CPU_STOP# H_STP_CPU# (20)
3 VSS_REF VDD_SRC_IO 52
+VCCP CLK_XTAL_OUT 4 51
CLK_XTAL_IN XTAL_OUT SRC_10#
5 XTAL_IN SRC_10 50
6 VDD_REF CLKREQ_10# 49
2

@ R158 1 2 33_0402_1% FSC 7 48

R150 (20) CLK_14M_ICH REF_0/FS_C/TEST_ SRC_11
PAD T98 8 REF_1 SRC_11# 47
1K_0402_5% (13,14) CLK_SMBDATA CLK_SMBDATA 9 46
CLK_SMBCLK SDA CLKREQ_11#
(13,14) CLK_SMBCLK 10 SCL SRC_9# 45 CLK_PCIE_LAN# (23)
11 44 CLK_PCIE_LAN (23) GLAN
1

FSB NC SRC_9
1 2 MCH_CLKSEL1 (7) 0905 Connect PCI_CLK 12 VDD_PCI CLKREQ_9# 43
R157 13 42 10K_0402_5% 1 R876 2
R162 1K_0402_5% 2007/12/07 PCI2_TME 14
PCI_1
PCI_2
VSS_SRC
CLKREQ_4# 41 R877 1 2
+3VS
EXP_CLKREQ# (28)
(5) CPU_BSEL1 1 2 R142 1 2 33_0402_1% 27_SEL 15 PCI_3 SRC_4# 40 475_0402_1%
CLK_PCIE_CARD# (28)
0_0402_5% (30) CLK_PCI_EC R873 PCI_CLK4 16 PCI_4/SEL_LCDCL SRC_4 39 CLK_PCIE_CARD (28)
1

USB_1/CLKREQ_A#
PCI_CLK 1 2 ITP_EN 17 38

LCDCLK#/27M_SS
(18) PCI_CLK PCIF_5/ITP_EN VDD_SRC_IO

SRC_0#/DOT_96#
@ 33_0402_1% 18 37 R_CLKREQ#_C 1 2 475_0402_1%
VSS_PCI CLKREQ_3# CLKREQ#_C (20)

SRC_0/DOT_96
R165 R149

VDD_PLL3_IO
LCDCLK/27M
USB_0/FS_A
0_0402_5%

VDD_PLL3

VSS_PLL3

VSS_SRC
2

VDD_48

SRC_2#

SRC_3#
VDD_IO
VSS_48

VSS_IO

SRC_2

SRC_3
+VCCP
SA000020H10 SLG8SP553VTR_QFN72_10x10

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
+3VS_CK505
1

@
R177
1K_0402_5% CLK_PCIE_SATA# (19)
R151 1 2 33_0402_1% FSA SATA
(20) CLK_48M_ICH CLK_PCIE_SATA (19)
PAD T112
B R182 B
CLK_PCIE_ICH# (20)
2

FSC 1 2 1 2 +1.05VS_CK505 ICH

MCH_CLKSEL2 (7) CLK_PCIE_ICH (20)
10K_0402_5% R183 +1.05VS_CK505
R187 1K_0402_5%
(7) CLK_MCH_DREFCLK
(5) CPU_BSEL2 1 2 NB (UMA) (7) CLK_MCH_DREFCLK# MCH_SSCDREFCLK# (7)
0_0402_5% NB_SSC (UMA)
MCH_SSCDREFCLK (7)
1

@
R188
0_0402_5%
0 = SRC8/SRC8#
ITP_EN
2

1 = ITP/ITP#
0 = Enable DOT96 & SRC1(UMA)
PCI_CLK3 +3VS
+3VS 1 = Enable SRC0 & 27MHz(DIS) +3VS
1

+3VS
R208 0820 R192 @ +3VS R189 R190
10K_0402_5%
1

@ 2.2K_0402_5% 2.2K_0402_5%
R192
2

10K_0402_5%
PCI2_TME 5
2

ITP_EN (20,22,28) ICH_SMBDATA 3 4 CLK_SMBDATA

1

PCI_CLK4
2

R207 SB, MINI PCI Q3B

1

@ 10K_0402_5%
1

R193 6 1 2N7002DW T/R7_SOT363-6 CLK_SMBCLK

A 10K_0402_5% (20,22,28) ICH_SMBCLK A
R194
2

10K_0402_5% 2N7002DW T/R7_SOT363-6

Q3A
2

for ICS Overclocking setting

0=Overclocking of CPU and SRC allowed
1=Overclocking of CPU and SRC NOT allowed Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 15 of 42
5 4 3 2 1
 A B C D E

BLUE
GREEN
RED

Place close to JP6

1
@ D5
@D5 @ D6 @ D7

DAN217_SC59

DAN217_SC59

DAN217_SC59
+CRTVDD

3
1 1

NOTE: L : A-->B1 +5VS

CRT Connector
H: A-->B2
0.1U_0402_16V4Z +5VS +RCRT_VCC +CRTVDD
1 2
C656 D4 F1
U25 W=40mils
2 1 1 2
VCC 16 1
EC_DOCKIN# 1 CH491D_SC59 1.1A_6VDC_FUSE C213
(23,30) EC_DOCKIN# SEL
15 2 D_CRT_R 0.1U_0402_16V4Z
OE# 1B1
2B1 5 D_CRT_G
D_CRT_R (24)
D_CRT_G (24)
DOCK 2
11 D_CRT_B
3B1 D_CRT_B (24)
M_RED 4 14 JCRT1
(9) M_RED 1A 4B1
M_GREEN 7 6
(9) M_GREEN 2A
M_BLUE 9 11
(9) M_BLUE 3A
12 3 CRT_R 1 2 RED 1
4A 1B2 L24 FCM2012C-800_0805 CONN@
2B2 6 7
3B2 10 12
13 CRT_G 1 2 GREEN 2
4B2 L26 FCM2012C-800_0805
8 GND 8
+CRTVDD
13
FSAV330MTC_TSSOP16 CRT_B 1 2 BLUE 3
L28 FCM2012C-800_0805 9

1
14

2
2 R560R561 C661 2
4 16
@ R562 1 1 1 1 1 1 10 17 R555
M_RED 1 2 CRT_R C657C658C659 22P_0402_50V8J C660 C662 15 100K_0402_5%
R971 0_0402_5% 150_0402_1% 5

2
M_GREEN 1 @ 2 CRT_G 22P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J

1
R972 0_0402_5% 150_0402_1% 2 2 2 2 2 2 SUYIN_070549FR015S208CR
CRT_DET# (20)
M_BLUE 1 @ 2 CRT_B 150_0402_1%
R973 0_0402_5% 22P_0402_50V8J +3VS
+CRTVDD +CRTVDD +3VS
10P_0402_50V8J

1
1
R197 R198 R199 R200

2
+5VS +5VS 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5%

2
2
C214 C215 D_DDCDATA 6 1 3VDDCDA
3VDDCDA (9)
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 2 1 2 2N7002DW T/R7_SOT363-6

5
Q4A
2 1
R872 D_DDCCLK 3 4 3VDDCCL
3VDDCCL (9)
5
1

10K_0402_5% U4
SN74AHCT1G125GW_SOT353-5 R196
P
OE#

CRT_HSYNC HSYNC_G_A Q4B

(9) CRT_HSYNC 2 A Y 4 1 2 0_0603_5% DHSYNC
2N7002DW T/R7_SOT363-6
G

5
1

R558 1 2 0_0402_5% D_DDC_DATA (24)

R202 R559 1 2 0_0402_5%
P
OE#

D_DDC_CLK (24)
3

CRT_VSYNC 2 4 VSYNC_G_A 1 2 0_0603_5% DVSYNC

(9) CRT_VSYNC A Y
G

U5 1 @ 1 @
SN74AHCT1G125GW_SOT353-5 C216 C217
3
1

3 3
R204 R205 5P_0402_50V8C 5P_0402_50V8C
51K_0402_5% 51K_0402_5% 2 2
2

D_HSYNC (24)
D_VSYNC (24)

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 16 of 42
A B C D E
 5 4 3 2 1

+3VS +LCDVDD +LCDVDD +3VS

2N7002_SOT23-3
Q30

1
U54
R563

S
1 3

P
NC
GMCH_INV_PWM 4 2 300_0603_5% AO3413_SOT23
Y A DPST_PWM (9) +5VALW

G
1 1 1

G
2

2
NC7SZ14P5X_NL_SC70-5 C669 C670

2
@ C668 4.7U_0603_6.3V6K

1+LCDVDD_R
+LCDVDD 0.1U_0402_16V4Z 4.7U_0805_10V4Z
+3VS R564 2 2 2
100K_0402_5%
+INVPWR_B+ 0.1U_0402_16V4Z

1
1 10U_0805_10V4Z 1 1 1 1 R565
D L29 2 1 C667 C663 C664 C943 Q31 D D
B+
W=40mils KC FBM-L11-201209-221LMAT_0805 C868 2 2 1
0.1U_0402_16V4Z 1800P_0402_50V7K 2N7002_SOT23 G
L30 2 2 2 2 2 2 100K_0402_5%
1 S 2

3
KC FBM-L11-201209-221LMAT_0805 390P_0402_50V7K
1 1 C938
C665 C666 1U_0402_6.3V4Z

1
JLVDS D 1
680P_0402_50V7k 68P_0402_50V8J 42 41 DAC_BRIG 2 Q54
2 2 GND GND DAC_BRIG (30) (9) ENAVDD
+INVPWR_B+ 40 39 G 2N7002_SOT23
40 39 GMCH_INV_PWM INV_PWM
38 37 1 2 INV_PWM (30) S

3
38 37

1
+3VS 36 35 DISPLAYOFF# R1004 0_0402_5%
DDC2_CLK 36 35
(9) DDC2_CLK 34 34 33 33 +LCDVDD
DDC2_DATA 32 31 R885
(9) DDC2_DATA 32 31
30 29 W=60mils 100K_0402_5%
30 29
28 27

2
28 27 LVDS_A_0-
26 26 25 25 LVDS_A_0- (9)
24 23 LVDS_A_0+
24 23 LVDS_A_0+ (9)
22 22 21 21
20 19 LVDS_A_1-
20 19 LVDS_A_1- (9)
18 17 LVDS_A_1+ +3VS
18 17 LVDS_A_1+ (9)
16 16 15 15
14 13 LVDS_A_2+
14 13 LVDS_A_2+ (9)

2
12 11 LVDS_A_2-
12 11 LVDS_A_2- (9)
10 9 R569
10 9 LVDS_A_C- 220P_0402_50V7K
8 8 7 7 LVDS_A_C- (9)
6 5 LVDS_A_C+ DAC_BRIG 1 2 4.7K_0402_5%
6 5 LVDS_A_C+ (9)
R567 1 2 USB20_CMOS_N3 4 3 C672
(20) USB20_N3

1
R568 1 USB20_CMOS_P3 4 3 INV_PWM
(20) USB20_P3 2 2 2 1 1 +3VS 1 2 220P_0402_50V7K D43
0_0603_5% C673 (30) BKOFF# BKOFF# 1 2 DISPLAYOFF#
0_0603_5% ACES_88242-4001 DISPLAYOFF# 1 2 220P_0402_50V7K
CONN@ C674 CH751H-40PT_SOD323-2
C C

LVDS and USB CAM connector

+5VS
+3VS

0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 1 1 1 1 1

2
C774 C775 C776 C777 C779 C780 C781 U36
R878 R879
10U_0805_10V4Z 0_0402_5% 2.2K_0402_5% 2.2K_0402_5%
2 2 2 2 2 2 2 R859
OE* 25 1 2

1
0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS 2 VCC3V DVI_SCLK
11 VCC3V SCL_SINK 28 DVI_SCLK (24)
15 VCC3V
21 29 DVI_SDATA
VCC3V SDA_SINK DVI_SDATA (24)
disable 26
33
VCC3V
VCC3V
+3VS
inverting 40 VCC3V HPD_SINK 30 DVI_DET
DVI_DET (24)
46 0_0402_5%
output VCC3V
DDC_EN 32 R860 1 2 +3VS
+3VS 10K_0402_5% 10K_0402_5%
@ R99210K_0402_5% 1 2 3 34 R9911 2
R990 FUNCTION1 FUNCTION3 R994 +3VS
1 2 4 35
FUCNTION2 FUNCTION4 Docking Conn
2

R862 R861 1 2 10K_0402_5%

2.2K_0402_5% 2.2K_0402_5% R993 R863 1.2K_0402_5% 1 2
10K_0402_5% 2 1 6 R9951 2
ANALOG1(REXT) 10K_0402_5%
B HPD_7318_R
0 = disable inverting output B
7 @ pin 4
1

HPD_SOURCE
SDVO_SDAT 8
1 = enable inverting output
(7) SDVO_SDAT SDA_SOURCE
SDVO_SCLK
0 =Default value
(7) SDVO_SCLK 9 SCL_SOURCE pin 35
1 = output driver current
inverting level shift for NB 10 ANALOG2 increased 10%
DVI_TXC+ 13 48
+3VS (24) DVI_TXC+ OUT_D4+ IN_D4+ TMDS_B_CLK (9)
DVI_TXC- 14 47
Docking Conn (24) DVI_TXC- OUT_D4- IN_D4- TMDS_B_CLK# (9)
DVI_TXD2+ 16 45
(24) DVI_TXD2+ OUT_D3+ IN_D3+ TMDS_B_DATA2 (9)
1

DVI_TXD2- 17 44
(24) DVI_TXD2- OUT_D3- IN_D3- TMDS_B_DATA2# (9)
R868
20K_0402_5% DVI_TXD1+ 19 42
(24) DVI_TXD1+ OUT_D2+ IN_D2+ TMDS_B_DATA1 (9)
@ DVI_TXD1- 20 41
(24) DVI_TXD1- OUT_D2- IN_D2- TMDS_B_DATA1# (9)
0_0402_5%
2

R871 1 2 DVI_HPDT# (9) DVI_TXD0+ 22 39

(24) DVI_TXD0+ OUT_D1+ IN_D1+ TMDS_B_DATA0 (9)
DVI_TXD0- 23 38
(24) DVI_TXD0- OUT_D1- IN_D1- TMDS_B_DATA0# (9)
R874 2N7002_SOT23
1

0_0402_5% D
HPD_7318_R 1 2HPD_7318 2 Q52 R869
20K_0402_5%

G 7.5K_0402_1% 1
@ GND
S 5
3

GND
2

12
2

R887 R888 GND

18 GND
R870

0_0402_5% 0_0402_5% 24 GND

C772 27 GND
31
1

DVI_TXC- GND
2 R864 1 1 2 DVI_TXC+ 36 GND
A 68_0402_5% 0.5pf_0402_50V A
37 GND
C773 43 GND
DVI_TXD2- 2 R865 1 1 2 DVI_TXD2+
68_0402_5% 0.5pf_0402_50V CH7318A-BF-TR_QFN48_7X7
SA00001U910
HPD_7318_EC (30)
C782
DVI_TXD1- 2 R866 1 1 2 DVI_TXD1+
HPD_7318_R_EC (30)
68_0402_5% 0.5pf_0402_50V Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title
C783
DVI_TXD0- 2 R867 1 1 2 DVI_TXD0+ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
68_0402_5% 0.5pf_0402_50V AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 17 of 42
5 4 3 2 1
 5 4 3 2 1

+3VS

RP29
1 8 PCI_PIRQF#
2 7 PCI_PIRQA#
3 6 PCI_PIRQE#
4 5 PCI_SERR#

RP30 8.2K_1206_8P4R_5%
1 <BOM Structure>
8 PCI_PLOCK# U6B
2 7 PCI_IRDY# D11 F1 PCI_REQ0#
PCI_REQ3# AD0 REQ0# PCI_GNT0#
D
3
4
6
5 PCI_PIRQB#
C8
D9
AD1 PCI GNT0# G4
B6 PCI_REQ1# D
AD2 REQ1#/GPIO50
E12 AD3 GNT1#/GPIO51 A7 T65 PAD
8.2K_1206_8P4R_5% E9 F13 PCI_REQ2#
AD4 REQ2#/GPIO52
<BOM Structure> C9 AD5 GNT2#/GPIO53 F12 T66 PAD
E10 E6 PCI_REQ3#
AD6 REQ3#/GPIO54 PCI_GNT3#
B7 AD7 GNT3#/GPIO55 F6
C7 AD8
C5 AD9 C/BE0# D8 T67 PAD
G11 AD10 C/BE1# B4 T68 PAD
F8 AD11 C/BE2# D6 T69 PAD
+3VS F11 A5
AD12 C/BE3# T70 PAD
E7 AD13
RP31 A3 D3 PCI_IRDY#
PCI_STOP# AD14 IRDY#
1 8 D2 AD15 PAR E3 T71 PAD
2 7 PCI_PIRQD# F10 R1 PCI_RST#
AD16 PCIRST# PCI_RST# (28,30)
3 6 PCI_FRAME# D5 C6 PCI_DEVSEL#
AD17 DEVSEL#

1
4 5 PCI_PERR# D10 E4 PCI_PERR#
AD18 PERR# PCI_PLOCK# R942
B3 AD19 PLOCK# C2
RP32 8.2K_1206_8P4R_5% F7 J4 PCI_SERR# 100K_0402_5%
PCI_PIRQG# AD20 SERR# PCI_STOP#
1 <BOM Structure>
8 C3 AD21 STOP# A4
2 7 PCI_TRDY# F3 F5 PCI_TRDY#

2
PCI_REQ0# AD22 TRDY# PCI_FRAME#
3 6 F4 AD23 FRAME# D7
4 5 PCI_PIRQH# C1 AD24 PLT_RST#
G7 AD25 PLTRST# C14 PLT_RST# (7,20,22,23,27)
RP33 8.2K_1206_8P4R_5% H7 D4 PCI_CLK
AD26 PCICLK PCI_CLK (15)
1 <BOM Structure>
8 PCI_PIRQC# D1 R2 T72 PAD
PCI_REQ2# AD27 PME#
2 7 G5 AD28
3 6 PCI_REQ1# H6
PCI_DEVSEL# AD29
4 5 G1 AD30
H3 AD31
8.2K_1206_8P4R_5%

C
<BOM Structure>
PCI_PIRQA# J5
Interrupt I/F H4 PCI_PIRQE# C
PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF#
E1 PIRQB# PIRQF#/GPIO3 K6
PCI_PIRQC# J6 F2 PCI_PIRQG#
PCI_PIRQD# PIRQC# PIRQG#/GPIO4 PCI_PIRQH#
C4 PIRQD# PIRQH#/GPIO5 G2

ICH9M REV 1.0

A16 swap override Strap Boot BIOS Strap

B B
Low= A16 swap override Enble
PCI_GNT3# High= Default* PCI_GNT0# SPI_CS#1 Boot BIOS Location

@ R249 0 1 SPI
PCI_GNT3# 1 2
1K_0402_5%

1 0 PCI

1 1 LPC *
@ R944
@R944 1K_0402_5%
1 2 +3VALW

@ R250
SPI_CS1#_R 1 2
(20) SPI_CS1#_R
1K_0402_5%
@ R251
PCI_GNT0# 1 2
1K_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 18 of 42
5 4 3 2 1
 5 4 3 2 1

ICH8M Internal VR Enable Strap

(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)

ICH_INTVRMEN Low = Internal VR Disabled +3VS

+RTCVCC
High = Internal VR Enabled(Default) R253
GATEA20 1 2
1 2 SM_INTRUDER# 10K_0402_5%
R252 1M_0402_5% ICH8M LAN100 SLP Strap
1 2 LAN100_SLP R256
R254 330K_0402_1% (Internal VR for VccLAN1.05 and VccCL1.05) KB_RST# 1 2
1 2 ICH_INTVRMEN C340 10K_0402_5%
R255 R279 330K_0402_1% 18P_0402_50V8J
D ICH_SRTCRST# ICH_RTCX1 D
1 2 2 1 ICH_LAN100_SLP Low = Internal VR Disabled
20K_0402_5% <BOM Structure> +VCCP
High = Internal VR Enabled(Default)

10M_0402_5%
0_0402_5%

0_0402_5%
1 32.768KHZ_12.5P_MC-306
1

1
CLRP3 C253 @ @ 3 NC @ R260
@R260
OUT 4

R270
SHORT PADS R258 R259 H_DPRSTP# 1 2
2 1 56_0402_5%
2

2
1U_0603_10V4Z NC IN
LPC_AD[0..3] (30)

2
X1 C339 U6A @ R261
@R261

2
18P_0402_50V8J C23 K5 LPC_AD0 H_DPSLP# 1 2
ICH_RTCX2 RTCX1 FWH0/LAD0 LPC_AD1 56_0402_5%
2 1 C24 RTCX2 FWH1/LAD1 K4
R262 <BOM Structure> L6 LPC_AD2
ICH_RTCRST# FWH2/LAD2 LPC_AD3
+RTCVCC 1 2 A25 RTCRST# FWH3/LAD3 K2
ICH_SRTCRST#

RTC
LPC
20K_0402_5% F20
SM_INTRUDER# SRTCRST# LPC_FRAME#
C22 INTRUDER# FWH4/LFRAME# K3 LPC_FRAME# (30)
1 +VCCP

1
C243 CLRP2 ICH_INTVRMEN B22 J3
SHORT PADS LAN100_SLP INTVRMEN LDRQ0#
A22 LAN100_SLP LDRQ1#/GPIO23 J1
1U_0603_10V4Z

2
2 GATEA20
E25 GLAN_CLK A20GATE N7 GATEA20 (30)
AJ27 H_A20M# R263
A20M# H_A20M# (4)
C13 56_0402_5%
LAN_RSTSYNC H_DPRSTP_R# R264 <BOM
DPRSTP# AJ25 1 Structure>
2 H_DPRSTP#
H_DPRSTP# (5,7,40)
+3VALW F14 AE23 H_DPSLP# 0_0402_5%

LAN / GLAN
H_DPSLP# (5)

1
LAN_RXD0 DPSLP#
G13 LAN_RXD1
D14 AJ26 R_H_FERR# R265 1 2 H_FERR#
LAN_RXD2 FERR# H_FERR# (4)

2
56_0402_5%
R946 D13 AD22 H_PWRGOOD 3/28 add 56ohm
LAN_TXD0 CPUPWRGD H_PWRGOOD (5)
10K_0402_5% D12 LAN_TXD1
E13 AF25 H_IGNNE#
LAN_TXD2 IGNNE# H_IGNNE# (4)

CPU
within 2" from R1557

1
+1.5VS GPIO56 B10 AE22 H_INIT#
GPIO56 INIT# H_INIT# (4) +VCCP
AG25 H_INTR
C INTR H_INTR (4) C
B28 L3 KB_RST#
GLAN_COMPI RCIN# KB_RST# (30)
R266 24.9_0402_1% 1 2 GLAN_COMP B27 GLAN_COMPO

1
AF23 H_NMI
NMI H_NMI (4)
R267 33_0402_5% 1 2 HDA_BITCLK AF6 AF24 H_SMI# R269
(25) HDA_BITCLK_CODEC HDA_BIT_CLK SMI# H_SMI# (4)
R271 33_0402_5% 1 2 HDA_SYNC AH4 56_0402_5%
(25) HDA_SYNC_CODEC HDA_SYNC
AH27 H_STPCLK#
STPCLK# H_STPCLK# (4)
R272 33_0402_5% 1 2 HDARST# AE7
(25) HDA_RST#_CODEC

2
HDA_RST# THRMTRIP_ICH# R274
THRMTRIP# AG26 1 2 54.9_0402_1% H_THERMTRIP# (4,7)
CODEC HDA_SDIN0 AF4
(25) HDA_SDIN0 HDA_SDIN0
MDC HDA_SDIN1 AG4 AG27 placed within 2" from
(31) HDA_SDIN1 HDA_SDIN1 TP12

IHDA
AH3 HDA_SDIN2 ICH8M
AE5 HDA_SDIN3
SATA4RXN AH11
R276 33_0402_5% 1 2 HDA_SDOUT AG5 AJ11
(25) HDA_SDOUT_CODEC HDA_SDOUT SATA4RXP
SATA4TXN AG12
PAD T45 AG7 HDA_DOCK_EN#/GPIO33 SATA4TXP AF12
0814 Add pull up R +3VS 1 2 PAD T46 AE8 HDA_DOCK_RST#/GPIO34
R52210K_0402_5% AH9
SATA_LED# SATA5RXN
AG8 SATALED# SATA5RXP AJ9
(32) SATA_LED# AE10
SATA5TXN
(22) SATA_RXN0_C AJ16 SATA0RXN SATA5TXP AF10
0.01U_0402_16V7K AH16
(22) SATA_RXP0_C

SATA
SATA_TXN0 C248 SATA_TXN0_C SATA0RXP CLK_PCIE_SATA#
S- HDD (22) SATA_TXN0
SATA_TXP0 C249
1
1
2
SATA_TXP0_C
2<BOM Structure>
AF17
AG17
SATA0TXN SATA_CLKN AH18
AJ18 CLK_PCIE_SATA
CLK_PCIE_SATA# (15)
(22) SATA_TXP0 SATA0TXP SATA_CLKP CLK_PCIE_SATA (15)
0.01U_0402_16V7K AH13 AJ7
(22) SATA_RXN4_C SATA1RXN SATARBIAS#
0.01U_0402_16V7K AJ13 AH7 R277 1 2
(22) SATA_RXP4_C SATA1RXP SATARBIAS
SATA_TXN4 C244 SATA_TXN4_C
ODD (22) SATA_TXN4
SATA_TXP4 C245
1
1
2<BOM Structure>
SATA_TXP4_C
2<BOM Structure>
AG14
AF14
SATA1TXN 24.9_0402_1%
(22) SATA_TXP4 SATA1TXP
0.01U_0402_16V7K ICH9M REV 1.0
Within 500 mils
B B
RTC Battery
(31) HDA_BITCLK_MDC
(31) HDA_SYNC_MDC
R268
R273
33_0402_5%
33_0402_5%
1
1
2
2
HDA_BITCLK
HDA_SYNC
- BATT1 + +RTCBATT

2 1 +RTCBATT
R275 33_0402_5% 1 2 HDARST#
(31) HDA_RST_MDC#

2
R278 33_0402_5% 1 2 HDA_SDOUT
+3VS (31) HDA_SDOUT_MDC
ML1220T13RE R48
45@ 1K_0402_5%

@ R280
MDC

1 1
1 2 HDA_SDOUT
1K_0402_5% D8

@ R281
1 2 ICH_RSVD +RTCVCC
ICH_RSVD (20)
1K_0402_5%

2
BAS40-04_SOT23-3
XOR CHAIN ENTRANCE STRAP:RSVD 1
+CHGRTC
C109
<BOM Structure>
0.1U_0402_16V4Z
2
ICH_RSVD HDA_SDOUT_CODEC

A 0 0 Change BATT1 P/N : SP093PA0200 (Panasonic) A

SP093MX0000 (MAXELL)
0 1
1 0
1 1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 19 of 42
5 4 3 2 1
 5 4 3 2 1

+3VS 1 2 SIRQ Place closely pin AF3 Place closely pin H1

R286 10K_0402_5% +3VALW R287 1 2 2.2K_0402_5%
1 2 PM_CLKRUN# R289 1 2 2.2K_0402_5%
R288 8.2K_0402_5% U6C CLK_48M_ICH CLK_14M_ICH
1 2 GPIO39 ICH_SMBCLK G16 AH23 PROJECT_ID1
(15,22,28) ICH_SMBCLK SMBCLK SATA0GP/GPIO21
@R290
@ R290 10K_0402_5% ICH_SMBDATA A13 AF19 PROJECT_ID0
(15,22,28) ICH_SMBDATA SMBDATA SATA1GP/GPIO19

1
1 2 THERM_SCI# LINKALERT# E17 AE21 1 2 @ @

SATA
GPIO
ME_EC_CLK1 LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36

SMB
@R291
@ R291 8.2K_0402_5% C17 AD20 R945 10K_0402_5% R292 R293
CLKREQ#_C ME_EC_DATA1 SMLINK0 SATA5GP/GPIO37
1 2 B18 SMLINK1
R294 10K_0402_5% H1 CLK_14M_ICH 10_0402_5% 10_0402_5%
+3VS CLK14 CLK_14M_ICH (15)
1 2 GPIO18 EC_SWI# F19 AF3 CLK_48M_ICH

Clocks
CLK_48M_ICH (15)

2
@R295
@ R295 8.2K_0402_5% (30) EC_SWI# RI# CLK48
1 2 CR_WAKE# PAD T47 SUS_STAT# R4 P1 ICH_SUSCLK T48 PAD 1 @ 1 @
R296 8.2K_0402_5% XDP_DBRESET# SUS_STAT#/LPCPD# SUSCLK C256 C257
(4) XDP_DBRESET# G19 SYS_RESET#

1
1 2 GPIO20 @ @ C16 SLP_S3#
D SLP_S3# SLP_S3# (30) D
@ R297 8.2K_0402_5% R298 R299 PM_BMBUSY# M6 E16 SLP_S4# 4.7P_0402_50V8C 4.7P_0402_50V8C
(7) PM_BMBUSY# PMSYNC#/GPIO0 SLP_S4# SLP_S4# (30) 2 2
1 2 OCP# 10K_0402_5% 10K_0402_5% G17 SLP_S5#
SLP_S5# SLP_S5# (30)
R300 10K_0402_5% (30) EC_LID_OUT# EC_LID_OUT# A17
PM_BMBUSY# SMBALERT#/GPIO11 S4_STATE#
1 2 C10

2
@ R301 8.2K_0402_5% H_STP_PCI# S4_STATE#/GPIO26
(15) H_STP_PCI# A14 STP_PCI#
R303 2 0_0402_5% R_STP_CPU# ICH_PWROK

SYS GPIO
(15) H_STP_CPU# 1 E19 STP_CPU# PWROK G20 ICH_PWROK (7)
@
1 2 EC_SCI# (30) PM_CLKRUN# PM_CLKRUN# L4 M2 1 2 0_0402_5%
CLKRUN# DPRSLPVR/GPIO16 DPRSLPVR (7,40)
R305 8.2K_0402_5% R306
1 2 GPIO17 ICH_PCIE_WAKE# E20 B13 ICH_LOW_BAT# ICH_PWROK 1 2

Power MGT
(22,28) ICH_PCIE_WAKE# WAKE# BATLOW#
@ R307 8.2K_0402_5% SIRQ M5 R302 R304 10K_0402_5%
(30) SIRQ SERIRQ
THERM_SCI# AJ23 R3 PWRBTN_OUT# 0_0402_5%
(30) THERM_SCI# THRM# PWRBTN# PWRBTN_OUT# (30)
1 2 CR_CPPE# 1 2 PLT_RST# (7,18,22,23,27)
R949 10K_0402_5% VGATE D21 D20 1 2
(7,40) VGATE VRMPWRGD LAN_RST# R526 0_0402_5% @
1 2 GPIO48 R311 1 2 PAD T49 ICH_TP11 A20 D22 SB_RSMRST# PM_PWROK 1 2
@R310
@ R310 8.2K_0402_5% 100K_0402_5% TP11 RSMRST# R312 10K_0402_5%
1 2 PROJECT_ID1 (4) OCP#OCP# AG19 R5 CK_PWRGD_R R315 1 2 0_0402_5%
GPIO1 CK_PWRGD CK_PWRGD (15)
R314 8.2K_0402_5% CRT_DET AH21
PROJECT_ID0 CR_CPPE# GPIO6 R351 1 ICH_PWROK
1 2 (27) CR_CPPE# AG21 GPIO7 CLPWROK R6 2
R316 8.2K_0402_5% (30) EC_SMI# EC_SMI# A21 0_0402_5%
EC_SCI# GPIO8 PM_SLP_M# +3VS
(30) EC_SCI# C12 GPIO12 SLP_M# B16 T92 PAD
PAD T93 GPIO13 C21
GPIO17 GPIO13 CL_CLK0 R319
AE18 GPIO17 CL_CLK0 F24 CL_CLK0 (7)
GPIO18 K1 B19 0.1U_0402_16V4Z 1 2
GPIO20 GPIO18 CL_CLK1 3.24K_0402_1%
AF8 GPIO20

1
1 2 GPIO49 CR_WAKE# AJ22 F22 CL_DATA0 1
(27) CR_WAKE# SCLOCK/GPIO22 CL_DATA0 CL_DATA0 (7)
@R318
@ R318 10K_0402_5% PAD T50 GPIO27 A9 C19 C258 R320

GPIO
Controller Link
GPIO28 GPIO27 CL_DATA1 453_0402_1%
PAD T94 D19 GPIO28
CLKREQ#_C L1 C25 CL_VREF0_ICH <BOM Structure>
(15) CLKREQ#_C SATACLKREQ#/GPIO35 CL_VREF0 2
0812 No install +3VS 1 2 GPIO38 AE19 A19 CL_VREF1_ICH NA lead free

2
R321 @ 8.2K_0402_5% GPIO39 SLOAD/GPIO38 CL_VREF1
AG22 SDATAOUT0/GPIO39
C GPIO48 AF21 F21 CL_RST# +3VALW C
+3VALW SDATAOUT1/GPIO48 CL_RST0# CL_RST# (7)
GPIO49 AH24 D18
LINKALERT# @ GPIO57 GPIO49 CL_RST1# R324
1 2 A8 GPIO57/CLGPIO5
R322 10K_0402_5% +3VS R323 1 2 1K_0402_5% A16 GPIO24 0.1U_0402_16V4Z 1 2
ICH_PCIE_WAKE# SB_SPKR MEM_LED/GPIO24 GPIO10 3.24K_0402_1%
1 2 (25) SB_SPKR M7 SPKR GPIO10/SUS_PWR_ACK C18

1
R326 1K_0402_5% MCH_ICH_SYNC# AJ24 C11 1
(7) MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT
1 2 EC_SMI# ICH_RSVD B21 C20 C259 R327
(19) ICH_RSVD TP3 WOL_EN/GPIO9
R336 8.2K_0402_5% @ ICH_TP8 453_0402_1%

MISC
PAD T95 AH20 TP8 2 1 +3VALW
1 2 ICH_LOW_BAT# PAD T96 ICH_TP9 AJ20 R329 100K_0402_5% <BOM Structure>
R325 8.2K_0402_5% ICH_TP10 TP9 ICH_ACIN 2
PAD T97 AJ21 2 1

2
S4_STATE# TP10 D10 ACIN (30,32,34,37)
1 2
R331 10K_0402_5% @ ICH9M REV 1.0 GPIO9 CH751H-40PT_SOD323-2
T111 PAD
RP34 <BOM Structure>
4 5 EC_SWI# U6D
3 6 XDP_DBRESET# PCIE_RXN1 N29 V27 DMI_RXN0 DMI_RXN0 (7) @
(28) PCIE_RXN1 PERN1 DMI0RXN
2 7 ME_EC_CLK1 PCIE_RXP1 N28 V26 DMI_RXP0 DMI_RXP0 (7) R355 2 1 0_0402_5%
(28) PCIE_RXP1 PERP1 DMI0RXP

Direct Media Interface

ME_EC_DATA1 C682 1 2 0.1U_0402_16V7K PCIE_C_TXN1 DMI_TXN0
1 8 New Card (28) PCIE_TXN1
C680 1 2 0.1U_0402_16V7K PCIE_C_TXP1
P27
P26
PETN1 DMI0TXN U29
U28 DMI_TXP0
DMI_TXN0 (7) +3VALW
(28) PCIE_TXP1 PETP1 DMI0TXP DMI_TXP0 (7)
10K_1206_8P4R_5%
4 5 GPIO10 L29 Y27 DMI_RXN1 DMI_RXN1 (7)
PERN2 DMI1RXN

5
3 6 EC_LID_OUT# L28 Y26 DMI_RXP1 DMI_RXP1 (7) U23
GPIO24 PERP2 DMI1RXP DMI_TXN1 PM_PWROK
2 7 M27 W29 2

P
PETN2 DMI1TXN DMI_TXN1 (7) B PM_PWROK (29,30)
1 8 M26 W28 DMI_TXP1 DMI_TXP1 (7) ICH_PWROK 4
PETP2 DMI1TXP Y VGATE
A 1

G
RP35 10K_1206_8P4R_5% GLAN_RXN J29 AB27 DMI_RXN2 DMI_RXN2 (7)
(23) GLAN_RXN PERN3 DMI2RXN
GLAN_RXP J28 AB26 DMI_RXP2 DMI_RXP2 (7) NC7SZ08P5X_NL_SC70-5 2 1 +3VS
(23) GLAN_RXP

3
PERP3 DMI2RXP

PCI-Express
C268 1 2 0.1U_0402_16V7K GLAN_TXN_C DMI_TXN2 R337 @ 2K_0402_1%
GIGA LAN (23) GLAN_TXN
C269 1 2 0.1U_0402_16V7K GLAN_TXP_C
K27
K26
PETN3 DMI2TXN AA29
AA28 DMI_TXP2
DMI_TXN2 (7)
(23) GLAN_TXP PETP3 DMI2TXP DMI_TXP2 (7)
PCIE_RXN4 G29 AD27 DMI_RXN3 DMI_RXN3 (7) @
(22) PCIE_RXN4 PERN4 DMI3RXN
PCIE_RXP4 G28 AD26 DMI_RXP3 R353 2 1 0_0402_5%
RP27
MINI CARD (22) PCIE_RXP4
C684 1 2 0.1U_0402_16V7K PCIE_C_TXN4 H27
PERP4 DMI3RXP
AC29 DMI_TXN3
DMI_RXP3 (7)
Q21
B
(22) PCIE_TXN4 PETN4 DMI3TXN DMI_TXN3 (7) B
USB_OC#6 4 5 (22) PCIE_TXP4 C685 1 2 0.1U_0402_16V7K PCIE_C_TXP4 H26 AC28 DMI_TXP3 DMI_TXP3 (7) MMBT3906_SOT23-3
+3VALW PETP4 DMI3TXP
USB_OC#7 3 6 SB_RSMRST# 1 <BOM 3Structure>

C
EC_RSMRST# (30)
USB_OC#2 2 7 PCIE_RXN5 E29 T26 CLK_PCIE_ICH#

E
(27) PCIE_RXN5 PERN5 DMI_CLKN CLK_PCIE_ICH# (15)
USB_OC#3 1 8 PCIE_RXP5 E28 T25 CLK_PCIE_ICH
CARD READER (27) PCIE_RXP5 PERP5 DMI_CLKP CLK_PCIE_ICH (15)

1
C693 1 2 0.1U_0402_16V7K PCIE_C_TXN5 F27

B
(27) PCIE_TXN5

2
10K_1206_8P4R_5% C692 1 PETN5
(27) PCIE_TXP5 2 0.1U_0402_16V7K PCIE_C_TXP5 F26 PETP5 DMI_ZCOMP AF29 R338 24.9_0402_1% Within 500 mils R357 1 2 +3VALW
AF28 DMI_IRCOMP 1 2 +1.5VS 10K_0402_5% R358 4.7K_0402_5%
RP28 DMI_IRCOMP
C29 PERN6/GLAN_RXN

e
x
t
e
r
n
a
l
U
S
B
p
o
r
t
USB_OC#8 4 5 +3VALW C28 AC5 USB20_N0 D51A
USB20_N0 (28)

2
USB_OC#9 PERP6/GLAN_RXP USBP0N USB20_P0
3 6 D27 PETN6/GLAN_TXN USBP0P AC4 USB20_P0 (28) 1

d B U e
o T S x
c
k
i
n
g
USB_OC#10 2 7 D26 AD3 USB20_N8 6
PETP6/GLAN_TXP USBP1N USB20_N8 (24)
2

USB_OC#11 1 8 @ AD2 USB20_P8 2

USBP1P USB20_P8 (24)
R309 ICH_SPI_CLK R641 1 2 33_0402_5% ICH_SPI_CLK_R D23 AC1 USB20_N2
SPI_CLK USBP2N USB20_N2 (31)
10K_1206_8P4R_5% 10K_0402_5% ICH_SPI_CS0# R649 1 2 33_0402_5% ICH_SPI_CS0#_R D24 AC2 USB20_P2 BAV99DW-7_SOT363
SPI_CS0# USBP2P USB20_P2 (31)

B t
c
a a
m l
e S
r
a B S
(18) SPI_CS1#_R SPI_CS1#_R F23 AA5 USB20_N3 <BOM Structure>
SPI_CS1#/GPIO58/CLGPIO6 USBP3N USB20_N3 (17)
AA4 USB20_P3 D51B
USB20_P3 (17)
1

USBP3P

e
n r
r
U U

p p
r o
o
t
GPIO57 GLAN ICH_SPI_MOSI R650 1 2 33_0402_5% ICH_SPI_MOSI_R D25 AB2 USB20_N4 4
SPI_MOSI USBP4N USB20_N4 (28)
SPI

ICH_SPI_MISO R651 1 2 33_0402_5% ICH_SPI_MISO_R E23 AB3 USB20_P4 3

SPI_MISO USBP4P USB20_P4 (28)

e
x
t
e
n
a
l
B
r
t
2

AA1 USB20_N5 5
USBP5N USB20_N5 (28)

1
USB_OC#0 N4 AA2 USB20_P5
100K_0402_5% (28) USB_OC#0 OC0#/GPIO59 USBP5P USB20_P5 (28)

F
P M
CP_PE# USB20_N6 +3VS BAV99DW-7_SOT363 R354
(28) CP_PE# N5 OC1#/GPIO40 USBP6N W5 USB20_N6 (31)
R524 USB_OC#2 USB20_P6 2.2K_0402_5%
N6 OC2#/GPIO41 USBP6P USB W4 USB20_P6 (31) <BOM Structure>

I
N
I W
C C
A A
R
D D
USB_OC#3 P6 Y3 USB20_N7
USB20_N7 (22)
1

OC3#/GPIO42 USBP7N

2
USB_OC#4 M1 Y2 USB20_P7
(28) USB_OC#4 USB20_P7 (22)

2
OC4#/GPIO43 USBP7P

N
E

R
USB_OC#5 N2 W1 USB20_N1 R360
(28) USB_OC#5 OC5#/GPIO29 USBP8N USB20_N1 (28)
USB_OC#6 M4 W2 USB20_P1 10K_0402_5%
OC6#/GPIO30 USBP8P USB20_P1 (28)
0814 UPDATE USB_OC#7 M3 V2 High: CRT Plugged
USB_OC#8 OC7#/GPIO31 USBP9N
N3 V3

1
USB_OC#9 OC8#/GPIO44 USBP9P CRT_DET
N1 OC9#/GPIO45 USBP10N U5
USB_OC#10 P5 U4
OC10#/GPIO46 USBP10P

1
USB_OC#11 D
P3 OC11#/GPIO47 USBP11N U1
U2 2 2N7002_SOT23
A +3VS USBP11P (16) CRT_DET# A
ICH SPI ROM for HDCP @ USBRBIAS AG2 R952 Q22G
U40 USBRBIAS
AG1 (24) D_CRT_DET# 2 1 S <BOM Structure>

3
USBRBIAS#
1

ICH_SPI_CS0# 1 8 Within 500 mils

R652 1 CS# VCC
+3VS 2 3.3K_0402_5% ICH_SPI_WP# 3 WP# SCLK 6 ICH_SPI_CLK ICH9M REV 1.0 0_0402_5%
R653 1 2 3.3K_0402_5% ICH_SPI_HOLD# 7 5 ICH_SPI_MOSI R340
HOLD# SI ICH_SPI_MISO 22.6_0402_1%
4 GND SO 2
2

MX25L512AMC-12G_SO8
SA000022S00 Security Classification Compal Secret Data Compal Electronics, Inc.
If ICH SPI not used, Left NC SPI ROM Footprint 150mil Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 20 of 42
5 4 3 2 1
 5 4 3 2 1

+RTCVCC +VCCP U6E

20 mils U6F AA26 H5
VSS[1] VSS[107]
A23 VCCRTC
G3: 6uA VCC1_05[1] A15 AA27 VSS[2] VSS[108] J23

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1634mA
VCC1_05[2] B15 AA3 VSS[3] VSS[109] J26
1 1 ICH_V5REF_RUN A6 2mA C15 0.1U_0402_16V4Z 0.1U_0402_16V4Z AA6 J27
V5REF VCC1_05[3] VSS[4] VSS[110]

C270

C271
VCC1_05[4] D15 1 1 AB1 VSS[5] VSS[111] AC22
ICH_V5REF_SUS AE1 2mA E15 C272 C273 AA23 K28
V5REF_SUS VCC1_05[5] VSS[6] VSS[112]
VCC1_05[6] F15 AB28 VSS[7] VSS[113] K29
2 2
AA24 VCC1_5_B[1] VCC1_05[7] L11 AB29 VSS[8] VSS[114] L13
646mA 2 2
0820 Change to 0805 AA25 VCC1_5_B[2] VCC1_05[8] L12 AB4 VSS[9] VSS[115] L15
AB24 VCC1_5_B[3] VCC1_05[9] L14 AB5 VSS[10] VSS[116] L2
AB25 VCC1_5_B[4] VCC1_05[10] L16 AC17 VSS[11] VSS[117] L26
R341 40 mils AC24 L17 0.01U_0402_16V7K AC26 L27
VCC1_5_B[5] VCC1_05[11] VSS[12] VSS[118]

<BOM Structure>
+1.5VS 1 2 10U_0805_10V4Z AC25 L18 +1.5VS_VCCDMIPLL R342 1 2 +1.5VS AC27 L5
0_0805_5% VCC1_5_B[6] VCC1_05[12] MBK1608301YZF_0603 VSS[13] VSS[119]
1 AD24 VCC1_5_B[7] VCC1_05[13] M11 AC3 VSS[14] VSS[120] L7
D D
1 1 1 AD25 VCC1_5_B[8] VCC1_05[14] M18 1 1 AD1 VSS[15] VSS[121] M12
+

220U_D2_4VM_R15
C275 C276 C277 AE25 P11 C278 C279 AD10 M13
VCC1_5_B[9] VCC1_05[15] VSS[16] VSS[122]

C274
AE26 VCC1_5_B[10] VCC1_05[16] P18 AD12 VSS[17] VSS[123] M14
AE27 VCC1_5_B[11] VCC1_05[17] T11 AD13 VSS[18] VSS[124] M15
2 2 2 2 2 2
0816 Change to 10 ohm <BOM Structure>
<BOM Structure> <BOM Structure> AE28 VCC1_5_B[12] VCC1_05[18] T18 <BOM Structure>
<BOM Structure> AD14 VSS[19] VSS[125] M16
AE29 U11 AD17 M17

CORE
10U_0805_10V4Z 2.2U_0603_6.3V4Z VCC1_5_B[13] VCC1_05[19] 10U_0805_10V4Z VSS[20] VSS[126]
F25 VCC1_5_B[14] VCC1_05[20] U18 AD18 VSS[21] VSS[127] M23
+5VS +3VS G25 V11 AD21 M28
VCC1_5_B[15] VCC1_05[21] VSS[22] VSS[128]
H24 VCC1_5_B[16] VCC1_05[22] V12 AD28 VSS[23] VSS[129] M29
H25 VCC1_5_B[17] VCC1_05[23] V14 +VCCP AD29 VSS[24] VSS[130] N11
1

22U_0805_6.3VAM
J24 VCC1_5_B[18] VCC1_05[24] V16 AD4 VSS[25] VSS[131] N12
R343 D11 J25 V17 1 0905 Connect to +VCCP AD5 N13
VCC1_5_B[19] VCC1_05[25] C280 VSS[26] VSS[132]
K24 VCC1_5_B[20] VCC1_05[26] V18 AD6 VSS[27] VSS[133] N14
100_0402_5% CH751H-40PT_SOD323-2 K25 AD7 N15
VCC1_5_B[21] VSS[28] VSS[134]
L23 R29 AD9 N16
2

VCC1_5_B[22] VCCDMIPLL 2 VSS[29] VSS[135]

L24 VCC1_5_B[23] AE12 VSS[30] VSS[136] N17
SD028100080 ICH_V5REF_RUN L25 23mA W23 AE13 N18
VCC1_5_B[24] VCC_DMI[1] +VCCP VSS[31] VSS[137]
1 20 mils M24 VCC1_5_B[25] VCC_DMI[2] Y23 AE14 VSS[32] VSS[138] N26
C281 M25 AE16 N27
VCC1_5_B[26] 48mA VSS[33] VSS[139]
N23 VCC1_5_B[27] V_CPU_IO[1] AB23 AE17 VSS[34] VSS[140] P12
1U_0402_6.3V4Z N24 AC23 AE2 P13
2 SE100105Z80 VCC1_5_B[28] V_CPU_IO[2] VSS[35] VSS[141]

4.7U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
N25 VCC1_5_B[29] AE20 VSS[36] VSS[142] P14
P24 2mA AG29 +3VS AE24 P15
VCC1_5_B[30] VCC3_3[1] 1 1 1 VSS[37] VSS[143]

C282

C283

C284
P25 VCC1_5_B[31] AE3 VSS[38] VSS[144] P16

VCCA3GP
R24 VCC1_5_B[32] VCC3_3[2] AJ6 AE4 VSS[39] VSS[145] P17
+5VALW +3VALW

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
R25 VCC1_5_B[33] AE6 VSS[40] VSS[146] P2
2 2 2
R26 VCC1_5_B[34] VCC3_3[7] AC10 1 1 1 AE9 VSS[41] VSS[147] P23
R27 VCC1_5_B[35] AF13 VSS[42] VSS[148] P28
1

C285

C286

C287
D12 T24 AD19 AF16 P29
R344 VCC1_5_B[36] VCC3_3[3] VSS[43] VSS[149]

VCCP_CORE
T27 VCC1_5_B[37] VCC3_3[4] AF20 AF18 VSS[44] VSS[150] P4
2 2 2 (DMI)
T28 VCC1_5_B[38] VCC3_3[5] AG24 AF22 VSS[45] VSS[151] P7
100_0402_5% CH751H-40PT_SOD323-2 T29 AC20 +3VS AH26 R11
C VCC1_5_B[39] VCC3_3[6] VSS[46] VSS[152] C
U24 AF26 R12
2

ICH_V5REF_SUS VCC1_5_B[40] 0.1U_0402_16V4Z VSS[47] VSS[153]

U25 VCC1_5_B[41]
308mA
VCC3_3[8] B9 AF27 VSS[48] VSS[154] R13
20 mils V24 VCC1_5_B[42] VCC3_3[9] F9 1 1 0816 Add 0.1uF AF5 VSS[49] VSS[155] R14
SD028100080 1 V25 G3 C288 C479 AF7 R15
C289 VCC1_5_B[43] VCC3_3[10] VSS[50] VSS[156]
U23 VCC1_5_B[44] VCC3_3[11] G6 AF9 VSS[51] VSS[157] R16
W24 J2 0.1U_0402_16V4Z AG13 R17
1U_0402_6.3V4Z VCC1_5_B[45] VCC3_3[12] 2 2 VSS[52] VSS[158]

PCI
W25 VCC1_5_B[46] VCC3_3[13] J7 AG16 VSS[53] VSS[159] R18
2 SE100105Z80
K23 VCC1_5_B[47] VCC3_3[14] K7 AG18 VSS[54] VSS[160] R28
Y24 R964 0_0402_5% AG20 T12
VCC1_5_B[48] +VCCHDA 0.1U_0402_16V4Z VSS[55] VSS[161]
Y25 VCC1_5_B[49] VCCHDA AJ4 1 R966 0_0402_5%
2 +3VS AG23 VSS[56] VSS[162] T13
R345 R965 0_0402_5% 1 1 2 +1.5VS AG3 T14
47mA 11mA +VCCSUSHDA R967 0_0402_5% C290 VSS[57] VSS[163]
+1.5VS 1 2 AJ19 VCCSATAPLL VCCSUSHDA AJ3 1 2 +3VALW AG6 VSS[58] VSS[164] T15
1U_0603_10V4Z

MBK1608301YZF_0603 0.1U_0402_16V4Z 1 1 2 +1.5V @ AG9 T16

11mA VSS[59] VSS[165]
10U_0805_10V4Z

AC16 AC8 C291 AH12 T17

+1.5VS VCC1_5_A[1] VCCSUS1_05[1] T55 2 VSS[60] VSS[166]
1 1 AD15 F17 @ AH14 T23
VCC1_5_A[2] VCCSUS1_05[2] T56 VSS[61] VSS[167]
C292

C293

1 AD16 VCC1_5_A[3] AH17 VSS[62] VSS[168] B26

2
ARX

C294 AE15 AD8 VCCSUS1_5_ICH_1 AH19 U12

VCC1_5_A[4] VCCSUS1_5[1] T57 VSS[63] VSS[169]
AF15 VCC1_5_A[5] AH2 VSS[64] VSS[170] U13
2 2 1U_0603_10V4Z VCCSUS1_5_ICH_2
<BOM Structure>
<BOM Structure> AG15 VCC1_5_A[6] VCCSUS1_5[2] F18 AH22 VSS[65] VSS[171] U14
2 T58
AH15 VCC1_5_A[7] 1 AH25 VSS[66] VSS[172] U15
AJ15 +3VALW C480 AH28 U16
VCC1_5_A[8] 0.1U_0402_16V4Z VSS[67] VSS[173]
A18 AH5 U17
VCCPSUS

VCCSUS3_3[1] VSS[68] VSS[174]

0.1U_0402_16V4Z
AC11 D16 1 1 0.1U_0402_16V4Z AH8 AD23
+1.5VS VCC1_5_A[9] VCCSUS3_3[2] 2 VSS[69] VSS[175]
1 AD11 VCC1_5_A[10] VCCSUS3_3[3] D17 AJ12 VSS[70] VSS[176] U26

C295

C296
C297 AE11 E22 AJ14 U27
VCC1_5_A[11] VCCSUS3_3[4] VSS[71] VSS[177]
ATX

AF11 VCC1_5_A[12] AJ17 VSS[72] VSS[178] U3

1U_0603_10V4Z 2 2
2
AG10 VCC1_5_A[13]
212mA 0816 Add 0.1uF AJ8 VSS[73] VSS[179] V1
AG11 VCC1_5_A[14] VCCSUS3_3[5] AF1 B11 VSS[74] VSS[180] V13
AH10 VCC1_5_A[15] B14 VSS[75] VSS[181] V15
AJ10 VCC1_5_A[16] VCCSUS3_3[6] T1 B17 VSS[76] VSS[182] V23
VCCSUS3_3[7] T2 B2 VSS[77] VSS[183] V28
AC9 VCC1_5_A[17] VCCSUS3_3[8] T3 B20 VSS[78] VSS[184] V29
B
T4 +3VALW B23 V4 B
VCCSUS3_3[9] VSS[79] VSS[185]
AC18 VCC1_5_A[18] VCCSUS3_3[10] T5 B5 VSS[80] VSS[186] V5
AC19 VCC1_5_A[19] VCCSUS3_3[11] T6 B8 VSS[81] VSS[187] W26
1342mA U6 1 C26 W27
VCCPUSB

+1.5VS VCCSUS3_3[12] VSS[82] VSS[188]

AC21 U7 C298 C27 W3
VCC1_5_A[20] VCCSUS3_3[13] VSS[83] VSS[189]
1 VCCSUS3_3[14] V6 E11 VSS[84] VSS[190] Y1
C299 G10 V7 4.7U_0603_6.3V6M E14 Y28
VCC1_5_A[21] VCCSUS3_3[15] 2 VSS[85] VSS[191]
G9 VCC1_5_A[22] VCCSUS3_3[16] W6 E18 VSS[86] VSS[192] Y29
0.1U_0402_16V4Z W7 E2 Y4
2 VCCSUS3_3[17] VSS[87] VSS[193]
AC12 VCC1_5_A[23] VCCSUS3_3[18] Y6 E21 VSS[88] VSS[194] Y5
AC13 VCC1_5_A[24] VCCSUS3_3[19] Y7 E24 VSS[89] VSS[195] AG28
+1.5VS AC14 VCC1_5_A[25] VCCSUS3_3[20] T7 E5 VSS[90] VSS[196] AH6
1 11mA 11mA E8 AF2
C300 VCCCL1_05_ICH VSS[91] VSS[197]
AJ5 VCCUSBPLL VCCCL1_05 G22 F16 VSS[92] VSS[198] B25
1 F28 VSS[93]
0.1U_0402_16V4Z AA7 G23 C481 F29 A1
2 VCC1_5_A[26] VCCCL1_5 VSS[94] VSS_NCTF[1]
USB CORE

AB6 VCC1_5_A[27]
19/73/73mA G12 VSS[95] VSS_NCTF[2] A2
AB7 VCC1_5_A[28] VCCCL3_3[1] A24 +3VS 1 @ 2
0.1U_0402_16V4Z G14 VSS[96] VSS_NCTF[3] A28
AC6 B24 C301 G18 A29
VCC1_5_A[29] VCCCL3_3[2] 1U_0603_10V4Z VSS[97] VSS_NCTF[4]
AC7 VCC1_5_A[30] G21 VSS[98] VSS_NCTF[5] AH1
G24 VSS[99] VSS_NCTF[6] AH29
T60 VCC_LAN1_05_INT_ICH_1 2
+3VS
A10 VCCLAN1_05[1] 0816 Add 0.1uF G26 VSS[100] VSS_NCTF[7] AJ1
T61 VCC_LAN1_05_INT_ICH_2 A11 G27 AJ2
R535 0_0603_5% VCCLAN1_05[2] VSS[101] VSS_NCTF[8]
G8 VSS[102] VSS_NCTF[9] AJ28
1 2 +3VS_VCCLAN A12 H2 AJ29
VCCLAN3_3[1] VSS[103] VSS_NCTF[10]
0.1U_0402_16V4Z

1 B12 19/78/78mA H23 B1

C302 R346 0_0603_5% VCCLAN3_3[2] VSS[104] VSS_NCTF[11]
23mA H28 VSS[105] VSS_NCTF[12] B29
1 2 +1.5VS_VCCGLANPLL A27 H29
R347 VCCGLANPLL VSS[106]
+1.5VS 80mA
2
GLAN POWER
10U_0805_10V4Z

2+1.5VS_VCCGLAND28 ICH9M REV 1.0

2.2U_0603_6.3V4Z

+1.5VS 1 VCCGLAN1_5[1]
D29 VCCGLAN1_5[2]
1 1 0_0603_5% 1 E26
A C303 C304 VCCGLAN1_5[3] A
E27 VCCGLAN1_5[4]
1mA
+3VS A26 VCCGLAN3_3
2 2 2
0316 change design C305 ICH9M REV 1.0
4.7U_0805_10V4Z

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 21 of 42
5 4 3 2 1
 5 4 3 2 1

HDD Connector
+5VS
JSATA1
CD-ROM Connector
GND S1
S2 SATA_TXP0
A+ SATA_TXP0 (19)
10U_0805_10V4Z

0.1U_0402_16V4Z
S3 SATA_TXN0
A- SATA_TXN0 (19)
1 1 1 1 S4 0.01U_0402_16V7K
GND +5VS
C311

C314
S5 SATA_RXN0 2 1 C306 SATA_RXN0_C
B- SATA_RXN0_C (19)
C312 C313 S6 SATA_RXP0 2 1 C315 SATA_RXP0_C JSATA2
2 2 2 2
B+
GND S7 0.01U_0402_16V7K
SATA_RXP0_C (19)
Placea caps. near ODD CONN. Near CONN side.
D 0.1U_0402_16V4Z 0.1U_0402_16V4Z Near CONN side. GND
A+
1
2 SATA_TXP4
SATA_TXP4 (19)
D
3 SATA_TXN4
A- SATA_TXN4 (19)
P1 4 0.01U_0402_16V7K
VCC3.3 +3VS_HDD1 GND SATA_RXN4
Pleace near HD CONN (JP23) VCC3.3 P2 B- 5 2 1 C322 SATA_RXN4_C SATA_RXN4_C (19)

0.1U_0402_16V4Z

1U_0603_10V4Z

10U_0805_10V4Z
P3 6 SATA_RXP4 2 1 C323 SATA_RXP4_C
VCC3.3 B+ SATA_RXP4_C (19)
P4 1 1 1 1 7 0.01U_0402_16V7K
GND GND

C324
+3VS P5
GND

C325

C326
@ R3480_0805_5%
@R3480_0805_5% +3VS_HDD1 P6 C327
GND 10U_0805_10V4Z
2 1 VCC5 P7 DP 8
0.1U_0402_16V4Z +5VS 2 2 2 2
VCC5 P8 +5V 9 +5VS
1 1 1 VCC5 P9 +5V 10
GND P10 MD 11
@C319
@ C319 @C320
@ C320 @ C321 P11 15 12
RESERVED GND GND
GND P12 14 GND GND 13
2 2 2
23 G1 VCC12 P13
1000P_0402_50V7K 1U_0603_10V4Z 24 P14
G2 VCC12 OCTEK_0709015-SD001_RV
VCC12 P15
Pleace near HD CONN
CONN@
OCTEK_SAT-22SB1_REVERS

CONN@

C C

+3VS_WLAN R415 1 2 0_1206_5% +3VS

R414 1 @ 2 0_1206_5% +3VALW

+3VS_WLAN +1.5VS +3VS

1 1 1 1 1 1
C686 C687 C688 C689 C690 C691

4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

2 2 2 2 2 2

JMINI1
ICH_PCIE_WAKE# R572 1 @ 2 0_0402_5% 1 2 +3VS_WLAN
(20,28) ICH_PCIE_WAKE# 1 2
WLAN_BT_DATA 3 4
(31) WLAN_BT_DATA 3 4
WLAN_BT_CLK 5 6 +1.5VS
(31) WLAN_BT_CLK 5 6
(15) MCARD_CLKREQ# 7 7 8 8
9 9 10 10
(15) CLK_PCIE_MCARD1# 11 11 12 12
(15) CLK_PCIE_MCARD1 13 13 14 14
15 15 16 16

17 17 18 18
19 20 WL_OFF#
19 20 WL_OFF# (30)
21 22 PLT_RST#
B 21 22 PLT_RST# (7,18,20,23,27) B
23 24 R573 1 2 0_0603_5% +3VS_WLAN
(20) PCIE_RXN4 23 24
25 26 R654 1 2 0_0603_5% +3VALW
(20) PCIE_RXP4 25 26
27 28 @
27 28 ICH_SMBCLK
29 29 30 30 ICH_SMBCLK (15,20,28)
(20) PCIE_TXN4 31 32 ICH_SMBDATA ICH_SMBDATA (15,20,28)
31 32
(20) PCIE_TXP4 33 33 34 34
35 35 36 36 USB20_N7 (20)
37 37 38 38 USB20_P7 (20)
+3VS_WLAN 39 39 40 40
41 42 (MINI1_LED#)
41 42
43 43 44 44 MINI1_LED# (32)
45 45 46 46

UTX
47
49
47 48 48
50
R998 (9~16mA)
(30) UTX 49 50
URX 51 52 1 2 +3VS
(30) URX 51 52
G1
G2
G3
G3

10K_0402_5%
FOX_AS0B226-S99N-7F @
For MINICARD Port80 Debug
53
54
55
56

CONN@

For Wireless LAN

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 22 of 42
5 4 3 2 1
 5 4 3 2 1

LAN RTL8111C/8102E

B3
e
a
dm
f
o
r
8
1
1
1
C
4
.
7
u
H
c
h
o
k
e

0
0
A
+3V_LAN
KC FBM-L11-201209-221LMAT_0805 L55 8111C@ +LAN_AVDD12 L56 +LAN_EVDD12
60mil 40mil 4.7UH_1008HC-472EJFS-A_5%_1008 MBK1608121YZF_0603
+3VALW 1
L62
2
SROUT12
40mil 20mil
1 1 2 1 2
1 1 1 1 1
C937 + C806 C807 C808 C809 C936 1 1 1 1 1 1 1 1 1
150U_D2_6.3VM C810 C811 C812 C813 C814 C815 C816 C817 C818
@
2 2
0.1U_0402_16V4Z
2 2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
2007/12/07
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
D 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 2 2 2 2 D
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
@ @

1
R891 @ @
SM010014520 KC FBM-L11-201209-221LMAT_0805
8111C@

2
1 LAN_PME# +1.2V_LAN
+3V_LAN 2
R890
EMI
100K_0402_5%
40mil

1 1 1 1 1 1 1 1
C873 C874 C823 C824 C825 C826 C827 C829

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

R894
3.6K_0402_5%
1 2 +3V_LAN

Place closed to Chip U41

U42
C830 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_P3 29 45 LAN_DO 4 5 2
C (20) GLAN_RXP HSOP EEDO DO GND C
47 LAN_DI 3 6 C831
C828 1 EEDI/AUX DI NC
(20) GLAN_RXN 2 0.1U_0402_16V7K PCIE_PTX_IRX_N3 30 HSON EESK 48 LAN_SK 2 SK NC 7 0.1U_0402_16V4Z
44 LAN_CS 1 8 +3V_LAN
GLAN_TXP EECS CS VCC 1
(20) GLAN_TXP 23 HSIP AT93C46-10SI-2.7_SO8
GLAN_TXN 24 SA000019910
(20) GLAN_TXN HSIN
LED3 54
55 @
LED2 LAN_LINK#
33 CLKREQB LED1 56
57 LAN_ACTIVITY#
LED0
(15) CLK_PCIE_LAN 26 REFCLK_P
27 3 LAN_MDI0+
(15) CLK_PCIE_LAN# REFCLK_N MDIP0
4 LAN_MDI0-
R895 1 MDIN0
(7,18,20,22,27) PLT_RST# 2 0_0402_5% LAN_RESET# 20 PERSTB MDIP1 6 LAN_MDI1+
7 LAN_MDI1-
MDIN1 LAN_MDI2+
switching 1.2V MDIP2 9
SROUT12 1 10 LAN_MDI2-
ouput for 8111c SROUT12 MDIN2
12 LAN_MDI3+
MDIP3 LAN_MDI3- +3V_LAN
+LAN_AVDD12 5 FB12 MDIN3 13

+3V_LAN R896 1 8111C@ 2 0_0603_5% ENSR 62 ENSR

DVDD12 21 +1.2V_LAN
R897 1 2 2.49K_0402_1% 64 32
RSET DVDD12 U34

56
50
38
27
18
10
DVDD12 38

4
1.2V 43 for 8111C: pin63 is PI3L500-AZFEX_TQFN56_11X5
DVDD12
49 a power input pin

VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
VDD0
R898 1 DVDD12
(30) EC_LAN_PME# 2 0_0402_5% LAN_PME# 19 LANWAKEB DVDD12 52 for 1.2v switching 0B1 48 D_LAN_MDI0+
D_LAN_MDI0+ (24)
47 D_LAN_MDI0-
regulator 1B1 D_LAN_MDI0- (24)
ISOLATEB 36 LAN_MDI0+ 2
ISOLATEB A0 D_LAN_MDI1+
EVDD12 22 +LAN_EVDD12 2B1 43 D_LAN_MDI1+ (24)
1.2V 28 LAN_MDI0- 3 42 D_LAN_MDI1-
B EVDD12 +3V_LAN A1 3B1 D_LAN_MDI1- (24) B
LAN_X1 60 CKTAL1 D_LAN_MDI2+
4B1 37 D_LAN_MDI2+ (24)
Y6 LAN_X2 LAN_MDI1+ D_LAN_MDI2-
61 CKTAL2 VDD33 16 +3V_LAN EMI 7 A2 5B1 36 D_LAN_MDI2- (24)

1
LAN_X1 1 2 LAN_X2 37
3.3V VDD33 R892 LAN_MDI1- D_LAN_MDI3+
VDD33 46 8 A3 6B1 32 D_LAN_MDI3+ (24)
1 25MHZ_20P 1 53 FBMA-L10-160808-301LMT_0603 31 D_LAN_MDI3-
VDD33 7B1 D_LAN_MDI3- (24)
65 8111C@
C832 C833 EXPOSE_PAD SM010017710 LAN_MDI2+ D_LAN_ACTIVITY#
40mil 11 22 D_LAN_ACTIVITY# (24)
2
27P_0402_50V8J 27P_0402_50V8J +VDDSR A4 0LED1 D_LAN_LINK#
VDDSR 63 1LED1 23 D_LAN_LINK# (24)
2 2 LAN_MDI2-
25 EGND 1 1 12 A5 2LED1 52
2 +AVDD33 C820 C821
3.3V AVDD33 8111C@ 8111C@ L_LAN_MDI0+
31 EGND AVDD33 59 0B2 46 L_LAN_MDI0+ (24)
0.1U_0402_16V4Z 10U_0805_10V4Z LAN_MDI3+ 14 45 L_LAN_MDI0-
2 2 A6 1B2 L_LAN_MDI0- (24)
R934 8 +LAN_AVDD12
AVDD12
+1.2V_LAN 1 2 0_0402_5% 15 NC AVDD12 11 LAN_MDI3- 15 A7 2B2 41 L_LAN_MDI1+
L_LAN_MDI1+ (24)
17 1.2V 14 40 L_LAN_MDI1-
NC AVDD12 3B2 L_LAN_MDI1- (24)
18 NC AVDD12 58 +1.2V_LAN
34 EC_DOCKIN# 17 35 L_LAN_MDI2+
NC (16,30) EC_DOCKIN# SEL 4B2 L_LAN_MDI2+ (24)
35 34 L_LAN_MDI2-
NC +3V_LAN 5B2 L_LAN_MDI2- (24)
39 NC IGPIO 50
40 51 1 2 LAN_ACTIVITY# 19 30 L_LAN_MDI3+
NC OGPIO LED0 6B2 L_LAN_MDI3+ (24)
41 R974 LAN_LINK# 20 29 L_LAN_MDI3-
NC EMI LED1 7B2 L_LAN_MDI3- (24)
1

42 15K_0402_1% 54
+3VS NC @ R899 LED2 L_LAN_ACTIVITY#
0LED2 25 L_LAN_ACTIVITY# (24)
RTL8111C-GR_QFN64_9X9 FBMA-L10-201209-301LMT_0805 5 26 L_LAN_LINK#
NC 1LED2 L_LAN_LINK# (24)
8111C@ NOTE: L : A-->B1 2LED2 51
1

SM010018010 57
H: A-->B2
2

R900 PAD_GND

GND10
GND11
GND12
GND13
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
1K_0402_1% +AVDD33
1 1
C834 C835
2

ISOLATEB

1
6
9
13
16
21
24
28
33
39
44
49
53
55
A 0.1U_0402_16V4Z 0.1U_0402_16V4Z A
1

2 2
R901
15K_0402_1%

Place closed to Pin2 & Pin59

2

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29
SCHEMATICS,MB A4271
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 23 of 42
5 4 3 2 1
 5 4 3 2 1

VIN_DOCK (17) DVI_TXC-

DVI_TXC- 1 2 DVI_R_TXC-
R954 0_0402_5%
C869 1800P_0402_50V7K
1 2 @ WCM-2012-900T_0805
4 4 3 3
JDOCK1
+5VALW
65
66
GND ACER DOCK 19V_5A 67
68
1 1 2 2
GND 5V_USB_3A L57
Normal
1 33 D_LINEIN_PLUG# DVI_TXC+ 1 2 DVI_R_TXC+
GND LIN_IN_DT# D_LINEIN_PLUG# (25) (17) DVI_TXC+
DVI_R_TXC+ 2 34 D_LINE_L R955 0_0402_5%
DVI_CLK 1 P1 P3 46 LIN_IN_L D_LINE_L (26)
DVI_R_TXC- 3 35 D_LINE_R
D DVI_CLK# 2 (65) (67) 47 LIN_IN_R D_LINE_R (26) D
4 36 MIC_PLUG#
GND 3 48 MIC_DT# MIC_PLUG# (25,26)
DVI_R_TXD0+ 5 37 D_MIC1_L DVI_TXD0- 1 2 DVI_R_TXD0-
DVI_TX0 4 20 33 49 MIC_L D_MIC1_L (26) (17) DVI_TXD0-
DVI_R_TXD0- 6 38 D_MIC1_R R956 0_0402_5%
DVI_TX0# 5 21 34 50 MIC_R D_MIC1_R (26)
7 39 D_GNDA2 R886 1 0_0603_5%
DVI_R_TXD1+ GND 6 22 35 51 GNDA DOCKIN# @ WCM-2012-900T_0805
8 DVI_TX1 DOCK_DT1# 40 DOCKIN# (30)
DVI_R_TXD1- 7 23 36 52 SPDIF
9 DVI_TX1# 24 SPDIF 41 SPDIF (25,26) 4 4 3 3
8 37 53
10 GND GND 42
DVI_R_TXD2+ 9 25 38 54 D_LAN_MDI2+
11 DVI_TX2 LAN_2 43 D_LAN_MDI2+ (23)
DVI_R_TXD2- 10 26 39 55 D_LAN_MDI2-
12 DVI_TX2# LAN_2# 44 D_LAN_MDI2- (23) 1 1 2 2
11 27 40 56
13 GND GND 45
D_CRT_R 12 28 41 57 L58
(16) D_CRT_R 14 VGA_R 13 29 42 58
15 GND
D_CRT_G 14 30 43 59 DVI_TXD0+ DVI_R_TXD0+
(16) D_CRT_G 16 VGA_G GND 46 (17) DVI_TXD0+ 1 2
15 31 44 60 USB20_P8 R957 0_0402_5%
17 GND USB 47 USB20_P8 (20)
D_CRT_B 16 32 45 61 USB20_N8
(16) D_CRT_B 18 VGA_B USB# 48 USB20_N8 (20)
17 62
19 GND USB_EN# 49 SYSON# (28,33,39)
1K_0402_5% 18 P2 P4 63
50
R916 1 19 (66) (68) 64 RESERVED D_CRT_DET# DVI_TXD1- DVI_R_TXD1-
2 VGA_DT# 51 D_CRT_DET# (20) (17) DVI_TXD1- 1 2
20 52 R958 0_0402_5%
D_HPOUT_L DOCK_DT2# LAN_PWR D_LAN_ACTIVITY#
21 53
(26) D_HPOUT_L
(26) D_HPOUT_R
D_HPOUT_R 22
HP_L
HP_R
LAN_ACT
LAN_LINK 54 D_LAN_LINK#
D_LAN_ACTIVITY# (23)
D_LAN_LINK# (23)
2007/12/07 @ WCM-2012-900T_0805
D_HP_PLUG# 23 55 4 3
(25) D_HP_PLUG# D_GNDA HP_DT# GND D_LAN_MDI0+ 4 3
24 GNDA LAN_0 56 D_LAN_MDI0+ (23)
DVI_DET 25 57 D_LAN_MDI0-
(17) DVI_DET DVI_DT LAN_0# D_LAN_MDI0- (23)
DVI_SDATA 26 58 1 2
(17) DVI_SDATA DVI_DCDT GND 1 2
DVI_SCLK 27 59 D_LAN_MDI1+
(17) DVI_SCLK DVI_DDCCK LAN_1 D_LAN_MDI1+ (23) L59
D_VSYNC 28 60 D_LAN_MDI1-
(16) D_VSYNC VGA_VS LAN_1# D_LAN_MDI1- (23)
D_HSYNC 29 61
(16) D_HSYNC VGA_HS GND
D_DDC_CLK 30 62 D_LAN_MDI3+ DVI_TXD1+ 1 2 DVI_R_TXD1+
(16) D_DDC_CLK VGA_DDCCK LAN_3 D_LAN_MDI3+ (23) (17) DVI_TXD1+
D_DDC_DATA 31 63 D_LAN_MDI3- R959 0_0402_5%
(16) D_DDC_DATA VGA_DDCDT LAN_3# D_LAN_MDI3- (23)
32 5V_S0 GND 64
C
+5VS C
69 72 DVI_TXD2- 1 2 DVI_R_TXD2-
GND GND (17) DVI_TXD2-
70 ACER DVR1027 Rev: 0.5 73 R960 0_0402_5%
GND GND
71 GND GND 74
@ WCM-2012-900T_0805
JAE_SP07-10207-22 4 3
CONN@ 4 3

1 1 2 2
L60

DVI_TXD2+ 1 2 DVI_R_TXD2+
(17) DVI_TXD2+
R961 0_0402_5%

EMI

C939 220P_0402_50V7K
2 1 LAN Conn.
JRJ45
R999 2 1 300_0402_5%
12
T104 +3V_LAN Amber LED+
1 24 L_LAN_ACTIVITY# 11
TCT1 MCT1 (23) L_LAN_ACTIVITY# Amber LED-
(23) L_LAN_MDI0+ L_LAN_MDI0+ 2 23 RJ45_MIDI0+ 2 16
B L_LAN_MDI0- TD1+ MX1+ RJ45_MIDI0- C940 RJ45_MIDI3- SHLD2 B
(23) L_LAN_MDI0- 3 TD1- MX1- 22 8 PR4-
4 21 68P_0402_50V8J 15
L_LAN_MDI1+ TCT2 MCT2 RJ45_MIDI1+ RJ45_MIDI3+ SHLD1
(23) L_LAN_MDI1+ 5 TD2+ MX2+ 20 7 PR4+
L_LAN_MDI1- RJ45_MIDI1- 1
(23) L_LAN_MDI1- 6 TD2- MX2- 19
7 18 RJ45_MIDI1- 6
L_LAN_MDI2+ TCT3 MCT3 RJ45_MIDI2+ PR2-
(23) L_LAN_MDI2+ 8 TD3+ MX3+ 17
(23) L_LAN_MDI2- L_LAN_MDI2- 9 16 RJ45_MIDI2- RJ45_MIDI2- 5
TD3- MX3- PR3-
10 TCT4 MCT4 15
(23) L_LAN_MDI3+ L_LAN_MDI3+ 11 14 RJ45_MIDI3+ RJ45_MIDI2+ 4
L_LAN_MDI3- TD4+ MX4+ RJ45_MIDI3- PR3+
(23) L_LAN_MDI3- 12 TD4- MX4- 13
RJ45_MIDI1+ 3
350uH_GSL5009LF PR2+
RJ45_MIDI0- 2 PR1-
SP050003T10 SHLD2 14
RJ45_MIDI0+ 1 PR1+
SHLD1 13
1

L_LAN_LINK# 10
(23) L_LAN_LINK# Green LED-
R902 R903 2 R146 1 300_0402_5% 9
75_0402_1% 75_0402_1% +3V_LAN Green LED+
2
C941 220P_0402_50V7K 2 1 C228 FOX_JM36113-L2R8-7F
2

68P_0402_50V8J RJ45_LANGND 1 2CONN@ LANGND

C942 1 1

2
R904 R905 1 1000P_1206_2KV7K C226 C227
1 1 1 1
C836 C837 C838 C839 75_0402_1% 75_0402_1% R574 0.1U_0402_16V4Z 4.7U_0805_10V4Z
FBMA-L10-160808-301LMT_0603
2

0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2
2 2 2 2
1
RJ45_GND
0.1U_0402_16V4Z 0.1U_0402_16V4Z 40mil EMI
A A

Place close to TCT pin

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 24 of 42
5 4 3 2 1
 A B C D E

HD Audio Codec +VDDA

+AVDD_AC97 +3VS_DVDD

1
L34
L33 1 2 0.1U_0402_16V4Z 680P_0402_50V7K 40mil 0.1U_0402_16V4Z 680P_0402_50V7K 1 2 R586
+VDDA +3VS

2
FBM-L11-160808-800LMT_0603 1 1 1 1 FBM-L11-160808-800LMT_0603 10K_0402_5%
C710 C711 C712 C713 R968 1 10U_0805_10V4Z
C709 20mil 1
0_0805_5%C714
1
C715 C716 C717 C718
1
C719

2
@ @ @
10U_0805_10V4Z 2 2 2 2 @ @ @ 1 2

1
0.1U_0402_16V4Z 100P_0402_50V8J 2 2 2 2 C721 1U_0402_6.3V4Z

1
<BOM Structure>
0.1U_0402_16V4Z 680P_0402_50V7K 100P_0402_50V8J R588
L61 MBK1608121YZF_0603 10K_0402_5%

25

38
EC Beep

9
1 U27 1
1 2 +1.5VS R589
C872 @ C722 1 2 1 2

DVDD
AVDD1

AVDD2

DVDD_IO
(30) BEEP#

2
1 2 1U_0402_6.3V4Z 560_0402_5% C723
@ <BOM Structure> 1 2 MONO_IN

AMP_LEFT 10U_0805_10V4Z 1U_0402_6.3V4Z

14 35
NC LINE_OUT_L AMP_LEFT (26) PCI Beep

1
C 1 Structure>2
<BOM
AMP_RIGHT C724 1 R587 Q55
15 NC LINE_OUT_R 36 AMP_RIGHT (26) (20) SB_SPKR 2 1 2 2
1U_0402_6.3V4Z 560_0402_5% B R590 2.4K_0402_1%
16 39 AMP_LEFT_HP <BOM Structure> E 2SC2411K_SOT23
AMP_LEFT_HP (26)

3
MIC2_L HP_OUT_L
17 41 AMP_RIGHT_HP
MIC2_R HP_OUT_R AMP_RIGHT_HP (26)
C720
LINE_L 2 R928 1 1 2 LINE_C_L 23 45
(26) LINE_L LINE1_L NC
75_0603_1% 4.7U_0805_6.3V6K 268@

1
LINE_R 2 1 1 2 LINE_C_R 24 46 20_0603_5%1 DMIC_CLK D47 @
(26) LINE_R LINE1_R DMIC_CLK
R929 75_0603_1% 4.7U_0805_6.3V6K R591
C725 18 43 R592
CD_L NC 10K_0402_5% RB751V_SOD323
C728
20 44 R59310_0402_5% 10P_0402_50V8J

2
CD_R NC
2 1 1 2
19 CD_GND
C730 6 HDA_BITCLK_CODEC
BIT_CLK HDA_BITCLK_CODEC (19)
MIC1_L 2 R930 1 1 2 MIC1_C_L 21
(26) MIC1_L MIC1_L
75_0603_1% 4.7U_0805_6.3V6K
MIC1_R 2 R931 1 1 2 MIC1_C_R 22 8 1 2
(26) MIC1_R MIC1_R SDATA_IN HDA_SDIN0 (19)
75_0603_1% 4.7U_0805_6.3V6K R594 33_0402_5%
C731 MONO_IN 12 37
PCBEEP MONO_OUT

11
LINE1_VREFO 29 DMIC Conn.
(19) HDA_RST#_CODEC RESET#
GPIO1 31
2 JP41 2
(19) HDA_SYNC_CODEC 10 SYNC
5
MIC1_VREFO_L 28 10mil +MIC1_VREFO_L 6
5
G2
(19) HDA_SDOUT_CODEC SDATA_OUT G1
L35
HDA_GPIO0 2
MIC1_VREFO_R 32 10mil +MIC1_VREFO_R
MBK1608121YZF_0603 DMIC_CLK
4
3
4
HDA_GPIO3 GPIO0 3
3 GPIO3 MIC2_VREFO 30 +3VS 1 2 2 2
SENSE_A DMIC_DATA
SENSE_B
13
34
SENSE A
27 ACZ_VREF 10mil 1 1
SENSE B VREF ACES_85204-04001
1
CODEC_EAPD 47 40 ACZ_JDREF 20K_0402_1% C732 CONN@
(30) CODEC_EAPD EAPD JDREF @

1
SPDIF 48 33 SENSE C 1 10U_0805_10V4Z 0.1U_0402_16V4Z DMIC_DATA
(24,26) SPDIF SPDIFO NC 2
R923 C733 DMIC_CLK
DMIC_DATA 1 2 0_0402_5% DMIC_DATA_R 4
ALC 888 senseR598
26
C 1
C734
1
C735
DVSS1 AVSS1

2
888VC@ 7 42 100P_0402_50V8J 0.1U_0402_16V4Z
DVSS2 AVSS2
2

2 D27

2
R604 R599 ALC888S-VB_LQFP48 2 2
PSOT24C-LF-T7_SOT23-3
0_0603_5% 0_0603_5% SA000026V00
888VB@ 268@ 888VC@
1

1
EMI

R924
R601 2 1 39.2K_0402_1% SENSE_A DMIC_DATA 1 2 HDA_GPIO0
(26) HP_PLUG#
R602 1 2 10K_0402_1% R925 268@ 0_0402_5%
(26) LINEIN_PLUG#
R603 2 1 20K_0402_1% DMIC_CLK 1 2
(24,26) MIC_PLUG#
888VB@ 0_0402_5%
3 DMIC_DATA HDA_GPIO3 3
1 2
R926 888VB@ 0_0402_5%
From Docking DMIC_CLK 1 2
R927 888VC@ FBMA-L10-160808-301LMT_0603
R606 1 2 0_0402_5% HP_PLUG#
(24) D_HP_PLUG#
R607 1 2 0_0402_5% LINEIN_PLUG#
(24) D_LINEIN_PLUG#

Sense Pin Impedance Codec Signals

39.2K PORT-A (PIN 39, 41)

20K PORT-B (PIN 21, 22)

Regulator for CODEC
SENSE A +5VS +5VS_VDDA
Adjustable Output +VDDA
L38
10K PORT-C (PIN 23, 24) U29
1 2 4 5 +VDDA
VIN VOUT

4.7U_0805_10V4Z

2
0.1U_0402_16V4Z

4.7U_0805_10V4Z
5.1K PORT-D (PIN 35, 36) KC FBM-L11-201209-221LMAT_0805 2 6
DELAY SENSE or ADJ

1
R610

0.1U_0402_16V4Z
7 1 69.8K_0603_1%
ERROR CNOISE

R609
39.2K PORT-E (PIN 14, 15) C740 C741
8 3

1
SD GND

0_0402_5% 2
20K PORT-F (PIN 16, 17) SI9182DH-AD_MSOP8
SENSE B

1
SA091820030
10K PORT-G (PIN 43, 44) R611

C742
24K _0402_1%
4 4

C743
5.1K PORT-H (PIN 45, 46) R612

2
(28,30,33,39) SUSP# 2 1
2007/12/07 39.2K CD @
0_0402_5%
1 2
R613 0_0603_5% 20K 1st S/PDIF Out
1
R614
2
@ 0_0805_5%
SENSE C
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title
10K 2nd S/PDIF Out SCHEMATICS,MB A4271
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
5.1K S/PDIF-IN DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 25 of 42
A B C D E
 A B C D E

ACES_88231-04001
APA2057 SPK/HP Amplifier Int. Speaker Conn. 20mil 6
5
GND2
+5VALW INTSPK_R2 R616 0_0603_5% SPK_R- GND1
L39 1 2 4 4
+5VS_VDDA KC FBM-L11-201209-221LMAT_0805 INTSPK_R1 R617 1 2 0_0603_5% SPK_R+ 3
INTSPK_L2 R618 0_0603_5% SPK_L- 3
1 2 1 2 2 2
W=40mil INTSPK_L1 R619 1 2 0_0603_5% SPK_L+ 1 1
1 2
@ JP43

680P_0402_50V7K

10U_0805_10V4Z
0.1U_0402_16V4Z

1U_0402_6.3V4Z
L40 KC FBM-L11-201209-221LMAT_0805 1 2 1
C744 C745 C746 C747 CONN@
+3VALW
@
2 1 2

1 1
R620 1.5K_0402_1%

11

19

20
10

1
1 2 U30
R621 1.5K_0402_1% +5VALW +5VALW

CVDD

HVDD

PVDD
PVDD

VDD
1 2

(25) AMP_RIGHT 1 2 AMP_R 1 2 AMPR 1 R622 2 HP_PLUG#

HP_PLUG# (25)

2
C750 1U_0402_6.3V4Z C748 1U_0402_6.3V4Z 0_0402_5% INR_A 3 22 INTSPK_R1
INR_A ROUT+

2
(25) AMP_LEFT 1 2 AMP_L 1 2 AMPL 1 R624 2 INL_A 5 21 INTSPK_R2 R626
C751 1U_0402_6.3V4Z C749 1U_0402_6.3V4Z 0_0402_5% INL_A ROUT- R625 100K_0402_5%

1
R623 1 AMP_EN#27 INTSPK_L1 D
2 100K_0402_5% /AMP EN LOUT+ 8 100K_0402_5%
100K_0402_5% 9 INTSPK_L2 2

1 1
R627 1 HP_EN LOUT- G
+5VS 2 24

1
HP EN

3
0_0402_5%1 @ 2 R950 HP_R
S D Q38
(30) EC_HP_EN 17 S

3
HP_R G
(25) AMP_RIGHT_HP 1 2 AMP_RHPIN 1 R628 2 INR_H 4 INR_H HP_L 18 HP_L 2 SPDIF_PLUG# 2
C752 4.7U_0805_6.3V6K 39K_0402_5% INL_H 6 G 2N7002_SOT23
INL_H
(25) AMP_LEFT_HP 1 2 AMP_LHPIN 1 R629 2 D Q39 Q40 S

3
C753 4.7U_0805_6.3V6K 39K_0402_5% 26 AO3413_SOT23-3 2N7002_SOT23
VOL_AMP /SD CVSS
CVSS 15 +5VSPDIF
1 2 2 1 AMP_BEEP 28 BEEP
C754 R630 47K_0402_5% 16
EC_MUTE 0.47U_0402_6.3V6K AMP_CP+ 12 CP+
VSS
1 2 AMP_CP- 14 2 1
C755 1U_0603_10V6K CP- GND
23
EC_HP_EN 1 2 AMP_BIAS 25
PGND
7 C757
C756 2.2U_0603_10V6K BIAS PGND
CGND 13
2
1U_0603_10V6K LINE Out/Headphone Out
2 1 GND1 29
C758 0.1U_0402_16V4Z
APA2056_TSSOP28
2007/12/07 S/PDIF Out JACK
30ms SA00001QD00 thermal pad to GND
20mil 2 @
2 2 D60 1
2 +5VALW C759 C760 2
3
IN_A Gain = 10dB (Internal Speaker) C950
330P_0402_50V7K 330P_0402_50V7K 1 2
IN_H Gain = 0dB (Headphone) 1 1 PJDLC05_SOT23~D
JHP1
1

0.1U_0402_16V4Z 6
R631 HP_L 1 2 HPOUT_L_1 1 2 HPOUT_L_2 4
10K_0402_5% R633 56.2_0603_1% L41 FBM-11-160808-700T_0603
HP_R 1 2 HPOUT_R_1 1 2 HPOUT_R_2 1
R634 56.2_0603_1% L42 FBM-11-160808-700T_0603
2

Docking Conn 5
VOL_AMP
R635 56.2_0603_1% SPDIF_PLUG# 7
1

D D_HPOUT_L HP_L
(24) D_HPOUT_L 1 2 +5VSPDIF 3
2

R637 1 2 EC_MUTE EC_MUTE (30) (24) D_HPOUT_R

D_HPOUT_R 1 2 HP_R
(24,25) SPDIF
SPDIF 8
22.6K_0402_1% G R636 56.2_0603_1%
C761 S Q41 1
3

2N7002_SOT23 2
2
0.01U_0402_16V7K C762
1

SINGA_2SJ1533-000111
2
100P_0402_50V8J CONN@

Docking Conn LINE-IN JACK

JLINE1
D_LINE_L R639 1 2 0_0603_5% LINE_L 6
(24) D_LINE_L
D_LINE_R R640 1 2 0_0603_5% LINE_R
(24) D_LINE_R

LINEIN_PLUG# 5
(25) LINEIN_PLUG#
3 3
4
L43 FBM-11-160808-700T_0603
LINE_R 1 2 LINE_R_L 1 2 LINE_R_R 3
(25) LINE_R
R1000 0_0603_5%
LINE_L 1 2 LINE_L_L 1 2 LINE_L_R 2
(25) LINE_L
R1001 0_0603_5% L44 FBM-11-160808-700T_0603 1
1 1
SINGA_2SJ-0960-C01
C763 C764
220P_0402_50V7K 220P_0402_50V7K
Volume Control Circuit +3VS
2 2 CONN@

+3VS Docking Conn

1

C765 D_MIC1_L R656 1 2 0_0603_5% MIC1_L

(24) D_MIC1_L
+3VS 2 1 R642 D_MIC1_R R655 1 2 0_0603_5% MIC1_R
(24) D_MIC1_R
1

100K_0402_5%
R643 R644 0.1U_0402_16V4Z MIC JACK
4

U31 10K_0402_5% 10K_0402_5%

2

+3VS JMIC1
GND

U32 +MIC1_VREFO_L +MIC1_VREFO_R 6

1
2

C766
P

NC

2 1 2 2 4 0.1U_0402_16V4Z
A A Y

1
R646 10K_0402_5%
G

2 MIC_PLUG# 5
(24,25) MIC_PLUG#
1 NC7SZ14P5X_NL_SC70-5 U33 R645 R647
3

COM 2.2K_0402_5% 2.2K_0402_5%

1 CD1# VCC 14 4
2 13

2
D1 CD2# MIC1_R_L MIC2_R_1
B 3 1 2 3 CP1 D2 12 (25) MIC1_R 1 2 1 2 FBM-11-160808-700T_0603 3
R648 10K_0402_5% 4 11 R1002 0_0603_5% L45
SD1# CP2 MIC1_L_L
1 1 5 10 1 2 1 2 FBM-11-160808-700T_0603 MIC2_L_1 2
GND

Q1 SD2# (25) MIC1_L

0.01U_0402_16V7K

0.01U_0402_16V7K

C767 C768 6 09 1 R1003 0_0603_5% L46 1

4 Q1# Q2 4
7 GND Q2# 08 1 1
XRE094PHDINB1-2-12-E-7016_3P C769 SINGA_2SJ-0960-C01
5

2 2 TC74LCX74FT_TSSOP14 C770 C771

0.1U_0402_16V4Z
2 220P_0402_50V7K 220P_0402_50V7K
2 2 CONN@

ENCODER_DIR (30)
SNC00000K00
ENCODER_PULSE (30) Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 26 of 42
A B C D E
 5 4 3 2 1

MDIO PULL HIGH/LOW ?

+3VS +1.8VS_APVDD
40mil
0.1U_0402_16V4Z 0.1U_0402_16V4Z
40mil 0.1U_0402_16V4Z
+3V_MCVCC
1 1 1 1 1 1 1 1 1 1
C840 C841 C842 C843 C844 C845 C846 C847 C848 C867
D XDWP_SDWP 1 2 D
0.1U_0402_16V4Z 0.1U_0402_16V4Z R906 10K_0402_5%
2 2 2 2 2007/12/07 2
10U_0805_10V4Z
2 2 2 2 2
XD_RB 1 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K R907 10K_0402_5%

+3VS

XD_CLE 1 2
U43 R908 10K_0402_5%

3 5 +1.8VS_APVDD XDCD0#_SDCD# 1 2
(15) CLK_PCIE_READER# APCLKN APVDD
4 10 R909 4.7K_0402_5%
(15) CLK_PCIE_READER APCLKP APV18
TAV33 30 +3VS
9 XDCD1#_MSCD# 1 2
(20) PCIE_TXN5 APRXN
8 19 R910 4.7K_0402_5%
(20) PCIE_TXP5 APRXP DV33
DV33 20
(20) PCIE_RXN5 C849 1 2 0.1U_0402_16V7K PCIE_C_RXN5 11 44
C850 1 0.1U_0402_16V7K PCIE_C_RXP5 APTXN DV33
(20) PCIE_RXP5 2 12 APTXP DV18 18 +1.8VS_APVDD
DV18 37
1 2 APREXT 7
8.2K_0402_5% 12mil / <250mil APREXT XD_SD_MS_D0
MDIO0 48
R911 47 XD_SD_MS_D1
MDIO1 XD_SD_MS_D2
+3VS 38 PCIES_EN MDIO2 46
39 45 XD_SD_MS_D3 XD_RE 1 2
PCIES JMB385 MDIO3
MDIO4 43 SDCMD_MSBS_XDWE# 22_0402_5% R912 200K_0402_5%
42 XDCE_SDCLK_MSCLK_R 1 2 XDCE_SDCLK_MSCLK
MDIO5 XDWP_SDWP XD_ALE
MDIO6 41 1 2
40 XD_CLE R963 R913 200K_0402_5%
MDIO7 XD_MMC_D4
MDIO8 29
(7,18,20,22,23) PLT_RST# 1 28 XD_MMC_D5
C XRSTN MDIO9 XD_MMC_D6 C
2 XTEST MDIO10 27
26 XD_MMC_D7
R970 MDIO11 XD_RE
MDIO12 25
(20) CR_CPPE# 1 2 0_0402_5% 13 23 XD_RB
PAD T110 SEECLK SEEDAT MDIO13 XD_ALE
14 SEECLK MDIO14 22

D31 34
CH751H-40PT_SOD323-2 XDCD1#_MSCD# NC
15 CR1_CD1N NC 35
(20) CR_WAKE# 1 2 XDCD0#_SDCD# 16 36
CR1_CD0N NC
+3V_MCVCC 6
APGND

>
2
0
m
i
l
R460 MC_PWREN# 17 D55
CR1_PCTLN XDCD0#_SDCD#
1 2 GND 24 2
0_0805_5% 31 1 XD_CD#
GND XDCD1#_MSCD#
(32) 5IN1_LED# 21 CR1_LEDN GND 32 3
GND 33
DAN202UT106_SC70-3 C851
<BOM Structure>
pin17 is Power switch output in next 270P_0402_50V7K
JMB385-LGEZ0A_LQFP48_7X7
IC version (can cost down power
switch) SA00001W910

(TOP)
JREAD1
B 3 21 B
+3V_MCVCC +3V_MCVCC XD-VCC SD-VCC +3V_MCVCC
MS-VCC 28 +3V_MCVCC
XD_SD_MS_D0 32
XD_SD_MS_D1 XD-D0 XDCE_SDCLK_MSCLK
40mil 10 XD-D1 7 IN 1 CONN SD_CLK 20
XD_SD_MS_D2 9 14 XD_SD_MS_D0
XD_SD_MS_D3 XD-D2 SD-DAT0 XD_SD_MS_D1
8 XD-D3 SD-DAT1 12
1

1 C853 1 C854 1 XD_MMC_D4 7 30 XD_SD_MS_D2

C852 R914 XD_MMC_D5 XD-D4 SD-DAT2 XD_SD_MS_D3
6 XD-D5 SD-DAT3 29
150K_0402_5% XD_MMC_D6 5 27 XD_MMC_D4
0.1U_0402_16V4Z @ XD_MMC_D7 XD-D6 SD-DAT4 XD_MMC_D5
4 XD-D7 SD-DAT5 23
2 2 2 XD_MMC_D6
18
2007/12/07
2

0.1U_0402_16V4Z
10U_0805_10V4Z SDCMD_MSBS_XDWE# SD-DAT6 XD_MMC_D7
34 XD-WE SD-DAT7 16
XDWP_SDWP 33
XD_ALE XD-WP XDCD0#_SDCD#
35 XD-ALE SD-CD 1
XD_CD# 40 2 XDWP_SDWP
XD_RB XD-CD SD-WP SDCMD_MSBS_XDWE#
39 XD-R/B SD-CMD 25
XD_RE 38
XDCE_SDCLK_MSCLK XD-RE XDCE_SDCLK_MSCLK
37 XD-CE MS-SCLK 26
XD_CLE 36 13 SDCMD_MSBS_XDWE#
XD-CLE MS-BS XDCD1#_MSCD#
MS-INS 22

17 XD_SD_MS_D0
MS-DATA0 XD_SD_MS_D1
MS-DATA1 15
11 19 XD_SD_MS_D2
7in1-GND MS-DATA2 XD_SD_MS_D3
31 7in1-GND MS-DATA3 24

41 7in1-GND
42 7in1-GND

TAITW_R015-A10-LM_NR

A A
CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 27 of 42
5 4 3 2 1
 5 4 3 2 1

New Card Power Switch

New Card Socket (Left/TOP)
+3VALW_CARD +3VS_CARD +1.5VS_CARD
Imax = 0.275A Imax = 1.35A Imax = 0.75A JEXP1
+3VS +1.5VS
1 GND
1 1 1 1 1 1 (20) USB20_N1 2 USB_D-
D C435 C439 C369 C370 C436 C437 D
1 1 (20) USB20_P1 3 USB_D+
C375 C374 CP_USB# 4
10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z CPUSB#
5 RSV
10U_0805_10V4Z 10U_0805_10V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 6 RSV
2 2 U24 40mil (15,20,22) ICH_SMBCLK 7 SMB_CLK
+1.5VS 12 1.5Vin 1.5Vout 11 +1.5VS_CARD (15,20,22) ICH_SMBDATA 8 SMB_DATA
14 1.5Vin 1.5Vout 13 +1.5VS_CARD 9 +1.5V
10 +1.5V
60mils (20,22) ICH_PCIE_WAKE# 11 WAKE#
+3VS 2 3.3Vin 3.3Vout 3 +3VS_CARD +3VALW_CARD 12 +3.3VAUX
4 5 PERST1# 13
3.3Vin 3.3Vout PERST#
40mil +3VS
+3VS_CARD 14 +3.3V
+3VALW 17 AUX_IN AUX_OUT 15 +3VALW_CARD 15 +3.3V
R9890_0402_5% CLKREQ1# 16
PCI_RST# CP_PE# 1 CLKREQ#
(18,30) PCI_RST# 6 SYSRST# OC# 19 (20) CP_PE# 2 CP_PE#_R 17 CPPE#
+3VS 1 18
(15) CLK_PCIE_CARD# REFCLK-
SYSON 20 8 PERST1# C438 19
(30,33,38) SYSON SHDN# PERST# (15) CLK_PCIE_CARD REFCLK+
20 GND

1
SUSP# 1 16 0.1U_0402_16V4Z 21
(25,30,33,39) SUSP# STBY# NC 2 (20) PCIE_RXN1 PERn0
R339 22
(20) PCIE_RXP1 PERp0

5
CP_PE# 10 7 10K_0402_5% U15 23
(Internal Pull High to AUXIN) CPPE# GND CLKREQ1# GND
2 24

G Vcc
B (20) PCIE_TXN1 PETn0
CP_USB# 9 4 (20) PCIE_TXP1 25
EXP_CLKREQ# (15)

2
(Internal Pull High to AUXIN) CPUSB# Y PETp0
1 A 26 GND
RCLKEN1 18 RCLKEN

1
D NC7SZ32P5X_NL_SC70-5 27 29

3
R5538D001-TR-F_QFN20_4X4 RCLKEN1 2 Q15 GND1 GND3
28 GND2 GND4 30
<BOM Structure> G 2N7002_SOT23
S SANTA_13181060-5_28P-T

3
CONN@

C C

+5VALW
+USB_VCCA
U26
1 GND OUT 8
C568 0.1U_0402_16V4Z 2 7
IN OUT
2 1 3 IN OUT 6 1
4 EN# FLG 5
R172 C700 +
TPS2061DRG4_SO8
1
100K_0402_5%
2 +3VALW
150U_D2_6.3VM ON BOARD
SYSON# 2
(24,33,39) SYSON#
JUSB1
USB_OC#4 (20)
1 VCC
+5VALW USB20_N4 2
+USB_VCCB (20) USB20_N4 USB20_P4 D-
(20) USB20_P4 3 D+
U37 4 GND
1 GND OUT 8
C569 0.1U_0402_16V4Z 2 7 5
IN OUT USB20_P4 GND1
2 1 3 IN OUT 6 6 GND2
4 5 USB20_N4 7
EN# FLG R206 GND3
8 GND4
TPS2061DRG4_SO8 100K_0402_5%

2
1 2 +3VALW SUYIN_020173MR004G565ZR
SYSON# CONN@
B D17 B
USB_OC#5 (20)
PJDLC05_SOT23~D

1
+USB_VCCB
to small board
+USB_VCCD

JP50
1

USB20_N5
2
3
1
2 to small board
(20) USB20_N5 USB20_P5 3
(20) USB20_P5 4 4
5 5
6 JP51
6
7 7 1 1
8 +5VALW 2
+3VALW 8 +USB_VCCD 2
9 USB20_N0 3
GND U50 (20) USB20_N0 USB20_P0 3
10 GND (20) USB20_P0 4 4
+3VALW 1 8 5
ACES_85201-08051~N C860 0.1U_0402_16V4Z GND OUT USB20_P0 5
2 IN OUT 7 6 6
2 1 3 6 USB20_N0 7
IN OUT GND
CONN@ 4 EN# FLG 5 8 GND
1

R933
right-up

2
R940 TPS2061DRG4_SO8 100K_0402_5% ACES_85201-06051
100K_0402_5% 1 2 +3VALW CONN@
SYSON# D57
A PJDLC05_SOT23~D A
USB_OC#0 (20)
2

USB20_N5
D61
USB20_P5 right-down

1
(30) LID_SW# 2 1
3

CH751H-40PT_SOD323-2
D18
PJDLC05_SOT23~D Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title
SCHEMATICS,MB A4271
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 28 of 42
5 4 3 2 1
 5 4 3 2 1

BIOS
+3VALW

C551 1 2 0.1U_0402_16V4Z
<BOM Structure>

(30) FSEL# U35 H1 H2 H3

+3VALW 4.7K_0402_5% 1 8 H_3P0 H_3P0 H_3P0
R935 1 SPI_WP# CE# VDD R443 1
2 3 WP# SCK 6 2 0_0402_5% SPI_CLK (30)
D R936 1 SPI_HOLD# 7 R445 1 D
2 HOLD# SI 5 2 0_0402_5% FWR# (30)
4.7K_0402_5% 4 2 R442 1 2 0_0402_5% @ @ @
FRD# (30)

1
VSS SO
MX25L8005M2C-15G_SOP8

ENE suggestion SPI Frequency over 66MHz H9

H_2P3
SST: 50MHz
MXIC: 70MHz
@
ST: 40MHz

1
H11 H12
H_2P3 H_2P3

@ @

1
H17 H18 H23 H24 H33
H_3P2 H_3P2 H_3P2 H_6P0 H_6P0

@ @ @ @ @
2007/12/07

1
H19 H20 H21 H22
C H_4P2 H_4P2 H_4P2 H_4P2 C

@ @ @ @

1
reserve VS_ON will be drived by EC
Power ON Circuit H27
H_4P5X6P5N
H28
H_4P0X3P0N
H29
H_3P0X8P0N
H30
H_3P0X8P0N
+3VS

+3VALW +3VALW @ @ @ @

1
1

U45A U45B H31 H34 H36

R917 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 H_3P0N H_4P0X3P0N H_3P0N
14

14

180K_0402_5%
D56 @
P

P
2

1 2 1 2 3 4 SYS_PWROK 1 2 @ @ @
(30,40) VR_ON PM_PWROK (20,30)

1
I O I O R918 @ 0_0402_5%
G

CH751H-40PT_SOD323-2 2
@
For South Bridge
7

C855
1U_0402_6.3V4Z
1
@
FD1 FD2 FD3 FD4

B +3VALW @ @ @ @ B

1
+3VALW +3VALW
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
1

R919 FD5 FD6

22K_0402_5% U45C U45D
14

14

SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
@ @
P

P
2

1
5 I O 6 9 I O 8 1 2 VS_ON (38)
2 R920 FIDUCIAL_C40M80 FIDUCIAL_C40M80
1

D C856 0_0402_5%
SUSP 2
For +VCCP
(33,39) SUSP
7

G
Q57 S 1
3

2N7002_SOT23
0.1U_0402_16V4Z

+3VALW 0.1U_0402_16V4Z
C857
1 2 +3VALW

U45E U45F
14

14

SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
P

11 I O 10 13 I O 12
G

G
7

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 29 of 42
5 4 3 2 1
 +3VALW_EC
+3VALW_EC

1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K
1 1 1 1 1
Ra
R450
C446 C447 C448 C449 C450 +3VALW +3VALW_EC +EC_AVCC 100K_0402_5%

2
2 2 2 2 2 R451 M/B_ID
0.1U_0402_16V4Z 1000P_0402_50V7K 1 2 Rb

1
0_0805_5% 1
C451 R452
0_0402_5%

111
125
+5VALW +3VS 0.1U_0402_16V4Z

22
33
96

67
9
U18 2

2
SMB_EC_DA1 R453 1 2 4.7K_0402_5%

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
SMB_EC_CK1 R454 1 2 4.7K_0402_5% VCC 3.3V+/-5%
SMB_EC_DA2 R455 1 2 4.7K_0402_5%
SMB_EC_CK2 R456 1 2 4.7K_0402_5% Ra 100K+/-5%
GATEA20 1 21 INV_PWM
(19) GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INV_PWM (17)
KB_RST# 2 23 BEEP# Board ID Rb V AD_BID min V AD_BID typ V AD_BID max
(19) KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# (25)
SIRQ 3 26 ENCODER_DIR
(20) SIRQ SERIRQ# FANPWM1/GPIO12 ENCODER_DIR (26)
@ LPC_FRAME# 4 27 ACOFF 0 0 0V 0V 0V
(19) LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF (37)
C452 @ R457 (19) LPC_AD3 LPC_AD3 5 0.01U_0402_16V7K
LPC_AD2 LAD3 C453 ECAGND
1 2 1 2 (19) LPC_AD2 7 LAD2 PWM Output 1 2 1 8.2K+/-5% 0.216V 0.250V 0.289V
33_0402_5% (19) LPC_AD1 LPC_AD1 8 63 BATT_TEMP
LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP (35)
15P_0402_50V8J LPC_AD0 BATT_OVP
(19) LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
BATT_OVP (37) 2 18K+/-5% 0.436V 0.503V 0.538V
ADP_I/AD2/GPIO3A 65 ADP_I (37)
CLK_PCI_EC 12 AD Input 66 M/B_ID 3 33K+/-5% 0.712V 0.819V 0.875V
(15) CLK_PCI_EC PCICLK AD3/GPIO3B
PCI_RST# 13 75
R458 1 (18,28) PCI_RST# ECRST# PCIRST#/GPIO05 AD4/GPIO42
+3VALW 2 37 ECRST# SELIO2#/AD5/GPIO43 76 PGD_IN (40) 4 56K+/-5% 1.036V 1.185V 1.264V
1 2 47K_0402_5% EC_SCI# 20
0.1U_0402_16V4Z (20) EC_SCI# SCI#/GPIO0E
38 CLKRUN#/GPIO1D 5 100K+/-5% 1.453V 1.650V 1.759V
C454 1 2 PM_CLKRUN#_R 68 DAC_BRIG
(20) PM_CLKRUN# DAC_BRIG/DA0/GPIO3C DAC_BRIG (17)
R943 0_0402_5% 70 EN_FAN1 6 200K+/-5% 1.935V 2.200V 2.341V
EN_DFAN1/DA1/GPIO3D EN_FAN1 (4)
DA Output 71 IREF
IREF/DA2/GPIO3E IREF (37)
KSI0 55 72 7 NC 2.500V 3.300V 3.300V
KSI0/GPIO30 DA3/GPIO3F Calibrate# (37)
KSI1 56
KSI2 KSI1/GPIO31
57 KSI2/GPIO32
KSI3 58 83 EC_MUTE
KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE (26)
KSI4 59 84 EC_HP_EN
KSI4/GPIO34 PSDAT1/GPIO4B EC_HP_EN (26)
KSI5 60 85 DOCKIN# +5VS
KSI5/GPIO35 PSCLK2/GPIO4C DOCKIN# (24)
KSI6 61 PS2 Interface 86 BT_LED#
KSI6/GPIO36 PSDAT2/GPIO4D BT_LED# (31,32)
KSI7 62 87 TP_CLK TP_CLK R462 1 2 4.7K_0402_5%
KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA TP_CLK (31)
39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA (31)
KSO1 40 3S/4S# TP_DATA R463 1 2 4.7K_0402_5%
KSO1/GPIO21 3S/4S# (37)
KSO2 41 4.7K_0402_5%
KSO3 KSO2/GPIO22 R465 1 R585
42 KSO3/GPIO23 SDICS#/GPXOA00 97 2 select SPI ROM or LPC ROM
KSO4 43 98 65W90W#
KSO4/GPIO24 SDICLK/GPXOA01 65W90W# (37)
KSO5 DOCKIN#
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99 EC_DOCKIN# (16,23) 1 2 +3VALW
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 E-KEY_BTN# (32)
KSO7 46 SPI Device Interface 10K_0402_5%
KSO8 KSO7/GPIO27
47 KSO8/GPIO28
KSO9 48 119 FRD# R948
KSO9/GPIO29 SPIDI/RD# FRD# (29)
KSO10 49 120 FWR# E-KEY_BTN# 1 2 +3VALW
KSO10/GPIO2A SPIDO/WR# FWR# (29)
KSO11 50 SPI Flash ROM 126 SPI_CLK
KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK (29)
KSO12 51 128 FSEL# 10K_0402_5%
KSO12/GPIO2C SPICS# FSEL# (29)
KSO13 52
KSO14 KSO13/GPIO2D
53
KSO15 54
KSO14/GPIO2E
KSO15/GPIO2F CIR_RX/GPIO40 73 2007/12/07 C861 100P_0402_50V8J
81 74 ENCODER_PULSE BATT_OVP 2 1
KSO16/GPIO48 CIR_RLC_TX/GPIO41 ENCODER_PULSE (26)
82 89 C862 100P_0402_50V8J
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG (37)
90 ACIN 2 1
BATT_CHGI_LED#/GPIO52 BATT_GRN_LED# (32)
91 CAPS_LED#
SMB_EC_CK1 CAPS_LED#/GPIO53 CAPS_LED# (32)
(35) SMB_EC_CK1 77 SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54 92 BATT_AMB_LED# (32)
SMB_EC_DA1 78 93
(35) SMB_EC_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PWR_LED (32)
SMB_EC_CK2 79 SM Bus 95 SYSON
(4) SMB_EC_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON (28,33,38)
SMB_EC_DA2 80 121 VR_ON
(4) SMB_EC_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON (29,40)
ACIN
AC_IN/GPIO59 127
2
ACIN
1
(20,32,34,37) For EMI
R473 R469 10K_0402_5% CP1
1 2 EC_PME# SLP_S3# 6 100 EC_RSMRST# KSI0 1 8
(23) EC_LAN_PME# (20) SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# (20)
0_0402_5% SLP_S5# 14 101 KSI1 2 7
(20) SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# (20)
EC_SMI# 15 102 EC_ON KSI2 3 6
(20) EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON (31)
LID_SW# 16 103 KSO0 4 5
(28) LID_SW# LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SWI# (20)
17 104 PM_PWROK
SUSP#/GPIO0B ICH_PWROK/GPXO06 BKOFF# PM_PWROK (20,29) 100P_1206_8P4C_50V8
18 PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08 105 BKOFF# (17)
EC_PME# 19 GPIO 106 WL_OFF# CP2
EC_PME#/GPIO0D WL_OFF#/GPXO09 WL_OFF# (22) KSO1
(7) MCH_TSATN_EC# 25 EC_THERM#/GPIO11 GPXO10 107 HPD_7318_R_EC (17) 1 8
28 108 KSO2 2 7
(4) FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11 HPD_7318_EC (17)
BT_ON# 29 KSI3 3 6
(31) BT_ON# FANFB2/GPIO15
UTX 30 KSO3 4 5
(22) UTX URX EC_TX/GPIO16 SLP_S4#
31 110
(22) URX
(31) ON/OFF
ON/OFF 32
EC_RX/GPIO17
ON_OFF/GPIO18
PM_SLP_S4#/GPXID1
ENBKL/GPXID2 112 ENABLT
SLP_S4# (20)
ENABLT (9)
2007/12/07 100P_1206_8P4C_50V8
PWR_SUSP_LED34 114
(32) PWR_SUSP_LED PWR_LED#/GPIO19 GPXID3 CODEC_EAPD (25)
NUM_LED# 36 GPI 115 THERM_SCI# CP3
(32) NUM_LED# NUMLED#/GPIO1A GPXID4 THERM_SCI# (20)
116 SUSP# KSO4 1 8
EC DEBUG port C455 GPXID5
117 PWRBTN_OUT#
SUSP# (25,28,33,39) ACES_85202-24051 KSO5 2 7
GPXID6 PWRBTN_OUT# (20)
CONN@ 15P_0402_50V8J 118 KSI0 KSO6 3 6
GPXID7 ARCADE# (32) 1
JP26 1 2 CRY2 122 KSI1 KSO7 4 5
XCLK1 (32) KSI1 2
1 123 124 KSI2
1 +3VALW XCLK0 V18R (32) KSI2 3
2 URX 1 KSO0 100P_1206_8P4C_50V8
2 Y5 4
1

AGND

3 UTX KSO1 CP4

GND
GND
GND
GND
GND

3 (32) KSO1 5
4 2 1 @ C478 KSO2 KSO8 1 8
4 NC IN R476 KSI3 6 KSI4
4.7U_0805_6.3V6K (32) KSI3 7 2 7
ACES_85205-0400 20M_0402_5% KB926QFB0_LQFP128_14X14 2 KSO3 KSO9
3 4 3 6
11
24
35
94
113

69

NC OUT SA00001J540 KSO4 8 KSI5 4 5

2

32.768KHZ_12.5P_MC-306 KSO5 9
KSO6 10 100P_1206_8P4C_50V8
CRY1 KSO7 11
1 2
+3VALW_EC For KB926 C0 reversion KSO8 12 CP5
C456 KSI4 13 KSI6 1 8
ECAGND

(32) KSI4 14
15P_0402_50V8J KSO9 KSO10 2 7
15
1

KSI5 KSO11 3 6
+EC_AVCC L21 KSI6 16 KSI7
17 4 5
0_0603_5% KSO10
KSO11 18 100P_1206_8P4C_50V8
L22 KSI7 19 CP6
2

KSO12 20 KSO12
1 2 1 2 21 1 8
C457 0.1U_0402_16V4Z 0_0603_5% KSO13 KSO13 2 7
<BOM Structure> KSO14 22 KSO14
23 3 6
<BOM Structure> <BOM Structure> KSO15 KSO15 4 5
24
100P_1206_8P4C_50V8
JP24 CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 30 of 42
 A B C D E

Power Button pin1

+3VALW
pin1
TOP Side
1 2
R578 @ 10K_0603_5%

2
+3VALW
1 2 R580
R579 @ 10K_0603_5% 1
1 100K_0402_5% @ C705 1
20mil
ON/OFF switch Bottom Side JP39 1 2 +1.5V

1
D44 R969 0_0402_5% 1U_0603_10V4Z
2
2 ON/OFF (30) 1 GND1 RES0 2 1 2
ON/OFFBTN# 1 3 4 R962 0_0402_5%
(32) ON/OFFBTN# (19) HDA_SDOUT_MDC IAC_SDATA_OUT RES1
3 51ON# 5 6
51ON# (32,34) GND2 3.3V +3VALW
(19) HDA_SYNC_MDC 7 IAC_SYNC GND3 8
DAN202UT106_SC70-3 (19) HDA_SDIN1 1 2 HDA_SDIN1_MDC 9 10
R583 33_0402_5% IAC_SDATA_IN GND4
(19) HDA_RST_MDC# 11 IAC_RESET# IAC_BITCLK 12 HDA_BITCLK_MDC (19)

1
R584

GND
GND
GND
GND
GND
GND
1
2 0_0402_5%
C704 D45
ACES_88018-124G

13
14
15
16
17
18

2
1000P_0402_50V7K RLZ20A_LL34 SP01000AT00 CONN@ 1
1
HDA MDC Conn. C706

2
Connector for MDC Rev1.5
22P_0402_50V8J
2

1
D
EC_ON 2 Q36
(30) EC_ON
G
2

S 2N7002_SOT23

3
R581

10K_0402_5%
1

+3VS

2 2
Finger Print Conn
1
USB20_N6 +3V_FP C698 C699
USB20_P6 0.1U_0402_16V4Z
@ 1U_0603_10V4Z

3
2
S
+3VS R1005 1 2 0_0603_5%
3

G
Q33
D26
EMI R1006 1 2 0_0603_5%
(30) BT_ON# 1
R575
2
10K_0402_5%
2
AO3413_SOT23
+3VALW
PSOT24C-LF-T7_SOT23-3
D

1
W=40mils
BT +BT_VCC
1

+3V_FP

CONN@ 1

1
C702 C703
ACES_85201-04051 R576
1 4.7U_0805_10V4Z 300_0603_5%
USB20_N6 1 2 0.1U_0402_16V4Z
(20) USB20_N6 2 2
USB20_P6 3
(20) USB20_P6

2
3
4 4
5 G1

1
D
6 G2
2 Q34
JP44 G 2N7002_SOT23
S

3
T/P Board TP_DATA
TP_CLK
BT_LED# (30,32)

R577
3

1
3 D 3
+5VS D25 1 2 2 Q35 +BT_VCC
+BT_VCC
PSOT24C-LF-T7_SOT23-3 G 2N7002_SOT23
10K_0402_5% S @ JP37

3
1 1 GND 9
@ 2
1

2
(20) USB20_P2 3 3
1 @ (20) USB20_N2 4 4
C459 5 5
(22) WLAN_BT_DATA 1 2 WLAN_BT_DATA_R 6 6
0.1U_0402_16V4Z R996
1 @ 0_0402_5%
2 WLAN_BT_CLK_R 7
2 (22) WLAN_BT_CLK 7
JP47 R997@ 0_0402_5% 8 10
8 GND
1 1
2 TP_CLK (30) ACES_87213-0800G
2
3 3 TP_DATA (30) CONN@
4 BTN_L
4 BTN_R
5 5
6 6
GND 7 1 1
8 @ @
GND C460 C461 USB20_P2
ACES_85201-06051 100P_0402_50V8J 100P_0402_50V8J USB20_N2
2 2
CONN@

2
D62
Left Right PJDLC05_SOT23~D

SW3 SW4

1
EVQPLHA15_4P EVQPLHA15_4P
BTN_L 3 1 BTN_R 3 1
4 4
4 2 4 2
5
6

5
6

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 31 of 42
A B C D E
 5 4 3 2 1

TO S/W B LED & E-BTN/B

+3VS +5VS +3VS

JP12
TO POWER BTN/B

5
U38
1 MINI1_LED# SATA_LED#
2

P
2 MINI1_LED# (22) B SATA_LED# (19)
MEDIA_LED# 4
3 BT_LED# Y +3VALW +5VS +5VALW
4 BT_LED# (30,31) A 1 5IN1_LED# (27)

G
ARCADE_BTN#
5 KSO1 NC7SZ08P5X_NL_SC70-5 JP45
KSO1 (30)

3
6 KSI1
7 KSI1 (30) 1 1
D KSI2 +5VS 2 PWR_SUSP_LED# D
8 KSI2 (30) 2
KSI3 KSI3 (30) 3
9 KSI4 3 PWR_LED#
10 KSI4 (30) 4 4
JP46 5
11 5 ACIN_LED#
12 1 1 6 6
2 2 NUM_LED# (30) 7 7 ON/OFFBTN# (31)
ACES_85201-1205 3 8 2N7002_SOT23
3 CAPS_LED# (30) 8

1
MEDIA_LED# D
CONN@ 4 4 GND 9 1
1 2 +3VALW 5 E-KEY_BTN# 10 C951 Q59 2
5 E-KEY_BTN# (30) GND ACIN (20,30,34,37)
R459 100K_0402_5% 6 0.1U_0402_16V4Z G
D19 6 ACES_85201-08051~N
7 1 S

3
GND C952 2
KSO1 ARCADE_BTN# 1
2 ARCADE# (30) GND 8
0.1U_0402_16V4Z CONN@
KSI1 WL_BTN# 3 51ON# ACES_85201-06051
51ON# (31,34) 2
CONN@
KSI2 BT_BTN# DAN202UT106_SC70-3

KSI3 EMAIL_BTN#
KSI4 IE_BTN#

C C

PWR_LED# PWR_SUSP_LED#
1

Q42 Q43
DTC114EKA_SC59-3 DTC114EKA_SC59-3
10K 10K
(30) PWR_LED 2 (30) PWR_SUSP_LED 2
10K 10K
3

HT-210UD/NB_AMB/BLUE
300_0402_5% R446
NB 2 1 2 PWR_LED#
B B

+5VALW 1
300_0402_5% R447
UD
3 1 2 PWR_SUSP_LED#

LED1

SC510UDB000

HT-210UD/UYG AMB/GREEN R448

120_0402_5%
2 1 2 BATT_GRN_LED# +5VS
NB
BATT_GRN_LED# (30)
JP53
+3VALW 1 1 1
R449 2 2
UD
3 1 2 BATT_AMB_LED# BATT_AMB_LED# (30)
150_0402_5%
3 G1
LED2 4 G2
SC510UDG000 ACES_88266-02001
CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 32 of 42

5 4 3 2 1
 5 4 3 2 1

+5VALW to +5VS Transfer

+3VALW to +3VS Transfer
+5VALW +5VS +3VALW
+3VS
U20 0.1U_0402_16V4Z U21 0.1U_0402_16V4Z
8 D S 1 8 D S 1
C644 1 7 2 1 7 2
+VSB 10U_0805_10V4Z D S +VSB C637 D S
6 D S 3 1 1 6 D S 3 1 1
5 4 10U_0805_10V4Z 5 4 C648 C649
1 D G C645 C646 D G

1
D 2 SI4800DY_SO8 10U_0805_10V4Z 2 SI4800DY_SO8 10U_0805_10V4Z D
R546 2 2 R548 2 2
200K_0402_5% 330K_0402_5%
2

2
RUNON +3VS_GATE R549 1 2 RUNON
@ 0_0402_5%
1 1
1

1
D C647 D C650
SUSP 2 Q27 0.1U_0603_25V7K SUSP 2 Q28 0.1U_0603_25V7K
G G
2N7002_SOT23 2 2N7002_SOT23 2
S S
3

3
+1.8V

+5VALW

1
@
C 0_0805_5% C
1
C931 R984
@ 1U_0402_6.3V6K

2
2
6

U53

1
5 @C932
@ C932
VCNTL

VIN 4.7U_0805_6.3V6K
7 POK
4

2
R985 VOUT

VOUT 3 +1.5V
@ 10K_0402_1%

22U_0805_6.3V6M
1 2 8 EN FB 2

1
(28,30,38) SYSON

C934
GND
1

9 R986 C933

2
VIN
1

R987 @ 1.54K_0402_1% @ 0.01U_0402_25V7K

2
C935 @47K_0402_5% @ APL5915KAI-TRL_SO8
1

@ 0.1U_0402_16V7K 2
2

@
R988
@ 1.74K_0402_1%
2

B B

+5VALW

+5VALW

1
R544
Discharge circuit

1
47K_0402_5% R545

2
10K_0402_5%
(24,28,39) SYSON# SYSON#

2
+5VS +3VS +1.8V +1.5VS +VCCP +0.9VS SUSP
(29,39) SUSP

1
D D
1

2 2 Q26
(28,30,38) SYSON (25,28,30,39) SUSP#
R498 R499 R500 R501 R502 R503 G G
2N7002_SOT23

2
Q49 S S

3
470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% R532 2N7002_SOT23 R547
100K_0402_5%
2

10K_0402_5%

1
6

Q9A Q9B Q10A Q10B Q11A Q11B

SUSP 2 SUSP 5 SYSON# 2 SUSP 5 SUSP 2 SUSP 5

1

2N7002DW T/R7_SOT363-6 2N7002DW T/R7_SOT363-6 2N7002DW T/R7_SOT363-6 2N7002DW T/R7_SOT363-6 2N7002DW T/R7_SOT363-6 2N7002DW T/R7_SOT363-6
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401556 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 29, 2008 Sheet 33 of 42
5 4 3 2 1
 A B C D

PDS1040-13_POWERDI5-3

PD11
VIN
SP020710240 VIN_DOCK
2
1
1 3 1

PR1
1M_0402_1%
1 2
SINGA_B2011H02-4P_4P-T PL1
SMB3025500YA_2P PJ1 VIN VS VIN
DC_IN_S1 1 2DC_IN_S2 2 1
2 1

1
1 1

1000P_0402_50V7K

4700P_0402_25V7K

390P_0402_50V7K

820P_0402_50V7K
JUMP_43X79 PR2 PR3

1000P_0402_50V7K

330P_0402_50V7K
100P_0402_50V8J
10K_0402_5% 84.5K_0402_1%

PC139
100P_0402_50V8J
2 PR5
2

8
PC96

PC3

PC107

PC150

PC151
PD2 22K_0402_5%

2
1

1
RB751V-40TE17_SOD323-2 3 1 2

P
+

PC2

PC4
3 PC1 1 2 2 1 1 0
3 (20,30,32,37) ACIN

20K_0402_1%
1000P_0402_50V7K 2

2
-

1
G

PR6
PR4 PU1A

1
PR7

PC5
0.1U_0603_25V7K
4 10K_0402_5% LM358DT_SO8 PC6

4
4 PD3 1000P_0402_50V7K

2
GLZ4.3B_LL34-2

2
10K_0402_5%
2

2
PJP1

1 2 RTCVREF
PR8
10K_0402_5%

2 2

Vin Dectector
Min. Typ Max.
H-->L 16.976V 17.525V 17.728V
L-->H 17.430V 17.901V 18.384V

PJ2 PJ3
VIN 2 1 2 1
+3VALWP 2 1 +3VALW +1.8VP 2 1 +1.8V
JUMP_43X118 JUMP_43X118
2

PD4
LL4148_LL34-2
LL4148_LL34-2
PJ4 PJ15
1

PD5 +5VALWP 2 1 +5VALW 2 1

2 1 2 1
BATT+ 2 1
1

3 3

JUMP_43X118 JUMP_43X118
PR9 PR10
PQ1 68_1206_5% 68_1206_5%
TP0610K-T1-E3_SOT23-3
PR11
PJ6
2

200_0603_5% PJ5
CHGRTCP 1 2 N1 3 1 VS +VSBP 2 1 +VSB +0.9VSP 2 1 +0.9VS
2 1 2 1
JUMP_43X39 JUMP_43X79
1

PC8
PR12 0.1U_0603_25V7K
100K_0402_1% PC7
2

PJ8
2

0.22U_0603_25V7K +1.05VP 2 1 +VCCP

2 1
(31,32) 51ON# 1 2
PR13 JUMP_43X118
22K_0402_1%
PJ9
2 2 1 1
RTCVREF JUMP_43X118
1

PR14
200_0603_5%
PR15 PR16 PU2 G920AT24U_SOT89-3
560_0603_5% 560_0603_5% 3.3V
2

1 2 1 2 3 2 N2
+CHGRTC OUT IN
1

GND
4
PC9 PC10 4

10U_0805_10V4Z 1
2

1U_0805_25V4Z

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401556
Date: Tuesday, April 29, 2008 Sheet 34 of 42
A B C D
 A B C D

PH1 under CPU botten side :

CPU thermal protection at 82 degree C
Recovery at 56 degree C
VL
VL
VL
VMB

2
PL2 PR17

1
1 1
OCTEK_TBTJ-0710019 SMB3025500YA_2P 47K_0402_1%
8 GND 7 7 BATT_S1 1 2 BATT+ PH1 PC11
MAINPWON (36)
9 6 100K_0603_1%_TH11-4H104FT 0.1U_0603_25V7K PR18

1
GND 6 47K_0402_1%
10 GND 5 5

1
11 4 EC_SMCA 1 2

2
GND 4 EC_SMDA PC12 PC13 PR19 PQ2
3 3

8
2 1000P_0402_50V7K 0.01U_0402_25V7K 7.5K_0402_1% PU3A DTC115EUA_SC70-3

2
2 PD6
1 1 2 3

P
1 +
O 1 2 1 2
PJP2 TM_REF1 2 -

G
LL4148_LL34-2
LM393DG_SO8

3
0.22U_0603_16V7K

17.4K_0402_1%
2

1
PC14

1000P_0402_50V7K
PR22
PR21 PR20
100_0402_1% 100_0402_1% 2 1 VL

1
PR24

PC15
6.49K_0402_1% PR23
1

2
2 1 100K_0402_1%
+3VALWP

1
1

PR25
PR26 100K_0402_1%
1K_0402_1%

2
2

2 2

BATT_TEMP (30)

SMB_EC_CK1 (30)

PH2 near main Battery CONN :

SMB_EC_DA1 (30)
BAT. thermal protection at 92 degree C
Recovery at 56 degree C
VL

2
@ PR27
@PR27
VL 47K_0402_1%
@PR28
@ PR28
47K_0402_1%

1
1 2

1
PQ3
TP0610K-T1-E3_SOT23-3
@PH2
@ PH2
100K_0603_1%_TH11-4H104FT VL
B+ 3 1 +VSBP

2
100K_0402_1%

0.22U_1206_25V7K

0.1U_0603_25V7K

@PR30
@ PR30
1

8
13.7K_0402_1% PU3B
1

1
PR29

PC16

PC17

1 2 5 @PD7
@ PD7

P
+
O 7 2 1
@ TM_REF1 6
2

G
3 3

PR31 LL4148_LL34-2
2

1
22K_0402_1% LM393DG_SO8

4
VL 1 2 @ PC18
@PC18 @ PR32
@PR32
@ 0.22U_0603_16V7K 15.4K_0402_1%

2
2

PR33
100K_0402_1%

PR34
1

0_0402_5% D
1 2 2 PQ4
(36) SPOK
G 2N7002W-T/R7_SOT323-3
0.1U_0402_16V7K

S
3
1

PC19
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401556
Date: Tuesday, April 29, 2008 Sheet 35 of 42
A B C D
 5 4 3 2 1

ISL6237_B+
ISL6237_B+
B+
PJ10 PR35
JUMP_43X118 0_0805_5%
2 2 1 1 1 2
D D

2200P_0402_50V7K

1800P_0402_50V7K

390P_0402_50V7K
4.7U_1206_25V6K

4.7U_1206_25V6K
1800P_0402_50V7K

390P_0402_50V7K

2200P_0402_50V7K

4.7U_1206_25V6K

4.7U_1206_25V6K
1

5
6
7
8
PC20

PC21

8
7
6
5

1
PC99

PC22

PC25

PC97

PC98
PC100
VL

PC23

PC24
2

1U_0603_10V6K
PQ6

2
2
PQ5 PC26 AO4466_SO8

4.7U_0603_6.3V6M
AO4466_SO8 0.1U_0603_25V7K 4

1
PC27
4

PC28
1
+5VALWP

3
2
1
PL3

1
2
3
PL4 10UH_1164AY-100M=P3_4.7A_20%

7
10UH_1164AY-100M=P3_4.7A_20% PU4 PC29 2 1
1 2 1U_0603_10V6K

LDO
VIN

VCC
+3VALWP 33 19 1 2
TP PVCC

5
6
7
8

1
4.7_1206_5%
1

8
7
6
5
4.7_1206_5%

PR37
DH3 26 15 DH5
UGATE2 UGATE1

PR36
PR38 PR39 PQ8
0_0402_5%

PQ7 2 1 BST3A 24 17 BST5A 2 1 AO4712_SO8

BOOT2 BOOT1
2

1 AO4712_SO8 2.2_0603_5%

2
2

2
PR40

61.9K_0402_1%
2.2_0603_5% PC32 4

2
+ PC30 4 PC31

2
680P_0603_50V7K
220U_6.3V_M 0.1U_0603_25V7K 0.1U_0603_25V7K

1
1
680P_0603_50V7K

PR41
LX3 25 16 LX5 1
1

2 PHASE2 PHASE1

PC33

PC34
3
2
1

2
C + PC35 C

1
2
3
DL3 23 18 DL5 220U_6.3V_M

1
LGATE2 LGATE1
2
10K_0402_1%
2

PGND 22

2
PR42

FB3 30 OUT2

10K_0402_1%
PR43
OUT1 10
VL 32
1

@ REFIN2

1
11 FB5
2VREF_ISL6237 FB1

1 2 1 REF
PC36 0.22U_0603_10V7K
BYP 9
8 LDOREFIN @ PR44 0_0402_5%
SKIP 29 2 1 VL
PR45 0_0402_5%
1 2
20 NC POK2 28
PR46
PD8 100K_0402_1%
1 2 1 2 4 13 PR48
SPOK (35)
VS EN_LDO POK1
2
200K_0402_5%

GLZ5.1B_LL34-2 287K_0402_1%
2

B B
PR47

PC37 14 12 ILM1 2 1
EN1 ILIM1
2

0.22U_0603_25V7K
PR49
1

PQ33 27 31 ILIM2 2 1

GND
TON
1

EN2 ILIM2

NC
2

TP0610K-T1-E3_SOT23-3 2 287K_0402_1%

0_0402_5%
@ PR50 ISL6237IRZ-T_QFN32_5X5

21
1 3 VL 0_0402_5%
806K_0603_1%

PR51
2

1
PR52

2VREF_ISL6237 1

2
1U_0402_6.3V6K
PR55
PC103

@ 47K_0402_5% PR53
PR54 0_0402_5%
+5VALWP Ipeak=8.444A ; Imax=5.91A
1

(35) MAINPWON
2 1 1 2
2VREF_ISL6237 2
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Vlimit=(5E-06 * 330K)/10=165mV
0.047U_0402_16V7-K

0.047U_0402_16V7K

0_0402_5%
2

Ilimit=165mV/18m ~ 165mV/15m
1

PD12
PC38

1SS355_SOD323-2
+3.3VALWP Ipeak=8.444A ; Imax=5.91A =9.167A ~ 11A
PC39
2

Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) Iocp=Ilimit+Delta I/2

1

Vlimit=(5E-06 * 330K)/10=165mV =10.147A ~ 11.980A

Ilimit=165mV/18m ~ 165mV/15m VS @ Delta I=1.96A (Freq=400KHz)
=9.167A ~ 11A
A Iocp=Ilimit+Delta I/2 A

=10.134A ~ 11.967A
Delta I=1.934A (Freq=300KHz)
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401556
Date: Wednesday, April 30, 2008 Sheet 36 of 42
5 4 3 2 1
 A B C D

B+
PQ9 PQ10
AO4407_SO8 AO4407_SO8 PR56
VIN 8 1 1 8 0.015_2512_1%
7 2 2 7 PJ11

3.3_1210_5%

0.01U_0402_25V7K
6 3 3 6 1 4 2 1 CHG_B+
2 1

1
1800P_0402_50V7K
5 5

2
2200P_0402_25V7K

390P_0402_50V7K

PC40
4.7U_1206_25V6K

4.7U_1206_25V6K
0.018U_0603_50V7J
2 3 JUMP_43X118 PR57
CHGEN#

PR58

PC159
0.01U_0603_50V7K
100K_0402_1%

2
PC41

0.01U_0402_25V7K

1
2

100K_0402_1%

PC42

PC43

PC44

PC152

PC153
1 2

2
1
PC46 PC49

1
2

5
6
7
8

3
2
1
1 1

PC45

PR59
3.3_1210_5%
0.1U_0402_16V7K PU5 0.1U_0603_25V7K

1
PR166
1 2 1 28 PVCC 1 2 PQ12
CHGEN PVCC AO4407_SO8

1
PR60 /BATDRV 4

2
PC47 @PC50
@PC50 2.2_0603_5% PQ11

2
0.1U_0603_25V7K 0.1U_0603_25V7K 27 BTST 1 2 4 AO4466_SO8

2
BTST

2
1
PR61

1
340K_0402_1% ACN 2 26 DH_CHG
@PD9
@ PD9 PC48 ACP ACN HIDRV
3

3
2
1

5
6
7
8
RLZ24B_LL34 2.2U_0805_25V6K ACP PR62
2

1
ACDRV 4 25 LX_CHG PL5 0.02_2512_1%
2

ACDET ACDRV PH 10UH_PCMB104T-100MS_6A_20% BATT+

5 ACDET
2 1 1 2 1 2 1 4

10U_1206_25V6M

10U_1206_25V6M
PD10 PC51 2 3

2
LL4148_LL34-2 0.1U_0603_25V7K

REGN

5
6
7
8

PC53
PR63 PR64

PC52
24751_VREF CELLS GND 3 Cell 54.9K_0402_1% ACSET 6 4.7_1206_5%
ACSET
24

2
REGN
VREF 4 Cell
1
2

1
PC54 PQ13
PR65 @ 1U_0603_10V6K 4 AO4466_SO8 PC56

1
100K_0402_1% PR66 680P_0402_50V7K

2
2

0_0402_5%
1 2 1 2 7 ACOP
1

2
PR67 PC55 23 DL_CHG

3
2
1
340K_0402_1% 0.47U_0603_16V7K LODRV
CELLS
1

PGND 22
OVPSET 8 PC57
OVPSET
1

2 D 0.1U_0402_16V7K 2

2 3S/4S# (30) 1 2
G 9 21 ACOFF (30)
AGND LEARN
2

S
3

1
PQ14 PR68 PC58 @ PC59
@PC59
@ 2N7002W-T/R7_SOT323-3 54.9K_0402_1% 0.1U_0603_25V7K 0.1U_0603_25V7K
24751_VREF 20 CELLS

2
SI2301BDS-T1-E3_SOT23-3 CELLS
1

24751_VREF 10
Cells selector PQ15 VREF
1

PC60

1U_0603_10V6K
PR69
100K_0402_1% 19 SE_CHG+

2
SRP
CP Point Setting PQ15_GATE 2 11 18 SE_CHG-
2

VDAC SRN
CP point=Iadapter*85% BAT 17
1

1
90W adapter PC62 VADJ 12
0.1U_0603_25V7K VADJ PC61
Vacset=3.3*(100K/(64.9K+100K))=2.001V
2

ACSET 0.1U_0603_25V7K

2
CP Point=(Vacset/Vvdac)*(0.1/PR56)=4.04A ACGOOD# 29 Icharge Setting
TP
13 ACGOOD ICHG setting For 2200mA, Icharge=0.8C=0.8*2*2.2=3.52A
65W adapter R=(100K*100K)/(100K+100K)=50K PR71 For 2400mA, Icharge=0.8C=0.8*2.4*2=3.84A
16 SRSET 2 1 Icharge=(Vsrset/Vdac)*(0.1/PR62)
Vacset=3.3*(50K/(50K+64.9K))=1.436V 24751_VREF 24751_VREF /BATDRV 14
SRSET IREF (30) IREF*(100k/(100K+17.4K)/3.3)*(0.1/0.02)=Icharge
BATDRV 17.4K_0402_1%

1
200K_0402_1%

PR72
IREF=0.77484*Icharge
1

1
100K_0402_1%

CP POINT=(1.436V/3.3V)*(0.1/0.015)=2.901A 10_0603_5% PR73

1

PR196

PQ15_GATE 15 1 2 100K_0402_1% PC63

IADAPT
PR194

@0.01U_0402_25V7K

2
BQ24751ARHDR_QFN28_5X5 24751_VREF
Input OVP : 22.3V

2
1

3 3
D PQ39
2

1
Input UVP : 17.26V 2 SSM3K7002F_SC59-3
2

2
0.1U_0402_16V7K G PC64 RTCVREF
1

PC168 D 100P_0402_50V8J
Fsw : 300KHz S
3

2
ACOFF 1 2 2 VMB @PR75
@ PR75

1
G PQ40 PR70 100K_0402_1%
S SSM3K7002F_SC59-3 VS
3

1
1

1
340K_0402_1%

ADP_I (30) 100K_0402_1%

PR195

@PR167
@ PR167 ACIN (20,30,32,34)
0.01U_0402_25V7K

PR74 0_0402_5%

1
340K_0402_1% 24751_VREF D
1 2
ACGOOD# 2 @ PQ16
2

2
1

1
PC65

G 2N7002W-T/R7_SOT323-3
PR78 S

3
1

887K_0402_1%
2

PR76 PQ17
LM358DT_SO8 499K_0402_1% SI2301BDS-T1-E3_SOT23-3 PR80 24751_VREF

2
0_0402_5%
8

S
PR77 PU1B REGN VADJ

D
3 1 1 2
2

2
10K_0402_1% 5
P

(30) BATT_OVP +
105K_0402_1%

PR81
1 2 7 0 LI-4S :18.0V----BATT-OVP=2.677V
1

1
0.01U_0402_25V7K

G
6 100K_0402_1%

2
-
1
G

PR79

PR83 PR82
BATT-OVP=0.1487*VMB

1
PC66

64.9K_0402_1% 100K_0402_1%
4

1
24751_VREF 1 ACSET @PR168
@ PR168 PR84 CHGEN#
2 LI-3S :13.5V----BATT-OVP=2.007V
2

4.3K_0402_5% 221K_0402_1%
2

2
BATT-OVP=0.1487*VMB
1

1
PQ18 D

2
Per cell=3.5V (30) FSTCHG 2

1
PR85 D G 2N7002W-T/R7_SOT323-3
100K_0402_1% 2 PQ19 S

3
(30) Calibrate#
1

4
G 2N7002W-T/R7_SOT323-3 4
2

PR86 S

3
100K_0402_1%
1

D
2 Charger ADJ Calibrate# PR78 PR84
2

(30) 65W90W# G
S
3

PQ20 4.0V L @ 0
2N7002W-T/R7_SOT323-3 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title
4.1V L 887K 221K SCHEMATICS,MB A4271
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
CP setting 4.2V H @ @
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401556
Date: Tuesday, April 29, 2008 Sheet 37 of 42
A B C D
 A B C D

PC67 PC68

1
1U_0402_6.3V6K 1U_0402_6.3V6K

2
2.2_0603_1%
PR87 PR88
1 +5VALW 2 1 1 2 +5VALW 1

2.2_0603_1%
PL6

B+ 1 2 ISL6228_B+

1
FBMA-L11-322513-151LMA50T_1210 PC69 PC70
0.1U_0603_25V7K 0.1U_0603_25V7K
1

1
PC137

2
330P_0402_50V7K PC138
2200P_0402_25V7K ISL6228_B+ 2 1 2 1 ISL6228_B+
2

2
PR89 PR90
10_0603_1% 10_0603_1%

1000P_0402_50V7K
2

2
PR92

1
PC73
PC72 PR91 18.2K_0402_1%
PR93 1000P_0402_50V7K 22K_0402_1%
PC71 PR94 22.6K_0402_1%

1
1000P_0402_25V8J 3.3K_0402_5%
2 1 1 2

1
2 1 FB1_1.8V
29

PGOOD1

FSET1

VIN1

VCC1

VCC2

VIN2

FSET2
PR95 GND_T

2
45.3K_0402_1%
PR96
2
1 2 8 28 PR97 PR98 PC74 2

FB1 PGOOD2 34K_0402_1% 3.3K_0402_5% 1000P_0402_25V8J

12K_0402_1% 2 1 1 2

1
ISL6228_B+
PR99
9 27 FB2_1.05V 1 2
VO1 FB2
1800P_0402_50V7K

390P_0402_50V7K
PC157

PC156

PC75

PC76
4.7U_1206_25V6K

4.7U_1206_25V6K

25.5K_0402_1%
1

8
7
6
5

PC77 PR100
0.015U_0402_16V7K 10 26 1 2
2

PQ21 OCSET1 VO2

1 2
AO4466_SO8 12K_0402_1%
2

4
PR101 1.8V_EN 11 25
12K_0402_1% PR102 EN1 PU6 OCSET2
1 2 ISL6228_B+
1

ISL6228HRTZ-T_QFN28_4X4
1
2
3

0_0603_5%

390P_0402_50V7K

1800P_0402_50V7K
PC154

PC155
+1.8VP 1 2 LX_1.8V 12 24 1.05V_EN PC79
PHASE1 EN2
1

PC78

PC81
4.7U_1206_25V6K

4.7U_1206_25V6K
PL7 0.015U_0402_16V7K

5
6
7
8

1
1.8UH_SIL104R-1R8PF_9.5A_30%
8
7
6
5

1 1 2
PR103

2
PC80 + 4.7_1206_5% PQ22 UG_1.8V 13 23
2

UGATE1 PHASE2

2
330U_4V_M AO4712_SO8
OS-CON 4 PR104
2 PR106 12K_0402_1%
4
1

0_0603_5% PQ23
PC82 2 1 2 1BST_1.8V
14 22 UG_1.05V 1 2 AO4466_SO8

1
470P_0402_50V7K BOOT1 UGATE2
2

3
2
1
3 3
LGATE1

LGATE2
PC83 PR105 LX_1.05V 1 2
PGND1

PGND2

BOOT2
PVCC1

PVCC2
+1.05VP
1
2
3

1
0.1U_0402_16V7K 2.2_0603_5% PL8

5
6
7
8
PR107 1.8UH_SIL104R-1R8PF_9.5A_30%
4.7_1206_5% 1
15

16

17

18

19

20

21
+ PC84

2
330U_4V_M
4 PQ24 OS-CON

1
BST_1.05V1 AO4712_SO8 PC87 2
+5VALW 2 1 2
+5VALW 470P_0402_50V7K
2

PR109 PC85

2
2

PC88 2.2_0603_5% 0.1U_0402_16V7K

3
2
1
1U_0402_6.3V6K PC89
1

1U_0402_6.3V6K
1

LG_1.8V LG_1.05V

1.05VP Ipeak=8.8A ; Imax=6.16A

DCR=10m ohm (max)
Rocset=(Iocp*DCR)/10E-06=12K ohm
PR108
1.8VP Ipeak=9.45A ; Imax=6.615A 0_0402_5% Iocp=12A
DCR=10m ohm (max) (28,30,33) SYSON 2 1 1.8V_EN
(29) VS_ON 2 1 1.05V_EN Csen=L/(Rocset*DCR)=0.015uF
Rocset=(Iocp*DCR)/10E-06=12K ohm
0.01U_0402_25V7K

PR110
1

1
PC86

0_0402_5%
Iocp=12A PC90 Freq=366KHz
Csen=L/(Rocset*DCR)=0.015uF 0.01U_0402_25V7K Rfset=1/(1.5E-10 * Freq)=18.2K
2

4 4
@

Freq=303KHz
@
Rfset=1/(1.5E-10 * Freq)=22K
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401556
Date: Wednesday, April 30, 2008 Sheet 38 of 42
A B C D
 5 4 3 2 1

D D

+1.8V

1
PJ12

1
JUMP_43X79

2
PU7

2
1 VIN VCNTL 6 +3VALW
2 GND NC 5

1
1
PC91 3 7 PC92
4.7U_0603_6.3V6M PR111 REFEN NC 1U_0402_6.3V6K

2
1K_0402_1% 4 8
VOUT NC
9

2
GND
RT9173DPSP_SO8

0.1U_0402_16V7K
PR112 PQ25
+0.9VSP

1
0_0402_5% 2N7002W-T/R7_SOT323-3 D PR113

PC93
(29,33) SUSP 1 2 2 1K_0402_1%

1
G

2
1
(24,28,33) SYSON# 1 2 S PC95

2
PR169 PC94 10U_0805_6.3V6M

2
0_0402_5%
0.1U_0402_16V7K

2
C C
@

+5VALW

1
+1.8V PC141
1U_0402_6.3V6K

2
1
PJ18

1
JUMP_43X79
PU11

2
6 VCNTL
5 3 +1.5VS

2
B VIN VOUT B
9 VIN VOUT 4

22U_0805_6.3V6M
8 EN

PC142
7 2 PR171 PC140

GND
POK FB

1
PC143 1.54K_0402_1% 0.01U_0402_25V7K

2
4.7U_0805_6.3V6K

2
APL5913-KAC-TRL_SO8

1
PR172
1.74K_0402_1%

2
PR170

10K_0402_1%
1 2
(25,28,30,33) SUSP#

1
1
PC144 PR184
1U_0402_6.3V6K 47K_0402_5%

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401556
Date: Wednesday, April 30, 2008 Sheet 39 of 42

5 4 3 2 1
 5 4 3 2 1

+5VS

B+
CPU_B+

2
PL9

(5)

(5)

(5)

(5)

(5)

(5)

(5)
CPU_VID6

CPU_VID5
CPU_VID4

CPU_VID3

CPU_VID2

CPU_VID1

CPU_VID0
PR117 FBMA-L18-453215-900LMA90T_1812

(29,30)
VR_ON
1_0603_5%
2 1

390P_0402_50V7K

2200P_0402_50V7K

1800P_0402_50V7K

4700P_0603_50V7K

1000P_0402_50V7K

1800P_0402_50V7K

390P_0402_50V7K

2200P_0402_50V7K
10U_1206_25V6M

10U_1206_25V6M
1

1
PC104

PC105
PR118 499_0402_1% + PC108
D D

PC145

PC106

PC135

PC136

PC109

PC158

PC146

PC147
(7,20) DPRSLPVR 1 2 PC102 220U_25V_M
PC101 2.2U_0603_6.3V6K

2
5
PR119 0_0402_5% 0.022U_0402_16V7K 2

2
(5,7,19) H_DPRSTP# 1 2

PR120 0_0402_5%
1 2 PQ27

1
1

PR122 0_0402_5%

PR123 0_0402_5%

PR124 0_0402_5%

PR125 0_0402_5%
CLK_ENABLE#

PR121 0_0402_5%

PR127 0_0402_5%

PR128 0_0402_5%

PR129 0_0402_5%
4
PR126 0_0402_5%
+3VS 1 2 SI7686DP-T1-E3_SO8
+3VS 2.2_0603_1%

3
2
1
1

2
1.91K_0402_1%

1U_0402_6.3V6K
0.22U_0603_10V7K UGATE_CPU1-2

PC110
PR130 PC111 0.36UH_FDU1040D-R36M_26A_20%

1
1 21 2 2 1 +VCC_CORE

2
2

PR132
PR131

5
6
7
8

1
10K_0402_1%
6.8_1206_5%

3.65K_0805_1%
PL10

5
6
7
8

1
PR134

PR135

PR136
499_0402_1% PQ29

49

48

47

46

45

44

43

42

41

40

39

38

37
BOOT_CPU1
1 2 AO4456_SO8 PR137
2

1_0402_5%

3V3

CLK_EN#

DPRSTP#

VID6

VID5

VID4

VID3

VID2

VID1

VID0
GND

DPRSLPVR

VR_ON
1

PR133 2.2_0603_1% PQ28 PR138

1 2

2
680P_0402_50V7K
1 36 AO4456_SO8 4 @0_0603_5%

2
(7,20) VGATE PGOOD BOOT1
4 1 2

PC112
(5) H_PSI# 1 2 2 35 UGATE_CPU1-1 VSUM PC113
PR139 0_0402_5% PSI# UGATE1
1 2

2
(30) PGD_IN 1 2 3 34 PHASE_CPU1 VCC_PRM

3
2
1
@ 0_0402_5% PMON PHASE1 ISEN1

3
2
1
PR140 1 2 4 33 0.22U_0603_10V7K
PR141 147K_0402_1% RBIAS PGND1
VR_TT# 5 32 LGATE_CPU1 CPU_B+
VR_TT# LGATE1

2200P_0402_50V7K

1800P_0402_50V7K
5
C C

390P_0402_50V7K
6 NTC PVCC 31

10U_1206_25V6M

10U_1206_25V6M
ISL6262ACRZ-T_QFN48_7X7

1
7 30 LGATE_CPU2
SOFT LGATE2

PC114

PC115

PC116

PC148

PC149
PU9 PQ30
PC117 8 29

2
0.022U_0603_25V7K OCSET PGND2
4
1 2 9 28 PHASE_CPU2 SI7686DP-T1-E3_SO8
VW PHASE2 PR142
PR143 13K_0402_1% 10 27 UGATE_CPU2-1 1 2 UGATE_CPU2-2
COMP UGATE2 2.2_0603_1% 0.36UH_FDU1040D-R36M_26A_20%
1 2

3
2
1
11 26 BOOT_CPU2
1 2 1 2 2 1
FB BOOT2 PR144 PL11
1 2

1
6.8_1206_5%
PC118 1000P_0402_50V7K 2.2_0603_1% PC119
DROOP

12 FB2 NC 25

1
VDIFF

ISEN2

ISEN1
VSUM

10K_0402_1%
PR146
VSEN

3.65K_0805_1%
PR145 6.81K_0402_1% 0.22U_0603_10V7K
GND

VDD
RTN

DFB

5
6
7
8

5
6
7
8

1
VIN

PR147
PR148
VO

1 2

PR149
PQ31 PQ32
1 2 AO4456_SO8 AO4456_SO8
13

14

15

16

17

18

19

20

21

22

23

24

1 2
1_0402_5%

2
PC120 1000P_0402_50V7K

2
680P_0402_50V7K
PC121
ISEN1 4 4 PR151 @0_0603_5%
ISEN2 1 2

2
PR153 2

@ 0_0402_5%

PR152 97.6K_0402_1% PC122 1 2 +5VS

2 PR154 1
1K_0402_1%

1 2 2 1 VSUM PC124
1

PR150 1_0603_5% 1 2

3
2
1

3
2
1
470P_0402_50V7K PC123
1 2 1U_0402_6.3V4Z
1

0.22U_0603_10V7K
PC125 220P_0402_50V7K VCC_PRM
PR156 ISEN2
255_0402_1% PC126 1000P_0402_50V7K 10_0603_5%
1 2 1 2 1 2 CPU_B+
B B
1

PR155 1 2 PC127
0.1U_0603_25V7K
PR157 1K_0402_1%
2

PC128 820P_0603_50V7K
(5) VCCSENSE 1 2 1 2
VSUM
1

PR158 0_0402_5%
1

2.61K_0402_1%

PC129 PC130
PR160

+VCC_CORE 1 2 @0.022U_0603_50V7K 0.01U_0603_50V7K

2

PR159 20_0402_5%
(5) VSSSENSE 1 2
2
1

11K_0402_1%

PC131 180P_0402_50V8J
2

PR163

PR161 0_0402_5% 1 2
2

PR162 PR165 10KB_0603_5%_ERTJ1VR103J

20_0402_5% 1 2 1 2 PH3
3.24K_0402_1%
2

PR164 1K_0402_1%
1

VCC_PRM

PC132 0.1U_0402_16V7K
1 2

2 1
PC134 2 1
0.22U_0603_10V7K PC133 0.22U_0402_6.3V6K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4271
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401556
Date: Wednesday, April 30, 2008 Sheet 40 of 42
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 2

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

D Exchange battery connector pin Use wrong model 35 Swap pin definition of PJP2 2007 EVT D

1 12/12

2007
2 For 2nd source of ISL6237 36 Add PC103 SE107105M80(S CER CAP 1U 6.3V M
X5R 0603) on pin 5 of PU4
12/12 EVT
2007
3 Some risk in heavy load 37 Change PL5 to SH000005Z80(S COIL 10UH +-20%
PCMB104T-100MS 6A)
12/12 EVT
2007
4 For EN function of PU4 36 Add PD12 SC100001K00(S DIO 1SS355 SOD323 T/R-5K)
on pin 3 of PQ33 to VS
12/12 EVT
2007
5 Down size 36 Change PC38 from 0603 to 0402(SE076473K80) 12/12 EVT
2007
6 Down size 34 Change PC7 from 1206 to 0603(SE000005Z80) 12/12 EVT
2007
7 Down size 37 Change PC49 from 0805 to 0603(SE042104K80) 12/12 EVT
2007
8 Down size 36 Change PC28 from 0805 to 0603(SE107475M80) 12/12 EVT
C C

2007
9 Down size 39 Change PC91 from 0805 to 0603(SE107475M80) 12/12 EVT
2007
10 Down size 39 Change PC96 from 0805 to 0603(SE107475M80) 12/12 EVT
2007
11 Down size 39 Change PC92 from 0603 to 0402(SE000000K80) 12/12 EVT
2007
12 Down size 39 Change PC97 from 0603 to 0402(SE000000K80) 12/12 EVT
2007
13 Down size 40 Change PC110 from 0603 to 0402(SE000000K80) 12/12 EVT
2007
14 Down size 35 Change PC14 from 0805 to 0603(SE026224K80) 12/12 EVT
2007
15 Down size 35 Change PC18 from 0805 to 0603(SE026224K80) 12/12 EVT
B B
2007
16 For EMI 34 Add PC107 SE075472K80(S CER CAP 4700P 25V K X7R 0402)
from VIN to GND
12/12 EVT
2007
17 For EMI 34 Add PC139 SE074331K80(S CER CAP 330P 50V K X7R 0402)
from VIN to GND
12/12 EVT
2007
18 For EMI 40 Add PC135 SE074182K80(S CER CAP 1800P 50V K X7R 0402)
from CPU_B+ to GND
12/12 EVT
2007
19 For EMI 40 Add PC136 SE025472K80(S CER CAP 4700P 50V K X7R 0603)
from B+ to GND
12/12 EVT
2007
20 For EMI 38 Add PR103 SD001470B80(S RES 1/4W 4.7 +-5% 1206)
from pin 12 of PU6 to PC82
12/12 EVT
2007
21 For EMI 38 Add PC82 SE074471K80(S CER CAP 470P 50V K X7R 0402)
from PR103 to GND
12/12 EVT
2007
22 For EMI 38 Add PR107 SD001470B80(S RES 1/4W 4.7 +-5% 1206)
from pin 23 of PU6 to PC82
12/12 EVT
A 2007 A

23 For EMI 38 Add PC87 SE074471K80(S CER CAP 470P 50V K X7R 0402)
from PR107 to GND
12/12 EVT

Compal Electronics, Inc.

Title
SCHEMATICS,MB A4271
Size Document Number Rev
401556 B

Date: Tuesday, April 29, 2008 Sheet 41 of 42

5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 2

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

D For more current 34 Change PD11 in SCS00002F00(S SCH DIO PDS1040-13 2007 EVT D

24 POWERDI5) 12/12

2007
25 Space is not enough 34 Delete PD1 12/18 EVT
2007
26 37 Change PR70 Pin 1 to RTCVREF 12/18 EVT
2007
27 Down size 37 Change PC56 from 0603 to 0402(SE074681K80) 12/18 EVT
2007
28 Down size 40 Change PC112 from 0603 to 0402(SE074681K80) 12/18 EVT
2007
29 Down size 40 Change PC121 from 0603 to 0402(SE074681K80) 12/18 EVT
2007
30 Down size 36 Change PC103 from 0603 to 0402(SE000000K80) 12/18 EVT
2007
31 Down size 40 Change PC128 from 0603 to 0402(SE000003W00) 12/20 EVT
C C

2007
32 APL5913 EN pin impedance must keep For APL5913 EN risk 39 Change PR184 from 47K to 20K(SD028200280) 12/31 EVT
under 20K
2008
33 Improve 3V/5V OCP 36 Change PR48、PR49 from 330K to 287K(SD000005D80) 02/25 DVT
Change PL3、PL4 from 4.7uH to 10uH(SH000008R80)
2008
34 Improve Load line 40 Change PR165 from 4.42K to 3.24K(SD034324180) 02/25 DVT
2008
35 For EMI 34 Add PC96 1000pF(SE074102K80) 02/25 DVT
2008
36 For EMI Add PC97、PC98、PC99、PC100、PC145、PC146、PC147、PC148、PC149、 02/27 DVT
PC150、PC151、PC152、PC153、PC154、PC155、PC156、PC157
Delete PR64、PC56 "@" mark
Change PR38、PR39、PR60、PR105、PR109、PR130、PR144 from 0 to 2.2
37
2008
38 Prevent ACOP issue 37 Add PC168、PQ39、PQ40、PR194、PR195、PR196 02/27 DVT
B B
2008
39 HW request 39 Change PC144 to 1uF , delete PR184 "@" mark 02/27 DVT
2008
40 For EMI Add PC158、PC159 03/03 DVT
2008
41 Thermal request 35 Change PR19 from 13.7K to 7.5K (SD034750180) 03/14 PVT1
Change PR22 from 15.4K to 17.4K (SD034174280)

42

43

44

45
A A

46

Compal Electronics, Inc.

Title
SCHEMATICS,MB A4271
Size Document Number Rev
401556 B

Date: Tuesday, April 29, 2008 Sheet 42 of 42

5 4 3 2 1