Compal La-H782p R1a

A B C D E
Compal Confidential
Model Name : Dopey_KL/Sleepy_KL/Taurus_KL
Compal Project Name : EH7L1/EH5L1/FH5T1
1
File Name : LA-H782P 1
2
Compal Confidential 2
EH7L1/EH5L1 MB Schematic Document

LA-H782P
3 3
Rev: 1.A
2019.05.13
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/12/11 Deciphered Date 2019/12/11 Title
Vinafix.com Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH7L1 LA-H782P
Date: Tuesday, May 14, 2019 Sheet 1 of 47
A B C D E
A B C D E
HDMI Conn. eDP Interleaved Memory
DDR4-ON BOARD 4G 8Gbx16
page 19
page 22 page 21 Memory BUS
1
DDI1 Dual Channel 1
260pin DDR4-SO-DIMM X1
HDMI x 4 lanes
eDP Intel Kabylake U 1.2V DDR4 2133/2400
DDI page 20
Kabylake U USB 2.0
Kabylake PCH-LP(MCP) USB 3.0 CMOS
conn x1 conn x2
(KBL-U_2+2) USB3 port 1
USB2 port2 Camera
USB2 Port3 on SUB/B USB2 port 7
(KBL-RU_4+2) USB2 port 1
(KBL-U_23E Fuse Down)

page 24 (Reserved PCIE 3.0 x4)
(Port 9-12, 8GT/s)
Processor
SATA3.0
6.0 Gb/s Flexible IO Dual Core + GT2
2
port 12 Base-U PCIE2.0 Quad Core + GT2 2
(SATA2) Premium-U PCIE3.0

page 27 page 28 page 22
SATA3.0 SATA3.0 USBx8 48MHz

NGFF PCIe 1.0 PCIe 1.0 6.0 Gb/s 6.0 Gb/s
WLAN 2.5GT/s 2.5GT/s port 7 port 8
USB2 port 5 port 6 port 5 (SATA0) (SATA1) HD Audio 3.3V 24MHz
page 24 Touch
LAN(GbE) SATA HDD SATA CDROM 15W Screen
Realtek 8111H Conn. Conn. HDA Codec
1356pin BGA USB2 port 6
page 25
page 07~18 SPI ALC255page 25 page 22
RJ45 conn. LPC/eSPI BUS

3
SPI ROM 3
page 26
page 26
CLK=24MHz 64Mb page 9
ENE
Fan Control KB9022 Int. Speaker Int. DMIC UAJ
page 31 page 29
on Camera
page 25 page 25 page 25
RTC CKT. Touch Pad
page 15 Sub Board PS2 (from EC) / I2C (from SOC)
Int.KBD USB2 port 8 (FP)
LS-H781P IO/B
Power On/Off CKT. page 28
page 30
LSH783P HS/B page 30 page 30
page 31
4 DC/DC Interface CKT. 4
page 32 LSH784P ODD/B

page 26
Power Circuit DC/DC
Vinafix.com
Block Diagrams
page 31~44 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Date: Monday, May 13, 2019 Sheet 2 of 47
A B C D E
A B C D E
Board ID Table for AD channel

Vcc 3.3V +/- 5%
Ra 100K +/- 1% Power State
Board ID Rb V BID min V BID typ V BID max EC AD3 PCB Revision SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
0 0 0 V 0 V 0.300 V 0x00 - 0x13
1 12K +/- 1% 0.347 V 0.345 V 0.360 V 0x14 - 0x1E S0 (Full ON) HIGH HIGH HIGH ON ON ON ON
2 15K +/- 1% 0.423 V 0.430 V 0.438 V 0x1F - 0x25 0.1(DVT) S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
1
3 20K +/- 1% 0.541 V 0.550 V 0.559 V 0x26 - 0x30 1.0(PVT) 1
4 27K +/- 1% 0.691 V 0.702 V 0.713 V 0x31 - 0x3A 1.A(MP) S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
5 33K +/- 1% 0.807 V 0.819 V 0.831 V 0x3B - 0x45 S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
6 43K +/- 1% 0.978 V 0.992 V 1.006 V 0x46 - 0x54
7 56K +/- 1% 1.169 V 1.185 V 1.200 V 0x55 - 0x64
14 270K +/- 1% 2.395 V 2.408 V 2.421 V 0xB8 - 0xBF
Voltage Rails
Power Plane Description S0 S3 S4/S5
+19V_VIN Adapter power supply N/A N/A N/A
BOM Structure Table
+17.4V_BATT Battery power supply N/A N/A N/A
+19VB AC or battery power rail for power circuit. N/A N/A N/A
BOM Option Table
+VCC_CORE Processor IA Cores Power Rail ON OFF OFF
Item BOM Structure +VCC_GT ON OFF OFF
Processor Graphics Power Rails
Unpop @ +VCC_SA System Agent power rail ON OFF OFF
Connector CONN@ +0.6VS_VTT DDR +0.6VS power rail for DDR terminator . ON OFF OFF
Acer BYOC BYOC@ / NBYOC@ +1.0VALW_PRIM +1.0V Always power rail ON ON ON*1
CODEC(ALC255/256) 255@/256@ +1.0V_VCCSTU Sustain voltage for processor in Standby modes ON ON OFF
EC Mode Select LPC@ / ESPI@ +VCCIO CPU IO power rail ON OFF OFF
2 For Intel CMC CMC@ +1.0VS_VCCSTG +1.0VALW_PRIM Gated version of VCCST ON OFF OFF
2
EMI requirement EMI@ / @EMI@ +1.2V_VDDQ DDR4 +1.2V Power Rail ON ON OFF
ESD requirement ESD@ / @ESD@ +1.8VALW_PRIM +1.8V Always power rail ON ON ON*1
RF requirement @RF@ +1.8VS System +1.8V power rail ON OFF OFF
CPU Selection U42@/U22@ +3VLP +19VB to +3VLP power rail for suspend power ON ON ON
ODD Support ODD@ +3VALW System +3VALW always on power rail ON ON ON*1
G Sensor BA@ +3VS System +3V power rail ON OFF OFF
TPM TPM@ / NTPM@ +5VALW +5V Always power rail ON ON ON
Finger Print FP@/FPEMC@ +5VS System +5V power rail ON OFF OFF
UMA or DGPU UMA@/VGA@ +RTCVCC RTC Battery Power ON ON ON
Intel Modern Standby MSB@/NMSB@
MB Stage EVT@/DVT@/PVT@/MP@
X76H4G@/X76M4G@/
Memory Select X76S4G@
Memory Mode SDP@ / DDP@

BOM Select 15@/15DIS@
3 3
Note : ON*1 means power plane is ON only when WOL enable and RTC wake at BIOS setting, otherwise it is OFF.
ON*2 power plane is ON when DGPU turn on
43 level BOM table

43 Level Description BOM Structure
431AI4BOL03 SMT MB AH782 EH5L1 I370U23E HDMI U22@/CMC@/LPC@/NRD@/NBYOC@/255@/MP@/MEM@/NMSB@/NTPM@/UMADAZ1A@/X76M@/X4EUMA@/UMA@/15@/EH5L1@/SR3N6@
431AI4BOL04 SMT MB AH782 EH5L1 I370U22 HDMI U22@/CMC@/LPC@/NRD@/NBYOC@/255@/MP@/MEM@/NMSB@/NTPM@/UMADAZ1A@/X76M@/X4EUMA@/UMA@/15@/EH5L1@/SR3TK@
431AI4BOL54 SMT MB AH782 EH7L1 I370U23E HDMI U22@/CMC@/LPC@/RD@/NBYOC@/255@/MP@/MEM@/NMSB@/NTPM@/ODD@/UMADAZ1A@/X76M@/X4EUMA@/UMA@/EH7L1@/SR3N6@
431AI4BOL55 SMT MB AH782 EH7L1 I370U22 HDMI U22@/CMC@/LPC@/RD@/NBYOC@/255@/MP@/MEM@/NMSB@/NTPM@/ODD@/UMADAZ1A@/X76M@/X4EUMA@/UMA@/EH7L1@/SR3TK@
4 4

Vinafix.com Issued Date 2018/12/11 Deciphered Date 2018/11/04 Title
Notes List
A B C D E
A B C D E
DRVEN_CPU RT9610CGQW PR9001 (For U42) +VCC_GTX_VCORE

(PUZ2) +VCC_CORE
PR9002 (For U42)

RT9610CGQW +VCC_GT_VCORE
(PUZ3) For U42
PR9003 (For U22)
RT9610CGQW +VCC_GT
(PUG1)
PR9005 (For U23FD)
RT9610CGQW
(PUA1) +VCC_SA
R-Short
PR9004 (For U23FD) +VCC_GTX_GT (RX8) +TS_PWR
ADAPTER
1
SYSON JUMP JUMP R-Short AP2330W 1
+1.2VP (PJM3) +1.2V_VDDQ (JPC1,JPC2) +1.2V_VDDQ_CPU (RC208) +1.2V_VDDQC (UY1) +HDMI_5V_OUT

RT8207PGQW
SM_PG_CTRL (PUM1) JUMP R-0ohm R-Short
+0.6VSP (PJM4) +0.6VS_VTT (RC274) +1.2V_VCCSFR_OC (RO3) +5VS_HDD
BATTERY +19VB
EN_VCCSTG_VCCPLL_OC UC11 R-Short
(For Modern standby) (RO2) +5VS_ODD
5V_3V_EN SY8288CRAC JUMP SUSP# EM5209VF JUMP JUMP
(PU501) +5VALWP (PJ501) +5VALW (UQ1) +5VS_OUT (JPQ2) +5VS (JPA1) +VDDA
R-Short
CHARGER USB_EN (RF1) +VCC_FAN1
SY6288C20AAC
(US22) +USB3_VCCA
KBL_EN SY6288C20AAC
(U1) +5VS_BL
LDO
+3VLP
R-Short
(RC197) +3VALW_1.8VALW_PGPPA
3V_EN SY8288CRAC JUMP R-Short R-Short
(PU301) +3VALWP (PJ301) +3VALW (RC173) +3VALW_DSW (RC161) +3VALW_PGPPB
JUMP R-Short
(JPC7) +3VALW_PRIM (RC163) +3VALW_PGPPC
SYSON G9661MF11U JUMP R-Short
2 (PUM2) +2.5VP (PJM5) +2.5V (RC172) +3VALW_1.8VALW_PGPPD 2
0 ohm
R-Short
(RC167) +3VALW_PGPPE
(RL2) +3V_LAN
R-Short SOC_ENVDD SY6288C20AAC
TP_PWR_EN (RC187) +3VALW_PGPPG (UX1) +LCDVDD
SY6288C20AAC +3V_PTP
(UK1)
R-Short 0 ohm
(RC171) +3VALW_RTC (RM1)NBYOC@ +3VS_WLAN
WLAN_ON SY6288C20AAC
(UM1)BYOC@ +3VS_WLAN
R-Short 0 ohm
(RC198) +3VALW_HDA (RM9) +3VS_SSD_NGFF
FP_PWR_EN SY6288C20AAC R-Short R-Short
+FP_VCC +3VALW_SPI +1.8VS_3VS_PGPPA
(UK6)FP@ (RC154) (RC178)
R-Short R-Short +3VS_TPM
(RW1) +3VALW_TPM (RW2)
SUSP# EM5209VF JUMP R-Short
+3VS_OUT (JPQ1) +3VS +3VS_DVDDIO
(UQ1) (RA2)
EN_1.8VALW G9661MF11U JUMP R-Short
(PU1801)N17S_VGA@ +1.8VALWP (PJ1802) +1.8VALW_PRIM (RA5) +3VS_DVDD
SUSP# EM5209VF R-Short

(UC5) +1.8VS (RA6) +1.8VS_VDDA
3 3
EN_1VALW SY8288RAC JUMP R-Short
(PUF1) +1.0VALWP (PJF1) +1.0VALW_PRIM (RC148) +1.0VALW_APLL
JUMP R-Short
(JPC9) +1.0VALW_MPHYPLL (RC176) +1.0VALW_SRAM
R-Short R-Short
(RC162) +1.0VALW_DTS (RC156) +1.0VALW_APLLEBB
R-Short R-Short
(RC169) +1.0VALW_CLK6_24TBT (RC209) +1.0VALW_MPHYGT
R-Short R-Short
(RC164) +1.0VALW_VCCCLK2 (RC149) +1.0VALW_AMPHYPLL
R-Short
(RC190) +1.0VALW_CLK4_F100OC
R-Short
(RC152) +1.0VALW_CLK5_F24NS
R-Short R-Short
(RC175) +1.0VALW_MPHYAON (RC143) +1.0V_VCCSFR
SYSON EM5209VF R-Short
(UC5) +1.0V_VCCSTU (RC140) +1.0V_VCCST
SUSP# AOZ1334DI-02 R-Short
(UC6) +1.0VS_VCCSTG_IO (RC188) +1.0VS_VCCSTG
EN_VCCSTG_VCCPLL_OC JUMP
(JPC5) +VCCIO
4 4
Vinafix.com Security Classification

Issued Date 2018/12/11
Compal Secret Data
Deciphered Date 2018/11/04 Title
Compal Electronics, Inc.
Power Rail
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Date : Monday, May 13, 2019 Sheet 4 of 47
A B C D E
A B C D E
2.2K 2.2K
2.2K
+3VALW_PRIM 2.2K
+3VS
R7 SOC_SMBCLK SOC_SMBCLK_1
SOC_SMBDATA 2N7002DW SOC_SMBDATA_1

1 SO-DIMM 1
R8
Kabylake
SOC
SOC_SML0CLK 499
R9 G-Sensor
499
+3VALW_PRIM
W2 SOC_SML0DATA
2.2K
2.2K
+3VALW_PRIM
W3 SOC_SML1CLK
V3 SOC_SML1DATA
2 2
2.2K
2.2K
+3VLP_EC
77 EC_SMB_CK1 100 ohm EC_SMB_CK1-1 4

SCL1 BATTERY
78 EC_SMB_DA1 100 ohm EC_SMB_DA1-1 3
SDA1 CONN
0 ohm 12
EC_SMB_CK1_CHGR
0 ohm Charger
EC_SMB_DA1_CHGR 11
KBC SCL2 79 SOC_SML1CLK
SDA2 80 SOC_SML1DATA
3
KB9022 I2C Address Table 3
Address(8bit)
BUS Device Address(7 bit)
Write Read
I2C_0 (+3VS) Reserved
TM-P3393-003 (TP) 0x2C
I2C_1 (+3VALW_PGPPC_E) FA577E-1206 (TP-ELAN) 0x15
SA577C-12A0 (TP-ELAN) 0x15
SO-DIMM 0xA4
SOC_SMBCLK (+3VS) G-Sensor 0x30
SOC_SML1CLK VGA 0x9E

(+3VALW_PRIM) EC
BQ24781RUYR (Charger IC) 0x12
EC_SMB_CK1 (+3VLP)
4 BATTERY PACK 0x16 4

Vinafix.com SMBUS_Routing_Table
A B C D E
A B C D E
PWR Sequence_KBL-U22/U42
+RTCVCC
tPCH01_Min : 9 ms
SOC_RTCRST#
1 1
+19VB
+3VLP
EC_ON
tPCH04_Min : 9 ms
+5VALW/+3VALW(+3VALW_DSW...)
tPCH34_Max : 20 ms
SPOK tPCH06_Min : 200 us (+3VALW stable (@95% of full value) to +1.0VALW_PRIM starting to ramp)
+1.8VALW_PRIM
+1.8VALW_PG
+VCCPRIM_CORE/+1.0VALW_PRIM
tPCH03_Min : 10 ms
EC_RSMRST#
ON/OFF
2
PBTN_OUT# tPCH43_Min : 95 ms 2
Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#
PM_SLP_S5#
tPCH18_Min : 90 us
ESPI_RST#
PM_SLP_S4#
SYSON
+1.0V_VCCSTU
+1.2V_VDDQ
PM_SLP_S3#
SUSP#
tCPU04 Min : 100 ns
+1.0VS_VCCSTG
tCPU10 Min : 1 ms
+VCCIO
3 3
+5VS/+3VS/+1.8VS/+1.5VS
tCPU00 Min : 1 ms
EC_VCCST_PG
VR_ON
tCPU19 Max : 100 ns
SM_PG_CTRL
tCPU18 Max : 35 us
+0.6VS_VTT
tCPU09 Min : 1 ms
+VCC_SA
VR_PWRGD
tCPU16 Min : 0 ns
PCH_PWROK (SYS_PWROK) tPLT05 Min : Platform dependent
H_CPUPWRGD
PLT_RST#
+VCC_CORE / +VCC_GT
4 4
Security Classification
2018/12/11
Compal Secret Data
2018/11/04 Title
Issued Date Deciphered Date
Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
A B C D E
A B C D E
1 1
UC1A SKL-U
Rev_0.53
E55 C47
<22> SOC_DP1_N0 F55 DDI1_TXN[0] EDP_TXN[0] C46 EDP_TXN0 <21>
<22> SOC_DP1_P0 E58 DDI1_TXP[0] EDP_TXP[0] D46 EDP_TXP0 <21>
<22> SOC_DP1_N1 F58 DDI1_TXN[1] EDP_TXN[1] C45 EDP_TXN1 <21>
<22> SOC_DP1_P1 F53 DDI1_TXP[1] EDP_TXP[1] A45 EDP_TXP1 <21>
HDMI <22> SOC_DP1_N2 G53 DDI1_TXN[2] EDP_TXN[2] B45 EDP_TXN2 <21> eDP
Functional Strap Definitions <22>
<22>
SOC_DP1_P2
SOC_DP1_N3
F56 DDI1_TXP[2]
DDI1_TXN[3]
EDP_TXP[2]
EDP_TXN[3]
A47 EDP_TXP2
EDP_TXN3
<21>
<21>
G56 B47
<22> SOC_DP1_P3 DDI1_TXP[3] EDP_TXP[3] EDP_TXP3 <21>
#543016 PDG2.0 P.844 C50 E45
EDP_AUXN <21>
D50 DDI2_TXN[0] DDI EDP EDP_AUXN F45
DDPB_CTRLDATA C52 DDI2_TXP[0] EDP_AUXP EDP_AUXP <21>
DDI2_TXN[1]
DDPC_CTRLDATA D52
A50 DDI2_TXP[1] EDP_DISP_UTIL
B52
Display Port B/C Detected B50 DDI2_TXN[2]

DDI2_TXP[2] DDI1_AUXN
G50
D51 F50
NC =Port is not detected. C51 DDI2_TXN[3] DDI1_AUXP E48
PU =Port is detected. DDI2_TXP[3] DDI2_AUXN
DDI2_AUXP
F48
G46
HDMI DDC (Port B) DISPLAY SIDEBANDS DDI3_AUXN F46
SOC_DP1_CTRL_CLK L13 DDI3_AUXP RC212 +3VS
<22> SOC_DP1_CTRL_CLK SOC_DP1_CTRL_DATA L12 GPP_E18/DDPB_CTRLCLK L9 SOC_DP1_HPD
SOC_DP1_HPD <22> From HDMI 10K_0402_5%
2 <22> SOC_DP1_CTRL_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7 EC_SCI# 1 2 2
N7 GPP_E14/DDPC_HPD1 L6
N8 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 N9 EC_SCI#
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 CPU_EDP_HPD EC_SCI# <29>
GPP_E17/EDP_HPD CPU_EDP_HPD <21> From eDP EC_SCI# SOC internal PU
+VCCIO N11
N12 GPP_E22/DDPD_CTRLCLK R12 ENBKL
GPP_E23/DDPD_CTRLDATA EDP_BKLTEN R11 SOC_BKL_PWM ENBKL <29>
RC1 1 2 24.9_0402_1% EDP_COMP EDP_COMP E52 1 OF 20 EDP_BKLTCTL U13 SOC_ENVDD SOC_BKL_PWM <21> #545659 PCH EDS1.51 P.131
EDP_RCOMP EDP_VDDEN SOC_ENVDD <21> SCI capability is available on all GPIOs, while
SKL-U_BGA1356 NMI and SMI capability is available on only
#543016 PDG2.0 P.225 @ select GPIOs.
COMPENSATION PU for eDP Below are the PCH GPIOs that can be
Trace width=5 mils,Spacing=25mil,Max length=600mils routed to generate SMI# or NMI:
‧ GPP_B14, GPP_B20, GPP_B23
‧ GPP_C 23 : 22
+1.0V_VCCST #543016 PDG2.0 P.857 ‧ GPP_ D 4 : 0
PU 1K to VCCST +1.0VS_VCCSTG ‧GPP_E 8 : 0 , GPP_E 16 : 13
1
RC2 1 2 1K_0402_5% H_THERMTRIP#

RC3
Reserved CATERR# for UC1D SKL-U
1 2 1K_0402_5%
sight i ngs i ss ue c heck Rev_0.53 @ESD@ CC81
CC132 ESD@ RC4 H_CATERR# D63 .1U_0402_16V7K
@ T166 H_PECI CATERR# SOC_XDP_TRST#
1000P_0402_50V7K 499_0402_1% A54 1 2
<29> H_PECI
2
1 2 H_PROCHOT#_R C65 PECI

<29,36> H_PROCHOT# H_THERMTRIP# C63 PROCHOT# JTA G
A65 THERMTRIP# B61 CPU_XDP_TCK0

SKTOCC# PROC_TCK D60 SOC_XDP_TDI
CPU MISC PROC_TDI
XDP_BPM#0 C55 A61 SOC_XDP_TDO
@ T160 XDP_BPM#1 BPM#[0] PROC_TDO SOC_XDP_TMS
@ T161 D55 C60
3 B54 BPM#[1] PROC_TMS B59 SOC_XDP_TRST# 3
BPM#[2] PROC_TRST# T194 @
C56
MP BPM#[3] B56 PCH_JTAG_TCK1
PCH_JTAG_TCK SOC_XDP_TDI T195 @
CC163 2 1 A6 D59
@ESD@ .1U_0402_16V7K A7 GPP_E3/CPU_GP0 PCH_JTAG_TDI A56 SOC_XDP_TDO
CC52 2 1 H_PECI RC137 2 @ 1 0_0402_5% TP_INT# BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDO C59 SOC_XDP_TMS
<29,30> EC_TP_INT# AY5 GPP_B3/CPU_GP2 PCH_JTAG_TMS C61 SOC_XDP_TRST#
@ESD@ .1U_0402_16V7K
GPP_B4/CPU_GP3 PCH_TRST# A59 CPU_XDP_TCK0
RC5 2 1 49.9_0402_1% CPU_POPIRCOMP AT16 JTAGX
2 1 H_PROCHOT#_R RC6 2 1 49.9_0402_1% PCH_OPIRCOMP AU16 PROC_POPIRCOMP
ESD@ CC53 RC7 2 1 49.9_0402_1% EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
1000P_0402_50V7K RC8 2 1 49.9_0402_1% EOPIO_RCOMP H65 OPCE_RCOMP
OPC_RCOMP
4 OF 20
SKL-U_BGA1356
#543016 PDG2.0 P.873 @
PROC_POPIRCOMP/PCH_OPIRCOMP
For Intel debug, place to CPU side. PD 50ohm
+1.0VS_VCCSTG
#543016 PDG2.0 P.629
#544669 CRB1.1 P.52
RC11 2 CMC@ 1 51_0402_5% SOC_XDP_TMS EDRAM_OPIO_RCOMP/EOPIO_RCOMP
PD 50ohm
RC13 2 @ 1 51_0402_5% SOC_XDP_TDI
RC15 2 CMC@ 1 51_0402_5% SOC_XDP_TDO
RC35 2 CMC@ 1 51_0402_5% CPU_XDP_TCK0
4 4
2018/12/11
Compal Secret Data
2018/11/04 Title
KBL-U(1/12)DDI,MSIC,XDP,EDP
A B C D E
A B C D E
Interleaved Memory
SKL-U
UC1B SKL-U UC1C
Rev_0.53 Rev_0.53
AU53 DDR_A_CLK#0
<19> DDR_A_D[0..15] DDR_A_D0 DDR0_CKN[0] DDR_A_CLK0 DDR_A_CLK#0 <19> <20> DDR_B_D[0..15] DDR_B_D0 DDR_B_CLK#0
AL71 AT53 AF65 AN45
DDR_A_D1 DDR0_DQ[0] DDR0_CKP[0] DDR_A_CLK#1 DDR_A_CLK0 <19> DDR_B_D1 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] DDR_B_CLK#1 DDR_B_CLK#0 <20>
AL68 AU55 AF64 AN46
DDR_A_D2 DDR0_DQ[1] DDR0_CKN[1] DDR_A_CLK1 @ T240 DDR_B_D2 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] DDR_B_CLK0 DDR_B_CLK#1 <20>
AN68 AT55 AK65 AP45
DDR_A_D3 DDR0_DQ[2] DDR0_CKP[1] @ T241 DDR_B_D3 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] DDR_B_CLK1 DDR_B_CLK0 <20>
AN69 AK64 AP46
DDR_A_D4 DDR0_DQ[3] DDR_A_CKE0 DDR_B_D4 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 <20>
AL70 BA56 AF66
DDR_A_D5 DDR0_DQ[4] DDR0_CKE[0] DDR_A_CKE1 DDR_A_CKE0 <19> DDR_B_D5 DDR1_DQ[4]/DDR0_DQ[20] DDR_B_CKE0
AL69 BB56 AF67 AN56
DDR_A_D6 DDR0_DQ[5] DDR0_CKE[1] @ T247 DDR_B_D6 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] DDR_B_CKE1 DDR_B_CKE0 <20>
AN70 AW56 AK67 AP55
1 DDR_A_D7 DDR0_DQ[6] DDR0_CKE[2] @ T14 DDR_B_D7 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] DDR_B_CKE1 <20> 1
AN71 AY56 AK66 AN55
DDR_A_D8 DDR0_DQ[7] DDR0_CKE[3] @ T15 DDR_B_D8 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] @ T17
AR70 AF70 AP53
DDR_A_D9 DDR0_DQ[8] DDR_A_CS#0 DDR_B_D9 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3] @ T18
AR68 AU45 AF68
DDR_A_D10 DDR0_DQ[9] DDR0_CS#[0] DDR_A_CS#1 DDR_A_CS#0 <19> DDR_B_D10 DDR1_DQ[9]/DDR0_DQ[25] DDR_B_CS#0
AU71 AU43 AH71 BB42
DDR_A_D11 DDR0_DQ[10] DDR0_CS#[1] DDR_A_ODT0 @ T242 DDR_B_D11 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] DDR_B_CS#1 DDR_B_CS#0 <20>
AU68 AT45 AH68 AY42
DDR_A_D12 DDR0_DQ[11] DDR0_ODT[0] DDR_A_ODT1 DDR_A_ODT0 <19> DDR_B_D12 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] DDR_B_ODT0 DDR_B_CS#1 <20>
AR71 AT43 AF71 BA42
DDR_A_D13 DDR0_DQ[12] DDR0_ODT[1] @ T243 DDR_B_D13 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] DDR_B_ODT1 DDR_B_ODT0 <20>
AR69 AF69 AW42
DDR_A_D14 DDR0_DQ[13] DDR_A_MA5 DDR_B_D14 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDR_B_ODT1 <20>
AU70 BA51 AH70
DDR_A_D15 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR_A_MA9 DDR_A_MA5 <19> DDR_B_D15 DDR1_DQ[14]/DDR0_DQ[30] DDR_B_MA5
AU69 BB54 AH69 AY48
<19> DDR_A_D[16..31] DDR_A_D16 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR_A_MA6 DDR_A_MA9 <19> <20> DDR_B_D[16..31] DDR_B_D16 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR_B_MA9 DDR_B_MA5 <20>
BB65 BA52 AT66 AP50
DDR_A_D17 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR_A_MA8 DDR_A_MA6 <19> DDR_B_D17 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR_B_MA6 DDR_B_MA9 <20>
AW65 AY52 AU66 BA48
DDR_A_D18 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR_A_MA7 DDR_A_MA8 <19> DDR_B_D18 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR_B_MA8 DDR_B_MA6 <20>
AW63 AW52 AP65 BB48
DDR_A_D19 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR_A_BG0 DDR_A_MA7 <19> DDR_B_D19 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR_B_MA7 DDR_B_MA8 <20>
AY63 AY55 AN65 AP48
DDR_A_D20 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR_A_MA12 DDR_A_BG0 <19> DDR_B_D20 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR_B_BG0 DDR_B_MA7 <20>
BA65 AW54 AN66 AP52
DDR_A_D21 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR_A_MA11 DDR_A_MA12 <19> DDR_B_D21 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR_B_MA12 DDR_B_BG0 <20>
AY65 BA54 AP66 AN50
DDR_A_D22 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR_A_ACT# DDR_A_MA11 <19> DDR_B_D22 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR_B_MA11 DDR_B_MA12 <20>
BA63 BA55 AT65 AN48
DDR_A_D23 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR_A_BG1 DDR_A_ACT# <19> DDR_B_D23 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDR_B_ACT# DDR_B_MA11 <20>
BB63 AY54 AU65 AN53
DDR_A_D24 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_BG1 <19> DDR_B_D24 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR_B_BG1 DDR_B_ACT# <20>
BA61 AT61 AN52
DDR_A_D25 DDR0_DQ[24]/DDR0_DQ[40] DDR_A_MA13 DDR_B_D25 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR_B_BG1 <20>
AW61 AU46 AU61
DDR_A_D26 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR_A_MA15 DDR_A_MA13 <19> DDR_B_D26 DDR1_DQ[25]/DDR0_DQ[57] DDR_B_MA13
BB59 AU48 AP60 BA43
DDR_A_D27 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR_A_MA14 DDR_A_MA15 <19> DDR_B_D27 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDR_B_MA15 DDR_B_MA13 <20>
AW59 AT46 AN60 AY43
DDR_A_D28 DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR_A_MA16 DDR_A_MA14 <19> DDR_B_D28 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR_B_MA14 DDR_B_MA15 <20>
BB61 AU50 AN61 AY44
DDR_A_D29 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR_A_BA0 DDR_A_MA16 <19> DDR_B_D29 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR_B_MA16 DDR_B_MA14 <20>
AY61 AU52 AP61 AW44
DDR_A_D30 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR_A_MA2 DDR_A_BA0 <19> DDR_B_D30 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR_B_BA0 DDR_B_MA16 <20>
BA59 AY51 AT60 BB44
DDR_A_D31 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDR_A_BA1 DDR_A_MA2 <19> DDR_B_D31 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR_B_MA2 DDR_B_BA0 <20>
AY59 AT48 AU60 AY47
<19> DDR_A_D[32..47] DDR_A_D32 DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR_A_MA10 DDR_A_BA1 <19> <20> DDR_B_D[32..47] DDR_B_D32 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDR_B_BA1 DDR_B_MA2 <20>
AY39 AT50 AU40 BA44
DDR_A_D33 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR_A_MA1 DDR_A_MA10 <19> DDR_B_D33 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR_B_MA10 DDR_B_BA1 <20>
AW39 BB50 AT40 AW46
DDR_A_D34 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR_A_MA0 DDR_A_MA1 <19> DDR_B_D34 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR_B_MA1 DDR_B_MA10 <20>
AY37 AY50 AT37 AY46
DDR_A_D35 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR_A_MA3 DDR_A_MA0 <19> DDR_B_D35 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR_B_MA0 DDR_B_MA1 <20>
AW37 BA50 AU37 BA46
DDR_A_D36 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] DDR_A_MA4 DDR_A_MA3 <19> DDR_B_D36 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR_B_MA3 DDR_B_MA0 <20>
BB39 BB52 AR40 BB46
DDR_A_D37 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDR_A_MA4 <19> DDR_B_D37 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] DDR_B_MA4 DDR_B_MA3 <20>
BA39 AP40 BA47
DDR_A_D38 DDR0_DQ[37]/DDR1_DQ[5] DDR_A_DQS#0 DDR_B_D38 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4] DDR_B_MA4 <20>
BA37 AM70 AP37
2 DDR_A_D39 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] DDR_A_DQS0 DDR_A_DQS#0 <19> DDR_B_D39 DDR1_DQ[38]/DDR1_DQ[22] DDR_B_DQS#0 2
BB37 AM69 AR37 AH66
DDR_A_D40 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] DDR_A_DQS#1 DDR_A_DQS0 <19> DDR_B_D40 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] DDR_B_DQS0 DDR_B_DQS#0 <20>
AY35 AT69 AT33 AH65
DDR_A_D41 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] DDR_A_DQS1 DDR_A_DQS#1 <19> DDR_B_D41 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] DDR_B_DQS#1 DDR_B_DQS0 <20>
AW35 AT70 AU33 AG69
DDR_A_D42 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] DDR_A_DQS#2 DDR_A_DQS1 <19> DDR_B_D42 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] DDR_B_DQS1 DDR_B_DQS#1 <20>
AY33 BA64 AU30 AG70
DDR_A_D43 DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] DDR_A_DQS2 DDR_A_DQS#2 <19> DDR_B_D43 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] DDR_B_DQS#2 DDR_B_DQS1 <20>
AW33 AY64 AT30 AR66
DDR_A_D44 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] DDR_A_DQS#3 DDR_A_DQS2 <19> DDR_B_D44 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] DDR_B_DQS2 DDR_B_DQS#2 <20>
BB35 AY60 AR33 AR65
BA35 BA60 AP33 AR61
DDR_A_D46 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] DDR_A_DQS#4 DDR_A_DQS3 <19> DDR_B_D46 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] DDR_B_DQS3 DDR_B_DQS#3 <20>
BA33 BA38 AR30 AR60
BB33 AY38 AP30 AT38
<19> DDR_A_D[48..63] DDR_A_D48 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] DDR_A_DQS#5 DDR_A_DQS4 <19> <20> DDR_B_D[48..63] DDR_B_D48 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] DDR_B_DQS4 DDR_B_DQS#4 <20>
AY31 AY34 AU27 AR38
DDR_A_D49 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] DDR_A_DQS5 DDR_A_DQS#5 <19> DDR_B_D49 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] DDR_B_DQS#5 DDR_B_DQS4 <20>
AW31 BA34 AT27 AT32
DDR_A_D50 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] DDR_A_DQS#6 DDR_A_DQS5 <19> DDR_B_D50 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] DDR_B_DQS5 DDR_B_DQS#5 <20>
AY29 BA30 AT25 AR32
DDR_A_D51 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] DDR_A_DQS6 DDR_A_DQS#6 <19> DDR_B_D51 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] DDR_B_DQS#6 DDR_B_DQS5 <20>
AW29 AY30 AU25 AR25
DDR_A_D52 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] DDR_A_DQS#7 DDR_A_DQS6 <19> DDR_B_D52 DDR1_DQ[51] DDR1_DQSN[6] DDR_B_DQS6 DDR_B_DQS#6 <20>
BB31 AY26 AP27 AR27
DDR_A_D53 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] DDR_A_DQS7 DDR_A_DQS#7 <19> DDR_B_D53 DDR1_DQ[52] DDR1_DQSP[6] DDR_B_DQS#7 DDR_B_DQS6 <20>
BA31 BA26 AN27 AR22
DDR_A_D54 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_A_DQS7 <19> DDR_B_D54 DDR1_DQ[53] DDR1_DQSN[7] DDR_B_DQS7 DDR_B_DQS#7 <20>
BA29 AN25 AR21
DDR_A_D55 DDR0_DQ[54]/DDR1_DQ[38] DDR_A_ALERT# DDR_B_D55 DDR1_DQ[54] DDR1_DQSP[7] DDR_B_DQS7 <20>
BB29 AW50 AP25
DDR_A_D56 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# DDR_A_PAR DDR_A_ALERT# <19> DDR_B_D56 DDR1_DQ[55] DDR_B_ALERT#
AY27 AT52 AT22 AN43
DDR_A_D57 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR DDR_A_PAR <19> DDR_B_D57 DDR1_DQ[56] DDR1_ALERT# DDR_B_PAR DDR_B_ALERT# <20>
AW27 AU22 AP43
DDR_A_D58 DDR0_DQ[57]/DDR1_DQ[41] +0.6V_A_VREFCA DDR_B_D58 DDR1_DQ[57] DDR1_PAR DDR_B_PAR <20>
AY25 AY67 AU21 AT13
DDR_A_D59 DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA +0.6V_A_VREFCA DDR_B_D59 DDR1_DQ[58] DRAM_RESET# SM_RCOMP0 DDR_DRAMRST# <19,20>
AW25 AY68 AT21 AR18
DDR_A_D60 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR CH - A
DDR0_VREF_DQ BA67 +0.6V_B_VREFCA DDR_B_D60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP1
DDR_A_D61 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ +0.6V_B_VREFCA DDR_B_D61 DDR1_DQ[60] DDR CH - B DDR_RCOMP[1] SM_RCOMP2
BA27 AP22 AU18
DDR_A_D62 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_PG_CTRL DDR_B_D62 AP21 DDR1_DQ[61] DDR_RCOMP[2]
DDR_A_D63 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL #543016 PDG2.0 P.190 DDR_B_D63 AN21 DDR1_DQ[62]
DDR0_DQ[63]/DDR1_DQ[47] 2 OF 20 Trace width/Spacing >= 20mils DDR1_DQ[63] 3 OF 20
Place componment near SODIMM
SKL-U_BGA1356 SKL-U_BGA1356
@ @
3 +1.2V_VDDQ 3
+3VS
561280 4.18 DDR4 Mixed SODIMM and Memory Down

2 1 CC57 Note: RCOMP[0] should be 121 ohm
0.1U_0201_10V6K PVT 03/13
1
UC7 RC10 SM_RCOMP0 RC38 1 2 121_0402_1%
1 5 SM_RCOMP1 RC39 1 2 80.6_0402_1%
NC VCC 100K_0402_5%
SM_RCOMP2 RC40 1 2 100_0402_1%
DDR_PG_CTRL 2
2
A 4
3 Y SM_PG_CTRL <38>
GND #543016 PDG2.0 P.139
W=12-15 Space= 20/25 L=500mil
2
74AUP1G07SE-7_SOT353_5P DDR_VTT_CNTL to DDR
RC16
@ 1M_0402_5% VTT supplied ramped @ESD@
Change PN to SA00007WE00 <35uS DDR_DRAMRST# CC70 1 2 .1U_0402_16V7K
(tCPU18)
1
2015MOW02, Can't install Cap on DRAMRST
Intel DOC: 549352
4 4
2018/12/11
Compal Secret Data
2018/11/04 Title
KBL-U(2/12)DDR4
A B C D E
A B C D E
+3VS
SOC_SMBCLK_1 RC222 1 2 2.2K_0402_5%

SOC_SMBDATA_1RC223 1 2 2.2K_0402_5%
+3VALW_PRIM
SOC_SML0CLK RC49 1 2 499_0402_1%
1 SOC_SML0DATA RC50 1 2 499_0402_1% 1
SOC_SML1CLK RC245 1 2 2.2K_0402_5%

SOC_SML1DATA RC246 1 2 2.2K_0402_5%
SOC_SMBCLK RC247 1 2 2.2K_0402_5%
SKL-U SOC_SMBDATA
SPI ROM UC1E RC248 1 2 2.2K_0402_5%
SPI - FLASH 11/12
SMBUS, SMLINK
SOC_SPI_CLK AV2
<30> SOC_SPI_CLK SOC_SPI_SO AW3 SPI0_CLK R7 SOC_SMBCLK +3VS
<30> SOC_SPI_SO SOC_SPI_SI AV3 SPI0_MISO GPP_C0/SMBCLK R8 SOC_SMBDATA
<30> SOC_SPI_SI SOC_SPI_IO2 AW2 SPI0_MOSI GPP_C1/SMBDATA R10 SOC_SMBALERT# SMB (to DDR, G sensor)
SOC_SPI_IO3 SPI0_IO2 GPP_C2/SMBALERT# @ T239
AU4
SPI0_IO3
5
SOC_SPI_CS#0 AU3 R9 SOC_SML0CLK +3VALW_PRIM
Strap Pin
G
AU2 SPI0_CS0# GPP_C3/SML0CLK W2 SOC_SML0DATA QC2B
SOC_SPI_CS#2 AU1 SPI0_CS1# GPP_C4/SML0DATA W1 SOC_SML0ALERT# 4.7K_0402_5% 2 ESPI@ 1 RC202 2N7002KDW_SOT363-6
<30> SOC_SPI_CS#2 SPI0_CS2# GPP_C5/SML0ALERT#
Add CS#2 for TPM use 11/16 W3 SOC_SML1CLK SOC_SMBCLK 3 4 SOC_SMBCLK_1
SOC_SML1CLK <29>
S
SPI - TOUCH GPP_C6/SML1CLK V3 SOC_SML1DATA SOC_SMBCLK_1 <20,26>
D
GPP_C7/SML1DATA SOC_SML1DATA <29> SML1 ( to EC, Thermal sensor)
2
M2 AM7 SOC_SML1ALERT#
G
GPP_D1/SPI1_CLK GPP_B23/SML1ALERT#/PCHHOT# @ T234
M3 QC2A
J4 GPP_D2/SPI1_MISO 2N7002KDW_SOT363-6
V1 GPP_D3/SPI1_MOSI
SPI Touch V2 GPP_D21/SPI1_IO2 SOC_SMBDATA 6 1 SOC_SMBDATA_1
Change RC144~RC147, RC45 to 15ohm when use ESPI SOC_SMBDATA_1 <20,26>
S
M1 GPP_D22/SPI1_IO3
D
GPP_D0/SPI1_CS#
LPC
AY13 LPC_AD0 RC144 1 @ 2 0_0402_5%
ESPI / LPC Bus
GPP_A1/LAD0/ESPI_IO0 BA13 LPC_AD1 1 2 LPC_AD0_R <29>
RC145 @ 0_0402_5% ESPI : +1.8V
C LINK GPP_A2/LAD1/ESPI_IO1 BB13 LPC_AD2 1 2 LPC_AD1_R <29>
RC146 @ 0_0402_5%
G3
G2 CL_CLK
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
AY12
BA12
LPC_AD3
LPC_FRAME#
RC147 1 @ 2 0_0402_5%
LPC_AD2_R
LPC_AD3_R
<29>
<29> * LPC : +3.3V
2 G1 CL_DATA GPP_A5/LFRAME#/ESPI_CS# BA11 ESPI_RST# LPC_FRAME# <29> 2
RCIN# PU 10Kohm 11/20 CL_RST# GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RST# <29>
+1.8VS_3VS_PGPPA
RCIN# AW13 AW9 CLKOUT_LPC0 RC45 2 LPC@ 1 22_0402_5% PM_CLKRUN# 1 2 10K_0402_5%

GPP_A0/RCIN# GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_LPC_EC <29> To EC RC107
AY9
EC_SERIRQ AY11 GPP_A10/CLKOUT_LPC1 AW11 PM_CLKRUN# EC_SERIRQ 1 2 10K_0402_5%
<29> EC_SERIRQ GPP_A6/SERIRQ GPP_A8/CLKRUN#
remove CLK_LPC_TPM 11/16 RC112
5 OF 20
LPC Mode
SKL-U_BGA1356
@
+3VS
RCIN# RC277 1 2 10K_0402_5%
SPI ROM ( 8MByte ) +3VALW_SPI CC8 SML0ALERT# / GPP_C5 (Internal Pull Down):
UC2 1 2
0.1U_0201_10V6K * (Sampled: Rising edge of RSMRST# )
SOC_SPI_CS#0 1 8
SOC_SPI_SO_0_R 2 /CS VCC 7 SOC_SPI_IO3_0_R
SOC_SPI_IO2_0_R 3 DO(IO1) /HOLD(IO3) 6 SOC_SPI_CLK_0_R eSPI or LPC
3
4 /WP(IO2)
GND
CLK
DI(IO0)
5 SOC_SPI_SI_0_R 0 = LPC is selected for EC --> For KB9022/9032 Use 3
RC241,RC242,RC243,RC244,RC52 are close UC2 W25Q64JVSSIQ_SO8 1 = eSPI is selected for EC --> For KB9032 Only.
SOC_SPI_IO3 RC241 2 NTPM@ 1 15_0402_5% SOC_SPI_IO3_0_R 2015MOW06 no need PU1K on SPI_IO2/IO3
SOC_SPI_SI RC242 2 NTPM@ 1 15_0402_5% SOC_SPI_SI_0_R +3VALW_SPI
SOC_SPI_CLK RC243 2 NTPM@ 1 15_0402_5% SOC_SPI_CLK_0_R
SOC_SPI_SO RC244 2 NTPM@ 1 15_0402_5% SOC_SPI_SO_0_R SOC_SPI_CLK_0_R 1 @EMI@ 2 1 2
RC24 0_0402_5% CC9 @EMI@ SOC_SPI_IO2 RC47 1 @ 2 1K_0402_1%
11/12 10P_0402_50V8J
SOC_SPI_IO3 RC48 1 @ 2 1K_0402_1% SMBALERT# / GPP_C2 (Internal Pull Down):
(Sampled: Rising edge of RSMRST# )
SOC_SPI_IO2 2 NTPM@ 1
RC52
SOC_SPI_IO2_0_R
15_0402_5%
*
ROM Socket, co-lay with UC2. +3VALW_SPI TLS Conf i dent ial i ty
SOC_SPI_CS#0
JC1 0 = Disable Intel ME Crypto Transport Layer Security
1 8
RC241 TPM@ RC243 TPM@ RC52 TPM@ SOC_SPI_IO2_0_R 3 CS# VCC 6 SOC_SPI_CLK_0_R (TLS) cipher suite (no conf i dent ial i ty).
SOC_SPI_IO3_0_R WP# SCLK SOC_SPI_SI_0_R
33_0402_5%
SD028330A80
33_0402_5%
SD028330A80
33_0402_5%
SD028330A80
7
4 HOLD# SI/SIO0
5
2 SOC_SPI_SO_0_R
1 = Enable Intel ME Crypto (TLS) (with conf i dent ial i ty).
GND SO/SIO1 Must be pulled up to support Intel AMT with TLS and Intel
RC242 TPM@
33_0402_5%
RC244 TPM@
33_0402_5% TPM Function
ACES_91960-0084N_MX25L3206EM2I
CONN@
SBA (Small Business Advantage) with TLS.
SD028330A80 SD028330A80
PVT JC1 cover solder mask
4 4
2018/12/11
Compal Secret Data
2018/11/04 Title
KBL-U(3/12)SPI,ESPI,SMB,LPC
A B C D E
A B C D E
1 1
UC1G SKL-U
Rev_0.53
AUDIO
HDA for AUDIO HDA_SYNC

HDA_BIT_CLK
BA22
HDA_SYNC/I2S0_SFRM
AY22
HDA_SDOUT BB22 HDA_BLK/I2S0_SCLK
SDIO/SDXC
HDA_SDIN0 HDA_SDIN0 BA21 HDA_SDO/I2S0_TXD
<25> HDA_SDIN0
AY21 HDA_SDI0/I2S0_RXD AB11
#543016 PDG2.0 P.403
HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13 SDIO signals are mult i pl exed w i t h GPI Os and def aul t
RC250 1 2 33_0402_5% HDA_BIT_CLK J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12 to GPIO funct i onali t y ( as i nput). If S DI Oi nt erf acei s
<25> HDA_BIT_CLK_R HDA_SYNC GPP_D23/I2S_MCLK GPP_G2/SD_DATA1
RC251 1 2 33_0402_5% AY20 W12 not used, the signals can be used as GPIOs instead.
<25> HDA_SYNC_R HDA_SDOUT I2S1_SFRM GPP_G3/SD_DATA2
RC252 1 2 33_0402_5% AW20 W11
<25> HDA_SDOUT_R
RC253 1 2 33_0402_5% HDA_RST# I2S1_TXD GPP_G4/SD_DATA3 W10 If the GPIO funct i onali t yi s al s o not us ed, t he si gnal s
<25> HDA_RST#_R GPP_G5/SD_CD# can be lef t as no- c onnect.
AK7 W8
11/12 AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7
AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
1 @ 2 AK10 GPP_F2/I2S2_TXD BA9
<29> ME_EN GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7
RC77 0_0402_5% BB9 RC76
GPP_A16/SD_1P8_SEL 200_0402_1%
PCH_DMIC_CLK H5 AB7 SD_RCOMP 2 1
HDA_SDO / I2S_TXD0 (Internal Pull Down): <25> PCH_DMIC_CLK PCH_DMIC_DATA D7 GPP_D19/DMIC_CLK0 SD_RCOMP
(Sampled: Rising edge of PCH_PWROK ) <25> PCH_DMIC_DATA GPP_D20/DMIC_DATA0
Flash Descriptor Security Override For 4Mic 11/29 PCH_DMIC_CLK1 D8 AF13
#543016 PDG2.0 P.879
<25> PCH_DMIC_CLK1 PCH_DMIC_DATA1 C8 GPP_D17/DMIC_CLK1 GPP_F23
0 = Enable security measures def i nedi n t he Fl as h <25> PCH_DMIC_DATA1 GPP_D18/DMIC_DATA1
2 Descriptor. PCH_SPKR AW5 2
<25> PCH_SPKR GPP_B14/SPKR
1 = Disable Flash Descriptor Security (override). This
strap should only be asserted high using external 7 OF 20
SKL-U_BGA1356
pull-up in manufacturing/debug environments ONLY. @
SPKR / GPP_B14 (Internal Pull Down): SKL_ULT

(Sampled:Rising edge of PCH_PWROK) UC1I
Rev_0.53
CSI-2
TOP Swap Override A36 C37 +3VALW_1.8VALW_PGPPD
* 0 = Disable TOP Swap mode. B36
C38
CSI2_DN0
CSI2_DP0
CSI2_CLKN0
CSI2_CLKP0
D37
C32
1 = Enable TOP Swap Mode. CSI2_DN1 CSI2_CLKN1
1
D38 D32
C36 CSI2_DP1 CSI2_CLKP1 C29 RC133
D36 CSI2_DN2 CSI2_CLKN2 D29 UMA@
CSI2_DP2 CSI2_CLKP2 10K_0402_5%
A38 B26
B38 CSI2_DN3 CSI2_CLKN3 A26
Intel HD Audio link capabilit i es #543016 PDG2.0 P.551
2
CSI2_DP3 CSI2_CLKP3
> Two SDI signals to support two external codecs. C31 E13 CSI2_COMP RC80 2 1 100_0402_1% DGPU_PRSNT#
> Drivers variable requency (5MHz to 24MHz) BCLK to support: D31 CSI2_DN4 CSI2_COMP B7 DGPU_PRSNT#
C33 CSI2_DP4 GPP_D4/FLASHTRIG
-- SDO double pumped up to 48 Mb/s CSI2_DN5
D33
-- SDI's single pumped up to 24 Mb/s CSI2_DP5
1
EMMC
A31
> Provides cadence for 44.1 kHz based sample rate output. B31 CSI2_DN6 AP2 RC134
> Support 1.5V, 1.8V, and 3.3V modes. A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1 VGA@
CSI2_DN7 GPP_F14/EMMC_DATA1 10K_0402_5%
B33 AP3
3 CSI2_DP7 GPP_F15/EMMC_DATA2 AN3 3
2
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
CSI2_DP8 GPP_F18/EMMC_DATA5 Remove eMMC pin 11/8
C28 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
CSI2_DP10 GPP_F21/EMMC_RCLK
DGPU_PRSNT#
C27 AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD DIS,Optimus 0
9 OF 20 AT1 EMMC_RCOMP 2 1
EMMC_RCOMP RC89 200_0402_1%
UMA 1
SKL-U_BGA1356
@ #543016 PDG2.0 P.393
4 4
2018/12/11
Compal Secret Data
2018/11/04 Title
KBL-U(4/12)HDA,EMMC,SDIO,CSI2
A B C D E
A B C D E
PVT 03/20
SOC_XTAL24_IN RC235 1 U22@ 2 33_0402_1% SOC_XTAL24_IN_R
+RTCVCC
U22@
RC91 1 2 20K_0402_5% SOC_SRTCRST# SOC_XTAL24_OUT RC236 1 U22@ 2 33_0402_1% SOC_XTAL24_OUT_R 1 2
RC92 1M_0402_5%
CC10 1 2 1U_0402_6.3V6K
YC1 U22@
1 563377 Intel MOW 33 24MHZ_18PF_XRCGB24M000F2P51R0 1
UC1J SKL_ULT
RC93 1 2 20K_0402_5% SOC_RTCRST# Rev_0.53 3 1
SOC_RTCRST# <29> 3 1
CLOCK SIGNALS
CC11 1 2 1U_0402_6.3V6K NC NC
1 1
Remove VGA 01/03 D42
JCMOS1 1 2 0_0603_5% C42 CLKOUT_PCIE_N0 4 2
@ CLR CMOS CLKOUT_PCIE_P0
CLKREQ_PCIE#0 AR10 CC12 CC13
GPP_B5/SRCCLKREQ0# 2 2
Place at RAM DOOR CLK_PCIE_N1
U22@ U22@
B42 27P_0402_50V8J 27P_0402_50V8J
<23> CLK_PCIE_N1 CLK_PCIE_P1 A42 CLKOUT_PCIE_N1 F43 CLK_CPU_ITP#
SM_INTRUDER# GLAN <23> CLK_PCIE_P1 CLKREQ_PCIE#1 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N CLK_CPU_ITP T164 @
RC941 2 1M_0402_5%
<23> CLKREQ_PCIE#1
AT7 E43 T165 @
GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
CLK_PCIE_N2 D41 BA17 SUSCLK
<24> CLK_PCIE_N2 CLK_PCIE_P2 CLKOUT_PCIE_N2 GPD8/SUSCLK T185 @
WLAN C41
+3VS <24> CLK_PCIE_P2 CLKREQ_PCIE#2 AT8 CLKOUT_PCIE_P2 E37 SOC_XTAL24_IN
<24> CLKREQ_PCIE#2 GPP_B7/SRCCLKREQ2# XTAL24_IN SOC_XTAL24_OUT
E35
CLK_PCIE_N3 D40 XTAL24_OUT
<24> CLK_PCIE_N3 CLK_PCIE_P3 C40 CLKOUT_PCIE_N3 E42 XCLK_BIASREF Follow 2014MOW48
CLKREQ_PCIE#0
M.2/SSD <24> CLK_PCIE_P3 CLKREQ_PCIE#3 AT10 CLKOUT_PCIE_P3 XCLK_BIASREF Skylake U PU 2.7k ohm to 1V
RC254 1 2 10K_0402_5%
CLKREQ_PCIE#1 <24> CLKREQ_PCIE#3 GPP_B8/SRCCLKREQ3# SOC_RTCX1
RC255 1 2 10K_0402_5%
RTCX1
AM18 Cannonlake U PD 60.4 ohm
B40 AM20 SOC_RTCX2 +1.0VALW_CLK5_F24NS
A40 CLKOUT_PCIE_N4 RTCX2
RC256 1 2 10K_0402_5% CLKREQ_PCIE#2 CLKREQ_PCIE#4 AU8 CLKOUT_PCIE_P4 AN18 SOC_SRTCRST# XCLK_BIASREF RC96 1 2 2.7K_0402_1%
RC257 1 2 10K_0402_5% CLKREQ_PCIE#3 GPP_B9/SRCCLKREQ4# SRTCRST# AM16 SOC_RTCRST#
RC258 1 2 10K_0402_5% CLKREQ_PCIE#4 E40 RTCRST#
RC259 1 2 10K_0402_5% CLKREQ_PCIE#5 E38 CLKOUT_PCIE_N5 RC136 1 @ 2 60.4_0402_1%
CLKREQ_PCIE#5 AU7 CLKOUT_PCIE_P5
11/12 GPP_B10/SRCCLKREQ5#
XCLK_BIASREF
10 OF 20
+1.0V_VCCST T:50ohm S:12/15 L:1000 Via:2
2 SKL-U_BGA1356 2
@
From EC(open-drain)
1
RC113
1K_0402_5%
RC116
2014MOW48:
60.4_0402_1% UC1K SKL-U Skylake-U use 24M 50 ohm ESR
2
1 2 EC_VCCST_PG Rev_0.53 Cannonlake U use 38.4M 30 ohm ESR

<29,32> EC_VCCST_PG_R SYSTEM POWER MANAGEMENT
AT11 PM_SLP_S0#
GPP_B12/SLP_S0# AP15 PM_SLP_S3# PM_SLP_S0# <14,29,30> SOC_RTCX2
Note for VCCST_PWRGD PLT_RST# AN10 GPD4/SLP_S3# BA16 PM_SLP_S4# PM_SLP_S3# <29,32>
1. 1.0V tolerance <29,30> PLT_RST# SYS_RESET# B5 GPP_B13/PLTRST# GPD5/SLP_S4# AY16 PM_SLP_S5# PM_SLP_S4# <29,32>
EC_RSMRST# SYS_RESET# GPD10/SLP_S5# @ T84 SOC_RTCX1
2. PDG2.0 P.598 Figure43-5 note17: when failure events, <29> EC_RSMRST#
AY17
RSMRST#
1 2
AN15 SLP_SUS#
VCCST_PWRGD and PCH_PWROK de-assert at the same t i me H_CPUPWRGD A68 SLP_SUS# AW15 SLP_LAN# @ T90 RC98 10M_0402_5%
T95 @ EC_VCCST_PG PROCPWRGD SLP_LAN# SLP_WLAN# @ T87
B65 BB17
VCCST_PWRGD GPD9/SLP_WLAN# PM_SLP_A# @ T88
AN16
T89 @ SYS_PWROK GPD6/SLP_A# @ T94
B6 YC2
+3VALW_PRIM <29,32> SYS_PWROK PCH_PWROK_R BA20 SYS_PWROK PBTN_OUT#_R
1 2 BA15 1 2
<29,32> PCH_PWROK PCH_DPWROK BB20 PCH_PWROK GPD3/PWRBTN# AC_PRESENT
RC20 AY15
+3VALW_DSW DSW_PWROK GPD1/ACPRESENT PM_BATLOW# AC_PRESENT <29>
10_0402_5% AU13 32.768KHZ_9PF_X1A000141000200
RC262 1 2 10K_0402_5% SYS_RESET# SUSPWRDNACK AR13 GPD0/BATLOW# Change PN to SJ10000Q400
1 2 LAN_WAKE# <29> SUSPWRDNACK SUSACK# AP11 GPP_A13/SUSWARN#/SUSPWRDNACK
RC263 10K_0402_5% T92 @ 1 1
RC260 1 2 10K_0402_5% PCH_PWROK GPP_A15/SUSACK# AU11 CC15 CC16
EC_RSMRST# GPP_A11/PME# SM_INTRUDER# @ T91
RC261 1 2 10K_0402_5% DVT 01/23 WAKE# BB15 AP16 6.8P_0402_50V8C 6.8P_0402_50V8C
LAN_WAKE# AM15 WAKE# INTRUDER#
11/12 AW17 GPD2/LAN_WAKE# AM10 EXT_PWR_GATE# 2 2
GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# SOC_VRALERT# @ T93
AT15 AM11
GPD7/RSVD GPP_B2/VRALERT#
11 OF 20
RC110 2 1 10K_0402_5% SYS_PWROK SKL-U_BGA1356
3 @ 3
+3VALW_DSW
2 @ 1 PBTN_OUT#_R
+3VALW_DSW <29> PBTN_OUT#
RC109 0_0402_5% PBTN_OUT#_R RC111
PCH
1
internal
@
PU
2 100K_0402_5%
RC104 1 2 1K_0402_5% WAKE#

EC_RSMRST# 2 @ 1 PCH_DPWROK AC_PRESENT RC106
EC1 internal
@
PU
2 10K_0402_5%
WAKE# (DSX wake event) RC114 0_0402_5%
10 KΩ pull- up t o Vcc DS W3_3. SYS_PWROK 2 @ 1 PCH_PWROK PM_BATLOW# RC103 1 2 10K_0402_5%
The pull-up is required even if PCIe* interface RC122 0_0402_5%
is not used on the plat f or m
.
+3VALW_PRIM
ESD@ 1000P_0402_50V7K Default : GPI
2 1 CC131 EC_VCCST_PG SOC_VRALERT# RC115 2 @ 1 10K_0402_5%
@ESD@ +3VS
CC51 2 1 .1U_0402_16V7K SYS_RESET# PCH PLTRST Buffer
5
ESD@ 1000P_0402_50V7K
2 1 CC50 H_CPUPWRGD PLT_RST# 2
P
B 4 PLT_RST_BUF#
1 Y PLT_RST_BUF# <23,24>
@ESD@
A
1
CC66 2 1 .1U_0402_16V7K SYS_PWROK @
UC3 3 RC118
ESD@ 1000P_0402_50V7K MC74VHC1G08DFT2G_SC70-5 100K_0402_5%
2 1 CC65 PCH_PWROK_R PLT_RST_BUF#
1
2
@ESD@ 2 1
4 CC69 2 1 .1U_0402_16V7K EC_RSMRST# @ RC125 0_0402_5% CC130 4
100P_0402_50V8J
@ESD@ 2 @ESD@
2 1 PCH_PWROK
CC156 1000P_0402_50V7K
Add CC156 12/17 Reserved for ESD place near UC2.1
#543016 PDG2.0 P.599 CC164

ESD@
2 1 EC_VCCST_PG_R
.1U_0402_16V7K
2018/12/11
Compal Secret Data
2018/11/04 Title
PROCPWRGD is used only for power sequence Issued Date Deciphered Date
debug and isVinafix.com
CC165 2 1
not required to be connected to ESD@ .1U_0402_16V7K
KBL-U(5/12)CLK,GPIO
anything on the plat f or m. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
PVT ESD request 03/22 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1A
A B C D E
A B C D E
DVT 02/24 +3VALW_1.8VALW_PGPPD
1
RC215
10K_0402_5%
U22@
2
CPU_ID
1
1
CPU_ID RC214
1
U22 1 10K_0402_5%
U42@
U42 0
2
UC1F SKL-U +3VALW_1.8VALW_PGPPD
Rev_0.53
LPSS ISH
PROJECT_ID0 RC207 2 @ 1 10K_0402_5%
TS_EN AN8 RC210 1 2 10K_0402_5%
<21,29> TS_EN GPP_B15/GSPI0_CS#
AP7 P2 EH7L1@
AP8 GPP_B16/GSPI0_CLK GPP_D9 P3 CPU_ID
GSPI0_MOSI AR7 GPP_B17/GSPI0_MISO GPP_D10 P4 PROJECT_ID0 PROJECT_ID1 RC211 2 @ 1 10K_0402_5%
@ T111 GPP_B18/GSPI0_MOSI GPP_D11 PROJECT_ID1
P1 RC213 1 2 10K_0402_5%
AM5 GPP_D12 EH7L1@
AN7 GPP_B19/GSPI1_CS# M4
AP5 GPP_B20/GSPI1_CLK GPP_D5/ISH_I2C0_SDA N3 RC207 EH5L1@
GSPI1_MOSI AN5 GPP_B21/GSPI1_MISO GPP_D6/ISH_I2C0_SCL 10K_0402_5%
@ T112 GPP_B22/GSPI1_MOSI N1 SD028100280
+3VS AB1 GPP_D7/ISH_I2C1_SDA N2
AB2 GPP_C8/UART0_RXD GPP_D8/ISH_I2C1_SCL RC213 EH5L1@
1 2 UART_2_CRXD_DTXD W4 GPP_C9/UART0_TXD AD11 10K_0402_5%
RC62 49.9K_0402_1% AB3 GPP_C10/UART0_RTS# GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12 SD028100280
1 2 UART_2_CTXD_DRXD GPP_C11/UART0_CTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
RC63 49.9K_0402_1% UART_2_CRXD_DTXD AD1
<24> UART_2_CRXD_DTXD GPP_C20/UART2_RXD
1 @ 2 UART_2_CRTS_DCTS UART_2_CTXD_DRXD AD2 U1 RAM_ID0
<24> UART_2_CTXD_DRXD UART_2_CRTS_DCTS GPP_C21/UART2_TXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA RAM_ID1
RC64 49.9K_0402_1% AD3 U2
1 @ 2 UART_2_CCTS_DRTS UART_2_CCTS_DRTS AD4 GPP_C22/UART2_RTS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3 RAM_ID2
RC65 49.9K_0402_1% GPP_C23/UART2_CTS# GPP_D15/ISH_UART0_RTS# U4 RAM_ID3 Project_ID1 Project_ID0
GPP_D16/ISH_UART0_CTS#/SML0BALERT# Project ID
I2C_0_SDA U7 AC1 GPP_D12 GPP_D11
2 I2C_0_SCL U6 GPP_C16/I2C0_SDA GPP_C12/UART1_RXD/ISH_UART1_RXD AC2 2
GPP_C17/I2C0_SCL GPP_C13/UART1_TXD/ISH_UART1_TXD AC3 EH7L1 0 0
I2C_1_SDA U8 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4
<Touch
<30>
PAD> <30>
I2C_1_SDA I2C_1_SCL U9 GPP_C18/I2C1_SDA GPP_C15/UART1_CTS#/ISH_UART1_CTS# EH5L1 0 1
+3VALW_PGPPC_E I2C_1_SCL GPP_C19/I2C1_SCL AY8
AH9 GPP_A18/ISH_GP0 BA8 1 0
AH10 GPP_F4/I2C2_SDA GPP_A19/ISH_GP1 BB7 G_INT#
+3VS GPP_F5/I2C2_SCL GPP_A20/ISH_GP2 BA7
G_INT# <26> 1 1
AH11 GPP_A21/ISH_GP3 AY7
RC126 1 @ 2 1K_0402_5% I2C_0_SDA AH12 GPP_F6/I2C3_SDA GPP_A22/ISH_GP4 AW7
RC127 1 @ 2 1K_0402_5% I2C_0_SCL GPP_F7/I2C3_SCL GPP_A23/ISH_GP5 AP13
AF11 GPP_A12/BM_BUSY#/ISH_GP6
RC128 1 2 2.2K_0402_5% I2C_1_SDA AF12 GPP_F8/I2C4_SDA
RC129 1 2 2.2K_0402_5% I2C_1_SCL GPP_F9/I2C4_SCL 6 OF 20
SKL-U_BGA1356
@
+3VS
+1.8VS_3VS_PGPPA +1.8VS
RC177
Memory Down Strap 0_0402_5% 2 ESPI@ 1
Functional Strap Definitions +3VALW_1.8VALW_PGPPD +3VALW_1.8VALW_PGPPD

+3VALW_1.8VALW_PGPPD +3VALW_1.8VALW_PGPPD
RC178
0_0402_5% 2 @ 1
GSPI0_MOSI /GPP_B18 (Internal Pull Down):
(Rising edge of PCH_PWROK)
1
No Reboot
RC151 RC150 RC153 RC224
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
* 0 = Disable No Reboot mode. --> AAX05 Use 2 NOX76@ NOX76@ NOX76@ NOX76@
2
RAM_ID0
3
1 = Enable No Reboot Mode. (PCH will disable the TCO RAM_ID1 3
RAM_ID2
Timer system reboot feature). This function is useful RAM_ID3
when running ITP/XDP.
1
1
RC155 RC225 RC226 RC227
GSPI1_MOSI / GPP_B22 (Internal Pull Down): 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
(Rising edge of PCH_PWROK) X76@ X76@ X76@ X76@
2
2
Boot BIOS Strap Bit
* 0 = SPI Mode --> AAX05 Use
1 = LPC Mode
RAM_ID3 RAM_ID2 *RAM_ID1 *RAM_ID0 PartNumber - Description

Hynix 4GB 0 0 0 0 SA0000BMN30 (S IC D4 512M16 H5AN8G6NCJR-VKC FBGA ABO!)
Micron 4GB 0 0 0 1 SA0000ARD60 (S IC D4 8G/2666 MT40A512M16LY-075:E ABO!)
Samsung 4GB 0 0 1 0 SA0000B6F30 (S IC D4 512M16 K4A8G165WC-BCTD FBGA ABO!)
0 0 1 1
No OnBoard No On Board Memory
Memory 1 1 1 1
4 4

KBL-U(6/12)GPIO
A B C D E
A B C D E
UC1H SKL-U
Rev_0.53
SSIC / USB3
PCIE/USB3/SATA
H8
USB3_1_RXN USB3_CRX_DTX_N1 <27>
G8
USB3_1_RXP USB3_CRX_DTX_P1 <27>
H13 C13 USB3 MB
G13 PCIE1_RXN/USB3_5_RXN USB3_1_TXN D13 USB3_CTX_DRX_N1 <27>
1 B17 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3_CTX_DRX_P1 <27> 1
A17 PCIE1_TXN/USB3_5_TXN J6
PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN USB3_CRX_DTX_N2 <28>
H6
USB3_2_RXP/SSIC_1_RXP USB3_CRX_DTX_P2 <28>
G11 B13
F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13 USB3_CTX_DRX_N2 <28>
D16 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP USB3_CTX_DRX_P2 <28> USB3 MB (reserve)
C16 PCIE2_TXN/USB3_6_TXN J10
PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN H10
H16 USB3_3_RXP/SSIC_2_RXP B15
PCIE3_RXN USB3_3_TXN/SSIC_2_TXN remove typeC USB
G16 A15
D17 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP
C17 PCIE3_TXN E10
PCIE3_TXP USB3_4_RXN F10
G15 USB3_4_RXP C15
F15 PCIE4_RXN USB3_4_TXN D15
B19 PCIE4_RXP USB3_4_TXP
A19 PCIE4_TXN AB9 USB20_N1
PCIE4_TXP USB2N_1 AB10 USB20_P1 USB20_N1 <27>
PCIE_CRX_DTX_N5 F16 USB2P_1 USB20_P1 <27> USB3 MB
<23> PCIE_CRX_DTX_N5 PCIE_CRX_DTX_P5 E16 PCIE5_RXN AD6 USB20_N2
<23> PCIE_CRX_DTX_P5 PCIE_CTX_DRX_N5 PCIE5_RXP USB2N_2 USB20_P2 USB20_N2 <28>
GLAN CC25 2 1 .1U_0402_16V7K C19 AD7 USB2.0 MB
<23> PCIE_CTX_C_DRX_N5 PCIE_CTX_DRX_P5 PCIE5_TXN USB2P_2 USB20_P2 <28>
CC26 2 1 .1U_0402_16V7K D19
<23> PCIE_CTX_C_DRX_P5 PCIE5_TXP AH3 USB20_N3
PCIE_CRX_DTX_N6 G18 USB2N_3 AJ3 USB20_P3 USB20_N3 <28>
<24> PCIE_CRX_DTX_N6 PCIE_CRX_DTX_P6 F18 PCIE6_RXN USB2P_3 USB20_P3 <28> SUB USB2.0
<24> PCIE_CRX_DTX_P6 1 2 .1U_0402_16V7K PCIE_CTX_DRX_N6 D20 PCIE6_RXP AD9 USB20_N4
NGFF WLAN+BT(Key E) <24> PCIE_CTX_C_DRX_N6
CC60
PCIE_CTX_DRX_P6 PCIE6_TXN USB2N_4 USB20_P4 USB20_N4 <28>
CC62 1 2 .1U_0402_16V7K C20 AD10 SUB/B Card reader (reserve) 11/13
<24> PCIE_CTX_C_DRX_P6 PCIE6_TXP USB2P_4 USB20_P4 <28>
F20 AJ1 USB20_N5
<26> SATA_CRX_DTX_N0 E20 PCIE7_RXN/SATA0_RXN USB2N_5 AJ2 USB20_P5 USB20_N5 <24>
<26> SATA_CRX_DTX_P0 B21 PCIE7_RXP/SATA0_RXP USB2P_5 USB20_P5 <24> BT
HDD <26> SATA_CTX_DRX_N0 PCIE7_TXN/SATA0_TXN
USB2
USB20_N6
A21 AF6
2 <26> SATA_CTX_DRX_P0 PCIE7_TXP/SATA0_TXP USB2N_6 AF7 USB20_P6 USB20_N6 <21> 2
G21 USB2P_6 USB20_P6 <21> TS
<26> SATA_CRX_DTX_N1 F21 PCIE8_RXN/SATA1A_RXN AH1 USB20_N7
<26> SATA_CRX_DTX_P1 D21 PCIE8_RXP/SATA1A_RXP USB2N_7 AH2 USB20_P7 USB20_N7 <21>
ODD <26> SATA_CTX_DRX_N1 PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 <21> Camera
C21
<26> SATA_CTX_DRX_P1 PCIE8_TXP/SATA1A_TXP AF8 USB20_N8
E22 USB2N_8 AF9 USB20_P8 USB20_N8 <30>
<24> PCIE_CRX_DTX_N9 E23 PCIE9_RXN USB2P_8 USB20_P8 <30> FP
<24> PCIE_CRX_DTX_P9 B23 PCIE9_RXP AG1
<24> PCIE_CTX_DRX_N9 A23 PCIE9_TXN USB2N_9 AG2
<24> PCIE_CTX_DRX_P9 PCIE9_TXP USB2P_9
F25 AH7
<24> PCIE_CRX_DTX_N10 E25 PCIE10_RXN USB2N_10 AH8
<24> PCIE_CRX_DTX_P10 D23 PCIE10_RXP USB2P_10 2015MOW10, USB2_ID Connected to GND Directly
<24> PCIE_CTX_DRX_N10 C23 PCIE10_TXN AB6 USB2_COMP RC119 1 2 113_0402_1%
<24> PCIE_CTX_DRX_P10 PCIE10_TXP USB2_COMP AG3 USB2_ID RC130 1 2 0_0402_5%
RC1201 2 100_0402_1% PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE RC131 1 2 0_0402_5%
PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE
NGFF SSD(Key M) #543016 PDG2.0 P.285 PCIE_RCOMPP USB_OC0#
A9
PCIE_RCOMPN/PCIE_RCOMPP +3VALW_PRIM XDP_PRDY# GPP_E9/USB2_OC0# USB_OC0# <27>
(Need Lane Reversal) @ T196 D56 C9
BO=4 W=12 S=12 R=100ohm XDP_PREQ# D61 PROC_PRDY# GPP_E10/USB2_OC1# D9
@ T197 PROC_PREQ# GPP_E11/USB2_OC2#
RC135 2 @ 1 10K_0402_5% TPM_PIRQ# BB11 B9
GPP_A7/PIRQA# GPP_E12/USB2_OC3# Unused OC pin need set to GPI. +3VALW_PRIM
<30> TPM_PIRQ# E28 J1
<24> PCIE_CRX_DTX_N11 E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2
<24> PCIE_CRX_DTX_P11 D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3 SSD_DEVSLP2 USB_OC0# RC132 1 2 10K_0402_5%
<24> PCIE_CTX_DRX_N11 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 SSD_DEVSLP2 <24>
C24
<24> PCIE_CTX_DRX_P11 E30 PCIE11_TXP/SATA1B_TXP H2
<24> PCIE_CRX_DTX_N12 F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3
<24> PCIE_CRX_DTX_P12 A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4 SATA_GP2
<24> PCIE_CTX_DRX_N12 B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 SATA_GP2 <24>
<24> PCIE_CTX_DRX_P12 PCIE12_TXP/SATA2_TXP H1 1 2
3 GPP_E8/SATALED# +3VS 3
8 OF 20 RH16
SKL-U_BGA1356 10K_0402_5%
@ M.2 SSD PCIE/SATA select pin
SSD_DET# (SATA_GP0)
SATA Device 0
PCIE Device 1
GPIO DEVICE CONTROL
USB_OC0# USB2 Port 1
USB_OC1# NA DEVSLP[2:0] Implementation

DEVSLP is a host-controlled hardware signal which enables a SATA host and device to
USB_OC2# NA enter an ultra-low interface power state, including the possibility to completely power
USB_OC3# NA down host and device PHYs.
The processor provides three SATA DEVSLP signals, DEVSLP[2:0] for SKL U.
DEVSLP0 NA ‧When hi gh, DEVSLP reWuests t he SATA devi ce t o ent er i nt o t he DEVSLP po wer st at e.
DEVSLP1 NA
‧When l o w, DEVSLP reWuests t he SATA devi ce t o eWit f r o mt he DEVSLP po wer st at e
and transition to active state.
DEVSLP2 NA SATA General Purpose (SATAGP[2:0]) Signals
‧The pr ocess or provi des t hree SATA general pur pose i nput si gnal s, SATAGP[ 2: 0] f or S KL U.
SATA_GP0 NA These signals can be configured as interlock switch inputs corresponding to a given SATA port.
NA ‧When used as an i nt erl oc k s wit c h st at us i ndi cati on, t hi s si gnal s houl d be dri ven t o 0
4
SATA_GP1 to indicate that the switch is closed and to a 1 to indicate that the switch is open. 4
SATA_GP2 NA
‧If mec hani cal presence s wit c hes will not be used on t he pl atf or m , SATAGP[ 2: 0]
signals can be configured as GPP_E[2:0] GPIOs signals.
2018/12/11
Compal Secret Data
2018/11/04 Title
KBL-U(7/12)PCIE,USB,SATA
A B C D E
A B C D E
+1.0VALW_PRIM TO +1.0V_VCCSTU / +1.0VCCST

+5VALW +1.0VALW_PRIM +1.0V_VCCSTU +1.2V_VDDQ +1.2V_VDDQ_CPU +VCCIO
UC1N SKL-U
Rev_0.53
CPU POWER 3 OF 4
JPC1
@
1U_0402_6.3V6K
22U_0603_6.3V6M
22U_0805_6.3V6M
1 1 1 2 AU23 AK28
VDDQ_AU23 VCCIO
CC98
CC97
1U_0402_6.3V6K
0.1U_0201_10V6K
CC96
1 1 @ AU28 AK30
VDDQ_AU28
2.73A VCCIO
1
CC134
CC135
JUMP_43X118 AU35 AL30
AU42 VDDQ_AU35 VCCIO AL42
2 2 BB23 VDDQ_AU42 VCCIO AM28
JPC2 6.35A
2
2 2 1 2 BB32 VDDQ_BB23 VCCIO AM30
@ BB41 VDDQ_BB32 VCCIO AM42
1 UC5 JUMP_43X118 BB47 VDDQ_BB41 VCCIO 1
CC105 2 1 .1U_0402_16V7K 1 14 BB51 VDDQ_BB47 AK23
VIN1 VOUT1 VDDQ_BB51 VCCSA +VCC_SA
2 13 AK25
VIN1 VOUT1 VCCSA G23
1 2 20K_0402_5% EN_1.0V_VCCSTU 3 12 1 2 AM40 VCCSA G25
RC142
ON1 CT1 +1.2V_VDDQC VDDQC
0.09A VCCSA
<29,32,38> SYSON CC95 G27
4 11 A18 VCCSA G28
VBIAS GND
1000P_0402_50V7K +1.0V_VCCST VCCST
0.04A VCCSA
6A J22
1 2 49.9K_0402_1% EN_1.8VS 5 10 1 2 A22 VCCSA J23
RC168
ON2 CT2 +1.0VS_VCCSTG VCCSTG_A22
0.04A VCCSA
<29,32,36,38> SUSP# CC94 J27
2 1 CC104 6 9 AL23 VCCSA K23
VIN2 VOUT2
1000P_0402_50V7K +1.2V_VCCSFR_OC VCCPLL_OC
0.26A VCCSA
.1U_0402_16V7K +1.8VALW_VS 7 8 K25
VIN2 VOUT2 +1.8VS K20 VCCSA K27
+1.0V_VCCSFR VCCPLL_K20
0.12A VCCSA
15 K21 K28
1 2 GPAD VCCPLL_K21 VCCSA K30
+1.8VALW_PRIM 1 2 VCCSA
AOZ1331DI_DFN14_2X3
VCCIO_SENSE
1U_0402_6.3V6K
JPC8 1 SA0000BEL00 1 AM23 T124 @
VCCIO_SENSE VSSIO_SENSE
CC99
JUMP_43X39 AM22 T125 @
@ CC100 VSSIO_SENSE
0.1U_0201_10V6K H21 VSSSA_SENSE
2 +1.8VALW_PRIM TO +1.8VS 2
14 OF 20VCCSA_SENSE
VSSSA_SENSE H20 VCCSA_SENSE VSSSA_SENSE <41>
VCCSA_SENSE <41>
SKL-U_BGA1356
@
PVT UC5 Change to SA0000BEL00 3/28
+1.0VALW_PRIM TO +1.0VS_VCCSTG
+1.0VALW_PRIM
2 +1.0VALW_PRIM_JP 2
JPC4 +1.2V_VDDQ_CPU +1.2V_VDDQC
1 2 PSC Side
1 2 +1.0VS_VCCSTG #543016 PDG2.0 P.750
+1.35V_VDDQC : 1x 10uF
1U_0402_6.3V6K
Imax : 3.44 A JUMP_43X79 1 RC208 1 @ 2 0_0402_5% CC47 1 2 10U_0603_6.3V6M

CC117
@ RC188 1 @ 2 0_0402_5%
For Power consumption UC6
Measurement 1
2 2 VIN1 +VCCIO +1.0V_VCCSTU +1.0V_VCCST
+5VALW VIN2 @ JPC5 PSC Side
CC107 @ 7 6 +1.0VS_VCCSTG_IO 1 2 @ #543016 PDG2.0 P.750
VIN thermal VOUT 1 2
0.1U_0201_10V6K
2 1 3 JUMP_43X79 Imax : 3.4 A
RC140 1 @ 2 0_0402_5% CC48 1 2 1U_0201_6.3V6M +1.0V_VCCST : 1x 1uF
VBIAS 1
CC147 1 2 10U_0402_6.3V6M
SUSP# NMSB@ 1 2 SUSP#_R1 4 5 CC127
0_0402_5% RC186 ON GND 0.1U_0201_10V6K
2
1U_0402_6.3V6K
EN_VCCSTG_VCCPLL_OC MSB@2 0_0402_5% 1

CC106
1 AOZ1334DI-02_DFN8-7_3X3 +1.0V_VCCSFR PSC Side

RC271
@ Rds_on 3.6m ohm @ #543016 PDG2.0 P.750
2 Rise time 0.5ms RC143 1 @ 2 0_0402_5% CC55 1 2 1U_0201_6.3V6M +1.0V_VCCSFR : 1x 1uF Reference GND as possible.
CC148 1 2 10U_0402_6.3V6M
+3VALW_PRIM
+1.2V_VDDQ_CPU +1.2V_VCCSFR_OC BSC Side
Resevre Modern standby function 11/15 #543016 PDG2.0 P.750
1 NMSB@
CC138
RC274
1 2
0_0402_5%
CC49 1 2 1U_0201_6.3V6M +1.35V_VCCSFR_OC : 1x 1uF
0.1U_0201_10V6K
SUSP# RC2701 MSB@2 0_0402_5% MSB@ CC150 1 2 1U_0201_6.3V6M
3 2 Change to 0om 11/15 3
5
UC10
1
P
B 4
2 Y EN_VCCSTG_VCCPLL_OC <15>
A
BSC Side
G
MSB@
PM_SLP_S0# RC2691 MSB@2 0_0402_5% MSB@ +1.0VS_VCCSTG CC56 1 2 1U_0201_6.3V6M #543016 PDG2.0 P.750
<11,29,30> PM_SLP_S0#
3
TC7SH08FUF_SSOP5
MSB@ 100K_0402_5%
RC278
+1.0V_VCCSTG : 1x 1uF (Placeholder)
SA007080120
2
+VCCIO +1.2V_VDDQ_CPU
DVT 02/07 BSC Side PSC Side PSC Side BSC Side
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
@ @
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
1
CC59
CC37
CC41
CC54
CC58
CC38
CC39
CC40
CC42
@ @ @ @
CC43
CC44
CC45
CC46
@
2
2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CC149
CC27
CC28
CC33
CC34
CC35
CC36
4 #543016 PDG2.0 P.750 #543016 PDG2.0 P.750 4
+VCCIO : 4x 1uF 0402 +1.35V_VDDQ_CPU :

4x 10uF 0402
3x 22uF 0603
2018/12/11
Compal Secret Data
2018/12/11 Title
KBL-U(8/12)Power
A B C D E
A B C D E
+3VALW_PRIM
+1.0VALW_PRIM UC1O SKL-U
Rev_0.53 +3VALW_1.8VALW_PGPPA +1.8VALW_PRIM
CPU POWER 4 OF 4
CC91 2 1 @
+1.0VALW_MPHYAON
CC87 near K17 (<3 mm) 1U_0201_6.3V6M AB19
+1.0VALW_PRIM AB20 VCCPRIM_1P0 AK15 0_0402_5% 2 ESPI@ 1 RC196
Near AB19 (<10 mm) 0.89A +3VALW_1.8VALW_PGPPA SPI Touch
CC152 near K17 P18 VCCPRIM_1P0 VCCPGPPA AG15 +3VALW_PGPPB 0_0402_5% 2 @ 1 RC197
RC175 1 @ 2 0_0402_5% 1 2 VCCPRIM_1P0 VCCPGPPB Y16
+1.0VALW_PRIM VCCPGPPC +3VALW_PGPPC_E
CC87 1U_0201_6.3V6M AF18 Y15 +3VALW_1.8VALW_PGPPD
Y16,T16 Change netname 12/05
1 2 CC76 2 1 @ AF19 VCCPRIM_CORE VCCPGPPD T16
2.57A +3VALW_PGPPC_E
CC153 1U_0201_6.3V6M 1U_0201_6.3V6M V20 VCCPRIM_CORE VCCPGPPE AF16 +3VALW_PGPPB +3VALW_PRIM
VCCPRIM_CORE VCCPGPPF +1.8VALW_PRIM
near AF18 (<10 mm) V21 AD15 +3VALW_PGPPG
+1.0VALW_PRIM +1.0VALW_APLL VCCPRIM_CORE VCCPGPPG No use @
2 DCPDSW_1P0 AL1
1 V19 CC102 2 1 0_0402_5% 2 @ 1 RC161
DCPDSW_1P0 VCCPRIM_3P3_V19 +3VALW_PRIM
1U_0201_6.3V6M CC85 1U_0201_6.3V6M
RC148 1 @ 2 0_0603_5% 1 2 CC123 K17 T1
1
10U_0402_6.3V6M
+1.0VALW_MPHYAON
L1 VCCMPHYAON_1P0 VCCPRIM_1P0_T1 +1.0VALW_DTS CC102 near AG15 (<3 mm) 1
VCCMPHYAON_1P0 AA1 +3VALW_PGPPC_E +3VALW_PRIM

VCCATS_1P8 +1.8VALW_PRIM
1 2 CC144 +1.0VALW_MPHYGT N15
0.1U_0201_10V6K N16 VCCMPHYGT_1P0_N15 AK17 @
+3VALW VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3 +3VALW_RTC
+3VALW_DSW N17 HSIO CC73 2 1 0_0402_5% 2 @ 1 RC163
Add CC144 11/16 P15 VCCMPHYGT_1P0_N17 AK19 1U_0201_6.3V6M
2.1A +RTCVCC
P16 VCCMPHYGT_1P0_P15 VCCRTC_AK19 BB14
RC173 1 @ 2 0_0402_5% VCCMPHYGT_1P0_P16 VCCRTC_BB14 CC73 near Y16 (<10 mm)
K15 BB10 CC71 1 2 0.1U_0201_10V6K +3VALW_1.8VALW_PGPPD +3VALW_PRIM
+1.0VALW_AMPHYPLL VCCAMPHYPLL_1P0 HSIO DCPRTC +1.8VALW_PRIM
L15
VCCAMPHYPLL_1P0 A14
+3VALW_PRIM +3VALW_HDA VCCCLK1 +1.0VALW_CLK6_24TBT
+1.0VALW_APLL V15 0_0402_5% 1 @ 2 RC206
@ VCCAPLL_1P0 K19 2 1 0_0402_5% 2 @ 1 RC172
VCCCLK2 +1.0VALW_VCCCLK2
RC198 1 @ 2 0_0402_5% 1 2 +1.0VALW_PRIM AB17 1U_0201_6.3V6M CC103
CC63 0.1U_0201_10V6K Y18 VCCPRIM_1P0_AB17 L21
VCCPRIM_1P0_Y18 VCCCLK3 +1.0VALW_APLL +3VALW_PRIM
+3VALW_PGPPC_E
CC63 near AJ19 (<10 mm) AD17 N20
+3VALW_DSW VCCDSW_3P3_AD17 VCCCLK4 +1.0VALW_CLK4_F100OC
+3VALW_SPI AD18 @
AJ17 VCCDSW_3P3_AD18 L19 CC74 2 1 0_0402_5% 2 @ 1 RC167
VCCDSW_3P3_AJ17 VCCCLK5 +1.0VALW_CLK5_F24NS
RC154 1 @ 2 0_0402_5% 1U_0201_6.3V6M
+3VALW_HDA AJ19 A10 +1.0VALW_CLK6_24TBT CC74 near T16 (<10 mm)
VCCHDA VCCCLK6
AJ16 AN11 PRIMCORE_VID0 +3VALW_PRIM
+3VALW_SPI VCCSPI GPP_B0/CORE_VID0 PRIMCORE_VID1 T136 @
AN13 +3VALW_PGPPG
GPP_B1/CORE_VID1 T138 @
+1.0VALW_SRAM AF20 @
AF21 VCCSRAM_1P0 HSIO CC83 2 1 0_0402_5% 2 @ 1 RC187
T19 VCCSRAM_1P0 1U_0201_6.3V6M
+3VALW +3VALW_PRIM T20 VCCSRAM_1P0
JPC7 VCCSRAM_1P0 @
1 2 +3VALW_PRIM AJ21 1U_0201_6.3V6M 2 1 CC67 +3VALW_PRIM
1 2 VCCPRIM_3P3_AJ21
JUMP_43X39 AK20
@
+1.0VALW_PRIM VCCPRIM_1P0_AK20 CC67 near V19 (<3 mm)
N18 +1.0VALW_DTS +1.0VALW_PRIM
2 +1.0VALW_APLLEBB VCCAPLLEBB 2
HSIO 15 OF 20
0.1U_0201_10V6K 2 1 CC158 2 @ 1 RC162
SKL-U_BGA1356 0_0402_5%
@
1U_0201_6.3V6M 2 1 CC72 +1.8VALW_PRIM
1U_0402_6.3V6K 2 1 CC157
@ reserve CC157 12/21
CC72 near AA1 (<10 mm) +3VALW_RTC +3VALW_PRIM
Resevre Modern standby 11/21
CC78 2 1 0_0402_5% 2 @ 1 RC171
0.1U_0201_10V6K
+1.2V_VDDQ_CPU TO +1.2V_VCCSFR_OC 2 1
+5VALW +1.2V_VDDQ_CPU 1U_0201_6.3V6M CC77
CC77,CC78 near AK17 (<3 mm)
+1.0VALW_CLK6_24TBT +1.0VALW_PRIM
+1.2V_VCCSFR_OC @
1U_0402_6.3V6K
1 CC86 2 1 0_0402_5% 2 @ 1 RC169

CC146
1U_0402_6.3V6K
1 1U_0201_6.3V6M
CC101
UC11 MSB@
1
CC86 near A10 (<3 mm)
MSB@ VIN1
2 @ 2
2 VIN2 +1.0VALW_VCCCLK2 +1.0VALW_PRIM
7 6 +1.2V_VCCSFR_OC_R 1 2 @
VIN thermal VOUT 0_0402_5% MSB@ CC75 2 1 0_0603_5% 2 @ 1 RC164
BSC Side
3 RC159 1U_0201_6.3V6M
VBIAS
1U_0402_6.3V6K
1 CC124 2 1
EN_VCCSTG_VCCPLL_OC
CC139
4 5 22U_0603_6.3V6M @
<14> EN_VCCSTG_VCCPLL_OC ON GND MSB@
TPS22961DNYR_WSON8 2 +1.0VALW_CLK4_F100OC +1.0VALW_PRIM

3 3
I(Max) : 120m A(+VCCPLL_OC) CC125 2 1 0_0603_5% 2 @ 1 RC190
RON(Max) : 6.2 mohm 22U_0603_6.3V6M @
V drop : 0.019 V +1.0VALW_PRIM
+1.0VALW_CLK5_F24NS
2 1 0_0603_5% 2 @ 1 RC152
1U_0201_6.3V6M CC145
2 1
22U_0603_6.3V6M CC154
#543016 PDG2.0 P.764
+1.0VALW_MPHYPLL
CC80 near N15 (<3mm)
+1.0VALW_PRIM HSIO +1.0VALW_MPHYGT CC82 near N15 (<10mm)
Imax : 3.5 A CC152 near N15
JPC9 @
1 2 RC209 1 @ 2 0_0603_5% CC82 1 2 22U_0603_6.3V6M
#543016 PDG2.0 P.470
1 2
JUMP_43X79 1 2 #543016 PDG2.0 P.758
VCCRTC does not exceed 3.2 V. RTC Battery +RTCBATT
@ CC80 1U_0201_6.3V6M JRTC1

1 2 +1.0VALW_PRIM +3VALW_PRIM +1.8VALW_PRIM 1
CC152 1U_0201_6.3V6M
Power Rail Voltage 2 1
+1.0VALW_AMPHYPLL +RTCBATT 2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
RH163 3
+CHGRTC 3.383V(MAX) 1K_0402_5% DC1 +RTCVCC 4 GND
CC61 near K15 (<3 mm) 1 1 1 1 1 1 GND
CC111
CC112
CC113
CC114
CC116
CC115
1 2 3
RC149 1 2 0_0603_5% CC61 1 2 1U_0201_6.3V6M
@ @ @ @ @ @ @
BAT54C(VF) 240 mV 1
ACES_50271-0020N-001
2 2 2 2 2 2 CONN@
CC155 1 2 22U_0603_6.3V6M 1
@
+RTCVCC 3.143V +CHGRTC 2
CC84
SP02000RO00
0.1U_0201_10V6K
+1.0VALW_SRAM CHN202UPT_SC70-3 2
Result : Pass
4 CC122 near AF20 (<10mm) 4
RC176 1 @ 2 0_0603_5% CC122 1 2 1U_0201_6.3V6M

@
+1.0VALW_APLLEBB
CC68 near N18 (<3mm)
RC156 1 @ 2 0_0402_5% CC68 1 2 1U_0201_6.3V6M
Vinafix.com CC133 1 2 0.1U_0201_10V6K
KBL-U(9/12)Power
CC151 1 2 1U_0201_6.3V6M AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A B C D E
A B C D E
#544924 SKL EDS1.2 P.136

VCCGT U(15W)-dual core GT2 31A(MAX)
0.55-1.5V
+VCC_GT +VCC_GT
UC1M SKL-U
#544924 SKL EDS1.2 P.134 Rev_0.53
VCC U(15W)-dual core GT2 29A(MAX) +VCC_GT_VCORE CPU POWER 2 OF 4
0.55-1.52V VCCGT
N70
+VCC_CORE +VCC_CORE A48 N71
A53 VCCGT VCCGT R63
1 UC1L SKL-U
+VCC_GT_VCORE (10pin) A58 VCCGT VCCGT R64 1
Rev_0.53 U22 --> +VCC_GT A62 VCCGT VCCGT R65
CPU POWER 1 OF 4 VCCGT VCCGT
U42 --> +VCC_CORE A66
VCCGT VCCGT
R66
A30 G32 AA63 R67
A34 VCC_A30 VCC_G32 G33 AA64 VCCGT VCCGT R68
AK33 VCC_A44 VCC_G37 G38 AA69 VCCGT VCCGT R71
AK35 VCC_AK33 VCC_G38 G40 AA70 VCCGT VCCGT T62
AK37 VCC_AK35 VCC_G40 G42 AA71 VCCGT VCCGT U65
AK38 VCC_AK37 VCC_G42 J30 AC64 VCCGT VCCGT U68
AK40 VCC_AK38 VCC_J30 J33 AC65 VCCGT VCCGT U71
AL33 VCC_AK40 VCC_J33 J37 AC66 VCCGT VCCGT W63
AL37 VCC_AL33 VCC_J37 J40 AC67 VCCGT VCCGT W64
AL40 VCC_AL37 VCC_J40 K33 AC68 VCCGT VCCGT W65
AM32 VCC_AL40 VCC_K33 K35 AC69 VCCGT VCCGT W66
AM33 VCC_AM32 VCC_K35 K37 AC70 VCCGT VCCGT W67
AM35 VCC_AM33 VCC_K37 K38 AC71 VCCGT VCCGT W68
+VCC_GTX_VCORE(12 pin)
AM37 VCC_AM35 VCC_K38 K40 J43 VCCGT VCCGT W69 U22 --> NC
AM38 VCC_AM37 VCC_K40 K42 J45 VCCGT VCCGT W70 U42 --> +VCC_CORE
G30 VCC_AM38 VCC_K42 K43 J46 VCCGT VCCGT W71
VCC_G30 VCC_K43 VCCGT VCCGT U23e-> +VCC_GT
J48 Y62
K32 E32
Trace Length < 25 mils J50 VCCGT VCCGT +VCC_GTX_VCORE
RSVD_K32 VCC_SENSE E33 VCCSENSE <41> J52 VCCGT
AK32 VSS_SENSE VSSSENSE <41> J53 VCCGT AK42
#544924 SKL EDS1.2 P.141 RSVD_AK32 SOC_SVID_ALERT# VCCGT VCCGTX_AK42
VCCOPC 1.0V 3.2A B63 J55 AK43
AB62 VIDALERT# A63 SOC_SVID_CLK +VCC_GT J56 VCCGT VCCGTX_AK43 AK45
VCC_OPC_1P8 1.8V 50mA VCCOPC_AB62 VIDSCK SOC_SVID_DAT SOC_SVID_CLK <41> VCCGT VCCGTX_AK45
P62 D64 J58 AK46
VCCEOPIO 0.8V,1.0V 2A V62 VCCOPC_P62 VIDSOUT J60 VCCGT VCCGTX_AK46 AK48
VCCOPC_V62 G20 +1.0VS_VCCSTG RC229 K48 VCCGT VCCGTX_AK48 AK50
H63 VCCSTG_G20 0_0402_5% K50 VCCGT VCCGTX_AK50 AK52 VCCGTX_AK52
VCC_OPC_1P8_H63 +VCC_GT_K52 VCCGT VCCGTX_AK52 @ T248
For CPU2+3e SKU 1 @ 2 K52 AK53
2 VCCGT VCCGTX_AK53 +VCC_GTX_GT 2
G61 K53 AK55
VCC_OPC_1P8_G61 K55 VCCGT VCCGTX_AK55 AK56
VCCOPC_SENSE AC63
+1.0VS(SUSP#) 569110 U42/U22 common K56 VCCGT VCCGTX_AK56 AK58
T132 @ VSSOPC_SENSE VCCOPC_SENSE baord K52/AK52 NC VCCGT VCCGTX_AK58
AE63 K58 AK60
T133 @ VSSOPC_SENSE VCCGT VCCGTX_AK60
K60 AK70
AE62 L62 VCCGT VCCGTX_AK70 AL43
CPU2+3e fuse down SKU
AG62 VCCEOPIO L63 VCCGT VCCGTX_AL43 AL46
VCCEOPIO L64 VCCGT VCCGTX_AL46 AL50
+VCC_GTX_GT (16 pin)
VCCEOPIO_SENSE AL63 L65 VCCGT VCCGTX_AL50 AL53 U22 / U42--> NC
T137 @ VCCEOPIO_SENSE VCCGT VCCGTX_AL53
T139 @
VSSEOPIO_SENSE AJ62 L66 AL56 U23e-> +VCC_GT
VSSEOPIO_SENSE 12 OF 20 L67 VCCGT VCCGTX_AL56 AL60
L68 VCCGT VCCGTX_AL60 AM48
SKL-U_BGA1356 L69 VCCGT VCCGTX_AM48 AM50
@ L70 VCCGT VCCGTX_AM50 AM52
L71 VCCGT VCCGTX_AM52 AM53
M62 VCCGT VCCGTX_AM53 AM56
N63 VCCGT VCCGTX_AM56 AM58
N64 VCCGT VCCGTX_AM58 AU58
N66 VCCGT VCCGTX_AU58 AU63
N67 VCCGT VCCGTX_AU63 BB57
N69 VCCGT VCCGTX_BB57 BB66
VCCGT VCCGTX_BB66
VCCGT_SENSE J70 AK62 VCCGTX_SENSE
<41> VCCGT_SENSE VSSGT_SENSE VCCGT_SENSE VCCGTX_SENSE T155 @
J69 AL61 VSSGTX_SENSE T219 @
<41> VSSGT_SENSE VSSGT_SENSE VSSGTX_SENSE
+1.0V_VCCST 13 OF 20
#543016 PDG2.0 P.273 Trace Length < 25 mils SKL-U_BGA1356
@
1
RC179 RC181
56_0402_5% 100_0402_1%
3 3
Place the PU
resistors close to CPU
2
RC180
220_0402_5%
SOC_SVID_ALERT# 1 2
SOC_SVID_ALERT#_R <41>
SOC_SVID_DAT To VR
SOC_SVID_DAT <41>
4 4
2018/12/11
Compal Secret Data
2018/12/11 Title
KBL-U(10/12)Power,SVID
A B C D E
A B C D E
1 1
UC1P SKL-U UC1Q SKL-U
Rev_0.53 Rev_0.53 UC1R SKL-U
GND 1 OF 3 GND 2 OF 3
GND 3 OF 3 Rev_0.53
A5 AL65 AT63 BA49 F8 L18
A67 VSS VSS AL66 AT68 VSS VSS BA53 G10 VSS VSS L2
A70 VSS VSS AM13 AT71 VSS VSS BA57 G22 VSS VSS L20
AA2 VSS VSS AM21 AU10 VSS VSS BA6 G43 VSS VSS L4
AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8
AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10
AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13
AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19
AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21
AD13 VSS VSS AM68 AV71 VSS VSS BB43 G63 VSS VSS P17
AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
AD19 VSS VSS AM8 AW12 VSS VSS BB6 H15 VSS VSS P20
AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
AD62 VSS VSS AN28 AW18 VSS VSS BB67 J11 VSS VSS R6
AD8 VSS VSS AN30 AW21 VSS VSS BB70 J13 VSS VSS T15
AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21
AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
2 AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10 2
AF1 VSS VSS AN42 AW36 VSS VSS D18 J8 VSS VSS U63
AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
AF17 VSS VSS AP10 AW43 VSS VSS D26 K22 VSS VSS U67
AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17
AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
AH6 VSS VSS AP70 AW66 VSS VSS D66 L17 VSS VSS Y21
AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
AH64 VSS VSS AR15 AY66 VSS VSS E11
AH67 VSS VSS AR16 B10 VSS VSS E15 18 OF 20
AJ15 VSS VSS AR20 B14 VSS VSS E18
AJ18 VSS VSS AR23 B18 VSS VSS E21 SKL-U_BGA1356
AJ20 VSS VSS AR28 B22 VSS VSS E46 @
AJ4 VSS VSS AR35 B30 VSS VSS E50
AK11 VSS VSS AR42 B34 VSS VSS E53
3 AK27 VSS VSS AR5 B58 VSS VSS F1 3
AK63 VSS VSS AR50 B62 VSS VSS F13
AK8 VSS VSS AR55 BA1 VSS VSS F23
AL2 VSS VSS AR58 BA10 VSS VSS F27
AL35 VSS VSS AT2 BA2 VSS VSS F33
AL52 VSS VSS AT4 F68 VSS VSS F40
AL58 VSS VSS AT56 VSS VSS BA41
AL64 VSS VSS AT58 VSS
VSS VSS
16 OF 20 17 OF 20
SKL-U_BGA1356 SKL-U_BGA1356
@ @
4 4

KBL-U(11/12)GND
A B C D E
A B C D E
1 1
UC1S SKL-U
Rev_0.53
RESERVED SIGNALS-1
@ T167 CFG0 E68 BB68 T156 @

CFG1 B67 CFG[0] RSVD_TP_BB68 BB69
@ T168 CFG[1] RSVD_TP_BB69 T157 @
@ T169 CFG2 D65
CFG3 D67 CFG[2] AK13
@ T170 CFG[3] RSVD_TP_AK13 T158 @
@ T171 CFG4 E70 AK12 T159 @
CFG5 C68 CFG[4] RSVD_TP_AK12
@ T172 CFG[5]
@ T173 CFG6 D68 BB2
CFG7 C67 CFG[6] RSVD_BB2 BA3
@ T174 CFG[7] RSVD_BA3
@ T175 CFG8 F71
CFG9 G69 CFG[8]
@ T176 CFG[9]
@ T177 CFG10 F70 AU5 T162 @
CFG11 G68 CFG[10] TP5 AT5
@ T178 CFG[11] TP6 T163 @
@ T179 CFG12 H70
CFG13 G71 CFG[12]
@ T180 CFG[13]
@ T181 CFG14 H69 D5
CFG15 G70 CFG[14] RSVD_D5 D4 UC1T SKL-U
@ T182 CFG[15] RSVD_D4 B2
RSVD_B2 Rev_0.53
@ T183 CFG16 E63 C2 SPARE
CFG17 F63 CFG[16] RSVD_C2
@ T184 CFG[17] B3 AW69 F6
CFG18 E66 RSVD_B3 A3 AW68 RSVD_AW69 RSVD_F6 E3 SOC_XTAL24_IN_U42
@ T186 CFG[18] RSVD_A3 RSVD_AW68 RSVD_E3
@ T188 CFG19 F66 AU56 C11
CFG[19] AW1 AW48 RSVD_AU56 RSVD_C11 B11
CFG_RCOMP E60 RSVD_AW1 SOC_XTAL24_OUT_U42 C7 RSVD_AW48 RSVD_B11 A11
CFG_RCOMP E1 U12 RSVD_C7 RSVD_A11 D12
XDP_ITP_PMODE E8 RSVD_E1 E2 U11 RSVD_U12 RSVD_D12 C12
2
@ T189 ITP_PMODE RSVD_E2 RSVD_U11 RSVD_C12 2
H11 F52
AY2 BA4 RSVD_H11 RSVD_F52
AY1 RSVD_AY2 RSVD_BA4 BB4 20 OF 20
RSVD_AY1 RSVD_BB4 Remove CC79, RC57 12/21
D1 A4 SKL-U_BGA1356
D3 RSVD_D1 RSVD_A4 C4 @
RSVD_D3 RSVD_C4
K46 BB5 T199 @
K45 RSVD_K46 TP4
RSVD_K45 A69
AL25 RSVD_A69 B69
AL27 RSVD_AL25 RSVD_B69
RSVD_AL27 AY3 RC182 1 @ 2 0_0402_5%
C71 RSVD_AY3
B70 RSVD_C71 D71
RSVD_B70 RSVD_D71 C70
F60 RSVD_C70
RSVD_F60 C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54
BA70 AY4
For 2+3e Solut i on
T213 @ RSVD_TP_BA70 TP1 T214 @
BA68 BB3 T216 @
T215 @ RSVD_TP_BA68 TP2 PM_ZVM#
J71 AY71 RC183 1 @ 2 0_0402_5% Zero Voltage Mode: Control Signal to OPC
2 1 CFG_RCOMP RC237 J68 RSVD_J71 VSS_AY71 AR56 PM_ZVM#
49.9_0402_1% RC185 0_0201_5% RSVD_J68 ZVM# T225 @ VR, when low OPC VR output is 0V.
1 @ 2 F65 AW71 T221 @
2 1 CFG4 G65 VSS_F65 RSVD_TP_AW71 AW70 PM_MSM#
VSS_G65 RSVD_TP_AW70 T223 @
1K_0402_1% RC193 Minimum Speed Mode: Control signal to
F61 AP56 PM_MSM# +1.0V_VCCST
E61 RSVD_F61 MSM# C64
T230 @ VccEOPIO VR (connected only in 2 VR
RSVD_E61 PROC_SELECT# solut i on f or OPC).
3 19 OF 20 SKL_CNL# 1 @ 2 3
RC184 100K_0402_5%
SKL-U_BGA1356
@ #544669 CRB1.1 P.54
#544924 SKL EDS1.2 P.125
PROC_SELECT#
Display Port Presence Strap This pin is for compatibility with future
platforms. It should be unconnected for
1 : Disabled; No Physical Display Port the processor.
CFG4 at t ac hed t o E mbedded Dis pl ay Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port 568813_KBL_U42 Rev0.5
PVT 03/20
SOC_XTAL24_IN_U42 RC233 1 U42@ 2 33_0402_1% SOC_XTAL24_IN_U42_R
SOC_XTAL24_OUT_U42 RC234 1 U42@ 2 33_0402_1% SOC_XTAL24_OUT_U42_R 1 U42@ 2

RC228 1M_0402_5%
YC3 U42@
563377 Intel MOW 33 24MHZ_18PF_XRCGB24M000F2P51R0
3 1
3 1
NC NC
1 1
4 2
4 CC128 CC129 4
U42@ 2 U42@ 2
27P_0402_50V8J 27P_0402_50V8J
DVT 02/08
2018/12/11
Compal Secret Data
2018/12/11 Title
KBL-U(12/12)RSVD
A B C D E
5 4 3 2 1
+DDR_VREF_CA +DDR_VREF_CA
+DDR_VREF_CA +DDR_VREF_CA
U2 U3
20mils 20mils U4 U5
M1 G2 DDR_A_D5 M1 G2 DDR_A_D25
VREFCA DQL0 DDR_A_D6 VREFCA DQL0 DDR_A_D29 20mils DDR_A_D40 20mils DDR_A_D56
0.047U_0402_25V7K
0.047U_0402_25V7K
F7 F7 M1 G2 M1 G2
DQL1 DDR_A_D1 DQL1 DDR_A_D27 VREFCA DQL0 DDR_A_D43 VREFCA DQL0 DDR_A_D58
0.047U_0402_25V7K
0.047U_0402_25V7K
H3 H3 F7 F7
DDR_A_MA0 P3 DQL2 H7 DDR_A_D2 DDR_A_MA0 P3 DQL2 H7 DDR_A_D26 DQL1 H3 DDR_A_D44 DQL1 H3 DDR_A_D57
A0 DQL3 A0 DQL3 DQL2 DQL2
1
DDR_A_MA1 DDR_A_D4
1
P7 H2 DDR_A_MA1 P7 H2 DDR_A_D24 DDR_A_MA0 P3 H7 DDR_A_D42 DDR_A_MA0 P3 H7 DDR_A_D59
CD124
CD125
DDR_A_MA2 A1 DQL4 DDR_A_D7 DDR_A_MA2 A1 DQL4 DDR_A_D31 A0 DQL3 A0 DQL3
1
DDR_A_MA1 DDR_A_D41
1
R3 H8 R3 H8 P7 H2 DDR_A_MA1 P7 H2 DDR_A_D61
CD126
CD127
DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D0 DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D28 DDR_A_MA2 R3 A1 DQL4 H8 DDR_A_D46 DDR_A_MA2 R3 A1 DQL4 H8 DDR_A_D62
2
MEM@ DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D3 MEM@ DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D30 DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D45 DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D60
2
DDR_A_MA5 P8 A4 DQL7 DDR_A_MA5 P8 A4 DQL7 MEM@ DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D47 MEM@ DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D63
DDR_A_MA6 P2 A5 DDR_A_MA6 P2 A5 DDR_A_MA5 P8 A4 DQL7 DDR_A_MA5 P8 A4 DQL7
DDR_A_MA7 R8 A6 A3 DDR_A_D13 DDR_A_MA7 R8 A6 A3 DDR_A_D16 DDR_A_MA6 P2 A5 DDR_A_MA6 P2 A5
DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D14 DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D18 DDR_A_MA7 R8 A6 A3 DDR_A_D37 DDR_A_MA7 R8 A6 A3 DDR_A_D52
D DDR_A_MA9 A8 DQU1 DDR_A_D9 DDR_A_MA9 A8 DQU1 DDR_A_D17 DDR_A_MA8 A7 DQU0 DDR_A_D39 DDR_A_MA8 A7 DQU0 DDR_A_D55 D
R7 C3 R7 C3 R2 B8 R2 B8
DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D15 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D23 DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D32 DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D53
DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D8 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D20 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D35 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D54
DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D10 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D22 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D34 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D49
DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D12 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D21 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D33 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D50
DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D11 DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D19 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D36 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D48
A14/WE DQU7 A14/WE DQU7 DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D38 DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D51
DDR_A_BA0 N2 DDR_A_BA0 N2 A14/WE DQU7 A14/WE DQU7
<8> DDR_A_BA0 DDR_A_BA1 BA0 DDR_A_BA1 BA0 DDR_A_BA0 DDR_A_BA0
<8> DDR_A_BA1 N8 B3 +1.2V_VDDQ N8 B3 +1.2V_VDDQ N2 N2 +1.2V_VDDQ
BA1 VDD B9 BA1 VDD B9 DDR_A_BA1 N8 BA0 B3 DDR_A_BA1 N8 BA0 B3
VDD VDD BA1 VDD +1.2V_VDDQ BA1 VDD
+1.2V_VDDQ E2 D1 +1.2V_VDDQ E2 D1 B9 B9
E7 DMU/DBIU VDD G7 E7 DMU/DBIU VDD G7 E2 VDD D1 E2 VDD D1
DML/DBIL VDD DML/DBIL VDD +1.2V_VDDQ DMU/DBIU VDD +1.2V_VDDQ DMU/DBIU VDD
J1 J1 E7 G7 E7 G7
VDD J9 VDD J9 DML/DBIL VDD J1 DML/DBIL VDD J1
VDD L1 VDD L1 VDD J9 VDD J9
DDR_A_CLK0 K7 VDD L9 DDR_A_CLK0 K7 VDD L9 VDD L1 VDD L1
<8> DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD DDR_A_CLK#0 CK_t VDD DDR_A_CLK0 VDD DDR_A_CLK0 VDD
<8> DDR_A_CLK#0 K8 R1 K8 R1 K7 L9 K7 L9
DDR_A_CKE0 K2 CK_c VDD T9 DDR_A_CKE0 K2 CK_c VDD T9 DDR_A_CLK#0 K8 CK_t VDD R1 DDR_A_CLK#0 K8 CK_t VDD R1
<8> DDR_A_CKE0 CKE VDD CKE VDD DDR_A_CKE0 CK_c VDD DDR_A_CKE0 CK_c VDD
K2 T9 K2 T9
CKE VDD CKE VDD
A1 A1
VDDQ A9 VDDQ A9 A1 A1
VDDQ C1 VDDQ C1 VDDQ A9 VDDQ A9
VDDQ D9 VDDQ D9 VDDQ C1 VDDQ C1
VDDQ F2 VDDQ F2 VDDQ D9 VDDQ D9
VDDQ F8 VDDQ F8 VDDQ F2 VDDQ F2
DDR_A_ODT0 K3 VDDQ G1 DDR_A_ODT0 K3 VDDQ G1 VDDQ F8 VDDQ F8
<8> DDR_A_ODT0 DDR_A_CS#0 ODT VDDQ DDR_A_CS#0 ODT VDDQ DDR_A_ODT0 VDDQ DDR_A_ODT0 VDDQ
<8> DDR_A_CS#0 L7 G9 L7 G9 K3 G1 K3 G1
DDR_A_MA16 L8 CS VDDQ J2 DDR_A_MA16 L8 CS VDDQ J2 DDR_A_CS#0 L7 ODT VDDQ G9 DDR_A_CS#0 L7 ODT VDDQ G9
DDR_A_MA15 M8 RAS VDDQ J8 DDR_A_MA15 M8 RAS VDDQ J8 DDR_A_MA16 L8 CS VDDQ J2 DDR_A_MA16 L8 CS VDDQ J2
CAS VDDQ CAS VDDQ DDR_A_MA15 M8 RAS VDDQ J8 DDR_A_MA15 M8 RAS VDDQ J8
B2 RD206 B2 RD207 CAS VDDQ CAS VDDQ
VSS 10mils VSS 10mils
E1 240_0402_1% E1 240_0402_1% B2 10mils RD208 B2 10mils
VSS E9 VSS_E9_U2 1 DDP@ 2 VSS E9 VSS_E9_U3 1 DDP@ 2 VSS E1 240_0402_1% VSS E1
VSS G8 VSS G8 VSS E9 VSS_E9_U4 1 DDP@ 2 VSS E9 VSS_E9_U5
DDR_A_DQS#1 A7 VSS K1 RD79 DDR_A_DQS#2 A7 VSS K1 VSS G8 VSS G8
DDR_A_DQS1 DQSU_c VSS 10mils DDR_A_DQS2 DQSU_c VSS 10mils DDR_A_DQS#4 VSS DDR_A_DQS#6 VSS
B7 K9 4.7K_0402_5% B7 K9 A7 K1 10mils A7 K1 DDP@
DDR_A_DQS#0 F3 DQSU_t VSS M9 DDR_A_BG1_R 1 SDP@ 2 DDR_A_DQS#3 F3 DQSU_t VSS M9 DDR_A_BG1_R DDR_A_DQS4 B7 DQSU_c VSS K9 DDR_A_DQS6 B7 DQSU_c VSS K9
DDR_A_DQS0 DQSL_c VSS DDR_A_DQS3 DQSL_c VSS DDR_A_DQS#5 DQSU_t VSS DDR_A_BG1_R DDR_A_DQS#7 DQSU_t VSS
1
240_0402_1%
RD209
G3 N1 G3 N1 F3 M9 F3 M9
DQSL_t VSS T1 RD78 DQSL_t VSS T1 DDR_A_DQS5 G3 DQSL_c VSS N1 DDR_A_DQS7 G3 DQSL_c VSS N1
DDR_A_BG1_R
MEMRST# P1 VSS 0_0201_1% MEMRST# P1 VSS DQSL_t VSS T1 DQSL_t VSS T1
RESET 1 DDP@ 2 DDR_A_BG1 RESET MEMRST# P1 VSS MEMRST# P1 VSS
1 MEM@ 2 RD210 F9 1 MEM@ 2 RD211 F9 RESET RESET
2
240_0402_1% ZQ 240_0402_1% ZQ 1 MEM@ 2 RD212 F9 1 MEM@ 2 RD213 F9
DDR_A_BG1(RD78, Intel:549352) ZQ ZQ
C 1. Near SOC side 240_0402_1% 240_0402_1% C
DDR_A_ACT# L3 A2 DDR_A_ACT# L3 A2
<8> DDR_A_ACT# DDR_A_BG0 ACT VSSQ 2. BO1+BO2+M small then other DDR_A_BG0 ACT VSSQ DDR_A_ACT# DDR_A_ACT# 10mils
<8> DDR_A_BG0 M2 A8 CMD 25mils M2 A8 L3 A2 L3 A2
N9 BG0 VSSQ C9 N9 BG0 VSSQ C9 DDR_A_BG0 M2 ACT VSSQ A8 DDR_A_BG0 M2 ACT VSSQ A8
DDR_A_ALERT# TEN VSSQ 3. BO1+BO2 small then 800mils DDR_A_ALERT# TEN VSSQ BG0 VSSQ BG0 VSSQ
<8> DDR_A_ALERT# P9 D2 P9 D2 N9 C9 N9 C9
DDR_A_PAR T3 ALERT VSSQ D8 DDR_A_PAR T3 ALERT VSSQ D8 DDR_A_ALERT# P9 TEN VSSQ D2 DDR_A_ALERT# P9 TEN VSSQ D2
<8> DDR_A_PAR PAR VSSQ PAR VSSQ DDR_A_PAR ALERT VSSQ DDR_A_PAR ALERT VSSQ
E3 E3 T3 D8 T3 D8
T7 VSSQ E8 T7 VSSQ E8 PAR VSSQ E3 PAR VSSQ E3
B1 NC VSSQ F1 B1 NC VSSQ F1 T7 VSSQ E8 T7 VSSQ E8
+2.5V VPP VSSQ +2.5V VPP VSSQ NC VSSQ NC VSSQ
R9 H1 R9 H1 +2.5V B1 F1 +2.5V B1 F1
VPP VSSQ H9 VPP VSSQ H9 R9 VPP VSSQ H1 R9 VPP VSSQ H1
<8> DDR_A_MA[0..16] VSSQ VSSQ VPP VSSQ VPP VSSQ
96-BALL 96-BALL H9 H9
SDRAM DDR4 SDRAM DDR4 96-BALL VSSQ 96-BALL VSSQ
<8> DDR_A_DQS#[0..7]
K4A8G165WB-BCPB_FBGA96 K4A8G165WB-BCPB_FBGA96 SDRAM DDR4 SDRAM DDR4
X76@ X76@ K4A8G165WB-BCPB_FBGA96 K4A8G165WB-BCPB_FBGA96
<8> DDR_A_DQS[0..7]
X76@ X76@
<8> DDR_A_D[0..63]
<8> DDR_A_BG1
TERMINATION +0.6VS_VTT
+0.6VS_VTT
DDR4 mapping SDP DDP +1.2V_VDDQ
DDR_A_MA14 RD220 1 MEM@ 2 36_0201_1%
E9 VSS UZQ +0.6V_A_VREFCA DDR_A_CLK0 RD214 1 MEM@ 2 36_0201_1% DDR_A_CS#0 RD221 1 MEM@ 2 36_0201_1%
DDR_A_CLK#0 RD215 1 MEM@ 2 36_0201_1% DDR_A_MA15 RD222 1 MEM@ 2 36_0201_1%
M9 VSS BG1
2
+DDR_VREF_CA DDR_A_MA12 RD223 1 MEM@ 2 36_0201_1%
T7 NC VSS RD195
1.8K_0402_1% +0.6VS_VTT 11/12
RD11
RCOMP[0] 2.7_0402_1%
MEM@
(SOC side) 200_1% 121_1% 20mils
1
2 MEM@ 1 DDR_A_BG1_R RD86 1 DDP@ 2 36_0201_1% DDR_A_MA13 RD224 1 MEM@ 2 36_0201_1%
DDR_A_MA8 RD225 1 MEM@ 2 36_0201_1%
DDR_A_PAR RD226 1 MEM@ 2 36_0201_1%
20mils
CD271
1U_0201_6.3V6M
+1.2V_VDDQ DDR_A_MA11 RD227 1 MEM@ 2 36_0201_1%
4 as near each on board RAM device as possible Follow MA51 1 1
+1.2V_VDDQ SDP@ SDP@
RD206 RD208 CD24
@ 0_0402_5% 0_0402_5% 0.022U_0402_16V7K DDR_A_ALERT# RD41 2 MEM@ 1 49.9_0402_1%
CD230
CD231
CD232
CD233
CD234
CD235
CD236
CD211
CD210
CD212
CD213
CD214
CD215
CD216
CD217
CD218
CD264
CD263
CD229
CD225
CD226
CD227
CD228
CD268
SD028000080 SD028000080 2 MEM@ 2

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
INTEL suggest 50ohm 1% DDR_A_MA1 RD228 1 MEM@ 2 36_0201_1%

B B
2
+ CD237 SDP@ SDP@ DDR_A_MA5 RD229 1 MEM@ 2 36_0201_1%
330U_D2_2V_Y RD207 RD209 RD13 RD200 DDR_A_MA7 RD230 1 MEM@ 2 36_0201_1%
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 @ 0_0402_5% 0_0402_5% DDR_A_MA9 RD231 1 MEM@ 2 36_0201_1%

2 SGA00009S00
24.9_0402_1% 1.8K_0402_1%
SD028000080 SD028000080 MEM@ MEM@
330U 2V H1.9
1
9mohm POLY
DDR_A_BG0 RD232 1 MEM@ 2 36_0201_1%
DDR_A_MA10 RD233 1 MEM@ 2 36_0201_1%
DDR_A_MA3 RD234 1 MEM@ 2 36_0201_1%
DDR_A_BA1 RD235 1 MEM@ 2 36_0201_1%
DDR_A_CKE0 RD236 1 MEM@ 2 36_0201_1%

DDR_DRAMRST# 1 MEM@ 2 MEMRST# DDR_A_MA16 RD237 1 MEM@ 2 36_0201_1%
<8,20> DDR_DRAMRST# DDR_A_ODT0
RD202 0_0402_5% RD238 1 MEM@ 2 36_0201_1%
DDR_A_ACT# RD239 1 MEM@ 2 36_0201_1%
1
+2.5V @ CD219
.1U_0402_16V7K
2
CD238
CD239
CD240
CD241
CD242
CD243
CD244
CD245
CD265
CD266
CD220
CD221
CD222
CD269
DDR_A_MA2 RD216 1 MEM@ 2 36_0201_1%

1 1 1 1 1 1 1 1 1 1
1
1
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
2
2 2 2 2 2 2 2 2 2 2
DDR_A_MA4 RD240 1 MEM@ 2 36_0201_1%

DDR_A_BA0 RD241 1 MEM@ 2 36_0201_1%
DDR_A_MA0 RD242 1 MEM@ 2 36_0201_1%
DDR_A_MA6 RD243 1 MEM@ 2 36_0201_1%
2 as near each on board RAM device as possible
+0.6VS_VTT
+0.6VS_VTT
A A
CD255
CD256
CD257
CD258
CD259
CD254
CD246
CD247
CD248
CD249
CD250
CD251
CD252
CD253
CD224
CD223
1 1 1 1 1
1
1 1 1 1 1 1 1 1
1
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
2
2 2 2 2 2
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
2
2 2 2 2 2 2 2 2
@ @ @ @ @
@
Vinafix.com Compal Electronics, Inc.

Security Classification Compal Secret Data
2 as near each on board RAM device as possible Issued Date 2018/12/11 Deciphered Date 2018/12/11 Title
DDR4 ON BOARD CHIPS
5 4 3 2 1
A B C D E
<8> DDR_B_DQS#[0..7]
JDIMM2A
<8> DDR_B_D[0..63]
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
137
139 CK0(T)
CK0#(C)
STD
DQ0
DQ1
8
7
DDR_B_D10
DDR_B_D14
DDR_B_D9
Standard Type
138 20
<8> DDR_B_DQS[0..7] DDR_B_CLK#1 140 CK1(T) DQ2 21 DDR_B_D12
CK1#(C) DQ3 4 DDR_B_D11 2-3A to 1 DIMMs/channel
DDR_B_CKE0 109 DQ4 3 DDR_B_D15
<8> DDR_B_MA[0..16] DDR_B_CKE1 110 CKE0 DQ5 16 DDR_B_D13
DDR_B_BA0 +3VS CKE1 DQ6 17 DDR_B_D8
<8> DDR_B_BA0 DDR_B_BA1 DDR_B_CS#0 149 DQ7 13 DDR_B_DQS1
<8> DDR_B_BA1 DDR_B_BG0 DDR_B_CS#1 157 S0# DQS0(T) 11 DDR_B_DQS#1
<8> DDR_B_BG0 DDR_B_BG1 162 S1# DQS0#(C) +1.2V_VDDQ +1.2V_VDDQ
<8> DDR_B_BG1 S2#/C0
1
1 DDR_B_ACT# 165 28 DDR_B_D1 JDIMM2B 1
<8> DDR_B_ACT# DDR_B_ALERT# S3#/C1 DQ8 DDR_B_D0
0_0402_5%
RD52
29 STD
<8> DDR_B_ALERT# DDR_B_PAR DDR_B_ODT0 155 DQ9 41 DDR_B_D7 111 141
<8> DDR_B_PAR DDR_B_ODT1 161 ODT0 DQ10 42 DDR_B_D2 112 VDD1 VDD11 142
@ ODT1 DQ11 24 DDR_B_D5 117 VDD2 VDD12 147
2
DDR_B_BG0 115 DQ12 25 DDR_B_D4 118 VDD3 VDD13 148
DDR_B_CLK0 DDR_B_BG1 113 BG0 DQ13 38 DDR_B_D3 +1.2V_VDDQ 123 VDD4 VDD14 153
<8> DDR_B_CLK0 DDR_B_CLK#0 DDR_B_SA2 DDR_B_BA0 150 BG1 DQ14 37 DDR_B_D6 +0.6V_B_VREFCA 124 VDD5 VDD15 154
<8> DDR_B_CLK#0 DDR_B_CLK1 DDR_B_SA1 DDR_B_BA1 145 BA0 DQ15 34 DDR_B_DQS0 129 VDD6 VDD16 159
<8> DDR_B_CLK1 BA1 DQS1(T) VDD7 VDD17
1
DDR_B_CLK#1 DDR_B_SA0 32 DDR_B_DQS#0 130 160
<8> DDR_B_CLK#1 DDR_B_MA0 144 DQS1#(C) RD46 135 VDD8 VDD18 163
A0 VDD9 VDD19
1
DDR_B_MA1 DDR_B_D17
0_0402_5%
RD54
0_0402_5%
RD56
133 50 1K_0402_1% 136
DDR_B_CKE0 DDR_B_MA2 132 A1 DQ16 49 DDR_B_D21 +0.6V_DDRB_VREFCA VDD10
<8> DDR_B_CKE0 DDR_B_CKE1 DDR_B_MA3 131 A2 DQ17 62 DDR_B_D19 255 258
RD49 +3VS +0.6VS_VTT
<8> DDR_B_CKE1
2
DDR_B_CS#0 DDR_B_MA4 128 A3 DQ18 63 DDR_B_D23 VDDSPD VTT
<8> DDR_B_CS#0
@ @
A4 DQ19
20mils 2_0402_1% 20mils
DDR_B_CS#1 DDR_B_MA5 126 46 DDR_B_D16 2 1 164 257
<8> DDR_B_CS#1 +2.5V
2
DDR_B_MA6 127 A5 DQ20 45 DDR_B_D20 VREFCA VPP1 259
DDR_B_MA7 A6 DQ21 DDR_B_D18 1 VPP2
1U_0201_6.3V6M
0.022U_0402_16V7K
CD272
122 58
SOC_SMBDATA_1 DDR_B_MA8 125 A7 DQ22 59 DDR_B_D22 1 99
<9,26> SOC_SMBDATA_1 A8 DQ23 1 1 VSS VSS
1
SOC_SMBCLK_1 DDR_B_MA9 121 55 DDR_B_DQS2 CD66 2 102
<9,26> SOC_SMBCLK_1 DDR_B_MA10 146 A9 DQS2(T) 53 DDR_B_DQS#2 2 5 VSS VSS 103
RD47 CD65
DDR_B_MA11 120 A10_AP DQS2#(C) 1K_0402_1% 0.1U_0201_10V6K 6 VSS VSS 106
A11 VSS VSS
1
DDR_B_ODT0 DDR_B_MA12 119 70 DDR_B_D25 2 2 9 107
<8> DDR_B_ODT0 DDR_B_ODT1 DDR_B_MA13 A12 DQ24 DDR_B_D28 VSS VSS
24.9_0402_1%
RD50
158 71 10 167
<8> DDR_B_ODT1
2
DDR_B_MA14 151 A13 DQ25 83 DDR_B_D31 14 VSS VSS 168
DDR_B_MA15 156 A14_WE# DQ26 84 DDR_B_D27 15 VSS VSS 171
DDR_B_MA16 152 A15_CAS# DQ27 66 DDR_B_D24 18 VSS VSS 172
2
A16_RAS# DQ28 67 DDR_B_D29 19 VSS VSS 175
DDR_B_ACT# 114 DQ29 79 DDR_B_D30 22 VSS VSS 176
ACT# DQ30 80 DDR_B_D26 23 VSS VSS 180
DDR_B_PAR 143 DQ31 76 DDR_B_DQS3 26 VSS VSS 181
DDR_B_ALERT# 116 PARITY DQS3(T) 74 DDR_B_DQS#3 27 VSS VSS 184
Layout Note:
2
Place near JDIMM2 +1.2V_VDDQ RD63 2 1 240_0402_1% DDR_B_EVENT# 134
DDR_DRAMRST# 108
ALERT#
EVENT#
DQS3#(C)
DDR_B_D37
Place near to SO-DIMM connector. 30 VSS
VSS
VSS
VSS
185 2
174 31 188
<8,19> DDR_DRAMRST# RESET# DQ32 173 DDR_B_D32 35 VSS VSS 189
RD1 1 2 470_0402_5% DQ33 187 DDR_B_D39 36 VSS VSS 192
+1.2V_VDDQ SOC_SMBDATA_1 254 DQ34 DDR_B_D35 VSS VSS
186 39 193
CD30 2 1 .1U_0402_16V7K SOC_SMBCLK_1 253 SDA DQ35 170 DDR_B_D36 40 VSS VSS 196
@ESD@ SCL DQ36 169 DDR_B_D33 43 VSS VSS 197
+1.2V_VDDQ DDR_B_SA2 166 DQ37 183 DDR_B_D38 44 VSS VSS 201
DDR_B_SA1 260 SA2 DQ38 182 DDR_B_D34 47 VSS VSS 202
DDR_B_SA0 256 SA1 DQ39 179 DDR_B_DQS4 48 VSS VSS 205
SA0 DQS4(T) DDR_B_DQS#4 VSS VSS
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
177 51 206
DQS4#(C) 52 VSS VSS 209
1 1 1 1 1 1 1 1 1 1 DDR_B_D41 VSS VSS
@ 92 195 56 210
91 CB0_NC DQ40 194 DDR_B_D45 57 VSS VSS 213
CB1_NC DQ41 DDR_B_D46 VSS VSS
CD32
CD33
CD34
CD35
CD36
CD37
CD69
CD70
CD260
CD261
101 207 60 214

2 2 2 2 2 2 2 2 2 2 105 CB2_NC DQ42 208 DDR_B_D42 61 VSS VSS 217
RD61 2 1 240_0402_1% DDR_B_DQS8 97 CB7_NC DQ47 200 DDR_B_DQS5 72 VSS VSS 227
+1.2V_VDDQ DDR_B_DQS#8 DQS8(T) DQS5(T) DDR_B_DQS#5 VSS VSS
RD62 2 1 240_0402_1% 95 198 73 230
DQS8#(C) DQS5#(C) 77 VSS VSS 231
216 DDR_B_D53 78 VSS VSS 234
+1.2V_VDDQ 12 DQ48 215 DDR_B_D49 81 VSS VSS 235
+1.2V_VDDQ DM0#/DBI0# DQ49 DDR_B_D54 VSS VSS
33 228 82 238
54 DM1#/DBI1# DQ50 229 DDR_B_D51 85 VSS VSS 239
DM4#/DBI4# DQ53 DDR_B_D55 VSS VSS
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
4.7U_0402_6.3V6M
199 224 90 247

1 1 DM6#/DBI6# DQ55 VSS VSS
1
DDR_B_DQS6
CD38
CD39
CD40
CD41
CD42
CD43
CD44
CD45
CD267
241 221 94 251

3 96 DM7#/DBI7# DQS6(T) 219 DDR_B_DQS#6 98 VSS VSS 252 3
DM8#/DBI8# DQS6#(C) VSS VSS
CD274
CD275
2
2 2 262 261
GND GND
237 DDR_B_D61
DQ56 236 DDR_B_D57 FOX_AS0A821-H4SB-7H
PVT DQ57 249 DDR_B_D58 CONN@
DQ58 250 DDR_B_D63
DQ59 DDR_B_D60
SP07001GA00
232
DQ60 233 DDR_B_D56
DQ61 245 DDR_B_D59
DQ62 246 DDR_B_D62
DQ63 242 DDR_B_DQS7
DQS7(T) 240 DDR_B_DQS#7
DQS7#(C)
Layout Note:
Place near JDIMM1.258
FOX_AS0A821-H4SB-7H
CONN@
SP07001GA00
Layout Note: Layout Note: +0.6VS_VTT

Place near JDIMM1.257,259 Place near JDIMM2.255
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
CD62
CD63
1 1 1 1
+3VS
CD262
CD64
+2.5V
2 2 2 2
4 4
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
2.2U_0402_6.3V6M
CD67
CD270
1 1 1 1
1
CD55
CD273
CD68
2 2 2 2
2018/12/11
Compal Secret Data
2018/12/11 Title
DDR4_DIMMB
A B C D E
A B C D E
Change to +19VB 11/16

LCD POWER CIRCUIT
+3VS +LCDVDD +19VB +INVPW R_B+ Place closed to JEDP1
UX1
W=80mils +LCDVDD
1U_0402_6.3V6K
CX1
5 1
1
IN OUT W=60mils LX1 W=60mils +3VS
2 1 1 HCB2012KF-221T30_0805
GND CX4 1 2
1 1
4 3 0.1U_0201_10V6K 1 1
2 EN OC
1000P_0402_50V7K
CX5
@ SM01000EJ00 3000ma 1 1
SY6288C20AAC_SOT23-5 CX3 2 2 CX2 CX6 CX7
220ohm@100mhz
4.7U_0402_6.3V6M DCR 0.04 68P_0402_50V8J 0.1U_0201_10V6K .1U_0402_16V7K
2 2
@EMI@
@EMI@ @
<7> SOC_ENVDD 2 2
1
RX9
100K_0402_5%
@
2
Note: Unmount LX1 when panel boost

circuit was use. (2S battery cell)
CX8 1 2 .1U_0402_16V7K EDP_TXP0_C

<7> EDP_TXP0 EDP_TXN0_C
CX9 1 2 .1U_0402_16V7K
<7> EDP_TXN0 EDP_TXP1_C
CX10 1 2 .1U_0402_16V7K
<7>
<7>
EDP_TXP1
EDP_TXN1
CX11 1 2 .1U_0402_16V7K EDP_TXN1_C
EDP_TXP2_C
LED PANEL Conn.
CX17 1 2 .1U_0402_16V7K
<7> EDP_TXP2 EDP_TXN2_C SOC_BKL_PW M
CX16 1 2 .1U_0402_16V7K RX1 1 @ 2 100K_0402_5% W=60mils JEDP1
<7> EDP_TXN2 EDP_TXP3_C <7> SOC_BKL_PW M
CX19 1 2 .1U_0402_16V7K +INVPW R_B+ 1
<7> EDP_TXP3 EDP_TXN3_C 1
CX18 1 2 .1U_0402_16V7K @EMI@ 2 41
<7> EDP_TXN3 2 G1
CX12 1 2 220P_0402_50V7K 3 42
CX14 1 2 .1U_0402_16V7K EDP_AUXP_C @EMI@ 4 3 G2 43
<7> EDP_AUXP EDP_AUXN_C 4 G3
<7> EDP_AUXN CX15 1 2 .1U_0402_16V7K BKOFF# CX13 1 2 220P_0402_50V7K 5 44
<29> BKOFF# SOC_BKL_PW M 5 G4
2 6 45 2
RX2 1 @ 2 10K_0402_5% BKOFF# 7 6 G5 46
+3VS EDP_HPD 8 7 G6
9 8
EDP_AUXN_C +LCDVDD 9
100K_0402_5% 1 @ 2 RX3 10
100K_0402_5% 1 @ 2 RX4 EDP_AUXP_C 11 10
RX5
W=60mils 12 11
0_0402_5% 13 12
1 @ 2 EDP_HPD EDP_AUXN_C 14 13
<7> CPU_EDP_HPD EDP_AUXP_C 14
15
RX6 16 15
100K_0402_5% EDP_TXP0_C 17 16
2 1 EDP_TXN0_C 18 17
19 18
EDP_TXP1_C 20 19
Touch Screen EDP_TXN1_C 21 20
21
22
+5VS +3VS +TS_PW R EDP_TXP2_C 23 22
EDP_TXN2_C 24 23
RX7 1 @ 2 0_0603_5% 25 24
RX8 1 @ 2 0_0603_5% EDP_TXP3_C 26 25
EDP_TXN3_C 27 26
28 27
USB20_P6 29 28
<13> USB20_P6 USB20_N6 29
30
<13> USB20_N6 30
31
32 31
Touch Screen +TS_PW R 32
33
TS_EN 34 33
3 Camera <12,29> TS_EN
+3VS USB20_N7_CAMERA
35 34
35
3
36
@EMI@ USB20_P7_CAMERA 37 36
USB20_N7 RX10 1 2 0_0402_5% USB20_N7_CAMERA 38 37
<13> USB20_N7 For Camera DMIC_CLK_R 38
39
<25> DMIC_CLK_R DMIC_DATA_R 39
@EMI@ 40
USB20_P7 USB20_P7_CAMERA <25> DMIC_DATA_R 40
RX11 1 2 0_0402_5%
<13> USB20_P7
E-T_0871K-F40N-00L
CONN@
DMIC_DATA_R SP010014B10
DMIC_CLK_R
Change eDP Conn. symbol & Pin define 11/20
3
DX1
@ESD@
YSLC05CH_SOT23-3
1
4 4

eDP Connector
A B C D E
A B C D E
+5VS W=40mils +HDMI_5V_OUT DY2 ESD@

HDMI_C_CLK- RY1 1 EMI@ 2 5.6_0402_5% HDMI_R_CK- HDMI_R_D0- 1 1 10 9 HDMI_R_D0-
UY1
2
HDMI_R_D0+ 2 2 9 8 HDMI_R_D0+
RY35
3 @EMI@ 360_0402_5% HDMI_R_CK- 4 4 7 7 HDMI_R_CK-
OUT
1
1 HDMI_R_CK+ 5 5 6 6 HDMI_R_CK+
1
IN CY9 HDMI_C_CLK+ RY2 1 EMI@ 2 5.6_0402_5% HDMI_R_CK+
1 1
2 0.1U_0201_10V6K 3 3
GND 2
8
AP2330W -7_SC59-3
TVW DF1004AD0
HDMI_C_TX0- RY3 1 EMI@ 2 5.6_0402_5% HDMI_R_D0-
SC300001Y00
2
RY36 DY3 ESD@
@EMI@ 360_0402_5% HDMI_R_D1- 1 1 10 9 HDMI_R_D1-
HDMI_R_D1+ 2 2 9 8 HDMI_R_D1+
1
HDMI_C_TX0+ RY4 1 EMI@ 2 5.6_0402_5% HDMI_R_D0+
<7> SOC_DP1_N1 CY4 2 1 .1U_0402_16V7K HDMI_C_TX1- RY20 1 2 470_0402_5% HDMI_R_D2- 4 4 7 7 HDMI_R_D2-
<7> SOC_DP1_P1 CY3 2 1 .1U_0402_16V7K HDMI_C_TX1+ RY21 1 2 470_0402_5%
<7> SOC_DP1_N0 CY2 2 1 .1U_0402_16V7K HDMI_C_TX2- RY22 1 2 470_0402_5% HDMI_R_D2+ 5 5 6 6 HDMI_R_D2+
<7> SOC_DP1_P0 CY1 2 1 .1U_0402_16V7K HDMI_C_TX2+ RY23 1 2 470_0402_5%
3 3
HDMI_GND
11/12
HDMI_C_TX1- RY5 1 EMI@ 2 5.6_0402_5% HDMI_R_D1- 8
2
<7> SOC_DP1_N2 CY6 2 1 .1U_0402_16V7K HDMI_C_TX0- RY24 1 2 470_0402_5% TVW DF1004AD0
<7> SOC_DP1_P2 CY5 2 1 .1U_0402_16V7K HDMI_C_TX0+ RY25 1 2 470_0402_5% RY37 SC300001Y00
<7> SOC_DP1_N3 CY8 2 1 .1U_0402_16V7K HDMI_C_CLK- RY26 1 2 470_0402_5% @EMI@ 360_0402_5%
<7> SOC_DP1_P3 CY7 2 1 .1U_0402_16V7K HDMI_C_CLK+ RY27 1 2 470_0402_5%
1
11/12 HDMI_C_TX1+ RY7 1 EMI@ 2 5.6_0402_5% HDMI_R_D1+
2 2
6
D
+3VS 2 QY1A
G 2N7002KDW _SOT363-6
HDMI_C_TX2- RY8 1 EMI@ 2 5.6_0402_5% HDMI_R_D2-
S
2
RY38
@EMI@ 360_0402_5%
+3VS
+3VS
1
HDMI_C_TX2+ RY10 1 EMI@ 2 5.6_0402_5% HDMI_R_D2+
1
RY6 Chnage to 5.6 ohm

G
1M_0402_5%
HDMI connector
2
4 3 HDMI_HPD
S
<7> SOC_DP1_HPD
D
JHDMI1
1
HDMI_HPD 19
QY1B RY9 18 HP_DET
2N7002KDW _SOT363-6 +HDMI_5V_OUT +5V
100K_0402_5% 17
HDMI_SDATA 16 DDC/CEC_GND
HDMI_SCLK 15 SDA
2
14 SCL
13 Utility
HDMI_R_CK- 12 CEC
11 CK-
3 HDMI_R_CK+ 10 CK_shield 3
DY1 HDMI_R_D0- 9 CK+
RY30 1 2 2.2K_0402_5% SOC_DP1_CTRL_CLK HDMI_HPD 6 3 HDMI_SDATA 8 D0-
+3VS I/O4 I/O2 D0_shield
RY31 1 2 2.2K_0402_5% SOC_DP1_CTRL_DATA HDMI_R_D0+ 7
HDMI_R_D1- 6 D0+
RY32 1 2 2.2K_0402_5% HDMI_SCLK 5 D1-
+HDMI_5V_OUT HDMI_SDATA HDMI_R_D1+ D1_shield
RY33 1 2 2.2K_0402_5% 5 2 4 23
VDD GND HDMI_R_D2- 3 D1+ GND1 22
11/12 2 D2- GND2 21
HDMI_R_D2+ 1 D2_shield GND3 20
HDMI_SCLK 4 1 D2+ GND4
I/O3 I/O1 +HDMI_5V_OUT
ACON_HMRBL-AK120D
AZC099-04S.R7G_SOT23-6 DC232007600
ESD@ CONN@
+3VS
SC300001G00
Change JHDMI1 symbol 11/15
Change to SC300001G00 12/04
2
G
1 6 HDMI_SDATA
<7> SOC_DP1_CTRL_DATA
S
QY2B
PJT138KA-2N_SOT363-6
5
G
4 HDMI_SCLK 4
4 3
<7> SOC_DP1_CTRL_CLK
S
QY2A
PJT138KA-2N_SOT363-6
Intel spec Ron/Cout : 3ohm/10pF. Issued Date 2016/11/04 Deciphered Date 2018/11/04 Title
Vinafix.comSB000016K00, S TR PJT138KA 2N SOT363-6 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI CONN.
A B C D E
A B C D E
LAN-RTL8111H W=60mil
Use LDO mode only 300mA
+LAN_VDD +3V_LAN
+REGOUT RL1 2 @ 1 0_0603_5%

+3VALW +3V_LAN
0.1U_0201_10V6K
1U_0201_6.3V6M
1U_0201_6.3V6M
CL1
4.7U_0402_6.3V6M
CL7
4.7U_0402_6.3V6M
CL8
CL27
RL2 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0.1U_0201_10V6K
CL2
0.1U_0201_10V6K
CL3
0.1U_0201_10V6K
CL4
0.1U_0201_10V6K
CL5
0.1U_0201_10V6K
CL6
0.1U_0201_10V6K
CL11
0.1U_0201_10V6K
CL12
0.1U_0201_10V6K
CL13
0_0805_5% The trace length from
1 2 Lx to PIN48 (REGOUT)
@
and from C to Lx must CL9
2 2 2 2 2 2 2 2 2 2 CL10 2 2 2 2
1
60mil 60mil < 200mils. 1
UL1 4.7U_0402_6.3V6M
5 1
IN OUT
Remove SWG Mode 11/20
2
GND Using for LDO mode
Place near Pin 3,8,33,46 Place near Pin 22 Place near Pin 11,32
4 3
EN OC
1 The trace length
CL14 SY6288C20AAC_SOT23-5 from C to
@ PIN34,35(VDDREG)
1U_0201_6.3V6M LAN_PWR_EN
2 LAN_PWR_EN <29> must < 200mils.
Place near Pin 11,32
From EC
High active. UL2
EN threshold voltage min:1.2V
typ:1.6V max:2.0V
Current limit threshold 1.5~2.8A
+3V_LAN Rising time must >0.5ms and <100ms +3V_LAN
1
LAN_MIDI0+ 1 17 PCIE_CRX_C_DTX_P5 .1U_0402_16V7K 2 1 CL16
LAN_MIDI0- 2 MDIP0 HSOP 18 PCIE_CRX_C_DTX_N5 PCIE_CRX_DTX_P5 <13>
.1U_0402_16V7K 2 1 CL15 RL12
+LAN_VDD 3 MDIN0 HSON 19 PLT_RST_BUF# PCIE_CRX_DTX_N5 <13>
AVDD10 PERSTB PLT_RST_BUF# <11,24> 10K_0402_5%
LAN_MIDI1+ 4 20 ISOLATEB
LAN_MIDI1- MDIP1 ISOLATEB LAN_PME# @
5 21 0_0402_5% 2 @ 1 RL24 EC_PME# <29>
2
LAN_MIDI2+ 6 MDIN1 LANWAKEB 22 +LAN_VDD GPO
LAN_MIDI2- 7 MDIP2 DVDD10 23 +3V_LAN 10K_0402_5% 2 1 RL3
+LAN_VDD MDIN2 VDDREG +3V_LAN
8 24 +REGOUT
LAN_MIDI3+ 9 AVDD10 REGOUT 25
MDIP3 LED2 reserve EC_PME# pull high 100K to +3VALW_EC
2 LAN_MIDI3- 10 26 GPO RL7 2 @ 1 0_0402_5% +3VS 2
+3V_LAN 11 MDIN3 LED1/GPIO 27 LAN_GPO <29>
CLKREQ_PCIE#1 12 AVDD33 LED0 28 XTLI PVT
PU at PCH side <11> CLKREQ_PCIE#1 CLKREQB CKXTAL1
1
13 29 XTLO_R 2 1 XTLO
<13> PCIE_CTX_C_DRX_P5 HSIP CKXTAL2 +LAN_VDD
14 30 RL5 0_0402_5% RL15
<13> PCIE_CTX_C_DRX_N5 CLK_PCIE_P1 HSIN AVDD10 LAN_RST
15 31 1 2 1K_0402_5%
<11> CLK_PCIE_P1 CLK_PCIE_N1 REFCLK_P RSET +3V_LAN 2.49K_0402_1%
16 32 RL6
<11> CLK_PCIE_N1 REFCLK_N AVDD33 33
2
GND ISOLATEB
2
RL18
15K_0402_5%
RTL8111H-CG_QFN32_4X4 YL1
1
25MHZ_10PF_XRCGB25M000F2P34R0
SA000080P00
XTLO 1 3 XTLI
1 3
NC NC
1
CL18 2 4 CL19
15P_0402_50V8J 15P_0402_50V8J
2
3 3
LAN Connector
TL1 JRJ45
LAN_TERMAL1 24 MCT1 12
LAN_MIDI0+ 2 TCT1 MCT1 23 RJ45_MIDI0+ RJ45_MIDI3- 8 GND
LAN_MIDI0- 3 TD1+ MX1+ 22 RJ45_MIDI0- PR4- 11
TD1- MX1- RJ45_MIDI3+ 7 GND
4 21 MCT2 PR4+
LAN_MIDI1+ 5 TCT2 MCT2 20 RJ45_MIDI1+ RJ45_MIDI1- 6
LAN_MIDI1- 6 TD2+ MX2+ 19 RJ45_MIDI1- PR2-
TD2- MX2- RJ45_MIDI2- 5
7 18 MCT3 PR3-
LAN_MIDI2+ 8 TCT3 MCT3 17 RJ45_MIDI2+ RJ45_MIDI2+ 4
LAN_MIDI2- 9 TD3+ MX3+ 16 RJ45_MIDI2- PR3+
B88069X9231T203_4P5X3P2-2
TD3- MX3- RJ45_MIDI1+ 3

10 15 MCT4 PR2+ CL25
LAN_MIDI3+ 11 TCT4 MCT4 14 RJ45_MIDI3+ RJ45_MIDI0- 2
40mil 40mil
10P_0402_50V8J
LAN_MIDI3- 12 TD4+ MX4+ 13 RJ45_MIDI3- PR1- 10 LANGND 2 1 RJ45_GND
TD4- MX4- RJ45_MIDI0+ GND
75_0402_1%
75_0402_1%
75_0402_1%
75_0402_1%
1
PR1+
1
1 9
GND
PESD5V0U2BT_SOT23-3
CL26 GST5009-E
3
.1U_0402_16V7K SP050006B10 SINGA_2RJ1660-000111F ESD@ @

2
@ESD@
CONN@ DL1 JPL1

1
1
1
1
JP1
Place close to TCT pin DC234009H00 JUMP_43X118

2
4 LANGND 4
1
DC23400G400 SCA00004300
2
2
2
2
RL20
RL21
RL22
RL23
ESD Change BOM 11/23
RJ45_GND

LAN RTL8111H
A B C D E
A B C D E
Wireless LAN
+3VS 60mil +3VS_WLAN
NGFF WL+BT (KEY E) NBYOC@
RM11 2 0_0805_5%
+3VALW
UM1 W=60mils
5 1
KEY E +3VS_WLAN IN OUT
2
1
1 GND 1 1 1 1
JNGFF1 CM4 @ CM1
1 2 1U_0201_6.3V6M 4 3 @ CM3
USB20_P5 3 GND_1 3.3VAUX_2 4 EN OC 4.7U_0402_6.3V6M CM2 0.1U_0201_10V6K
<13> USB20_P5 USB20_N5 5 USB_D+ 3.3VAUX_4 6 2 2 2 2
SY6288C20AAC_SOT23-5
For BT <13> USB20_N5 7 USB_D- LED1# 8 BYOC@ 0.1U_0201_10V6K
9 GND_7 PCM_CLK 10
11 SDIO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_OUT 14 <29> WLAN_ON
15 SDIO_DAT0 PCM_IN 16
17 SDIO_DAT1 LED2# 18
19 SDIO_DAT2 GND_18 20
21 SDIO_DAT3 UART_WAKE 22 UART_2_CRXD_DTXD
23 SDIO_WAKE UART_TX UART_2_CRXD_DTXD <12>
SDIO_RST
24
PH +3VS at SOC
UART_2_CTXD_DRXD side, for win7 USB3 debug
25 UART_RX 26 UART_2_CTXD_DRXD <12>
PCIE_CTX_C_DRX_P6 27 GND_33 UART_RTS 28 RM3 1 2 100K_0402_5%
<13> PCIE_CTX_C_DRX_P6 PCIE_CTX_C_DRX_N6 29 PET_RX_P0 UART_CTS 30 E51TXD_P80DATA_R 2 1 0_0402_5%
RM2 @
<13> PCIE_CTX_C_DRX_N6 31 PET_RX_N0 CLink_RST 32 E51RXD_P80CLK_R 2 1 0_0402_5% E51TXD_P80DATA <29>
RM7 @
PCIE_CRX_DTX_P6 33 GND_39 CLink_DATA 34 E51RXD_P80CLK <29>
<13> PCIE_CRX_DTX_P6 PCIE_CRX_DTX_N6 PER_TX_P0 CLink_CLK
35 36
<13> PCIE_CRX_DTX_N6 PER_TX_N0 COEX3
37 38
CLK_PCIE_P2 39 GND_45 COEX2 40
<11> CLK_PCIE_P2 CLK_PCIE_N2 41 REFCLK_P0 COEX1 42 SUSCLK_R
<11> CLK_PCIE_N2 REFCLK_N0 SUSCLK(32KHz) WL_RST#_R T205 @ PLT_RST_BUF#
43 44 RM4 1 @ 2 0_0402_5%
CLKREQ_PCIE#2 45 GND_51 PERST0# 46 BT_ON PLT_RST_BUF# <11,23>
<11> CLKREQ_PCIE#2 WLAN_PME# CLKREQ0# W_DISABLE2# WL_OFF# BT_ON <29>
47 48
<29> WLAN_PME# 49 PEWAKE0# W_DISABLE1# 50 WL_OFF# <29>
51 GND_57 I2C_DAT 52
RM6 53 RSVD/PCIE_RX_P1 I2C_CLK 54
+3VS_WLAN
2 1 10K_0402_5% 55 RSVD/PCIE_RX_N1 I2C_IRQ 56 P80CLK and BT_ON enable seperate.
57 GND_63 RSVD_64 58
2 59 RSVD/PCIE_TX_P1 RSVD_66 60 2
61 RSVD/PCIE_TX_N1 RSVD_68 62
63 GND_69 RSVD_70 64
65 RSVD_71 3.3VAUX_72 66
67 RSVD_73 3.3VAUX_74
GND_75 68
69 GND1
GND2
BELLW_80152-3221
CONN@
SP070013E00
mSATA/SSD JSSD1
KEY M
+3VS
DVT 01/23
+3VS_SSD_NGFF
Change to 0201 package 11/27 1 2 @ RM9
GND 3P3VAUX +3VS_SSD_NGFF
3 4 0_0805_5%
PCIE_CRX_DTX_N9 5 GND 3P3VAUX 6 1 2
<13> PCIE_CRX_DTX_N9 PCIE_CRX_DTX_P9 7 PERn3 NC 8
<13> PCIE_CRX_DTX_P9 PERp3 NC SSD_LED#
10U_0402_6.3V6M
9 10 1 2 1
PCIE_CTX_C_DRX_N9 GND DAS/DSS# @ T245
CM5 1 2 0.22U_0201_6.3V6K 11 12
<13> PCIE_CTX_DRX_N9 PCIE_CTX_C_DRX_P9 PETn3 3P3VAUX +3VS_SSD_NGFF + CS29
CM6 1 2 0.22U_0201_6.3V6K 13 14
<13> PCIE_CTX_DRX_P9 15 PETp3 3P3VAUX 16 CM14 150U_B2_6.3VM_R35M
PCIE_CRX_DTX_N10 17 GND 3P3VAUX 18 2 1 CM13 SGA00009M00
<13> PCIE_CRX_DTX_N10 PCIE_CRX_DTX_P10 19 PERn2 3P3VAUX 20 2
3 <13> PCIE_CRX_DTX_P10 21 PERp2 NC 22 0.1U_0201_10V6K 3
CM7 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_N10 23 GND NC 24
<13> PCIE_CTX_DRX_N10 CM8 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_P10 25 PETn2 NC 26
<13> PCIE_CTX_DRX_P10 27 PETp2 NC 28
PCIE_CRX_DTX_N11 29 GND NC 30
<13> PCIE_CRX_DTX_N11 PCIE_CRX_DTX_P11 31 PERn1 NC 32
<13> PCIE_CRX_DTX_P11 PERp1 NC DVT 01/23
33 34
CM9 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_N11 35 GND NC 36
<13> PCIE_CTX_DRX_N11 CM10 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_P11 37 PETn1 NC 38 RM21 1 @ 2 0_0402_5%
<13> PCIE_CTX_DRX_P11 39 PETp1 DEVSLP 40 SSD_DEVSLP2 <13>
RM16 1 @ 2 0_0201_5% PCIE_CRX_R_DTX_P12 41 GND NC 42 RM20 1 2 0_0402_5%
<13> PCIE_CRX_DTX_P12 RM17 1 @ 2 0_0201_5% PCIE_CRX_R_DTX_N12 43 PERn0/SATA-B+ NC 44
<13> PCIE_CRX_DTX_N12 PVT 45 PERp0/SATA-B- NC 46 CM15 1 2 100P_0402_50V8J
CM11 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_N12 47 GND NC 48 ESD@
<13> PCIE_CTX_DRX_N12 CM12 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_P12 49 PETn0/SATA-A- NC 50 NGFF_SSD_RST#_R RM18 1 @ 2 0_0402_5% PLT_RST_BUF#
<13> PCIE_CTX_DRX_P12 51 PETp0/SATA-A+ PERST# 52 NGFF_CLKREQ#_R RM5 1 @ 2 0_0402_5%
GND CLKREQ# CLKREQ_PCIE#3 <11>
53 54
<11> CLK_PCIE_N3 REFCLKN PEWake#
Port P and N follow SATA 55 56
<11> CLK_PCIE_P3 REFCLKP NC
57 58
GND NC
+3VS_SSD_NGFF 59 60 SUSCLK_SSD
NC SUSCLK(32kHz) @ T246
RM22 61 62
10K_0402_5% 63 PEDET(NC-PCIE/GND-SATA) 3P3VAUX 64
1 @ 2 65 GND 3P3VAUX 66
GND 3P3VAUX +3VS_SSD_NGFF
67
@ GND 68
1 2 SSD_DET# GND1 69
<13> SATA_GP2 GND2
4
DVT 01/23 RM23 BELLW_80159-3221
4
0_0402_5% CONN@
1
D
QM1 2
SP070018L00
BSS138W-7-F_SOT323-3 G
@ S
3
SSD_DET# (SATA_GP0)
SATA Device 0
Vinafix.com PCIE Device 1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M.2 Key E (WLAN)/Key M(SSD)
A B C D E
A B C D E
HD Audio Codec +PVDD_HDA
SM01000EJ00 3000mA 220ohm@100mhz DCR 0.04 +5VS (output = 300 mA) +VDDA Int. Speaker Conn.
40mil 40mil JPA1 40mil LA2,LA3 Change to 0ohm 12/25 40mil SPK_R+
LA1 2 1 1 2 SPKR+ LA2 EMI@ 1 2 PBY160808T-121Y-N_2P
SPK_R+ <28>
+VDDA 1 2 SPK_R-
HCB2012KF-221T30_0805 1 1 1 SPKR- LA3 EMI@ 1 2 PBY160808T-121Y-N_2P SPK_R- <28>
0.1U_0201_10V6K
CA2
0.1U_0201_10V6K
CA3
.1U_0402_16V7K
CA4
JUMP_43X79 4.75V
10U_0402_6.3V6M
CA1
@ LA4 PBY160808T-121Y-N_2P JSPK1
SPKL+ RA54 1 2 0_0805_5% SPK_L+ EMI@ 1 2 SPK_R_L+ 1
2
2 2 @ +AVDD1_HDA 2 SPKL- RA55 1 2 0_0805_5% SPK_L- EMI@ 1 2 SPK_R_L- 2 1
@ESD@ LA5 PBY160808T-121Y-N_2P 2 3
GND GND
GND & GNDA moat G1 4
G2
3
GND
Place near Pin41 Place near Pin46 CVILU_CI4202M2HR0-NH
@ESD@ @ESD@
DA1 DA2
1 1
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
20mil GND
1
CA5 1 2 10U_0402_6.3V6M RA1 1 @ 2
GND +VDDA
CA8
0.1U_0201_10V6K
CA9
0_0603_5%
CA34
1
10U_0402_6.3V6M
10U_0402_6.3V6M
1
1
Pin9 need to matching with SOC HDA CA6 1 2 0.1U_0201_10V6K GND GND
interface. @
RA2 2 @ 1 0_0402_5% +3VS_DVDDIO
+3VS Place near Pin9
2
2
+3VS_DVDD GND & GNDA moat
20mil GNDA
RA5 2 @ 1 0_0402_5% Place near Pin26
+3VS
1
+1.8VS_VDDA
0.1U_0201_10V6K
CA11
RA6 2 @ 1
CA10
+1.8VS
10U_0402_6.3V6M
CA13
1
10U_0402_6.3V6M
1
0.1U_0201_10V6K
CA12
0_0402_5%
2
2
2
2 @
1 2 DMIC_CLK Place near Pin1 GND GNDA
CA32 @EMI@
10P_0402_50V8J
41
46
26
40
1
9
UA1 Place near Pin40
Reserved for EMI
PVDD1
PVDD2
AVDD1
AVDD2
DVDD
DVDD-IO
GND
Headphone Out
LINE1-L 22
LINE1-R 21 LINE1-L(PORT-C-L) 43 SPKL-
UA1 LINE1-R(PORT-C-R) SPK-OUT-L- 42 SPKL+ +MIC2_VREFO
24 SPK-OUT-L+
23 LINE2-L(PORT-E-L) 45 SPKR+
LINE2-R(PORT-E-R) SPK-OUT-R+ 44 SPKR-
RING2 17 SPK-OUT-R-
40mil SLEEVE 18 MIC2-L(PORT-F-L) /RING2
MIC2-R(PORT-F-R) /SLEEVE
1
ALC233-VB2-CG_MQFN48_6X6 32 HP_LEFT
Combo MIC HPOUT-L(PORT-I-L) HP_RIGHT
2 233@ +MICBIAS +MICBIAS 31 33 RA19 RA20 2
SA00007BF10 30 LINE1-VREFO-L HPOUT-R(PORT-I-R) 2.2K_0402_5%
LINE1-VREFO-R 2.2K_0402_5%
10 HDA_SYNC_R
DMIC_DATA SYNC HDA_BIT_CLK_R HDA_SYNC_R <10>
UA1 2 6
HDA_BIT_CLK_R <10>
2
DMIC_CLK 3 GPIO0/DMIC-DATA BCLK
GPIO1/DMIC-CLK 1 @EMI@ 2 1 2 CA15 @EMI@ SLEEVE
GND
RA10 0_0402_5% 22P_0402_50V8J RING2
EC_MUTE# 47 5 HDA_SDOUT_R
<29> EC_MUTE# HDA_RST#_R 2 PDB SDATA-OUT HDA_SDIN0_AUDIO HDA_SDOUT_R <10> HP_LEFT HPOUT_L_1
<10> HDA_RST#_R 255@ 1 RESETB 11 8 1 RA33 2
HDA_SDIN0 <10> RA24 1 @ 2 0_0603_5%
ALC256-CG MQFN 48P CODEC 0_0402_5% RA41 RESETB SDATA-IN 33_0402_5%
256@ 48 DMIC_DATA34 HP_RIGHT RA27 1 @ 2 0_0603_5% HPOUT_R_1
SA000080Q00 MONO_IN 12 SPDIF-OUT/GPIO2
10mil Close codec1
PCBEEP 16 PC_BEEP
HP_PLUG# RA13 2 200K_0402_1% SENSE_A 13 MONO-OUT LINE1-L 1 2
2 1 100K_0402_1% 14 SENSE A +MIC2_VREFO
+3VS RA14 CA29 4.7U_0402_6.3V6M
SENSE B 29 10U_0402_6.3V6M 2 1 CA18 LINE1-R 1 2
1 MIC2-VREFO GND
37 CA30 4.7U_0402_6.3V6M
CA19 35 CBP 7 10U_0402_6.3V6M 2 1 CA20 +MICBIAS DA5
Pin36 CBN LDO3-CAP GNDA
2 256@ 1 2.2U_0402_6.3V6M 39 2 2 RA29 1
ALC255 : 3.3V +1.8VS_VDDA
0_0402_5% RA42 2 LDO2-CAP 27 10U_0402_6.3V6M 2 1 CA21 GNDA 4.7K_0402_5%
ALC256 : 1.8V 2 255@ 1 CPVDD 36 LDO1-CAP 1
+3VS_DVDD CPVDD
0_0402_5% RA43 100K_0402_5% 1 RA15 2
Pin20 28 CODEC_VREF 10mil 3 2 RA32 1
RA16 1 @ 2 0_0402_5% 20 VREF 4.7K_0402_5%
ALC255 : 3.3V +3VALW CPVREF 1 1
0.1U_0201_10V6K
CA23
2.2U_0402_6.3V6M
CA24
15 BAT54A-7-F_SOT23-3
ALC256 : 3.3V or 5V 2 1 CA22 19 JDREF 34
GNDA 10U_0402_6.3V6M CPVEE SCSBAT54100
MIC-CAP CPVEE
Power for combo jack depop 2 2
@
circuit at system shutdown mode 4
1
BLM15PX330SN1D_2P
49 DVSS 25 CA26 L1
Pin4 Thermal PAD AVSS1 38 2.2U_0402_6.3V6M SLEEVE EMI@ 2 1 SLEEVE_L
ALC283 : DVSS AVSS2 2 RING2 EMI@ 2 1 RING2_L
ALC255/256/233 : DC DET (For Japen customer only) Place near pin28 L2
ALC255-CG_MQFN48_6X6 BLM15PX330SN1D_2P
SA000082700 GND
GND 255@ 2 2
2
GNDA C11 C10
3 GNDA 3
Pin15 680P_0402_50V7K 680P_0402_50V7K
ESD@ 1 1 ESD@
RA21 CA27 ALC283 : Ref. Resistor for Jack Detect
DOS mode 22K_0402_5% .1U_0402_16V7K ALC255/256/233 : Jack Detect for SPDIF-OUT and SPK-OUT port D3
2 1 BEEP#_R 1 2 MONO_IN AZ5123-02S.R7G 3P C/A SOT23
<29> BEEP# GND GND
255@ Pin16 ESD@
ALC255: MONO-OUT
1
2
RA22 1
ALC256 : BEEP
100P_0402_50V8J
CA28 @EMI@
OS mode 22K_0402_5% CA33

4.7K_0402_5%
RA23
2 1 .1U_0402_16V7K GND
<10> PCH_SPKR 1 2 PC_BEEP
2 256@ JHP1
1
RING2_L 3
HPOUT_L_1 R10 1 2 HPOUT_L_2 1
62_0603_1%
GND Confirm with ESD HP_PLUG# 5
HPOUT_R_2
GND & GNDA moat HPOUT_L_2 6
Digital MIC
TVNST52302AB0_SOT523-3
2
3
HPOUT_R_1 R11 1 2 HPOUT_R_2 2 7
PCH_DMIC_DATA SLEEVE_L G
1 @ 2 2 @ 1 62_0603_1% 4
<10> PCH_DMIC_DATA
D4
1 @ 2 RA46 0_0402_5% 33_0402_5% RA36
RA44 0_0402_5% PCH_DMIC_CLK 2 @ 1 YUQIU_PJ588-F07J1BE-1
1 @ 2
<10> PCH_DMIC_CLK
33_0402_5% RA11
TO eDP Conn 2
C15
2 DC232005W00
RA47 0_0402_5% @ESD@ C16 @ESD@
1
1 @ 2 DMIC_DATA 2 EMI@ 1 RA35 DMIC_DATA_R @ESD@ 330P_0402_50V7K CONN@

RA45 0_0402_5% 1 @ 2 0_0402_5% DMIC_DATA_R <21> 330P_0402_50V7K 1 SINGA_2SJ3095-059111F_6P-T
DMIC_CLK DMIC_CLK_R 1 GNDA
RA48 0_0402_5% 2 1 GND GNDA
CA31 @EMI@ RA34 DMIC_CLK_R <21>
.1U_0402_16V7K 1 @ 2 BLM15PX221SN1D
1 2 RA49 0_0402_5% EMI@
RA25 1 @EMI@ 2 0_0402_5% GNDA

4
PCH_DMIC_DATA1 2 @ 1 4
<10> PCH_DMIC_DATA1
33_0402_5% RA52 Reserve RA50 11/28
PCH_DMIC_CLK1 2 @ 1
<10> PCH_DMIC_CLK1 +3VS
GND GNDA GND GNDA 33_0402_5% RA53
JDMIC1
RA50 1
DMIC_DATA34 2 256@ 1 0_0402_5% DMIC_DATA1_R 2 1
DMIC_CLK 2 256@ 1 DMIC_CLK1_R 3 2
RA51 0_0402_5% 4 3
5 4
6 G1
G2 Security Classification Compal Secret Data Compal Electronics, Inc.
Vinafix.com ACES_50278-00401-001
CONN@
HD Audio Codec ALC255/ALC233 Colay
GND SP02000RR00 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1A
A B C D E
A B C D E
G-Sensor reserved for BA serial SATA ODD Conn. SWAP Pin define 11/27
+3VS +5VS_ODD
+5VS @ RO2
0_0805_5% JODD1
1
1 2 +5VS_ODD 1
RZ1 +3VS 2 1
2
CO10
10K_0402_5% 1 3
10U_0402_6.3V6M
1
10U_0402_6.3V6M
1
0.1U_0201_10V6K
BA@ UZ1 BA@ 4 3
1 CZ1 1 2 10U_0402_6.3V6M 5 4
1 1
2
8 Vdd_IO CO11 CO9 ODD@ 6 5
4 CS 14 CZ2 1 2 BA@ ODD@ 2 ODD@ 2 2 7 6
<9,20> SOC_SMBCLK_1 SCLSPC Vdd 7
6 0.1U_0201_10V6K 8
<9,20> SOC_SMBDATA_1 SDA/SDI/SDO 8
+3VS RZ2 1 @ 2 10K_0402_5% 7 9
RO25 1 BA@ 2 10K_0402_5% SDO/SA0 11 G_INT# 10 9
INT1 G_INT2 G_INT# <12> 10
16 9 11
15 ADC1 INT2 ODD@ CO8 1 2 0.01U_0402_16V7K SATA_CRX_C_DTX_P1 12 11
ADC2 <13> SATA_CRX_DTX_P1 SATA_CRX_C_DTX_N1 12
13 10 INT1/2 all High Active ODD@ CO7 1 2 0.01U_0402_16V7K 13
ADC3 RES <13> SATA_CRX_DTX_N1 13
14
2 ODD@ CO6 1 2 0.01U_0402_16V7K SATA_CTX_C_DRX_N1 15 14
NC <13> SATA_CTX_DRX_N1 SATA_CTX_C_DRX_P1 15
3 5 <13> SATA_CTX_DRX_P1 ODD@ CO5 1 2 0.01U_0402_16V7K 16
NC GND 12 16
GND 17
LIS3DHTR_LGA16_3X3 18 GND17
BA@ GND18
LIS3DH CONN@
SA0 ->0, Address is 0011 000 (0x30h) ACES_51625-01601-001
SA0 ->1, Address is 0011 001 (0x32h) SP01002OK00
SATA Re-Driver and cable HDD Conn. +3VS

2 2
B_EQ1
A_EQ2
A_EQ1
CO14
DEW
2 1 RD@
0.01U_0402_16V7K UO2
20
19
18
17
16
RD@ PS8527CTQFN20GTR2A_TQFN20_4X4 DVT 01/23
SA00007JU10
VDD2
B_EQ1
A_EQ2
A_EQ1
DEW
+5VS +5VS_HDD
RD@ CO16 2 1 SATA_CTX_C_DRX_P0 0.01U_0402_16V7K 1 15 RDSATA_CTX_DRX_P0 @

<13> SATA_CTX_DRX_P0
RD@ CO17 2 1 SATA_CTX_C_DRX_N0 0.01U_0402_16V7K 2 A_INP A_OUTP 14 RDSATA_CTX_DRX_N0 1 2
100mils
<13> SATA_CTX_DRX_N0 A_INN A_OUTN B_EQ2
3 13 RO3
RD@ CO18 2 1 SATA_CRX_C_DTX_N0 0.01U_0402_16V7K 4 GND1 B_EQ2 12 RDSATA_CRX_DTX_N0 0_0805_5% 1
10U_0402_6.3V6M
1
10U_0402_6.3V6M
<13> SATA_CRX_DTX_N0 B_OUTN B_INN 1
RD@ CO19 2 1 SATA_CRX_C_DTX_P0 0.01U_0402_16V7K 5 11 RDSATA_CRX_DTX_P0 CO12 CO13
<13> SATA_CRX_DTX_P0 B_OUTP B_INP
21 0.1U_0201_10V6K
GND2
REXT
VDD1
B_DE
A_DE
CO28 @
2 2 2
EN
+3VS DVT 02/07

6
7
8
9
10
+3VS
RO10 1 @ 2 4.7K_0402_5% A_DE RO26 +3VS
RO15 1 @ 2 4.7K_0402_5% 4.99K_0402_1% 1
2 @ 1 CO15
B_DE
A_DE
RO13 1 @ 2 4.7K_0402_5% A_EQ1 0.1U_0201_10V6K

RO18 1 RD@ 2 4.7K_0402_5% RO6 2 RD@ 1 RD@
+3VS 4.99K_0402_1% 2 JHDD1
RO14 1 @ 2 4.7K_0402_5% A_EQ2 14
3 RO19 1 RD@ 2 4.7K_0402_5% RO5 1 @ 2 13 GND 3
4.7K_0402_5% GND
RO11 1 @ 2 4.7K_0402_5% B_DE +5VS_HDD 12
RO16 1 @ 2 4.7K_0402_5% 11 12
0_0402_5% 10 11
RO12 1 @ 2 4.7K_0402_5% B_EQ1 G_INT2 RO4 1 @ 2 JHDD_P9 9 10
RO17 1 RD@ 2 4.7K_0402_5% Add RO34 Pull-down 11/20 RO34 1 2 0_0402_5% 8 9
RD@ 7 8
RO20 1 @ 2 4.7K_0402_5% B_EQ2 RDSATA_CRX_DTX_P0 CO22 1 2 0.01U_0402_16V7K RDSATA_CRX_C_DTX_P0 6 7
RO21 1 RD@ 2 4.7K_0402_5% RDSATA_CRX_DTX_N0 CO21 1 2 0.01U_0402_16V7K RDSATA_CRX_C_DTX_N0 5 6
RD@ RD@ 4 5
RO22 1 @ 2 4.7K_0402_5% DEW RDSATA_CTX_DRX_N0 CO23 1 2 0.01U_0402_16V7K RDSATA_CTX_C_DRX_N0 3 4
RO27 1 @ 2 4.7K_0402_5% RDSATA_CTX_DRX_P0 CO20 1 2 0.01U_0402_16V7K RDSATA_CTX_C_DRX_P0 2 3
RD@ 1 2
1
PVT 03/13 close to CONN.
ACES_51625-01201-001
CONN@
PS8527C EQ and DE SP010028W00
Co-lay non-redriver
NRD@
SATA_CTX_DRX_P0 RO30 1 NRD@ 2 0_0402_5% SATA_CTX_DRX_P0_NRD CO24 1 2 0.01U_0402_16V7K RDSATA_CTX_C_DRX_P0
* SATA_CTX_DRX_N0 RO31 1 NRD@ 2 0_0402_5% SATA_CTX_DRX_N0_NRD CO25 1
NRD@
2 0.01U_0402_16V7K
NRD@
RDSATA_CTX_C_DRX_N0
* SATA_CRX_DTX_N0
SATA_CRX_DTX_P0
RO32 1 NRD@
RO33 1 NRD@
2
2
0_0402_5%
0_0402_5%
SATA_CRX_DTX_N0_NRD CO26 1
SATA_CRX_DTX_P0_NRD CO27 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
RDSATA_CRX_C_DTX_N0
RDSATA_CRX_C_DTX_P0
NRD@
4 4

HDD/ODD/ HDD Re-Driver
A B C D E
A B C D E
USB3.0 (Port 1)
1 1
For ESD request

DS21 +5VALW +USB3_VCCA
USB3_CTX_L_DRX_P1 1 1 USB3_CTX_L_DRX_P1
@RF@ 10 9
CS21 1 2 USB3_CTX_C_DRX_N1 RS21 1 2 0_0402_5% USB3_CTX_L_DRX_N1
<13> USB3_CTX_DRX_N1 USB3_CTX_L_DRX_N1 USB3_CTX_L_DRX_N1
.1U_0402_16V7K 2 2 9 8 CS93 US22
@RF@ 1 2 5 1 W=100mils
CS22 1 2 USB3_CTX_C_DRX_P1 1 2 0_0402_5% USB3_CTX_L_DRX_P1 USB3_CRX_L_DTX_P1 4 4 USB3_CRX_L_DTX_P1 IN OUT
<13> USB3_CTX_DRX_P1 RS22 7 7
.1U_0402_16V7K 1U_0201_6.3V6M 2
USB3_CRX_L_DTX_N1 5 5 USB3_CRX_L_DTX_N1 GND
6 6
@RF@ 4 3 1 @ 2 USB_OC0#
USB3_CRX_DTX_N1 USB3_CRX_L_DTX_N1 <28,29> USB_EN EN OC USB_OC0# <13>
RS24 1 2 0_0402_5% 3 3 0_0402_5%
<13> USB3_CRX_DTX_N1
SY6288C20AAC_SOT23-5 RS98 1
@RF@ 8 CS92
USB3_CRX_DTX_P1 RS25 1 2 0_0402_5% USB3_CRX_L_DTX_P1 1000P_0402_50V7K
<13> USB3_CRX_DTX_P1
AZ1045-04F_DFN2510P10E-10-9 ESD@
2
SC300001Y00
2 2
+USB3_VCCA
W=100mils
DS22 ESD@
USB20_N1_L 6 3
I/O4 I/O2 1 1
LS2 EMI@ +USB3_VCCA CS25 + CS26
2 1 USB20_P1_L 220U_6.3V_ESR18M_6.3X4.5 470P_0402_50V7K
<13> USB20_P1 2 1 5 2 2
SF000006R00 @
USB20_N1_L
VDD GND 2 USB3.0 Conn.
3 4
<13> USB20_N1 3 4 JUSB1
DLM0NSN900HY2D_4P 4 1 USB20_P1_L 1
SM070005U00 I/O3 I/O1 USB20_N1_L 2 VBUS
AZC099-04S.R7G_SOT23-6 USB20_P1_L 3 D-
4 D+
USB3_CRX_L_DTX_N1 5 GND
USB3_CRX_L_DTX_P1 6 SSRX- 10
7 SSRX+ GND 11
SWAP pin 12/13 USB3_CTX_L_DRX_N1 8 GND GND 12
USB3_CTX_L_DRX_P1 9 SSTX- GND 13
SSTX+ GND
ACON_TARBA-9U1393
CONN@
3 3
DC23300TT00
Change USB3.0 Conn. symbol 11/16
remove USB Charger IC 12/12
4 4

USB Conn/USB_B
A B C D E
5 4 3 2 1
USB2.0 (Port 2)
Swap pin again 12/13
D
@ D
CS3 1 2 USB3_CTX_C_DRX_N2 RS5 1 @ 2 0_0402_5% USB3_CTX_L_DRX_N2 DS23 @ESD@
<13> USB3_CTX_DRX_N2 USB3_CTX_L_DRX_P2 USB3_CTX_L_DRX_P2
.1U_0402_16V7K 1 1 10 9
@
CS4 1 2 USB3_CTX_C_DRX_P2 RS6 1 @ 2 0_0402_5% USB3_CTX_L_DRX_P2 USB3_CTX_L_DRX_N2 2 2 9 8
USB3_CTX_L_DRX_N2
<13> USB3_CTX_DRX_P2
.1U_0402_16V7K
USB3_CRX_L_DTX_P2 4 4 7 7
USB3_CRX_L_DTX_P2
USB3_CRX_DTX_N2 RS7 1 @ 2 0_0402_5% USB3_CRX_L_DTX_N2
<13> USB3_CRX_DTX_N2 USB3_CRX_L_DTX_N2 USB3_CRX_L_DTX_N2
5 5 6 6
USB3_CRX_DTX_P2 RS8 1 @ 2 0_0402_5% USB3_CRX_L_DTX_P2 3 3
<13> USB3_CRX_DTX_P2
8
AZ1045-04F_DFN2510P10E-10-9
SC300001Y00
Place near JUSB2
+USB3_VCCA
W=100mils
1
CS91 USB2.0 Conn.
470P_0402_50V7K
2 @
DS24 ESD@
6 3 USB20_P2_L
LS5 EMI@ I/O4 I/O2 JUSB2
USB20_P2 2 1 USB20_P2_L +USB3_VCCA 1
<13> USB20_P2 2 1 USB20_N2_L VBUS
2
C 5 2 USB20_P2_L 3 D- C
USB20_N2 3 4 USB20_N2_L VDD GND 4 D+
<13> USB20_N2 3 4 GND
5
DLM0NSN900HY2D_4P 6 GND
SM070005U00 4 1 USB20_N2_L 7 GND
I/O3 I/O1 8 GND
AZC099-04S.R7G_SOT23-6 GND
C-K_20282-8K19-06_4P
RC281 1 @ 2 0_0201_1% T263 @

@ T264
RC280 1 @ 2 0_0201_1% T266 @ Change USB3.0 Conn. symbol
@ T265
Reserve U3 first 11/16
B
USB/B (USBx1,Card Reader,SPK) B
+5VALW
CONN@
DVT
1 @EMI@ 2 SP01001KD00
ESD@ CS11
RS30 0_0402_5% ACES_51522-02001-P02
1U_0201_6.3V6M
1 1
1U_0402_6.3V6K
SM070005U00 22
USB2 I/O DLM0NSN900HY2D_4P 21 GND
@ESD@
3 4 USB20_L_N3 GND
CS10
<13> USB20_N3 3 4 2 2
20
2 1 USB20_L_P3 19 20
<13> USB20_P3 2 1 19
18
LS3 @EMI@ DVT 1/29 17 18
RS10 16 17
1 @EMI@ 2 0_0402_5% 15 16
RS31 0_0402_5% 2 1 14 15
@ SPK_R+ 13 14
<25> SPK_R+ 13
12
SPK_R- 11 12
<25> SPK_R- 11
1 @EMI@ 2 10
RS32 0_0402_5% 9 10
Card reader SM070005U00
<27,29> USB_EN
USB_EN 8 9
DLM0NSN900HY2D_4P 7 8
3 4 USB20_L_N4 USB20_L_N4 6 7
<13> USB20_N4 3 4 USB20_L_P4 6
Card reader 5
4 5
2 1 USB20_L_P4 USB20_L_N3 3 4
<13> USB20_P4 2 1 USB20_L_P3 3
USB2.0 Conn. 2
LS4 @EMI@ 1 2
1
1 @EMI@ 2 JIO1
A RS33 0_0402_5% A
PVT change JIO1 symbol
PVT RS30,RS31,RS32,RS33 Change to R-short

LS3 ,LS4 cover solder mask

USB2.0 / IO_B
5 4 3 2 1
Vinafix.com
A B C D E
+3VLP_EC PN:SM01000K500 +3VLP_ECA

+3VLP @ RB22 LB1
EC_RST#
0_0805_5% FBMA-L11-160808-800LMT_0603
+3VLP_ECA
near SOC SOC_RTCRST# <11>
CB9 1 2 0.1U_0201_10V6K 1 2 1 2
D
1
Change to 0.1U 11/26 EC_CLR_CMOS 2 QB6
+3VALW_1.8VALW_PGPPA
0.1U_0201_10V6K
CB2
0.1U_0201_10V6K
CB3
1U_0201_6.3V6M
CB1
1 1 1 G L2N7002WT1G_SC-70-3
1
S SB00001GE00
3
1
0_0402_5%
RB26
RB2
10K_0402_5%
+3VLP_EC 2 2 RB3 @ 2
0_0402_5%
2
@ ECAGND
ECAGND <35>
2
1 @ 2 EC_PME#
2
1 RB5 47K_0402_5% +3VCC_LPC 1
EC_PME# PU +3V_LAN at LAN side
111
125
22
33
96
67
9
+3VLP_EC UB1
VCC0
VCC_LPC
VCC
VCC
VCC
VCC
AVCC
RB13 1 2 2.2K_0402_5% EC_SMB_CK1
RB14 1 2 2.2K_0402_5% EC_SMB_DA1
ESPI Bus Pin : 1~5.7.8.10.12.14
LPC Bus Pin : 3~5.7.8.10.12.13 SUSPWRDNACK 1 21 EC_VCCST_PG_R
<11> SUSPWRDNACK 2 GATEA20/GPIO00 EC_VCCST_PG/GPIO0F 23 BEEP# EC_VCCST_PG_R <11,32>
EC_SERIRQ 3 KBRST#/GPIO01 BEEP#/GPIO10 26 FAN_PWM1 BEEP# <25>
remove pin2 11/14
<9> EC_SERIRQ SERIRQ EC_FAN_PWM/GPIO12 FAN_PWM1 <31>
LPC_FRAME# 4 27
<9> LPC_FRAME# LPC_AD3_R LPC_FRAME# PWM Output AC_OFF/GPIO13
For turn off internal LPC module of KB9032 5 remove pin27 12/12
<9> LPC_AD3_R LPC_AD2_R 7 LPC_AD3
<9> LPC_AD2_R LPC_AD1_R 8 LPC_AD2 63 BATT_TEMP
ESPI@
1 2 ESPI_RST# <9> LPC_AD1_R LPC_AD0_R 10 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38 64 VCIN1_BATT_DROP BATT_TEMP <35,36> +3VLP_EC
<9> LPC_AD0_R LPC_AD0LPC & MISC VCIN1_BATT_DROP/AD1/GPIO39 ADP_I VCIN1_BATT_DROP <35>
RB8 47K_0402_5% 65
CLK_LPC_EC 12 ADP_I/AD2/GPIO3A 66 AD_BID ADP_I <35,36>
<9> CLK_LPC_EC PLT_RST# CLK_PCI_EC AD Input AD_BID/AD3/GPIO3B WLAN_PME# LID_SW#
ESPI@ 13 75 RB15 1 2 100K_0402_1%
1 2 PLT_RST# <11,30> PLT_RST# EC_RST# 37 PCIRST#/GPIO05 AD4/GPIO42 76 EC_PME# WLAN_PME# <24>
<31> EC_RST# EC_SCI# 20 EC_RST# AD5/GPIO43 EC_PME# <23>
RB9 47K_0402_5% Combine w/ SMI
<7> EC_SCI# WLAN_ON 38 EC_SCI#/GPIO0E
1 2 <24> WLAN_ON CLKRUN#/GPIO1D
CB5 @ESD@ 100P_0402_50V8J 68 LAN_PWR_EN
<30> KSI[0..7] DA0/GPIO3C 70 EC_TP_INT# LAN_PWR_EN <23>
DA Output EN_DFAN1/DA1/GPIO3D VR_PWRGD EC_TP_INT# <7,30>
1 2 KSI0 55 71
KSI1 56 KSI0/GPIO30 DA2/GPIO3E 72 KBL_EN VR_PWRGD <41>
CB10 @ESD@ 100P_0402_50V8J
Place on CPU side 12/19 57 KSI1/GPIO31 DA3/GPIO3F KBL_EN <30>
KSI2
KSI3 58 KSI2/GPIO32 83 EC_MUTE#
KSI4 59 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A 84 USB_EN EC_MUTE# <25>
1 2 AC_IN KSI5 60 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B 85 USB_EN <27,28>
KSI5/GPIO35 PSCLK2/GPIO4C
remove pin85 11/9
2 KSI6 61 86 remove pin86 12/12 2
CB6 100P_0402_50V8J
KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D TP_CLK SYS_PWROK_R
KSI7 62 87 1 @ 2 SYS_PWROK <11,32>
<30> KSO[0..17] 39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TP_DATA TP_CLK <30>
@EMI@ @EMI@ KSO0 RB11 0_0402_5%
2 1 2 1 CLK_LPC_EC 40 KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <30>PU at PTP side
KSO1
CB7 RB10 33_0402_5% KSO2 41 KSO1/GPIO21
22P_0402_50V8J KSO3 42 KSO2/GPIO22 97 ENBKL
43 KSO3/GPIO23 ENKBL/GPXIOA00 98 TP_PWR_EN ENBKL <7>
KSO4
KSO5 44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 ME_EN TP_PWR_EN <30>
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH ME_EN <10>
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH1/GPXIOD00 VCIN0_PH <35>
DB1
For Thermal Portect Shutdown
KSO8 47 KSO7/GPIO27
KSO8/GPIO28 SPI Device Interface SPOK_5V
RB751V-40_SOD323-2
3V_EN
KSO9 48 119 Add SPOK_5V 11/21 MAINPWON 1 2
KSO10 49 KSO9/GPIO29 MISO/GPIO5B 120 BT_ON SPOK_5V <37> 3V_EN <37>
50 KSO10/GPIO2A MOSI/GPIO5C 126 EC_CLR_CMOS BT_ON <24>
KSO11 SPI Flash ROM SPICLK/GPIO58
KSO12 51 KSO11/GPIO2B 128 FP_PWR_EN 3V_EN_R 1 2 RB17 1 2
KSO13 52 KSO12/GPIO2C SPICS#/GPIO5A FP_PWR_EN <30>
RB16 1M_0402_5%
KSO14 53 KSO13/GPIO2D 1K_0402_5%
KSO15 54 KSO14/GPIO2E 73 remove pin73 1/3
KSO16 81 KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 74 SYS_PWROK_R
KSO17 82 KSO16/GPIO48 SYS_PWROK/AD7/GPIO41 89 BATT_4S
KSO17/GPIO49 GPIO50 90 BATT_BLUE_LED# BATT_4S <36>
BATT_CHG_LED#/GPIO52 91 BATT_BLUE_LED# <31>
CAPS_LED#/GPIO53
remove pin91 12/12
EC_SMB_CK1 77 92 PWR_LED#
PU at CPU side <35,36> EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CLK1/GPIO44 GPIO PWR_LED#/GPIO54 BATT_AMB_LED# PWR_LED# <31>
78 93
<35,36> EC_SMB_DA1 SOC_SML1CLK 79 EC_SMB_DAT1/GPIO45 BATT_LOW_LED#/GPIO55 95 SYSON BATT_AMB_LED# <31>
T262
<9> SOC_SML1CLK SOC_SML1DATA 80 EC_SMB_CLK2/GPIO46 SYSON/GPIO56 121 VR_ON SYSON <14,32,38>
@
<9> SOC_SML1DATA EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 VR_ON <32,41>
1
D
127
DPWROK_EC/GPIO59 2
SM Bus remove pin127 12/12 @ T261 QB7
G L2N7002WT1G_SC-70-3
PM_SLP_S3# 6 100 EC_RSMRST#
<11,32> PM_SLP_S3# EC_RSMRST# <11> remove pin101 1/3
S SB00001GE00
3
SPOK_3V 1 @ 2 ESPI_RST# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101
<9> ESPI_RST# SPOK_3V 15 GPIO07 GPXIOA04 102 VCIN1_ADP_PROCHOT
RB27 0_0402_5%
3 SPOK_5V 1 2 SPOK_3V_5V <37,40> SPOK_3V TP_EN 16 GPIO08 VCIN1_ADP_PROCHOT/GPXIOA05 103 VCOUT1_PROCHOT# VCIN1_ADP_PROCHOT <35> 3
pin15 change to SPOK_3V 11/17 <30> TP_EN TS_EN 17 GPIO0A VCOUT1_PROCHOT#/GPXIOA06 104 MAINPWON
RB28 @ 0_0402_5%
<12,21> TS_EN WL_OFF# 18 GPIO0B VCOUT0_MAIN_PWR_ON/GPXIOA07 105 BKOFF# MAINPWON <31,37>
<24> WL_OFF# AC_PRESENT 19 GPIO0C BKOFF#/GPXIOA08 106 LAN_GPO BKOFF# <21>
<11> AC_PRESENT AC_PRESENT/GPIO0D GPIO GPO GPXIOA09 3V_EN_R LAN_GPO <23>
25 107
For abnormal shutdown FAN_SPEED1 28 PWM2/GPIO11 PCH_PWR_EN/GPXIOA10 108 PM_SLP_S0#
<31> FAN_SPEED1 29 FAN_SPEED1/GPIO14 PWR_VCCST_PG/GPXIOA11 PM_SLP_S0# <11,14,30>
remove pin29 11/9 FANFB1/GPIO15
DB2 E51TXD_P80DATA 30
<24> E51TXD_P80DATA E51RXD_P80CLK 31 EC_TX/GPIO16 110 AC_IN
RB751V-40_SOD323-2
SPOK_3V_5V 1 2 EC_RSMRST# <24> E51RXD_P80CLK PCH_PWROK 32 EC_RX/GPIO17 VCIN1_AC_IN/GPXIOD01 112 EC_ON AC_IN <36>
<11,32> PCH_PWROK PWR_SUSP_LED# 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 EC_ON <37>
ON/OFFBTN#
<31> PWR_SUSP_LED# 36 SUSP_LED#/GPIO19 ON/OFF#/GPXIOD03 115 LID_SW# ON/OFFBTN# <30>
DB3 GPI
NUM_LED#/GPIO1A LID_SW#/GPXIOD04 116 SUSP# LID_SW# <31>
RB751V-40_SOD323-2
1 2 PCH_PWROK SUSP#/GPXIOD05 117 SUSP# <14,32,36,38> remove pin117 1/3
GPXIOD06 118 H_PECI_R 1 2
PBTN_OUT# PECI/GPXIOD07 H_PECI <7>
122 RB19 43_0402_1%
<11> PBTN_OUT# PM_SLP_S4# 123 PBTN_OUT#/GPIO5D 124
DB4 +3VLP_EC
<11,32> PM_SLP_S4# PM_SLP_S4#/GPIO5E V18R/VCC_IO2
RB751V-40_SOD323-2
EC_VCCST_PG_R
AGND
1 2
GND
GND
GND
GND
GND
remove 1/3
KB9022QD_LQFP128_14X14
11
24
35
94
113
ECAGND 69
Board ID 20mil
+3VLP_EC
CO-LAY with KB9032QA (SA000080J00) 1 2 BATT_TEMP
CB8
100P_0402_50V8J
RB4 DVT@ LB2 2 1
2
15K_0402_1% FBMA-L11-160808-800LMT_0603
RB1 SD034150280 PN:SM01000K500
Ra 100K_0402_1%
RB4 PVT@
20K_0402_1%
1
4 AD_BID SD034200280 RB20 1 @ 2 0_0402_5% VR_HOT# 4

VR_HOT# <41>
1
1 RB4 MP@
RB4 CB4 27K_0402_1% H_PROCHOT# RB21 1 @ 2 0_0402_5% VCOUT1_PROCHOT#
<7,36> H_PROCHOT#
Rb 0_0402_5% 0.1U_0201_10V6K SD034270280
EVT@ @
2
2

Please see page 3.

Vinafix.com
Analog Board ID definition,
EC ENE KB9022
A B C D E
A B C D E
change Pin define same as EH5AW 11/16

TP/B Conn.
ON/OFF BTN
RK1
KB Conn. +3VS RK3
+3V_PTP
JKB1
100K_0402_5% +3VALW 0_0402_5%
2 1 30 2 @ 1
+3VLP GND2
29
KSO16 28 GND1
ON/OFFBTN# KSO17 27 28 UK1 +3V_PTP
<29> ON/OFFBTN# 27 +3V_PTP
KSO0 26 5 1
26 IN OUT
1U_0201_6.3V6M
1U_0201_6.3V6M
KSO1 25 1 @ CK2
1 KSO2 24 25 2 0.1U_0201_10V6K 1
24 GND
2
CK13
CK3
KSO3 23 1 1 CK1 2 1 JTP1
KSO4 22 23 4 3 1
22 EN OC 4.7U_0402_6.3V6M 1
KSO5 21 2 RK4 TP_CLK 2
KSO6 20 21 @ SY6288C20AAC_SOT23-5 10K_0402_5% TP_DATA 3 2
KSO7 19 20 2 2 EC PS2 4 3
1
PVT Remove SWK1 3/27 KSO8 18 19 EC_TP_INT# I2C_1_SDA_R 5 4
KSO9 17 18 I2C_1_SCL_R 6 5
KSO10 16 17 TP_PWR_EN <29> PCH I2C EC_TP_INT# 7 6
15 16 <7,29> EC_TP_INT# TP_EN 8 7
KSO11 <29> TP_EN
KSO12 14 15 9 8
KSO13 13 14 TP_PWR_EN follow SYSON behavior 10 GND
KSO14 12 13 GND
KSO15 11 12 ACES_51524-00801-001
KSI0 10 11 CONN@
KSI[0..7] KSI1 9 10
KSI[0..7] <29> KSI2 8 9 SP01001A910
KSO[0..17] KSI3 7 8 +3V_PTP +3V_PTP
KSO[0..17] <29> 6 7 +3V_PTP
KSI4
KSI5 5 6
KSI6 4 5
4
1
KSI7 3 RK7 RK10
3
1
2 2.2K_0402_5% 2.2K_0402_5%
G
2
KB BackLight ON/OFFBTN# 1
1
QK1B
2N7002KDW_SOT363-6
RK5
4.7K_0402_5%
RK6
4.7K_0402_5%
2
ACES_85201-2805 3 4 I2C_1_SCL_R
S
<12> I2C_1_SCL
2
+5VS JBL1 CONN@
D
U1 1
5
IN OUT
1 +5VS_BL 2 1
2
SP01000GO00 1 2
<29> TP_CLK
TP_CLK
3 RK8 @ 0_0402_5% TP_DATA
3 <29> TP_DATA
2
2 4
G
2 GND 4 2
4 3 5 QK1A
<29> KBL_EN EN OC GND
6 2N7002KDW_SOT363-6
SY6288C20AAC_SOT23-5 GND 6 1 I2C_1_SDA_R
S
<12> I2C_1_SDA
ACES_51524-0040N-001
D
1 CONN@
1 @ 2
C3 SP010022M00 RK9 0_0402_5%
0.1U_0201_10V6K
2
TPM
+3VALW
change TPM to NPCT750 11/16
RW1 +3VALW_TPM +3VS RW2 +3VS_TPM

Finger Print
0_0603_5% 0_0603_5%
1 @ 2 1 @ 2 Power Souce Check
EGIS ETU801 +FP_VCC=5V
0.1U_0201_10V6K
CW2 TPM@
0.1U_0201_10V6K
CW4 TPM@
0.1U_0201_10V6K
CW5 TPM@
0.1U_0201_10V6K
CW6 TPM@
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
CW1
CW7
CW3
CW8
1 1 1 1 1 1 1 1
ELAN SA464K-2200 +FP_VCC=3.3V
+FP_VCC
2 2 2 near pin1 2 2 2 2 2
TPM@
TPM@
TPM@
TPM@
+FP_VCC
RK16 1 FP@ 2 0_0603_5% UK6 SP010020S00
+3VALW CONN@
+5VALW RK17 1 @ 2 0_0603_5% 5 1
IN OUT JXT_FP201H-008G10M
1
2 FP@ 1
GND CK12 USB20_P8_L 2 1
3 4 3 USB20_N8_L 3 2 3
near pin8,22 EN OC 2
4.7U_0402_6.3V6M
4 3
1 4
+3VALW_TPM FP@ SY6288C20AAC_SOT23-5 5
CK11 FP@ 6 5
1U_0201_6.3V6M 7 6
RW10 1 TPM@ 2 10K_0402_5% TPM_PIRQ# 2 8 7
FP_PWR_EN <29> 8
9
SOC_SPI_SO RW5 1 TPM@ 2 33_0402_5% SOC_SPI_SO_TPM_R 10 GND
<9> SOC_SPI_SO GND
SOC_SPI_SI RW6 1 TPM@ 2 33_0402_5% SOC_SPI_SI_TPM_R JFP1
<9> SOC_SPI_SI
LK2 FPEMC@
SOC_SPI_CLK RW7 1 TPM@ 2 33_0402_5% SOC_SPI_CLK_TPM_R USB20_N8 3 4 USB20_N8_L
<9> SOC_SPI_CLK <13> USB20_N8 3 4 Update pin define 01/19
+3VALW_TPM USB20_P8 2 1 USB20_P8_L

UW1 place close and before UC7 <13> USB20_P8 2 1
UW1 TPM@ DLM0NSN900HY2D_4P
1 +3VS_TPM SM070005U00
2 TPM@ 1 29 VSB
<11,14,29> PM_SLP_S0#
RW11 0_0402_5% 30 SDA/GPIO0 8 PIN ETU801 SA464K-2200
SCL/GPIO1 VHIO 22
6 VHIO DK2 FPEMC@ 1 +FP_VCC(5V) +FP_VCC(3V)
GPIO3 2 6 3 USB20_N8_L
SOC_SPI_SO_TPM_R 24 NC 3 I/O4 I/O2 2 USBP D+
SOC_SPI_SI_TPM_R 21 MISO NC 5
TPM_PIRQ# 18 MOSI/GPIO7 NC 7 3 USBN D-
<13> TPM_PIRQ# PIRQ/GPIO2 NC 9 5 2
NC 10
+FP_VCC VDD GND 4 GND GND
SOC_SPI_CLK_TPM_R 19 NC 11
SOC_SPI_CS#2 20 SCLK NC 12 5 NC NC
<9> SOC_SPI_CS#2 PLT_RST# SCS/GPIO5 NC USB20_P8_L
17 14 4 1
4 <11,29> PLT_RST#
27 PLTRST NC 15 I/O3 I/O1 6 NC NC 4
13 NC NC 26 AZC099-04S.R7G_SOT23-6
GPIO4 NC 25 7 NC
NC 28
4 NC 31 8 NC
PP/GPIO6 NC 32
NC
16
GND 23 Security Classification Compal Secret Data Compal Electronics, Inc.
GND 33
PGND Issued Date 2016/11/04 Deciphered Date 2018/11/04 Title
Vinafix.com NPCT750AAAYX_QFN32_5X5
KB & TP & TPM & LID & FP
SA0000AQ230 S IC NPCT750AAAYX QFN 32P TPM AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
SA0000AQ250 S IC NPCT750AABYX QFN 32P TPM MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH7L1 LA-H782P
A B C D E
A B C D E
FAN1 Conn Screw Hole

+5VS
40mil
RF1 1 @ 2 0_0603_5% +VCC_FAN1 H1 H2 H3 H4 H5 H6 H7 H8
1 2 H_3P0-G H_3P0-G H_3P3 H_3P3 H_3P3 H_3P3 H_3P0-G H_4P5X4P0
1 FD1 FD2 1
@EMI@ CF2 CF1
1000P_0402_50V7K 4.7U_0402_6.3V6M
1
2 1 @ @
1
FIDUCIAL_C40M80 FIDUCIAL_C40M80
@ @ @ @ @ @ @ @
FD3 FD4
@ @
1
+3VS H20 H22 FIDUCIAL_C40M80 FIDUCIAL_C40M80
H_2P0N H_2P7X2P0N
1
RF2 @ @
1
10K_0402_5%
40mil
JFAN1
2
+VCC_FAN1 1
FAN_SPEED1 2 1
<29> FAN_SPEED1 FAN_PWM1 3 2
<29> FAN_PWM1 4 3
1 4
5
6 G1
CF3 G2
2 1000P_0402_50V7K ACES_50278-00401-001
@EMI@ CONN@
SP02000RR00
2 2
Lid Switch
(Hall Effect Switch) Reset Circuit
+3VLP +3VLP
JLID2 +3VLP
JLID1 1
1 LID_SW# 2 1 RG1 1 @ 2 0_0402_5%
LID_SW# 2 1 <29> LID_SW# 3 2 MAINPWON <29,37>
2 3
2
3 5 4
4 3 G1 6 PWR_LED# 5 4 RG3 RG2 1 @ 2 0_0402_5%
4 G2 <29> PWR_LED# PWR_SUSP_LED# 5 EC_RST# <29>
6 10K_0402_5%
<29> PWR_SUSP_LED# BATT_BLUE_LED# 6
ACES_51575-00401-001 7
<29> BATT_BLUE_LED# BATT_AMB_LED# 7
CONN@ 8
<29> BATT_AMB_LED#
1
8
6
9 11 D
+5VALW 10 9 G11 12 BI_GATE# 2
SP01002BY00 10 G12 G 2N7002KDW_SOT363-6
ACES_51530-01001-P01
BI_GATE PH to +RTCVCC at PWR side QG1A
3
add JLID1 11/30 D S
CONN@ 1
1
BI_GATE 5
3 <35> BI_GATE G C70 3
QG1B 0.1U_0201_10V6K
Update Pin define 11/20 2N7002KDW_SOT363-6 S 2
4
+3VLP
Battery LED
1U_0402_6.3V6K
0.1U_0201_10V6K
Reset Button
CC160
CC162
1 1 LED1
RG4
680_0402_5%
@ BATT_AMB_LED# 1 2 3 A 4
2 2 +5VALW
15@
SWG2
BATT_BLUE_LED# 1 2 1 B 2 BI_GATE 1 2 BI_GATE
15@
RG6 remove SWG1 11/27
560_0402_5% LTST-C295TBKF-CA_AMBER-BLUE
15@ 3 4
PVT
SKRPABE010_4P
Power LED
LED2
RG11
680_0402_5%
PWR_SUSP_LED# 1 2 3 A 4
4 4
15@
PWR_LED# 1 2 1 B 2
+5VALW
RG10
560_0402_5%
LTST-C295TBKF-CA_AMBER-BLUE
15@ 15@
FAN &LID& Screw Hole & Reset
A B C D E
A B C D E
DC Interface 1U_0402_6.3V6K
+5VALW
UQ1
CQ5
.1U_0402_16V7K
1 2
+5VS
For Power ON/Off Sequence PM_SLP_S3
2 1 1 14 @ JPQ2
CQ10 2 VIN1 VOUT1 13 +5VS_OUT 1 2 +3VALW
VIN1 VOUT1 1 2
2
G
1
SUSP# 2 @ 1 0_0402_5% 5VS_ON 3 12 1 2 JUMP_43X118 Q1A
RQ2 ON1 CT1 CQ1 1000P_0402_50V7K R24 2N7002KDW_SOT363-6
1 2 CQ4 4 11 100K_0402_5%
+5VALW VBIAS GND
@ 1 6
S
EC_VCCST_PG_R <11,29>
D
.1U_0402_16V7K 5 10
2
ON2 CT2
.1U_0402_16V7K
1 MOW14, For tCPU28 200us(max)
6 9 SLP_S3# to VCCST_PWRGD deassertion
VIN2 VOUT2
5
7 8
G
1 VIN2 VOUT2
CQ13
1
2 15 Q1B
GPAD Q2A 2N7002KDW_SOT363-6
AOZ1331DI_DFN14_2X3 2N7002KDW_SOT363-6 4 3
S
VR_ON <29,41>
D
SA0000BEL00 D
2 MOW14, For tPLT17 200us(max)
<11,29> PM_SLP_S3# G SLP_S3# to IMVP VR_ON deassertion
5
UQ2
G
1 14 S
1
2 VIN1 VOUT1 13 Q2B
VIN1 VOUT1 2N7002KDW_SOT363-6
.1U_0402_16V7K 3 12 4 3 SUSP#
S
ON1 CT1
D
CQ14 2 1
@ 4 11 +3VS MOW14, For tPLT18 200us(max)
+5VALW VBIAS GND
SLP_S3# to VCCIO VR disable
2
SUSP# 2 @ 1 0_0402_5% 3VS_ON 5 10 1 2
G
RQ1 ON2 CT2 CQ3 1000P_0402_50V7K Q3A @
1 2 6 9 @ JPQ1 2N7002KDW_SOT363-6
+3VALW VIN2 VOUT2 +3VS_OUT
CQ2 @ 7 8 1 2
.1U_0402_16V7K VIN2 VOUT2 1 2 1 6
S
1 SYS_PWROK <11,29>
D
1 15 .1U_0402_16V7K JUMP_43X118
CQ11 GPAD
AOZ1331DI_DFN14_2X3 CQ6
5
1U_0402_6.3V6K SA0000BEL00 2
G
2 +3VALW Q3B @
2N7002KDW_SOT363-6
PVT Change to SA0000BEL00 3/28
1
4 3
S
PCH_PWROK <11,29>
D
R29
100K_0402_5%
2
2 +5VALW +0.6VS_VTT Q6A PM_SLP_S4 2
+2.5V 2N7002KDW_SOT363-6
5
+1.2V_VDDQ +5VALW D
G
2
2 Q6B
<11,29> PM_SLP_S4#
2
R25 R26 G 2N7002KDW_SOT363-6
2
100K_0402_5% @ @ 470_0603_5% R31
2
470_0603_5% R27 R28 S 4 3 SYSON
S
1
D
+0.6VS_VTT_R
@ 470_0603_5% 100K_0402_5% MOW14, For tPLT15 200us(max)
1
SUSP @ @ SLP_S4# to VDDQ ramp down

1
1
Q4A @ Q4B @
1
2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
6
D +1.2V_VDDQ_R
D D SYSON#
2 5 SUSP SYSON# 2 Q7
<14,29,36,38> SUSP# G G G L2N7002WT1G_SC-70-3 Q5A @ Q5B @
@ S SB00001GE00 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
3
1
3
S S D D
1
R30 SYSON# 2 5 SYSON

G G SYSON <14,29,38>
10K_0402_5%
@
S S
2
4
3 3
4 4

DC Interface
A B C D E
5 4 3 2 1
PCB Number
Kabylake_U22 CPU Part Number Kabylake_R U42 CPU Part Number
HDCP2.2
UC1 SR3LA@ UC1 SR3LABR@
CPU_KBL_Y0_U42_I5-8250U_1.6G CPU_KBL_Y0_U42_I5-8250U_1.6G ZZZ PCB@
UC1 SR343@ UC1 SR343BR@ SA0000AW B40 SA0000AW B90 PCB 2MD LA-H782P REV0 MB 3
CPU_KBL_H0_i3-7100U_2.4G CPU_KBL_H0_i3-7100U_2.4G DA60026S000
SA0000A38M0 SA0000A38O0 UC1 SR3LC@ UC1 SR3LCBR@
CPU_KBL_Y0_U42_I7-8550U_1.8G CPU_KBL_Y0_U42_I7-8550U_1.8G
D UC1 SR342@ UC1 SR342BR@ SA0000AW C40 SA0000AW C70 D
CPU_KBL_H0_i5-7200U_2.5G CPU_KBL_H0_i5-7200U_2.5G
SA0000A37N0 SA0000A37O0 ZZZ UMADAZ10@
PCB EH7L1 LA-H782P LS-H781P/H783P/H784P
UC1 SR341@ UC1 SR341BR@ DAZ2MD00200
CPU_KBL_H0_i7-7500U_2.7G CPU_KBL_H0_i7-7500U_2.7G
SA0000A34L0 SA0000A34M0
UC1 SR3JY@ ZZZ UMADAZ1A@

CPU_KBL_H0_i3-7130U_2.7G PCB EH7L1 LA-H782P LS-H781P/H783P/H784P
SA0000B2Y70 DAZ2MD00202
UC1 SR3TK@
CPU_KBL_H0_i3-7020U_2.3G
SA0000BLH60
Kabylake_RU22 CPU Part Number Kabylake_U23E Fuse Down CPU
UC1 SR3W 0@ UC1 SR3N6@ UC1 QNMU@

CPU_KBL_Y0_RU22_I3-8130U_2.2G CPU_KBL_J1_i3-7020U_2.3G CPU_KBL_J1_i3-7020U_2.3G QS
SA0000BKN60 SA0000BVB10 SA0000BVB00
UC1 SR3W 0BR@

CPU_KBL_Y0_RU22_I3-8130U_2.2G
SA0000BKN70
C UC1 SR3LD@ C
CPU_KBL_Y0_RU22_I3-7020U_2.3G
SA0000BLD70
B B
A A

CPU/X76 BOM
5 4 3 2 1
A B C D E
1 1
EMI 90W@ PL102

5A_Z120_25M_0805_2P
1 2
+19V_ADPIN 5A_Z120_25M_0805_2P
EMI@ PL101
+19V_VIN
pitch 1.25mm, 1 2
6
G2 5
G1
1
4
4
1
3 EMI@ PC104
3 2 EMI@ PC105 PC102 EMI@ 1000P_0402_50V7K
2
2 1 1000P_0402_50V7K 100P_0402_50V8J
2
1
ACES_50278-00401-001
@ PJP101
2 2
PR101
1 2
+3VLP +CHGRTC
0_0402_5%
3 3
4 4
2018/01/10
Compal Secret Data
2018/11/04 Title
PWR DCIN / Pre-charge
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH5AW M/B LA-G521P
A B C D E
A B C D E
2013/07/23
change PC5 and PC6 function field from 37.1 to 47.1
1 1
PR207 100_0402_1%
MB:Battery Con Put TOP Side 1 2
EC_SMB_DA1 <29,36>
PR205 100_0402_1%
1 2
EC_SMB_CK1 <29,36>
Battery Bot Side PR202

200K_0402_1%
1 2
PIN1 GND @ PJP201 +3VLP
PIN2 GND 1 2
1
1 2
PIN3 SMD 2 3
3 4
EC_SMB_DA1-1 BATT_TEMP <29,36>
EC_SMB_CK1-1 PR203 1K_0402_1%
PIN4 SMC 4 5 BATT_TS
5 6
PIN5 TEMP 6 7
BATT_B/I
PIN6 BI 7 8
8 9 +RTCVCC
PIN7 Batt+ GND 10
PIN8 Batt+ GND
CVILU_CI9908M2HR0-NH
2016/11/16 update
1
PR212
100K_0402_5% For KB9022
PQ201 Change to SB00000QO00,
sense 20mΩ Active Recovery
SB501380010(BSS138LT1G Del)
2
2 2
1
D
<31> BI_GATE 2 PQ201
G LBSS139LT1G 1N SOT-23-3 45W PR206 58.5W,0.61V Active=recovery
+12.6V_BATT+ S
10K ohm
3
EMI@ PL201
2
5A_Z120_25M_0805_2P
1 2 PR217
change PL201, PL202 +12.6V_BATT 65W PR206
SM01000C000 to comm PL202 0_0402_5% 84.5W,0.61V
1 2
19.1K ohm Active=recovery
part SM01000P200
1
5A_Z120_25M_0805_2P
EMI@ 90W PR206 117W,0.61V
30.1K ohm Active=recovery
1
EMI@ PC201 EMI@ PC202

1000P_0402_50V7K 0.01U_0402_25V7K PH1 under CPU botten side :
2
PH1 2V 1V CPU thermal protection at 89 +-3 degree C

Recovery at 56 +-3 degree C
2013/06/07
Add for ENE9022 Battery Voltage drop detection.
Connect to ENE9022 pin64 AD1.
3 +3VLP_ECA 3
ADP_I <29,36>
+19VB_5V
VAL50/ZAL20 Battery is 3-cell NVDC design.
1
B+=9V PR204
Change PR12=50k if Battery is 2-cell NVDC design 16.9K_0402_1%
45W@ PR206
B+=6V
1
2.32K_0402_1%
2
PR209 65W@
VCIN0_PH <29>
750K_0402_1%
PR206
7.87K_0402_1%
PR210
2
1
1
1 2
VCIN1_BATT_DROP <29> PC203 must close to EC pin
2
PH201
VCIN1_ADP_PROCHOT <29>
@ PC203
0_0402_5% 100K_0402_1%_NCP15WF104F03RC 0.1U_0402_25V6
1
1
1
2
2
PC204 PR211 PR208

0.1U_0402_25V6 150K_0402_1%
T202 T201 must close to PH201
T202@ 10K_0402_1%
1
2
T201@
ECAGND <29>
4 4
2018/01/10
Compal Secret Data
2018/11/04 Title
PWR-BATTERY CONN/OTP
A B C D E
A B C D E
PRB1
1
D
1M_0402_1%
2 1 2
PQB1 +19VB PQB2 AON7506_DFN33-8-5
1
G L2N7002SW T1G_SOT323-3 2 +12.6V_BATT_CHG
PRB2 S 5 3
3
2 1
+19V_P1 +19V_P2
PQB3 3M_0402_5%
4
EMB04N03H_EDFN5X6-8-5
1
AON7506_DFN33-8-5
1
PQB4 PRB3
0.01_1206_1% EMI@ PLB1
+19V_CHG
2 2 SUPPRE_ 5A Z80 20M 0805
5 3 3 5 1 4 1 2
+19V_VIN
2 3
10U_0603_25V6M
10U_0603_25V6M
0.047U_0603_25V7M
4
4
1 1
PCB2
10U_0603_25V6M
1000P_0402_50V7K
2200P_0402_50V7K
1 2
1
1
PCB1
PCB3
PCB4
ACP ACN
68P_0402_50V8J
0.1U_0402_25V6
0.1U_0402_25V6
2
1
@EMI@ PCB5
EMI@ PCB6
EMI@ PCB9
EMI@ PCB10
0.022U_0603_25V7K
4.7_0603_1%
PRB4
4.02K_0402_1%
2
10_0402_1%
PCB12
PCB11
2
0.1U_0402_25V6 PCB13
PRB5
PRB6
2 1 1 2 1 2
1
ACDRV_CHGR_R
PCB7
PCB8
0.01U_0402_25V7K~N
2
ACFET MDU1512 SB00000SY00 0.1U_0402_25V7K
Rds(on):4.2~5m Ohm PRB7
Vgs=20V 4.02K_0402_1% BATDRV_CHGR
Vds=30V 1 2 ACDRV_CHGR
1
ID= 24.2A (Ta=70C)
PRB8 PRB9
0_0402_5%
2 1CMSRC_CHGR 0_0402_5% BATSRC_CHGR
PRB10
2
4.02K_0402_1%
ACN_CHGR
ACP_CHGR
+19V_VIN
PDB1 PRB12 @ PCB15
S SCH DIO BAS40CW SOT-323 10_1206_5% 1000P_0402_50V7K 2016/03/13 SE158225K80 X1
+19V_VIN
3 1 2 down size SE00000WP00 S
1
1 2 1
PRB11 +19VB 2 ACDRV_CHGR CER CAP 2.2U 25V K X5R 0603
422K_0402_1% PCB16 1U_0603_25V6K +6V_CHG_REGN
2 1 PCB18 PQB5
2.2U_0603_25V7M AON7506_DFN33-8-5
2
5
2 ACDET PUB1 2
1 2 Choke 4.7uH SH00000YC00 (Common Part)
ACDRV
ACP
ACN
28
VCC PRB14
(Size:6.6 x 7.3 x 3 mm)
66.5K_0402_1%
(DCR:28m~33m)
1
CMSRC_CHGR 3 24 0_0603_5%
CMSRC REGN
1
2DH_CHGR_R 4
PRB13
PCB19 1
6 PRB16
PCB17 0.047U_0603_25V7M
2200P_0402_25V7K PRB15 0_0402_5% ACDET 25 BST_CHGR1 2BST_CHGR_R 1 2
2
1 2 EC_SMB_DA1_CHGR 11 BTST
<29,35> EC_SMB_DA1 +12.6V_BATT
2
SDA
3
2
1
1 2 EC_SMB_CK1_CHGR 12 26 UG_CHGR 0_0603_5% PRB19
<29,35> EC_SMB_CK1 SCL HIDRV
PRB17 0_0402_5% PLB2 0.01_1206_1%
ACPRN_CHGR 5 4.7UH_PCMB063T-4R7MS_8A_20%
<29,35> ADP_I PCB20 ACOK 27 LX_CHGR 1 2 1 4
1 2 PRB18 1 2 0_0402_5% 7 PHASE
IADP 2 3
1
100P_0402_50V8J DCHG_I 8 23 LG_CHGR PQB6
4.7_1206_5%
IDCHG LODRV
5
@
EMI@ PRB20
PCB21
1 2 9
10U_0603_25V6M
10U_0603_25V6M
AON7506_DFN33-8-5
PMON
100P_0402_50V8J 10 22 PRB22 316K_0402_1% SRP SRN
1SNUB_CHGR 2
/PROCHOT GND
1
1 2
PCB22
PCB23
+3VLP 4
PRB24 78.7K_0402_1%
PRB23
2
13 21 ILIM_CHGR 1 2
1 2 GND ILIM PRB25
680P_0402_50V7K
<7,29> H_PROCHOT# 14 10_0402_1%
3
2
1
NC 20 SRP_CHGR 1 2
EMI@ PCB24
0_0402_5% PRB26 SRP
1 2 15 19 SRN_CHGR 1 2
20160601 colay BQ24781
2
/BATPRES SRN
3 PRB27 3
0_0402_5% 16 18 BATDRV_CHGR 10_0402_1% PCB25
/TB_STAT BATDRV 0.1U_0402_25V6
29 17 BATSRC_CHGR 1 2
PWPD BATSRC
For 4S per cell 4.35V battery <29,35> BATT_TEMP
BQ24781RUYR_W QFN28_4X4
1 2 CHG_TB_STAT
ACDET 3.3*100/(316+100)=0.79 H/L Side AON7506 SB000010A00
0.1U_0402_25V6
0.1U_0402_25V6
+6V_CHG_REGN ICHG= 0.79 /(20*0.01)=3.95A Rds(on):13~15.8mohm
1
PCB26
PCB27
@ PRB36 10K_0402_1%
Vgs=20V
1
4S_BATT@ 3.3*78.7/(316+78.7)=0.66 Vds=30V
2
PRB28 ICHG= 0.66 /(20*0.01)=3.28A ID= 10.5A (Ta=70C)
2M_0402_1%
+6V_CHG_REGN
1 2
4S_BATT@
PRB31
0_0402_5%
1
PRB32
2
10K_0402_1%
PRB34
1
4S_BATT@ 10K_0402_1%
2
PQB7 1 2 ACPRN_CHGR
4S_BATT@ PRB33 LMUN5236T1G NPN SOT323-3 <29> AC_IN 1
100K_0402_1%
1 2 2 PRB35
<29> BATT_4S
4 12K_0402_1% 4
2
4S_BATT@
3
1
PQB9 D
2
<14,29,32,38> SUSP# G
L2N7002SW T1G_SOT323-3S
3
2016/11/03 2017/06/14
Vinafix.com Issued Date Title
Deciphered Date
charger
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C5PRH M/B LA-E921P
A B C D E
A B C D E
PR302
499K_0402_1%
ENLDO_3V 1 2
EN1 and EN2 dont't floating
+19VB
1
150K_0402_1%
+19VB
PR303
EMI@ PL301 PC302
PR304
FBMA-L11-201209-800LMA50T 0.1U_0402_25V7K Choke 1.5uH SH000016800(Common Part)
1
1 2 +19VB_3V BST_3V 1 2 1 2 1
2200P_0402_50V7K
(Size:5 x 5 x 3 mm) DCR:9~10m ohm
10U_0603_25V6M
10U_0603_25V6M
2
EMI@ PC301
@EMI@ PC303
EMI@ PC304
0.1U_0402_25V6
0.1U_0402_25V6
1
1
0_0603_5%
PC305
PC306
1
PU301 SY8286BRAC_QFN20_3X3
2
PL302
BS
IN
IN
IN
IN
@ 1.5UH_6A_20%_5X5X3_M
LX_3V 6 20 LX_3V 1 2
LX LX +3VALWP
7 19
GND LX
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
8 18
+3VALWP GND GND
@ PC307
PC308
PC309
@ PC310
PC311
PC312
@EMI@
SPOK_3V 9 17 PR305
+3VLP
2
PG LDO 4.7_1206_5%
1 3V_SN
10 16
2
NC NC
1
PC313
OUT
EN2
EN1
21 4.7U_0402_6.3V6M
NC
FF
2
PR301 GND @EMI@
100K_0402_5% PC314
11
12
13
14
15
680P_0402_50V7K
2
Vout is 3.234V~3.366V
<29,40> SPOK_3V
3.3V LDO 150mA~300mA
ENLDO_3V PC315 PR306

1000P_0402_50V7K 1K_0402_5%
3V_FB 1 2 1 2
<29> 3V_EN
@ PJ301
+3VALWP 1 2 +3VALW
1 2
keep short pad, JUMP_43X118
2 +19VB_5V snubber is for EMI only. 2
+19VB EMI@ PL501 PC502

PR502
FBMA-L11-201209-800LMA50T 0.1U_0402_25V7K
1 2 +19VB_5V BST_5V 1 2 BST_5V_R 1 2
Choke 1.5uH SH00000II00, SH000008800, SH000019B00
2200P_0402_50V7K
0.1U_0402_25V6
0.1U_0402_25V6
0_0402_5% (Size:6.8 x 6.47 x 3 mm)

10U_0603_25V6M
10U_0603_25V6M
PU501
(DCR:14m~15m Ohm)
5
1
SY8288CRAC_QFN20_3X3
1
1
@EMI@ PC501
PC503
PC504
EMI@ PC505
@EMI@ PC506
BS
IN
IN
IN
IN
PL502
LX_5V 6 20 1.5UH +-20% 9A 7X7X3 MOLDING
2
LX LX
7 19 LX_5V 1 2
GND LX +5VALWP
8 18
GND GND
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
+3VLP
1
9 17 VCC_5V 1 2
PG VCC
1
PR503
PC508
PC509
PC510
PC511
PC512
PC513
4.7_1206_5%
@EMI@
10 16 PC507
2
NC NC
1
2.2U_0402_6.3V6M
OUT
LDO
EN2
EN1
21 @
FF
PR501 GND
2
100K_0402_5%
11
12
13
14
15
2
15V_SN
680P_0402_50V7K
<29> SPOK_5V +5VLP
ENLDO_5V
@EMI@
PC514
5V LDO 150mA~300mA
4.7U_0402_6.3V6M
2
1
PC515
PR504
2.2K_0402_5% 5V_3V_EN
2
1 2 Iocp=12A
<29> EC_ON PR505
1 2 EN1 and EN2 dont't be floating.
3
<29,31> MAINPWON EN :H>0.8V ; L<0.4V PC516 PR506 @ PJ501
3
1000P_0402_50V7K 1K_0402_1% +5VALWP 1 2 +5VALW
0_0402_5% 5V_FB 1 2 5V_FB_1 1 2 1 2
Fsw : 600K Hz
JUMP_43X118
5V_3V_EN
1M_0402_1%
1
1
PR507
PC517
4.7U_0402_6.3V6M
2
PR509
2
499K_0402_1%
ENLDO_5V 1 2
+19VB
1
150K_0402_1%
PR508
2
4 4

+3VALW/+5VALW
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH5AV_JV_0V_LA-G021P
A B C D E
A B C D E
Pin19 need pull separate from +1.35VP.

+19VB_1.2VP If you have +1.35V and +0.675V sequence question, 0.6Volt +/- 5%
@ PJM1 you can change from +1.35VP to +1.35VS. TDC 0.7A
JUMP_43X79
1
1 2 +19VB_1.2VP PRM1 Peak Current 1A 1
+19VB 1 2 2.2_0603_5%
BST_1.2VP_R 1 2 BST_1.2VP
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
0.1U_0402_25V6
+1.2VP
1
@EMI@ PCM1
EMI@ PCM2
PCM3
PCM4
UG_1.2VP +0.6VSP
2
PQM1
AON7408L_DFN8-5
LX_1.2VP
10U_0402_6.3V6M
10U_0402_6.3V6M
5
1
PCM5
1
PCM6
PCM7
0.1U_0402_25V7K
16
17
18
19
20
2
2
VLDOIN
PHASE
UGATE
BOOT
VTT
4 21
PAD
LG_1.2VP 15 1
LGATE VTTGND
PLM1
1
2
3
14 2
1UH_11A_20%_7X7X3_M PRM2 PGND VTTSNS
30.9K_0402_1% PUM1
1 2LX_1.2VP 1 2 CS_1.2VP 13 3
+1.2VP PCM8 CS RT8207PGQW _W QFN20_3X3 GND
1
1U_0402_10V6K
5
1 2 12 4 VTTREF_1.2VP
@EMI@ PRM3 PRM4 VDDP VTTREF
2 4.7_1206_5% 5.1_0603_5% 2
1 2 VDD_1.2VP 11 5
+5VALW +1.2VP
1 2
VDD VDDQ
1
PGOOD
PCM12
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
TON
1
PCM9
PCM13
PCM14
PCM10
PCM15
PCM16
@EMI@ PCM11 PCM17 0.033U_0402_16V7K
FB
S5
S3
2
1
680P_0402_50V7K
2
2 PQM2 1U_0402_10V6K
10
6
AON7506_DFN3X3-8-5 PRM5
1
2
3
2.2_0402_1%
FB_1.2VP
2
TON_1.2VP
EN_1.2VP
PRM6
+5VALW
EN_0.6VSP
6.19K_0402_1%
PRM7 1 2 +1.2VP
470K_0402_1%
+19VB_1.2VP 1 2
1
PRM8 48.7K_0402_1%
Vout=0.75V* (1+Rup/Rdown)
<14,29,32> SYSON
SYSON 1 2 PRM9 =0.75*(1+(6.19/10))
10K_0402_1%
=1.21V
2
1
PCM18
+5VALW 0.1U_0402_10V7K
2
+3VALW @ PRM10
0_0402_5%
1 2
<14,29,32,36> SUSP#
@ PJM2
3 JUMP_43X39 @ PJM3 3
PRM11
1
1 2 VIN_2.5V PCM19 JUMP_43X118

1 2 1 2 1 2
+1.2VP +1.2V_VDDQ
1U_0402_6.3V6K <8> SM_PG_CTRL 1 2
2
0_0402_5%
1
1
@ PCM21 @ PJM4
PCM20 JUMP_43X39
4.7U_0402_6.3V6M 0.1U_0402_10V7K 1 2
+0.6VSP +0.6VS_VTT
2
2
PUM2 1 2
G9661MF11U_SO8
4 5
PRM12 VPP NC
3 6 MOSFET: 3x3 DFN
SYSON 1 2 EN_2.5V 2 VIN VO 7 +2.5VP
H/S Rds(on): 27mohm(Typ), 32mohm(Max)
GND
1 VEN ADJ 8
22U_0603_6.3V6M
0.01U_0402_25V7K
POK GND Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C

1
0.1U_0402_16V7K
0_0402_5%
1
PCM23
PRM14
9
1
1
PCM22
PCM24
PRM13
21.5K_0402_1%
Rup L/S Rds(on): 13mohm(Typ), 15.8mohm(Max)
Vout=0.8V* (1+(21.5/10)) = 2.52V 0.8%Idsm: 12A@Ta=25C, 10.5A@Ta=70C
2
1M_0402_5%
2
2
2
FB_2.5V
@ Choke: 7x7x3
Rdc=14mohm(Typ), 15mohm(Max)
1
Mode Level +0.6VSP VTTREF_1.2V

PRM15
S5 L off off Switching Frequency: 538kHz
10K_0402_1%
Rdown S3 L off on Ipeak=7.5A
S0 H on on Iocp=Ipeak*1.2A
2
4
OVP: 110%~120% 4
@ PJM5
Note: S3 - sleep ; S5 - power off VFB=0.75V, Vout=1.365V
JUMP_43X39
1 2
MOSFET footprint: SIS412DN
+2.5VP 1 2 +2.5V

RT8207P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C5V01 M/B LA-E892P
A B C D E
A B C D E
EN pin don't floating

If have pull down resistor at HW side, pls delete PR702
1 +19VB_1VALW @EMI@ PRF2 @EMI@ PCF2

1
4.7_1206_5% 680P_0603_50V7K @ PJF1

@ PJF2 1 2 SNUB_1VALW 1 2 JUMP_43X118
PUF1 1 2
JUMP_43X79
+19VB_1VALW +1.0VALWP 1 2 +1.0VALW_PRIM
+19VB 2
2 1
1 2
IN PG
9
PRF1 0_0603_5%
PCF5
10U_0603_25V6M
0.1U_0402_25V6
3 1 BST_1VALW 1 2 BST_1VALW_R1 2 PLF1
2200P_0402_50V7K
IN BS
1
1UH_6.6A_20%_5X5X3_M
EMI@ PCF3
@EMI@ PCF4
PCF6
LDO_3V LX_1VALW
4
IN LX
6
0.1U_0402_25V7K
1 2
+1.0VALWP
2
5 19
13.7K_0402_1%
330P_0402_50V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
IN LX
1
PRF4
1
PRF3 7 20
PCF7
PCF8
PCF1
PCF9
PCF10
PCF11
PCF17
PCF16
GND LX
0_0402_5%
8 14 FB_1VALW Rup
2
GND FB
2
2
ILMT_1VALW 18 17 LDO_3V
GND VCC
1
1
EN_1VALW 11 10 @ @
EN NC
@ PRF5 PCF13 FB = 0.6V
1
ILMT_1VALW 13 12 2.2U_0402_6.3V6M
2
ILMT NC PRF6
0_0402_5%
15 16
+3VALW Rdown
2
BYP NC 20K_0402_1%
21
Ipeak=9.5A
2
PAD Imax=6.65A
SY8288RAC_QFN20_3X3 Pin 7 BYP is for CS.
1
The current limit is set to 6A, 8A or 12A when this pin Common NB can delete +3VALW and PC15
PCF14
is pull low, floating or pull high 1U_0201_6.3V6M
2
+3VALW =0.6*(1+(13.7/20))
Vout=1.011V
2 2
2
@ PRF7
10K_0402_1%
1
PRF8
EN_1VALW 1 2
+1.8VALW_PG <40>
0_0402_5%
1
PRF9
0.22U_0402_10V6K
2
1M_0402_1%
@ PCF15
2
3 3
4 4

VCCP
A B C D E
A B C D E
+3VALW
2
+5VALW
@ PJ1801
2
JUMP_43X39
@ PJ1802
1
JUMP_43X39
VIN_1.8VALW +1.8VALWP
1 2
+1.8VALW_PRIM
1
1 2
1
1 VIN_1.8VALW PC1801
1
1U_0402_6.3V6K
2
1
PC1804
4.7U_0402_6.3V6M
2
PU1801
G9661MF11U_SO8
4 5
PR1801 3 VPP NC 6
SPOK_3V 1 2 EN_1.8VALW 2 VIN VO 7 +1.8VALWP
GND
<29,37> SPOK_3V VEN ADJ
1 8
0.01U_0402_25V7K
POK GND
PC1803
0_0402_5%
1
PR1804
9
@ 12.7K_0402_1%
PC1802
Rup
2
PR1802 0.1U_0402_16V7K
1
1M_0402_1% FB_1.8VS
2
+3VALW PC1805
22U_0603_6.3V6M
2
1
2
PR1803
PR1805 10K_0402_1%
10K_0402_1%
Rdown
2
1
<39> +1.8VALW_PG +1.8VALW_PG
Vout=0.8V* (1+(12.7/10)) = 1.816V
2 2
3 3
4 4

SY8032
A B C D E
1 2 3 4 5
Module model information

Close IC
PRZ1 and PRZ22 are for debug only. RT3602AE_U22_RU42_colay_V1A.mdd for IC portion
VCCSSA_SENSE and VSSSA_SENSE need other resistor at HW side.
RT3602AE_U22_RU42_colay_V1B.mdd for SW portion
RT3602_VREF Vref=0.6V +VCC_SA PRZ1 PRZ8 PRZ10
100_0402_1% 10K_0402_1% 71.5K_0402_1% PCZ3
1 2 VCCSA_SENSE_R 1 2 1 2 0.1U_0402_25V6
1
2.15K_0402_1%
28K_0402_1%
2.15K_0402_1%
PRZ15
1 2 1 2
2
1
1
<14> VCCSA_SENSE
1 2 <42> ISENSE1N_SA ISENSE1P_SA_R1 <42>
@ PCZ200 PCZ5 390P_0402_50V7K PCZ6 68P_0402_50V8J
PRZ2
PRZ3
PRZ4
0_0402_5% 0.1U_0402_25V6
2
A @ PCZ1 @ PRZ16 A
FB_SA FB_SA
0.1U_0402_10V6K 10K_0402_1% @ PCZ4
2
1
1 2 1 2 0.47U_0402_25V6K
@ PCZ203 1 2
1
1
0.1U_0402_25V6
10K_0402_1%
10K_0402_1%
10K_0402_1%
0.47U_0402_6.3V6K
Close IC RT3602_VREF
PRZ6
PRZ11
PCZ193
PRZ94
1
1 2 1 2
PRZ5
1 2
<14> VSSSA_SENSE PRZ13 PRZ14
2
2
RT3602_SET1
2
1
PRZ22 44.2K_0402_1% 0_0402_5%
RT3602_SET2 1 0_0402_5%
2 @ PCZ199
RT3602_SET3
0.1U_0402_25V6
Close IC
RT3602_VREF 3.9_0402_1%
2
1
100_0402_1%
PRZ24
VR_PSYS
PRZ95
PRZ23 +3VS
1
<16> VSSSENSE 1 2 100K_0402_1%

1K_0402_1%
665_0402_1%
665_0402_1%
10K_0402_1%
1 2
Close CORE1 choke
PRZ18
PRZ19
PRZ20
2
PRZ17
0_0402_5% PRZ21
@ PRZ107 PHZ1 PRZ26 1 2
VR_PWRGD <29> EN
2
0_0402_5% 100K_0402_1%_B25/50 4250K 38.3K_0402_1%

PRZ25 High: > 0.7V
@ PCZ7 1 2PHZ1_R1 1 2 PHZ1_R 1 2 U22@ PRZ35 100_0402_1%
0.1U_0402_25V6
RGND_MAIN 6.04K_0402_1% 1 2 VR_ON
Low: < 0.3V
<29,32>
2
RT3602_VREF
1
1
2K_0402_1%
2K_0402_1%
16.9K_0402_1%
+1.0V_VCCST
IMON_SA
PRZ29
PRZ30
1 2 IMON_CORE_R 1 2 0_0402_5%
RT3602_EN
PRZ28
VSEN_CORE
RGND_MAIN
FB_SA
PRZ33
COMP_SA
RGND_SA
VR_PSYS
28.7K_0402_1% @ PCZ9 PRZ35 U42@ @ PCZ206
2
1
@ PCZ204 0.1U_0402_10V6K 6.49K_0402_1% @ PCZ201 0.1U_0402_25V6
PCZ194
110_0402_1%
0.1U_0402_25V6
1
1
0.1U_0402_25V6 @ PCZ207 1 2 0.1U_0402_25V6 1 2
75_0402_1%
100_0402_1%
45.3_0402_1%
1
U42@ PRZ45 47P_0402_50V8J @
PRZ37
CORE1_LX <42> CORE1_LX 1
2
@ PCZ8 @ PRZ40 28.7K_0402_1% 2 1 2
2
0.1U_0402_10V6K 10K_0402_1% 1M_0402_1% PRZ108 PUZ1
49
48
47
46
45
44
43
42
41
40
39
38
37
PRZ36
PRZ38
PRZ39
2
1 2 1 2 @ RT3602AJGQW_WQFN48_6X6 @
Close IC
2
PRZ43 U22@ PRZ45
GND
RGND_MAIN
VSEN_MAIN
EN
PSYS
FB_SA
RGND_SA
COMP_SA
ISENN_SA
ISENP_SA
IMON_SA
VR_READY
VREF06/PSET
10K_0402_1% 26.1K_0402_1% SOC_SVID_CLK <16>
VSEN_CORE 1 2 1 2 SOC_SVID_ALERT#_R <16>
+VCC_CORE PRZ41
IMON_CORE SOC_SVID_DAT <16>
100_0402_1% PCZ12 82P_0402_50V8J 1 36 PWM_SA <42>
1 2 1 2 1 2 2 RT3602_SET1 IMON_MAIN PWM_SA 35 VR_HOT# <29>
FB_CORE SET1 DRVEN DRVEN_CPU <42>
3 34 1 2
PRZ47 COMP_CORE FB_MAIN VCLK RT3602_VREF
<42> ISENSE1N_CORE PCZ13 4 33 PRZ98 49.9_0402_1%
1 2 PCZ11 330P_0402_50V8J 0.1U_0402_25V6 5 RT3602_SET2 COMP_MAIN ALERT# 32 PRZ99 1 210_0402_1% PRZ48
<16> VCCSENSE
1 2 Ra 6 RT3602_SET3 SET2 VDIO 31 1
PRZ100 2
100_0402_1% 30K_0402_1% PRZ49 5.76k_0402_1%
SET3 VR_HOT# IMON_GT
1
U42@ PRZ106 7 30 1 2 1 2
0_0402_5% @ PCZ196 1 2 1 2 ISEN1N_MAIN 8 ISEN1N_MAIN IMON_AUXI 29 @ PCZ15 0.47U_0402_25V6K
Close IC
U42@ 0_0402_5% 9 ISEN2N_MAIN ISENP_AUXI 28 1 2
0.1U_0402_25V6
2
PCZ16 0.1U_0402_25V6 10 ISEN2P_MAIN ISENN_AUXI 27 VSEN_GT

<42> ISENSE2N_CORE TSEN_CORE 11 ISEN1P_MAIN VSEN_AUXI COMP_GT
26 ISENSE1P_GT_R1 <42>
RT3602_VIN 12 TSEN_MAIN COMP_AUXI 25 PRZ50 0_0402_5%
Rb VIN RGND_AUXI ISENSE1N_GT <42>
PWM1_MAIN
PWM2_MAIN
DRVEN_SET
B 1 2 B
TSEN_AUXI
PWM_AUXI
+5VALW VSEN_GT
RGND_AUXI
U22@ PRZ105 10K_0402_1% 1 2 1 2 VCCGT_SENSE <16>
FB_AUXI
0.22U_0402_25V6K
1
1
PCZ18
2.2_0805_1%
<42> ISENSE2P_CORE_R1
0.1U_0402_25V6 PRZ54 PRZ56 PRZ59
PRZ41 and PRZ21 are for debug only.
VCC
27K_0402_1% 10K_0402_1% 100_0402_1% +VCC_GT
NC
NC
NC
NC
NC
Rc
PRZ53
PCZ19
2
VCCCORE_SENSE and VSSCORE_SENSE need other resistor +5VALW
1 2 1 2 1 2 1 2
U22@ PRZ104 10K_0402_1%
at HW side.
13
14
15
16
17
DRVEN_SET 18
19
20
21
22
TSEN_GT 23
FB_GT 24
1
<42> ISENSE1P_CORE_R1
1 2 1 2 @ PCZ198
Ra Rb/Rc RT3602_VREF PRZ51 PRZ52 0.1U_0402_25V6
RT3602_VCC
2
110K_0402_1% 1.65K_0402_1% PCZ20 82P_0402_50V8J PCZ21
TSEN_CORE_R 1 2 1 2 270P_0402_50V7K
+19VB_CPU
PHZ2
U22 N/A Stuff
1
1 2 1 2 1 2
15K_0402_1%
@ PCZ202
1
FB_GT
@ PRZ61 @ PCZ22 0.1U_0402_25V6
10K_0402_1%
100K_0402_1%_B25/50 4250K
2
10K_0402_1% 0.1U_0402_10V6K
U42 Stuff N/A
PRZ64
<42>
PWM_GT
Close CORE1 MOSFET
PRZ63
+5VALW
<42>
<42>
PRZ65
Close IC
PWM_CORE2
PWM_CORE1
2
8.2_0402_1%
1 2
PRZ93
1
1
1K_0402_1%
6.04K_0402_1%
U22@ PRZ68 1 2
U42@ PRZ68
VSSGT_SENSE <16>
11K_0402_1%
PRZ67
1
0_0402_5%
1
+5VALW PCZ23
2
1
4.7U_0402_6.3V6M PRZ66
TSEN_CORE_R TSEN_GT_R
2
110K_0402_1% @ PCZ197 PRZ60
1
100K_0402_1%_B25/50 4250K
0.1U_0402_25V6 100_0402_1%
2
1
2
1
@ PRZ72
2K_0402_1%
6.98K_0402_1%
U42@ PRZ71
10K_0402_5%
U22@ PRZ71
PRZ70
1
3.48K_0402_1%
PHZ3
2
DRVEN_SET PRZ69
2
1.65K_0402_1%
1
2
1
PRZ75
15K_0402_1%
10K_0402_1%
PRZ74
10K_0402_5%
Close GT MOSFET
PRZ73
TSEN_GT_R
PRZ59 and PRZ60 are for debug only.
2
2
VCCGT_SENSE and VSSGT_SENSE need other resistor

at HW side.
C
Set DRVEN output function at PS4. Set to 5V DRVEN C
is floating, and set to GND DRVEN is low at PS4.
D D

CPU_CORE
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1A
1 2 3 4 5
5 4 3 2 1
+19VB_CPU
@
PJZ1 +19VB
1 2 +19VB_CPU
1 2
PRZ76
33U_25V_M
33U_25V_M
10U_0603_25V6M
10U_0603_25V6M
JUMP_43X118
2200P_0402_50V7K
2.2_0603_5%
PCZ29
PCZ30
PCZ31
PCZ32
CORE1_BST CORE1_BST_R 1 1
0.1U_0402_25V6
D D
1 2
1
+ + U42@ PRZ77
PCZ26
PCZ37
PCZ34
PCZ195
10U_0603_25V6M
10U_0603_25V6M
1
2200P_0402_50V7K
PQZ1 2.2_0603_5%
@EMI@ PCZ36
EMI@ PCZ33
CORE2_BST CORE2_BST_R
0.1U_0402_25V6
PCZ28 1 2
EMIU42@
@EMIU42@
PUZ2
1
2@ 2
AON6380_DFN5X6-8-5
0.1U_0402_25V6
1
U42@
CORE1_UG CORE1_UG_R
U42@
U42@
4 3 1 2 4 PCZ35
PUZ3
2
BOOT UGATE PRZ78 U42@ 0.1U_0402_25V6
2
5 2 0_0603_5%
<41> PWM_CORE1 PWM PHASE 4 3 CORE2_UG 1 2 CORE2_UG_R4
1 6 BOOT UGATE U42@ PRZ79 U42@
<41> DRVEN_CPU Rdc=0.9mohm
3
2
1
+5VALW EN PGND +VCC_CORE 5 2 CORE2_LX 0_0603_5% PQZ3
1 VCC_CORE1 PLZ1 <41> PWM_CORE2 PWM PHASE
PRZ80 2 8 7 AON6380_DFN5X6-8-5
VCC LGATE 9 CORE1_LX 1 4 +5VALW DRVEN_CPU 1 6
Rdc=0.9 mohm
3
2
1
5.1_0402_1% GND EN PGND +VCC_CORE
ISENSE1P_CORE 2 3 1 2 VCC_CORE2 8 7 U42@ PLZ2
RT9610CGQW_WDFN8_2X2 VCC LGATE
1
PQZ2 9 1 4
@EMI@ PRZ82
4.7_1206_5%
GND
1
PCZ40 U42@ PRZ81
CORE1_LX <41> 0.15UH_NA__35A_20% 5.1_0402_1% ISENSE2P_CORE 2 3
1U_0402_10V6K
2
RT9610CGQW_WDFN8_2X2
1
AON6314_N_DFN56-8-5
U42@
@EMI@ PRZ84
4.7_1206_5%
5
1
Can be closed to choke PCZ41
0.15UH_NA__35A_20%
1U_0402_10V6K
1CORE1_SNUB 2
2
CORE1_LG 4 PCZ42
0.1U_0402_25V6
1 2 ISENSE1P_CORE_R1 2 1 2
1CORE2_SNUB 2
CORE2_LG 4 PRZ87 PRZ103 U42@ PCZ43
PRZ85 PRZ102 @ PRZ88 750_0603_1% 750_0603_1% 0.1U_0402_25V6
3
2
1
750_0603_1% 750_0603_1% 3.57K_0402_1% 1 2 ISENSE2P_CORE_R
1 2 1 2
1 2 U42@
@EMI@ PCZ44
PQZ4 U42@ U42@ @ PRZ90
3
2
1
680P_0603_50V7K
AON6314_N_DFN56-8-5 3.57K_0402_1%
1 2
@EMI@ PCZ45
2
680P_0603_50V7K
Can be closed to choke
2
ISENSE1N_CORE <41>
ISENSE2N_CORE <41>
ISENSE1P_CORE_R1 <41>
ISENSE2P_CORE_R1 <41>
C C
+19VB_CPU VCC_CORE
FSW=450kHz VCC_GT VCC_SA
Choke=0.15uH FSW=450kHz FSW=600kHz
DCR=0.9mohm +/- 5% Choke=0.15uH DCR=6.2 mohm +/- 5%
PRG2 DCR=0.9 mohm +/- 5%
PCG5
PCG6
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
2.2_0603_5%
PCG3
PCG4
GT_BST GT_BST_R U22
0.1U_0402_25V6
1 2
U22
1
LL=2.4 mohm U22 LL=10.3 mohm
1
PCG2 LL=3.1 mohm TDC=4A
EMI@
@EMI@
PUG1 TDC=21A
2
2
0.1U_0402_25V6 TDC=18A ICCMAX=4.5A
2
GT_UG ICCMAX=32A
4
BOOT UGATE
3
OCP=40A ICCMAX=31A OCP=9.5A
5 2 GT_LX PQG1 OCP=39A
<41> PWM_GT PWM PHASE
2
AON6962_DFN5X6D-8-7
+5VALW DRVEN_CPU 1 6 U42 U42
Rdc=0.9 mohm
D1
G1
VCC_GT
EN PGND
PLG1
+VCC_GT
LL=2.4 mohm U42 LL=10.3 mohm
1 PRG1 2 8 7
VCC LGATE 9 7 GT_LX 1 4 TDC=42A LL=3.1 mohm TDC=
GND D2/S1
5.1_0402_1%
ISENSE1P_GT 2 3 ISENSE1N_GT ICCMAX=64A TDC=12A ICCMAX=6A
RT9610CGQW_WDFN8_2X2 ICCMAX=31A OCP=9.5A
1
OCP=70A
@EMI@ PRG4
G2
S2
S2
S2
4.7_1206_5%
1
PCG1
0.15UH_NA__35A_20% OCP=39A
1U_0402_10V6K
2
PRG6 PRG9 PCG8

1K_0603_1% 1K_0603_1% 0.1U_0402_25V6
1 2 ISENSE1P_GT_R 1 2 1 2
1GT_SNUB
PRG7 PRG8
2.61K_0402_1% 10K_0402_1%
GT_LG 1 2 1 2
@EMI@ PCG9
AVGT1_R
680P_0603_50V7K
2
1 2
Close GT choke
PHG1
10K_0402_1%_B25/50 3370K
B ISENSE1N_GT <41> B
ISENSE1P_GT_R1 <41>
+19VB_CPU
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
PRA2
@EMI@ PCA6
PCA2
0.1U_0402_25V6
2.2_0603_5%
SA_BST SA_BST_R
1
1 2
PCA4
PCA5
1
EMI@
2
PCA3
PUA1
0.1U_0402_25V6
2
4 3 SA_UG
BOOT UGATE
5 2 SA_LX
<41> PWM_SA PWM PHASE
1
+5VALW DRVEN_CPU 1 6 PQA1

Rdc=6.2 mohm
G1
D1
D1
D1
EN PGND AONH36334_DFN3X3A8-10 +VCC_SA

1 2 VCC_SA 8 7 PLA1
VCC LGATE 9 9 10 1 4
PRA1 5.1_0402_1% GND D2/S1 D1
ISENSE1P_SA 2 3
RT9610CGQW_WDFN8_2X2
1
@EMI@ PRA4
G2
S2
S2
S2
4.7_1206_5%
1
PCA1
0.47UH_NA__12.2A_20%
1U_0402_10V6K
2
SA_LG
2
PCA7
0.1U_0402_25V6
ISENSE1P_SA_R
1 SA_SNUB
1 2 1 2 1 2
PRA6 PRA9 PRA7 PRA8

A 750_0603_1% 750_0603_1% 866_0402_1% 1K_0402_1% A
1 2 1 2
@EMI@ PCA8
AVCCSA_R
680P_0402_50V7K
Close SA choke
2
1 2
PHA1
1K_0402_5%_TSM0B102J3652RE ISENSE1N_SA <41>
ISENSE1P_SA_R1 <41>
3650K
Vinafix.com Security Classification Compal Secret Data Compal Electronics, Inc.

CPU Power stage
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Re v
EH5AW M/B LA-G521P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2 1
1
1A
Rev
47
of
43
Sheet
EH5AW M/B LA-G521P
E
E
Monday, May 13, 2019
Power Train
Document Number
+VCC_SA
PC9079
1U_0201_4V6M
+VCC_SA
1 2
PC9078
Date:
Title
Size
PC9052 1U_0201_4V6M
22U_0603_6.3V6M
C
1 2
1 2 PC9077
PC9051 1U_0201_4V6M
22U_0603_6.3V6M
22uF_0603*7
22uF_0603*1
1 2
1 2 PC9076
1uF_0201*7
PC9050 1U_0201_4V6M
@
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
22U_0603_6.3V6M
1 2
1 2 PC9075
2018/11/04
PC9049 1U_0201_4V6M
unpop:
22U_0603_6.3V6M
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 2
1 2 PC9074
pop:
PC9022 PC9048 1U_0201_4V6M

22U_0603_6.3V6M 22U_0603_6.3V6M
1 2
SA
1 2 1 2 PC9073
PC9021 PC9047 1U_0201_4V6M
22U_0603_6.3V6M 22U_0603_6.3V6M
1 2
Deciphered Date
1 2 1 2 Compal Secret Data
D
D
0.47uF*4
22uF*36
22uF *8
220uF*1
unpop:
1uF*9
1uF*1
2018/10/10
+VCC_GT
+VCC_GT
PC9020 PC9046 PC9072 PC9095 @ PC9109 PC9129 PC9153

@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 0.47U_0201_4V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9019 PC9045 PC9071 PC9094 @ PC9108 PC9128 PC9152
Issued Date
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9018 PC9044 PC9070 PC9093 @ PC9107 PC9127 PC9151
@

1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9017 PC9043 PC9069 PC9092 @ PC9106 PC9126 PC9150
@

1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9016 PC9042 PC9063 PC9091 PC9125
@
C
C
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
+VCC_GTX_GT
1 2 1 2 1 2 1 2 1 2
PC9015 PC9041 PC9062 PC9090 PC9124
@

1 2 1 2 1 2 1 2 1 2
+VCC_GTX_VCORE
PC9014 PC9040 PC9061 PC9089 PC9123
@
+VCC_GT_VCORE
1 2 1 2 1 2 1 2 1 2
PC9013 PC9039 PC9060 @ PC9088 PC9122
@
1 2 1 2 1 2 1 2 1 2
SOLDER_PREFORMS_0402
PC9012 PC9038 PC9059 PC9087 PC9121
1 2 1 2 1 2 1 2 1 2
2
PC9011 PC9037 PC9058 PC9086 PC9120
PR9003
PR9005
PR9004
PR9001
PR9002
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 0.47U_0201_4V6M
2
+
1
1 2 1 2 1 2 1 2 1 2
220U_D2 SX_2VY_R9M
1
U23FD@
U23FD@
SKU22@
PC9105
RU42@
RU42@
1
1
SGA20221D40
VCORE Output Capacitor:

+VCC_CORE
+VCC_GT
+VCC_CORE
B
B
22uF_0603*29
1uF_0201*35
PC9001 PC9036 PC9068 PC9099 PC9104 PC9119 PC9139 PC9149 PC9158
@
+VCC_CORE
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
2017/07/03
22_0603*7
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
220uF *3
PC9010 PC9035 PC9067 PC9098 PC9103 PC9118 PC9138 PC9148 PC9157
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9009 PC9034 PC9066 PC9080 PC9117 PC9137 PC9147
UNPOP
@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
+
1
U22
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9008 PC9033 PC9065 PC9097 PC9116 PC9136 PC9146
220U_D2 SX_2VY_R9M
@
@
U42@ PC9102
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9007 PC9032 PC9064 PC9115 PC9135 PC9145
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
+
1
2
+VCC_GT_VCORE
1 2 1 2 1 2 1 2 1 2 1 2
VCORE Output Capacitor:

PC9006 PC9031 PC9057 PC9114 PC9134 PC9144
220U_D2 SX_2VY_R9M
U42@ PC9100
1 2 1 2 1 2 U42@ PC9084 1 2 1 2 1 2
PC9005 PC9030 PC9056 22U_0603_6.3V6M PC9113 PC9133 PC9143
Vinafix.com
1 2
1 2 1 2 1 2 U42@ PC9083 1 2 1 2 1 2
1 2
1 2 1 2 1 2 U42@ PC9082 1 2 1 2 1 2
@
A
A
1 2
1 2 1 2 1 2 U42@ PC9081 1 2 1 2 1 2
22uF_0603*35
+VCC_GTX_VCORE
@ PC9002 PC9027 PC9053 22U_0603_6.3V6M PC9110 PC9130 PC9140
1uF_0201*35
1 2
2017/07/03
1 2 1 2 1 2 PC9156 1 2 1 2 1 2
22_0603*7
1U_0201_4V6M
220uF *2
1 2
PC9155 U42@ PC9096
1U_0201_4V6M 22U_0603_6.3V6M
UNPOP
1 2 1 2
PC9154 U42@ PC9085
U42
1U_0201_4V6M 22U_0603_6.3V6M
1 2 1 2

Compal La-H782p R1a

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A B C D E

EH7L1/EH5L1 MB Schematic Document

Security Classification Compal Secret Data Compal Electronics, Inc.

HDMI Conn. eDP Interleaved Memory

DDR4-ON BOARD 4G 8Gbx16

(KBL-U_23E Fuse Down)

(SATA2) Premium-U PCIE3.0

SATA3.0 SATA3.0 USBx8 48MHz

RJ45 conn. LPC/eSPI BUS

page 32 LSH784P ODD/B

Board ID Table for AD channel

Memory Mode SDP@ / DDP@

43 level BOM table

431AI4BOL04 SMT MB AH782 EH5L1 I370U22 HDMI U22@/CMC@/LPC@/NRD@/NBYOC@/255@/MP@/MEM@/NMSB@/NTPM@/UMADAZ1A@/X76M@/X4EUMA@/UMA@/15@/EH5L1@/SR3TK@

431AI4BOL54 SMT MB AH782 EH7L1 I370U23E HDMI U22@/CMC@/LPC@/RD@/NBYOC@/255@/MP@/MEM@/NMSB@/NTPM@/ODD@/UMADAZ1A@/X76M@/X4EUMA@/UMA@/EH7L1@/SR3N6@

431AI4BOL55 SMT MB AH782 EH7L1 I370U22 HDMI U22@/CMC@/LPC@/RD@/NBYOC@/255@/MP@/MEM@/NMSB@/NTPM@/ODD@/UMADAZ1A@/X76M@/X4EUMA@/UMA@/EH7L1@/SR3TK@

Security Classification Compal Secret Data Compal Electronics, Inc.

DRVEN_CPU RT9610CGQW PR9001 (For U42) +VCC_GTX_VCORE

PR9002 (For U42)

+1.2VP (PJM3) +1.2V_VDDQ (JPC1,JPC2) +1.2V_VDDQ_CPU (RC208) +1.2V_VDDQC (UY1) +HDMI_5V_OUT

SUSP# EM5209VF R-Short

Vinafix.com Security Classification

SOC_SMBDATA 2N7002DW SOC_SMBDATA_1

77 EC_SMB_CK1 100 ohm EC_SMB_CK1-1 4

KBC SCL2 79 SOC_SML1CLK

SOC_SML1CLK VGA 0x9E

Security Classification Compal Secret Data Compal Electronics, Inc.

Display Port B/C Detected B50 DDI2_TXN[2]

RC2 1 2 1K_0402_5% H_THERMTRIP#

1 2 H_PROCHOT#_R C65 PECI

A65 THERMTRIP# B61 CPU_XDP_TCK0

RC15 2 CMC@ 1 51_0402_5% SOC_XDP_TDO

RC35 2 CMC@ 1 51_0402_5% CPU_XDP_TCK0

561280 4.18 DDR4 Mixed SODIMM and Memory Down

Intel DOC: 549352

SOC_SMBCLK_1 RC222 1 2 2.2K_0402_5%

SOC_SML0CLK RC49 1 2 499_0402_1%

1 SOC_SML0DATA RC50 1 2 499_0402_1% 1

SOC_SML1CLK RC245 1 2 2.2K_0402_5%

RCIN# AW13 AW9 CLKOUT_LPC0 RC45 2 LPC@ 1 22_0402_5% PM_CLKRUN# 1 2 10K_0402_5%

RCIN# RC277 1 2 10K_0402_5%

HDA for AUDIO HDA_SYNC

SPKR / GPP_B14 (Internal Pull Down): SKL_ULT

1 2 EC_VCCST_PG Rev_0.53 Cannonlake U use 38.4M 30 ohm ESR

RC104 1 2 1K_0402_5% WAKE#

#543016 PDG2.0 P.599 CC164

DVT 02/24 +3VALW_1.8VALW_PGPPD

Functional Strap Definitions +3VALW_1.8VALW_PGPPD +3VALW_1.8VALW_PGPPD

RAM_ID3 RAM_ID2 *RAM_ID1 *RAM_ID0 PartNumber - Description

Security Classification Compal Secret Data Compal Electronics, Inc.

USB_OC1# NA DEVSLP[2:0] Implementation

+1.0VALW_PRIM TO +1.0V_VCCSTU / +1.0VCCST

Imax : 3.44 A JUMP_43X79 1 RC208 1 @ 2 0_0402_5% CC47 1 2 10U_0603_6.3V6M

EN_VCCSTG_VCCPLL_OC MSB@2 0_0402_5% 1

1 AOZ1334DI-02_DFN8-7_3X3 +1.0V_VCCSFR PSC Side

4 #543016 PDG2.0 P.750 #543016 PDG2.0 P.750 4

+VCCIO : 4x 1uF 0402 +1.35V_VDDQ_CPU :

VCCMPHYAON_1P0 AA1 +3VALW_PGPPC_E +3VALW_PRIM

1 CC86 2 1 0_0402_5% 2 @ 1 RC169

TPS22961DNYR_WSON8 2 +1.0VALW_CLK4_F100OC +1.0VALW_PRIM

@ CC80 1U_0201_6.3V6M JRTC1

RC176 1 @ 2 0_0603_5% CC122 1 2 1U_0201_6.3V6M

RAM_ID3 RAM_ID2 RAM_ID1 RAM_ID0 PartNumber - Description