Compal LA-H791P EH7LW - EH5LW - FH5TW - EH7LC - EH5LC Rev 2.0 Acer EX215-51K

A B C D E
1 1
2
Compal Confidential 2
EH7LW/EH5LW/FH5TW/EH7LC/EH5LC
DIS MB Schematic Document
LA-H791P
3 3
Rev: 2.0
2019.05.29
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/12/27 Deciphered Date 2019/12/27 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH7LW M/B LA-H791P
Date: Thursday, June 06, 2019 Sheet 1 of 57
A B C D E
A B C D E
HDMI Conn. eDP Interleaved Memory
DDR4-ON BOARD 4G 8Gbx16
page 19
page 29 page 28 Memory BUS
1
DDI2 Dual Channel 1
HDMI x 4 lanes
260pin DDR4-SO-DIMM X1
eDP 1.2V DDR4 2400
DDI page 20
Intel Whiskey lake U USB 3.0 USB 2.0 CMOS

Intel Comet lake U conn x1 conn x2
USB2 port2 (MB) Camera
USB3 port 1
Nvidia N17S-G0/G2 USB2 port 1 USB2 port4(SUB) USB2 port 7
with GDDR5 x2 Processor
page 21~27
Card Reader
page 31
PCIe 3.0 x 4 RTS5140
8GT/s SATA Gen 3 PCIE 3.0 x4 Reserved
2 6.0 Gb/s 8GT/s Flexible IO 2
port 1-4 Port 9-12 Base-U PCIE 3.0x2 (CML)
(SATA2) page 35 page 35 page 28 USB2 port 6(SUB)
SATA Gen 3 SATA Gen 1
Cannon Lake PCH-LP USBx8 48MHz
NGFF PCIe 1.0 PCIe 1.0 6.0 Gb/s 1.5. Gb/s Finger
WLAN 2.5GT/s 2.5GT/s port 0 port 1 Printer
support CNVi port 6 port 5 (SATA0) (SATA1A) 3.3V 24MHz USB2 port 5
HD Audio
USB2 port 10 page 31 46x24 mm Touch
LAN(GbE) SATA HDD SATA ODD 15W Screen
Realtek 8111H Conn. Conn. 1528pin BGA HDA Codec
WHL-U 4+2 USB2 port 3
page 30
page 07~18 SPI ALC255page 32 page 28
WHL-U 2+2
RJ45 conn. LPC/eSPI BUS

3
SPI ROM 3
page 33 CLK=24MHz 128Mb page 9
ENE
KB9022 Int. Speaker Int. DMIC UAJ
page 36
on Camera
Fan Controlpage 39
Sub Board page 32 page 28 page 35
Touch Pad
LS-H802P LS-H783P PS2 (from EC) / I2C (from SOC)
RTC CKT. page 15 HDD/B LID/B Int.KBD USB2 port 8 (FP)
page 33 page 38
Power On/Off CKT.

page 37 page 37 page 37
LS-H781P LS-H784P
IO/B ODD/B
4 4
page 38 page 33
DC/DC Interface CKT.
page 40
2018/12/27 2019/12/27 Title
Issued Date Deciphered Date Block Diagrams
Power Circuit DC/DC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
page 41~54 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
A B C D E
A B C D E
Board ID Table for AD channel

Vcc 3.3V +/- 5%
Ra 100K +/- 1% Power State
Board ID Rb V BID min V BID typ V BID max EC AD3 PCB Revision SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
0 0 0 V 0 V 0.300 V 0x00 - 0x13 0.1(EVT)
1 12K +/- 1% 0.347 V 0.345 V 0.360 V 0x14 - 0x1E 0.2(DVT) S0 (Full ON) HIGH HIGH HIGH ON ON ON ON
2 15K +/- 1% 0.423 V 0.430 V 0.438 V 0x1F - 0x25 0.3(PVT) S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
1
3 20K +/- 1% 0.541 V 0.550 V 0.559 V 0x26 - 0x30 1.0(PreMP) 1
4 27K +/- 1% 0.691 V 0.702 V 0.713 V 0x31 - 0x3A S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
5 33K +/- 1% 0.807 V 0.819 V 0.831 V 0x3B - 0x45 S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
6 43K +/- 1% 0.978 V 0.992 V 1.006 V 0x46 - 0x54
7 56K +/- 1% 1.169 V 1.185 V 1.200 V 0x55 - 0x64
Voltage Rails
Power Plane Description S0 S3 S4/S5
+19V_VIN Adapter power supply N/A N/A N/A
+12.6V_BATT Battery power supply N/A N/A N/A
BOM Structure Table
+19VB AC or battery power rail for power circuit. N/A N/A N/A
+VCC_CORE Processor IA Cores Power Rail ON OFF OFF
BOM Option Table BOM Option Table
+VCC_GT Processor Graphics Power Rails ON OFF OFF
Item BOM Structure Item BOM Structure +VCC_SA ON OFF OFF
System Agent power rail
Unpop @ MB Stage EVT@/DVT@/PVT@/MP@ +0.6VS_VTT DDR +0.6VS power rail for DDR terminator . ON OFF OFF
Connector CONN@ G Sensor GSEN@ +1.05VALW_PRIM +1.05V Always power rail ON ON ON*1
For over 3 cell battery 3S@ +1.05V_VCCSTU Sustain voltage for processor in Standby modes ON ON OFF
CODEC 255@/256@ NOX76@/X76DSAM@/ +VCCIO CPU IO power rail ON OFF OFF
MD BOM Select
2 EC Mode Select LPC@ / ESPI@ X76DMIC@/X76DHYN@/ +1.05VS_VCCSTG +1.0VALW_PRIM Gated version of VCCST ON OFF OFF
2
For Intel CMC CMC@ X76VSAM@/X76VMIC@/ +1.2V_VDDQ DDR4 +1.2V Power Rail ON ON OFF
VRAM BOM Select X76VHYN@/
CNVi /BT PCM Select CNVI@/PCM@ +1.8VALW_PRIM +1.8V Always power rail ON ON ON*1
EMI requirement EMI@ / @EMI@ Memory related SPD@/DDP@/MEM@ +1.8VS System +1.8V power rail ON OFF OFF
ESD requirement ESD@ / @ESD@ CPU C10 support C10@ +3VLP +19VB to +3VLP power rail for suspend power ON ON ON
RF requirement @RF@ BOM select 15DIS@/15@/ +3VALW System +3VALW always on power rail ON ON ON*1
TPM TPM@ VGA chip G0@/G2@ +3VS System +3V power rail ON OFF OFF
Finger Print FP@/FPEMC@
+5VALW +5V Always power rail ON ON ON
Finger print power FP3V@/FP5V@ +5VS System +5V power rail ON OFF OFF
UMA or DGPU UMA@/VGA@ +RTCVCC RTC Battery Power ON ON ON
CPU Select WHL@/CML@ +1.0VSDGPU +1.0VS power rail for N17S ON*2 OFF OFF
SATA/ODD select RD@/NRD@/ODD@ +1.35VSDGPU +1.35VS power rail for GPU ON*2 OFF OFF
USB charger CHG@ +1.8VSDGPU_AON +1.8VS power rail for N17S(AON) ON*2 OFF OFF
+1.8VSDGPU_MAIN +1.8VS power rail for N17S(MAIN) ON*2 OFF OFF
+VGA_CORE Core power for discrete GPU ON*2 OFF OFF
3 3
Note : ON*1 means power plane is ON only when WOL enable and RTC wake at BIOS setting, otherwise it is OFF.
ON*2 power plane is ON when DGPU turn on
43 level BOM table

43 Level Description BOM Structure
431AHVBOL01 SMT MB AH791 EH7LW I37020U22 230 HDMI 8145U@/PCB@/MEM@/SPD@/X76DHYN@/VGA@/G0@/X76VHYN@/NC10@/CNVI@/NCHG@/FP@/3S@/LPC@/CMC@/GSEN@/RD@/ODD@/255@/BYOC@/TPM@/EVT@/
X4E@/15@/15DIS@/FP3V@
431AHVBOL02 SMT MB AH791 EH7LW I38130U42 250 HDMI 8265U@/PCB@/MEM@/SPD@/X76DHYN@/VGA@/G2@/X76VHYN@/NC10@/CNVI@/NCHG@/FP@/3S@/LPC@/CMC@/GSEN@/RD@/ODD@/255@/BYOC@/TPM@/EVT@/
X4E@/15@/15DIS@/FP3V@
431AHVBOL03 SMT MB AH791 EH7LW I38145U22 230 HDMI 8145U@/PCB@/WHL@/MEM@/SDP@/X76DHYN@/VGA@/G0@/X76VHYN@/NC10@/CNVI@/NCHG@/RD@/ODD@/3S@/LPC@/CMC@/255@/DVT@/X4E@/17@/
431AHVBOL04 SMT MB AH791 EH7LW I58265U42 230 HDMI 8265U@/PCB@/WHL@/MEM@/SDP@/X76DHYN@/VGA@/G0@/X76VHYN@/NC10@/CNVI@/NCHG@/RD@/ODD@/3S@/LPC@/CMC@/255@/DVT@/X4E@/17@/
431AHVBOL05 SMT MB AH791 EH7LW I38145U22 230V8 HDMI 8145U@/PCB@/WHL@/MEM@/SDP@/X76DHYN@/VGA@/G0@/X76VSAM@/NC10@/CNVI@/NCHG@/RD@/ODD@/3S@/LPC@/CMC@/255@/DVT@/X4E@/17@/
431AHVBOL06 SMT MB AH791 EH7LW I58265U42 230V8 HDMI 8265U@/PCB@/WHL@/MEM@/SDP@/X76DHYN@/VGA@/G0@/X76VSAM@/NC10@/CNVI@/NCHG@/RD@/ODD@/3S@/LPC@/CMC@/255@/DVT@/X4E@/17@/
431AHVBOL51 SMT MB AH791 EH5LW I38145U22 230 HDMI 8145U@/PCB@/WHL@/MEM@/SDP@/X76DHYN@/VGA@/G0@/X76VHYN@/NC10@/CNVI@/NCHG@/NRD@/3S@/LPC@/CMC@/255@/DVT@/X4E@/15@/15DIS@/

4 4
431AHVBOL52 SMT MB AH791 EH5LW I58265U42 230 HDMI 8265U@/PCB@/WHL@/MEM@/SDP@/X76DHYN@/VGA@/G0@/X76VHYN@/NC10@/CNVI@/NCHG@/NRD@/3S@/LPC@/CMC@/255@/DVT@/X4E@/15@/15DIS@/
431AHVBOL53 SMT MB AH791 EH5LW I38145U22 230V8 HDMI 8145U@/PCB@/WHL@/MEM@/SDP@/X76DHYN@/VGA@/G0@/X76VSAM@/NC10@/CNVI@/NCHG@/NRD@/3S@/LPC@/CMC@/255@/DVT@/X4E@/15@/15DIS@/
431AHVBOL54 SMT MB AH791 EH5LW I58265U42 230V8 HDMI 8265U@/PCB@/WHL@/MEM@/SDP@/X76DHYN@/VGA@/G0@/X76VSAM@/NC10@/CNVI@/NCHG@/NRD@/3S@/LPC@/CMC@/255@/DVT@/X4E@/15@/15DIS@/

Notes List
A B C D E
A B C D E
DRVEN_CPU RT9610CGQW
(PUZ2) +VCC_CORE
RT9610CGQW
(PUZ3) U42@
RT9610CGQW
+VCC_GT
(PUG1)
R-Short +TS_PWR
RT9610CGQW (RX8)
(PUA1) +VCC_SA
ADAPTER AP2330W +HDMI_5V_OUT
1 SYSON JUMP R-0ohm (UY1) 1
+1.2VP (PJM3) +1.2V_VDDQ (RC464) +1.2V_VCCPLL_OC

RT8207PGQW R-Short +5VS_HDD
SM_PG_CTRL (PUM1) JUMP (RO3)
+0.6VSP (PJM4) +0.6VS_VTT
+19VB R-short
BATTERY (RO26) +5VS_ODD
JUMP SUSP# AOZ1331DI JUMP JUMP

5V_EN SY8288CRAC +5VALWP +5VALW +5VS_OUT +5VS +VDDA
(PJ501) (UQ1) (JPQ2) (JPA1)
(PU501)
CHG_EN SLGC55544CVTR R-Short
(US12) CHG@ +USB3_VCCA (RF1) +VCC_FAN1
CHARGER
(PU301) USB_EN SY6288C20AAC JUMP KBL_EN SY6288C20AAC
+USB3_VCCB (JPC10) NCHG@ +5VS_BL
(US21) (U1)
LDO JIO1
+3VLP (IO/B)
SOC_ENVDD SY6288C20AAC
(UX1) +LCDVDD
0 ohm PEX_VDD_EN SY8032ABC JUMP

(RS155) +3VALW_USB3RD (PU1101) VGA@ +1.05VSDGPUP (PJ1101) +1.05VS_1.0VSDGPU
3V_EN SY8286BRAC JUMP R-Short 0 ohm
(PU301) +3VALWP (PJ301) +3VALW (RC173) +3VALW_DSW (RM1)NBYOC@ +3VS_WLAN
JUMP R-Short
(JPC7) +3VALW_PRIM (RC198) +3VALW_HDA
2 SYSON G9661MF11UI R-Short R-Short 2
(PUM2) +2.5VP (RC154) +3VALW_SPI (RM9) +3VS_SSD_NGFF

LAN_PWR_EN SY6288C20AAC R-Short
(UL1)/R-Short +3V_LAN (RC178) +1.8VS_3VS_PGPPA
TP_PWR_EN SY6288C20AAC R-Short
+3V_PTP +3VS_TPM
(UK1) (RW2)
WLAN_ON SY6288C20AAC R-Short
(UM1) +3VS_WLAN (RA2) +3VS_DVDDIO
0 ohm R-Short
(RS10) +3VALW_CC (RA5) +3VS_DVDD
FP_PWR_EN SY6288C20AAC JEDP1
+FP_VCC
(UK6)FP@ (CAMERA)
0-ohm JMIC1
(RW1) TPM@ +3VALW_TPM (4DMIC)
SUSP# AOZ1331DI JUMP
+3VS_OUT (JPQ3) +3VS 1.8VSDGPU_AON
(UQ2) DGPU_PWR_EN_AON EM5209VF
EN_1.8VALW 1.8VSDGPU_MAIN_EN (UV16)
G9661MF11U JUMP
(PU1801) +1.8VALWP (PJ1802) +1.8VALW_PRIM 1.8VSDGPU_MAIN
SUSP# AOZ1331DI R-Short

(UC5) +1.8VS (RA6) +1.8VS_VDDA
EN_1VALW SY8288RAC JUMP R-Short

3
(PUF1) +1.05VALWP (PJF1) +1.05VALW_PRIM (RC243) +1.05VALW_MPHY 3
Inductor
(LC1) +1.05VALW_MPHYPLL
Inductor
(LC2) +VCCA_XTAL_1.05V
0 ohm
(RC143) +1.05V_VCCSFR
SYSON AOZ1331DI 0 ohm
(UC5) +1.05V_VCCSTU (RC140) +1.05V_VCCST
SUSP# AOZ1334DI-02 0 ohm

(UC6) +1.05VS_VCCSTG_IO (RC462) +1.05VS_VCCSTG
JUMP
(JPC5) +VCCIO
1.35VSDGPU_PWR_EN SY8286RAC JUMP
(PU1001) VGA@ +1.35VSDGPUP (PJ1002) +1.35VSDGPU
3_1.8VSDGPU_MAIN_EN RT8812AGQW
(PU1201)N16S_ VGA@ +VGA_CORE
4 4
RT8816AGQW
(PU1201) N17S_VGA@
EN_12VSP HCB2012KF +INVPWR_B+

(LX1) 3S@

2018/12/27 2019/12/27 Title
Issued Date Deciphered Date Power Rail
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Date : Thursday, June 06, 2019 Sheet 4 of 57
A B C D E
A B C D E
2.2K 2.2K
2.2K
+3VALW_PRIM 2.2K
+3VS
CK14 SOC_SMBCLK
SOC_SMBDATA 2N7002DW
1 SO-DIMM 1
CH15
Whiskeylake
SOC
SOC_SML0CLK 2.2K
CH14 G-Sensor
2.2K
+3VALW_PRIM
CF15 SOC_SML0DATA
1.8K
2.2K
1.8K
+1.8VSDGPU_AON
2.2K
+3VALW_PRIM
CN15 SOC_SML1CLK I2CS_SCL

D9
PJT138KA GPU
CM15 SOC_SML1DATA I2CS_SDA D8
2 2
2.2K
2.2K
+3VLP_EC
77 EC_SMB_CK1 100 ohm EC_SMB_CK1-1 4

SCL1 BATTERY
78 EC_SMB_DA1 100 ohm EC_SMB_DA1-1 3
SDA1 CONN
12
Charger
11
KBC SCL2 79 SOC_SML1CLK
SDA2 80 SOC_SML1DATA
3
KB9022 3
I2C Address Table

BUS Device Address (8 bit)
I2C_0 (+3VS) Reserved

TM-P3393-003 (TP) 0x2C
I2C_1 (+3VALW_PRIM)
FA577E-1206 (TP-ELAN) 0x15
SA577C-12A0 (TP-ELAN) 0x15
SOC_SMBCLK (+3VS) SO-DIMM2 0xA4
G-Sensor 0x30
SOC_SML1CLK GPU 0x9E
(+3VALW_PRIM) EC
BQ24781 (Charger IC) 0x12
EC_SMB_CK1 (+3VLP)
4 BATTERY PACK 0x16 4

SMBUS_Routing_Table
A B C D E
A B C D E
PWR Sequence_SKL-U2+2_DDR3L_Value_NON CS
+RTCVCC
tPCH01_Min : 9 ms
SOC_RTCRST#
1 1
+19VB
+3VLP
EC_ON
tPCH04_Min : 9 ms
+5VALW/+3VALW(+3VALW_DSW...)
tPCH34_Max : 20 ms
SPOK tPCH06_Min : 200 us (+3VALW stable (@95% of full value) to +1.0VALW_PRIM starting to ramp)
+1.8VALW_PRIM
+1.8VALW_PG
+VCCPRIM_CORE/+1.0VALW_PRIM
tPCH03_Min : 10 ms
EC_RSMRST#
ON/OFF
2
PBTN_OUT# tPCH43_Min : 95 ms 2
Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#
PM_SLP_S5#
tPCH18_Min : 90 us
ESPI_RST#
PM_SLP_S4#
SYSON
+1.0V_VCCSTU
+1.2V_VDDQ
PM_SLP_S3#
SUSP#
tCPU04 Min : 100 ns
+1.0VS_VCCSTG
tCPU10 Min : 1 ms
+VCCIO
3 3
+5VS/+3VS/+1.8VS/+1.5VS
tCPU00 Min : 1 ms
EC_VCCST_PG
VR_ON
tCPU19 Max : 100 ns
SM_PG_CTRL
tCPU18 Max : 35 us
+0.6VS_VTT
tCPU09 Min : 1 ms
+VCC_SA
VR_PWRGD
tCPU16 Min : 0 ns
PCH_PWROK (SYS_PWROK) tPLT05 Min : Platform dependent
H_CPUPWRGD
PLT_RST#
+VCC_CORE / +VCC_GT
4 4
Security Classification
2018/12/27
Compal Secret Data
2019/12/27 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
Power Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
A B C D E
A B C D E
UC1
UC1
S IC CL8068404064409 SRFFW V0 1.8G ABO!

S IC FJ8068404064702 SRD1V W0 2.1G ABO! 8565U@
8145W0@ SA0000CNR50 UC1A
SA0000C6R60 AL5 AG4
AL6 DDI1_TXN_0 EDP_TXN_0 AG3 EDP_TXN0 <28>
AJ5 DDI1_TXP_0 EDP_TXP_0 AG2 EDP_TXP0 <28>
AJ6 DDI1_TXN_1 EDP_TXN_1 AG1 EDP_TXN1 <28>
UC1
AF6 DDI1_TXP_1 EDP_TXP_1 AJ4 EDP_TXP1 <28>
UC1
AF5 DDI1_TXN_2 EDP EDP_TXN_2 AJ3 EDP_TXN2 <28>
S IC FJ8070104303905 SRGKW V0 1.8G BGA AE5 DDI1_TXP_2 EDP_TXP_2 AJ2 EDP_TXP2 <28> eDP
1 AE6 DDI1_TXN_3 EDP_TXN_3 AJ1 EDP_TXN3 <28> 1
S IC FJ8068404064604 SREJQ W0 1.6G ABO! 10510U@
DDI1_TXP_3 DDI EDP_TXP_3 EDP_TXP3 <28>
8265W0@ SA0000CNR50
SA0000C6Q60 AC4
<29> SOC_DP2_N0 AC3 DDI2_TXN_0 AH4
<29> SOC_DP2_P0 DDI2_TXP_0 EDP_AUX_N EDP_AUXN <28>
HDMI change to DDI2 port 11/26 AC1 AH3
<29> SOC_DP2_N1 DDI2_TXN_1 EDP_AUX_P EDP_AUXP <28>
UC1 AC2
<29> SOC_DP2_P1 AE4 DDI2_TXP_1 AM7
HDMI <29> SOC_DP2_N2 AE3 DDI2_TXN_2 DISP_UTILS
<29> SOC_DP2_P2 AE1 DDI2_TXP_2 AC7
UC1 S IC FJ8070104307606 SRGL0 V0 2.1G BGA
<29> SOC_DP2_N3 AE2 DDI2_TXN_3 DDI1_AUX_N AC6
10110U@
<29> SOC_DP2_P3 DDI2_TXP_3 DDI1_AUX_P AD4
SA0000CNR50 DDI2_AUX_N
S IC CL8068404064708 SRFFZ V0 2.1G ABO! AD3
8145U@ DDI2_AUX_P AG7
DISPLAY SIDEBANDS DDI3_AUX_N AG6
SA0000CNT60 EDP_COMP DDI3_AUX_P
UC1 AM6
HDMI DDC (Port B) DISP_RCOMP
CC8 CN6
UC1 S IC FJ8070104307504 SRGKY V0 1.6G BGA CC9 GPP_E18/DPPB_CTRLCLK/CNV_BT_HOST_WAKE# GPP_E13/DDPB_HPD0/DISP_MISC0 CM6 SOC_DP2_HPD From HDMI
GPP_E19/DPPB_CTRLDATA GPP_E14/DDPC_HPD1/DISP_MISC1 SOC_DP2_HPD <29>
10210U@ CP7
SOC_DP2_CTRL_CLK CH4 GPP_E15/DPPD_HPD2/DISP_MISC2 CP6 EC_SCI#
SA0000CNR50 <29> SOC_DP2_CTRL_CLK SOC_DP2_CTRL_DATA CH3 GPP_E20/DPPC_CTRLCLK GPP_E16/DPPE_HPD3/DISP_MISC3 CPU_EDP_HPD EC_SCI# <36>
S IC CL8068404064610 SRFFX V0 1.6G ABO! CM7
8265U@
<29> SOC_DP2_CTRL_DATA GPP_E21/DPPC_CTRLDATA GPP_E17/EDP_HPD/DISP_MISC4 CPU_EDP_HPD <28> From eDP
SA0000CNS70 CP4 CK11 ENBKL
CN4 GPP_E22/DPPD_CTRLCLK EDP_BKLTEN CG11 SOC_ENVDD ENBKL <36>
GPP_E23/DPPD_CTRLDATA EDP_VDDEN CH11 SOC_BKL_PWM SOC_ENVDD <28>
CR26 EDP_BKLTCTL SOC_BKL_PWM <28>
CP26 GPP_H16/DDPF_CTRLCLK
GPP_H17/DDPF_CTRLDATA
12/21 PU
#571021 CFL-U PDG R0.7 p.104
RC212 +3VS
WHL-U42_BGA1528 10K_0402_5%
2 EC_SCI# 1 @ 2 2
@ 1 of 20
EC_SCI# SOC internal PU
#545659 PCH EDS1.51 P.131

SCI capability is available on all GPIOs, while
NMI and SMI capability is available on only
select GPIOs.
Below are the PCH GPIOs that can be
+VCCIO routed to generate SMI# or NMI:
‧ GPP_B14, GPP_B20, GPP_B23
EDP_COMP
‧ GPP_C 23 : 22
RC1 1 2 24.9_0402_1%
‧ GPP_ D 4 : 0
‧GPP_E 8 : 0 , GPP_E 16 : 13
#571021 CFL-U PDG R0.7 p.39
PU 24.9ohm for eDP
+1.05VS_VCCSTG @ESD@ CC81
Reserved CATERR# .1U_0402_16V7K
SOC_XDP_TRST# 1 2
#571021 CFL-U PDG R0.7 p.248 for sight i ngs i ss ue
1
+1.05V_VCCST
PU 1Kohm to VCCST RC3 check
1K_0402_5% UC1D
RC4 H_CATERR# AA4 T6 CPU_XDP_TCK0
@ T166 CATERR# PROC_TCK
RC2 1 2 1K_0402_5% H_THERMTRIP# 499_0402_1% H_PECI AR1 U6 SOC_XDP_TDI
<36> H_PECI
2
1 2 H_PROCHOT#_R Y4 PECI CPU MISC JTAG

PROC_TDI Y5 SOC_XDP_TDO
3 <36,43> H_PROCHOT# H_THERMTRIP# PROCHOT# PROC_TDO SOC_XDP_TMS 3
1 2 BJ1 T5
CC132 ESD@ THRMTRIP# PROC_TMS AB6 SOC_XDP_TRST# ZZZ
1000P_0402_50V7K XDP_BPM#0 U1 PROC_TRST# PCB@
@ T160 XDP_BPM#1 BPM#_0
@ T161 U2
U3 BPM#_1 W6 PCH_JTAG_TCK1 PCB EH7LW LA-H791P LS-H781P/H802P/H783P
BPM#_2 PCH_TCK SOC_XDP_TDI T280 @
U4 U5 DAZ2MF00301
BPM#_3 PCH_TDI W5 SOC_XDP_TDO
PCH_TDO P5 SOC_XDP_TMS
CE9 PCH_TMS Y6 SOC_XDP_TRST#
CN3 GPP_E3/CPU_GP0 PCH_TRST# P6 CPU_XDP_TCK0 ZZZ
RC137 2 @ 1 0_0402_5% TP_INT# CB34 GPP_E7/CPU_GP1 PCH_JTAGX PCB20@
<36,37> EC_TP_INT# CC35 GPP_B3/CPU_GP2
CC52 @ESD@ GPP_B4/CPU_GP3 W2 XDP_PREQ# PCB EH7LW LA-H791P LS-H781P/H802P/H783P
PROC_PREQ# XDP_PRDY# T197 @
.1U_0402_16V7K W1 T196 @ DAZ2MF00302
2 1 H_PECI RC5 2 1 49.9_0402_1% CPU_POPIRCOMP BP27 PROC_PRDY#
RC6 2 1 49.9_0402_1% PCH_OPIRCOMP BW25 PROC_POPIRCOMP
PCH_OPIRCOMP
2 1 H_PROCHOT#_R RC7 2 @ 1 49.9_0402_1% EDRAM_OPIO_RCOMP L5 ZZZ

ESD@ CC53 RC8 2 @ 1 49.9_0402_1% EOPIO_RCOMP N5 RSVD70
1000P_0402_50V7K RSVD71
HDMI LOGO LOGO@
WHL-U42_BGA1528 RO0000003HM
#575412 WHL-U PDG R0.8
For CFL U43e, Pins L5 and N5 are OPCE_RCOMP and OPC_RCOMP respect i vel y whil e i n @ 4 of 20
WHL, CNL SoCs these pins are RSVD
For Intel debug, place to CPU side. ZZZ

+1.05VS_VCCSTG X4E@
#575412 WHL-U PDG R0.8 Figure.13-6
SMT EMC EE AH791 EH7LW
RC11 2 CMC@ 1 51_0402_5% SOC_XDP_TMS
X4EAHVBOL01
4 4
RC13 2 CMC@ 1 51_0402_5% SOC_XDP_TDI
ZZZ
RC15 2 CMC@ 1 51_0402_5% SOC_XDP_TDO X4E@
SMT EMC DIS AH791 EH5LC

CPU_XDP_TCK0
X4EAHVBOLD1
RC35 2 CMC@ 1 51_0402_5%
2018/12/27
Compal Secret Data
2019/12/27 Title
WHL-U(1/12)DDI,MSIC,XDP,EDP
Date: Friday, August 02, 2019 Sheet 7 of 57
A B C D E
A B C D E
Interleaved Memory
UC1B UC1C
<19> DDR_A_D[0..15] DDR_A_D0 A26 Interleave / Non-Interleaved <20> DDR_B_D[0..15] DDR_B_D0 J22
lnterleave /
Non-lnterleav e d
LPDDR3 / DDR4
AF28 DDR_B_CLK#0
DDR_A_D1 DDR0_DQ_0/DDR0_DQ_0 LPDDR3 / DDR4 DDR_A_CLK#0 DDR_B_D1 DDR1_DQ_0/DDR0_DQ_16 DDR1_CKN_0/DDR1_CKN_0 DDR_B_CLK0 DDR_B_CLK#0 <20>
D26 V32 H25 AF29
DDR_A_D2 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 DDR_A_CLK0 DDR_A_CLK#0 <19> DDR_B_D2 DDR1_DQ_1/DDR0_DQ_17 DDR1_CKP_0/DDR1_CKP_0 DDR_B_CLK#1 DDR_B_CLK0 <20>
D28 V31 G22 AE28
DDR_A_D3 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_0/DDR0_CKP_0 DDR_A_CLK#1 DDR_A_CLK0 <19> DDR_B_D3 DDR1_DQ_2/DDR0_DQ_18 DDR1_CKN_1/DDR1_CKN_1 DDR_B_CLK1 DDR_B_CLK#1 <20>
C28 T32 H22 AE29
DDR_A_D4 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 DDR_A_CLK1 @ T286 DDR_B_D4 DDR1_DQ_3/DDR0_DQ_19 DDR1_CKP_1/DDR1_CKP_1 DDR_B_CLK1 <20>
B26 T31 F25
DDR_A_D5 DDR0_DQ_4/DDR0_DQ_4 DDR0_CKP_1/DDR0_CKP_1 @ T285 DDR_B_D5 DDR1_DQ_4/DDR0_DQ_20 DDR_B_CKE0
C26 J25 T28
DDR_A_D6 DDR0_DQ_5/DDR0_DQ_5 DDR_A_CKE0 DDR_B_D6 DDR1_DQ_5/DDR0_DQ_21 DDR1_CKE_0/DDR1_CKE_0 DDR_B_CKE1 DDR_B_CKE0 <20>
B28 U36 G25 T29
1 DDR_A_D7 DDR0_DQ_6/DDR0_DQ_6 DDR0_CKE_0/DDR0_CKE_0 DDR_A_CKE1 DDR_A_CKE0 <19> DDR_B_D7 DDR1_DQ_6/DDR0_DQ_22 DDR1_CKE_1/DDR1_CKE_1 DDR_B_CKE1 <20> 1
A28 U37 F22 V28
DDR_A_D8 DDR0_DQ_7/DDR0_DQ_7 DDR0_CKE_1/DDR0_CKE_1 @ T289 DDR_B_D8 DDR1_DQ_7/DDR0_DQ_23 DDR1_CKE_2/NC
B30 U34 D22 V29
DDR_A_D9 D30 DDR0_DQ_8/DDR0_DQ_8 DDR0_CKE_2/NC U35 DDR_B_D9 C22 DDR1_DQ_8/DDR0_DQ_24 DDR1_CKE_3/NC
DDR_A_D10 B33 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_3/NC DDR_B_D10 C24 DDR1_DQ_9/DDR0_DQ_25 AL37 DDR_B_CS#0
DDR_A_D11 DDR0_DQ_10/DDR0_DQ_10 DDR_A_CS#0 DDR_B_D11 DDR1_DQ_10/DDR0_DQ_26 DDR1_CS#_0/DDR1_CS#_0 DDR_B_CS#1 DDR_B_CS#0 <20>
D32 AE32 D24 AL35
DDR_A_D12 DDR0_DQ_11/DDR0_DQ_11 DDR0_CS#_0/DDR0_CS#_0 DDR_A_CS#1 DDR_A_CS#0 <19> DDR_B_D12 DDR1_DQ_11/DDR0_DQ_27 DDR1_CS#_1/DDR1_CS#_1 DDR_B_ODT0 DDR_B_CS#1 <20>
A30 AF32 A22 AL36
DDR_A_D13 DDR0_DQ_12/DDR0_DQ_12 DDR0_CS#_1/DDR0_CS#_1 DDR_A_ODT0 @ T287 DDR_B_D13 DDR1_DQ_12/DDR0_DQ_28 DDR1_ODT_0/DDR1_ODT_0 DDR_B_ODT1 DDR_B_ODT0 <20>
C30 AE31 B22 AL34
DDR_A_D14 DDR0_DQ_13/DDR0_DQ_13 DDR0_ODT_0/DDR0_ODT_0 DDR_A_ODT1 DDR_A_ODT0 <19> DDR_B_D14 DDR1_DQ_13/DDR0_DQ_29 NC/DDR1_ODT_1 DDR_B_MA0 DDR_B_ODT1 <20>
B32 AF31 A24 AG36
DDR_A_D15 DDR0_DQ_14/DDR0_DQ_14 NC/DDR0_ODT_1 @ T288 DDR_B_D15 DDR1_DQ_14/DDR0_DQ_30 DDR1_CAB_9/DDR1_MA_0 DDR_B_MA1 DDR_B_MA0 <20>
C32 B24 AG35
<19> DDR_A_D[16..31] DDR_A_D16 DDR0_DQ_15/DDR0_DQ_15 DDR_A_MA0 <20> DDR_B_D[16..31] DDR_B_D16 DDR1_DQ_15/DDR0_DQ_31 DDR1_CAB_8/DDR1_MA_1 DDR_B_MA2 DDR_B_MA1 <20>
H37 AC37 G31 AF34
DDR_A_D17 DDR0_DQ_16/DDR0_DQ_32 DDR0_CAB_9/DDR0_MA_0 DDR_A_MA1 DDR_A_MA0 <19> DDR_B_D17 DDR1_DQ_16/DDR0_DQ_48 DDR1_CAB_5/DDR1_MA_2 DDR_B_MA3 DDR_B_MA2 <20>
H34 AC36 G32 AG37
DDR_A_D18 DDR0_DQ_17/DDR0_DQ_33 DDR0_CAB_8/DDR0_MA_1 DDR_A_MA2 DDR_A_MA1 <19> DDR_B_D18 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_MA_3 DDR_B_MA4 DDR_B_MA3 <20>
K34 AC34 H29 AE35
DDR_A_D19 DDR0_DQ_18/DDR0_DQ_34 DDR0_CAB_5/DDR0_MA_2 DDR_A_MA3 DDR_A_MA2 <19> DDR_B_D19 DDR1_DQ_18/DDR0_DQ_50 NC/DDR1_MA_4 DDR_B_MA5 DDR_B_MA4 <20>
K35 AC35 H28 AF35
DDR_A_D20 DDR0_DQ_19/DDR0_DQ_35 NC/DDR0_MA_3 DDR_A_MA4 DDR_A_MA3 <19> DDR_B_D20 DDR1_DQ_19/DDR0_DQ_51 DDR1_CAA_0/DDR1_MA_5 DDR_B_MA6 DDR_B_MA5 <20>
H36 AA35 G28 AE37
DDR_A_D21 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_MA_4 DDR_A_MA5 DDR_A_MA4 <19> DDR_B_D21 DDR1_DQ_20/DDR0_DQ_52 DDR1_CAA_2/DDR1_MA_6 DDR_B_MA7 DDR_B_MA6 <20>
H35 AB35 G29 AC29
DDR_A_D22 DDR0_DQ_21/DDR0_DQ_37 DDR0_CAA_0/DDR0_MA_5 DDR_A_MA6 DDR_A_MA5 <19> DDR_B_D22 DDR1_DQ_21/DDR0_DQ_53 DDR1_CAA_4/DDR1_MA_7 DDR_B_MA8 DDR_B_MA7 <20>
K36 AA37 H31 AE36
K37 AA36 H32 AB29
N36 AB34 L31 AG34
DDR_A_D25 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAA_3/DDR0_MA_8 DDR_A_MA9 DDR_A_MA8 <19> DDR_B_D25 DDR1_DQ_24/DDR0_DQ_56 DDR1_CAB_7/DDR1_MA_10 DDR_B_MA11 DDR_B_MA10 <20>
N34 W36 L32 AC28
R37 Y31 N29 AB28
DDR_A_D27 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAB_7/DDR0_MA_10 DDR_A_MA11 DDR_A_MA10 <19> DDR_B_D27 DDR1_DQ_26/DDR0_DQ_58 DDR1_CAA_6/DDR1_MA_12 DDR_B_MA13 DDR_B_MA12 <20>
R34 W34 N28 AK35
DDR_A_D28 DDR0_DQ_27/DDR0_DQ_43 DDR0_CAA_7/DDR0_MA_11 DDR_A_MA12 DDR_A_MA11 <19> DDR_B_D28 DDR1_DQ_27/DDR0_DQ_59 DDR1_CAB_0/DDR1_MA_13 DDR_B_MA13 <20>
N37 AA34 L28
DDR_A_D29 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAA_6/DDR0_MA_12 DDR_A_MA13 DDR_A_MA12 <19> DDR_B_D29 DDR1_DQ_28/DDR0_DQ_60 DDR_B_MA14
N35 AC32 L29 AJ35
DDR_A_D30 DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_0/DDR0_MA_13 DDR_A_MA13 <19> DDR_B_D30 DDR1_DQ_29/DDR0_DQ_61 DDR1_CAB_2/DDR1_MA_14 DDR_B_MA15 DDR_B_MA14 <20>
R36 N31 AK34
DDR_A_D31 DDR0_DQ_30/DDR0_DQ_46 DDR_A_MA14 DDR_B_D31 DDR1_DQ_30/DDR0_DQ_62 DDR1_CAB_1/DDR1_MA_15 DDR_B_MA16 DDR_B_MA15 <20>
R35 AC31 N32 AJ34
<19> DDR_A_D[32..47] DDR_A_D32 DDR0_DQ_31/DDR0_DQ_47 DDR0_CAB_2/DDR0_MA_14 DDR_A_MA15 DDR_A_MA14 <19><20> DDR_B_D[32..47] DDR_B_D32 DDR1_DQ_31/DDR0_DQ_63 DDR1_CAB_3/DDR1_MA_16 DDR_B_MA16 <20>
AN35 AB32 AJ29
DDR_A_D33 DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_1/DDR0_MA_15 DDR_A_MA16 DDR_A_MA15 <19> DDR_B_D33 DDR1_DQ_32/DDR1_DQ_16 DDR_B_BA0
AN34 Y32 AJ30 AJ37
DDR_A_D34 DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_3/DDR0_MA_16 DDR_A_MA16 <19> DDR_B_D34 DDR1_DQ_33/DDR1_DQ_17 DDR1_CAB_4/DDR1_BA_0 DDR_B_BA1 DDR_B_BA0 <20>
AR35 AM32 AJ36
DDR_A_D35 DDR0_DQ_34/DDR1_DQ_2 DDR_A_BA0 DDR_B_D35 DDR1_DQ_34/DDR1_DQ_18 DDR1_CAB_6/DDR1_BA_1 DDR_B_BG0 DDR_B_BA1 <20>
AR34 W32 AM31 W29
DDR_A_D36 DDR0_DQ_35/DDR1_DQ_3 DDR0_CAB_4/DDR0_BA_0 DDR_A_BA1 DDR_A_BA0 <19> DDR_B_D36 DDR1_DQ_35/DDR1_DQ_19 DDR1_CAA_5/DDR1_BG_0 DDR_B_BG0 <20>
AN37 AB31 AM30
DDR_A_D37 DDR0_DQ_36/DDR1_DQ_4 DDR0_CAB_6/DDR0_BA_1 DDR_A_BG0 DDR_A_BA1 <19> DDR_B_D37 DDR1_DQ_36/DDR1_DQ_20 DDR_B_BG1
AN36 V34 AM29 Y28
DDR_A_D38 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_5/DDR0_BG_0 DDR_A_BG0 <19> DDR_B_D38 DDR1_DQ_37/DDR1_DQ_21 DDR1_CAA_9/DDR1_BG_1 DDR_B_ACT# DDR_B_BG1 <20>
AR36 AJ31 W28
2 DDR_A_D39 DDR0_DQ_38/DDR1_DQ_6 DDR_A_ACT# DDR_B_D39 DDR1_DQ_38/DDR1_DQ_22 DDR1_CAA_8/DDR1_ACT# DDR_B_ACT# <20> 2
AR37 V35 AJ32
DDR_A_D40 DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_8/DDR0_ACT# DDR_A_BG1 DDR_A_ACT# <19> DDR_B_D40 DDR1_DQ_39/DDR1_DQ_23 lnterleave / Non-lnterleaved DDR_B_DQS#0
AU35 W35 AR31 H24
DDR_A_D41 DDR0_DQ_40/DDR1_DQ_8 DDR0_CAA_9/DDR0_BG_1 DDR_A_BG1 <19> DDR_B_D41 DDR1_DQ_40/DDR1_DQ_24 DDR1_DQSN_0/DDR0_DQSN_2 DDR_B_DQS0 DDR_B_DQS#0 <20>
AU34 AR32 G24
DDR_A_D42 DDR0_DQ_41/DDR1_DQ_9 Interleave / Non-Interleaved DDR_A_DQS#0 DDR_B_D42 DDR1_DQ_41/DDR1_DQ_25 DDR1_DQSP_0/DDR0_DQSP_2 DDR_B_DQS#1 DDR_B_DQS0 <20>
AW35 C27 AV30 C23
DDR_A_D43 DDR0_DQ_42/DDR1_DQ_10 DDR0_DQSN_0/DDR0_DQSN_0 DDR_A_DQS0 DDR_A_DQS#0 <19> DDR_B_D43 DDR1_DQ_42/DDR1_DQ_26 DDR1_DQSN_1/DDR0_DQSN_3 DDR_B_DQS1 DDR_B_DQS#1 <20>
AW34 D27 AV29 D23
DDR_A_D44 DDR0_DQ_43/DDR1_DQ_11 DDR0_DQSP_0/DDR0_DQSP_0 DDR_A_DQS#1 DDR_A_DQS0 <19> DDR_B_D44 DDR1_DQ_43/DDR1_DQ_27 DDR1_DQSP_1/DDR0_DQSP_3 DDR_B_DQS#2 DDR_B_DQS1 <20>
AU37 D31 AR30 G30
AU36 C31 AR29 H30
AW36 J35 AV32 L30
AW37 J34 AV31 N30
<19> DDR_A_D[48..63] DDR_A_D48 DDR0_DQ_47/DDR1_DQ_15 DDR0_DQSP_2/DDR0_DQSP_4 DDR_A_DQS#3 DDR_A_DQS2 <19>
<20> DDR_B_D[48..63] DDR_B_D48 DDR1_DQ_47/DDR1_DQ_31 DDR1_DQSP_3/DDR0_DQSP_7 DDR_B_DQS#4 DDR_B_DQS3 <20>
BA35 P34 BA32 AL31
BA34 P35 BA31 AL30
BC35 AP35 BD31 AU31
BC34 AP34 BD32 AU30
BA37 AV34 BA30 BC31
BA36 AV35 BA29 BC30
BC36 BB35 BD29 BH31
BC37 BB34 BD30 BH30
DDR_A_D56 DDR0_DQ_55/DDR1_DQ_39 DDR0_DQSP_6/DDR1_DQSP_4 DDR_A_DQS#7 DDR_A_DQS6 <19> DDR_B_D56 DDR1_DQ_55/DDR1_DQ_55 DDR1_DQSP_7/DDR1_DQSP_7 DDR_B_DQS7 <20>
BE35 BF34 BG31
DDR_A_D57 DDR0_DQ_56/DDR1_DQ_40 DDR0_DQSN_7/DDR1_DQSN_5 DDR_A_DQS7 DDR_A_DQS#7 <19> DDR_B_D57 DDR1_DQ_56/DDR1_DQ_56 DDR_B_ALERT#
BE34 BF35 BG32 Y29
DDR_A_D58 DDR0_DQ_57/DDR1_DQ_41 DDR0_DQSP_7/DDR1_DQSP_5 DDR_A_DQS7 <19> DDR_B_D58 DDR1_DQ_57/DDR1_DQ_57 NC/DDR1_ALERT# DDR_B_PAR DDR_B_ALERT# <20>
BG35 BK32 AE34
DDR_A_D59 DDR0_DQ_58/DDR1_DQ_42 LPDDR3 / DDR4 DDR_A_ALERT# DDR_B_D59 DDR1_DQ_58/DDR1_DQ_58 NC/DDR1_PAR DDR_B_PAR <20>
BG34 W37 BK31 BU31
DDR_A_D60 DDR0_DQ_59/DDR1_DQ_43 NC/DDR0_ALERT# DDR_A_PAR DDR_A_ALERT# <19> DDR_B_D60 DDR1_DQ_59/DDR1_DQ_59 DRAM_RESET# DDR_DRAMRST# <19,20>
BE37 W31 BG29
DDR_A_D61 DDR0_DQ_60/DDR1_DQ_44 NC/DDR0_PAR DDR_A_PAR <19> DDR_B_D61 DDR1_DQ_60/DDR1_DQ_60 SM_RCOMP0
BE36 BG30 BN28
DDR_A_D62 BG36 DDR0_DQ_61/DDR1_DQ_45 F36 +0.6V_A_VREFCA DDR_B_D62 BK30 DDR1_DQ_61/DDR1_DQ_61 DDR_RCOMP_0 BN27 SM_RCOMP1
DDR_A_D63 DDR0_DQ_62/DDR1_DQ_46 DDR_VREF_CA +0.6V_A_VREFCA DDR_B_D63 DDR1_DQ_62/DDR1_DQ_62 DDR_RCOMP_1 SM_RCOMP2
BG37 D35 BK29 BN29
DDR0_DQ_63/DDR1_DQ_47 DDR0_VREF_DQ_0 D37 DDR1_DQ_63/DDR1_DQ_63 DDR_RCOMP_2
DDR0_VREF_DQ_1 E36 +0.6V_B_VREFCA
DDR1_VREF_DQ DDR_PG_CTRL +0.6V_B_VREFCA
C35 WHL-U42_BGA1528
DDR_VTT_CTL
WHL-U42_BGA1528
#571021 CFL-U PDG0.7 p.64 @ 3 of 20
@
Trace width/Spacing >= 20mils
2 of 20
3 3
+1.2V_VDDQ
+3VS #595182 P38 SM_RCOMP0 RC38 1 2 121_0402_1%

SM_RCOMP1 RC39 1 2 80.6_0402_1%
0.1U_0201_10V6K 2 1 CC57 SM_RCOMP2 RC40 1 2 100_0402_1%
2
UC7 RC10
1 5
NC VCC 100K_0402_5% #571021 PDG P.64
DDR_PG_CTRL 2 W=15 Space= 20/25 L=500mil
1
A 4
3 Y SM_PG_CTRL <45>
@ESD@
GND DDR_DRAMRST# CC70 1 2 .1U_0402_16V7K
2
74AUP1G07SE-7_SOT353_5P DDR_VTT_CNTL to DDR

RC16
@ 1M_0402_5% VTT supplied ramped
Change PN to SA00007WE00 <35uS 2015MOW02, Can't install Cap on DRAMRST
(tCPU18)
1
4 4
2018/12/27
Compal Secret Data
2019/12/27 Title
WHL-U(2/12)DDR4
A B C D E
A B C D E
+3VS
SOC_SMBCLK_1 RC222 1 2 2.2K_0402_5%

SOC_SMBDATA_1RC223 1 2 2.2K_0402_5%
+3VALW_PRIM
SOC_SML0CLK RC49 1 2 2.2K_0402_5%

SOC_SML0DATA RC50 1 2 2.2K_0402_5%
#571021 CFL-U PDG R0.7 p.290
1 change RC49,RC50 to 2.2K 1
SOC_SML1CLK RC267 1 2 2.2K_0402_5%

SOC_SML1DATA RC268 1 2 2.2K_0402_5%
SOC_SMBCLK RC269 1 2 2.2K_0402_5%
SOC_SMBDATA RC270 1 2 2.2K_0402_5%
SPI ROM UC1E
SOC_SPI_CLK CH37 CK14 SOC_SMBCLK +3VS
<37> SOC_SPI_CLK SOC_SPI_SO CF37 SPI0_CLK GPP_C0/SMBCLK CH15 SOC_SMBDATA SMB (to DDR, G sensor)
<37> SOC_SPI_SO SOC_SPI_SI SPI0_MISO GPP_C1/SMBDATA SOC_SMBALERT#
CF36 CJ15
<37> SOC_SPI_SI SOC_SPI_IO2 SPI0_MOSI GPP_C2/SMBALERT# @ T239
CF34
SPI0_IO2
5
SOC_SPI_IO3 CG34 SPI - FLASH CH14 SOC_SML0CLK +3VALW_PRIM
Strap Pin SML0 (Reserve)
G
SOC_SPI_CS#0 CG36 SPI0_IO3 SMBUS , SMLINK GPP_C3/SML0CLK CF15 SOC_SML0DATA QC2B
CG35 SPI0_CS0# GPP_C4/SML0DATA CG15 SOC_SML0ALERT# 4.7K_0402_5% 2 ESPI@ 1 RC202 2N7002KDW_SOT363-6
SOC_SPI_CS#2 CH34 SPI0_CS1# GPP_C5/SML0ALERT#
<37> SOC_SPI_CS#2 SPI0_CS2# SOC_SML1CLK SOC_SMBCLK SOC_SMBCLK_1
CN15 3 4
SOC_SML1CLK <21,36>
S
#575412 WHL-U schchecklist R0.8 SPI0_CS2# GPP_C6/SML1CLK CM15 SOC_SML1DATA SOC_SMBCLK_1 <20,33>
SML1 ( to EC, Thermal sensor)
D
GPP_C7/SML1DATA SOC_SML1DATA <21,36>
2
Used to select TPM device if it connected to SPI interface CF20 CC34 SOC_SML1ALERT#
G
GPP_D1/SPI1_CLK/BK1/SBK1 GPP_B23/SML1ALERT#/PCHHOT# @ T234
CG22 QC2A
CF22 GPP_D2/SPI1_MISO_IO1/BK2/SBK2 2N7002KDW_SOT363-6
CG23 GPP_D3/SPI1_MOSI_IO0/BK3/SBK3 CA29 LPC_AD0 RC144 1 @ 2 0_0402_5%
ESPI / LPC Bus
+3VS
SPI Touch CH23 GPP_D21/SPI1_IO2 SPI - TOUCH GPP_A1/LAD0/ESPI_IO0 BY29 LPC_AD1 1 2 LPC_AD0_R <36> SOC_SMBDATA 6 1 SOC_SMBDATA_1
RC145 @ 0_0402_5% ESPI : +1.8V SOC_SMBDATA_1 <20,33>
S
CG20 GPP_D22/SPI1_IO3 GPP_A2/LAD1/ESPI_IO1 BY27 LPC_AD2 1 2 LPC_AD1_R <36>
RC146 @ 0_0402_5%
D
GPP_D0/SPI1_CS0#/BK0/SBK0 GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
BV27 LPC_AD3 RC147 1 @ 2 0_0402_5%
LPC_AD2_R
LPC_AD3_R
<36>
<36> * LPC : +3.3V
1
CA28 LPC_FRAME#
GPP_A5/LFRAME#/ESPI_CS# CA27 ESPI_RST# LPC_FRAME# <36>
RC466
CH7 LPC , ESPI GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RST# <36>
10K_0402_5% CL_CLK
CH8 C LINK
CH9 CL_DATA BV32 CLKOUT_LPC0 RC45 2 LPC@ 1 22_0402_5%
CLK_LPC_EC <36> To EC
2
CL_RST# GPP_A9/CLKOUT_LPC0/ESPI_CLK BV30 +1.8VS_3VS_PGPPA

2 RCIN# BV29 GPP_A10/CLKOUT_LPC1 BY30 PM_CLKRUN# 2
#570990 CFL-U CRB R1.0 p.134
EC_SERIRQ BV28 GPP_A0/RCIN#/TIME_SYNC1 GPP_A8/CLKRUN# Change PM_CLKRUN# PU 8.2K
<36> EC_SERIRQ GPP_A6/SERIRQ PM_CLKRUN#
#575412 WHL-U Schchk R0.8 1 2
LPC Mode change RC45 to 15ohm when use ESPI RC107 8.2K_0402_5%
WHL-U42_BGA1528 EC_SERIRQ 1 2
@ RC112 8.2K_0402_5%
5 of 20
RC45 ESPI@ #571021 CFL-U Schchk R0.7 p.37
15_0402_5% Change TPM_SERIRQ PU 8.2K
SD028150A80
SML0ALERT# / GPP_C5 (Internal Pull Down):

(Sampled: Rising edge of RSMRST# )
eSPI or LPC
*0 = LPC is selected for EC --> For KB9022/9032 Use
#575412 WHL-U schchk R0. 1 = eSPI is selected for EC --> For KB9032 Only.
50Ω series resistor: 3.3V UC2
33Ω series resistor: 1.8V
SMBALERT# / GPP_C2 (Internal Pull Down):
256M MX25L25673GM2I-08G SOP 8P
(Sampled: Rising edge of RSMRST# )
VPRO@
SPI ROM ( 16MByte ) +3VALW_SPI CC8 SA0000AV400 TLS Conf i dent ial i ty
close UC2 0.1U_0201_10V6K
SOC_SPI_SO RC263 2 1 51_0402_5% SOC_SPI_SO_0_R SOC_SPI_CS#0 1
UC2
8
1 2 * 0 = Disable Intel ME Crypto Transport Layer Security
SOC_SPI_SI RC264 2 1 51_0402_5% SOC_SPI_SI_0_R SOC_SPI_SO_0_R 2 /CS VCC 7 SOC_SPI_IO3_0_R (TLS) cipher suite (no conf i dent ial i ty).
SOC_SPI_CLK RC265 SOC_SPI_CLK_0_R SOC_SPI_IO2_0_R DO(IO1) /HOLD(IO3) SOC_SPI_CLK_0_R
SOC_SPI_IO3 RC266
2
2
1
1
51_0402_5%
SOC_SPI_IO3_0_R
3
4 /WP(IO2) CLK
6
5 SOC_SPI_SI_0_R
1 = Enable Intel ME Crypto (TLS) (with conf i dent ial i ty).
51_0402_5%
3 GND DI(IO0) Must be pulled up to support Intel AMT with TLS and Intel 3
128M XM25QH128AHIG SOP 8P
SA0000B8400 Main
2015MOW06 no need PU1K on SPI_IO2/IO3 SBA (Small Business Advantage) with TLS.
source: XMC +3VALW_SPI
SOC_SPI_CLK_0_R 1 @EMI@ 2 1 2
RC24 0_0402_5% CC9 @EMI@ SOC_SPI_IO2 RC47 1 @ 2 1K_0402_1%
10P_0402_50V8J
SOC_SPI_IO3 RC48 1 @ 2 1K_0402_1%
SOC_SPI_IO2 2 1 SOC_SPI_IO2_0_R
RC52 51_0402_5% ROM Socket
PVT remove JC1 socket footprint
4 4
2018/12/27
Compal Secret Data
2019/12/27 Title
WHL-U(3/12)SPI,ESPI,SMB,LPC
A B C D E
A B C D E
#575412 WHL DG p292_

add 2pF cap on HDA_SDO and HDA_RST# close to CPU
add 2pF cap on HDA_SDI close to codec
11/26
HDA_SDOUT
HDA_RST#
1 1
CC154
CC153
2P_0201_25V8B 2P_0201_25V8B
1 2 2 1
UC1G
HDA for AUDIO HDA_SYNC
HDA_BIT_CLK
BN34
HDA_SYNC/I2S0_SFRM
BN37 CH36
HDA_SDOUT BN36 HDA_BCLK/I2S0_SCLK AUDIO SDIO / SDXC GPP_G0/SD_CMD CL35
HDA_SDIN0 HDA_SDIN0 BN35 HDA_SDO/I2S0_TXD GPP_G1/SD_DATA0 CL36
<32> HDA_SDIN0 HDA_SDI0/I2S0_RXD GPP_G2/SD_DATA1
BL36 CM35
HDA_RST# BL35 HDA_SDI1/I2S1_RXD/SNDW1_DATA GPP_G3/SD_DATA2 CN35
RC271 1 2 33_0402_5% HDA_BIT_CLK CK23 HDA_RST#/I2S1_SCLK/SNDW1_CLK GPP_G4/SD_DATA3 CH35
<32> HDA_BIT_CLK_R HDA_SDOUT GPP_D23/I2S_MCLK GPP_G5/SD_CD#
RC272 1 2 33_0402_5% I2S_MCLK internal pu-down CK36
<32> HDA_SDOUT_R HDA_SYNC GPP_G6/SD_CLK
RC273 1 2 33_0402_5% BL37 CK34
<32> HDA_SYNC_R HDA_RST# I2S1_SFRM/SNDW2_CLK GPP_G7/SD_WP
RC274 1 2 33_0402_5% BL34
<32> HDA_RST#_R I2S1_TXD/SNDW2_DATA
CNV_RF_RESET# CJ32
2 1 <31> CNV_RF_RESET# M2_BT_PCM_CLK CH32 GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET#
<36> ME_EN @ <31> M2_BT_PCM_CLK
RC77 0_0402_5% CLKREQ_CNV# CH29 GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK
<31> CLKREQ_CNV# M2_BT_PCM_OUT CH30 GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ BW36
<31> M2_BT_PCM_OUT GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7 BY31
HDA_SDO / I2S_TXD0 (Internal Pull Down): PCH_DMIC_CLK CP24 GPP_A16/SD_1P8_SEL
(Sampled: Rising edge of PCH_PWROK ) <32> PCH_DMIC_CLK PCH_DMIC_DATA GPP_D19/DMIC_CLK0/SNDW4_CLK
CN24 RC76
<32> PCH_DMIC_DATA GPP_D20/DMIC_DATA0/SNDW4_DATA
Flash Descriptor Security Override SD_1P8_RCOMP
CK33 200_0402_1%
0 = Enable security measures def i nedi n t he Fl as h CK25 CM34 RCOMP 2 1
CJ25 GPP_D17/DMIC_CLK1/SNDW3_CLK SD_3P3_RCOMP
2 Descriptor. GPP_D18/DMIC_DATA1/SNDW3_DATA 2
1 = Disable Flash Descriptor Security (override). This PCH_SPKR CF35
#571021 CFL-U PDG R1.0 p.39
<32> PCH_SPKR GPP_B14/SPKR SD_1P8_RCOMP, SD_3P3_RCOPM, EMMC_RCOMP
strap should only be asserted high using external
WHL-U42_BGA1528 can be marged into one 200ohm +/-1%
@
pull-up in manufacturing/debug environments ONLY. 7 of 20
+3VALW_PRIM
Add PU resistor 12/20
1
SPKR / GPP_B14 (Internal Pull Down): RC467 +3VALW_PRIM
(Sampled:Rising edge of PCH_PWROK) 100K_0402_5%
C10@
1
UC1I
2
TOP Swap Override CNV_PRX_DTX_N0 CR30 CNVio CN27 CPU_C10_GATE# UMA@
RC133
10K_0402_5%
* 0 = Disable TOP Swap mode. <31>
<31>
CNV_PRX_DTX_N0
CNV_PRX_DTX_P0
CNV_PRX_DTX_P0 CP30 CNV_WR_D0N
CNV_WR_D0P
GPP_H18/CPU_C10_GATE#
CM27
CPU_C10_GATE# <14>
1 = Enable TOP Swap Mode.
2
CNV_PRX_DTX_N1 CM30 GPP_H19/TIMESYNC_0
<31> CNV_PRX_DTX_N1 CNV_PRX_DTX_P1 CN30 CNV_WR_D1N CF25 XTAL_FREQ_SELECT DGPU_PRSNT#
<31> CNV_PRX_DTX_P1 CNV_PTX_DRX_N0 CN32 CNV_WR_D1P GPP_H21/XTAL_FREQ_SELECT CN26
<31> CNV_PTX_DRX_N0 CNV_PTX_DRX_P0 CNV_WT_D0N GPP_H22 GPP_H23
CM32 CM26
<31> CNV_PTX_DRX_P0 CNV_WT_D0P GPP_H23 @ T276 +3VALW_DSW
CK17
Intel HD Audio link capabilit i es GPP_F10
1
CNV_PTX_DRX_N1 CP33
> Two SDI signals to support two external codecs. <31> CNV_PTX_DRX_N1 CNV_PTX_DRX_P1 CN33 CNV_WT_D1N BV35 GPD7 1 2 RC134
<31> CNV_PTX_DRX_P1 CNV_WT_D1P GPD7
> Drivers variable requency (5MHz to 24MHz) BCLK to support: CN20 RC259 100K_0402_5% VGA@ 10K_0402_5%
CLK_CNV_PRX_DTX_N CN31 GPP_F3
-- SDO double pumped up to 48 Mb/s <31> CLK_CNV_PRX_DTX_N CLK_CNV_PRX_DTX_P CNV_WR_CLKN DGPU_PRSNT#
#570990 CFL-U CRB R1.0
GPD7 (External pull-up is required)
CP31 CG25
-- SDI's single pumped up to 24 Mb/s <31> CLK_CNV_PRX_DTX_P
2
CLK_CNV_PTX_DRX_N CNV_WR_CLKP GPP_D4/IMGCLKOUT0/BK4/SBK4 XTAL INPUT MODE
CP34 CH25 HIGH:XTAL is at t ached
> Provides cadence for 44.1 kHz based sample rate output. <31> CLK_CNV_PTX_DRX_N CLK_CNV_PTX_DRX_P CNV_WT_CLKN GPP_H20/IMGCLKOUT_1
CN34
<31> CLK_CNV_PTX_DRX_P CNV_WT_CLKP
> Support 1.5V, 1.8V, and 3.3V modes. GPP_F12/EMMC_DATA0
CR20
1 2 CNV_WT_RCOMP CP32 CM20
3 RC254 150_0402_1% CR32 CNV_WT_RCOMP_0 GPP_F13/EMMC_DATA1 CN19 3
CP20 CNV_WT_RCOMP_1 EMMC GPP_F14/EMMC_DATA2 CM19
GPP_F0/CNV_PA_BLANKING GPP_F15/EMMC_DATA3
DGPU_PRSNT#
CN18
CK19 GPP_F16/EMMC_DATA4 CR18
CG17 GPP_F1 GPP_F17/EMMC_DATA5 CP18
DIS,Optimus 0
GPP_F2 GPP_F18/EMMC_DATA6 CM18
0_0402_5%2 @ 1 RC230 CR14 GPP_F19/EMMC_DATA7 UMA 1
<21,36,43> DGPU_AC_DETECT CP14 GPP_C8/UART0_RXD
GPU_EVENT# 2 @ 1 GPU_EVENT_R# CN14 GPP_C9/UART0_TXD CM16
<21> GPU_EVENT# CM14 GPP_C10/UART0_RTS# GPP_F20/EMMC_RCLK CP16
0_0402_5% RC204
GPP_C11/UART0_CTS# GPP_F21/EMMC_CLK CR16
CJ17 GPP_F11/EMMC_CMD CN16
CH17 GPP_F8/CNV_MFUART2_RXD GPP_F22/EMMC_RESET# +3VALW_PRIM
GPP_F9/CNV_MFUART2_TXD CK15 RCOMP
1 WHL@ 2 A4WP_PRESENT CF17 EMMC_RCOMP
GPP_F23/A4WP_PRESENT
1
RC262 10K_0402_5% #571021 CFL-U PDG R1.0 p.39
INTEL_MAX recommend to mount PD 10K
WHL-U42_BGA1528 SD_1P8_RCOMP, SD_3P3_RCOPM, EMMC_RCOMP RC256
@ can be marged into one 200ohm 1% 4.7K_0402_5%
RC262 CML@ 9 of 20
2
75K_0402_5% XTAL_FREQ_SELECT
SD028750280
2
RC258
@ 20K_0402_5%
1
#570990 CFL-U CRB R1.0
XTAL_FREQ_SELECT
LOW: 38.4/19.2MHz
4
HIGH: 24MHz 4
2018/12/27
Compal Secret Data
2019/12/27 Title
WHL-U(4/12)HDA,EMMC,SDIO,CNVI
A B C D E
A B C D E
#575412 WHL DG p268

change to 200K 1% resistor
11/26
#575412 P31 SOC_XTAL24_IN RC235 1 2 33_0402_1% SOC_XTAL24_IN_R

+RTCVCC
RC92
RC91 1 2 20K_0402_5% SOC_SRTCRST# SOC_XTAL24_OUT RC236 1 2 33_0402_1% SOC_XTAL24_OUT_R 2 1 200K_0402_1%
1 2 563377 Intel MOW 33

For layout routing ,PCIE CLK P0/P3 exchange
CC10 1U_0201_6.3V6M YC1
1 RC93 1 2 20K_0402_5% SOC_RTCRST# 24MHZ_18PF_XRCGB24M000F2P51R0 1
SOC_RTCRST# <36>
1 2 UC1J 3 1
CC11 1U_0201_6.3V6M 3 1
CLK_PCIE_N0 CLOCK SINGNALS CLK_CPU_ITP# NC NC
JCMOS1 1 @ 2 0_0603_5% CLR CMOS AW2 AU1 T164 @ 1 1
<31> CLK_PCIE_N0 CLK_PCIE_P0 AY3 CLKOUT_PCIE_N_0 CLKOUT_ITPXDP_N AU2 CLK_CPU_ITP
M.2/SSD <31> CLK_PCIE_P0 CLKREQ_PCIE#0 CLKOUT_PCIE_P_0 CLKOUT_ITPXDP_P T165 @ 4 2
Place at RAM DOOR CF32
<31> CLKREQ_PCIE#0 GPP_B5/SRCCLKREQ0# BT32 SUSCLK CC12 CC13
CLK_PCIE_N1 BC1 GPD8/SUSCLK SUSCLK <31> 2 2
<30> CLK_PCIE_N1 CLK_PCIE_P1 BC2 CLKOUT_PCIE_N_1 CK3 SOC_XTAL24_IN
GLAN <30> CLK_PCIE_P1 CLKREQ_PCIE#1 CLKOUT_PCIE_P_1 XTAL_IN SOC_XTAL24_OUT
27P_0402_50V8J 27P_0402_50V8J
CE32 CK2
SM_INTRUDER# <30> CLKREQ_PCIE#1 GPP_B6/SRCCLKREQ1# XTAL_OUT
RC941 2 1M_0402_5%
CLK_PCIE_N2 BD3 CJ1 XCLK_BIASREF
<31> CLK_PCIE_N2 CLK_PCIE_P2 BC3 CLKOUT_PCIE_N_2 XCLK_BIASREF CM3
WLAN <31> CLK_PCIE_P2 CLKREQ_PCIE#2 CLKOUT_PCIE_P_2 CLKIN_XTAL REFCLK_CNV <31>
CF30
+3VS <31> CLKREQ_PCIE#2 GPP_B7/SRCCLKREQ2# SOC_RTCX1
BN31
CLK_PCIE_N3 BH3 RTCX1 BN32 SOC_RTCX2
<21> CLK_PCIE_N3 CLKOUT_PCIE_N_3 RTCX2
1
1 2 10K_0402_5% CLKREQ_PCIE#1 CLK_PCIE_P3 BH4
RC121 DGPU <21> CLK_PCIE_P3 CLKREQ_PCIE#3 CLKOUT_PCIE_P_3 SOC_SRTCRST# #575412 P46
CE31 BR37 RC255
CLKREQ_PCIE#0 <21> CLKREQ_PCIE#3 GPP_B8/SRCCLKREQ3# SRTCRST# SOC_RTCRST# PD 60 ohm
R115 1 2 10K_0402_5% BR34 10K_0402_5%
BA1 RTCRST#
BA2 CLKOUT_PCIE_N_4
2
CLKREQ_PCIE#4 CE30 CLKOUT_PCIE_P_4
RC282 2 1 10K_0402_5% CLKREQ_PCIE#5 GPP_B9/SRCCLKREQ4#
RC281 2 1 10K_0402_5% CLKREQ_PCIE#4 BE1
RC280 2 1 10K_0402_5% CLKREQ_PCIE#3 BE2 CLKOUT_PCIE_N_5
RC279 2 1 10K_0402_5% CLKREQ_PCIE#2 CLKREQ_PCIE#5 CF31 CLKOUT_PCIE_P_5 XCLK_BIASREF RC136 1 2 60.4_0402_1%
GPP_B10/SRCCLKREQ5#
WHL-U42_BGA1528
10 of 20
@
+3VALW_PRIM XCLK_BIASREF
+1.05V_VCCST T:50ohm S:12/15 L:1000 Via:2
2 EXT_PWR_GATE# 100K_0402_5% 1 2 RC295 2
PM_SLP_S0# 100K_0402_5% 1 2 RC296
From EC(open-drain)
1
RC113
1K_0402_5% PM_SLP_S3# 100K_0402_5% 1 2 RC297
PM_SLP_S4# 100K_0402_5% 1 2 RC298
RC116 PM_SLP_A# 100K_0402_5% 1 @ 2 RC299
2014MOW48:
62_0201_1% SLP_WLAN# 100K_0402_5% 1 @ 2 RC300 Skylake-U use 24M 50 ohm ESR
2
1 2 EC_VCCST_PG SLP_SUS# 100K_0402_5% 1 2 RC301 Cannonlake U use 38.4M 30 ohm ESR

<36,40> EC_VCCST_PG_R SLP_LAN# 1 2
100K_0402_5% RC302
#575412 WHL DG p274 SOC_RTCX2

change to 62 1% resistor INTEL WHL-U Schchecklist R0.9
11/26
UC1K SOC_RTCX1 1 2
RC98 10M_0402_5%
SYSTEM POWER MANAGEMENT BJ37 PM_SLP_S0#
PLT_RST# BJ35 GPP_B12/SLP_S0# BU36 PM_SLP_S3# PM_SLP_S0# <36,37>
<36,37> PLT_RST# SYS_RESET# CN10 GPP_B13/PLTRST# GPD4/SLP_S3# BU27 PM_SLP_S4# PM_SLP_S3# <36,40>
+3VALW_PRIM EC_RSMRST# BR36 SYS_RESET# GPD5/SLP_S4# BT29 PM_SLP_S5# PM_SLP_S4# <36,40>
<36> EC_RSMRST# @ T84 YC2
RSMRST# GPD10/SLP_S5# 1 2
+3VALW_DSW RC277 2 1 10K_0402_5% SYS_RESET# H_CPUPWRGD AR2 BU29 SLP_SUS#
T95 @ EC_VCCST_PG PROCPWRGD SLP_SUS# SLP_LAN# @ T90
BJ2 BT31 32.768KHZ_9PF_X1A000141000200
LAN_WAKE# VCCST_PWRGOOD SLP_LAN# SLP_WLAN# @ T87
RC278 2 1 10K_0402_5% BT30 Change PN to SJ10000Q400
T89 @ SYS_PWROK GPD9/SPL_WLAN# PM_SLP_A# @ T290
CR10 BU37 1 1
<36,40> SYS_PWROK PCH_PWROK_R SYS_PWROK GPD6/SLP_A# @ T291
1 2 BP31 CC15 CC16
PCH_PWROK <36,40> PCH_PWROK PCH_DPWROK PCH_PWROK PBTN_OUT#_R
RC275 2 1 10K_0402_5% RC20 BP30 BU28 6.8P_0402_50V8C 6.8P_0402_50V8C
10_0402_5% DSW_PWROK GPD3/PWRBTN# BU35 AC_PRESENT
EC_RSMRST# GPD1/ACPRESENT PM_BATLOW# AC_PRESENT <36> 2 2
RC276 2 1 10K_0402_5% SUSPWRDNACK BV34 BV36
<36> SUSPWRDNACK SUSACK# BY32 GPP_A13/SUSWARN#/SUSPWRDACK GPD0/BATLOW#
T92 @ GPP_A15/SUSACK#
WAKE# BU30 BR35 SM_INTRUDER#
RC110 2 1 10K_0402_5% SYS_PWROK LAN_WAKE# BU32 WAKE# INTRUDER#
3 BU34 GPD2/LAN_WAKE# CC37 EXT_PWR_GATE# 3
GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# SOC_VRALERT# @ T93
CC36
GPP_B2/VRALERT#
BT27 INPUT3VSEL +3VALW_DSW
INPUT3VSEL
PBTN_OUT#_R RC111
PCH
1
internal
@
PU
2 100K_0402_5%
+3VALW_DSW WHL-U42_BGA1528
AC_PRESENT RC106
EC1 internal
@
PU
2 10K_0402_5%
@ 11 of 20
RC104 1 2 1K_0402_5% WAKE#
#575412 WHL-U schchecklist R0.8 PM_BATLOW# RC103 1 2 10K_0402_5%

1 Kohm pull-up to VCCDSW_3p3.
The pull-up is required even if PCIe* interface
is not used on the plat f or m
.
+3VALW_PRIM
PCH PLTRST Buffer SOC_VRALERT# RC115

Default
2 @
: GPI
1 10K_0402_5%
ESD@ 1000P_0402_50V7K +3VS

2 1 CC131 EC_VCCST_PG
+3VALW_DSW
@ESD@ 5
CC51 2 1 .1U_0402_16V7K SYS_RESET# 2 @ 1 PBTN_OUT#_R PLT_RST# 2 P
<36> PBTN_OUT# B
1
RC109 0_0402_5% 4 PLT_RST_BUF#
1 Y PLT_RST_BUF# <21,30,31>
ESD@ 1000P_0402_50V7K
A
G
1
2 1 CC50 H_CPUPWRGD EC_RSMRST# 2 @ 1 PCH_DPWROK @ @ RC260
RC114 0_0402_5% UC3 RC118 4.7K_0402_5%
3
ESD@ MC74VHC1G08DFT2G_SC70-5 100K_0402_5%
2
CC66 2 1 .1U_0402_16V7K SYS_PWROK SYS_PWROK 2 @ 1 PCH_PWROK PLT_RST_BUF# INPUT3VSEL
RC122 0_0402_5% 1
2
1
ESD@ 1000P_0402_50V7K 2 @ 1
4 2 1 CC65 PCH_PWROK_R RC125 0_0402_5% CC130 #570990 CFL-U CRB R1.0 4
100P_0402_50V8J INPUT3VSEL RC261
2 ESD@ L : supply is 3.3V +- 5%
ESD@ H : supply is 3.0V +- 5% 4.7K_0402_5%
CC69 2 1 .1U_0402_16V7K EC_RSMRST#
2
Reserved for ESD place near UC2.1
#543016 PDG2.0 P.599

2018/12/27
Compal Secret Data
2019/12/27 Title
PROCPWRGD is used only for power sequence Issued Date Deciphered Date
debug and is not required to be connected to THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WHL-U(5/12)CLK,GPIO
anything on the plat f or m. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
A B C D E
A B C D E
+3VALW_PRIM
1
RC215
10K_0402_5%
UC1F WHL@
+3VS
2
TS_EN CC27
<28,36> TS_EN 2 1 CC32 GPP_B15/GSPI0_CS0# CN22 CPU_ID
PIRQA#
#575412 WHL-U schchecklist R0.8 RC135 10K_0402_5% CE28 GPP_A7/PIRQA#/GSPI0_CS1# GPP_D9/ISH_SPI_CS#/GSPI2_CS0# CR22 CPU_ID
GPP_B16/GSPI0_CLK GPP_D10/ISH_SPI_CLK/GSPI2_CLK
1
1 PIRQA# PU 8.2K~10K to +3.3VS GC6_FB_EN CE27 CM22 PROJECT_ID0 1
@ T111
GSPI0_MOSI CE29 GPP_B17/GSPI0_MISO ISH GPP_D11/ISH_SPI_MISO/GSPI2_MISO CP22 PROJECT_ID1 CPU_ID RC214
GPP_B18/GSPI0_MOSI GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI
CA31 CK22 WHL 1 10K_0402_5%
CML@
CA32 GPP_B19/GSPI1_CS0# GPP_D5/ISH_I2C0_SDA CH20
CML 0
2
CC29 GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PWR_EN# GPP_D6/ISH_I2C0_SCL
CC30 GPP_B20/GSPI1_CLK CH22
GSPI1_MOSI CA30 GPP_B21/GSPI1_MISO GPP_D7/ISH_I2C1_SDA CJ22
@ T112 GPP_B22/GSPI1_MOSI GPP_D8/ISH_I2C1_SCL
CNV_BRI_PRX_DTX CK20 +3VALW_PRIM
<31> CNV_BRI_PRX_DTX CNV_RGI_PTX_DRX CG19 GPP_F5/CNV_BRI_RSP CJ27 I2C_5_SDA
<31> CNV_RGI_PTX_DRX CNV_BRI_PTX_DRX GPP_F6/CNV_RGI_DT GPP_H10/I2C5_SDA/ISH_I2C2_SDA I2C_5_SCL T105 @
CJ20 CJ29
<31> CNV_BRI_PTX_DRX CNV_RGI_PRX_DTX CH19 GPP_F4/CNV_BRI_DT GPP_H11/I2C5_SCL/ISH_I2C2_SCL T106 @ no use PROJECT_ID0 RC207 2 15@ 1 10K_0402_5%
<31> CNV_RGI_PRX_DTX GPP_F7/CNV_RGI_RSP CM24 RAM_ID0 1 17@ 2 10K_0402_5%
RC210
GPP_D13/ISH_UART0_RXD CN23 RAM_ID1
UART_2_CRXD_DTXD CR12 GPP_D14/ISH_UART0_TXD CM23 RAM_ID2
<31> UART_2_CRXD_DTXD UART_2_CTXD_DRXD CP12 GPP_C20/UART2_RXD GPP_D15/ISH_UART0_RTS#/GSPI2_CS1# CR24 RAM_ID3 PROJECT_ID1 2 TARUS@1 10K_0402_5%
RC211
<31> UART_2_CTXD_DRXD UART_2_CRTS_DCTS CN12 GPP_C21/UART2_TXD GPP_D16/ISH_UART0_CTS#/SML0BALERT# 1 WLCML@2 10K_0402_5%
RC213
UART_2_CCTS_DRTS CM12 GPP_C22/UART2_RTS# CG12 DGPU_PWR_EN
GPP_C23/UART2_CTS# GPP_C12/UART1_RXD/ISH_UART1_RXD CH12 DGPU_HOLD_RST# DGPU_PWR_EN <22,40>
I2C_0_SDA CM11 I2C , UART GPP_C13/UART1_TXD/ISH_UART1_TXD CF12 DGPU_HOLD_RST# <21>
I2C_0_SCL CN11 GPP_C16/I2C0_SDA GPP_C14/UART1_RTS#/ISH_UART1_RTS# CG14
GPP_C17/I2C0_SCL GPP_C15/UART1_CTS#/ISH_UART1_CTS#
I2C_1_SDA CK12 BW35
<37> I2C_1_SDA I2C_1_SCL CJ12 GPP_C18/I2C1_SDA GPP_A18/ISH_GP0 BW34
<Touch PAD> <37> I2C_1_SCL GPP_C19/I2C1_SCL GPP_A19/ISH_GP1 CA37 G_INT# Project_ID1 Project_ID0
no use
I2C_2_SDA CF27 GPP_A20/ISH_GP2 CA36 TPM_PIRQ# G_INT# <33> Project ID
T135
T134
@
@
I2C_2_SCL CF29 GPP_H4/I2C2_SDA GPP_A21/ISH_GP3 CA35
TPM_PIRQ# <37> GPP_D12 GPP_D11
GPP_H5/I2C2_SCL GPP_A22/ISH_GP4 CA34
I2C_3_SDA CH27 GPP_A23/ISH_GP5 BW37 GPP_A12 * EH7LW/FH7LC 0 0
no use T131 @ I2C_3_SCL CH28 GPP_H6/I2C3_SDA GPP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF# T277 @
T130 @ GPP_H7/I2C3_SCL EH5LW/FH5LC 0 1
2 I2C_4_SDA CJ30 2
no use T128 @ I2C_4_SCL CJ31 GPP_H8/I2C4_SDA NA 1 0
T129 @ GPP_H9/I2C4_SCL
WHL-U42_BGA1528 FH5TW 1 1
@
6 of 20
+3VS
+1.8VALW_PRIM
1 2 UART_2_CRXD_DTXD
RC62 49.9K_0402_1%
1 2 UART_2_CTXD_DRXD RC2501 CNVI@ 2 20K_0402_1% CNV_BRI_PRX_DTX
RC63 49.9K_0402_1%
1 @ 2 UART_2_CRTS_DCTS RC2511 CNVI@ 2 20K_0402_1% CNV_RGI_PRX_DTX Memory Down Strap
RC64 49.9K_0402_1%
1 @ 2 UART_2_CCTS_DRTS #570990 CFL U ORB R1.0 p.114 +3VALW_PRIM
PU 20K
RC65 49.9K_0402_1%
1
+3VS
+1.8VALW_PRIM Voltage level – 1.8V only RC151 RC150 RC153 RC224
M.2 CNV Mode Select 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% +1.8VS_3VS_PGPPA +1.8VS
+3VALW_PRIM NODX76@ NODX76@ NODX76@ NODX76@
2
RAM_ID0 RC177
RC252 2 1 20K_0402_5% CNV_RGI_PTX_DRX RAM_ID1 0_0402_5%2 ESPI@ 1
+3VS RAM_ID2
STRAP RAM_ID3
RC126 1 @ 2 1K_0402_5% I2C_0_SDA RC253 2 1 4.7K_0402_5% 2 1
1
RC127 1 @ 2 1K_0402_5% I2C_0_SCL @
RC155 RC225 RC226 RC227 RC178 0_0402_5%
RC128 1 2 2.2K_0402_5% I2C_1_SDA An external pull-up or pull-down is required. 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
3 RC129 1 2 2.2K_0402_5% I2C_1_SCL 0 = Integrated CNVi enable.
@ @ @ @ 3
1 = Integrated CNVi disable.
2
Note: When a RF companion chip is connected to the
PCH CNVi interface, the device internal pulldown
resistor will pull the strap load to enable
CNVi interface.
+3VS
DGPU_PWR_EN RC231 1 VGA@ 2 10K_0402_5%
DGPU_HOLD_RST# RC219 1 VGA@ 2 10K_0402_5%
GC6_FB_EN 2 @ 1 GC6_FB_EN3V3
GC6_FB_EN3V3 <21>
RC195 0_0402_5%
Functional Strap Definitions
GSPI0_MOSI /GPP_B18 (Internal Pull Down):
(Rising edge of PCH_PWROK)
RAM_ID3 RAM_ID2 *RAM_ID1 *RAM_ID0 PartNumber - Description
No Reboot ZZZ1 Hynix4GB
X76DHYN@ X76829BOL04 Hynix 4GB SA0000BMN30 (S IC D4 512M16 H5AN8G6NCJR-VKC FBGA ABO!)
0 0 0 0
* 0 = Disable No Reboot mode. --> AAX05 Use ZZZ2
X76DMIC@
Micron4GB
X76829BOL05
Micron 4GB 0 0 0 1 SA0000ARD60 (S IC D4 8G/2666 MT40A512M16LY-075:E ABO!)
1 = Enable No Reboot Mode. (PCH will disable the TCO Samsung 4GB SA0000B6F00 (S IC D4 512M16 K4A8G165WC-BCTD FBGA 96P)
0 0 1 0
4
Timer system reboot feature). This function is useful ZZZ3 Samsung4GB 4
X76DSAM@ X76829BOL06
when running ITP/XDP. 0 0 1 1
No OnBoard No On Board Memory
Memory 1 1 1 1
GSPI1_MOSI / GPP_B22 (Internal Pull Down):
(Rising edge of PCH_PWROK)
Boot BIOS Strap Bit Issued Date 2018/12/27 Deciphered Date 2019/12/27 Title
* 0 = SPI Mode --> AAX05 Use THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WHL-U(6/12)GPIO
Size Document Number R ev
1 = LPC Mode AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A B C D E
A B C D E
UC1H
CB5
PCIE_CRX_GTX_N1 PCIE1_RXN/USB31_1_RXN USB3_CRX_DTX_N1 <35>
BW9 CB6
<21> PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P1 PCIE5_RXN/USB31_5_RXN PCIE1_RXP/USB31_1_RXP USB3_CRX_DTX_P1 <35>
BW8 CA4 USB3 MB (Front&Charging)
1 <21> PCIE_CRX_GTX_P1 PCIE_CTX_GRX_N1 PCIE5_RXP/USB31_5_RXP PCIE1_TXN/USB31_1_TXN USB3_CTX_DRX_N1 <35> 1
CC17 VGA@1 2 0.22U_0402_16V7K BW4 PCIE / USB3.1 / SATA CA3
<21> PCIE_CTX_C_GRX_N1 PCIE_CTX_GRX_P1 PCIE5_TXN/USB31_5_TXN PCIE1_TXP/USB31_1_TXP USB3_CTX_DRX_P1 <35>
CC21 VGA@1 2 0.22U_0402_16V7K BW3
<21> PCIE_CTX_C_GRX_P1 PCIE5_TXP/USB31_5_TXP BY8
PCIE_CRX_GTX_N2 PCIE2_RXN/USB31_2_RXN/SSIC_1_RXN USB3_CRX_DTX_N2 <34>
BU6 BY9
<21> PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P2 PCIE6_RXN/USB31_6_RXN PCIE2_RXP/USB31_2_RXP/SSIC_1_RXP USB3_CRX_DTX_P2 <34>
BU5 CA2 USB3 MB
<21> PCIE_CRX_GTX_P2 PCIE_CTX_GRX_N2 PCIE6_RXP/USB31_6_RXP PCIE2_TXN/USB31_2_TXN/SSIC_1_TXN USB3_CTX_DRX_N2 <34>
CC18 VGA@1 2 0.22U_0402_16V7K BU4 CA1
<21> PCIE_CTX_C_GRX_N2 PCIE_CTX_GRX_P2 PCIE6_TXN/USB31_6_TXN PCIE2_TXP/USB31_2_TXP/SSIC_1_TXP USB3_CTX_DRX_P2 <34>
CC19 VGA@1 2 0.22U_0402_16V7K BU3
<21> PCIE_CTX_C_GRX_P2 PCIE6_TXP/USB31_6_TXP
DGPU BY7
PCIE_CRX_GTX_N3 BT7 PCIE3_RXN/USB31_3_RXN BY6
<21> PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P3 PCIE7_RXN PCIE3_RXP/USB31_3_RXP
BT6 BY4
<21> PCIE_CRX_GTX_P3 PCIE_CTX_GRX_N3 PCIE7_RXP PCIE3_TXN/USB31_3_TXN
CC20 VGA@1 2 0.22U_0402_16V7K BU2 BY3
<21> PCIE_CTX_C_GRX_N3 2 0.22U_0402_16V7K PCIE_CTX_GRX_P3 BU1 PCIE7_TXN PCIE3_TXP/USB31_3_TXP
CC22 VGA@1
<21> PCIE_CTX_C_GRX_P3 PCIE7_TXP BW6
PCIE_CRX_GTX_N4 BU9 PCIE4_RXN/USB31_4_RXN BW5
11/28 <21> PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P4 BU8 PCIE8_RXN PCIE4_RXP/USB31_4_RXP BW2
For layout routing <21> PCIE_CRX_GTX_P4
CC23 VGA@1 2 0.22U_0402_16V7K PCIE_CTX_GRX_N4 BT4 PCIE8_RXP PCIE4_TXN/USB31_4_TXN BW1
PCIE P5/P6 exchange <21> PCIE_CTX_C_GRX_N4 2 0.22U_0402_16V7K PCIE_CTX_GRX_P4 BT3 PCIE8_TXN PCIE4_TXP/USB31_4_TXP
CC24 VGA@1
<21> PCIE_CTX_C_GRX_P4 PCIE8_TXP CE3 USB20_N1
PCIE_CRX_DTX_N5 BP5 USB2_1N CE4 USB20_P1 USB20_N1 <35>
<31> PCIE_CRX_DTX_N5 PCIE_CRX_DTX_P5 BP6 PCIE9_RXN USB2_1P USB20_P1 <35> USB3 MB (Front&Charging)
<31> PCIE_CRX_DTX_P5 CC25 2 1 .1U_0402_16V7K PCIE_CTX_DRX_N5 BR2 PCIE9_RXP USB2.0 CE1 USB20_N2
<31> PCIE_CTX_C_DRX_N5 PCIE_CTX_DRX_P5 PCIE9_TXN USB2_2N USB20_P2 USB20_N2 <34>
NGFF WLAN+BT(Key E) CC26 2 1 .1U_0402_16V7K BR1 CE2 USB3 MB
<31> PCIE_CTX_C_DRX_P5 PCIE9_TXP USB2_2P USB20_P2 <34>
PCIE_CRX_DTX_N6 BN6 CG3 USB20_N3
<30> PCIE_CRX_DTX_N6 PCIE_CRX_DTX_P6 BN5 PCIE10_RXN USB2_3N CG4 USB20_P3 USB20_N3 <28>
<30> PCIE_CRX_DTX_P6 1 2 .1U_0402_16V7K PCIE_CTX_DRX_N6 BR4 PCIE10_RXP USB2_3P USB20_P3 <28> TS
GLAN <30> PCIE_CTX_C_DRX_N6
CC60
PCIE_CTX_DRX_P6 PCIE10_TXN USB20_N4
CC62 1 2 .1U_0402_16V7K BR3 CD3
<30> PCIE_CTX_C_DRX_P6 PCIE10_TXP USB2_4N CD4 USB20_P4 USB20_N4 <38>
BN10 USB2_4P USB20_P4 <38> TO D/B USB2
<33> SATA_CRX_DTX_N0 BN8 PCIE11_RXN/SATA0_RXN CG5 USB20_N5
<33> SATA_CRX_DTX_P0 BN4 PCIE11_RXP/SATA0_RXP USB2_5N CG6 USB20_P5 USB20_N5 <37>
HDD <33> SATA_CTX_DRX_N0 PCIE11_TXN/SATA0_TXN USB2_5P USB20_P5 <37> FP
BN3
2 <33> SATA_CTX_DRX_P0 PCIE11_TXP/SATA0_TXP CC1 USB20_N6 2
BL6 USB2_6N CC2 USB20_P6 USB20_N6 <38>
<33> SATA_CRX_DTX_N1 BL5 PCIE12_RXN/SATA1A_RXN USB2_6P USB20_P6 <38> Card reader(Reserved)
<33> SATA_CRX_DTX_P1 BN2 PCIE12_RXP/SATA1A_RXP CG8 USB20_N7
ODD <33> SATA_CTX_DRX_N1 PCIE12_TXN/SATA1A_TXN USB2_7N USB20_P7 USB20_N7 <28>
BN1 CG9
<33> SATA_CTX_DRX_P1 PCIE12_TXP/SATA1A_TXP USB2_7P USB20_P7 <28> Camera
BK6 CB8
<31> PCIE_CRX_DTX_N9 BK5 PCIE13_RXN USB2_8N CB9
<31> PCIE_CRX_DTX_P9 BM4 PCIE13_RXP USB2_8P
<31> PCIE_CTX_DRX_N9 BM3 PCIE13_TXN CH5
* CML Base not support
<31> PCIE_CTX_DRX_P9 PCIE13_TXP USB2_9N CH6
BJ6 USB2_9P
<31> PCIE_CRX_DTX_N10 BJ5 PCIE14_RXN CC3 USB20_N10
<31> PCIE_CRX_DTX_P10 BL2 PCIE14_RXP USB2_10N CC4 USB20_P10 USB20_N10 <31>
<31> PCIE_CTX_DRX_N10 BL1 PCIE14_TXN USB2_10P USB20_P10 <31> BT #571906 change to USB port10 for CNVi
<31> PCIE_CTX_DRX_P10 PCIE14_TXP CC5 USB2_COMP RC119 1 2 113_0402_1%
BG5 USB2_COMP CE8 USB2_ID RC130 1 @ 2 0_0402_5%
<31> PCIE_CRX_DTX_N11 BG6 PCIE15_RXN/SATA1B_RXN USB2_ID CC6 USB2_VBUSSENSE 1 2 0_0402_5%
NGFF SSD(Key M) <31> PCIE_CRX_DTX_P11 PCIE15_RXP/SATA1B_RXP USB2_VBUSSENSE
RC131 @
BL4 USB2_ID, USB2_VBUSSENSE
<31> PCIE_CTX_DRX_N11 BL3 PCIE15_TXN/SATA1B_TXN CK6 USB_OC0#
(Need Lane Reversal) <31> PCIE_CTX_DRX_P11 PCIE15_TXP/SATA1B_TXP GPP_E9/USB2_OC0#/GP_BSSB_CLK USB_OC1# USB_OC0# <35> INTEL_Calvin recommend reserving the PD resisters
CK5
BE5 GPP_E10/USB2_OC1#/GP_BSSB_DI CK8 USB_OC2#
<31> PCIE_CRX_DTX_N12 BE6 PCIE16_RXN/SATA2_RXN GPP_E11/USB2_OC2# CK9 USB_OC3# Unused OC pin need set to GPI.
<31> PCIE_CRX_DTX_P12 BJ4 PCIE16_RXP/SATA2_RXP GPP_E12/USB2_OC3#
<31> PCIE_CTX_DRX_N12 BJ3 PCIE16_TXN/SATA2_TXN CP8
<31> PCIE_CTX_DRX_P12 PCIE16_TXP/SATA2_TXP GPP_E4/DEVSLP0 CR8
RC1201 2 100_0402_1% PCIE_RCOMPN CE6 GPP_E5/DEVSLP1 CM8 SSD_DEVSLP2
PCIE_RCOMPP PCIE_RCOMP_N GPP_E6/DEVSLP2 SSD_DEVSLP2 <31> +3VALW_PRIM
CE5
* CML Base not support SATA funct i on PCIE_RCOMP_P CN8 GPP_E0
GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1 @ T278
CR28 CM10
#575412 p.46 CP28 GPP_H12/M2_SKT2_CFG_0 GPP_E1/SATAXPCIE1/SATAGP1 CP10 SATAXPCIE2
@ T279
PCIE_RCOMPN/PCIE_RCOMPP CN28 GPP_H13/M2_SKT2_CFG_1 GPP_E2/SATAXPCIE2/SATAGP2 SATAXPCIE2 <31>
3 R=100ohm CM28 GPP_H14/M2_SKT2_CFG_2 CN7 1 2 3
GPP_H15/M2_SKT2_CFG_3 GPP_E8/SATALED#/SPI1_CS1# +3VS
AR3 RH16
RSVD_69 10K_0402_5%
WHL-U42_BGA1528 M.2 SSD PCIE/SATA select pin USB_OC3# RC283 2 1 10K_0402_5%
USB_OC2# RC284 2 1 10K_0402_5%
@
8 of 20
SSD_DET# (SATA_GP0) USB_OC1# RC285 2 1 10K_0402_5%
SATA Device 0 USB_OC0# RC286 2 1 10K_0402_5%
0.1U_0201_10V6K
ESD@ CC321
PCIE Device 1 1
GPIO DEVICE CONTROL
For MB field lesson learnt
USB_OC0# USB2 Port 1 2
USB_OC1# NA
USB_OC2# NA DEVSLP[2:0] Implementation
DEVSLP is a host-controlled hardware signal which enables a SATA host and device to
USB_OC3# NA enter an ultra-low interface power state, including the possibility to completely power
DEVSLP0 NA down host and device PHYs.
The processor provides three SATA DEVSLP signals, DEVSLP[2:0] for SKL U.
DEVSLP1 NA ‧When hi gh, DEVSLP reWuests t he SATA devi ce t o ent er i nt o t he DEVSLP po wer st at e.
‧When l o w
, DEVSLP reWuests t he SATA devi ce t o eWit f r o mt he DEVSLP po wer st at e
DEVSLP2 NA and transition to active state.
SATA_GP0 NA
SATA General Purpose (SATAGP[2:0]) Signals
SATA_GP1 NA ‧The pr ocess or provi des t hree SATA general pur pose i nput si gnal s, SATAGP[ 2: 0] f or S KL U.
4 These signals can be configured as interlock switch inputs corresponding to a given SATA port. 4
SATA_GP2 NA ‧When used as an i nt erl oc k s wit c h st at us i ndi cati on, t hi s si gnal s houl d be dri ven t o 0
to indicate that the switch is closed and to a 1 to indicate that the switch is open.
‧If mec hani cal presence s wit c hes will not be used on t he pl atf or m , SATAGP[ 2: 0]
signals can be configured as GPP_E[2:0] GPIOs signals.
2018/12/27
Compal Secret Data
2019/12/27 Title
WHL-U(7/12)PCIE,USB,SATA
A B C D E
A B C D E
+1.2V_VDDQ
+VCCIO
+1.05VALW_PRIM TO +1.05V_VCCSTU / +1.05VCCST UC1N
AK24
+5VALW +1.05VALW_PRIM +1.05V_VCCSTU 3.3A AD36
CPU POWER 3 OF 4 VCCIO1 AK26
AH32 VDDQ1 VCCIO2 AL24
4.066A
AH36 VDDQ2 VCCIO3 AL25
AM36 VDDQ3 VCCIO4 AL26
AN32 VDDQ4 VCCIO5 AL27
1 1 VDDQ5 VCCIO6
1U_0201_6.3V6M
1U_0201_6.3V6M
CC98
CC97
1 AW32 AM25
AY36 VDDQ6 VCCIO7 AM27
CC96 BE32 VDDQ7 VCCIO8 BH24
2 2 0.1U_0201_10V6K BH36 VDDQ8 VCCIO9 BH25
2 R32 VDDQ9 VCCIO10 BH26
Y36 VDDQ10 VCCIO11 BH27
1 UC5 VDDQ11 VCCIO12 BJ24 1
CC105 2 1 .1U_0402_16V7K 1 14 VCCIO13 BJ26
2 VIN1 VOUT1 13 VCCIO14 BP16
VIN1 VOUT1 BC28 VCCIO15 BP18
RC142 1 2 20K_0402_5% EN_1.0V_VCCSTU 3 12 1 2 RSVD1 VCCIO16
<36,40,45> SYSON ON1 CT1 CC95
0.06A BP11 BG8
+1.05V_VCCST VCCST1 VCCSA2 +VCC_SA
4 11 1000P_0402_50V7K BP2 BG10
VBIAS GND VCCST2 VCCSA1 BH9
RC168 1 2 49.9K_0402_1% EN_1.8VS 5 10 1 2 VCCSA3 BJ8
0~1.52V
<36,40,43,45> SUSP# ON2 CT2 CC94
0.02A BG1 VCCSA5 BJ9 6A
+1.05VS_VCCSTG VCCSTG1 VCCSA6
2 1 CC104 6 9 1000P_0402_50V7K BG2 BJ10
.1U_0402_16V7K +1.8VALW_VS 7 VIN2 VOUT2 8 VCCSTG2 VCCSA4 BK8
VIN2 VOUT2 +1.8VS 0.12A BL27 VCCSA9 BK25
+1.2V_VCCPLL_OC VCCPLL_OC1 VCCSA7
15 BM26 BK27
1 2 GPAD VCCPLL_OC2 VCCSA8 BL8
+1.8VALW_PRIM 1 2 AOZ1331DI_DFN14_2X3
0.13A BR11 VCCSA13 BL9
+1.05V_VCCSFR VCCPLL1 VCCSA14
JPC8 1 1 BT11 BL10
VCCPLL2 VCCSA10
1U_0201_6.3V6M
CC99
JUMP_43X39 BL24
@ CC100 VCCSA11 BL26
0.1U_0201_10V6K VCCSA12 BM24
2
+1.8VALW_PRIM TO +1.8VS 2 VCCSA15
VCCSA16
BN25
BP28 VCCIO_SENSE
VCCIO_SENSE VSSIO_SENSE T124 @
BP29 T125 @
VSSIO_SENSE
BE7 VSSSA_SENSE
+1.05VALW_PRIM TO +1.05VS_VCCSTG VSSSA_SENSE
VCCSA_SENSE
BG7 VCCSA_SENSE VSSSA_SENSE <48>
VCCSA_SENSE <48>
+1.05VALW_PRIM WHL-U42_BGA1528
+1.05VALW_PRIM_JP
@
JPC4 14 of 20
1 2
2 1 2 +1.05VS_VCCSTG 2
Imax : 3.44 AJUMP_43X79 1 NC10@
+1.05V_VCCSTU +1.05V_VCCST
1U_0201_6.3V6M
CC117
@ RC462 1 2 0_0402_5%
For Power consumption UC6
Measurement 1 CC322 1 2 10U_0402_6.3V6M reserve for ripple
2 2 VIN1 +VCCIO
+5VALW VIN2 @ JPC5 PSC Side
CC107 @ 7 6 +1.05VS_VCCSTG_IO 1 2
0.19A
#575412_WHL_U_PDG_R0.7 table11-2
VIN thermal VOUT 1 2
0.1U_0201_10V6K
2 1 3 JUMP_43X79 Imax : 4.066A
2
RC140
@ 1
0_0402_5%
CC48 1 2 1U_0201_6.3V6M +1.05V_VCCST : 1x 1uF
VBIAS 1
RC188
SUSP# 1 2 SUSP#_R1 4 5 CC127 +1.05V_VCCSFR
0_0402_5% ON GND 0.1U_0201_10V6K
2 CC323 1 2 10U_0402_6.3V6M reserve for ripple
1
1U_0201_6.3V6M
CC106
RC465 AOZ1334DI-02_DFN8-7_3X3
S0_C10_GATE# 1 2 PSC Side
Rds_on 3.6m ohm #575962 WHL_DDR4_RVP_SCH R0.7
2
0_0402_5% Rise time 0.5ms 2 @ 1 CC55 1 2 1U_0201_6.3V6M +1.05V_VCCSFR : 1x 1uF
@ RC143 0_0402_5%
+1.2V_VDDQ +1.2V_VCCPLL_OC PSC Side
#575962 WHL_DDR4_RVP_SCH R0.7
+VCCIO : #575412_WHL_U_PDG_R0.7 table11-2
#575412_WHL_U_PDG_R0.7 table11-2 RC464 1 2 0_0402_5% CC49 1 2 1U_0201_6.3V6M +1.2V_VCCSFR_OC: 1x 1uF
8 x 1uF +VCCIO +1.2V_VDDQ_CPU:
2 x 10uF PSC Side BSC Side 9 x 10uF 0402 NC10@
PSC Side
1 x 22uF 0603 CC56 1 2 1U_0201_6.3V6M #575412_WHL_U_PDG_R0.7 table11-2
+1.05VS_VCCSTG
4 x 1uF 0402 +1.05V_VCCSTG : 1x 1uF
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
+1.2V_VDDQ
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1 PSC Side BSC Side

1
1
CC58
CC150
3 3
CC151
CC152
CC27
CC28
CC33
CC34
CC35
CC36
2
2 2 2 2 2 2 2 2 +1.05V_VCCSFR 12/6
22U_0603_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 2
1
1
CC37
CC149
CC148
CC147
CC146
CC38
CC39
CC40
CC42
CC145
CC43
CC44
CC45
CC46
CC329
22U_0603_6.3V6M
2
2
2 2 2 2 2 1
@
reserve for ripple
+1.2V TO +VCCPLL_OC
CPU C10 Save Power +5VALW +1.2V_VDDQ
I(Max) : 120m A(+VCCPLL_OC)

+1.05VALW TO +1.05VS_VCCSTG RON(Max) : 6.2 mohm
0.1U_0201_10V6K
1U_0201_6.3V6M
+3VALW 1 V drop : 0.019 V
1
CC178
CC177
CC176
UC9 C10@ 0.1U_0201_10V6K UC10 C10@
CPU_C10_GATE# 1 6 1 2 C10@ C10@ 1 +1.2V_VCCPLL_OC
2
+5VALW +1.05VALW_PRIM <10> CPU_C10_GATE# A VCC 2 2 VIN1
I(Max) : 20m A(+1.05VS_VCCSTG) C10@
VIN2
RON(Max) : 6.2 mohm SUSP# 2 5 RC460
B NC 7 6 +VCCPLL_OC_R 1 2
V drop : 0.019 V 3 4 S0_C10_GATE# VIN thermal VOUT
GND Y 1
+1.05VS_VCCSTG
0.1U_0201_10V6K
1U_0201_6.3V6M
1 3 0_0402_5%
VBIAS
1
CC174
4 74LVC1G08FZ4-7_X2-DFN1410-6 CC179 4
S0_C10_GATE# 4 C10@
CC175
UC8 @ 5 C10@ 0.1U_0201_10V6K

C10@ 1 ON GND 2
2
2 2 VIN1
VIN2 RC459 RC457 1 @ 2 0_0402_5% TPS22961DNYR_WSON8
7 6 +1.05VS_VCCSTG_R 1 2
C10@ VIN thermal VOUT
1
3 0_0402_5%
S0_C10_GATE# 4
VBIAS
5
C10@ CC180 C10@ Security Classification
2018/12/27
Compal Secret Data
2019/12/27 Title
ON GND 0.1U_0201_10V6K Issued Date Deciphered Date
2
WHL-U(8/12)Power
TPS22961DNYR_WSON8 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
A B C D E
A B C D E
+1.05VALW_PRIM +1.05VALW_MPHY UC1P

CPU POWER 4 OF 4
BP20 CB16
RC243 1 @ 2 0_0603_5% 1 2 CC136
Close to BV12 +1.05VALW_PRIM
BW16 VCCPRIM_1P05_1 VCCPRIM_3P3_3 +3VALW_PRIM
22U_0603_6.3V6M
2.104A BW18 VCCPRIM_1P05_9
BW19 VCCPRIM_1P05_10
BY16 VCCPRIM_1P05_11 BR23
VCCPRIM_1P05_12 VCCRTC +RTCVCC
+1.05VALW_MPHYPLL CA14
VCCPRIM_1P05_14 BY20
0.002A
Add 1 cap for downsize +1.05VALW_PRIM
+1.05VALW_PRIM 1 2 CC328 CC15 VCCPRIM_1P05_13 BP24
+1.8VALW_PRIM VCCPRIM_1P8_1 DCPRTC +DCPRTC Intenal VRM
2.2uH DCR:0.3 ohm Rated 750mA 1U_0201_6.3V6M CD15
LC1 0.702A CD16 VCCPRIM_1P8_4
1 2 1 2 CC135
Close to BV2 CP17 VCCPRIM_1P8_5 BR20 2.2uH DCR:0.3 ohm Rated 750mA
1 1U_0201_6.3V6M VCCPRIM_1P8_8 VCCPRIM_1P05_3 +1.05VALW_PRIM +VCCA_XTAL_1.05V 1
CB22 BT12 LC2
2.2UH_CPI160809UF-2R2M-0A7_20% +3VALW_PRIM
#575412_WHL_U_PDG_R0.7 table11-12 1 2 CC320 #575412_WHL_U_PDG_R0.7 table11-12 CB23 VCCPRIM_3P3_4 VCCAPLL_1P05_3 1 2
Add inductor 2.2uH DCR 0.33 ohm +/- 30% rated 100mA 47U_0603_6.3V6M Add 47uF @ 0.207A CC22 VCCPRIM_3P3_5 BP14
1 2 CC324 CC23 VCCPRIM_3P3_6 VCCA_BCLK_1P05 2.2UH_CPI160809UF-2R2M-0A7_20%
VCCPRIM_3P3_7
47U_0603_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
47U_0603_6.3V6M
@ 47U_0603_6.3V6M CD22 BR14 #575412_WHL_U_PDG_R0.7 table11-12 1 1
VCCPRIM_3P3_8 VCCAPLL_1P05_1
1
Add inductor 2.2uH DCR 0.33 ohm +/- 30% rated 100mA
CC319
CC325
CD23
+3VALW +3VALW_DSW CP29 VCCPRIM_3P3_9 @ CC86 CC326 <BOM Structure>
VCCPRIM_3P3_10 BU12
2
BU15 VCCA_SRC_1P05 #575412_WHL_U_PDG_R0.7 table11-12 2 2
2 @ 1 1 2 CC137
Close to BR24 +1.05VALW_PRIM
BU22 VCCPRIM_CORE1 CP5 Add 47uF @
4.26A VCCPRIM_CORE2 VCCA_XTAL_1P05 +VCCA_XTAL_1.05V
@
RC173 0_0402_5% 1U_0201_6.3V6M BV15

BV16 VCCPRIM_CORE3 BY24
BV18 VCCPRIM_CORE4 VCCDPHY_1P24_2 CA24
Close to CP5
BV19 VCCPRIM_CORE5 VCCDPHY_1P24_4
Add 1 cap for downsize
BV20 VCCPRIM_CORE6 BY23
+3VALW_PRIM +3VALW_HDA BV22 VCCPRIM_CORE7 VCCDPHY_1P24_1 CA23
BW20 VCCPRIM_CORE8 VCCDPHY_1P24_3 CP25 +DCPRTC
BW22 VCCPRIM_CORE9 VCCDPHY_1P24_5 +VCCDPHY_1.24V Intenal VRM
2 @ 1 1 2 CC63 CA12 VCCPRIM_CORE10 BT23
VCCPRIM_CORE11 VCCDSW_3P3_2 +3VALW_DSW
RC198 0_0402_5% 1U_0201_6.3V6M CA16
VCCPRIM_CORE12
@
CA18 BR12
VCCPRIM_CORE13 VCCA_19P2_1P05 +1.05VALW_PRIM
+3VALW_SPI CA19 2
CA20 VCCPRIM_CORE14
CB12 VCCPRIM_CORE15 CC71
2 @ 1 CB14 VCCPRIM_CORE16 @
VCCPRIM_CORE17 0.1U_0201_10V6K
RC154 0_0402_5% CB15 CC18 1
VCCPRIM_CORE18 VCCPRIM_1P8_2 +1.8VALW_PRIM
CC19
BT24 VCCPRIM_1P8_3 CD18
Close to BP24
Intenal VRM +VCCDSW_1P05 VCCDSW_1P05 VCCPRIM_1P8_6 CD19
BU14 VCCPRIM_1P8_7 CP23
+1.05VALW_PRIM VCCAPLL_1P05_4 VCCPRIM_1P8_9 +1.8VALW_PRIM
2 BV12 BW23 2
+1.05VALW_MPHY VCCPRIM_MPHY_1P05_1 VCCPRIM_3P3_2 +3VALW_PRIM
BW12
+1.05VALW_PRIM +3VALW_PRIM 2.878A BW14 VCCPRIM_MPHY_1P05_3
BY12 VCCPRIM_MPHY_1P05_4
BY14 VCCPRIM_MPHY_1P05_5 BP23
VCCPRIM_MPHY_1P05_6 VCCPRIM_3P3_1 1 1
1U_0201_6.3V6M
1U_0201_6.3V6M
PRIMCORE_VID0
@
BV2 CB36 CC72 CC144
2 2 2 1 +1.05VALW_MPHYPLL VCCAMPHYPLL_1P05 GPP_B0/CORE_VID0 PRIMCORE_VID1 T136 @
CC138 CC327 CB35 T138 @ 1U_0201_6.3V6M 1U_0201_6.3V6M
CC139 CC140 BR15 GPP_B1/CORE_VID1 2 2
1U_0201_6.3V6M 0.1U_0201_10V6K VCCAPLL_1P05_2
1 1 1 2 CC12
Close to CP23 Close to CP17
@
@ VCCDUSB_1P05
BR24
Close to BP20 Close to CP29 +3VALW_DSW VCCDSW_3P3_1
0.004A BT20
Add 1 cap for downsize +3VALW_HDA VCCHDA
BV23
+3VALW_SPI VCCSPI
BT18
BT19 VCCPRIM_1P05_4
BU18 VCCPRIM_1P05_5
+1.05VALW_PRIM +VCCDSW_1P05 BU19 VCCPRIM_1P05_7 +VCCDPHY_1.24V
VCCPRIM_1P05_8
BT22
BP22 VCCPRIM_1P05_6
VCCPRIM_1P05_2
1 1 2
CC141 CC134 BV14
+1.05VALW_MPHY VCCPRIM_MPHY_1P05_2
@
1U_0201_6.3V6M 1U_0201_6.3V6M CC142

WHL-U42_BGA1528 4.7U_0402_6.3V6M
2 2 16 of 20 1
@
Close to BV18 Close to BT24 Close to CP25

3 3
UC1O
RESERVED SIGNALS
K12 AA24
K14 RSVD48 RSVD38 AA26
K15 RSVD49 RSVD39 AB25
K17 RSVD50 RSVD40 AC24
L25 RSVD53 RSVD43 AD24
M24 RSVD54 RSVD44 AD26
M26 RSVD55 RSVD45 V25
P24 RSVD56 RSVD46 T25
+3VALW +3VALW_PRIM P26 RSVD57 RSVD47
JPC7 R24 RSVD58
1 2 R25 RSVD59
1 2 R26 RSVD60
JUMP_43X39 RSVD61
@
W25
RTC Battery
V24 RSVD62
Y25 RSVD63 +RTCBATT
Y24 RSVD64 RH163 +RTCBATT
RSVD65 1K_0402_5% DC1 +RTCVCC
1 2 3 JRTC1
#543016 PDG2.0 P.470 1
VCCRTC does not exceed 3.2 V. WHL-U42_BGA1528 1 2 1
2
@ 1 1
15 of 20 2 3
+CHGRTC CC143 GND
CC84 4
Power Rail Voltage VCCOPC and VCCEOPIO for CFL U43e only 0.1U_0201_10V6K 1U_0201_6.3V6M GND
4 CHN202UPT_SC70-3 2 2 4
ACES_50271-0020N-001
+CHGRTC 3.383V(MAX) CONN@
#575412_WHL_U_PDG_R0.7 table11-11
Close to BR23 SP02000RO00
BAT54C(VF) 240 mV
+RTCVCC 3.143V Security Classification

2018/12/27
Compal Secret Data
2019/12/27 Title
Result : Pass WHL-U(9/12)Power
A B C D E
A B C D E
+VCC_CORE +VCC_CORE +VCC_GT +VCC_GT
UC1L UC1M
0~1.52V
31A
AN9
CPU POWER 1 OF 4
AW24
0~1.52V A5
CPU POWER 2 OF 4
D15
AN10 VCCCORE5 VCCCORE35 AW25 70A A6 VCCGT8 VCCGT58 D17
AN24 VCCCORE1 VCCCORE36 AW26 +VCC_CORE A8 VCCGT9 VCCGT59 D18
AN26 VCCCORE2 VCCCORE37 AW27 A11 VCCGT10 VCCGT60 D20
AN27 VCCCORE3 VCCCORE38 AY24 A12 VCCGT1 VCCGT61 E4
AP2 VCCCORE4 VCCCORE44 AY26 A14 VCCGT2 VCCGT64 F5
1 AP9 VCCCORE6 VCCCORE45 BA5 A15 VCCGT3 VCCGT69 F6 1
AP24 VCCCORE9 VCCCORE48 BA7 A17 VCCGT4 VCCGT70 F7
AP26 VCCCORE7 VCCCORE49 BA8 A18 VCCGT5 VCCGT71 F8
AR5 VCCCORE8 VCCCORE50 BA25 A20 VCCGT6 VCCGT72 F11
AR6 VCCCORE13 VCCCORE46 BA27 VCCGT7 VCCGT65 F14
AR7 VCCCORE14 VCCCORE47 BB2 AA9 ES1/ES2 VCCGT66 F17
AR8 VCCCORE15 VCCCORE51 BB26 AB2 VCCGT11/VCCCORE75 VCCGT67 F20
AR10 VCCCORE16 VCCCORE52 BC5 AB8 VCCGT13/VCCCORE76 VCCGT68 G11
AT9 VCCCORE12 VCCCORE58 BC9 AC8 VCCGT12/VCCCORE79 VCCGT75 G15
AT24 VCCCORE19 VCCCORE59 BC10 AD9 VCCGT16/VCCCORE80 VCCGT76 G17
AT26 VCCCORE17 VCCCORE53 BC26 AE8 VCCGT17/VCCCORE81 VCCGT77 G18
AU5 VCCCORE18 VCCCORE54 BC27 AE9 VCCGT19/VCCCORE82 VCCGT78 G20
AU6 VCCCORE24 VCCCORE55 BD5 AE10 VCCGT20/VCCCORE83 VCCGT79 H5
AU7 VCCCORE25 VCCCORE63 BD8 AF2 VCCGT18/VCCCORE84 VCCGT87 H6
AU24 VCCCORE28 VCCCORE61 BD27 AG8 VCCGT21/VCCCORE87 VCCGT90 H11
AU25 VCCCORE20 VCCCORE62 BE9 AG9 VCCGT24/VCCCORE88 VCCGT80 H12
AU26 VCCCORE21 VCCCORE69 BE24 AH9 VCCGT25/VCCCORE89 VCCGT81 H14
AU27 VCCCORE22 VCCCORE65 BE25 AJ8 VCCGT26/VCCCORE90 VCCGT82 H15
AV2 VCCCORE23 VCCCORE66 BE26 AJ10 VCCGT28/VCCCORE91 VCCGT83 H17
AV5 VCCCORE30 VCCCORE67 BE27 AK2 VCCGT27/VCCCORE92 VCCGT84 H18
AV7 VCCCORE32 VCCCORE68 BF2 AK9 VCCGT29//VCCCORE93 VCCGT85 H20
AV10 VCCCORE33 VCCCORE70 BF9 AL8 VCCGT30/VCCCORE94 VCCGT86 J7
AV27 VCCCORE29 VCCCORE73 BF24 AL9 VCCGT32/VCCCORE95 VCCGT95 J8
AW5 VCCCORE31 VCCCORE71 BF26 AL10 VCCGT33/VCCCORE96 VCCGT96 J11
AW6 VCCCORE39 VCCCORE72 BG27 AM8 VCCGT31/VCCCORE97 VCCGT91 J14
AW7 VCCCORE40 VCCCORE74 V2 VCCGT34/VCCCORE98 VCCGT92 J17
AW8 VCCCORE41 AN6
Trace Length < 25 mils Y10 VCCGT115/VCCCORE99 VCCGT93 J20
AW9 VCCCORE42 VCC_SENSE AN5 VCCSENSE <48> Y8 VCCGT119/VCCCORE100 VCCGT94 K2
2 AW10 VCCCORE43 VSS_SENSE VSSSENSE <48> VCCGT120/VCCCORE101 VCCGT98 K11 2
VCCCORE34 AA3 SOC_SVID_ALERT# B3 VCCGT97 L7
VIDALERT# B4 VCCGT39 VCCGT100 L8
BB9 AA1 SOC_SVID_CLK B6 VCCGT40 VCCGT101 L10
BC24 RSVD3 VIDSCK SOC_SVID_CLK <48> B8 VCCGT41 VCCGT99 M9
AY9 RSVD4 AA2 SOC_SVID_DAT B11 VCCGT42 VCCGT102 N7
BB24 RSVD1 VIDSOUT B14 VCCGT35 VCCGT104 N8
RSVD2 Y3 +1.05VS_VCCSTG B17 VCCGT36 VCCGT105 N9
RSVD5 B20 VCCGT37 VCCGT106 N10
BG3 C2 VCCGT38 VCCGT103 P2
VCCSTG1 C3 VCCGT49 VCCGT107 P8
WHL-U42_BGA1528 C6 VCCGT51 VCCGT108 R9
C7 VCCGT52 VCCGT109 T8
@ 12 of 20 VCCGT53 VCCGT111
C8 T9
C11 VCCGT54 VCCGT112 T10
C12 VCCGT43 VCCGT110 U8
C14 VCCGT44 VCCGT114 U10
C15 VCCGT45 VCCGT113
C17 VCCGT46 V9
C18 VCCGT47 VCCGT116 W8
C20 VCCGT48 VCCGT117 W9
D4 VCCGT50 VCCGT118
D7 VCCGT62
D11 VCCGT63 E3 VCCGT_SENSE
D12 VCCGT55 VCCGT_SENSE D2 VSSGT_SENSE VCCGT_SENSE <48>
D14 VCCGT56 VSSGT_SENSE VSSGT_SENSE <48>
VCCGT57
WHL-U42_BGA1528
13 of 20
@
Trace Length < 25 mils
3 3
+1.05V_VCCST
#543016 PDG2.0 P.273
1
RC179 RC181
56_0402_5% 100_0402_1%
Place the PU
resistors close to CPU
2
RC180
220_0402_5%
SOC_SVID_ALERT# 1 2
SOC_SVID_ALERT#_R <48>
SOC_SVID_DAT To VR
4 SOC_SVID_DAT <48> 4
2018/12/27
Compal Secret Data
2019/12/27 Title
WHL-U(10/12)Power,SVID
A B C D E
A B C D E
1 1
UC1R UC1S UC1T

GND 1 OF 3
BT35 GND 2 OF 3 BY25 GND 3 OF 3
CR34 BL7 D6 VSS_145 VSS_217 J18 N6 CF23
BT5 VSS_1 VSS_73 AE25 AL32 VSS_146 VSS_218 AU32 B37 VSS_290 VSS_362 V4
BY5 VSS_2 VSS_74 BM33 BT36 VSS_147 VSS_219 BY28 CB3 VSS_291 VSS_363 BE30
CP35 VSS_3 VSS_75 CM5 D8 VSS_148 VSS_220 J21 P10 VSS_292 VSS_364 CF28
CM37 VSS_4 VSS_76 AE27 AL7 VSS_149 VSS_221 AV25 B5 VSS_293 VSS_365 W10
CK37 VSS_5 VSS_77 BM35 D9 VSS_150 VSS_222 BY33 CB33 VSS_294 VSS_366 BE31
AW1 VSS_6 VSS_78 CM9 AM10 VSS_151 VSS_223 J24 P3 VSS_295 VSS_367 CF3
CM1 VSS_7 VSS_79 AE30 BU11 VSS_152 VSS_224 AV28 B7 VSS_296 VSS_368 W27
BD6 VSS_8 VSS_80 BM36 E23 VSS_153 VSS_225 BY35 CB4 VSS_297 VSS_369 CF4
AY4 VSS_9 VSS_81 CN13 AM28 VSS_154 VSS_226 J33 P33 VSS_298 VSS_370 W30
B34 VSS_10 VSS_82 AE7 E27 VSS_155 VSS_227 AV3 B9 VSS_299 VSS_371 BF3
E35 VSS_11 VSS_83 BM9 AM33 VSS_156 VSS_228 BY36 CB7 VSS_300 VSS_372 CG33
A4 VSS_12 VSS_84 CN17 BU23 VSS_157 VSS_229 J36 P36 VSS_301 VSS_373 W7
AE24 VSS_13 VSS_85 AF27 E29 VSS_158 VSS_230 AV33 BA10 VSS_302 VSS_374 BF33
AE26 VSS_14 VSS_86 BN30 AM35 VSS_159 VSS_231 J6 CC11 VSS_303 VSS_375 CG7
AF25 VSS_15 VSS_87 CN21 BU24 VSS_160 VSS_232 AV36 P4 VSS_304 VSS_376 BF36
AG24 VSS_16 VSS_88 AF3 E31 VSS_161 VSS_233 C1 BA28 VSS_305 VSS_377 Y26
AG26 VSS_17 VSS_89 BN7 BU25 VSS_162 VSS_234 K21 P7 VSS_306 VSS_378 BF4
AH24 VSS_18 VSS_90 CN25 E33 VSS_163 VSS_235 AV4 BA3 VSS_307 VSS_379 CH31
AH25 VSS_19 VSS_91 AF30 AN25 VSS_164 VSS_236 C21 CC20 VSS_308 VSS_380 Y27
B2 VSS_20 VSS_92 CN29 BU7 VSS_165 VSS_237 K22 R27 VSS_309 VSS_381 BG25
B36 VSS_21 VSS_93 AF33 E9 VSS_166 VSS_238 AV6 BB3 VSS_310 VSS_382 Y30
C36 VSS_22 VSS_94 BP15 AN28 VSS_167 VSS_239 C25 CC25 VSS_311 VSS_383 BG28
C37 VSS_23 VSS_95 AF36 BV11 VSS_168 VSS_240 K24 R28 VSS_312 VSS_384 CJ11
2 CN1 VSS_24 VSS_96 AF4 F12 VSS_169 VSS_241 AV8 BB33 VSS_313 VSS_385 Y33 2
CN2 VSS_25 VSS_97 CN5 AN29 VSS_170 VSS_242 C29 CC28 VSS_314 VSS_386 CJ14
CN37 VSS_26 VSS_98 AF7 F15 VSS_171 VSS_243 K25 R29 VSS_315 VSS_387 Y35
CP2 VSS_27 VSS_99 BP25 AN30 VSS_172 VSS_244 AW28 BB36 VSS_316 VSS_388 BH28
D1 VSS_28 VSS_100 CN9 F18 VSS_173 VSS_245 C33 CC31 VSS_317 VSS_389 CJ19
A32 VSS_29 VSS_101 AG10 AN31 VSS_174 VSS_246 K27 R30 VSS_318 VSS_390 Y7
F33 VSS_30 VSS_102 BP3 BV3 VSS_175 VSS_247 AW29 BB4 VSS_319 VSS_391 BH29
A3 VSS_31 VSS_103 CP1 F2 VSS_176 VSS_248 C4 CC7 VSS_320 VSS_392 CJ23
BJ7 VSS_32 VSS_104 BP32 AN7 VSS_177 VSS_249 K28 R31 VSS_321 VSS_393 BH32
CJ36 VSS_33 VSS_105 CP11 BV31 VSS_178 VSS_250 AW3 BC25 VSS_322 VSS_394 CJ28
A36 VSS_34 VSS_106 AH27 F21 VSS_179 VSS_251 C9 CD11 VSS_323 VSS_395 BH33
BK10 VSS_35 VSS_107 BP33 AN8 VSS_180 VSS_252 K29 T27 VSS_324 VSS_396 CJ33
CJ4 VSS_36 VSS_108 CP13 BV33 VSS_181 VSS_253 AW30 CD12 VSS_325 VSS_397 BH35
AB27 VSS_37 VSS_109 AH28 F24 VSS_182 VSS_254 CA11 T30 VSS_326 VSS_398 CJ35
BK2 VSS_38 VSS_110 BP4 BV4 VSS_183 VSS_255 K3 BC29 VSS_327 VSS_399 BP19
CK1 VSS_39 VSS_111 CP15 F3 VSS_184 VSS_256 AW31 CD14 VSS_328 VSS_400 BR16
AB3 VSS_40 VSS_112 AH29 AP3 VSS_185 VSS_257 CA15 T33 VSS_329 VSS_401 BY18
BK28 VSS_41 VSS_113 BP7 BW11 VSS_186 VSS_258 K30 T35 VSS_330 VSS_402 BY19
AB30 VSS_42 VSS_114 CP19 F4 VSS_187 VSS_259 AY33 BC32 VSS_331 VSS_403 CC16
BK3 VSS_43 VSS_115 AH30 AP33 VSS_188 VSS_260 CA22 CD24 VSS_332 VSS_404 BU16
CK4 VSS_44 VSS_116 CP21 BW15 VSS_189 VSS_261 K31 T36 VSS_333 VSS_405 CC14
AB33 VSS_45 VSS_117 AH31 G21 VSS_190 VSS_262 AY35 CD25 VSS_334 VSS_406 BR22
BK33 VSS_46 VSS_118 BR19 AP36 VSS_191 VSS_263 K32 T7 VSS_335 VSS_407 BU20
CK7 VSS_47 VSS_119 CP27 G27 VSS_192 VSS_264 B12 BC8 VSS_336 VSS_408 CD20
AB36 VSS_48 VSS_120 AH33 AP4 VSS_193 VSS_265 K4 CE33 VSS_337 VSS_409 BT14
BK4 VSS_49 VSS_121 BR25 G33 VSS_194 VSS_266 B15 U26 VSS_338 VSS_410 BP12
CL2 VSS_50 VSS_122 AH35 AR28 VSS_195 VSS_267 CA25 BD28 VSS_339 VSS_411 CB24
AB4 VSS_51 VSS_123 CP37 G35 VSS_196 VSS_268 K9 CE35 VSS_340 VSS_412 CC24
BK7 VSS_52 VSS_124 AJ25 G36 VSS_197 VSS_269 B18 U7 VSS_341 VSS_413 J5
3 CM13 VSS_53 VSS_125 BT15 AT33 VSS_198 VSS_270 CB11 BD33 VSS_342 VSS_414 U24 3
AB7 VSS_54 VSS_126 AJ28 BW24 VSS_199 VSS_271 L27 CE36 VSS_343 VSS_415 BD7
BL25 VSS_55 VSS_127 BT16 G9 VSS_200 VSS_272 B21 V26 VSS_344 VSS_416 AR4
CM17 VSS_56 VSS_128 CP9 AT35 VSS_201 VSS_273 L33 BD35 VSS_345 VSS_417 AU4
AC10 VSS_57 VSS_129 AJ7 H21 VSS_202 VSS_274 B23 CE7 VSS_346 VSS_418 AW4
BL28 VSS_58 VSS_130 CR2 AT36 VSS_203 VSS_275 L35 V27 VSS_347 VSS_419 BA6
CM21 VSS_59 VSS_131 AK3 BW7 VSS_204 VSS_276 B25 BD36 VSS_348 VSS_420 BC4
AC27 VSS_60 VSS_132 CR36 H27 VSS_205 VSS_277 CB18 CF11 VSS_349 VSS_421 BE4
BL29 VSS_61 VSS_133 AK33 AT4 VSS_206 VSS_278 L36 V3 VSS_350 VSS_422 BE8
CM25 VSS_62 VSS_134 D21 BY11 VSS_207 VSS_279 B27 BE10 VSS_351 VSS_423 BA4
AC30 VSS_63 VSS_135 AK36 AU10 VSS_208 VSS_280 CB19 CF14 VSS_352 VSS_424 BD4
BL30 VSS_64 VSS_136 BT25 BY15 VSS_209 VSS_281 L6 V30 VSS_353 VSS_425 BG4
CM29 VSS_65 VSS_137 D25 H9 VSS_210 VSS_282 B29 BE28 VSS_354 VSS_426 CJ2
BL31 VSS_66 VSS_138 AK4 AU28 VSS_211 VSS_283 CB2 CF19 VSS_355 VSS_427 CJ3
CM31 VSS_67 VSS_139 BT28 BY22 VSS_212 VSS_284 N25 V33 VSS_356 VSS_428 AM5
AD33 VSS_68 VSS_140 AL28 J12 VSS_213 VSS_285 B31 BE29 VSS_357 VSS_429 CM4
BL32 VSS_69 VSS_141 BT33 AU29 VSS_214 VSS_286 CB20 CF2 VSS_358 VSS_430 AC5
CM33 VSS_70 VSS_142 D5 J15 VSS_215 VSS_287 N27 V36 VSS_359 VSS_431 AG5
AD35 VSS_71 VSS_143 AL29 VSS_216 VSS_288 CB25 BE3 VSS_360 VSS_432 CR6
VSS_72 VSS_144 VSS_289 VSS_361 VSS_433
W HL-U42_BGA1528 W HL-U42_BGA1528 W HL-U42_BGA1528

@ @ 18 of 20 @ 19 of 20
17 of 20
4 4

WHL-U(11/12)GND
A B C D E
A B C D E
UC1Q
RESERVED SIGNALS
F37
CFG0 T4 RSVD_TP5 F34 F37,F34,CN36 are RSVD on WHL-U
@ T167 CFG_0 RSVD_TP4
@ T168 CFG1 R4
CFG2 T3 CFG_1 CP36
1
@ T169 CFG_2 IST_TRIG T162 @ 1
@ T170 CFG3 R3 CN36
CFG4 J4 CFG_3 RSVD_TP3
@ T171 CFG_4
@ T172 CFG5 M4 BJ36
CFG6 J3 CFG_5 RSVD15 BJ34
@ T173 CFG_6 RSVD14
@ T174 CFG7 M3
CFG8 R2 CFG_7 BK34
@ T175 CFG_8 TP_1 T273 @
@ T176 CFG9 N2 BR18 T272 @
CFG10 R1 CFG_9 TP_2
@ T177 CFG_10
@ T178 CFG11 N1
CFG12 J2 CFG_11
@ T179 CFG_12
@ T180 CFG13 L2 BT9
CFG14 J1 CFG_13 RSVD21 BT8
@ T181 CFG_14 RSVD20
@ T182 CFG15 L1
CFG_15 BP8
CFG16 L3 RSVD18 BP9
@ T186 CFG18 N3
CFG17 L4 CFG_18 CR4
@ T188 CFG19 N4
CFG_19 CP3
RSVD26 CR3
CFG_RCOMP AB5 RSVD27
CFG_RCOMP
XDP_ITP_PMODE W4 #575414 WHL MechSpec R1.2
@ T189 ITP_PMODE BP36-> VSS-> GND
BP36
CG2 VSS_434
CG1 RSVD25
RSVD24
AT3
RSVD12 AU3
RSVD13
H4
H3 RSVD34
2 RSVD33 AN1 2
BV24 RSVD8 AN2
BV25 RSVD22 RSVD9
RSVD23 AN4
RSVD11 AN3
RSVD10
AL2
G3 RSVD72 AL1
G3,G4 are RSVD on WHL-U G4 RSVD66 RSVD73
RSVD67
AL4
RSVD74 AL3
BK36 RSVD75
BK35 RSVD17 BP34
RSVD16 TP_4 T214 @
BP35 T216 @
W3 TP_3
AM4 RSVD35
RSVD7 C34
AM3 RSVD68
RSVD6 A34
RSVD_TP1 B35 C34, A34,B35,AH26,AJ27 are RSVD on WHL-U
RSVD_TP2
CR35 T281 @ INTEL RF Linda suggest add test point for monitor CNVio
A35 RSVD28
2 1 CFG_RCOMP D34 RSVD1
49.9_0402_1% RC185 RSVD30 AH26
G2 RSVD36 AJ27 +1.05V_VCCST
2 1 CFG4 G1 RSVD32 RSVD37
1K_0402_1% RC193 RSVD31 E1 SKL_CNL# 1 @ 2
SKTOCC# RC184 100K_0402_5%
WHL-U42_BGA1528
3 3
@ 20 of 20
#544669 CRB1.1 P.54
#544924 SKL EDS1.2 P.125
PROC_SELECT#
This pin is for compatibility with future
Display Port Presence Strap platforms. It should be unconnected for
the processor.
1 : Disabled; No Physical Display Port
CFG4 at t ac hed t o E mbedded Dis pl ay Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
4 4
2018/12/27
Compal Secret Data
2019/12/27 Title
WHL-U(12/12)RSVD
A B C D E
5 4 3 2 1
+DDR_VREF_CA +DDR_VREF_CA
+DDR_VREF_CA +DDR_VREF_CA
U2 U3
U4 U5
M1 G2 DDR_A_D5 M1 G2 DDR_A_D25
VREFCA DQL0 DDR_A_D6 VREFCA DQL0 DDR_A_D29 DDR_A_D40 DDR_A_D56
0.047U_0402_25V7K
0.047U_0402_25V7K
F7 F7 M1 G2 M1 G2
DQL1 DDR_A_D1 DQL1 DDR_A_D27 VREFCA DQL0 DDR_A_D43 VREFCA DQL0 DDR_A_D58
0.047U_0402_25V7K
0.047U_0402_25V7K
H3 H3 F7 F7
DDR_A_MA0 P3 DQL2 H7 DDR_A_D2 DDR_A_MA0 P3 DQL2 H7 DDR_A_D26 DQL1 H3 DDR_A_D44 DQL1 H3 DDR_A_D57
A0 DQL3 A0 DQL3 DQL2 DQL2
1
DDR_A_MA1 DDR_A_D4
1
P7 H2 DDR_A_MA1 P7 H2 DDR_A_D24 DDR_A_MA0 P3 H7 DDR_A_D42 DDR_A_MA0 P3 H7 DDR_A_D59
CD124
CD125
DDR_A_MA2 A1 DQL4 DDR_A_D7 DDR_A_MA2 A1 DQL4 DDR_A_D31 A0 DQL3 A0 DQL3
1
DDR_A_MA1 DDR_A_D41
1
R3 H8 R3 H8 P7 H2 DDR_A_MA1 P7 H2 DDR_A_D61
CD126
CD127
DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D0 DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D28 DDR_A_MA2 R3 A1 DQL4 H8 DDR_A_D46 DDR_A_MA2 R3 A1 DQL4 H8 DDR_A_D62
2
MEM@ DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D3 MEM@ DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D30 DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D45 DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D60
2
DDR_A_MA5 P8 A4 DQL7 DDR_A_MA5 P8 A4 DQL7 MEM@ DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D47 MEM@ DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D63
DDR_A_MA6 P2 A5 DDR_A_MA6 P2 A5 DDR_A_MA5 P8 A4 DQL7 DDR_A_MA5 P8 A4 DQL7
DDR_A_MA7 R8 A6 A3 DDR_A_D13 DDR_A_MA7 R8 A6 A3 DDR_A_D16 DDR_A_MA6 P2 A5 DDR_A_MA6 P2 A5
DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D14 DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D18 DDR_A_MA7 R8 A6 A3 DDR_A_D37 DDR_A_MA7 R8 A6 A3 DDR_A_D52
D DDR_A_MA9 A8 DQU1 DDR_A_D9 DDR_A_MA9 A8 DQU1 DDR_A_D17 DDR_A_MA8 A7 DQU0 DDR_A_D39 DDR_A_MA8 A7 DQU0 DDR_A_D55 D
R7 C3 R7 C3 R2 B8 R2 B8
DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D15 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D23 DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D32 DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D53
DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D8 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D20 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D35 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D54
DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D10 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D22 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D34 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D49
DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D12 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D21 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D33 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D50
DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D11 DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D19 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D36 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D48
A14/WE DQU7 A14/WE DQU7 DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D38 DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D51
DDR_A_BA0 N2 DDR_A_BA0 N2 A14/WE DQU7 A14/WE DQU7
<8> DDR_A_BA0 DDR_A_BA1 BA0 DDR_A_BA1 BA0 DDR_A_BA0 DDR_A_BA0
<8> DDR_A_BA1 N8 B3 +1.2V_VDDQ N8 B3 +1.2V_VDDQ N2 N2 +1.2V_VDDQ
BA1 VDD B9 BA1 VDD B9 DDR_A_BA1 N8 BA0 B3 DDR_A_BA1 N8 BA0 B3
VDD VDD BA1 VDD +1.2V_VDDQ BA1 VDD
+1.2V_VDDQ E2 D1 +1.2V_VDDQ E2 D1 B9 B9
E7 DMU/DBIU VDD G7 E7 DMU/DBIU VDD G7 E2 VDD D1 E2 VDD D1
DML/DBIL VDD DML/DBIL VDD +1.2V_VDDQ DMU/DBIU VDD +1.2V_VDDQ DMU/DBIU VDD
J1 J1 E7 G7 E7 G7
VDD J9 VDD J9 DML/DBIL VDD J1 DML/DBIL VDD J1
VDD L1 VDD L1 VDD J9 VDD J9
DDR_A_CLK0 K7 VDD L9 DDR_A_CLK0 K7 VDD L9 VDD L1 VDD L1
<8> DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD DDR_A_CLK#0 CK_t VDD DDR_A_CLK0 VDD DDR_A_CLK0 VDD
<8> DDR_A_CLK#0 K8 R1 K8 R1 K7 L9 K7 L9
DDR_A_CKE0 K2 CK_c VDD T9 DDR_A_CKE0 K2 CK_c VDD T9 DDR_A_CLK#0 K8 CK_t VDD R1 DDR_A_CLK#0 K8 CK_t VDD R1
<8> DDR_A_CKE0 CKE VDD CKE VDD DDR_A_CKE0 CK_c VDD DDR_A_CKE0 CK_c VDD
K2 T9 K2 T9
CKE VDD CKE VDD
A1 A1
VDDQ A9 VDDQ A9 A1 A1
VDDQ C1 VDDQ C1 VDDQ A9 VDDQ A9
VDDQ D9 VDDQ D9 VDDQ C1 VDDQ C1
VDDQ F2 VDDQ F2 VDDQ D9 VDDQ D9
VDDQ F8 VDDQ F8 VDDQ F2 VDDQ F2
DDR_A_ODT0 K3 VDDQ G1 DDR_A_ODT0 K3 VDDQ G1 VDDQ F8 VDDQ F8
<8> DDR_A_ODT0 DDR_A_CS#0 ODT VDDQ DDR_A_CS#0 ODT VDDQ DDR_A_ODT0 VDDQ DDR_A_ODT0 VDDQ
<8> DDR_A_CS#0 L7 G9 L7 G9 K3 G1 K3 G1
DDR_A_MA16 L8 CS VDDQ J2 DDR_A_MA16 L8 CS VDDQ J2 DDR_A_CS#0 L7 ODT VDDQ G9 DDR_A_CS#0 L7 ODT VDDQ G9
DDR_A_MA15 M8 RAS VDDQ J8 DDR_A_MA15 M8 RAS VDDQ J8 DDR_A_MA16 L8 CS VDDQ J2 DDR_A_MA16 L8 CS VDDQ J2
CAS VDDQ CAS VDDQ DDR_A_MA15 M8 RAS VDDQ J8 DDR_A_MA15 M8 RAS VDDQ J8
B2 RD206 B2 RD207 CAS VDDQ CAS VDDQ
VSS 10mils VSS 10mils
E1 240_0402_1% E1 240_0402_1% B2 10mils RD208 B2 10mils
VSS E9 VSS_E9_U2 1 DDP@ 2 VSS E9 VSS_E9_U3 1 DDP@ 2 VSS E1 240_0402_1% VSS E1
VSS G8 VSS G8 VSS E9 VSS_E9_U4 1 DDP@ 2 VSS E9 VSS_E9_U5
DDR_A_DQS#1 A7 VSS K1 RD79 DDR_A_DQS#2 A7 VSS K1 VSS G8 VSS G8
DDR_A_DQS1 DQSU_c VSS 10mils DDR_A_DQS2 DQSU_c VSS 10mils DDR_A_DQS#4 VSS DDR_A_DQS#6 VSS
B7 K9 0_0402_5% B7 K9 A7 K1 10mils A7 K1 DDP@
DDR_A_DQS#0 F3 DQSU_t VSS M9 DDR_A_BG1_R 1 SDP@ 2 DDR_A_DQS#3 F3 DQSU_t VSS M9 DDR_A_BG1_R DDR_A_DQS4 B7 DQSU_c VSS K9 DDR_A_DQS6 B7 DQSU_c VSS K9
DDR_A_DQS0 DQSL_c VSS DDR_A_DQS3 DQSL_c VSS DDR_A_DQS#5 DQSU_t VSS DDR_A_BG1_R DDR_A_DQS#7 DQSU_t VSS
1
240_0402_1%
RD209
G3 N1 G3 N1 F3 M9 F3 M9
DQSL_t VSS T1 RD78 DQSL_t VSS T1 DDR_A_DQS5 G3 DQSL_c VSS N1 DDR_A_DQS7 G3 DQSL_c VSS N1
DDR_A_BG1_R
MEMRST# P1 VSS 0_0201_1% MEMRST# P1 VSS DQSL_t VSS T1 DQSL_t VSS T1
RESET 1 DDP@ 2 DDR_A_BG1 RESET MEMRST# P1 VSS MEMRST# P1 VSS
1 MEM@ 2 RD210 F9 1 MEM@ 2 RD211 F9 RESET RESET
2
240_0402_1% ZQ 240_0402_1% ZQ 1 MEM@ 2 RD212 F9 1 MEM@ 2 RD213 F9
DDR_A_BG1(RD78, Intel:549352) ZQ ZQ
C 1. Near SOC side 240_0402_1% 240_0402_1% C
DDR_A_ACT# L3 A2 DDR_A_ACT# L3 A2
<8> DDR_A_ACT# DDR_A_BG0 ACT VSSQ 2. BO1+BO2+M small then other DDR_A_BG0 ACT VSSQ DDR_A_ACT# DDR_A_ACT# 10mils
<8> DDR_A_BG0 M2 A8 CMD 25mils M2 A8 L3 A2 L3 A2
N9 BG0 VSSQ C9 N9 BG0 VSSQ C9 DDR_A_BG0 M2 ACT VSSQ A8 DDR_A_BG0 M2 ACT VSSQ A8
DDR_A_ALERT# TEN VSSQ 3. BO1+BO2 small then 800mils DDR_A_ALERT# TEN VSSQ BG0 VSSQ BG0 VSSQ
<8> DDR_A_ALERT# P9 D2 P9 D2 N9 C9 N9 C9
DDR_A_PAR T3 ALERT VSSQ D8 DDR_A_PAR T3 ALERT VSSQ D8 DDR_A_ALERT# P9 TEN VSSQ D2 DDR_A_ALERT# P9 TEN VSSQ D2
<8> DDR_A_PAR PAR VSSQ PAR VSSQ DDR_A_PAR ALERT VSSQ DDR_A_PAR ALERT VSSQ
E3 E3 T3 D8 T3 D8
T7 VSSQ E8 T7 VSSQ E8 PAR VSSQ E3 PAR VSSQ E3
B1 NC VSSQ F1 B1 NC VSSQ F1 T7 VSSQ E8 T7 VSSQ E8
+2.5V VPP VSSQ +2.5V VPP VSSQ NC VSSQ NC VSSQ
R9 H1 R9 H1 +2.5V B1 F1 +2.5V B1 F1
VPP VSSQ H9 VPP VSSQ H9 R9 VPP VSSQ H1 R9 VPP VSSQ H1
<8> DDR_A_MA[0..16] VSSQ VSSQ VPP VSSQ VPP VSSQ
96-BALL 96-BALL H9 H9
SDRAM DDR4 SDRAM DDR4 96-BALL VSSQ 96-BALL VSSQ
<8> DDR_A_DQS#[0..7]
K4A8G165WB-BCPB_FBGA96 K4A8G165WB-BCPB_FBGA96 SDRAM DDR4 SDRAM DDR4
X76@ X76@ K4A8G165WB-BCPB_FBGA96 K4A8G165WB-BCPB_FBGA96
<8> DDR_A_DQS[0..7]
X76@ X76@
<8> DDR_A_D[0..63]
<8> DDR_A_BG1
TERMINATION
+1.2V_VDDQ
+0.6VS_VTT
DDR_A_CLK0 RD214 1 MEM@ 2 36_0201_1% 1 2
DDR4 mapping SDP DDP +1.2V_VDDQ DDR_A_CLK#0 RD215 1 MEM@ 2 36_0201_1%
CD50 MEM@ DDR_A_MA14 RD218 1 MEM@ 2 36_0201_1%
E9 VSS UZQ +0.6V_A_VREFCA 0.01U_0402_16V7K DDR_A_CS#0 RD217 1 MEM@ 2 36_0201_1%
DDR_A_CLK0 #595182_WHL_6L_twp_ p34 11/27 DDR_A_MA15 RD220 1 MEM@ 2 36_0201_1%
M9 VSS BG1 1
2
DDR_A_MA12 RD219 1 MEM@ 2 36_0201_1%
T7 NC VSS RD195 CD51
DDR_A_CLK#0 3.3P_0402_50V8W
1.8K_0402_1%
RD11 +DDR_VREF_CA 2@
VDDQ RCOMP[0] MEM@
(SOC side) 200_1% 121_1% 2.7_0402_1%
1uF*16
1
2 MEM@ 1 DDR_A_MA13 RD222 1 MEM@ 2 36_0201_1%
10uF*5 CD51 close to CPU DDR_A_MA8 RD221 1 MEM@ 2 36_0201_1%
DDR_A_PAR RD223 1 MEM@ 2 36_0201_1%
+0.6VS_VTT DDR_A_MA11 RD224 1 MEM@ 2 36_0201_1%
4 as near each on board RAM device as possible Follow MA51 1
+1.2V_VDDQ SDP@ SDP@
RD206 RD208 CD24
DDR_A_BG1_R
CD230
CD231
CD232
CD233
CD234
CD235
CD236
CD218
CD210
CD211
CD212
CD213
CD214
CD215
CD216
CD217
CD225
CD226
CD227
CD228
CD229
0_0402_5% 0_0402_5% 0.022U_0402_16V7K RD86 1 DDP@ 2 36_0201_1%

SD028000080 SD028000080 MEM@ 2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DDR_A_MA1
B
RD225 1 MEM@ 2 36_0201_1% B
2
+ CD237 SDP@ SDP@ +1.2V_VDDQ DDR_A_MA5 RD226 1 MEM@ 2 36_0201_1%
DDR_A_MA7
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
330U_D2_2V_Y RD207 RD209 RD13 RD200 RD228 1 MEM@ 2 36_0201_1%

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 @ 0_0402_5% 0_0402_5% DDR_A_MA9 RD227 1 MEM@ 2 36_0201_1%
2 SGA00009S00 SD028000080 SD028000080
24.9_0402_1%
MEM@
1.8K_0402_1%
DDR_A_ALERT# RD41 2 1 49.9_0201_1%
330U 2V H1.9 MEM@
1
9mohm POLY MEM@ INTEL suggest 50ohm 1%
DDR_A_BG0 RD229 1 MEM@ 2 36_0201_1%

DDR_A_MA10 RD230 1 MEM@ 2 36_0201_1%
DDR_A_MA3 RD232 1 MEM@ 2 36_0201_1%
DDR_A_BA1 RD231 1 MEM@ 2 36_0201_1%
+1.2V_VDDQ
DVT 01/23
DDR_A_CKE0 RD234 1 MEM@ 2 36_0201_1%
DDR_DRAMRST# 1 MEM@ 2 MEMRST# DDR_A_MA16 RD233 1 MEM@ 2 36_0201_1%
<8,20> DDR_DRAMRST# DDR_A_ODT0
CD264
CD263
CD266
CD267
RD202 0_0402_5% RD235 1 MEM@ 2 36_0201_1%

DDR_A_ACT# RD236 1 MEM@ 2 36_0201_1%
1 1 1 1
1
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
@ CD219
2 2 2 2
.1U_0402_16V7K
2
DDR_A_MA2 1 MEM@ 2 RD216
36_0201_1%
Add for cap downsize DDR_A_MA4 RD238 1 MEM@ 2 36_0201_1%

DDR_A_BA0 RD237 1 MEM@ 2 36_0201_1%
DDR_A_MA0 RD239 1 MEM@ 2 36_0201_1%
DDR_A_MA6 RD240 1 MEM@ 2 36_0201_1%
VPP
1uF*8 VTT
1uF*8 Page12
A
10uF*3 A
10uF*2 RAM_ID3 RAM_ID2 *RAM_ID1 *RAM_ID0 PartNumber - Description
+2.5V +0.6VS_VTT Hynix 4GB 0 0 0 0 SA0000A1H20 (S IC D4 512M16 H5AN8G6NAFR-UHC FBGA ABO!)

CD238
CD254
CD255
CD241
CD256
CD243
CD244
CD245
CD220
CD221
CD222
CD269
CD270
CD271
Micron 4GB 0 0 0 1 SA00009V220 (S IC D4 512M16 MT40A512M16JY-083E:B ABO!)

CD246
CD247
CD248
CD249
CD250
CD251
CD252
CD253
CD224
CD223
CD274
CD272
CD273
1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 Samsung 4GB 0 0 1 0 SA00009U420 (S IC D4 512M16 K4A8G165WB-BCRC FBGA 96P ABO !)
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
2 2 2 2 2 2 2 2 2 2 2 2 2 2 0 0 1 1
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
2 2 2 2 2 2 2 2 2 2 2 2 2 No OnBoard
1 1 1 1 No On Board Memory
Memory

DDR4 ON BOARD CHIPS
2 as near each on board RAM device as possible AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Add for cap downsize
2 as near each on board RAM device as possible Add for cap downsize DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
5 4 3 2 1
A B C D E
<8> DDR_B_DQS#[0..7]
JDIMM2A
<8> DDR_B_D[0..63]
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
137
139 CK0(T)
CK0#(C)
STD
DQ0
DQ1
8
7
DDR_B_D12
DDR_B_D8
DDR_B_D15
Standard Type
138 20
<8> DDR_B_DQS[0..7] DDR_B_CLK#1 140 CK1(T) DQ2 21 DDR_B_D11
CK1#(C) DQ3 4 DDR_B_D13 2-3A to 1 DIMMs/channel
DDR_B_CKE0 109 DQ4 3 DDR_B_D9
<8> DDR_B_MA[0..16] DDR_B_CKE1 110 CKE0 DQ5 16 DDR_B_D10
DDR_B_BA0 +3VS CKE1 DQ6 17 DDR_B_D14
<8> DDR_B_BA0 DDR_B_BA1 DDR_B_CS#0 149 DQ7 13 DDR_B_DQS1
<8> DDR_B_BA1 DDR_B_BG0 DDR_B_CS#1 157 S0# DQS0(T) 11 DDR_B_DQS#1
<8> DDR_B_BG0 DDR_B_BG1 162 S1# DQS0#(C) +1.2V_VDDQ +1.2V_VDDQ
<8> DDR_B_BG1 S2#/C0
1
1 DDR_B_ACT# 165 28 DDR_B_D3 JDIMM2B 1
<8> DDR_B_ACT# DDR_B_ALERT# S3#/C1 DQ8 29 DDR_B_D7 STD
RD52
<8> DDR_B_ALERT# DDR_B_PAR DDR_B_ODT0 155 DQ9 41 DDR_B_D4 111 141
0_0402_5% @
<8> DDR_B_PAR DDR_B_ODT1 161 ODT0 DQ10 42 DDR_B_D5 112 VDD1 VDD11 142
ODT1 DQ11 24 DDR_B_D0 117 VDD2 VDD12 147
2
DDR_B_BG0 115 DQ12 25 DDR_B_D2 118 VDD3 VDD13 148
DDR_B_CLK0 DDR_B_BG1 113 BG0 DQ13 38 DDR_B_D1 +1.2V_VDDQ 123 VDD4 VDD14 153
<8> DDR_B_CLK0 DDR_B_CLK#0 DDR_B_SA2 DDR_B_BA0 150 BG1 DQ14 37 DDR_B_D6 124 VDD5 VDD15 154
<8> DDR_B_CLK#0 DDR_B_CLK1 DDR_B_SA1 DDR_B_BA1 145 BA0 DQ15 34 DDR_B_DQS0 +0.6V_B_VREFCA 129 VDD6 VDD16 159
<8> DDR_B_CLK1 BA1 DQS1(T) VDD7 VDD17
1
DDR_B_CLK#1 DDR_B_SA0 32 DDR_B_DQS#0 130 160
<8> DDR_B_CLK#1 DDR_B_MA0 144 DQS1#(C) RD46 135 VDD8 VDD18 163
A0 VDD9 VDD19
1
DDR_B_MA1 133 50 DDR_B_D16 1K_0402_1% 136
DDR_B_CKE0 RD54 RD56 DDR_B_MA2 132 A1 DQ16 49 DDR_B_D17 +0.6V_DDRB_VREFCA VDD10
<8> DDR_B_CKE0 DDR_B_CKE1 DDR_B_MA3 131 A2 DQ17 62 DDR_B_D22 Data swap 12/12 255 258
0_0402_5% @ 0_0402_5% @ RD49 +3VS +0.6VS_VTT
<8> DDR_B_CKE1
2
DDR_B_CS#0 DDR_B_MA4 128 A3 DQ18 63 DDR_B_D19 VDDSPD VTT
<8> DDR_B_CS#0 DDR_B_CS#1 DDR_B_MA5 A4 DQ19 DDR_B_D20
2_0402_1% 20mils
126 46 2 1 164 257
<8> DDR_B_CS#1 +2.5V
2
DDR_B_MA6 127 A5 DQ20 45 DDR_B_D21 VREFCA VPP1 259
DDR_B_MA7 A6 DQ21 DDR_B_D23 1 VPP2
122 58
SOC_SMBDATA_1 DDR_B_MA8 125 A7 DQ22 59 DDR_B_D18 CD66 1 99
<9,33> SOC_SMBDATA_1 A8 DQ23 1 VSS VSS
1
SOC_SMBCLK_1 DDR_B_MA9 121 55 DDR_B_DQS2 0.022U_0402_16V7K 2 102
<9,33> SOC_SMBCLK_1 DDR_B_MA10 146 A9 DQS2(T) 53 DDR_B_DQS#2 2 5 VSS VSS 103
RD47 CD65
DDR_B_MA11 120 A10_AP DQS2#(C) 1K_0402_1% 0.1U_0201_10V6K 6 VSS VSS 106
A11 VSS VSS
1
DDR_B_ODT0 DDR_B_MA12 119 70 DDR_B_D25 2 9 107
<8> DDR_B_ODT0 DDR_B_ODT1 DDR_B_MA13 158 A12 DQ24 71 DDR_B_D29 10 VSS VSS 167
RD50
<8> DDR_B_ODT1
2
DDR_B_MA14 151 A13 DQ25 83 DDR_B_D30 14 VSS VSS 168
A14_WE# DQ26 24.9_0402_1% VSS VSS
DDR_B_MA15 156 84 DDR_B_D27 15 171
DDR_B_MA16 152 A15_CAS# DQ27 66 DDR_B_D28 18 VSS VSS 172
2
A16_RAS# DQ28 67 DDR_B_D24 19 VSS VSS 175
DDR_B_ACT# 114 DQ29 79 DDR_B_D31 22 VSS VSS 176
ACT# DQ30 80 DDR_B_D26 23 VSS VSS 180
DDR_B_PAR 143 DQ31 76 DDR_B_DQS3 26 VSS VSS 181
DDR_B_ALERT# 116 PARITY DQS3(T) 74 DDR_B_DQS#3 27 VSS VSS 184
Layout Note:
2
Place near JDIMM2 +1.2V_VDDQ RD63 2 1 240_0402_1% DDR_B_EVENT# 134
DDR_DRAMRST# 108
ALERT#
EVENT#
DQS3#(C)
DDR_B_D39
Place near to SO-DIMM connector. 30 VSS
VSS
VSS
VSS
185 2
174 31 188
<8,19> DDR_DRAMRST# RESET# DQ32 173 DDR_B_D38 35 VSS VSS 189
RD1 1 2 470_0402_5% DQ33 187 DDR_B_D37 36 VSS VSS 192
+1.2V_VDDQ SOC_SMBDATA_1 254 DQ34 DDR_B_D34 VSS VSS
186 39 193
CD30 2 1 .1U_0402_16V7K SOC_SMBCLK_1 253 SDA DQ35 170 DDR_B_D32 40 VSS VSS 196
@ESD@ SCL DQ36 169 DDR_B_D33 43 VSS VSS 197
+1.2V_VDDQ DDR_B_SA2 166 DQ37 183 DDR_B_D36 44 VSS VSS 201
DDR_B_SA1 260 SA2 DQ38 182 DDR_B_D35 47 VSS VSS 202
DDR_B_SA0 256 SA1 DQ39 179 DDR_B_DQS4 48 VSS VSS 205
SA0 DQS4(T) DDR_B_DQS#4 VSS VSS
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
177 51 206
DQS4#(C) 52 VSS VSS 209
1 1 1 1 1 1 1 1 DDR_B_D40 VSS VSS
CD32
CD33
CD34
CD35
CD36
CD37
CD69
CD70
92 195 56 210
91 CB0_NC DQ40 194 DDR_B_D41 57 VSS VSS 213
2 2 2 2 2 2 2 2 105 CB2_NC DQ42 208 DDR_B_D46 61 VSS VSS 217
RD61 2 1 240_0402_1% DDR_B_DQS8 97 CB7_NC DQ47 200 DDR_B_DQS5 72 VSS VSS 227
+1.2V_VDDQ DDR_B_DQS#8 DQS8(T) DQS5(T) DDR_B_DQS#5 VSS VSS
RD62 2 1 240_0402_1% 95 198 73 230
DQS8#(C) DQS5#(C) 77 VSS VSS 231
+1.2V_VDDQ 216 DDR_B_D53 78 VSS VSS 234
12 DQ48 215 DDR_B_D52 81 VSS VSS 235
+1.2V_VDDQ DM0#/DBI0# DQ49 DDR_B_D54 VSS VSS
33 228 82 238
54 DM1#/DBI1# DQ50 229 DDR_B_D50 85 VSS VSS 239
DM3#/DBI3# DQ52 DDR_B_D48 VSS VSS
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
178 212 89 244

DM5#/DBI5# DQ54 VSS VSS
1
DDR_B_D51
CD38
CD39
CD40
CD41
CD42
CD43
CD44
CD45
220 225 93 248

241 DM6#/DBI6# DQ55 221 DDR_B_DQS6 94 VSS VSS 251
3 96 DM7#/DBI7# DQS6(T) 219 DDR_B_DQS#6 98 VSS VSS 252 3
2
DM8#/DBI8# DQS6#(C) VSS VSS

VDDQ
262 261
1uF*8 GND GND
10uF*8 237 DDR_B_D61
DQ56 DDR_B_D57
330uF*1 DQ57
236
DDR_B_D58
FOX_AS0A821-H4SB-7H
249 CONN@
DQ58 250 DDR_B_D63
DQ59 DDR_B_D60
SP07001GA00
232
DQ60 233 DDR_B_D56
+1.2V_VDDQ DQ61 245 DDR_B_D59
DQ62 246 DDR_B_D62
DQ63 DDR_B_DQS7
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
242
DQS7(T) 240 DDR_B_DQS#7
1@
1@
1 1 DQS7#(C)
CD258
CD259
CD260
CD261
Layout Note:
Place near JDIMM1.258
2
2 2 FOX_AS0A821-H4SB-7H
CONN@
SP07001GA00
VTT
Compatible with SP07001HW00 1uF*2
Reserved for cap downsize +0.6VS_VTT
Layout Note: 10uF*1
Place near JDIMM2.255
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
Layout Note:
Place near JDIMM1.257,259 #575412 WHL-U PDG R0.7 Table 4-23 1 1
1
CD257
CD64
CD62
CD63
add 0.1UF
2
+3VS 2 2
4
+2.5V VPP VDDSPD 4
1uF*1 0.1uF*1
10uF*1 2.2uF*1
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
2.2U_0402_6.3V6M
add 1 cap for MLCC downsize
1 1
1
1
CD240
CD68
CD67
CD239
CD55
.1U_0402_16V7K

2
2 2
DDR4_DIMMB
add 1 cap for MLCC downsize Date: Thursday, June 06, 2019 Sheet 20 of 57
A B C D E
A B C D E
N16 GPU
UGPU1A +1.8VSDGPU_AON GPIO I/O USAGE
GPIO0 O GC6_FB_EN
Part 1 of 6 GPIO1
DGPU_VID A6_OVERT# O MEM_VDD_CTL
<13> PCIE_CTX_C_GRX_P1 AG6 C6 RV289 2 VGA@ 1 10K_0402_5%
PEX_RX0 GPIO0 GC6_FB_EN1V8 DGPU_VID <53> GPIO9_ALERT LCD_BL_PWM
<13> PCIE_CTX_C_GRX_N1 AG7 B2 RV290 2 VGA@ 1 10K_0402_5% GPIO2 O
PEX_RX0_N GPIO1 GPU_EVENT#_1 GC6_FB_EN1V8 <22> ACIN_BUF
<13> PCIE_CTX_C_GRX_P2 AF7 D6 RV291 2 VGA@ 1 10K_0402_5% GPIO3 O LCD_VCC
AE7 PEX_RX1 GPIO2 C7 VRAM_VREF_CTL RV292 2 VGA@ 1 10K_0402_5%
<13> PCIE_CTX_C_GRX_N2 PEX_RX1_N GPIO3 1.8VSDGPU_MAIN_EN GPIO4 O LCD_BLEN
AE9 F9
<13> PCIE_CTX_C_GRX_P3 PEX_RX2 GPIO4 1.8VSDGPU_MAIN_EN <22,40> GPIO5 O 3V3_MAIN_EN
AF9 A3
<13> PCIE_CTX_C_GRX_N3 PEX_RX2_N GPIO5 DGPU_PSI
AG9 A4 GPIO6 I GPU_EVENT#
<13> PCIE_CTX_C_GRX_P4 PEX_RX3 GPIO6 DGPU_PSI <53>
AG10 B6 GPIO7 O 3D Vision
<13> PCIE_CTX_C_GRX_N4 PEX_RX3_N GPIO7 A6_OVERT# +1.8VSDGPU_AON
AF10 A6
AE10 NC PEX_RX4 OVERT F8 GPIO9_ALERT GPIO8 I SYS_PEX_RST_MON#
AE12 NC PEX_RX4_N GPIO9 C5 VRAM_VREF_CTL GPIO9 I/O THERM_ALERT
1 NC PEX_RX5 GPIO10 VRAM_VREF_CTL <26> GPU_EVENT#_1 1
AF12 E7 RV293 2 VGA@ 1 10K_0402_5%
AG12 NC PEX_RX5_N GPIO11 D7 ACIN_BUF 1.8VSDGPU_MAIN_EN RV294 2 VGA@ 1 10K_0402_5%
GPIO10 O MEM_VREF_CTL
AG13 NC PEX_RX6 GPIO12 B4 GPU_PEX_RST_HOLD# RV295 2 VGA@ 1 10K_0402_5% GPIO11 O PWM_VID
GPIO
AF13 NC PEX_RX6_N GPIO13 B3 GC6_FB_EN1V8 RV296 2 VGA@ 1 10K_0402_5% GPIO12 I PWR_LEVEL
AE13 NC PEX_RX7 GPIO14 C3
NC PEX_RX7_N GPIO15 GPIO13 O PSI
AE15 D5
AF15 NC PEX_RX8 GPIO16 D4 GPIO14 I HPD_A
AG15 NC PEX_RX8_N GPIO17 C2 GPIO15 I HPD_C
AG16 NC PEX_RX9 GPIO18 F7
AF16 NC PEX_RX9_N GPIO19 E6 +1.8VSDGPU_AON GPIO16 I FRAME_LOCK#
AE16 NC PEX_RX10 GPIO20 C4 GPU_PEX_RST_HOLD# GPIO17 I HPD_D

AE18 NC PEX_RX10_N GPIO21 GPIO18 I HPD_E
AF18 NC PEX_RX11 NC AB6
AG18 NC PEX_RX11_N PEX_WAKE_NC R2000
GPIO19 I HPD_F or HPD_B
AG19 NC PEX_RX12 I2CS_SDA 1 VGA@ 2 1.8K_0402_1% GPIO20 Reserved
AF19 NC PEX_RX12_N +1.8VSDGPU_AON R2001 GPIO21 O GPU_PEX_RST_HOLD#
AE19 NC PEX_RX13 I2CS_SCL 1 VGA@ 2 1.8K_0402_1%
AE21 NC PEX_RX13_N AG3 +1.8VSDGPU_AON R2052
GPIO22
NC PEX_RX14 NC
2
AF21 AF4 DGPU_PSI 2 VGA@ 1 10K_0402_5% GPIO23
AG21 NC PEX_RX14_N NC AF3 VCC: 1.65 ~ 5.5V RV83
AG22 NC PEX_RX15 NC
NC PEX_RX15_N
Push Pull Output 10K_0402_5% CLKREQ_PCIE#3 <11>
5
@ N17 GPU
PH at PCH side GPU_EVENT#_1 2 1
VCC
GPU_EVENT# <10> GPIO I/O USAGE
3
CV11 VGA@ 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_P1 AC9 AE3 1VS_DGPU_PG 1 D2011 VGA@
<13> PCIE_CRX_GTX_P1 PEX_TX0 NC IN B
DACs
CV12 VGA@ 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_N1 AB9 AE4 4 ALL_GPWRGD 5 G
D
QV5A RB751V-40_SOD323-2 GPIO0 O PWM_VID
<13> PCIE_CRX_GTX_N1 PCIE_CRX_C_GTX_P2 PEX_TX0_N NC OUT Y ACIN_BUF
CV13 VGA@ 1 2 0.22U_0402_16V7K AB10 <40,51> 1.35VS_DGPU_PG 2 PJT138KA 2N SOT363-6 2 1 GPIO1 GC6_FB_EN
GND
<13> PCIE_CRX_GTX_P2 O
S
CV14 VGA@ 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_N2 AC10 PEX_TX1 IN A CV264 RV165 VGA@ D2000 VGA@ DGPU_AC_DETECT <10,36,43>
<13> PCIE_CRX_GTX_N2
4
PEX_TX1_N
2
PCIE_CRX_C_GTX_P3 GPIO2 I GPU_EVENT#
PCI EXPRESS
<13> PCIE_CRX_GTX_P3 CV15 VGA@ 1 2 0.22U_0402_16V7K AD11 UV11 1 RB751V-40_SOD323-2
CV16 VGA@ 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_N3 AC11 PEX_TX2 W5 NL17SZ08DFT2G_SC70-5 GPIO3 I/O NVVDDS_PWM
<13> PCIE_CRX_GTX_N3
3
CV17 VGA@ 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_P4 AC12 PEX_TX2_N NC AE2 VGA@ VGA@ VGA@ DGPU_CLKREQ#
0.01U_0402_16V7K
<13> PCIE_CRX_GTX_P4 PCIE_CRX_C_GTX_N4 PEX_TX3 TS_VREF TSEN_VREF GPIO4 O 1V8_MAIN_EN
VGA@ 1 2 AB12 AF2
10K_0402_5%
<13> PCIE_CRX_GTX_N4 CV18 0.22U_0402_16V7K
AB13 PEX_TX3_N NC 2 GPIO5 I FRAME_LOCK#
1
AC13 NC PEX_TX4 1 @ 2 GPIO6 O PSI
2 AD14 NC PEX_TX4_N RV166 GPIO7
2
O LCD_BL_PWM
DA-08329-001_V02 AC14
AC15
NC PEX_TX5
NC PEX_TX5_N
0_0402_5% GPIO8 O MEM_VDD_CTL
AB15 NC PEX_TX6 GPIO9 I/O THERM_ALERT
AB16 NC PEX_TX6_N B7 +1.8VSDGPU_AON
GPIO23 I2CA_SCL GPIO10 O MEM_VREF_CTL
AC16 NC PEX_TX7 A7
NC PEX_TX7_N GPIO22 I2CA_SDA GPIO11 O LCD_VDD
AD17 Add CV264 for wavefrom glitch
AC17 NC PEX_TX8 C9 NV_I2CB_SCL RV183 1 VGA@ 2 1.8K_0402_1% GPIO12 I PWR_LEVEL
AC18 NC PEX_TX8_N I2CB_SCL C8 NV_I2CB_SDA RV184 1 VGA@ 2 1.8K_0402_1% PLTRST_VGA#
NC PEX_TX9 I2CB_SDA GPIO13 O LCD_BLEN
I2C
AB18
AB19 NC PEX_TX9_N A9 NV_I2CC_SCL RV185 1 VGA@ 2 1.8K_0402_1% QV5B GPIO14 I HPD_IFPA
AC19 NC PEX_TX10 I2CC_SCL B9 NV_I2CC_SDA RV186 1 VGA@ 2 1.8K_0402_1% GPIO15 I HPD_IFPB
PJT138KA 2N SOT363-6
NC PEX_TX10_N I2CC_SDA
2
AD20 GPIO16 Reserved
NC PEX_TX11 I2CS_SCL VGA@
AC20 D9
G
AC21 NC PEX_TX11_N I2CS_SCL D8 I2CS_SDA A6_OVERT# 1 6
GPIO17 I HPD_IFPD
NC PEX_TX12 I2CS_SDA +GPU_PLLVDD GPU_OVERT# <22,36> GPIO18
AB21
D
I HPD_IFPE
AD23 NC PEX_TX12_N L2001
NearGPU GPIO19 O 3D_VISION
AE23 NC PEX_TX13 +GPU_PLLVDD 1 2
NC PEX_TX13_N +1.8VSDGPU_MAIN GPIO20 Reserved
0.1U_0201_10V6K
.1U_0402_16V7K
.1U_0402_16V7K
AF24 VGA@
22U_0603_6.3V6M
4.7U_0402_6.3V6M
NC PEX_TX14 2 2 2 1 1
AE24 XS_PLLVDD L6 C2750 C2000 C2001 C2752 C2007 PBY160808T-300Y-N_2P GPIO21 Reserved (OC_WARN)
AG24 NC PEX_TX14_N PLLVDD M6 DVT:downsize GPIO22 Reserved
AG25 NC PEX_TX15 SP_PLLVDD VGA@ VGA@ VGA@ VGA@ VGA@ SM010008A00
NC PEX_TX15_N N6 1 1 1 2 2 GPIO23 Reserved
VID_PLLVDD NC
3000ma 30ohm@100mhz DCR 0.03
R2009
10K_0402_5%
+1.8VSDGPU_AON 1 VGA@ 2 AE8 Near M6 Near L6 Near N6
<11> CLK_PCIE_P3 PEX_REFCLK
AD8
DGPU_CLKREQ# <11> CLK_PCIE_N3 PEX_REFCLK_N
AC6 2016/11/10
PEX_CLKREQ_N
PEX_TSTCLK_OUT+ C2007 change to 22uF
AF22 NC
CLK
PEX_TSTCLK_OUT- PEX_TSTCLK_OUT NC 1. NV reference design

2 @ 1 AE22 C11 XTALIN
R2010 200_0402_1% PEX_TSTCLK_OUT_N XTAL_IN B10 XTALOUT
2. Top side only 1.2mm high
XTAL_OUT
3 PLTRST_VGA# AC7 A10 XTAL_SSIN R2012 1 VGA@ 2 10K_0402_5% 3
2 VGA@ 1 PEX_TREMP AF25 PEX_RST_N XTAL_SSIN C10 XTAL_OUTBUFF R2013 1 VGA@ 2 10K_0402_5%
R2011 2.49K_0402_1% PEX_TERMP XTAL_OUTBUFF
GM108-ES-S-A1_FCBGA595
@
GC6 2.0 function
+3VS
RV113
1 VGA@ 2 GC6_FB_EN3V3
GC6_FB_EN3V3 <12>
10K_0402_5%
3
RV111 D2001
1 VGA@ 2 5 2
D
G
10K_0402_5% 1 1.35VSDGPU_PWR_EN
1.35VSDGPU_PWR_EN <40,51>
S
6
QV8A 3 VGA@
4
GC6_FB_EN1V8 2 G
D
VGA@
1
QV8B S PJT138KA 2N SOT363-6 BAV70W_SOT323-3 +1.8VSDGPU_AON

PJT138KA 2N SOT363-6 R2014
1
VGA@ 200K_0402_1% VCC: 1.65 ~ 5.5V

5
@ Push Pull Output VGA_GATE

PD at Power Side Q2001B X2000
VCC
2
2
PLTRST_VGA# 1 PJT138KA 2N SOT363-6 27MHZ_10PF_7R27000001
1VS_DGPU_PG IN B 4 VGA_GATE VGA@ R4961 VGA@
G
<52> 1VS_DGPU_PG OUT Y I2CS_SCL XTALOUT_R
2 1 6 XTALOUT 2 1 3 1 XTALIN
GND
+1.8VSDGPU_MAIN IN A 1 SOC_SML1CLK <9,36> 3 1
15P_0402_50V8J
+1.8VSDGPU_AON CV233 0_0402_5% NC NC
15P_0402_50V8J
1
UV12 @ 0.01U_0402_16V7K VGA_GATE VGA@ C2005
3
1
VCC: 1.65 ~ 5.5V NL17SZ08DFT2G_SC70-5 2 @ Q2001A VGA@ 4 2 VGA@
5
5
Push Pull Output PJT138KA 2N SOT363-6 C2004
2
R2017 VGA@
G
VCC
2
PLT_RST_BUF# 1 10K_0402_5% 1 VGA@ 2 VGA_GATE I2CS_SDA 4 3
<11,30,31> PLT_RST_BUF# IN B SOC_SML1DATA <9,36>
4SYS_PEX_RST_MON# 1 VGA@2
S
RV161
DGPU_HOLD_RST# 2 OUT Y 0_0402_5%
1 Crystals must have a max ESR of 80 ohm
GND
<12> DGPU_HOLD_RST# IN A
4 CV266 4
UV2 VGA@ +1.8VSDGPU_AON
2
NL17SZ08DFT2G_SC70-5 0.01U_0402_16V7K
3
VGA@ 2 R2019
0_0402_5% RV100
VGA@ 10K_0402_5%
@
1
PLTRST_VGA# <22> Security Classification Compal Secret Data Compal Electronics, Inc.
R2018 2 @1 10K_0402_5%
N17S PEG 1/7
CV265 1 2 0.01U_0402_16V7K AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Add CV265,CV266
@ for wavefrom glitch MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH7LW M/B LA-H791P
A B C D E
A B C D E
VRAM Interface MDA[15..0]

UGPU1 UGPU1
<26> MDA[15..0] MDA[31..16]

<26> MDA[31..16] MDA[47..32]
<27> MDA[47..32] MDA[63..48]
<27> MDA[63..48]
S IC N17S-G0-A1 BGA 595P GPU ABO ! S IC N17S-G2-A1 BGA 595P GPU ABO !
UGPU1B G0@ G2@
SA0000CC920 SA0000CCB20
Part 2 of 6
CMDA[31..0] <26,27>
MDA0 E18 C27 CMDA0
1 FBA_D00 FBA_CMD0 1
MDA1 F18 C26 CMDA1
MDA2 E16 FBA_D01 FBA_CMD1 E24 CMDA2
MDA3 F17 FBA_D02 FBA_CMD2 F24 CMDA3
MDA4 D20 FBA_D03 FBA_CMD3 D27 CMDA4
MDA5 D21 FBA_D04 FBA_CMD4 D26 CMDA5
MDA6 F20 FBA_D05 FBA_CMD5 F25 CMDA6
MDA7 E21 FBA_D06 FBA_CMD6 F26 CMDA7
MDA8 E15 FBA_D07 FBA_CMD7 F23 CMDA8
MDA9 D15 FBA_D08 FBA_CMD8 G22 CMDA9
MDA10 F15 FBA_D09 FBA_CMD9 G23 CMDA10 +1.35VSDGPU
MDA11 F13 FBA_D10 FBA_CMD10 G24 CMDA11
MDA12 C13 FBA_D11 FBA_CMD11 F27 CMDA12 +3VS
MDA13 B13 FBA_D12 FBA_CMD12 G25 CMDA13 CMDA14 2 VGA@ 1
MDA14 E13 FBA_D13 FBA_CMD13 G27 CMDA14 RV87 10K_0402_5%
MDA15 D13 FBA_D14 FBA_CMD14 G26 CMDA15 CMDA30 2 VGA@ 1
MDA16 B15 FBA_D15 FBA_CMD15 M24 CMDA16 RV88 10K_0402_5%
1
MDA17 C16 FBA_D16 FBA_CMD16 M23 CMDA17
FBA_D17 FBA_CMD17
1
MDA18 A13 K24 CMDA18 RV108
MDA19 A15 FBA_D18 FBA_CMD18 K23 CMDA19 CMDA13 2 VGA@ 1 RV106 10K_0402_5%
MDA20 B18 FBA_D19 FBA_CMD19 M27 CMDA20 RV89 10K_0402_5% 10K_0402_5% @
MDA21 A18 FBA_D20 FBA_CMD20 M26 CMDA21 CMDA29 2 VGA@ 1 @
2
MDA22 A19 FBA_D21 FBA_CMD21 M25 CMDA22 RV90 10K_0402_5%
2
MDA23 C19 FBA_D22 FBA_CMD22 K26 CMDA23
FBA_D23 FBA_CMD23 Power Side PU to +31.8VSDGPU_AON
3
MDA24 B24 K22 CMDA24
MDA25 C23 FBA_D24 FBA_CMD24 J23 CMDA25 5 G
D
RV188
MDA26 A25 FBA_D25 FBA_CMD25 J25 CMDA26 S 0_0402_5%
6
MDA27 A24 FBA_D26 FBA_CMD26 J24 CMDA27 QV7A 1 VGA@ 2 VGA_CORE_PG
4
MDA28 A21 FBA_D27 FBA_CMD27 K27 CMDA28 2 G @
D
MDA29 B21 FBA_D28 FBA_CMD28 K25 CMDA29 QV7B S
MDA30 C20 FBA_D29 FBA_CMD29 J27 CMDA30 PJT138KA 2N SOT363-6
1
MDA31 C21 FBA_D30 FBA_CMD30 J26 CMDA31 @
MDA32 R22 FBA_D31 FBA_CMD31
MDA33 R24 FBA_D32 D19 FBA_DBI0
FBA_D33 FBA_DQM0 FBA_DBI0 <26>
INTERFACE A
2 MDA34 T22 D14 FBA_DBI1 DV10 VGA@ 2

FBA_D34 FBA_DQM1 FBA_DBI2 FBA_DBI1 <26>
MDA35 R23 C17 RB751S40T1G_SOD523-2
MDA36 N25 C22 +1.8VSDGPU_AON
MDA37 N26 P24 1 2
MEMORY

MDA38 N23 W24
FBA_DBI5 <27>
VCC: 1.65 ~ 5.5V
MDA39 N24 FBA_D38 FBA_DQM5 AA25 FBA_DBI6
FBA_DBI6 <27> Push Pull Output
5
MDA40 V23 FBA_D39 FBA_DQM6 U25 FBA_DBI7 RV103
FBA_D40 FBA_DQM7 FBA_DBI7 <27>
MDA41 V22 10K_0402_1%
VCC
MDA42 T23 FBA_D41 F19 DQSA#0 T254 @ 2 @ 1 DGPU_MAIN_EN 1
FBA_D42 FBA_DQS_RN0 <21,40> 1.8VSDGPU_MAIN_EN IN B PEX_VDD_EN
MDA43 U22 C14 DQSA#1 T249 @ 1 4
FBA_D43 FBA_DQS_RN1 OUT Y PEX_VDD_EN <40,52>
MDA44 Y24 A16 DQSA#2 T252 @ 2
GND
MDA45 AA24 FBA_D44 FBA_DQS_RN2 A22 DQSA#3 T253 @ CV231 @ IN A UV10
MDA46 Y22 FBA_D45 FBA_DQS_RN3 P25 DQSA#4 T255 @ VGA@
FBA_D46 FBA_DQS_RN4 .1U_0402_16V7K
MDA47 AA23 W22 DQSA#5 T256 @ 2 NL17SZ08DFT2G_SC70-5
3
MDA48 AD27 FBA_D47 FBA_DQS_RN5 AB27 DQSA#6 T250 @
MDA49 AB25 FBA_D48 FBA_DQS_RN6 T27 DQSA#7 T251 @
MDA50 AD26 FBA_D49 FBA_DQS_RN7 DV7 VGA@
FBA_D50 FBA_EDC0 DGPU_PWR_EN <12,40>
MDA51 AC25 E19 RB751S40T1G_SOD523-2
FBA_D51 FBA_DQS_WP0 FBA_EDC1 FBA_EDC0 <26> GPU_OVERT#
MDA52 AA27 C15 1 2 PVT 03/09
FBA_D52 FBA_DQS_WP1 FBA_EDC2 FBA_EDC1 <26> <21,36> GPU_OVERT#
MDA53 AA26 B16
FBA_D53 FBA_DQS_WP2 FBA_EDC3 FBA_EDC2 <26>
MDA54 W26 B22
MDA55 Y25 R25 VGA@
MDA56 R26 W23 +1.8VSDGPU_AON RV189 1 2 2.2K_0402_5%
FBA_D56 FBA_DQS_WP5 FBA_EDC6 FBA_EDC5 <27> NVVDD_EN <53>
MDA57 T25 AB26 CV230
MDA58 N27 T26 0.1U_0201_10V6K 2 1
FBA_D58 FBA_DQS_WP7 FBA_EDC7 <27>
MDA59 R27 2 1 1
MDA60 V26 FBA_D59 @ @ DV11 CV263
FBA_D60
5
MDA61 V27 RB751S40T1G_SOD523-2 .1U_0402_16V7K
MDA62 W27 FBA_D61 QV6A VGA@
VCC
FBA_D62
3
MDA63 W25 PLTRST_VGA# 1 PJT138KA 2N SOT363-6 2
FBA_D63 <21> PLTRST_VGA# IN B
D24 4 5
D
G @
FBA_CLK0 FBA_CLK0 <26> OUT Y
F16 D25 1 @ 2 2 Near Power PWM IC
GND
+1.8VSDGPU_AON
S
+FB_PLLAVDD FB_PLLAVDD_1 FBA_CLK0_N FBA_CLK0# <26> IN A
P22 RV102
4
6
3 FB_PLLAVDD_2 N22 10K_0402_5% DV11 change to @ for wavefrom glitch 3
FBA_CLK1 FBA_CLK1 <27> VGA_CORE_PG
D23 M22 2
D
T97 @ FB_VREF G UV9
FBA_CLK1# <27> <21> GC6_FB_EN1V8 VGA_CORE_PG <53>
3
FB_VREF_PROBE FBA_CLK1_N S NL17SZ08DFT2G_SC70-5
D18 QV6B @ VCC: 1.65 ~ 5.5V
FBA_WCK01 <26>
1
R2028 H22 FB_REFPLL_AVDD FBA_WCK01 C18 PJT138KA 2N SOT363-6
FB_DLLAVDD FBA_WCK01_N FBA_WCK01# <26> Push Pull Output
10K_0402_5% D17 @
FB_CLAMP GNDS_SENSE FBA_WCK23 FBA_WCK23 <26>
1 @ 2 F3 D16
FB_CLAMP FBA_WCK23_N FBA_WCK23# <26>
T24 Thermal shutdown protection
FBA_WCK45 FBA_WCK45 <27>
R2020 60.4_0402_1% U24
FBA_CMD34 FBA_WCK45_N FBA_WCK45# <27>
1 @ 2 F22 V24 change to @ for wavefrom glitch
FBA_CMD35 FBA_CMD34 FBA_WCK67 FBA_WCK67 <27>
+1.35VSDGPU 1 @ 2 J22 V25
FBA_CMD35 FBA_WCK67_N FBA_WCK67# <27>
R2022 60.4_0402_1%
@
+1.8VSDGPU_MAIN
15+55mA
Place Under F16 P22
1
L2002
2 VGA@
PBY160808T-300Y-N_2P
+FB_PLLAVDD
NV 15x DG-06803-V03
22U_0603_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
NV 16x DG-07158-V04
VGA@
VGA@
VGA@
VGA@
.1U_0402_16V7K
.1U_0402_16V7K
1 1 1 1 1
C2008 DA-08329-001_V01
C2011
C2010
C2009
C2736
VGA@
2 2 2 2 2
4 4
Place Near GPU Place Under H22

SM010008A00 3000ma 30ohm@100mhz DCR 0.03

N17S VRAM 2/7
A B C D E
A B C D E
+GPU_PLLVDD +1.8VSDGPU_AON
MULTI LEVEL STRAPS
UGPU1C
strap0 strap1 strap2 strap3 strap4 strap5
Part 3 of 6 F11 C2751 1 2 0.1U_0201_10V6K
GPCPLL_AVDD NC
1
AC3 AD10 VGA@
AC4 NC IFPA_L3 NC AD7 R2029 R2030 R2031 R2032 R2033 R4972 R2035 R2036 R2037
Y4 NC IFPA_L3_N NC B19 @ @ @ @ @ @ VGA@ VGA@ VGA@
Near F11
Y3 NC IFPA_L2 FBA_CMD32 V5 100K_0402_5% 4.99K_0402_1% 10K_0402_1% 4.99K_0402_1% 10K_0402_1% 10K_0402_1% 100K_0402_5% 100K_0402_5% 100K_0402_5%
AA3 NC IFPA_L2_N RSV_XVDD_63 NC
V6
2
AA2 NC IFPA_L1 RSV_XVDD_64 NC
G1
AB1 NC IFPA_L1_N XVDD NC G2 STRAP0
NC IFPA_L0 XVDD NC
NC
AA1 G3 STRAP1
AA4 NC IFPA_L0_N XVDD NC G4 STRAP2 ROM_SI
AA5 NC IFPA_AUX_SCL XVDD NC G5 STRAP3 ROM_SO
1 NC IFPA_AUX_SDA_N XVDD NC G6 STRAP4 ROM_SCLK 1
XVDD NC G7 STRAP5
AB5 XVDD NC V1
NC IFPB_L3 XVDD NC
AB4 IFPB_L3_N V2
1
AB3 NC XVDD NC W1
NC IFPB_L2 XVDD NC
AB2 IFPB_L2_N W2 R2038 R2039 R2040 R2041 R2042 R4971 R2044 R2045 R2046
AD3 NC XVDD NC W3 @ @ @ VGA@ VGA@ VGA@ @ @ VGA@
NC IFPB_L1 XVDD NC
AD2 IFPB_L1_N W4 4.99K_0402_1% 45.3K_0402_1% 15K_0402_1% 100K_0402_5% 100K_0402_5% 100K_0402_5% 4.99K_0402_1% 4.99K_0402_1% 100K_0402_5%
AE1 NC XVDD NC
IFPB_L0
2
AD1 NC
IFPB_L0_N
AD4 NC
NC IFPB_AUX_SCL
AD5 IFPB_AUX_SDA_N D11 GPU_BUFRST# PAD @ T284
NC BUFRST_N N17X Straps N16X Straps
NC NC D10
T2
NC XVDD VRAM_VDD_CTL
T3 E9 PAD @ T292
NC XVDD GPIO8
T1
NC XVDD
R1 E10
NC XVDD NC
GENERAL
R2
LVDS/TMDS
NC XVDD
R3 F10 N17S no spport VRAM voltage contral
NC XVDD NC
N2
N3 NC XVDD Multi strap table MX230/250 Decive ID : N17S-G0/G2-A1 0x1D11/0x1D13
NC XVDD GPU VRAM RANK X76 Freq Memory Size Memory Config ROM_SI ROM_SO ROM_SCLK
D1 STRAP0 strap0 strap1 strap2 strap3 strap4 strap5
STRAP0 Voltage
D2 STRAP1
V3 STRAP1 E4 STRAP2 X76xxxxxxx PU 100K
V4 NC XVDD STRAP2 E3 STRAP3 0x4 (SA00009TV50) Micron MT51J256M32HF-70:B PD 100K PD 100K
U3 NC XVDD STRAP3 D3 STRAP4 PU 100K PU 100K
U4 NC XVDD STRAP4 C1 STRAP5 0x5 (SA00009U160) Hynix H5GC8H24AJR-R0C PD 100K
NC XVDD STRAP5 NC
T4
NC XVDD N17S-G0 +1.35V 0x0 (SA00009TA10) Samsung K4G80325FB-HC25 PD 100K PD 100K
T5 N17S-G2 SR PD 100K
PU 100K
R4 NC XVDD NC F6
NC XVDD MULTI_STRAP_REF0_GND 3.0GHz PD 100K PU 100K PU 100K
R5 F4 256Mx32x2 PD 100K
NC XVDD VDDS_SENSE NC
F5 2G
2 NC NC PD 100K PD 100K PD 100K 2
N1
NC XVDD
M1 PD 100K PU 100K PD 100K
NC XVDD
M2 F12
NC XVDD THERMDP
M3 PU 100K PD 100K PD 100K
NC XVDD
K2 E12
NC XVDD THERMDN
K3
NC XVDD
K1
NC XVDD
J1
NC XVDD
M4 F2 VCCSENSE_VGA
NC XVDD VDD_SENSE VCCSENSE_VGA <53>
M5
NC XVDD
L3
NC XVDD
L4
NC XVDD
K4
NC XVDD
K5
J4 NC XVDD F1 VSSSENSE_VGA
NC XVDD GND_SENSE VSSSENSE_VGA <53>
J5
N4 NC XVDD
N5 NC XVDD TEST
NC XVDD
P3 AD9 TESTMODE R2054 1 VGA@ 2 10K_0402_5%
P4 NC XVDD NVJTAG_SEL TESTMODE
AE5 JTAG_TCK_VGA PAD @ T258
NC XVDD JTAG_TCK AE6 JTAG_TDI PAD @ T257
JTAG_TDI AF6 JTAG_TDO PAD @ T260
J2 JTAG_TDO AD6 JTAG_TMS PAD @ T259
J3 NC XVDD JTAG_TMS AG4 JTAG_RST R2053 1 VGA@ 210K_0402_5%
NC XVDD JTAG_TRST_N
3 3
H3
H4 NC XVDD
NV 17S DG-07785-001_V07
NC XVDD SERIAL
D12
ROM_CS_N B12 ROM_SI
ROM_SI A12 ROM_SO
ROM_SO C12 ROM_SCLK
ROM_SCLK
DA-08329-001_V02
@
4 4

N17S LVDS 3/7
A B C D E
A B C D E
DA-08329-001_V02
NV 16x DG-07158-V05 NV 16x DG-07158-V05
1 1
+1.35VSDGPU
UGPU1D +1.8VSDGPU_MAIN NV 16x DG-07158-V05
3.24A Part 4 of 6
1.275A
B26 PEX_HVDD AA10
FBVDDQ_01 PEX_IOVDDQ_1
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
C25 AA12
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
VGA@
VGA@ C2732
VGA@ C2733
VGA@ C2727
VGA@ C2726
VGA@ C2039
VGA@ C2040
VGA@ C2032
VGA@ C2033
VGA@ C2021
VGA@ C2022
E23 AA13
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 2 2 1 1 1 1 1 1 1
1
1
E26 FBVDDQ_03 PEX_IOVDDQ_3 AA16
F14 FBVDDQ_04 PEX_IOVDDQ_4 AA18
F21 FBVDDQ_05 PEX_IOVDDQ_5 AA19
2
2
2 2 2 2 2 2 1 1 FBVDDQ_06 PEX_IOVDDQ_6 2 2 2 2 2 2 2
C2013
C2737
C2754
C2755
C2014
C2738
C2016
C2739
C2017
G13 AA20
G14
G15
FBVDDQ_07
FBVDDQ_08
PEX_IOVDDQ_7
PEX_IOVDDQ_8
AA21
AB22
NV 16x DG-07158-V05
Under GPU G16 FBVDDQ_09 PEX_IOVDDQ_9 AC23
FBVDDQ_10 PEX_IOVDDQ_10 Under GPU Near GPU
G18 AD24
G19 FBVDDQ_11 PEX_IOVDDQ_11 AE25
10U_0402_6.3V6M
VGA@ C2734
VGA@ C2735
VGA@ C2045
VGA@ C2047
G20 AF26
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1 1 1 1 FBVDDQ_13 PEX_IOVDDQ_13 Midway GPU & Power supply
Under GPU G21 AF27
H24 FBVDDQ_14 FBVDDQ PEX_IOVDDQ_14
H26 FBVDDQ_AON
Near GPU Midway GPU & Power supply
2
2 2 2 J21 FBVDDQ_AON PEX_DVDD AA22

FBVDDQ_AON PEX_IOVDD_1 +1.0VSDGPU
K21 AB23
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
FBVDDQ_AON PEX_IOVDD_2
VGA@ C2740
VGA@ C2741
VGA@ C2742
VGA@ C2743
VGA@ C2744
VGA@ C2745
VGA@ C2746
L22 AC24
1U_0201_6.3V6M
FBVDDQ_19 PEX_IOVDD_3 1 1 1 1 1
1
Near GPU L24 AD25
POWER
L26 FBVDDQ_20 PEX_IOVDD_4 AE26
M21 FBVDDQ_21 PEX_IOVDD_5 AE27
2
2 N21 FBVDDQ_22 PEX_IOVDD_6 2 2 2 2 2 2
R21 FBVDDQ_23
T21 FBVDDQ_24
RV156 +1.35VSDGPU V21 FBVDDQ_25 +1.8VSDGPU_AON
0_0402_5% W21 FBVDDQ_26
FBVDDQ_27 Under GPU
1 @ 2 1V8_AON G10
<51> FB_VDDQ_SENSE 1V8_AON3V3_AON G12
0.1U_0201_10V6K
0.1U_0201_10V6K
56mA
4.7U_0402_6.3V6M
VDD18 3V3_AON DA-08329-001_V01
VGA@ C2048
VGA@ C2753
VGA@ C2049
VGA@ C2050
G8
1U_0201_6.3V6M
Near DGPU VDD18 VDD33_3 G9
2 2 1 1
DA-08329-001_V02 VDD33_4
V7 1 1 2 2
W7 NC +1.35VSDGPU
AA6 NC
W6 NC FB_CAL_PD_VDDQ D22 FB_CAL_PD_VDDQ 1 VGA@ 2
NC FB_CAL_PD_VDDQ Under GPU Near GPU
Y6 40.2_0402_1% R2078 +1.8VSDGPU_MAIN
NC
FB_CAL_PU_GND C24 FB_CAL_PU_GND 1 VGA@ 2
FB_CAL_PU_GND 40.2_0402_1% R2079
0.1U_0201_10V6K
0.1U_0201_10V6K
4.7U_0402_6.3V6M
B25 FB_CAL_TERM_GND 2 VGA@
C2051
C2052
VGA@ C2053
VGA@ C2054
M7 FB_CAL_TERM_GND 1
1U_0201_6.3V6M
NC FB_CAL_TERM_GND 2 2 1 1
N7 60.4_0402_1% R2080
T6 NC
P6 NC
NC 1 1 2 2
VGA@
VGA@
T7
R7 IFPD_PLLVDD_2 +1.8VSDGPU_MAIN
Under GPU Near GPU NV 16x DG-07158-V05
U6 NC
R6 IFPD_RSET AA8
286mA
NC PEX_PLL_HVDD_1 AA9
0.1U_0201_10V6K
PEX_PLL_HVDD_2
C2034
2
3 NC AB8 DVT:downsize 3
PEX_SVDD_3V3
Near GPU 1
VGA@
J7
K7 NC
K6 NC NC AA14
H6 NC NC PEX_PLLVDD_1 AA15
J6 NC PEX_PLLVDD_2
NC
@
NV 16x DG-07158-V05
4 4

N17S POWER & GND 4/7
A B C D E
A B C D E
NV 16x DG-07158-V05
UGPU1F
+VGA_CORE +VGA_CORE
Part 6 of 6
UGPU1E K10 V18

K12 VDD_001 VDD_041 V16
A2 Part 5 of 6 K11 K14 VDD_002 VDD_040 V14
A26 GND_001 GND_057 K13 K16 VDD_003 VDD_039 V12
AB11 GND_002 GND_058 K15 K18 VDD_004 VDD_038 V10
1 GND_003 GND_059 VDD_005 VDD_037 1
AB14 K17 L11 U17
POWER
AB17 GND_004 GND_060 L10 L13 VDD_006VDDS VDDS VDD_036 U15
AB20 GND_005 GND_061 L12 L15 VDD_007 VDD_035 U13
AB24 GND_006 GND_062 L14 L17 VDD_008 VDD_034 U11
GND_007 GND_063 VDD_009VDDS VDDS VDD_033
AC2 L16 M10 T18
AC22 GND_008 GND_064 L18 M12 VDD_010 VDD_032 T16
GND_010 GND_066 VDD_012VDDS VDDS VDD_030
AC5 L23 M16 T12
AD12 GND_012 GND_068 L5 N11 VDD_014 VDD_028 R17
AD13 GND_013 GND_069 M11 N13 VDD_015 VDD_027 R15
AD18 GND_016 GND_072 M17 P10 VDD_018 VDD_024 P18
AD19 GND_017 GND_073 N10 P12 VDD_019 VDDS VDDS VDD_023 P16
AD21 GND_018 GND_074 N12 VDD_020 VDDS VDDS VDD_022 P14
AD22 GND_019 GND_075 N14 VDD_021
AE11 GND_020 GND_076 N16
AE14 GND_021 GND_077 N18
AE17 GND_022 GND_078 P11
AE20 GND_023 GND_079 P13
AF1 GND_024 GND_080 P15
AF11 GND_025 GND_081
DA-07750-000-V02
GND
P17
AF14 GND_026 GND_082 P2
AF17 GND_027 GND_083 P23
AF20
AF23
GND_028
GND_029
GND_084
GND_085
P26
P5
@
DA-08329-001_V01
AF5 GND_030 GND_086 R10
AF8 GND_031 GND_087 R12
AG2 GND_032 GND_088 R14
AG26 GND_033 GND_089 R16
B1 GND_034 GND_090 R18
B11 GND_035 GND_091 T11
2 B14 GND_036 GND_092 T13 2
B17 GND_037 GND_093 T15
B20 GND_038 GND_094 T17
B23 GND_039 GND_095 U10
B27 GND_040 GND_096 U12
B5 GND_041 GND_097 U14
B8 GND_042 GND_098 U16
E11 GND_043 GND_099 U18
E14 GND_044 GND_100 U2
E17 GND_045 GND_101 U23
E2 GND_046 GND_102 U26
E20 GND_047 GND_103 U5
E22 GND_048 GND_104 V11
E25 GND_049 GND_105 V13
E5 GND_050 GND_106 V15
E8 GND_051 GND_107 V17
H2 GND_052 GND_108 Y2
H23 GND_053 GND_109 Y23
H25 GND_054 GND_110 Y26
H5 GND_055 GND_111 Y5
GND_056 GND_112
AA7
GND AB7
GND
@
3 3
DA-07751-000-V02
SP-08318-001_V03
4 4

N17S POWER & GND 5/7
A B C D E
A B C D E
GDDR5 Mode H Mapping

VRAM GDDR5 chips
MDA[63..0] Address 0..31
DATA Bus
32..63
Channel 0 BOT SIDE
<22,27> MDA[63..0]
CMDA[31..0] CMD0 CS#
<22,27> CMDA[31..0]
UV13 @ MF=0
CMD1 A3_BA3
MF=0 MF=1 MF=1 MF=0
CMD2 A2_BA0
A4 MDA0
FBA_EDC0 C2 DQ24 DQ0 A2 MDA1
CMD3 A4_BA2 <22> FBA_EDC0 FBA_EDC1 EDC0 EDC3 DQ25 DQ1
C13 B4 MDA2
X76 for N17S 2G VRAM CMD4 A5_BA1
<22> FBA_EDC1 FBA_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 MDA3 BYTE0
<22> FBA_EDC2 FBA_EDC3 R2 EDC2 EDC1 DQ27 DQ3 E4 MDA4
<22> FBA_EDC3 EDC3 EDC0 DQ28 DQ4
CMD5 WE# E2 MDA5
1
ZZZ DQ29 DQ5 F4 MDA6 1
FBA_DBI0 D2 DQ30 DQ6 F2 MDA7
X76VSAM@ CMD6 A7_A8 <22> FBA_DBI0 FBA_DBI1 DBI0# DBI3# DQ31 DQ7
D13 A11 MDA8
<22> FBA_DBI1 FBA_DBI2 P13 DBI1# DBI2# DQ16 DQ8 A13
CMD7 A6_A11 MDA9
<22> FBA_DBI2 FBA_DBI3 DBI2# DBI1# DQ17 DQ9
Samsung_256Mx32x2 P2 B11 MDA10
<22> FBA_DBI3 DBI3# DBI0# DQ18 DQ10
X76829BOL03 CMD8 ABI# B13 MDA11 BYTE1
FBA_CLK0 J12 DQ19 DQ11 E11 MDA12
<22> FBA_CLK0 FBA_CLK0# CK DQ20 DQ12
CMD9 A12_RFU J11 E13 MDA13
<22> FBA_CLK0# J3 CK# DQ21 DQ13 F11
ZZZ CMDA14 MDA14
CKE# DQ22 DQ14 F13
X76VHYN@ CMD10 A0_A10 DQ23 DQ15
MDA15
U11 MDA16
CMDA2 H11 DQ8 DQ16 U13 MDA17
CMD11 A1_A9 BA0/A2 BA2/A4 DQ9 DQ17
Hynix_256Mx32x2 CMDA4 K10 T11 MDA18
CMDA3 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 MDA19
X76829BOL01 CMD12 RAS# BA2/A4 BA0/A2 DQ11 DQ19 BYTE2
CMDA1 H10 N11 MDA20
BA3/A3 BA1/A5 DQ12 DQ20 N13 MDA21
CMD13 RST# DQ13 DQ21
ZZZ M11 MDA22
K4 DQ14 DQ22 M13
X76VMIC@ CMD14 CKE# CMDA6
A8/A7 A10/A0 DQ15 DQ23
MDA23
CMDA11 H5 U4 MDA24
H4 A9/A1 A11/A6 DQ0 DQ24 U2
CMD15 CAS# CMDA10
A10/A0 A8/A7 DQ1 DQ25
MDA25
Micron_256Mx32x2 CMDA7 K5 T4 MDA26
CMDA9 J5 A11/A6 A9/A1 DQ2 DQ26 T2 MDA27
X76829BOL02 CMD16 CS# A12/RFU/NC DQ3 DQ27 BYTE3
N4 MDA28
A5 DQ4 DQ28 N2 MDA29
CMD17 A3_BA3 VPP/NC DQ5 DQ29
U5 M4 MDA30
VPP/NC DQ6 DQ30 M2 MDA31
CMD18 A2_BA0 DQ7 DQ31
CMD19 A4_BA2 RV131 2 VGA@ 1 1K_0402_1% J1 +1.35VSDGPU
J10 MF
J13 SEN B1
CMD20 A5_BA1 ZQ VDDQ
RV132 2 VGA@ 1 121_0402_1% D1
VDDQ F1
CMD21 WE# VDDQ
CMDA8 J4 M1
CMDA12 G3 ABI# VDDQ P1
CMD22 A7_A8 RAS# CAS# VDDQ
CMDA0 G12 T1
CMDA15 L3 CS# WE# VDDQ G2
CMD23 A6_A11 CAS# RAS# VDDQ
CMDA5 L12 L2
WE# CS# VDDQ B3
2 CMD24 ABI# VDDQ
2
D3
VDDQ F3
CMD25 A12_RFU FBA_WCK01# VDDQ
D5 H3
<22> FBA_WCK01# FBA_WCK01 D4 WCK01# WCK23# VDDQ K3
CMD26 A0_A10 <22> FBA_WCK01 WCK01 WCK23 VDDQ M3
FBA_WCK23# P5 VDDQ P3
CMD27 A1_A9 <22> FBA_WCK23# FBA_WCK23 WCK23# WCK01# VDDQ
P4 T3
<22> FBA_WCK23 WCK23 WCK01 VDDQ
CMD28 RAS# E5
VDDQ N5
A10 VDDQ E10
CMD29 RST# VREFD VDDQ
U10 N10
+FBA_VREFC0 J14 VREFD VDDQ B12
CMD30 CKE# VREFC VDDQ D12
VDDQ F12
CMD31 CAS# VDDQ H12
CMDA13 J2 VDDQ K12
RESET# VDDQ M12
VDDQ P12
VDDQ T12
FBA_CLK0 FBA_CLK0# VDDQ G13
H1 VDDQ L13
VSS VDDQ
1
K1 B14
RV63 RV95 B5 VSS VDDQ D14
40.2_0402_1% 40.2_0402_1% G5 VSS VDDQ F14
VGA@ VGA@ L5 VSS VDDQ M14
T5 VSS VDDQ P14
2
B10 VSS VDDQ T14

D10 VSS VDDQ
1 VSS
0.01U_0402_16V7K
VGA@ G10
VSS
CV190
L10 A1
+1.35VSDGPU P10 VSS VSSQ C1
2 T10 VSS VSSQ E1
H14 VSS VSSQ N1
VSS VSSQ
1
RV136 K14 R1
549_0402_1% +1.35VSDGPU VSS VSSQ U1
VGA@ VSSQ H2
G1 VSSQ K2
3 +FBA_VREFC0 <27> VDD VSSQ 3
RV135 L1 A3
2
931_0402_1% G4 VDD VSSQ C3

FBA_VREFC_L 1 2 +FBA_VREFC0 L4 VDD VSSQ E3
C5 VDD VSSQ N3
VGA@ R5 VDD VSSQ R3
VDD VSSQ
1
1 C10 U3
RV56 R10 VDD VSSQ C4
VDD VSSQ
1
D 1.33K_0402_1% CV195 D11 R4

2 QV3 VGA@ 820PF_0402_50V7K G11 VDD VSSQ F5
<21> VRAM_VREF_CTL 2 VGA@ VDD VSSQ
G BSS138W-7-F_SOT323-3 L11 M5
2
VGA@ P11 VDD VSSQ F10

S
3
G14 VDD VSSQ M10

L14 VDD VSSQ C11
VDD VSSQ R11
VSSQ A12
VSSQ C12
VSSQ E12
VSSQ N12
VSSQ R12
170-BALL VSSQ U12
VSSQ H13
SGRAM GDDR5 VSSQ K13
VSSQ A14
VSSQ C14
DA8335 Cap Q'ty VSSQ E14
+1.35VSDGPU +1.35VSDGPU 22U x2 VSSQ N14
10U x 6 VSSQ R14
VSSQ
1U x 10 VSSQ
U14
22U x 3 (unPOP) H5GC4H24AJR-R0C_BGA170
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
VGA@ CV76
VGA@ CV192
VGA@ CV197
VGA@ CV198
VGA@ CV199
VGA@ CV200
1 1
1
1
VGA@ CV72
VGA@ CV196
2 2
4 4
+1.35VSDGPU
CV201
CV202
CV203
CV204
CV205
CV207
CV206
CV208
CV210
CV209
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1

VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
2 2 2 2 2 2 2 2 2 2 2018/12/27 2019/12/27 Title

N17S Lower Rank0 6/7
A B C D E
A B C D E
GDDR5 Mode H Mapping

VRAM GDDR5 chips
MDA[63..0] Address 0..31
DATA Bus
32..63
Channel 1 BOT SIDE
<22,26> MDA[63..0]
CMDA[31..0] CMD0 CS#
<22,26> CMDA[31..0]
UV15 @ MF=1
CMD1 A3_BA3
MF=0 MF=1 MF=1 MF=0
CMD2 A2_BA0
A4 MDA56
FBA_EDC7 C2 DQ24 DQ0 A2 MDA57
CMD3 A4_BA2 <22> FBA_EDC7 FBA_EDC6 EDC0 EDC3 DQ25 DQ1
C13 B4 MDA58
<22> FBA_EDC6 FBA_EDC5 EDC1 EDC2 DQ26 DQ2
CMD4 A5_BA1 R13 B2 MDA59 BYTE7
<22> FBA_EDC5 FBA_EDC4 R2 EDC2 EDC1 DQ27 DQ3 E4 MDA60
<22> FBA_EDC4 EDC3 EDC0 DQ28 DQ4
CMD5 WE# E2 MDA61
1 DQ29 DQ5 F4 MDA62 1
FBA_DBI7 D2 DQ30 DQ6 F2 MDA63
CMD6 A7_A8 <22> FBA_DBI7 FBA_DBI6 DBI0# DBI3# DQ31 DQ7
D13 A11 MDA48
<22> FBA_DBI6 FBA_DBI5 P13 DBI1# DBI2# DQ16 DQ8 A13
CMD7 A6_A11 MDA49
<22> FBA_DBI5 FBA_DBI4 DBI2# DBI1# DQ17 DQ9
P2 B11 MDA50
<22> FBA_DBI4 DBI3# DBI0# DQ18 DQ10
CMD8 ABI# B13 MDA51 BYTE6
FBA_CLK1 J12 DQ19 DQ11 E11 MDA52
<22> FBA_CLK1 FBA_CLK1# CK DQ20 DQ12
CMD9 A12_RFU J11 E13 MDA53
<22> FBA_CLK1# J3 CK# DQ21 DQ13 F11
CMDA30 MDA54
CKE# DQ22 DQ14 F13
CMD10 A0_A10 DQ23 DQ15
MDA55
U11 MDA40
CMDA19 H11 DQ8 DQ16 U13 MDA41
CMD11 A1_A9 BA0/A2 BA2/A4 DQ9 DQ17
CMDA17 K10 T11 MDA42
CMDA18 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 MDA43
CMD12 RAS# BA2/A4 BA0/A2 DQ11 DQ19 BYTE5
CMDA20 H10 N11 MDA44
BA3/A3 BA1/A5 DQ12 DQ20 N13 MDA45
CMD13 RST# DQ13 DQ21 M11 MDA46
K4 DQ14 DQ22 M13
CMD14 CKE# CMDA26
A8/A7 A10/A0 DQ15 DQ23
MDA47
CMDA23 H5 U4 MDA32
H4 A9/A1 A11/A6 DQ0 DQ24 U2
CMD15 CAS# CMDA22
A10/A0 A8/A7 DQ1 DQ25
MDA33
CMDA27 K5 T4 MDA34
CMDA25 J5 A11/A6 A9/A1 DQ2 DQ26 T2 MDA35
CMD16 CS# A12/RFU/NC DQ3 DQ27 BYTE4
N4 MDA36
A5 DQ4 DQ28 N2 MDA37
CMD17 A3_BA3 +1.35VSDGPU VPP/NC DQ5 DQ29
U5 M4 MDA38
VPP/NC DQ6 DQ30 M2 MDA39
CMD18 A2_BA0 DQ7 DQ31
CMD19 A4_BA2 RV140 2 VGA@ 1 1K_0402_1% J1 +1.35VSDGPU
FBA_SEN2 J10 MF
J13 SEN B1
CMD20 A5_BA1 ZQ VDDQ
RV141 2 VGA@ 1 121_0402_1% D1
VDDQ F1
CMD21 WE# VDDQ
CMDA24 J4 M1
CMDA31 G3 ABI# VDDQ P1
CMD22 A7_A8 RAS# CAS# VDDQ
CMDA21 G12 T1
CMDA28 L3 CS# WE# VDDQ G2
CMD23 A6_A11 CAS# RAS# VDDQ
CMDA16 L12 L2
WE# CS# VDDQ B3
2 CMD24 ABI# VDDQ
2
D3
VDDQ F3
CMD25 A12_RFU FBA_WCK67# VDDQ
D5 H3
<22> FBA_WCK67# FBA_WCK67 D4 WCK01# WCK23# VDDQ K3
CMD26 A0_A10 <22> FBA_WCK67 WCK01 WCK23 VDDQ M3
FBA_WCK45# P5 VDDQ P3
CMD27 A1_A9 <22> FBA_WCK45# FBA_WCK45 WCK23# WCK01# VDDQ
P4 T3
<22> FBA_WCK45 WCK23 WCK01 VDDQ
CMD28 RAS# E5
VDDQ N5
A10 VDDQ E10
CMD29 RST# VREFD VDDQ
U10 N10
+FBA_VREFC0 J14 VREFD VDDQ B12
CMD30 CKE# <26> +FBA_VREFC0 VREFC VDDQ D12
VDDQ F12
CMD31 CAS# 1 VDDQ H12
CMDA29 J2 VDDQ K12
CV229 RESET# VDDQ M12
820PF_0402_50V7K 2 VDDQ P12
VGA@ VDDQ T12
VDDQ G13
H1 VDDQ L13
K1 VSS VDDQ B14
FBA_CLK1 FBA_CLK1# B5 VSS VDDQ D14
G5 VSS VDDQ F14
VSS VDDQ
1
L5 M14
RV96 RV62 T5 VSS VDDQ P14
40.2_0402_1% 40.2_0402_1% B10 VSS VDDQ T14
VGA@ VGA@ D10 VSS VDDQ
G10 VSS
2
L10 VSS A1
P10 VSS VSSQ C1
1 VSS VSSQ
0.01U_0402_16V7K
VGA@ T10 E1
VSS VSSQ
CV191
H14 N1
K14 VSS VSSQ R1
2 +1.35VSDGPU VSS VSSQ U1
VSSQ H2
G1 VSSQ K2
3
L1 VDD VSSQ A3 3
G4 VDD VSSQ C3
L4 VDD VSSQ E3
C5 VDD VSSQ N3
R5 VDD VSSQ R3
C10 VDD VSSQ U3
R10 VDD VSSQ C4
D11 VDD VSSQ R4
G11 VDD VSSQ F5
+1.35VSDGPU +1.35VSDGPU L11 VDD VSSQ M5
P11 VDD VSSQ F10
G14 VDD VSSQ M10
L14 VDD VSSQ C11
VDD VSSQ R11
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
VSSQ A12
VGA@ CV217
VGA@ CV218
VGA@ CV219
VGA@ CV220
VGA@ CV221
VGA@ CV222
1 1 VSSQ
1
C12
VGA@ CV215
VGA@ CV216
VSSQ E12
VSSQ N12
2
2 2 VSSQ R12
VSSQ U12
DA8335 Cap Q'ty 170-BALL
VSSQ H13
22U x2 SGRAM GDDR5 VSSQ K13
10U x 6 VSSQ A14
VSSQ
1U x 10 VSSQ
C14
+1.35VSDGPU E14
22U x 3 (unPOP) VSSQ N14
VSSQ R14
VSSQ U14
VSSQ
CV223
CV224
CV225
CV226
CV228
CV212
CV227
CV211
CV213
CV214
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 H5GC4H24AJR-R0C_BGA170
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
2 2 2 2 2 2 2 2 2 2
4 4

N17S Lower Rank1 7/7
A B C D E
A B C D E
LCD POWER CIRCUIT

+3VS +LCDVDD +19VB +INVPW R_B+ Place closed to JEDP1
UX1
5 1 W=80mils +LCDVDD
W=60mils W=60mils
1U_0201_6.3V6M
IN OUT LX1 +3VS

1
CX1 2 1 1 HCB2012KF-221T30_0805
GND CX4 1 2
1 4 3 0.1U_0201_10V6K 3S@ 1 1 1
2 EN OC
1000P_0402_50V7K
CX5
@ SM01000EJ00 3000ma 1 1
SY6288C20AAC_SOT23-5 CX3 2 2 CX2 CX6 CX7
220ohm@100mhz
4.7U_0402_6.3V6M DCR 0.04 68P_0402_50V8J 0.1U_0201_10V6K .1U_0402_16V7K
2 2
@EMI@
@EMI@ @
<7> SOC_ENVDD 2 2
1
RX9
100K_0402_5%
@
2
Note: Unmount LX1 when panel boost

circuit was use. (2S battery cell)
<7> EDP_TXP0
CX8 1 2 .1U_0402_16V7K EDP_TXP0_C
EDP_TXN0_C
LED PANEL Conn.
CX9 1 2 .1U_0402_16V7K
<7> EDP_TXN0 EDP_TXP1_C
CX10 1 2 .1U_0402_16V7K
<7> EDP_TXP1 EDP_TXN1_C
CX11 1 2 .1U_0402_16V7K
<7> EDP_TXN1 EDP_TXP2_C CONN@
CX17 1 2 .1U_0402_16V7K
<7> EDP_TXP2 EDP_TXN2_C +INVPW R_B+
CX16 1 2 .1U_0402_16V7K W=60mils
<7> EDP_TXN2 EDP_TXP3_C
CX19 1 2 .1U_0402_16V7K 1
<7> EDP_TXP3 EDP_TXN3_C 1
CX18 1 2 .1U_0402_16V7K 2 41
<7> EDP_TXN3 2 G1
3 42
CX14 1 2 .1U_0402_16V7K EDP_AUXP_C 4 3 G2 43
<7> EDP_AUXP EDP_AUXN_C 4 G3
<7> EDP_AUXN CX15 1 2 .1U_0402_16V7K 5 44
SOC_BKL_PW M RX1 1 @ 2 100K_0402_5% SOC_BKL_PW M 6 5 G4 45
<7> SOC_BKL_PW M 6 G5
2 BKOFF# 7 46 2
+3VS @EMI@ +LCDVDD EDP_HPD 8 7 G6
CX12 1 2 220P_0402_50V7K 9 8
100K_0402_5% 1 @ 2 RX3 EDP_AUXN_C @EMI@ 10 9
100K_0402_5% 1 @ 2 RX4 EDP_AUXP_C BKOFF# CX13 1 2 220P_0402_50V7K
W=60mils 11 10
<36> BKOFF# 11
12
RX2 1 @ 2 10K_0402_5% 13 12
EDP_AUXN_C 14 13
EDP_AUXP_C 15 14
16 15
EDP_TXP0_C 17 16
EDP_TXN0_C 18 17
19 18
2 @ 1 EDP_HPD EDP_TXP1_C 20 19
<7> CPU_EDP_HPD EDP_TXN1_C 20
RX5 0_0402_5% 21
Touch Screen RX6
EDP_TXP2_C
22 21
22
100K_0402_5% 23
+5VS +3VS +TS_PW R 2 1 EDP_TXN2_C 24 23
25 24
RX7 1 @ 2 0_0603_5% EDP_TXP3_C 26 25
RX8 1 @ 2 0_0603_5% EDP_TXN3_C 27 26
28 27
USB20_P3 29 28
<13> USB20_P3 USB20_N3 29
30
<13> USB20_N3 30
31
32 31
Touch +TS_PW R 32
Screen 33
TS_EN 34 33
<12,36> TS_EN 34
35
3 Camera +3VS USB20_N7_CAMERA
USB20_P7_CAMERA
36 35
36
3
For 37
38 37
USB20_N7 USB20_N7_CAMERA Camera DMIC_CLK_R 38
RX10 1 @ 2 0_0402_5% 39
<13> USB20_N7 <32> DMIC_CLK_R DMIC_DATA_R 39
40
<32> DMIC_DATA_R 40
USB20_P7 RX11 1 @ 2 0_0402_5% USB20_P7_CAMERA
<13> USB20_P7 JEDP1
DMIC_DATA_R
DMIC_CLK_R STARC_107K40-000001-G2
SP010014B10
2
DX1
@ESD@
YSLC05CH_SOT23-3
1
4 4

eDP Connector
A B C D E
A B C D E
+5VS W=40mils +HDMI_5V_OUT

HDMI_C_CLKN 2 1 HDMI_R_CLKN
RY28 1 2 2.2K_0402_5% SOC_DP2_CTRL_CLK RY40 5.6_0402_5%
UY1 +3VS
2
EMI@
RY29 1 2 2.2K_0402_5% SOC_DP2_CTRL_DATA RY48
3 @EMI@ 360_0402_5%
OUT
1
1 RY27 1 2 2.2K_0402_5% HDMI_CTRL_DAT
+HDMI_5V_OUT
1
IN CY9 HDMI_C_CLKP 2 1 HDMI_R_CLKP
2 0.1U_0201_10V6K RY30 1 2 2.2K_0402_5% HDMI_CTRL_CLK RY41 5.6_0402_5%
GND 2
EMI@
1 1
AP2330W -7_SC59-3 HDMI_C_TX_N0 2 1 HDMI_R_TX_N0
RY42 5.6_0402_5%
2
EMI@
RY49
@EMI@ 360_0402_5%
port 0, 2 swap for INTEL HDMI
<7> SOC_DP2_P2 CY14 2 1 0.1U_0201_10V6K HDMI_C_TX_P0 RY31 1 2 470_0402_5%
1
<7> SOC_DP2_N2 CY15 2 1 0.1U_0201_10V6K HDMI_C_TX_N0 RY32 1 2 470_0402_5%
HDMI_C_TX_P0 2 1 HDMI_R_TX_P0
<7> SOC_DP2_P1 CY12 2 1 0.1U_0201_10V6K HDMI_C_TX_P1 RY33 1 2 470_0402_5% RY43 5.6_0402_5%
<7> SOC_DP2_N1 CY13 2 1 0.1U_0201_10V6K HDMI_C_TX_N1 RY34 1 2 470_0402_5% EMI@
<7> SOC_DP2_P0 CY10 2 1 0.1U_0201_10V6K HDMI_C_TX_P2 RY35 1 2 470_0402_5%

<7> SOC_DP2_N0 CY11 2 1 0.1U_0201_10V6K HDMI_C_TX_N2 RY36 1 2 470_0402_5%
HDMI_C_TX_N1 2 1 HDMI_R_TX_N1
<7> SOC_DP2_P3 CY16 2 1 0.1U_0201_10V6K HDMI_C_CLKP RY37 1 2 470_0402_5% RY44 5.6_0402_5%
<7> SOC_DP2_N3 CY17 2 1 0.1U_0201_10V6K HDMI_C_CLKN RY38 1 2 470_0402_5% EMI@
2
RY50
@EMI@ 360_0402_5%
1
+3VS RY45 5.6_0402_5%
6
D EMI@
2
G 2N7002KDW _SOT363-6
2 QY5A HDMI_C_TX_N2 2 1 HDMI_R_TX_N2 2
S RY46 5.6_0402_5%
1
EMI@
2
+3VS
RY51
@EMI@ 360_0402_5%
1
2
RY47 5.6_0402_5%
G
SOC_DP2_CTRL_DATA 1 6 HDMI_CTRL_DAT
<7> SOC_DP2_CTRL_DATA EMI@
S
QY7B
5
+3VS
HDMI connector
G
SOC_DP2_CTRL_CLK 4 3 HDMI_CTRL_CLK
<7> SOC_DP2_CTRL_CLK
S
JHDMI1
PJT138KA 2N SOT363-6 HDMI_HPD 19
18 HP_DET
QY7A +HDMI_5V_OUT +5V
17
DDC/CEC_GND
2
HDMI_CTRL_DAT 16
RY39 HDMI_CTRL_CLK 15 SDA
1M_0402_5% 14 SCL
13 Utility
CEC
5
HDMI_R_CLKN 12
G
1
QY5B 11 CK-
3 2N7002KDW _SOT363-6 HDMI_R_CLKP 10 CK_shield 3
HDMI_R_TX_N0 9 CK+
SOC_DP2_HPD 4 3 HDMI_HPD 8 D0-
S
<7> SOC_DP2_HPD HDMI_R_TX_P0 D0_shield
D
7
HDMI_R_TX_N1 6 D0+
D1-
2
5
RY11 HDMI_R_TX_P1 4 D1_shield 23
HDMI_R_TX_N2 3 D1+ GND1 22
100K_0402_5% D2- GND2
2 21
HDMI_R_TX_P2 1 D2_shield GND3 20
1
D2+ GND4
ACON_HMRBL-AK120D
DC232007600
CONN@
SYMBOL:DC232004700
DY1
HDMI_HPD 6 3 HDMI_CTRL_DAT
I/O4 I/O2
DY3 ESD@ DY2 ESD@
HDMI_R_TX_P11 1 10 9 HDMI_R_TX_P1 HDMI_R_TX_N0 1 1 10 9 HDMI_R_TX_N0
5 2
HDMI_R_TX_N12 2 HDMI_R_TX_N1 HDMI_R_TX_P0 HDMI_R_TX_P0 VDD GND
9 8 2 2 9 8
HDMI_R_TX_N24 4 7 7 HDMI_R_TX_N2 HDMI_R_CLKN 4 4 7 7 HDMI_R_CLKN

HDMI_CTRL_CLK 4 1
HDMI_R_TX_P25 5 HDMI_R_TX_P2 HDMI_R_CLKP HDMI_R_CLKP I/O3 I/O1 +HDMI_5V_OUT
6 6 5 5 6 6
AZC099-04S.R7G_SOT23-6
3 3 3 3 ESD@
4 4
8 8
P/N: SC300001G00,S DIO(BR) AZC099-04S.R7G SOT23 ESD
TVW DF1004AD0 TVW DF1004AD0

HDMI CONN.
A B C D E
A B C D E
LAN-RTL8111H
+3VALW +3V_LAN
PVT modify
60mil 1 2 0_0805_5%
RL1 @ W=60mil W=60mil
UL1 IDC=1200mA +LAN_VDD +3V_LAN
5 1
60mil PVT modify
W=60mil
IN OUT 300mA 1.4A
1 2 +REGOUT RL10 1 @ 2 0_0603_5% 1
GND
4 3
EN OC
1 1 1 1 1 1 1 1 1 1 1 1 1
0.1U_0201_10V6K
CL7
0.1U_0201_10V6K
CL1
0.1U_0201_10V6K
CL2
0.1U_0201_10V6K
CL3
0.1U_0201_10V6K
CL8
0.1U_0201_10V6K
CL9
1U_0201_6.3V6M
CL4
1U_0201_6.3V6M
CL23
4.7U_0402_6.3V6M
CL10
4.7U_0402_6.3V6M
C11
1U_0201_6.3V6M
CL12
0.1U_0201_10V6K
CL13
0.1U_0201_10V6K
CL14
2 2 SY6288C20AAC_SOT23-5
@
CL22 CL5
1U_0201_6.3V6M 1U_0201_6.3V6M LAN_PWR_EN 2 2 2 2 2 2 2 2 2 2 2 2 2
Using LDO mode
@
1 1 LAN_PWR_EN <36>
@
Place near Pin 3,8,22,30 Place near Pin 22 For surge improvement Place near Pin 11,32
From EC Place near Pin 11,32 For downsize CL12 change to 1uF
Add 1 cap for downsize reserved
High act i ve.
EN threshold voltage min:1.2V typ:1.6V max:2.0V
Current limit threshold 1.5~2.8A
+3V_LAN Rising t i me must >0. 5 ms and <100 ms
+3V_LAN
UL2 +3VS
1
RL4 RL8
reserve EC_PME# pull high 100K to +3VALW_EC 10K_0402_5% 1K_0402_5%
@
2
2 LAN_MIDI0+ 1 17 PCIE_CRX_C_DTX_P6 .1U_0402_16V7K 2 1 CL16 GPO ISOLATEB 2
LAN_MIDI0- 2 MDIP0 HSOP 18 PCIE_CRX_C_DTX_N6 .1U_0402_16V7K 2 1 PCIE_CRX_DTX_P6 <13>
CL15
MDIN0 HSON PCIE_CRX_DTX_N6 <13>
2
+LAN_VDD 3 19 PLT_RST_BUF#
LAN_MIDI1+ 4 AVDD10 PERSTB 20 ISOLATEB PLT_RST_BUF# <11,21,31>
RL9
LAN_MIDI1- 5 MDIP1 ISOLATEB 21 LAN_PME# 0_0402_5% 2 @ 1 RL2
MDIN1 LANWAKEB EC_PME# <36> 15K_0402_5%
LAN_MIDI2+ 6 22 +LAN_VDD
LAN_MIDI2- 7 MDIP2 DVDD10 23 +3V_LAN 10K_0402_5% 2 1 RL3 +3V_LAN
1
+LAN_VDD 8 MDIN2 VDDREG 24 +REGOUT
LAN_MIDI3+ 9 AVDD10 REGOUT 25
LAN_MIDI3- 10 MDIP3 LED2 26 GPO 2 @ 1
+3V_LAN 11 MDIN3 LED1/GPIO 27 LAN_GPO <36> YL1
0_0402_5% RL7
CLKREQ_PCIE#1 12 AVDD33 LED0 28 XTLI 25MHZ_10PF_7R25000006
PU at PCH side <11> CLKREQ_PCIE#1 13 CLKREQB CKXTAL1 29 XTLO_R 2 1 XTLO 3/13 update Pin 28 to XTALIN
<13> PCIE_CTX_C_DRX_P6 HSIP CKXTAL2 +LAN_VDD RL5
14 30 0_0402_5% XTLI 1 3 XTLO
<13> PCIE_CTX_C_DRX_N6 HSIN AVDD10 LAN_RST 1 3
15 31 1 2
<11> CLK_PCIE_P1 REFCLK_P RSET +3V_LAN 2.49K_0402_1% NC NC
16 32 RL6
<11> CLK_PCIE_N1 REFCLK_N AVDD33
1
33
GND CL20 2 4 CL21
15P_0402_50V8J 15P_0402_50V8J
2
SJ10000UN00
RTL8111H-CG_QFN32_4X4
SA000080P00 LAN Connector 12/21 change YL1 size to 20x16
JRJ45
12
RJ45_MIDI3- 8 GND
PR4- 11
3 RJ45_MIDI3+ 7 GND 3
PR4+
RJ45_MIDI1- 6
PR2-
TR1 RJ45_MIDI2- 5
PR3-
LAN_TERMAL 1 24 MCT1 RJ45_MIDI2+ 4
LAN_MIDI0+ 2 TCT1 MCT1 23 RJ45_MIDI0+ PR3+
LAN_MIDI0- 3 TD1+ MX1+ 22 RJ45_MIDI0- RJ45_MIDI1+ 3
TD1- MX1- PR2+
4 21 MCT2 RJ45_MIDI0- 2
LAN_MIDI1+ 5 TCT2 MCT2 20 RJ45_MIDI1+ PR1- 10
LAN_MIDI1- 6 TD2+ MX2+ 19 RJ45_MIDI1- RJ45_MIDI0+ 1 GND
TD2- MX2- PR1+ 9
7 18 MCT3 GND
LAN_MIDI2+ 8 TCT3 MCT3 17 RJ45_MIDI2+
LAN_MIDI2- 9 TD3+ MX3+ 16 RJ45_MIDI2- SINGA_2RJ1660-000111F
TD3- MX3- CONN@
10 15 MCT4 LTCX008KA00
LAN_MIDI3+ 11 TCT4 MCT4 14 RJ45_MIDI3+
LAN_MIDI3- 12 TD4+ MX4+ 13 RJ45_MIDI3-
TD4- MX4- 40mil
RJ45_GND
RL35
RL34
RL33
RL32
1 2 LANGND
C1
1 GST5009-E 40mil 10P_0402_50V8J
2
2
2
2
SP050006B10
C2 LANGND
2
.1U_0402_16V7K
2 @
Place close to TCT pin J1 JP2
1
1
1
1
75_0402_1%~D
75_0402_1%~D
75_0402_1%~D
75_0402_1%~D
JUMP_43X118 XEMC@
B88069X9231T203_4P5X3P2-2
4 4
2
D1
ESD@
MESC5V02BD03_SOT23-3
1
RJ45_GND

LAN RTL8111H-CG
Date: Wednesday, June 19, 2019 Sheet 30 of 57
A B C D E
A B C D E
+3VS_WLAN
Wireless LAN
+3VS_WLAN CNVi use ALW power rail / PCIE WLAN use VS rail
autodetct and change EN pin power domain by BIOS
RM6 +3VALW DVT modify
2 1 10K_0402_5% WLAN_PME# UM1 W=60mils +3VS_WLAN
5 1
IN OUT
CM2/CM4 close to pin64,66
NGFF WL+BT (KEY E) CM19
1 GND
2 1
CM4
1
CM2
WLAN_ON
@
4 3 1 1 @
UART_2_CRXD_R_DTXD RM45 1 UART@ 2 0_0402_5% <36> WLAN_ON EN OC
1U_0201_6.3V6M CM1 CM3 4.7U_0402_6.3V6M
UART_2_CTXD_R_DRXD RM46 1 UART@ 2 0_0402_5% UART_2_CRXD_DTXD <12> 2 2 2
SY6288C20AAC_SOT23-5
UART_2_CTXD_DRXD <12>
4.7U_0402_6.3V6M0.1U_0201_10V6K 0.1U_0201_10V6K
2 2
Co-layout with CNVi PH +3VS at SOC side,
1 for win7 USB3 debug 1
KEY E +3VS_WLAN
reserve 1000p for cnvi
JNGFF1 1 2 1000P_0402_50V7K
#571906 change to USB port10 for CNVi 1 2 CM18 @
USB20_P10 GND_1 3.3VAUX_2 @ T52
3 4
<13> USB20_P10 USB20_N10 5 USB_D+ 3.3VAUX_4 6 1 RM41 2 CNVI@ INTEL RF Linda suggest reserve for CNVi
For BT <13> USB20_N10 7 USB_D- LED1# 8 M2_BT_PCM_CLK_R RM42 75K_0402_1%
RM26 1 2 0_0201_5% CNV_PRX_R_DTX_N1 9 GND_7 PCM_CLK 10 CNV_RF_RESET#_R 2 1 +1.8VALW_PRIM
<10> CNV_PRX_DTX_N1 SDIO_CLK PCM_SYNC CNV_RF_RESET# <10>
RM25 1 2 0_0201_5% CNV_PRX_R_DTX_P1 11 12 M2_BT_PCM_OUT_R 0_0402_5%
<10> CNV_PRX_DTX_P1 SDIO_CMD PCM_OUT CLKREQ_CNV#_R CNV_BRI_PTX_R_DRX 1 RM57 2
13 14 2 1
SDIO_DAT0 PCM_IN CLKREQ_CNV# <10>
RM27 1 2 0_0201_5% CNV_PRX_R_DTX_N0 15 16 0_0402_5% @ 10K_0402_5%
<10> CNV_PRX_DTX_N0 SDIO_DAT1 LED2# @ T267
RM28 1 2 0_0201_5% CNV_PRX_R_DTX_P0 17 18 RM37
<10> CNV_PRX_DTX_P0 SDIO_DAT2 GND_18 +3VS_WLAN
19 20
RM29 1 2 0_0201_5% CLK_CNV_PRX_R_DTX_N 21 SDIO_DAT3 UART_WAKE 22 UART_2_CRXD_R_DTXD RM47 1 CNVI@ 2 0_0402_5%
<10> CLK_CNV_PRX_DTX_N 2 0_0201_5% CLK_CNV_PRX_R_DTX_P SDIO_WAKE UART_TX CNV_BRI_PRX_DTX <12> WL_OFF#
RM30 1 23 1 RM58 2
<10> CLK_CNV_PRX_DTX_P SDIO_RST
PH +3VS at SOC side, for win7 USB3 debug @ 10K_0402_5%
24 UART_2_CTXD_R_DRXD RM48 1 CNVI@ 2 0_0402_5%
25 UART_RX 26 CNV_RGI_PRX_R_DTX 2 1 CNV_RGI_PTX_DRX <12>
PCIE_CTX_C_DRX_P5 27 GND_33 UART_RTS 28 CNV_BRI_PTX_R_DRX RM38 2 1 0_0402_5% CNV_RGI_PRX_DTX <12> 2 RM56 1 CLKREQ_CNV#_R
<13> PCIE_CTX_C_DRX_P5 PCIE_CTX_C_DRX_N5 PET_RX_P0 UART_CTS E51TXD_P80DATA_R CNV_BRI_PTX_DRX <12>
29 30 RM39 2 1 0_0402_5% 71.5K_0402_1%
<13> PCIE_CTX_C_DRX_N5 31 PET_RX_N0 CLink_RST 32 E51RXD_P80CLK_R 2 1 0_0402_5% E51TXD_P80DATA <36>
RM2
PCIE_CRX_DTX_P5 33 GND_39 CLink_DATA 34 E51RXD_P80CLK <36>
<13> PCIE_CRX_DTX_P5 RM7 0_0402_5%
PCIE_CRX_DTX_N5 35 PER_TX_P0 CLink_CLK 36
<13> PCIE_CRX_DTX_N5 PER_TX_N0 COEX3
37 38
CLK_PCIE_P2 39 GND_45 COEX2 40
<11> CLK_PCIE_P2 CLK_PCIE_N2 41 REFCLK_P0 COEX1 42 SUSCLK_R RM14 1 @ 2 0_0402_5%
<11> CLK_PCIE_N2 43 REFCLK_N0 SUSCLK(32KHz) 44 WL_RST#_R 2 1 PLT_RST_BUF# SUSCLK <11>
CLKREQ_PCIE#2 45 GND_51 PERST0# 46 BT_ON PLT_RST_BUF# <11,21,30> E51TXD_P80DATA_R
<11> CLKREQ_PCIE#2 RM4 0_0402_5%
WLAN_PME# 47 CLKREQ0# W_DISABLE2# 48 WL_OFF# BT_ON <36>
<36> WLAN_PME# 49 PEWAKE0# W_DISABLE1# 50 WL_OFF# <36>
GND_57 I2C_DAT P80CLK and BT_ON enable seperate.
1
RM33 1 2 0_0201_5% CNV_PTX_R_DRX_N1 51 52
2 <10> CNV_PTX_DRX_N1 2 0_0201_5% CNV_PTX_R_DRX_P1 RSVD/PCIE_RX_P1 I2C_CLK 2
RM35 1 53 54 RM19
<10> CNV_PTX_DRX_P1 55 RSVD/PCIE_RX_N1 I2C_IRQ 56 REFCLK_CNV_R 2 WHL@ 1 0_0201_5%
RM40 REFCLK_CNV <11> 100K_0402_5%
RM36 1 2 0_0201_5% CNV_PTX_R_DRX_N0 57 GND_63 RSVD_64 58
<10> CNV_PTX_DRX_N0 2 0_0201_5% CNV_PTX_R_DRX_P0 RSVD/PCIE_TX_P1 RSVD_66 For CNVi Feature
RM31 1 59 60
<10> CNV_PTX_DRX_P0
2
61 RSVD/PCIE_TX_N1 RSVD_68 62
GND_69 RSVD_70 ESD reserve LC filter 1 @ESD@
RM32 1 2 0_0201_5% CLK_CNV_PTX_R_DRX_N 63 64 CM17
<10> CLK_CNV_PTX_DRX_N
RM34 1 2 0_0201_5% CLK_CNV_PTX_R_DRX_P 65 RSVD_71 3.3VAUX_72 66 close PCH 0.1U_0201_10V6K
<10> CLK_CNV_PTX_DRX_P 67 RSVD_73 3.3VAUX_74
GND_75 68 2 Reserved for BT I2S bus
69 GND1
reserve for BT_ON OD pull high (1.0) GND2
BELLW_80152-3221 M2_BT_PCM_CLK_R 0_0402_5% 2 PCM@ 1 RM60
BT_ON M2_BT_PCM_CLK <10>
1 @ 2 CONN@
+3VS_WLAN M2_BT_PCM_OUT_R
8.2K_0402_5% RM49 0_0402_5% 2 PCM@ 1 RM59
SP070013E00 M2_BT_PCM_OUT <10>
mSATA/SSD JSSD1
KEY M
+3VS +3VS_SSD_NGFF
1 2
GND 3P3VAUX +3VS_SSD_NGFF
3 4
PCIE_CRX_DTX_N9 5 GND 3P3VAUX 6 RM9 1 2
<13> PCIE_CRX_DTX_N9 PCIE_CRX_DTX_P9 7 PERn3 NC 8
<13> PCIE_CRX_DTX_P9 PERp3 NC SSD_LED#
10U_0402_6.3V6M
10U_0402_6.3V6M
9 10 0_0805_5% 2 1
GND DAS/DSS# @ T245
1
2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_N9
CM30
CM14
CM5 1 11 12
<13> PCIE_CTX_DRX_N9 CM6 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_P9 13 PETn3 3P3VAUX 14 + CM29
<13> PCIE_CTX_DRX_P9 15 PETp3 3P3VAUX 16 150U_B2_6.3VM_R35M
2
PCIE_CRX_DTX_N10 17 GND 3P3VAUX 18 1 CM13 SGA00009M00
<13> PCIE_CRX_DTX_N10 PCIE_CRX_DTX_P10 19 PERn2 3P3VAUX 20 2
3 <13> PCIE_CRX_DTX_P10 21 PERp2 NC 22 0.1U_0201_10V6K 3
CM7 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_N10 23 GND NC 24
<13> PCIE_CTX_DRX_N10 CM8 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_P10 25 PETn2 NC 26
<13> PCIE_CTX_DRX_P10 27 PETp2 NC 28 add 1 cap for MLCC downsize
PCIE_CRX_DTX_N11 29 GND NC 30
<13> PCIE_CRX_DTX_N11 PCIE_CRX_DTX_P11 31 PERn1 NC 32
<13> PCIE_CRX_DTX_P11 33 PERp1 NC 34
CM9 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_N11 35 GND NC 36
<13> PCIE_CTX_DRX_N11 CM10 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_P11 37 PETn1 NC 38 RM21 1 @ 2 0_0402_5%
<13> PCIE_CTX_DRX_P11 39 PETp1 DEVSLP 40 SSD_DEVSLP2 <13>
RM16 1 2 0_0201_5% PCIE_CRX_R_DTX_P12 41 GND NC 42 2 1
<13> PCIE_CRX_DTX_P12 RM17 1 2 0_0201_5% PCIE_CRX_R_DTX_N12 43 PERn0/SATA-B+ NC 44 RM20 0_0402_5%
<13> PCIE_CRX_DTX_N12 45 PERp0/SATA-B- NC 46 CM15 1 2 ESD@
CM11 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_N12 47 GND NC 48 100P_0402_50V8J DVR change from 1000p to 100p
<13> PCIE_CTX_DRX_N12 CM12 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_P12 49 PETn0/SATA-A- NC 50 NGFF_SSD_RST#_R 2 1 PLT_RST_BUF#
<13> PCIE_CTX_DRX_P12 51 PETp0/SATA-A+ PERST# 52 NGFF_CLKREQ#_R RM18 2 1 0_0402_5%
GND CLKREQ# CLKREQ_PCIE#0 <11>
53 54 RM5 0_0402_5%
<11> CLK_PCIE_N0 REFCLKN PEWake#
Port P and N follow SATA 55 56
<11> CLK_PCIE_P0 REFCLKP NC
57 58
GND NC
+3VS_SSD_NGFF 59 60 SUSCLK_SSD
NC SUSCLK(32kHz) @ T246
RM22 61 62
10K_0402_5% 63 PEDET(NC-PCIE/GND-SATA) 3P3VAUX 64
1 @ 2 65 GND 3P3VAUX 66
GND 3P3VAUX +3VS_SSD_NGFF
67
GND 68
2 1 SSD_DET# GND1 69
<13> SATAXPCIE2 GND2
RM23 0_0402_5%
BELLW_80159-3221
4 4
CONN@
1
D
QM1 2
SP070018L00
BSS138W-7-F_SOT323-3 G
@ S
3
SSD_DET# (SATA_GP0)
SATA Device 0
PCIE Device 1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M.2 Key E (WLAN)/Key M(SSD)
A B C D E
A B C D E
HD Audio Codec add 1 cap for MLCC downsize

+PVDD_HDA
Int. Speaker Conn.
DVT change to R-short,SPK_R bead on sub/B 40mil
SM01000EJ00 3000mA 220ohm@100mhz DCR 0.04 +5VS (output = 300 mA) +VDDA SPKR+ LA2 1 2 0_0603_5% SPK_R+
40mil 40mil JPA1 40mil SPKR- LA3 1 2 0_0603_5% SPK_R- SPK_R+
SPK_R-
<38>
<38>
LA1 2 1 1 2
+VDDA 1 2
HCB2012KF-221T30_0805 1 1 1
0.1U_0201_10V6K
CA2
0.1U_0201_10V6K
CA3
.1U_0402_16V7K
CA4
JUMP_43X79 4.75V JSPK1
10U_0402_6.3V6M
10U_0402_6.3V6M
10_0805_5%2SPKL+_R LA4 EMI@ 1 2 PBY160808T-121Y-N_2P SPK_L+ 1
CA1
SPKL+ RA3
CA34
@
SPKL- RA4 10_0805_5%2SPKL-_R LA5 EMI@ 1 2 PBY160808T-121Y-N_2P SPK_L- 2 1
2
2 2 @ +AVDD1_HDA 2 2 3
@ESD@ G1 4
GND & GNDA moat EMI request for solve EMI noise, SM01000OW00. G2
GND GND
3
GND CVILU_CI4202M2HR0-NH
DVT :Change 0805 for R/L channel balance GND
1 Place near Pin41 Place near Pin46 @ESD@ @ESD@ SP02000RR00 1
DA1 DA2 CONN@
add 1 cap for MLCC downsize CA35 1 2 10U_0402_6.3V6M add 1 cap for MLCC downsize TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
GND 20mil
1
CA5 1 2 10U_0402_6.3V6M RA1 1 2 0_0603_5%
+VDDA
1 GND
1
0.1U_0201_10V6K
CA8
Pin9 need to matching with SOC HDA CA6 1 2 0.1U_0201_10V6K CA9 CA36 GND
interface.
10U_0402_6.3V6M
10U_0402_6.3V6M
2 1 +3VS_DVDDIO
+3VS Place near Pin9
2
RA2 0_0402_5% 2 @
+3VS_DVDD GND & GNDA moat
20mil GNDA place close codec
2 1 Place near Pin26
+3VS +3VS
RA5 0_0402_5%
1
1
+1.8VS_VDDA
0.1U_0201_10V6K
CA11
CA37 CA10 2 1 +1.8VS
1 RA6 0_0402_5%
1
0.1U_0201_10V6K
CA12
CA13 JDMIC1
10U_0402_6.3V6M
10U_0402_6.3V6M
2
2
2 1
#575412 WHL DG p292_ DMIC_DATA34 RA50 2 4MIC@ 10_0402_5% DMIC_DATA34_1 2 1
10U_0402_6.3V6M
2
2 @ add 2pF cap on HDA_SDO and HDA_RST# close to CPU DMIC_CLK 2 1 DMIC_CLK34_1 3 2
1 2 DMIC_CLK add 2pF cap on HDA_SDI close to codec
LA9 4MIC@ BLM15PX221SN1D_2P 4 3
Place near Pin1 GND GNDA 11/26 4
CA32 @EMI@ 5
10P_0402_50V8J HDA_SDIN0_AUDIO SM01000Q500 6 G1
41
46
26
40
G2
9
UA1 Place near Pin40
Reserved for EMI ACES_50278-00401-001
DVDD
DVDD-IO
PVDD1
PVDD2
AVDD1
AVDD2
add 1 cap for MLCC downsize CONN@
GND 1
CA31 GND
SP02000RR00
LINE1-L 22 2P_0201_25V8B
LINE1-R 21 LINE1-L(PORT-C-L) 43 SPKL- 2
UA1 LINE1-R(PORT-C-R) SPK-OUT-L- 42 SPKL+
24 SPK-OUT-L+
23 LINE2-L(PORT-E-L) 45 SPKR+
LINE2-R(PORT-E-R) SPK-OUT-R+ GND
44 SPKR-
2 RING2 17 SPK-OUT-R- 2
40mil SLEEVE 18 MIC2-L(PORT-F-L) /RING2
ALC256-CG MQFN 48P CODEC MIC2-R(PORT-F-R) /SLEEVE 32 HP_LEFT
Combo MIC
256@ +MICBIAS
+MICBIAS 31
LINE1-VREFO-L
HPOUT-L(PORT-I-L)
HPOUT-R(PORT-I-R)
33 HP_RIGHT Digital MIC
SA000080Q00 30
LINE1-VREFO-R 10 HDA_SYNC_R
DMIC_DATA SYNC HDA_BIT_CLK_R HDA_SYNC_R <10>
2 6
DMIC_CLK GPIO0/DMIC-DATA BCLK HDA_BIT_CLK_R <10>
3
GPIO1/DMIC-CLK 1 @EMI@ 2 1 2 CA15 @EMI@ PCH_DMIC_DATA 2 @ 1
GND <10> PCH_DMIC_DATA
RA10 0_0402_5% 22P_0402_50V8J 33_0402_5% RA36
EC_MUTE# 47 5 HDA_SDOUT_R PCH_DMIC_CLK 2 @ 1
<36> EC_MUTE# HDA_RST#_R 2 PDB SDATA-OUT HDA_SDIN0_AUDIO HDA_SDOUT_R <10> <10> PCH_DMIC_CLK TO eDP Conn
Pin11,12 <10> HDA_RST#_R 255@ 1 11 8 1 RA33 2 HDA_SDIN0 <10> 33_0402_5% RA11
0_0402_5% RA41 RESETB SDATA-IN 33_0402_5%
ALC255: RESETB, PCBEEP 48 DMIC_DATA34 DMIC_DATA 2 EMI@ 1 RA35 DMIC_DATA_R
ALC256 : Float i ng ( I 2C ) MONO_IN 12 SPDIF-OUT/GPIO2 0_0402_5% DMIC_DATA_R <28>
10mil Close codec1
PCBEEP 16 PC_BEEP DMIC_CLK 2 1 DMIC_CLK_R
HP_PLUG# RA13 2 200K_0402_1% SENSE_A 13 MONO-OUT LA6 EMI@ BLM15PX221SN1D_2P DMIC_CLK_R <28>
2 1 100K_0402_1% 14 SENSE A +MIC2_VREFO
+3VS RA14 SM01000Q500
SENSE B 29 10U_0402_6.3V6M 1 2 CA18
MIC2-VREFO GND
1
37
CA19 35 CBP 7 10U_0402_6.3V6M 1 2 CA20
CBN LDO3-CAP GNDA
+1.8VS_VDDA
2 256@ 1 2.2U_0402_6.3V6M 39
2
0_0402_5% RA43 LDO2-CAP 27 10U_0402_6.3V6M 1 2 CA21 GNDA

+3VS_DVDD
2 255@ 1 CPVDD 36
CPVDD
LDO1-CAP Headphone Out
Pin20 0_0402_5% RA42 1 RA15 2
28 CODEC_VREF 100K_0402_5% 10mil +MIC2_VREFO
ALC255 : 3.3V VREF
2.2U_0402_6.3V6M
+3VALW
2 1 20
ALC256 : 3.3V or 5V CPVREF
0.1U_0201_10V6K
CA23
RA16 0_0402_5% 15 1
JDREF
CA24
Power for combo jack depop 10U_0402_6.3V6M 1 2 CA22 19 34 CPVEE
GNDA MIC-CAP CPVEE
circuit at system shutdown mode
2
1
1
4 @ 2
49 DVSS 25 CA26 RA19 RA20
Pin4 Thermal PAD AVSS1 38 2.2U_0402_6.3V6M 2.2K_0402_5% 2.2K_0402_5%
ALC283 : DVSS
2
AVSS2
3 ALC255/256/233 : DC DET (For Japen customer only) Place near pin28GNDA 3
2
ALC255-CG_MQFN48_6X6 LA7 EMI@
Pin36 SA000082700 GND BLM15PX330SN1D 0402
255@ SLEEVE 2 1 SLEEVE_L
ALC255 : 3.3V GND
GNDA RING2_L
ALC256 : 1.8V RING2 2 1
LA8 EMI@
AZ5123-02S.R7G 3P C/A SOT23

BLM15PX330SN1D 0402
RA21 CA27 2 2
DOS mode 22K_0402_5% .1U_0402_16V7K Pin15 CA40 CA41 D3
2 1 BEEP#_R 1 2 MONO_IN ESD@
<36> BEEP# ALC283 : Ref. Resistor for Jack Detect 680P_0402_50V7K 680P_0402_50V7K
255@
Pin16 ALC255/256/233 : Jack Detect for SPDIF-OUT and SPK-OUT port 1 1
RA22 CA33 ALC255: MONO-OUT ESD@ ESD@
2
ALC256 : BEEP
4.7K_0402_5%
OS mode 22K_0402_5% 1 .1U_0402_16V7K

PC_BEEP
100P_0402_50V8J
CA28 @EMI@
2 1 1 2 GND
1
<10> PCH_SPKR
RA23
256@ GND
2 LINE1-L 1 2 JHP1
1
CA29 4.7U_0402_6.3V6M
RING2_L 4
HP_LEFT RA24 1 2 0_0603_5% HPOUT_L_1 RA48 1 2 HPOUT_L_2 2
62_0603_1%
GND 5
HP_PLUG# 6
GND & GNDA moat HP_RIGHT RA27 1 2 0_0603_5% HPOUT_R_1 RA491 2 HPOUT_R_2
SLEEVE_L
3 G 7
62_0603_1% 1
RA47 2 1 0_0402_5%
ESD reserved DEREN_570704-001H
LINE1-R 1 2 2 2
HPOUT_R_2
HPOUT_L_2
CA30 4.7U_0402_6.3V6M CA38 CA39 SP02000RR00
4 +MICBIAS DA5 @ESD@ @ESD@ 4
CONN@
TVNST52302AB0_SOT523-3
RA44 2 1 0_0402_5% 2 2 RA29 1 330P_0402_50V7K 330P_0402_50V7K GNDA GNDA

2
4.7K_0402_5% 1 1
Vendor suggest: 1
At least one Ground short close to codec.
D4
RA45 2 1 0_0402_5% 3 2 RA32 1

4.7K_0402_5%
@ESD@ BAT54A-7-F_SOT23-3 GNDA
1
SYMBOL:SCSBAT540A0 SCSBAT54100
RA46 2 1 0_0402_5%
GND
HD Audio Codec ALC255/ALC256 Colay
GND GNDA AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
A B C D E
A B C D E
G-Sensor reserved for BA serial

+3VS
1
+5VS +5VS_HDD
RZ1 +3VS
10K_0402_5% 100mils
GSEN@ UZ1 GSEN@ 1 2
1 CZ1 1 2 10U_0402_6.3V6M RO3 0_0805_5%
10U_0402_6.3V6M
10U_0402_6.3V6M
1 1
2
8 Vdd_IO
CS 1
1
CO16
CO12
4 14 CZ2 1 2 GSEN@ CO13
<9,20> SOC_SMBCLK_1 SCLSPC Vdd
6 0.1U_0201_10V6K 0.1U_0201_10V6K
<9,20> SOC_SMBDATA_1 SDA/SDI/SDO
+3VS RZ2 1 @ 2 10K_0402_5% 7 @
2
RO25 1 GSEN@ 2 10K_0402_5% SDO/SA0 11 G_INT# 2
INT1 G_INT2 G_INT# <12>
16 9
15 ADC1 INT2 G_INT2_R
13 ADC2 10 INT1/2 all High Active
ADC3 RES add 1 cap for MLCC downsize
2
2
3 NC 5 RO29
NC GND 12
GND 0_0402_5%
LIS3DHTR_LGA16_3X3 GSEN@
1
GSEN@
LIS3DH
SA0 ->0, Address is 0011 000 (0x30h) HDD JHDD1
FFC Type
SA0 ->1, Address is 0011 001 (0x32h)
14
+5VS_HDD 13 GND
GND
+5VS_HDD 12
11 12
0_0402_5% 10 11
G_INT2 RO4 1 2
GSEN@ G_INT2_R 9 10
8 9
+3VS 7 8
2 RDSATA_CRX_DTX_P0 CO4 1 RD@
2 0.01U_0402_16V7K RDSATA_CRX_C_DTX_P0 6 7 2
RDSATA_CRX_DTX_N0 CO3 1 RD@
2 0.01U_0402_16V7K RDSATA_CRX_C_DTX_N0 5 6
5
B_EQ1
A_EQ2
A_EQ1
4
CO14 4
DEW
RDSATA_CTX_DRX_N0 CO2 1 RD@
2 0.01U_0402_16V7K RDSATA_CTX_C_DRX_N0 3
2 1 RDSATA_CTX_DRX_P0 CO1 1 RD@
2 0.01U_0402_16V7K RDSATA_CTX_C_DRX_P0 2 3
1 2
0.01U_0402_16V7K UO2 1
20
19
18
17
16
RD@ PS8527CTQFN20GTR2A_TQFN20_4X4 ACES_51625-01201-001
SA00007JU10 CONN@
VDD2
B_EQ1
A_EQ2
A_EQ1
DEW
RD@ close to CONN. SP010028W00
RD@ CO24 2 1 SATA_CTX_C_DRX_P0 0.01U_0402_16V7K 1 15 RDSATA_CTX_DRX_P0
<13> SATA_CTX_DRX_P0 SATA_CTX_C_DRX_N0 A_INP A_OUTP RDSATA_CTX_DRX_N0
<13> SATA_CTX_DRX_N0 RD@ CO25 2 1 0.01U_0402_16V7K 2 14
3 A_INN A_OUTN 13 B_EQ2
RD@ CO26 2 1 SATA_CRX_C_DTX_N0 0.01U_0402_16V7K 4 GND1 B_EQ2 12 RDSATA_CRX_DTX_N0
<13> SATA_CRX_DTX_N0 SATA_CRX_C_DTX_P0 B_OUTN B_INN RDSATA_CRX_DTX_P0
RD@ CO27 2 1 0.01U_0402_16V7K 5 11
<13> SATA_CRX_DTX_P0 B_OUTP B_INP
21
GND2 SATA_CTX_DRX_P0 1 NRD@ 2 0_0402_5% SATA_CTX_DRX_P0_R RDSATA_CTX_C_DRX_P0
REXT
VDD1
B_DE
A_DE
RO30 CO31 1NRD@2 0.01U_0402_16V7K

SATA_CTX_DRX_N0 RO31 1 NRD@ 2 0_0402_5% SATA_CTX_DRX_N0_R CO29 1NRD@2 0.01U_0402_16V7K RDSATA_CTX_C_DRX_N0
EN
+3VS SATA_CRX_DTX_N0 1 NRD@ 2 0_0402_5% SATA_CRX_DTX_N0_R CO30 1NRD@2 0.01U_0402_16V7K RDSATA_CRX_C_DTX_N0

DVT 02/07 RO32
6
7
8
9
10
+3VS SATA_CRX_DTX_P0 RO33 1 NRD@ 2 0_0402_5% SATA_CRX_DTX_P0_R CO28 1NRD@2 0.01U_0402_16V7K RDSATA_CRX_C_DTX_P0
A_DE
@@
RO10 1 2 4.7K_0402_5% RO27 +3VS

RO15 1 2 4.7K_0402_5% 4.99K_0402_1% 1 Co-lay non redriver
@
2 1 CO15
B_DE
A_DE
A_EQ1
@
RO13 1 2 4.7K_0402_5% RD@ 0.1U_0201_10V6K

RO18 1 RD@ 2 4.7K_0402_5% RO6 2 1 RD@
+3VS 4.99K_0402_1% 2
A_EQ2
@
RO14 1 2 4.7K_0402_5%
3 3
@
RO19 1 RD@ 2 4.7K_0402_5% RO5 1 2 change ODD pin def i ne

4.7K_0402_5%
B_DE ODD FFC Type
@@
RO11 1 2 4.7K_0402_5%
RO16 1 2 4.7K_0402_5% +5VS_ODD
B_EQ1 +5VS_ODD
@
RO12 1 2 4.7K_0402_5% 1
RO17 1 RD@ 2 4.7K_0402_5% 2 1
3 2
B_EQ2 3
@
RO20 1 2 4.7K_0402_5% 4
RO21 1 RD@ 2 4.7K_0402_5% 5 4
6 5
6
@@
RO22 1 2 4.7K_0402_5% DEW 7

RO28 1 2 4.7K_0402_5% 8 7
9 8
10 9
PVT 03/13 10
11
SATA_CRX_DTX_P1 ODD@ CO20 1 2 0.01U_0402_16V7K SATA_CRX_C_DTX_P1 12 11
<13> SATA_CRX_DTX_P1 SATA_CRX_DTX_N1 SATA_CRX_C_DTX_N1 12
ODD@ CO18 1 2 0.01U_0402_16V7K 13
<13> SATA_CRX_DTX_N1 13
14
SATA_CTX_DRX_N1 ODD@ CO19 1 2 0.01U_0402_16V7K SATA_CTX_C_DRX_N1 15 14
<13> SATA_CTX_DRX_N1 SATA_CTX_DRX_P1 SATA_CTX_C_DRX_P1 15
<13> SATA_CTX_DRX_P1 ODD@ CO17 1 2 0.01U_0402_16V7K 16
16
+5VS +5VS_ODD close to CONN. 17
18 GND17
GND18
1 2
100mils JODD1
RO26 0_0805_5% ACES_51625-01601-001
10U_0402_6.3V6M
10U_0402_6.3V6M
SP01002OK00
ODD@
1@
1
1
CO23
CO22
4
CO21 CONN@ 4
0.1U_0201_10V6K
@
2
add 1 cap for MLCC downsize Security Classification Compal Secret Data Compal Electronics, Inc.
G-Sensor/HDD/ODD
A B C D E
5 4 3 2 1
USB3 port reserved

USB3.0 (Port 2) DS1~4 change to SC300001Y00 For ESD request
CS3 1 2 USB3_CTX_C_DRX_N2 RS5 1 @ 2 0_0402_5% USB3_CTX_L_DRX_N2 DS23 ESD@

<13> USB3_CTX_DRX_N2 USB3_CTX_L_DRX_P2 USB3_CTX_L_DRX_P2
.1U_0402_16V7K 1 1 10 9
CS4 1 2 USB3_CTX_C_DRX_P2 RS6 1 @ 2 0_0402_5% USB3_CTX_L_DRX_P2 USB3_CTX_L_DRX_N2 2 2 9 8 USB3_CTX_L_DRX_N2

<13> USB3_CTX_DRX_P2
.1U_0402_16V7K
USB3_CRX_L_DTX_P2 4 4 7 7
USB3_CRX_L_DTX_P2
USB3_CRX_L_DTX_N2 5 5 USB3_CRX_L_DTX_N2
D 6 6 D
USB3_CRX_DTX_N2 RS7 1 @ 2 0_0402_5% USB3_CRX_L_DTX_N2 3 3
<13> USB3_CRX_DTX_N2
8
USB3_CRX_DTX_P2 RS8 1 @ 2 0_0402_5% USB3_CRX_L_DTX_P2
<13> USB3_CRX_DTX_P2
AZ1045-04F_DFN2510P10E-10-9
USB2.0 (Port 2)
DS24 ESD@
+5VALW 6 3 USB20_N2_L
LS5 EMI@ +USB3_VCCB I/O4 I/O2
USB20_P2 2 1 USB20_P2_L CS93 +USB3_VCCB
<13> USB20_P2 2 1 1U_0201_6.3V6M US21
1 2 5 1 W=100mils 5 2
C USB20_N2 3 4 USB20_N2_L IN OUT VDD GND C
<13> USB20_N2 3 4 2
DLM0NSN900HY2D_4P GND
SM070005U00 4 3 4 1 USB20_P2_L
<36,38> USB_EN EN OC I/O3 I/O1
SY6288C20AAC_SOT23-5 AZC099-04S.R7G_SOT23-6
+USB3_VCCB
W=100mils
10U_0402_6.3V6M
470P_0402_50V7K
1
1 1
+
CS91
CS94
CS90
150U_B2_6.3VM_R35M
SGA00009M00 2 2 2 @
@
@
USB2.0 Conn.
B JUSB2 B
1
USB20_N2_L 2 VBUS
USB20_P2_L 3 D-
4 D+
5 GND
6 GND
7 GND
8 GND
GND
C-K_20282-8K19-06_4P
CONN@
DC23300JB00
Symbol:DC23300N800
compatible: DC23300TT00
A A

USB3_P2_MB
5 4 3 2 1
A B C D E
USB3.0 (Port 1)
DS21 change to SC300001Y00 For ESD request +USB3_VCCB +USB3_VCCA
JPC10
DS21 ESD@ 1 2
USB3_CTX_L_DRX_P1 1 USB3_CTX_L_DRX_P1 1 2
@RF@ 1 10 9
CS21 1 2 USB3_CTX_C_DRX_N1 1 2 0_0402_5% USB3_CTX_L_DRX_N1
<13> USB3_CTX_DRX_N1 RS21
USB3_CTX_L_DRX_N1 2 2 USB3_CTX_L_DRX_N1
JUMP_43X79 Non charger need short this JP
.1U_0402_16V7K 9 8 @
@RF@
CS22 1 2 USB3_CTX_C_DRX_P1 RS22 1 2 0_0402_5% USB3_CTX_L_DRX_P1 USB3_CRX_L_DTX_P1 4 4 7 7 USB3_CRX_L_DTX_P1
modify 11/12
1 <13> USB3_CTX_DRX_P1 1
.1U_0402_16V7K
USB3_CRX_L_DTX_N1 5 6 6 USB3_CRX_L_DTX_N1
5
3 3
@RF@
USB3_CRX_DTX_N1 RS24 1 2 0_0402_5% USB3_CRX_L_DTX_N1 8
<13> USB3_CRX_DTX_N1
@RF@ AZ1045-04F_DFN2510P10E-10-9
USB3_CRX_DTX_P1 RS25 1 2 0_0402_5% USB3_CRX_L_DTX_P1
<13> USB3_CRX_DTX_P1
DS22 ESD@
6 3 U2DN1_L +USB3_VCCA
LS2 EMI@ I/O4 I/O2
U2DN1 2 1 U2DN1_L
2 1
+USB3_VCCA W=100mils
5 2 1
U2DP1 3 4 U2DP1_L VDD GND
3 4 1 1
10U_0402_6.3V6M
CS26
470P_0402_50V7K
CS95
CS25 +
DLM0NSN900HY2D_4P 220U_6.3V_ESR18M_6.3X4.5
SM070005U00 4 1 U2DP1_L SF000006R00
I/O3 I/O1 2 2 2 @
@
AZC099-04S.R7G_SOT23-6
USB3.0 Conn.
DVT: R-short JUSB1
USB3_CTX_L_DRX_P1 9
1 SSTX+
USB3_CTX_L_DRX_N1 8 VBUS
U2DP1_L 3 SSTX-
2 USB20_N1 RS96 1 2 0_0201_5% USB20_N1_R RS162 1 2 0_0201_5% U2DN1 7 D+ 2
USB20_P1 RS97 1 2 0_0201_5% USB20_P1_R RS161 1 2 0_0201_5% U2DP1 U2DN1_L 2 GND 10
USB3_CRX_L_DTX_P1 6 D- GND 11
4 SSRX+ GND 12
Co-lay non redriver / Reserved-1/29 change to R-short USB3_CRX_L_DTX_N1 5 GND GND 13
SSRX- GND
ACON_TARBA-9U1393
CONN@
LTCX008KB00
Symbol:DC23300N800
+5VALW compatible: DC23300TT00
For Test Debug Only
+5VALW RS14 1 CHG@ 2 10K_0402_5% CHG_CTL2
1 @ 2 CHG_CTL3
RS150 10K_0402_5% RS152 1 @ 2 10K_0402_5% CHG_ILMSEL
CHG_EN 2 @ 1 CHG_CTL1
RS151 10K_0402_5%
Rerserve PU, vendor suggest to EC control
if future need support SDP2
0904 vendor recommend
+5VALW
3
USB Host Charger Truth Table CHG@
3
22U_0603_6.3V6M
0.1U_0201_10V6K
CHG_EN CTL1 CTL2 CTL3 ILIM_SEL MODE Current Limit Note 1 1
Setting +USB3_VCCA
CS9
CS7
@
0 0 1 0 1 SDP1-OFF ILIM_H Port power off 2 2 US12
1 0 1 0 1 SDP1 ILIM_H Data Lines Connected CHG@
1 12 +USB3_VCCA_R 1 CHG@ 2 RS18
VIN VOUT 0_0805_5%
1 0 1 1 1 DCP ILIM_H Data Lines Disconnected
Aut o 2
<13> USB20_N1 3 DM_OUT
RS11
<13> USB20_P1 DP_OUT 10 U2DP1
1 1 1 1 1 CDP ILIM_H Data Lines Connected 0_0201_5%
2 @ 1 13 DP_IN 11 U2DN1
<13> USB_OC0# FAULT# DM_IN
1 4
<36> CHG_ILMSEL ILIM_SEL
CS8 5 15 0831 Reserve ILIM_L R as vendor recommend
<36> CHG_EN EN ILIM_L 16
0.1U_0201_10V6K
@ 2 ILIM_HI
1
6
<36> CHG_CTL1 CHG_CTL2 CTL1
22.1K_0402_1%
39K_0402_1%
7 9
CTL2 NC
RS12
RS13
8 14
<36> CHG_CTL3 CTL3 GND 17
Thermal Pad ILM R vaule
CHG@ @
Ios(mA)=50250/R(Kohm)
2
SLGC55544CVTR_TQFN16_3X3 ILIM_Hi=2273mA
ILIM_L=1288mA(reserve)
4 4

USB3_P1_CHG_MB
A B C D E
A B C D E
+3VLP_EC PN:SM01000K500 +3VLP_ECA

+3VLP LB1
EC_RST#
FBMA-L11-160808-800LMT_0603
+3VLP_ECA
near SOC SOC_RTCRST# <11>
CB9 1 2 0.1U_0201_10V6K 1 2 1 2
D
1
RB22 0_0805_5%
EC_CLR_CMOS 2 QB6
+1.8VALW_PRIM
0.1U_0201_10V6K
CB1
0.1U_0201_10V6K
CB2
0.1U_0201_10V6K
CB3
1 1 1 G L2N7002WT1G_SC-70-3
1
S
3
1
RB26
1
RB2 10K_0402_5%
+3VLP_EC 2 2 RB3 2
0_0402_5%
ESPI@ 0_0402_5%
2
ECAGND
ECAGND <42>
2
1 @ 2 EC_PME#
2
1 RB5 47K_0402_5% +3VCC_LPC 1
EC_PME# PU +3V_LAN at LAN side
+3VS
111
125
22
33
96
67
9
+3VLP_EC UB1
GPU_ALERT# RB23 1 @ 2 10K_0402_5%
VCC0
VCC_LPC
VCC
VCC
VCC
VCC
AVCC
RB13 1 2 2.2K_0402_5% EC_SMB_CK1
RB14 1 2 2.2K_0402_5% EC_SMB_DA1
ESPI Bus Pin : 1~5.7.8.10.12.14 GPU_OVERT# RB24 1 2 10K_0402_5%
LPC Bus Pin : 3~5.7.8.10.12.13 SUSPWRDNACK 1 21 EC_VCCST_PG_R
<11> SUSPWRDNACK 2 GATEA20/GPIO00 EC_VCCST_PG/GPIO0F 23 BEEP# EC_VCCST_PG_R <11,40>
EC_SERIRQ 3 KBRST#/GPIO01 BEEP#/GPIO10 26 FAN_PWM1 BEEP# <32>
<9> EC_SERIRQ LPC_FRAME# 4 SERIRQ EC_FAN_PWM/GPIO12 27 CHG_CTL1 FAN_PWM1 <39>
<9> LPC_FRAME# LPC_AD3_R LPC_FRAME# PWM Output AC_OFF/GPIO13 CHG_CTL1 <35>
For turn off internal LPC module of KB9032 5
<9> LPC_AD3_R LPC_AD2_R 7 LPC_AD3
<9> LPC_AD2_R LPC_AD1_R 8 LPC_AD2 63 BATT_TEMP
ESPI@
1 2 ESPI_RST# <9> LPC_AD1_R LPC_AD0_R 10 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38 64 VCIN1_BATT_DROP BATT_TEMP <42,43> +3VLP_EC
<9> LPC_AD0_R LPC_AD0LPC & MISC VCIN1_BATT_DROP/AD1/GPIO39 ADP_I VCIN1_BATT_DROP <42>
RB8 47K_0402_5% 65
CLK_LPC_EC 12 ADP_I/AD2/GPIO3A 66 AD_BID ADP_I <42,43>
<9> CLK_LPC_EC PLT_RST# CLK_PCI_EC AD Input AD_BID/AD3/GPIO3B WLAN_PME# LID_SW#
ESPI@ 13 75 RB15 1 2 100K_0402_1%
1 2 PLT_RST# <11,37> PLT_RST# EC_RST# 37 PCIRST#/GPIO05 AD4/GPIO42 76 EC_PME# WLAN_PME# <31>
<39> EC_RST# EC_SCI# 20 EC_RST# AD5/GPIO43 EC_PME# <30>
RB9 47K_0402_5% Combine w/ SMI
<7> EC_SCI# WLAN_ON 38 EC_SCI#/GPIO0E
1 2 <31> WLAN_ON CLKRUN#/GPIO1D
CB5 ESD@ 100P_0402_50V8J 68 LAN_PWR_EN
<37> KSI[0..7] DA0/GPIO3C 70 EC_TP_INT# LAN_PWR_EN <30>
DA Output EN_DFAN1/DA1/GPIO3D VR_PWRGD EC_TP_INT# <7,37>
KSI0 55 71
KSI1 56 KSI0/GPIO30 DA2/GPIO3E 72 KBL_EN VR_PWRGD <48>
1 2 AC_IN KSI2 57 KSI1/GPIO31 DA3/GPIO3F KBL_EN <37>
CB6 100P_0402_50V8J KSI3 58 KSI2/GPIO32 83 EC_MUTE#
KSI4 59 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A 84 USB_EN EC_MUTE# <32>
KSI5 60 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B 85 USB_EN <34,38>
@EMI@ @EMI@
2 2 1 2 1 CLK_LPC_EC KSI6 61 KSI5/GPIO35 PSCLK2/GPIO4C 86 CHG_EN 2
KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D TP_CLK CHG_EN <35> SYS_PWROK_R
CB7 RB10 33_0402_5% KSI7 62 87 2 1 SYS_PWROK <11,40>
<37> KSO[0..17] KSO0 39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TP_DATA TP_CLK <37>
22P_0402_50V8J PU at PTP side
KSO1 40 KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <37>
RB11 0_0402_5%
KSO2 41 KSO1/GPIO21
KSO3 42 KSO2/GPIO22 97 ENBKL
43 KSO3/GPIO23 ENKBL/GPXIOA00 98 TP_PWR_EN ENBKL <7>
KSO4
44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 ME_EN TP_PWR_EN <37>
KSO5
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH ME_EN <10>
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH1/GPXIOD00 VCIN0_PH <42>
DB1
For Thermal Portect Shutdown
KSO8 47 KSO7/GPIO27
KSO8/GPIO28 SPI Device Interface SPOK_5V
RB751V-40_SOD323-2
3V_EN
KSO9 48 119 MAINPWON 1 2
49 KSO9/GPIO29 MISO/GPIO5B 120 BT_ON SPOK_5V <44> 3V_EN <44>
KSO10
KSO11 50 KSO10/GPIO2A MOSI/GPIO5C 126 EC_CLR_CMOS BT_ON <31>
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 FP_PWR_EN 3V_EN_R
KSO12 51 128 1 2 RB17 1 2
KSO13 52 KSO12/GPIO2C SPICS#/GPIO5A FP_PWR_EN <37>
RB16 1M_0402_5%
KSO14 53 KSO13/GPIO2D 1K_0402_5%
KSO15 54 KSO14/GPIO2E 73 GPU_ALERT#
81 KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 74 SYS_PWROK_R GPU_ALERT# <42>
RB28 0_0402_5% KSO16
SPOK_3V 2 1 KSO17 82 KSO16/GPIO48 SYS_PWROK/AD7/GPIO41 89 BATT_4S
KSO17/GPIO49 GPIO50 90 BATT_BLUE_LED# BATT_4S <43>
SPOK_5V 1 RB27 2 0_0402_5% SPOK_3V_5V BATT_CHG_LED#/GPIO52 91 CHG_CTL3 BATT_BLUE_LED# <38>
EC_SMB_CK1 77 CAPS_LED#/GPIO53 92 PWR_LED# CHG_CTL3 <35>
@ GPIO
<42,43> EC_SMB_CK1 EC_SMB_DA1 78 EC_SMB_CLK1/GPIO44 PWR_LED#/GPIO54 93 BATT_AMB_LED# PWR_LED# <38>
<42,43> EC_SMB_DA1 SOC_SML1CLK 79 EC_SMB_DAT1/GPIO45 BATT_LOW_LED#/GPIO55 95 SYSON BATT_AMB_LED# <38>
<9,21> SOC_SML1CLK SOC_SML1DATA 80 EC_SMB_CLK2/GPIO46 SYSON/GPIO56 121 VR_ON SYSON <14,40,45>
PU at CPU side <9,21> SOC_SML1DATA EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 127 CHG_ILMSEL VR_ON <40,48>
DPWROK_EC/GPIO59 CHG_ILMSEL <35>
SM Bus
PM_SLP_S3# 6 100 EC_RSMRST#
<11,40> PM_SLP_S3# ESPI_RST# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 DGPU_AC_DETECT EC_RSMRST# <11>
<9> ESPI_RST# SPOK_3V 15 GPIO07 GPXIOA04 102 VCIN1_ADP_PROCHOT DGPU_AC_DETECT <10,21,43>
3 <44,47> SPOK_3V TP_EN 16 GPIO08 VCIN1_ADP_PROCHOT/GPXIOA05 103 VCOUT1_PROCHOT# VCIN1_ADP_PROCHOT <42> 3
<37> TP_EN TS_EN 17 GPIO0A VCOUT1_PROCHOT#/GPXIOA06 104 MAINPWON
<12,28> TS_EN WL_OFF# 18 GPIO0B VCOUT0_MAIN_PWR_ON/GPXIOA07 105 BKOFF# MAINPWON <39,44>
<31> WL_OFF# AC_PRESENT 19 GPIO0C BKOFF#/GPXIOA08 106 LAN_GPO BKOFF# <28>
<11> AC_PRESENT GPU_OVERT# AC_PRESENT/GPIO0D GPIO GPO GPXIOA09 3V_EN_R LAN_GPO <30>
25 107
<21,22> GPU_OVERT# FAN_SPEED1 28 PWM2/GPIO11 PCH_PWR_EN/GPXIOA10 108 PM_SLP_S0#
For abnormal shutdown PM_SLP_S0# <11,37>
<39> FAN_SPEED1 29 FAN_SPEED1/GPIO14 PWR_VCCST_PG/GPXIOA11
E51TXD_P80DATA FANFB1/GPIO15 T85 @
DB2 30
<31> E51TXD_P80DATA E51RXD_P80CLK 31 EC_TX/GPIO16 110 AC_IN
RB751V-40_SOD323-2
SPOK_3V_5V 1 2 EC_RSMRST# <31> E51RXD_P80CLK PCH_PWROK 32 EC_RX/GPIO17 VCIN1_AC_IN/GPXIOD01 112 EC_ON AC_IN <43>
<11,40> PCH_PWROK PWR_SUSP_LED# 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 ON/OFFBTN# EC_ON <44>
RB25
<38> PWR_SUSP_LED# 36 SUSP_LED#/GPIO19 ON/OFF#/GPXIOD03 115 LID_SW# ON/OFFBTN# <37> 2 1 VCOUT1_PROCHOT#
DB3 GPI
NUM_LED#/GPIO1A LID_SW#/GPXIOD04 116 SUSP# LID_SW# <38>
RB751V-40_SOD323-2 0_0402_5%
1 2 PCH_PWROK SUSP#/GPXIOD05 117 SW_PROCHOT# SUSP# <14,40,43,45> DGPU_AC_DETECT SW_PROCHOT#
GPXIOD06 118 H_PECI_R 1 2
PBTN_OUT# PECI/GPXIOD07 H_PECI <7> QB1A @
122 RB19 43_0402_1%
<11> PBTN_OUT# PBTN_OUT#/GPIO5D
3
DB4 PM_SLP_S4# 123 124 2N7002KDW_SOT363-6 D D
<11,40> PM_SLP_S4# PM_SLP_S4#/GPIO5E V18R/VCC_IO2 +3VLP_EC VCOUT1_PROCHOT# VCOUT1_PROCHOT#
RB751V-40_SOD323-2 2 5
EC_VCCST_PG_R
AGND
1 2 G G
GND
GND
GND
GND
GND
VCOUT1_PROCHOT# is QB1B
high active when QB1 S S 2N7002KDW_SOT363-6
4
KB9022QD_LQFP128_14X14 mount @
11
24
35
94
113
ECAGND 69
Board ID RB4 DVT@

20mil
+3VLP_EC
CO-LAY with KB9032QA (SA000080J00) 1 2 BATT_TEMP
2015/1/9 acer require:
12K_0402_5% CB8
SD028120280 100P_0402_50V8J reserved protact circuit when
LB2 2 1 adaptor 107% happen
2
RB4 PVT@ FBMA-L11-160808-800LMT_0603

RB1 15K_0402_1% PN:SM01000K500
Ra 100K_0402_1% SD034150280
RB4 MP@
1
4 AD_BID 20K_0402_1% 2 1 VR_HOT# 4

VR_HOT# <48>
SD034200280 RB20 0_0402_5%
1
1 H_PROCHOT# SW_PROCHOT#
RB4 CB4 2 1
<7,43> H_PROCHOT#
Rb 0_0402_5% 0.1U_0201_10V6K RB21 0_0402_5%
EVT@ @
2
2

Analog Board ID definition, EC ENE KB9022
Please see page 3. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A B C D E
A B C D E
KB Conn. TP/B Conn.

ON/OFF BTN 30
GND2
JKB1
+3VS RK3
+3V_PTP
RK1 29 +3VALW 0_0402_5%

100K_0402_5% KSO16 28 GND1 2 @ 1
2 1 KSO17 27 28
+3VLP 27
KSO0 26
KSO1 25 26 UK1 +3V_PTP
ON/OFFBTN# KSO2 24 25 5 1 +3V_PTP
<36> ON/OFFBTN# 24 IN OUT
KSO3 23 1 @ CK2
1 KSO4 22 23 2 0.1U_0201_10V6K 1
22 GND
2
KSO5 21 CK1 2 1 JTP1
KSO6 20 21 4 3 1
20 EN OC 4.7U_0402_6.3V6M 1
KSO7 19 2 RK4 TP_CLK 2
19 1 TP_DATA 2
DVT: remove SWK1 switch button KSO8 18 CK3 SY6288C20AAC_SOT23-5 10K_0402_5% 3
KSO9 17 18 EC PS2 4 3
1
KSO10 16 17 1U_0201_6.3V6M EC_TP_INT# I2C_1_SDA_R 5 4
KSO11 15 16 2 I2C_1_SCL_R 6 5
KSO12 14 15 TP_PWR_EN <36> PCH I2C EC_TP_INT# 7 6
13 14 <7,36> EC_TP_INT# TP_EN 8 7
KSO13 <36> TP_EN
KSO14 12 13 9 8
KSO15 11 12 TP_PWR_EN follow SYSON behavior 10 GND
KSI0 10 11 GND
KSI1 9 10 ACES_51524-00801-001
KSI2 8 9 CONN@
KSI3 7 8
KSI[0..7] KSI4 6 7 SP01001A900
KSI[0..7] <36> KSI5 5 6 +3V_PTP +3V_PTP
KSO[0..17] KSI6 4 5
KSO[0..17] <36> KSI7 3 4
2 3
2
1
ON/OFFBTN# 1 RK7 RK10
1
5
2.2K_0402_5% 2.2K_0402_5%
G
QK1B
ACES_85201-2805
KB BackLight CONN@
2N7002KDW_SOT363-6 +3V_PTP
2
3 4 I2C_1_SCL_R
SP01000GO00
S
<12> I2C_1_SCL
1
+5VS JBL1
U1 1 1 2 RK5 RK6
5 1 +5VS_BL 2 1 RK8 @ 0_0402_5% 4.7K_0402_5% 4.7K_0402_5%
IN OUT 2
2
3
G
2 2 4 3 2
2
GND 4 QK1A
4 3 5 2N7002KDW_SOT363-6
<36> KBL_EN EN OC GND I2C_1_SDA_R TP_CLK
6 6 1
S
GND <12> I2C_1_SDA <36> TP_CLK TP_DATA
SY6288C20AAC_SOT23-5
D
<36> TP_DATA
ACES_51524-0040N-001
1 CONN@ 1 @ 2
RK9 0_0402_5%
C3 SP010022M00
0.1U_0201_10V6K
2
TPM 2.0 Finger Print

DVT:swap pin define
+FP_VCC
SP010020S00
Power Souce Check CONN@
JXT_FP201H-008G10M
EGIS ETU801 +FP_VCC=5V 1
USB20_P5_L 1
+3VALW +3VALW_TPM +3VS +3VS_TPM
ELAN SA464K-2200 +FP_VCC=3.3V USB20_N5_L
2
3 2
add 1 cap for MLCC downsize 4 3
1 TPM@ 2 1 TPM@ 2 5 4
5
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
RW1 0_0603_5% RW2 0_0603_5% 6

6
0.1U_0201_10V6K
CW2 TPM@
0.1U_0201_10V6K
CW4 TPM@
0.1U_0201_10V6K
CW5 TPM@
0.1U_0201_10V6K
CW6 TPM@
TPM@ CW7
TPM@ CW1
TPM@ CW8
TPM@ CW3
1 1 1 1 7
7
1
8
8
9
near pin1
2
2 2 2 2 10 GND
3 GND 3
JFP1
add 1 cap for MLCC downsize
+3VALW_TPM near pin8,22

+FP_VCC
RW16 1 TPM@ 2 10K_0402_5% TPM_PIRQ# +3VALW RK16 1 FP3V@ 2 0_0603_5% UK6

+5VALW RK17 1 FP5V@ 2 0_0603_5% 5 1
IN OUT
1
UW1 2 FP@
1 GND CK12 LK2
VSB +3VALW_TPM USB20_P5 USB20_P5_L
2 TPM@ 1 29 4 3 4.7U_0402_6.3V6M 3 4
<11,36> PM_SLP_S0# SDA/GPIO0 EN OC 2 <13> USB20_P5 3 4
RW10 0_0402_5% 30 8 1
SCL/GPIO1 VHIO +3VS_TPM
22 CK11 SY6288C20AAC_SOT23-5
6 VHIO FP@ FP@ USB20_N5 2 1 USB20_N5_L
GPIO3 <13> USB20_N5 2 1
2 1U_0201_6.3V6M
SOC_SPI_SO RW5 2 TPM@ 1 51_0402_5% TPM_SPI_SO 24 NC 3 2 DLM0NSN900HY2D_4P
SOC_SPI_SI RW13 2 TPM@ 1 51_0402_5% TPM_SPI_SI MISO NC FP_PWR_EN <36>
21 5 SM070005U00FPEMC@
TPM_PIRQ# 2 TPM@ 1 TPM_PIRQ#_R 18 MOSI/GPIO7 NC 7
RW11 0_0402_5% PIRQ/GPIO2 NC 9 DK2 FPEMC@
NC 10 6 3 USB20_N5_L
SOC_SPI_CLK RW14 2 TPM@ 1 51_0402_5% TPM_SPI_CLK 19 NC 11 I/O4 I/O2
SOC_SPI_CS#2 2 TPM@ 1 TPM_SPI_CS#2 20 SCLK NC 12
PLT_RST# RW15 2 TPM@ 10_0402_5% TPM_RST# 17 SCS/GPIO5 NC 14
RW12 0_0402_5% 27 PLTRST NC 15 5 2
NC NC +FP_VCC VDD GND
13 26
GPIO4 NC 25
NC 28
4 NC 31 4 1 USB20_P5_L
@ T283 PP/GPIO6 NC I/O3 I/O1
32
4 NC AZC099-04S.R7G_SOT23-6 4
16
GND 23
GND 33
PGND
SOC_SPI_SO NPCT750AAAYX_QFN32_5X5
<9> SOC_SPI_SO SOC_SPI_SI
<9> SOC_SPI_SI TPM_PIRQ# TPM@
<12> TPM_PIRQ#
<9> SOC_SPI_CLK
SOC_SPI_CLK Security Classification Compal Secret Data Compal Electronics, Inc.
SOC_SPI_CS#2
<9> SOC_SPI_CS#2 PLT_RST# Issued Date 2018/12/27 Deciphered Date 2019/12/27 Title
<11,36> PLT_RST#
KB & TP & TPM & FP
SA0000AQ230, S IC NPCT750AAAYX QFN 32P TPM (SPI interface) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
A B C D E
A B C D E
I/O Borad (USB2 /Card reader/ Speaker-RCH)

USB2 I/O 22
GND
RS157 1 @ 2 0_0402_5% USB20_L_P4
PVT: Delete choke DVT:update JIO1 pin define +5VALW
21
GND
<13> USB20_P4
20
RS158 1 @ 2 0_0402_5% USB20_L_N4 19 20
<13> USB20_N4 18 19
17 18
16 17
1 15 16 1
14 15
13 14
<32> SPK_R+ 13
12
11 12
Reserved CMC on SUB/B side <32> SPK_R- 11
10
9 10
Card reader <34,36> USB_EN
8 9
8
7
USB20_L_N6 6 7
USB20_L_P6 5 6
4 5
USB20_L_N4 3 4
USB20_L_P4 2 3
1 2
RS159 1 @ 2 0_0402_5% USB20_L_N6 1
<13> USB20_N6
JIO1
USB20_L_P6 CONN@
RS160 1 @ 2 0_0402_5%
<13> USB20_P6
SP01001KD00
ACES_51522-02001-P02
LID/B with LED for 17" UMA &DIS

CONN@
+5VALW
SP010025K00
ACES_51530-01001-P01
2 2
10 12
9 10 G12 11
8 9 G11
<36> BATT_AMB_LED# 8
7
<36> BATT_BLUE_LED# 7
6
<36> PWR_SUSP_LED# 6
5
<36> PWR_LED# 5
4
3 4
2 3
<36> LID_SW# 2
1
+3VLP 1
LID for 15" DIS JLID2
LED for 15" UMA
+3VLP hall sensor change to TOP side
UG1
Battery LED 3 LID_SW#
2 OUT
VDD 1
LED1 GND
RG4
680_0402_5%
1
APX8132AI_TSOT-23-3 LID/B for 15" UMA 4pin
BATT_AMB_LED# 1 2 3 A 4 CG3 15DIS@
+5VALW
0.1U_0201_10V6K
15@ 15DIS@ 2
BATT_BLUE_LED# 1 2 1 B 2
RG7 +3VLP
560_0402_5% SA00008K800, S IC APX8132AI-TRG SOT-23 3P HALL SENSOR
LTST-C295TBKF-CA_AMBER-BLUE JLID1
15@
15@ 1
LID_SW# 2 1
3 3 2 5 3
Power LED +3VLP 4 3 G1 6
4 G2
LED2
RG11 UG2 ACES_51575-00401-001
680_0402_5% 3 LID_SW#
PWR_SUSP_LED# 1 OUT CONN@
2 3 A 4 2
VDD 1
15@
GND SP01002BY00
PWR_LED# 1
1 2 1 B 2 APX8132AI_TSOT-23-3
+5VALW
RG10 CG2 @
560_0402_5% 0.1U_0201_10V6K
@ 2
LTST-C295TBKF-CA_AMBER-BLUE
15@
15@
4 4

IO/LiD/LED
A B C D E
A B C D E
FAN1 Conn Screw Hole

+5VS DIS
40mil
RF1 1 2 0_0603_5% +VCC_FAN1 H1 H2 H3 H4 H5 H6 H7 H8 H10 H11 H12 H13
1 2 H_3P0-G H_3P0-G H_3P3 H_3P3 H_3P3 H_3P3 H_3P0-G H_4P5X4P0 H_4P2 H_4P2 H_3P0-G H_3P2
1 FD1 FD2 1
@EMI@ CF2 CF1
1000P_0402_50V7K 4.7U_0402_6.3V6M
1
2 1 @ @
1
FIDUCIAL_C40M80 FIDUCIAL_C40M80
@ @ @ @ @ @ @ @ @ @ @ @
FD3 FD4
@ @
1
+3VS H20 H22 H23 H24 FIDUCIAL_C40M80 FIDUCIAL_C40M80
H_2P0N H_2P7X2P0N H_3P5N H_5P5X5P0N
1
RF2 @ @ @ @
1
10K_0402_5%
40mil
JFAN1
2
+VCC_FAN1 1
FAN_SPEED1 2 1
<36> FAN_SPEED1 FAN_PWM1 3 2
<36> FAN_PWM1 4 3
1 4
5
6 G1
CF3 G2
2 1000P_0402_50V7K ACES_50278-00401-001
@EMI@ CONN@
SP02000RR00
2 2
Reset Circuit
+3VLP
RG1 1 @ 2 0_0402_5%
MAINPWON <36,44>
2
RG3 RG2 1 2 0_0402_5%
EC_RST# <36>
10K_0402_5%
6
D
BI_GATE# 2
G 2N7002KDW_SOT363-6
BI_GATE PH to +RTCVCC at PWR side QG1A
3
D S
1
1
BI_GATE 5
3 <42> BI_GATE G C70 3
QG1B 0.1U_0201_10V6K
2N7002KDW_SOT363-6 S 2
4
Reset Button
SWG2
BI_GATE 1 2 BI_GATE
3 4
SKRPABE010_4P
4 4

FAN & Screw Hole & Reset
A B C D E
A B C D E
DC Interface AOZ1331DI_DFN14_2X3
15
CQ5
.1U_0402_16V7K
1 2
RQ2
+5VALW
1U_0402_10V7
CQ8 1 2
7
6 VIN2
VIN2
GPAD
VOUT2
VOUT2
8
9 +5VS_OUT 1
@ JPQ2
1 2
2
+5VS
For Power ON/Off Sequence PM_SLP_S3
0_0402_5%
SUSP# 2 1 5VS_ON 5 10 1 2 JUMP_43X118 +3VALW
ON2 CT2
2
CQ1 1000P_0402_50V7K
G
1
1 2 4 11 Q1A
+5VALW VBIAS GND
CQ4 .1U_0402_16V7K R24 2N7002KDW_SOT363-6
@ 3 12 100K_0402_5%
1 ON1 CT1 1 6 1
2 CQ10
S
EC_VCCST_PG_R <11,36>
.1U_0402_16V7K
D
2 13
2
1 VIN1 VOUT1 14
VIN1 VOUT1
MOW14, For tCPU28 200us(max)
@ SLP_S3# to VCCST_PWRGD deassertion
5
1 UQ1
G
Q1B
Q2A 2N7002KDW_SOT363-6
2N7002KDW_SOT363-6 4 3
S
VR_ON <36,48>
D
1 2 D
2 MOW14, For tPLT17 200us(max)
AOZ1331DI_DFN14_2X3 <11,36> PM_SLP_S3# G
CQ7 SLP_S3# to IMVP VR_ON deassertion
5
15 .1U_0402_16V7K
G
+3VALW GPAD S
1
1U_0402_10V7 7 8 @ JPQ3 Q2B
CQ9 1 2 6 VIN2 VOUT2 9 +3VS_OUT 1 2 2N7002KDW_SOT363-6
VIN2 VOUT2 1 2 +3VS
4 3 SUSP#
S
3VS_ON 5
D
SUSP# 2 1 10 1 2 JUMP_43X118
ON2 CT2
RQ1 0_0402_5% CQ3 1000P_0402_50V7K MOW14, For tPLT18 200us(max)
4 11 SLP_S3# to VCCIO VR disable
+5VALW VBIAS GND
2
1 2
G
CQ2 .1U_0402_16V7K 2 CQ11 3 12 Q3A @
ON1 CT1
.1U_0402_16V7K
@ 2N7002KDW_SOT363-6
2 13
@ 1 VIN1 VOUT1 14 1 6
S
1 VIN1 VOUT1 SYS_PWROK <11,36>
D
UQ2
5
G
+3VALW Q3B @
2N7002KDW_SOT363-6
1
2 4 3 2
S
PCH_PWROK <11,36>
D
R29
100K_0402_5%
+5VALW +0.6VS_VTT
+2.5V +1.2V_VDDQ +5VALW
2
Q6A PM_SLP_S4
2
2N7002KDW_SOT363-6
2
5
R25 R26 D
G
2
100K_0402_5% @ @ 470_0603_5% R31 R27 R28 2 Q6B
<11,36> PM_SLP_S4# G
470_0603_5% 470_0603_5% 100K_0402_5% 2N7002KDW_SOT363-6
@ @ @
+0.6VS_VTT_R
1
SUSP S 4 3 SYSON
S
1
D
MOW14, For tPLT15 200us(max)
1
Q4A @ Q4B @ SLP_S4# to VDDQ ramp down
2N7002KDW_SOT363-6 2N7002KDW_SOT363-6 +1.2V_VDDQ_R SYSON#
6
D
D D
2 5 SUSP SYSON# 2 Q5A @ Q5B @
<14,36,43,45> SUSP# G G G 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
3
Q7 S D D
3
1
S S L2N7002WT1G_SC-70-3 SYSON# 2 5 SYSON

@ SYSON <14,36,45>
1
R30 G G
10K_0402_5%
@ S S
4
2
+1.8VALW_PRIM
+5VS +1.35VSDGPU
3 3
1.8A
2
CV236 VGA@ @
UV16 .1U_0402_16V7K R1007 R571
CV258 1 2 1 14 1 2 100K_0402_5% 47_0603_5%
DV9 VGA@ VGA@ 1U_0201_6.3V6M 2 VIN1 VOUT1 13 @
VIN1 VOUT1 +1.8VSDGPU_AON
2 BAV70W_SOT323-3
<12,22> DGPU_PWR_EN
1
1 DGPU_PWR_EN_AON 3 12 1 2 680P_0402_50V7K
3 ON1 CT1 CV238 VGA@ 1.35VSDGPU_PWR_EN# +1.35VSDGPU_R
<21,51> 1.35VS_DGPU_PG +5VALW
RV164 CV259 1 2 4 11
2 VGA@ 1 100K_0402_5% VGA@ 1U_0201_6.3V6M VBIAS GND
6
1.8VSDGPU_MAIN_EN 5 10 1 2 680P_0402_50V7K D D
<21,22> 1.8VSDGPU_MAIN_EN ON2 CT2 1.35VSDGPU_PWR_EN 1.35VSDGPU_PWR_EN#
CV235 1 2 CV239 VGA@ 5 2
6 9 <21,51> 1.35VSDGPU_PWR_EN G G
@ .1U_0402_16V7K +1.8VSDGPU_MAIN
7 VIN2 VOUT2 8 1 2
+1.8VALW_PRIM VIN2 VOUT2 S S
1
15 CV237 +5VS +1.0VSDGPU Q2513B Q2513A
2 GPAD .1U_0402_16V7K 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
EM5209VF_DFN14_2X3 VGA@ @ @
2
VGA@
CV262 1 R4916 R574
@
1U_0201_6.3V6M 100K_0402_5% 10_0603_1%
VGA@ VGA@
1
+5VS +VGA_CORE
PEX_VDD_EN# +1.0VSDGPU_R
2
6
R4911 R4910
100K_0402_5% 47_0603_5% PEX_VDD_EN 5 G
D D
G 2 PEX_VDD_EN#
<22,52> PEX_VDD_EN
@ @ Q2515A S S Q2515B
PJT138KA 2N SOT363-6 PJT138KA 2N SOT363-6
1
1
4 VGA_CORE_EN# +VGA_CORE_R VGA@ VGA@ 4
3
1.8VSDGPU_MAIN_EN 5
D D
2 VGA_CORE_EN#
G G
Q2516A S S Q2516B Security Classification Compal Secret Data

PJT138KA 2N SOT363-6 PJT138KA 2N SOT363-6 Issued Date 2018/12/27 2019/12/27 Title
Deciphered Date
4
@
@
DC Interface
A B C D E
A B C D E
1 1
+19V_ADPIN 5A_Z120_25M_0805_2P
EMI@ PL101
+19V_VIN
@ PJP101 1 2
ACES_50278-00401-001
6
G2 5
G1
1
4
4
1
3 EMI@ PC104
3 2 EMI@ PC105 PC102 EMI@ 1000P_0402_50V7K
2
2 1 1000P_0402_50V7K 100P_0402_50V8J
2
1
2 2
@
PR101
1 2
+3VLP +CHGRTC
0_0402_5%
3 3
4 4
2018/12/27
Compal Secret Data
2019/12/27 Title
PWR DCIN / Pre-charge
A B C D E
A B C D E
+3VLP
1 1
1
OTP@
PC205
1
PR207 100_0402_1% 0.1U_0402_25V7K
MB:Battery Con Put TOP Side
2
1 2 OTP@ OTP@
EC_SMB_DA1 <36,43>
PR205 100_0402_1% PR215 PR214
1
1 2 OTP@ 10K_0402_1% 10K_0402_1%
EC_SMB_CK1 <36,43> <45,47> PR213
2
100K_0402_1% OTP@
PU201
Battery Bot Side PR202 1 8
2
200K_0402_1% VCC TMSNS1
1 2 2 7 2 1
PIN1 GND @ PJP201 +3VLP GND RHYST1
GPU_ALERT# 1 GPU_ALERT#_R
PIN2 GND 1 2
1
<36> GPU_ALERT#
2 3
OT1 TMSNS2
6 PR216
1
1 2 PR218 47K_0402_1%
PIN3 SMD 2 3
3 4
EC_SMB_DA1-1
EC_SMB_CK1-1
BATT_TEMP <36,43>
0_0402_5%
4
OT2 RHYST2
5 OTP@ OTP@
PR203 1K_0402_1% PH202
PIN4 SMC 4 5 BATT_TS OTP@ G718TM1U_SOT23-8 100K_0402_1%_NCP15WF104F03RC
5 6
PIN5 TEMP BATT_B/I
2
6 7
PIN6 BI 7 8
8 9 +RTCVCC
PIN7 Batt+ GND 10
PIN8 Batt+ GND
CVILU_CI9908M2HR0-NH
2016/11/16 update
1
PR212
100K_0402_5% For KB9022
PQ201 Change to SB00000QO00,
sense 20mΩ Active Recovery
SB501380010(BSS138LT1G Del)
2
2 2
1
D
<39> BI_GATE 2 PQ201
G LBSS139LT1G 1N SOT-23-3 45W PR206 58.5W,1V Active=recovery
+12.6V_BATT+ S
2.32K ohm
3
EMI@ PL201
2
5A_Z120_25M_0805_2P @
1 2 PR217
change PL201, PL202 +12.6V_BATT 65W PR206
SM01000C000 to comm PL202 0_0402_5% 84.5W,1V
1 2
7.87K ohm Active=recovery
part SM01000P200
1
5A_Z120_25M_0805_2P
EMI@ 90W PR20K __W,__V
ohm Active=recovery
1
EMI@ PC201 EMI@ PC202

1000P_0402_50V7K 0.01U_0402_25V7K PH1 under CPU botten side :
2
PH1 2V 1V CPU thermal protection at 89 +-3 degree C

Recovery at 56 +-3 degree C
2013/06/07
Add for ENE9022 Battery Voltage drop detection.
Connect to ENE9022 pin64 AD1.
3 +3VLP_ECA 3
ADP_I <36,43>
+19VB_5V
VAL50/ZAL20 Battery is 3-cell NVDC design.
1
B+=9V PR204
Change PR12=50k if Battery is 2-cell NVDC design 16.9K_0402_1%
45W@ PR206
B+=6V
1
2.32K_0402_1%
2
PR209 65W@
VCIN0_PH <36>
750K_0402_1%
@ PR206
7.87K_0402_1%
PR210
2
1
1
1 2
VCIN1_BATT_DROP <36> PC203 must close to EC pin
2
PH201
VCIN1_ADP_PROCHOT <36>
@ PC203
0_0402_5% 100K_0402_1%_NCP15WF104F03RC 0.1U_0402_25V6
1
1
1
2
2
PC204 PR211 PR208

0.1U_0402_25V6 150K_0402_1%
T202 T201 must close to PH201
T202@ 10K_0402_1%
1
2
T201@
ECAGND <36>
4 4
2018/12/27
Compal Secret Data
2019/12/27 Title
PWR-BATTERY CONN/OTP
A B C D E
A B C D E
PRB1
1
D
1M_0402_1%
2 1 2
PQB1 +19VB PQB2 AON7506_DFN33-8-5
1
G L2N7002SW T1G_SOT323-3 2 +12.6V_BATT_CHG
PRB2 S 5 3
3
2 1
+19V_P1 +19V_P2
PQB3 3M_0402_5%
4
EMB04N03H_EDFN5X6-8-5
1
AON7506_DFN33-8-5
1
PQB4 PRB3
0.01_1206_1% EMI@ PLB1
+19V_CHG
2 2 HCB2012KF-121T50_0805
5 3 3 5 1 4 1 2
+19V_VIN
2 3
10U_0603_25V6M
PCB8 @ 10U_0603_25V6M
0.047U_0603_25V7M
4
4
1 1
PCB2
10U_0603_25V6M
1000P_0402_50V7K
2200P_0402_50V7K
1 2
1
1
PCB1
PCB3
PCB4
ACP ACN
68P_0402_50V8J
0.1U_0402_25V6
0.1U_0402_25V6
1
1
@EMI@ PCB5
EMI@ PCB6
PCB9
EMI@ PCB10
0.022U_0603_25V7K
2
4.7_0603_1%
4.02K_0402_1%
2
10_0402_1%
PRB4
PCB12
PCB11
2
0.1U_0402_25V6 PCB13
PRB5
PRB6
EMI@
2 1 1 2 1 2
PCB7
1 0.01U_0402_25V7K~N
2
ACDRV_CHGR_R 0.1U_0402_25V7K
PRB7
4.02K_0402_1% BATDRV_CHGR
ACFET MDU1512 SB00000SY00 1 2 ACDRV_CHGR
1
Rds(on):4.2~5m Ohm PRB8 PRB9
Vgs=20V 0_0402_5%
Vds=30V 2 1CMSRC_CHGR 0_0402_5% BATSRC_CHGR
ID= 24.2A (Ta=70C) PRB10
2
4.02K_0402_1%
ACN_CHGR
ACP_CHGR
+19V_VIN
PDB1 PRB12 @ PCB15
S SCH DIO BAS40CW SOT-323 10_1206_5% 1000P_0402_50V7K 2016/03/13 SE158225K80 X1
+19V_VIN
3 1 2 down size SE00000WP00 S
1
1 2 1
PRB11 +19VB 2 ACDRV_CHGR CER CAP 2.2U 25V K X5R 0603
422K_0402_1% PCB16 1U_0603_25V6K +6V_CHG_REGN
2 1 PCB18 PQB5
2.2U_0603_25V7M AON7506_DFN33-8-5
2
5
2 ACDET PUB1 2
1 2 Choke 4.7uH SH00000YC00 (Common Part)
ACDRV
ACP
ACN
28
VCC PRB14
(Size:6.6 x 7.3 x 3 mm)
66.5K_0402_1%
(DCR:28m~33m)
1
CMSRC_CHGR 3 24 0_0603_5%
CMSRC REGN
1
2DH_CHGR_R 4
PRB13
@ PCB19 1
6 PRB16
PCB17 0.047U_0603_25V7M
2200P_0402_25V7K @ ACDET 25 BST_CHGR1 2BST_CHGR_R 1 2
2
PRB15 1 2 0_0402_5% EC_SMB_DA1_CHGR 11 BTST

<36,42> EC_SMB_DA1 +12.6V_BATT
2
SDA
3
2
1
PRB17 1 @ 2 0_0402_5% EC_SMB_CK1_CHGR 12 26 UG_CHGR 0_0603_5% PRB19
<36,42> EC_SMB_CK1 SCL HIDRV PLB2 0.01_1206_1%
ACPRN_CHGR 5 4.7UH_PCMB063T-4R7MS_8A_20%
<36,42> ADP_I PCB20 ACOK 27 LX_CHGR 1 2 1 4
1 2 PRB18 1 2 0_0402_5% 7 PHASE
IADP 2 3
1
100P_0402_50V8J DCHG_I 8 23 LG_CHGR PQB6
4.7_1206_5%
IDCHG LODRV
EMI@ PRB20
1 2 9
10U_0603_25V6M
10U_0603_25V6M
AON7506_DFN33-8-5
PMON
@ PCB21 10 22 PRB22 316K_0402_1% SRP SRN
1SNUB_CHGR 2
/PROCHOT GND
1
1 2
PCB22
PCB23
100P_0402_50V8J
@ +3VLP 4
PRB24 78.7K_0402_1%
PRB23
2
13 21 ILIM_CHGR 1 2
1 2 GND ILIM PRB25
680P_0402_50V7K
<7,36> H_PROCHOT# 14 10_0402_1%
3
2
1
NC 20 SRP_CHGR 1 2
EMI@ PCB24
@
0_0402_5% PRB26 SRP
1 2 15 19 SRN_CHGR 1 2
20160601 colay BQ24781
2
/BATPRES SRN
3 PRB27 3
0_0402_5% 16 18 BATDRV_CHGR 10_0402_1% PCB25
/TB_STAT BATDRV 0.1U_0402_25V6
29 17 BATSRC_CHGR 1 2
PWPD BATSRC
For 4S per cell 4.35V battery <36,42> BATT_TEMP
CHG_TB_STAT BQ24781RUYR_W QFN28_4X4
+6V_CHG_REGN
ACDET 3.3*100/(316+100)=0.79 H/L Side AON7506 SB000010A00
0.1U_0402_25V6
0.1U_0402_25V6
@ PRB36
+3VS ICHG= 0.79 /(20*0.01)=3.95A Rds(on):13~15.8mohm
1
PCB26
PCB27
10K_0402_1%
1 2 Vgs=20V
1
4S_BATT@ 3.3*78.7/(316+78.7)=0.66 Vds=30V
2
PRB28 ICHG= 0.66 /(20*0.01)=3.28A ID= 10.5A (Ta=70C)
2M_0402_1%
1
@VGA@ @VGA@ +6V_CHG_REGN

1 2
PRB29 PRB30
4S_BATT@ 10K_0402_1% 10K_0402_1%
PRB31
0_0402_5%
2
1
PRB32
2
<10,21,36> DGPU_AC_DETECT 10K_0402_1%

PRB34
1
4S_BATT@ 10K_0402_1%
2
PQB7 1 2 ACPRN_CHGR
<36> AC_IN
6
4S_BATT@ PRB33 LTC015EUBFS8TL_UMT3F D 1

100K_0402_1% 2
1 2 2 G PRB35
<36> BATT_4S
@VGA@
4 PQB10 PQB8B S PQB8A 12K_0402_1% 4
1
1
RUM001L02_VMT3 2N7002KDW _SOT363-6 2N7002KDW _SOT363-6

2
4S_BATT@
3
1
PQB9 D D
2 H_PROCHOT# 2 AC_IN 5 @VGA@
<14,36,40,45> SUSP# G G
L2N7002SW T1G_SOT323-3S S
3
4
3

@VGA@
charger
A B C D E
A B C D E
PR302
499K_0402_1%
ENLDO_3V 1 2
EN1 and EN2 dont't floating
+19VB
1
150K_0402_1%
+19VB
PR303
EMI@ PL301 @ PC302
PR304
FBMA-L11-201209-800LMA50T 0.1U_0402_25V7K
1
1 2 +19VB_3V BST_3V 1 2 1 2 1
2200P_0402_50V7K
10U_0603_25V6M
10U_0603_25V6M
2
EMI@ PC301
@EMI@ PC303
EMI@ PC304
0.1U_0402_25V6
0.1U_0402_25V6
1
1
0_0603_5%
@ PC305
PC306
1
PU301
2
PL302
BS
IN
IN
IN
IN
1.5UH_6A_20%_5X5X3_M
LX_3V 6 20 LX_3V 1 2
LX LX +3VALWP
7 19
GND LX
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
8 18
+3VALWP GND GND
@ PC307
PC308
PC309
@ PC310
PC311
PC312
SY8286BRAC_QFN20_3X3 @EMI@
SPOK_3V 9 17 PR305
+3VLP
2
PG LDO 4.7_1206_5%
1 3V_SN
10 16
2
NC NC
1
PC313
OUT
EN2
EN1
21 4.7U_0402_6.3V6M
NC
FF
2
PR301 GND @EMI@
100K_0402_5% PC314
11
12
13
14
15
680P_0402_50V7K
2
Vout is 3.234V~3.366V
<36,47> SPOK_3V
3.3V LDO 150mA~300mA
ENLDO_3V PC315 PR306

1000P_0402_50V7K 1K_0402_5%
3V_FB 1 2 1 2
<36> 3V_EN
@ PJ301
+3VALWP 1 2 +3VALW
1 2
keep short pad, JUMP_43X118
2 snubber is for EMI only. 2
+19VB_5V
+19VB EMI@ PL501 @ PC502
PR502
FBMA-L11-201209-800LMA50T 0.1U_0402_25V7K
1 2 +19VB_5V 1BST_5V 2 BST_5V_R 1 2
Choke 1.5uH SH00000II00, SH000008800, SH000019B00
2200P_0402_50V7K
0.1U_0402_25V6
0.1U_0402_25V6
0_0402_5% (Size:6.8 x 6.47 x 3 mm)

10U_0603_25V6M
10U_0603_25V6M
PU501
(DCR:14m~15m Ohm)
5
1
SY8288CRAC_QFN20_3X3
1
1
@EMI@ PC501
PC503
PC504
EMI@ PC505
@EMI@ PC506
BS
IN
IN
IN
IN
PL502
LX_5V 6 20 1.5UH_MMD-06CZ-1R5M-V1_9A_20%
2
LX LX
7 19 LX_5V 1 2
GND LX +5VALWP
8 18
GND GND
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
+3VLP
1
9 17 VCC_5V 1 2
PG VCC
1
PR503
PC508
PC509
PC510
PC511
PC512
PC513
4.7_1206_5%
@EMI@
10 16 PC507
2
NC NC
1
2.2U_0402_6.3V6M
OUT
LDO
EN2
EN1
21 @
FF
PR501 GND
2
100K_0402_5%
11
12
13
14
15
2
15V_SN
680P_0402_50V7K
<36> SPOK_5V +5VLP
ENLDO_5V
@EMI@
PC514
5V LDO 150mA~300mA
4.7U_0402_6.3V6M
2
1
PC515
PR504
2.2K_0402_5% 5V_3V_EN
2
1 2 Iocp=12A
<36> EC_ON PR505
@
1 2 EN1 and EN2 dont't be floating.
3
<36,39> MAINPWON EN :H>0.8V ; L<0.4V PC516 PR506 @ PJ501
3
1000P_0402_50V7K 1K_0402_1% +5VALWP 1 2 +5VALW
0_0402_5% 5V_FB 1 2 5V_FB_1 1 2 1 2
Fsw : 600K Hz
JUMP_43X118
5V_3V_EN
1M_0402_1%
1
1
PR507
PC517
4.7U_0402_6.3V6M
2
2
PR509
499K_0402_1%
ENLDO_5V 1 2
+19VB
1
150K_0402_1%
PR508
4 4

+3VALW/+5VALW
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A B C D E
A B C D E
Pin19 need pull separate from +1.35VP.

+19VB_1.2VP If you have +1.35V and +0.675V sequence question, 0.6Volt +/- 5%
@ PJM1 you can change from +1.35VP to +1.35VS. TDC 0.7A
JUMP_43X79
1
1 2 +19VB_1.2VP PRM1 Peak Current 1A 1
+19VB 1 2 2.2_0603_5%
BST_1.2VP_R 1 2 BST_1.2VP
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
0.1U_0402_25V6
+1.2VP
1
@EMI@ PCM1
EMI@ PCM2
PCM3
PCM4
UG_1.2VP +0.6VSP
2
PQM1
AON7408L_DFN8-5
LX_1.2VP
10U_0402_6.3V6M
10U_0402_6.3V6M
5
1
PCM5
1
PCM6
PCM7
0.1U_0402_25V7K
16
17
18
19
20
2
2
VLDOIN
PHASE
UGATE
BOOT
VTT
4 21
PAD
LG_1.2VP 15 1
LGATE VTTGND
PLM1
1
2
3
14 2
1UH_11A_20%_7X7X3_M PRM2 PGND VTTSNS
30.9K_0402_1% PUM1
1 2LX_1.2VP 1 2 CS_1.2VP 13 3
+1.2VP PCM8 CS RT8207PGQW _W QFN20_3X3 GND
1
1U_0402_10V6K
5
1 2 12 4 VTTREF_1.2VP
@EMI@ PRM3 PRM4 VDDP VTTREF
2 4.7_1206_5% 5.1_0603_5% 2
1 2 VDD_1.2VP 11 5
+5VALW +1.2VP
1 2
VDD VDDQ
1
PGOOD
PCM12
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
TON
1
PCM9
PCM13
PCM14
PCM10
PCM15
PCM16
@EMI@ PCM11 PCM17 0.033U_0402_16V7K
FB
S5
S3
2
1
680P_0402_50V7K
2
2 PQM2 1U_0402_10V6K
10
6
AON7506_DFN3X3-8-5 PRM5
1
2
3
2.2_0402_1%
FB_1.2VP
2
TON_1.2VP
EN_1.2VP
PRM6
+5VALW
EN_0.6VSP
6.19K_0402_1%
PRM7 1 2 +1.2VP
470K_0402_1%
+19VB_1.2VP 1 2
1
PRM8 Vout=0.75V* (1+Rup/Rdown)
<14,36,40> SYSON
SYSON 1 2 PRM9 =0.75*(1+(6.19/10))
10K_0402_1%
0_0402_5% =1.21V
2
1
@ PCM18
+5VALW 0.1U_0402_10V7K
2
+3VALW @ PRM10
0_0402_5%
1 2
<14,36,40,43> SUSP#
@ PJM2
3 JUMP_43X39 @ @ PJM3 3
PRM11
1
1 2 VIN_2.5V PCM19 JUMP_43X118

1 2 1U_0402_6.3V6K 1 2 1 2
+1.2VP +1.2V_VDDQ
<8> SM_PG_CTRL 1 2
2
0_0402_5%
1
1
@ PCM21 @ PJM4
PCM20 JUMP_43X39
4.7U_0402_6.3V6M 0.1U_0402_10V7K 1 2
+0.6VSP +0.6VS_VTT
2
2
PUM2 1 2
G9661MF11U_SO8
@ 4 5
PRM12 VPP NC
3 6 MOSFET: 3x3 DFN
SYSON 1 2 EN_2.5V 2 VIN VO 7 +2.5VP
H/S Rds(on): 27mohm(Typ), 32mohm(Max)
GND
1 VEN ADJ 8
22U_0603_6.3V6M
0.01U_0402_25V7K
POK GND Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C

1
0.1U_0402_16V7K
PCM23
0_0402_5% PRM14
9
1
1
PCM22
PCM24
PRM13
21.5K_0402_1%
Rup L/S Rds(on): 13mohm(Typ), 15.8mohm(Max)
Vout=0.8V* (1+(21.5/10)) = 2.52V 0.8%Idsm: 12A@Ta=25C, 10.5A@Ta=70C
2
1M_0402_5%
2
2
2
FB_2.5V
@ Choke: 7x7x3
Rdc=14mohm(Typ), 15mohm(Max)
1
Mode Level +0.6VSP VTTREF_1.2V

PRM15
S5 L off off Switching Frequency: 538kHz
10K_0402_1%
Rdown S3 L off on Ipeak=7.5A
S0 H on on Iocp=Ipeak*1.2A
2
4
OVP: 110%~120% 4
@ PJM5
Note: S3 - sleep ; S5 - power off VFB=0.75V, Vout=1.365V
JUMP_43X39
1 2
MOSFET footprint: SIS412DN
+2.5VP 1 2 +2.5V

RT8207P
A B C D E
A B C D E
EN pin don't floating

If have pull down resistor at HW side, pls delete PR702
1 +19VB_1VALW @EMI@ PRF2 @EMI@ PCF2

1
4.7_1206_5% 680P_0603_50V7K @ PJF1

@ PJF2 1 2 SNUB_1VALW 1 2 JUMP_43X118
PUF1 1 2
JUMP_43X79 @
+19VB_1VALW +1.05VALWP 1 2 +1.05VALW_PRIM
+19VB 2
2 1
1 2
IN PG
9 PRF1
0_0603_5%
PCF5
10U_0603_25V6M
0.1U_0402_25V6
3 1 BST_1VALW 1 2 BST_1VALW_R1 2 PLF1
2200P_0402_50V7K
IN BS
1
1UH_6.6A_20%_5X5X3_M
EMI@ PCF3
@EMI@ PCF4
PCF6
LDO_3V LX_1VALW
4
IN LX
6
0.1U_0402_25V7K
1 2
+1.05VALWP
2
@ 5 19
15.4K_0402_1%
330P_0402_50V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
IN LX
1
PRF4
1
PRF3 7 20
PCF7
PCF8
PCF1
PCF9
PCF10
PCF11
PCF16
PCF17
GND LX
0_0402_5%
8 14 FB_1VALW Rup
2
GND FB @ @
2
2
ILMT_1VALW 18 17 LDO_3V
GND VCC
1
1
EN_1VALW 11 10
EN NC
@ PRF5 PCF13 FB = 0.6V
1
ILMT_1VALW 13 12 2.2U_0402_6.3V6M
2
ILMT NC PRF6
0_0402_5%
15 16
+3VALW Rdown
2
BYP NC 20K_0402_1%
21
Ipeak=9.5A
2
PAD Imax=6.65A
SY8288RAC_QFN20_3X3 Pin 7 BYP is for CS.
1
The current limit is set to 6A, 8A or 12A when this pin Common NB can delete +3VALW and PC15
PCF14
is pull low, floating or pull high 1U_0201_6.3V6M
2
Vout=0.6V* (1+Rup/Rdown)
+3VALW =0.6*(1+(15.4/20))
Vout=1.062V
2 2
2
@ PRF7
10K_0402_1%
1
@
PRF8
EN_1VALW 1 2
1.8VALW_PG <47>
0_0402_5%
1
PRF9
0.22U_0402_10V6K
2
1M_0402_1%
@ PCF15
2
3 3
4 4

VCCP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
A B C D E
A B C D E
+3VALW +5VALW
@ PJ1802
JUMP_43X39
1 2
+1.8VALWP 1 2 +1.8VALW_PRIM
1
PC1801
1 1
1U_0402_6.3V6K
2
1
PC1804
4.7U_0402_6.3V6M
2
PU1801
G9661MF11U_SO8
@ 4 5
PR1801 3 VPP NC 6
SPOK_3V 1 2 EN_1.8VALW 2 VIN VO 7 +1.8VALWP
GND
<36,44> SPOK_3V VEN ADJ
1 8
0.01U_0402_25V7K
POK GND
PC1803
0_0402_5%
1
PR1804
9
@ 12.7K_0402_1%
PC1802
Rup
2
PR1802 0.1U_0402_16V7K
1
1M_0402_1% FB_1.8VS
2
+3VALW PC1805
22U_0603_6.3V6M
2
1
2
PR1803
PR1805 10K_0402_1%
10K_0402_1%
Rdown
2
1
1.8VALW_PG
<46> 1.8VALW_PG
Vout=0.8V* (1+(12.7/10)) = 1.816V
2 2
3 3
4 4

SY8032
A B C D E
1 2 3 4 5
Module model information

Close IC
PRZ1 and PRZ22 are for debug only. RT3602AE_U22_RU42_colay_V1A.mdd for IC portion
VCCSSA_SENSE and VSSSA_SENSE need other resistor at HW side.
RT3602AE_U22_RU42_colay_V1B.mdd for SW portion
RT3602_VREF Vref=0.6V +VCC_SA PRZ1 PRZ8 PRZ10
100_0402_1% 10K_0402_1% 57.6K_0402_1% PCZ3
1 2 VCCSA_SENSE_R 1 2 1 2 0.1U_0402_25V6
1
953_0402_1%
15K_0402_1%
6.81K_0402_1%
PRZ15
@ 1 2 1 2
2
1
1
<14> VCCSA_SENSE
1 2 <49> ISENSE1N_SA ISENSE1P_SA_R1 <49>
@ PCZ200 PCZ5 390P_0402_50V7K PCZ6 68P_0402_50V8J
PRZ2
PRZ3
PRZ4
0_0402_5% 0.1U_0402_25V6
2
A @ PCZ1 @ PRZ16 A
FB_SA FB_SA
0.1U_0402_10V6K 10K_0402_1% @ PCZ4
2
1
1 2 1 2 0.47U_0402_25V6K
@ PCZ203 1 2
1
1
0.1U_0402_25V6
10_0402_1%
11K_0402_1%
4.99K_0402_1%
0.47U_0402_6.3V6K
@ PRZ94
Close IC RT3602_VREF
PRZ6
PRZ11
PCZ193
IMON_SA_R
1
0_0402_5% 1 2 1 2
PRZ5
1 2
<14> VSSSA_SENSE PRZ13 PRZ14
2
2
RT3602_SET1
2
1
PRZ22 48.7K_0402_1% 0_0402_5%
RT3602_SET2 1 2 @ PCZ199
RT3602_SET3
0.1U_0402_25V6
Close IC
RT3602_VREF 3.9_0402_1%
2
1
100_0402_1%
PRZ24
VR_PSYS @
PRZ95
PRZ23 +3VS
1
<16> VSSSENSE 1 2 100K_0402_1%

464_0402_1%
10K_0402_1%
1.1K_0402_1%
5.23K_0402_1%
1 2
Close CORE1 choke
PRZ18
PRZ19
PRZ20
2
PRZ17
0_0402_5% PRZ21
@ PRZ107 PHZ1 PRZ26 1 2
VR_PWRGD <36> EN
2
0_0402_5% 100K_0402_1%_B25/50 4250K 40.2K_0402_1% @ PRZ25 High: > 0.7V

@ PCZ7 1 2PHZ1_R1 1 2 PHZ1_R 1 2 100_0402_1% 0_0402_5%
0.1U_0402_25V6
RGND_MAIN 1 2 VR_ON
Low: < 0.3V
<36,40>
2
RT3602_VREF
1
1
3K_0402_1%
499_0402_1%
2.1K_0402_1%~N
SOC_SVID_CLK_R +1.05V_VCCST
IMON_SA
PRZ29
PRZ30
1 2 IMON_CORE_R 1 2 U22@ PRZ35 SOC_SVID_DAT_R
RT3602_EN
PRZ28
VSEN_CORE
RGND_MAIN
FB_SA
PRZ33 U42@ 4.22K_0402_1%
COMP_SA
RGND_SA
VR_PSYS
26.7K_0402_1% @ PCZ9 PRZ35 @ PCZ206
2
1
@ PCZ204 0.1U_0402_10V6K 4.22K_0402_1% @ PCZ201 0.1U_0402_25V6
PCZ194
110_0402_1%
0.1U_0402_25V6
1
1
0.1U_0402_25V6 U42@ PRZ45 @ PCZ207 1 2 0.1U_0402_25V6 1 2
75_0402_1%
100_0402_1%
45.3_0402_1%
1
63.4K_0402_1% 47P_0402_50V8J @
PRZ37
CORE1_LX <49> CORE1_LX 1
2
@ PCZ8 @ PRZ40 2 1 2
2
0.1U_0402_10V6K 10K_0402_1% 1M_0402_1% PRZ108 PUZ1
49
48
47
46
45
44
43
42
41
40
39
38
37
PRZ36
PRZ38
PRZ39
2
1 2 1 2 @ RT3602AJGQW_WQFN48_6X6 @
Close IC
2
PRZ43 U22@ PRZ45
GND
RGND_MAIN
VSEN_MAIN
EN
PSYS
FB_SA
RGND_SA
COMP_SA
ISENN_SA
ISENP_SA
IMON_SA
VR_READY
VREF06/PSET
10K_0402_1% 46.4K_0402_1% SOC_SVID_CLK <16>
VSEN_CORE 1 2 1 2 SOC_SVID_ALERT#_R <16>
+VCC_CORE PRZ41
IMON_CORE SOC_SVID_DAT <16>
100_0402_1% PCZ11 PCZ12 82P_0402_50V8J 1 36 PWM_SA <49>
1 2 1 2 1 2 2 RT3602_SET1 IMON_MAIN PWM_SA 35 VR_HOT# <36>
FB_CORE SET1 DRVEN DRVEN_CPU <49>
3 34 1 2
PRZ47 COMP_CORE FB_MAIN VCLK
@ <49> ISENSE1N_CORE PCZ13 4 33 PRZ98 49.9_0402_1%
1 2 330P_0402_50V7K 0.1U_0402_25V6 5 RT3602_SET2 COMP_MAIN ALERT# 32 PRZ99 1 210_0402_1% PRZ48 RT3602_VREF
<16> VCCSENSE
1 2 Ra 6 RT3602_SET3 SET2 VDIO 31 VR_HOT#_R 1
PRZ100 2
100_0402_1% 30K_0402_1% PRZ49 5.49K_0402_1%
SET3 VR_HOT# IMON_GT 2 IMON_GT_R 1
1
U42@ PRZ106 7 30 1 2
0_0402_5% @ PCZ196 1 2 1 2 ISEN1N_MAIN 8 ISEN1N_MAIN IMON_AUXI 29 @ PCZ15 0.47U_0402_25V6K
Close IC
U42@ 0_0402_5% 9 ISEN2N_MAIN ISENP_AUXI 28 1 2
0.1U_0402_25V6
2
PCZ16 0.1U_0402_25V6 10 ISEN2P_MAIN ISENN_AUXI 27 VSEN_GT

<49> ISENSE2N_CORE TSEN_CORE 11 ISEN1P_MAIN VSEN_AUXI COMP_GT
26 ISENSE1P_GT_R1 <49>
RT3602_VIN 12 TSEN_MAIN COMP_AUXI 25 @ PRZ50
Rb VIN RGND_AUXI ISENSE1N_GT <49>
PWM1_MAIN
PWM2_MAIN
DRVEN_SET
B 1 2 0_0402_5% B
TSEN_AUXI
PWM_AUXI
+5VALW VSEN_GT
RGND_AUXI
U22@ PRZ105 10K_0402_1% 1 2 1 2 VCCGT_SENSE <16>
FB_AUXI
0.22U_0402_25V6K
1
1
PCZ18
2.2_0805_1%
<49> ISENSE2P_CORE_R1
0.1U_0402_25V6 PRZ54 PRZ56 PRZ59
PRZ41 and PRZ21 are for debug only.
VCC
23.2K_0402_1% 10K_0402_1% 100_0402_1% +VCC_GT
NC
NC
NC
NC
NC
Rc
PRZ53
PCZ19
2
VCCCORE_SENSE and VSSCORE_SENSE need other resistor +5VALW
1 2 1 2 1 2 1 2
U22@ PRZ104 10K_0402_1%
at HW side.
13
14
15
16
17
DRVEN_SET 18
19
20
21
22
TSEN_GT 23
FB_GT 24
1
<49> ISENSE1P_CORE_R1
1 2 1 2 @ PCZ198
Ra Rb/Rc RT3602_VREF U42@ PRZ51 PRZ52 0.1U_0402_25V6
RT3602_VCC
2
110K_0402_1% 1.65K_0402_1% PCZ20 82P_0402_50V8J PCZ21
TSEN_CORE_R 1 2 1 2 270P_0402_50V7K
U42@
+19VB_CPU
PHZ2
U22 N/A Stuff
1
1 2 1 2 1 2
15K_0402_1%
U22@ PRZ63 U22@ PRZ64 @ PCZ202

1
FB_GT
13K_0402_1% 9.76K_0402_1% U42@ @ PRZ61 @ PCZ22 0.1U_0402_25V6
10K_0402_1%
100K_0402_1%_B25/50 4250K
2
10K_0402_1% 0.1U_0402_10V6K
U42 Stuff N/A
PRZ64
<49>
PWM_GT
Close CORE1 MOSFET
PRZ63
+5VALW
<49>
<49>
PRZ65
Close IC
PWM_CORE2
PWM_CORE1
2
U22@ PRZ51 U22@ PRZ52 8.2_0402_1%

U42@
8.45K_0402_1% 33.2K_0402_1% 1 2
U42@
PRZ93
1
@
1K_0402_1%
2.87K_0402_1%
U22@ PRZ68 1 2
U42@ PRZ68
VSSGT_SENSE <16>
U22@ PRZ67 3.92K_0402_1% U22@ PHZ2
PRZ67
1
2.32K_0402_1% 220K_0402_5%_B25/50 4700K
0_0402_5%
1
+5VALW PCZ23
1 U42@ 2
1
4.7U_0402_6.3V6M PRZ66 U22@ PRZ66
TSEN_CORE_R TSEN_GT_R
2
110K_0402_1% 8.45K_0402_1% @ PCZ197 PRZ60
1
100K_0402_1%_B25/50 4250K
0.1U_0402_25V6 100_0402_1%
2
1
U42@
2
1
@ PRZ72 U22@ PRZ69

2K_0402_1%
13K_0402_1%
33.2K_0402_1%
U42@ PRZ71
10K_0402_5%
U22@ PRZ70 U22@ PRZ71
PRZ70
1
1.37K_0402_1% 2.32K_0402_1%
PHZ3
2
DRVEN_SET PRZ69 U22@ PHZ3

1U42@ 2
1.65K_0402_1% 220K_0402_5%_B25/50 4700K
U42@
1
U42@
2
1
PRZ75
15K_0402_1%
10K_0402_1%
U22@ PRZ74
PRZ74
10K_0402_5%
U22@ PRZ73 16.5K_0402_1%
Close GT MOSFET
PRZ73
TSEN_GT_R
15K_0402_1%
PRZ59 and PRZ60 are for debug only.
2
2
VCCGT_SENSE and VSSGT_SENSE need other resistor

U42@
U42@
at HW side.
C
Set DRVEN output function at PS4. Set to 5V DRVEN C
is floating, and set to GND DRVEN is low at PS4.
D D

CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
EH7LW M/B LA-H791P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 2 3 4 5
5 4 3 2 1
+19VB_CPU
@
PJZ1 +19VB
1 2 +19VB_CPU
1 2
PRZ76
33U_25V_M
33U_25V_M
10U_0603_25V6M
10U_0603_25V6M
JUMP_43X118
2200P_0402_50V7K
2.2_0603_5%
PCZ29
PCZ30
PCZ31
PCZ32
CORE1_BST CORE1_BST_R 1 1
0.1U_0402_25V6
D D
1 2
1
+ + U42@ PRZ77
PCZ26
PCZ37
PCZ34
PCZ195
10U_0603_25V6M
10U_0603_25V6M
1
2200P_0402_50V7K
PQZ1 2.2_0603_5%
@EMI@ PCZ36
EMI@ PCZ33
CORE2_BST CORE2_BST_R
0.1U_0402_25V6
PCZ28 1 2
EMIU42@
@EMIU42@
PUZ2
1
2 2
AON6380_DFN5X6-8-5
0.1U_0402_25V6
1
U42@
4 3 CORE1_UG 1 2 CORE1_UG_R 4 U42@ U42@ PCZ35
PUZ3
2
BOOT UGATE PRZ78 U42@ 0.1U_0402_25V6
2
5 2 0_0603_5%
<48> PWM_CORE1 PWM PHASE 4 3 CORE2_UG 1 2 CORE2_UG_R4
1 6 BOOT UGATE U42@ PRZ79 U42@
<48> DRVEN_CPU Rdc=0.9mohm
3
2
1
+5VALW EN PGND +VCC_CORE 5 2 CORE2_LX 0_0603_5% PQZ3
VCC_CORE1 PLZ1 <48> PWM_CORE2 PWM PHASE
1 PRZ80 2 8 7 AON6380_DFN5X6-8-5
VCC LGATE 9 CORE1_LX 1 4 +5VALW DRVEN_CPU 1 6
Rdc=0.9 mohm
3
2
1
5.1_0402_1% GND EN PGND +VCC_CORE
ISENSE1P_CORE 2 3 1 2 VCC_CORE2 8 7 U42@ PLZ2
RT9610CGQW_WDFN8_2X2 VCC LGATE
1
PQZ2 9 1 4
@EMI@ PRZ82
4.7_1206_5%
GND
1
PCZ40 U42@ PRZ81
CORE1_LX <48> 0.15UH_NA__35A_20% ISENSE2P_CORE 2 3
1U_0402_10V6K 5.1_0402_1%
2
RT9610CGQW_WDFN8_2X2
1
AON6314_N_DFN56-8-5
U42@
@EMI@ PRZ84
4.7_1206_5%
5
1
Can be closed to choke PCZ41
0.15UH_NA__35A_20%
1U_0402_10V6K
1CORE1_SNUB 2
2
CORE1_LG 4 PCZ42
0.1U_0402_25V6
1 2 ISENSE1P_CORE_R1 2 1 2
1CORE2_SNUB 2
CORE2_LG 4 PRZ87 PRZ103 U42@ PCZ43
PRZ85 PRZ102 @ PRZ88 750_0603_1% 750_0603_1% 0.1U_0402_25V6
3
2
1
750_0603_1% 750_0603_1% 3.57K_0402_1% 1 2 ISENSE2P_CORE_R
1 2 1 2
1 2 U42@
@EMI@ PCZ44
PQZ4 U42@ U42@ @ PRZ90
3
2
1
680P_0603_50V7K
AON6314_N_DFN56-8-5 3.57K_0402_1%
1 2
@EMI@ PCZ45
2
680P_0603_50V7K
Can be closed to choke
2
ISENSE1N_CORE <48>
ISENSE2N_CORE <48>
ISENSE1P_CORE_R1 <48>
ISENSE2P_CORE_R1 <48>
C C
+19VB_CPU VCC_CORE
FSW=450kHz VCC_GT VCC_SA
Choke=0.15uH FSW=450kHz FSW=600kHz
DCR=0.9mohm +/- 5% Choke=0.15uH DCR=6.2 mohm +/- 5%
PRG2 DCR=0.9 mohm +/- 5%
PCG5
PCG6
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
2.2_0603_5%
PCG3
PCG4
GT_BST GT_BST_R U22
0.1U_0402_25V6
1 2
U22
1
LL=2.4 mohm U22 LL=10.3 mohm
1
PCG2 LL=3.1 mohm TDC=4A
EMI@
@EMI@
PUG1 TDC=21A
2
2
0.1U_0402_25V6 TDC=18A ICCMAX=4.5A
2
GT_UG ICCMAX=32A
4
BOOT UGATE
3
OCP=40A ICCMAX=31A OCP=9.5A
5 2 GT_LX PQG1 OCP=39A
<48> PWM_GT PWM PHASE
2
AON6962_DFN5X6D-8-7
+5VALW DRVEN_CPU 1 6 U42 U42
Rdc=0.9 mohm
D1
G1
VCC_GT
EN PGND
PLG1
+VCC_GT
LL=2.4 mohm U42 LL=10.3 mohm
1 PRG1 2 8 7
VCC LGATE 9 7 GT_LX 1 4 TDC=42A LL=3.1 mohm TDC=
GND D2/S1
5.1_0402_1%
ISENSE1P_GT 2 3 ISENSE1N_GT ICCMAX=64A TDC=12A ICCMAX=6A
RT9610CGQW_WDFN8_2X2 ICCMAX=31A OCP=9.5A
1
OCP=70A
@EMI@ PRG4
G2
S2
S2
S2
4.7_1206_5%
1
PCG1
0.15UH_NA__35A_20% OCP=39A
1U_0402_10V6K
2
PRG6 PRG9 PCG8

1K_0603_1% 1K_0603_1% 0.1U_0402_25V6
1 2 ISENSE1P_GT_R 1 2 1 2
1GT_SNUB
PRG7 PRG8
2.61K_0402_1% 10K_0402_1%
GT_LG 1 2 1 2
@EMI@ PCG9
AVGT1_R
680P_0603_50V7K
2
1 2
Close GT choke
PHG1
10K_0402_1%_B25/50 3370K
B ISENSE1N_GT <48> B
ISENSE1P_GT_R1 <48>
+19VB_CPU
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
PRA2
@EMI@ PCA6
PCA2
0.1U_0402_25V6
2.2_0603_5%
SA_BST SA_BST_R
1
1 2
PCA4
PCA5
1
EMI@
2
PCA3
PUA1
0.1U_0402_25V6
2
4 3 SA_UG
BOOT UGATE
5 2 SA_LX
<48> PWM_SA PWM PHASE
1
+5VALW DRVEN_CPU 1 6 PQA1

Rdc=6.2 mohm
G1
D1
D1
D1
EN PGND AONH36334_DFN3X3A8-10 +VCC_SA

1 2 VCC_SA 8 7 PLA1
VCC LGATE 9 9 10 1 4
PRA1 5.1_0402_1% GND D2/S1 D1
ISENSE1P_SA 2 3
RT9610CGQW_WDFN8_2X2
1
@EMI@ PRA4
G2
S2
S2
S2
4.7_1206_5%
1
PCA1
0.47UH_NA__12.2A_20%
1U_0402_10V6K
2
SA_LG
2
PCA7
0.1U_0402_25V6
ISENSE1P_SA_R
1 SA_SNUB
1 2 1 2 1 2
PRA6 PRA9 PRA7 PRA8

A 750_0603_1% 750_0603_1% 866_0402_1% 1K_0402_1% A
1 2 1 2
@EMI@ PCA8
AVCCSA_R
680P_0402_50V7K
Close SA choke
2
1 2
PHA1
1K_0402_5%_TSM0B102J3652RE ISENSE1N_SA <48>
ISENSE1P_SA_R1 <48>
3650K

CPU Power stage
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Re v
EH7LW M/B LA-H791P 0.2
5 4 3 2 1
1
0.2
Rev
57
of
50
Sheet
EH7LW M/B LA-H791P
E
E
Thursday, June 06, 2019
Power Train
Document Number
+VCC_SA
PC9079
1U_0201_4V6M
+VCC_SA
1 2
PC9078
Date:
Title
Size
PC9052 1U_0201_4V6M
22U_0603_6.3V6M
C
1 2
1 2 PC9077
PC9051 1U_0201_4V6M
22U_0603_6.3V6M
22uF_0603*7
22uF_0603*1
1 2
1 2 PC9076
1uF_0201*7
PC9050 1U_0201_4V6M
@
22U_0603_6.3V6M
1 2
1 2 PC9075
2019/12/27
PC9049 1U_0201_4V6M
unpop:
22U_0603_6.3V6M
1 2
1 2 PC9074
PC9022
22U_0603_6.3V6M
PC9048
22U_0603_6.3V6M
1U_0201_4V6M
1 2
pop:
SA
1 2 1 2 PC9073
PC9021 PC9047 1U_0201_4V6M
22U_0603_6.3V6M 22U_0603_6.3V6M
1 2
Deciphered Date
1 2 1 2
Compal Secret Data

D
D
0.47uF*4
22uF *13
22uF*31
220uF*1
unpop:
1uF*9
1uF*1
2018/12/27
+VCC_GT
+VCC_GT
PC9020 PC9046 PC9072 PC9095 @ PC9109 PC9129 PC9153

@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 0.47U_0201_4V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9019 PC9045 PC9071 PC9094 @ PC9108 PC9128 PC9152
Issued Date
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9018 PC9044 PC9070 PC9093 @ PC9107 PC9127 PC9151
@

1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9017 PC9043 PC9069 PC9092 @ PC9106 PC9126 PC9150
@

1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9016 PC9042 PC9063 PC9091 PC9125
@
C
C
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2
PC9015 PC9041 PC9062 PC9090 PC9124
@

1 2 1 2 1 2 1 2 1 2
PC9014 PC9040 PC9061 PC9089 PC9123
@

1 2 1 2 1 2 1 2 1 2
PC9013 PC9039 PC9060 @ PC9088 PC9122
@

1 2 1 2 1 2 1 2 1 2
PC9012 PC9038 PC9059 PC9087 PC9121
1 2 1 2 1 2 1 2 1 2
PC9011 PC9037 PC9058 PC9086 PC9120
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 0.47U_0201_4V6M
+
1
1 2 1 2 1 2 1 2 1 2
220U_D2 SX_2VY_R9M
PC9105
SGA20221D40
VCORE Output Capacitor:
+VCC_CORE
B
B
22uF_0603*29
1uF_0201*35
PC9001 PC9036 PC9068 PC9099 PC9104 PC9119 PC9139 PC9149 PC9158

@
+VCC_CORE
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M

2017/07/03
22_0603*7
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
220uF *2
PC9010 PC9035 PC9067 PC9098 PC9103 PC9118 PC9138 PC9148 PC9157

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9009 PC9034 PC9066 PC9080 PC9117 PC9137 PC9147
UNPOP
@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M

U22
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9008 PC9033 PC9065 PC9097 PC9116 PC9136 PC9146
@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M

+
1
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9007 PC9032 PC9064 PC9115 PC9135 PC9145
220U_D2 SX_2VY_R9M
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
U42@ PC9101
+
1
1 2 1 2 1 2 1 2 1 2 1 2
VCORE Output Capacitor:
PC9006 PC9031 PC9057 PC9114 PC9134 PC9144

220U_D2 SX_2VY_R9M
+VCC_CORE

U42@ PC9100
1 2 1 2 1 2 U42@ PC9084 1 2 1 2 1 2
PC9005 PC9030 PC9056 22U_0603_6.3V6M PC9113 PC9133 PC9143
1 2
1 2 1 2 1 2 U42@ PC9083 1 2 1 2 1 2
1 2
1 2 1 2 1 2 U42@ PC9082 1 2 1 2 1 2
@
A

1 2
1 2 1 2 1 2 U42@ PC9081 1 2 1 2 1 2
22uF_0603*35

@
1uF_0201*35

1 2
2017/07/03
+VCC_CORE
1 2 1 2 1 2 PC9156 1 2 1 2 1 2
22_0603*7
1U_0201_4V6M
220uF *2
1 2
PC9155 U42@ PC9096
1U_0201_4V6M 22U_0603_6.3V6M
UNPOP
1 2 1 2
PC9154 U42@ PC9085
U42
1U_0201_4V6M 22U_0603_6.3V6M
1 2 1 2
1
4
A B C D E
1 1
EN pin don't floating

If have pull down resistor at HW side, pls delete PR2
<21,40> 1.35VS_DGPU_PG
PRW2
1 2
+3VS 10K_0402_5%
PL1002 from SH00000PJ00

change to common part
SH00000YE00 2013/10/23
VGA@
@ PJW1
+19VB JUMP_43X79
PUW1
@VGA@ @VGA_EMI@ @VGA_EMI@
1 2 +19VB_1.35VSDGPUP 2 9 PCW4 VGA@ PRW4 PCW1
1 2 IN PG PRW3 0.1U_0402_25V7K 4.7_1206_5% 680P_0603_50V7K
10U_0603_25V6M
3 1 BST_1.35VSDGPUP
1 2 1 2 1 2 SNB_1.35VSDGPUP 1 2
PCW2
PCW3
0.1U_0402_25V6
2200P_0402_50V7K
IN BS
1
PCW5
4 6 TDC=4.7A
IN LX 0_0603_5%
2
Ipeak=7.2A +1.35VSDGPUP
2
5 19 VGA@ PLW1
VGA_EMI@
@VGA_EMI@
IN LX
VGA@
7 20 LX_1.35VSDGPUP 1 2
GND LX
8 14 FB_1.35VSDGPUP PCMB063T-1R0MS 12A
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
@VGA@ GND FB
1
2 18 17 LDO_3V_1.35VSDGPUP 2
PRW5 GND VCC
PCW6
PCW7
PCW8
VGA@ PCW10
@VGA@ PCW11
VGA@ PCW12
1
<21,40> 1.35VSDGPU_PWR_EN 1 2 11 10 PCW9 VGA@ @VGA@
2
EN NC
1
ILMT_1.35VSDGPUP 13 12 2.2U_0402_6.3V6M PRW6
2
0_0402_5% ILMT NC
VGA@
VGA@
@VGA@
0_0402_5%
1
15 16
+3VALW BYP NC
1
VGA@ PRW7 VGA@
PCW14
1U_0201_6.3V6M
2
100K_0402_1% PCW13 21
PAD
1
0.1U_0402_16V7K
2
GM4G need 1.35V 1 2

2
SY8286RAC_QFN20_3X3 FB_VDDQ_SENSE <24>

GT/GM2G need 1.5V
2
LDO_3V_1.35VSDGPUP
1
@VGA@ @VGA@ PRW8 0_0402_5%
PRW1
VGA@ 0_0402_5%
1
1
@VGA@ VGA@
PRW9 PRW10
1 2
0_0402_5% 25.5K_0402_1%
VGA@
PCW15
2
2
ILMT_1.35VSDGPUP
330P_0402_50V7K
2
1
@
PRW11
0_0402_5%
FB = 0.6V
2
(R1)
1
VGA@
VFB=0.6V
PRW13
20K_0402_1%
Vout=0.6V* (1+R1/R2)
The current limit is set to 8A, 12A or 16A when this pin Rdown=25.5K Vout=1.365V
2
is pull low, floating or pull high (R2) Rdown=97.6K Vout=1.525V
3 3
@
PJW2
+1.35VSDGPUP 1 2 +1.35VSDGPU
1 2
JUMP_43X118
4 4

Power Train
A B C D E
A B C D E
1 1
Module model information

SY8032_V2.mdd
@ PJE1
JUMP_43X79
1 2
+1.0VSDGPUP 1 2 +1.0VSDGPU
VIN_1.0VS
VGA@
PCE1
22U_0603_6.3V6M (Common Part)
VGA@
2 1 2 PUE1 SH00000YG00 4*4*2 2
SY8032ABC_SOT23-6
@ PJE2 PLE1 VGA@
JUMP_43X79 1UH_2.8A_30%_4X4X2_F
1 2 VIN_1.0VS 4 3 LX_1.0VS 1 2
+3VS 1 2 IN LX +1.0VSDGPUP Imax= 0.8A, Ipeak= 2.1A
VGA@
5 2 PRE3
PG GND
1
<21> 1VS_DGPU_PG 1 2
+3VS
68P_0402_50V8J
6 1 @VGA_EMI@
PRE4
6.98K_0402_1%
22U_0603_6.3V6M
22U_0603_6.3V6M
FB EN
1
PRE2
PCE2
1
10K_0402_5% 4.7_0603_5%
PCE3
PCE4
VGA@
2
@VGA@ PRE5
2
0_0402_5%
2
Rup
SNUB_1.0VS
1 2 EN_1.0VS
VGA@
VGA@
<22,40> PEX_VDD_EN
FB_1.0VS
1
@VGA@ PRE6 VGA@ 1

10K_0402_1% PRE1 @VGA@ VGA@
1
1 2 1M_0402_1% PCE5 PCE6
+1.8VSDGPU_AON Function Field :
1
0.1U_0402_16V7K @VGA_EMI@ PRE7
2
Rdown PWR.Plane.Regulator_1.05VDGPU - 43.7

2
680P_0402_50V7K 10K_0402_1%
Rest of support elements - 43.8
2
Note:
When design Vin=5V, please stuff snubber
to prevent Vin damage
N16=>1.05V
=>0.6V*(1+(7.68/10)=1.061 (1.01%)
3
=>0.6V*(1+(7.32/10)=1.039 (-1%) 3
N17=>1.0V
Vout=0.6V*(1+(6.98/10)=1.019V (1.02%)
4 4

Power Train
A B C D E
A B C D E
unmount PRV5 for 2 phase select
R1, R2, R3, R4, R5, C are +19VB_GPU_NVVDD
based on VGA type to set. R2 +19VB

DGPU_PSI <21>
@
PJ1501
N17S_VGA@
2 1
PR1208 +3VS @VGA@ 2 1
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
0.1U_0402_25V6
2200P_0402_50V7K
<21> DGPU_VID
20.5K_0402_1%
@VGA_EMI@ PC1220
VGA_EMI@ PC1221
PC1222
PC1223
PC1224
PC1225
PR1231 JUMP_43X118
1
2 1
R1 VGA_EN 2 1
1 R1 R2 NVVDD_EN <22> 1
105
105
N17S_VGA@
10K_0402_5%
.1U_0402_16V7K
2
2
105
105
N16S_VGA@ PR1209 N16S_VGA@ PR1208 PR1209
R3
@VGA@ PR1203
0_0402_5%
10K_0402_5%
0_0402_5%
1
20K_0402_1% 20K_0402_1% N17S_VGA@ 6.19K_0402_1%
@VGA@
@VGA@
PR1204
@VGA@ PR1205
PC1209
2 1 2 1
PR1211 VGA@ VGA@ VGA@ VGA@
R3 R4
2
4.32K_0402_1%
2
1
N16S_VGA@ PR1211 N16S_VGA@ PR1210
1
2K_0402_1% 18K_0402_1%
N17S_VGA@
R4 PR1210 UG1_VGA VGA@
R5 C
1
16.5K_0402_1% N17S_VGA@
1 2
N16S_VGA@ PR1224 N16S_VGA@ PC1210 PC1210 @VGA@ PQ1201
C PR1201
1
0_0402_5% 2700P_0402_50V7K AON6962_DFN5X6D-8-7
4700P_0402_50V7K Rdc=0.98 mohm
2
N17S_VGA@ BST1_VGA 1 2 BST1_VGA_R
D1
G1
PR1224 PL1202
R5 309_0402_1% 0.22UH_24A_+-20%_7X7X4_M +VGA_CORE
0_0603_5% 7 LX1_VGA 2 1
2
D2/S1
1
NVVDD_GND_SENSE_R VGA@ PC1201
VGA@
UGATE1
BOOT1
VID
PSI
EN
2
0.1U_0402_25V7K
G2
@VGA_EMI@
S2
S2
S2
4.7_1206_5%
2
REFADJ 6 20 LX1_VGA
PR1212
3
6
REFADJ PHASE1
1SNUB_VGA1 1
REFIN_VGA 7 19 @VGA@
REFIN LGATE1 PR1213
N16S_VGA@ LG1_VGA 0_0402_5%
1
VREF_VGA 8 PU1201 18 PVCC_VGA 1 2
VREF RT8812AGQW_WQFN20_3X3 PVCC +5VS
10.5K_0402_1%
1
VGA@
N16S_VGA@
1
VGA@ PR1215 TON_VGA 9 17 LG2_VGA PC1214 @VGA_EMI@
PR1225
PC1213 VGA@ 499K_0402_1% TON LGATE2 4.7U_0402_6.3V6M PC1215
2
1U_0201_6.3V6M +19VB_GPU_NVVDD 2 1
+19VB_GPU_NVVDD 680P_0603_50V7K
2
2
10 16 +19VB_GPU_NVVDD
RGND PHASE2
UGATE2
PGOOD
BOOT2
VSNS
N17S_VGA@
GND
PU1201
SS
2 VGA@ PR1216 RT8816BGQW_WQFN20_3X3 LX2_VGA 2
100_0402_1%
21
11
12
13
14
15
1 2
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
0.1U_0402_25V6
2200P_0402_50V7K
@VGA_EMI@ PC1226
VGA_EMI@ PC1227
PC1228
PC1229
PC1230
PC1231
1
1
VGA@ PC1216
@VGA@ @VGA@
PR1218
0.1U_0402_25V7K
PR1217
2
<23> VSSSENSE_VGA NVVDD_GND_SENSE_R
105
105
105
105
1 2
BST2_VGA 1 2 BST2_VGA_R UG2_VGA
VGA@
PC1218
@N16S_VGA@
.1U_0402_16V7K
0_0402_5% VGA@ VGA@ VGA@ VGA@
1
1
@VGA@ PC1217
0_0603_5% PQ1202
1
@VGA@ 1000P_0402_50V7K UG2_VGA AON6962_DFN5X6D-8-7
PR1220
2
D1
G1
<23> VCCSENSE_VGA 1 2 PL1203
NVVDD_SENSE_R
VGA_CORE_PG <22> LX2_VGA
0.22UH_24A_+-20%_7X7X4_M +VGA_CORE
0_0402_5% 7 2 1
VGA@ PR1221 D2/S1
@VGA_EMI@
4.7_1206_5%
2
100_0402_1% VGA@
1 2 VGA@ PR1232
Rdc=0.98 mohm
PR1222
G2
+VGA_CORE
S2
S2
S2
1 2 10K_0402_1%
2 1 +1.8VSDGPU_AON
6
N17S_VGA@
1SNUB_VGA2 1
PR1228
0_0402_5% @VGA@ PR1223
10K_0402_1%
1 2 2 1 +3VS
N16S_VGA@
PR1226 LG2_VGA @VGA_EMI@
1
0_0402_5% N17S_VGA@ PC1219

1
PR1230 680P_0603_50V7K
2
N17S_VGA@ 110K_0402_1%
PC1232
2
0.033U_0402_16V7K
2
3 3
4 4

Power Train
A B C D E
4
3
2
1
A
A
2 1 2 1
2 1
VGA@ PC1315 VGA@ PC1301
@VGA@ PC1319 1U_0402_10V7 4.7U_0402_6.3V6M
0.1U_0402_25V6 2 1 2 1
2 1 VGA@ PC1316 VGA@ PC1326

1U_0402_10V7 4.7U_0402_6.3V6M
@VGA@ PC1320 2 1 2 1
+VGA_CORE
0.1U_0402_25V6
VGA@ PC1317 VGA@ PC1332
B
B
2 1 1U_0402_10V7 4.7U_0402_6.3V6M
+VGA_CORE Under
2 1 2 1
@VGA@ PC1321
0.1U_0402_25V6 VGA@ PC1318 VGA@ PC1324
1U_0402_10V7 4.7U_0402_6.3V6M
2 1 2 1 2 1
@VGA@ PC1322 N17S_VGA@ PC1338 VGA@ PC1305

0.1U_0402_25V6 1U_0402_10V7 4.7U_0402_6.3V6M
2 1
2 1
VGA@ PC1306
@ESD_VGA@ PC1323 4.7U_0402_6.3V6M
GPU Core
0.1U_0402_25V6 2 1
2 1 VGA@ PC1307
4.7U_0402_6.3V6M
@ESD_VGA@ PC1304 2 1
0.1U_0402_25V6
VGA@ PC1308
2 1
GB4-128 package
4.7U_0402_6.3V6M
2 1
@ESD_VGA@ PC1325
0.1U_0402_25V6 VGA@ PC1309
2 1 4.7U_0402_6.3V6M
2 1
@ESD_VGA@ PC1302
0.1U_0402_25V6 VGA@ PC1310
4.7U_0402_6.3V6M
2 1
N17S_VGA@ PC1330
4.7U_0402_6.3V6M
2 1
N17S_VGA@ PC1337
4.7U_0402_6.3V6M
C
C
2 1
22U_0603_6.3V6M
PC1339 N17S_VGA@
2 1 2 1
N17S_VGA@
10U_0402_6.3V6M 22U_0603_6.3V6M
PC1340 PC1335 VGA@
2 1 2 1
N17S_VGA@
10U_0402_6.3V6M 22U_0603_6.3V6M
+VGA_CORE
PC1341 PC1328 VGA@
Issued Date
2 1 2 1
10U_0402_6.3V6M 22U_0603_6.3V6M
N17S_VGA@
PC1342 PC1327 VGA@
2 1
2 1 PC1311
N17S_VGA@ 220U_D2 SX_2VY_R9M
10U_0402_6.3V6M
PC1343
VGA@ PC1329 VGA@
2
1
+
2 1 4.7U_0402_6.3V6M
2 1
N17S_VGA@
10U_0402_6.3V6M
VGA@ PC1336
PC1344
2 1 4.7U_0402_6.3V6M VGA@
2
1
+
2 1
2018/12/27
N17S_VGA@
10U_0402_6.3V6M
+VGA_CORE
PC1345
N17S_VGA@ PC1331 PC1312
2 1 4.7U_0402_6.3V6M 220U_D2 SX_2VY_R9M
2 1
Near GPU Core
N17S_VGA@ VGA@
10U_0402_6.3V6M
2
1
+
N17S_VGA@ PC1303
PC1346
2 1 4.7U_0402_6.3V6M
2 1 PC1313
10U_0402_6.3V6M
N17S_VGA@ 220U_D2 SX_2VY_R9M
N17S_VGA@ PC1333
PC1347
2 1 4.7U_0402_6.3V6M VGA@
2
1
+
2 1
N17S_VGA@
10U_0402_6.3V6M
PC1348
N17S_VGA@ PC1334 PC1314
D
D
2 1 4.7U_0402_6.3V6M 220U_D2 SX_2VY_R9M

Compal Secret Data N17S_VGA@
10U_0402_6.3V6M
Deciphered Date
PC1349
2 1
N17S_VGA@
10U_0402_6.3V6M
PC1350
2019/12/27
C
Size
Title
Date:
Document Number
Power Train
Thursday, June 06, 2019

E
E
EH7LW M/B LA-H791P

Sheet
54
of
57
Rev
0.2
4
3
2
1
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 1 for

PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
01 Reserve gpu prochot function Reserve gpu prochot function P.43 Del PQB8 for function reserve. 19.0103 EVT
D 02 D
change PL502 to common part change PL502 to common part(SH000016700)
change PL502 to common part P.44 19.0212 DVT
03
change PR1230 to 110K change PR1230 to 110K for ocp setting P.53 change PR1230 to 110K(SD034110380) 19.0212 DVT
change PC302,PC502,PCB11 to SE00000W210
04 change CAP size to 0402 change CAP size to 0402 for cost down change PCB1 to SE074102K80
P.43,44 19.0212 DVT
change PR101,PR217,PR210,PRB15,PRB17,PRB23,PRB26,PRB16,PR304,PR505,PR502,PRM8,PRM11,
change 0 ohm to R-short change 0 ohm to R-short for cost down PRM12,PRF3,PRF8,PRF1,PR1801,PRZ15,PRZ94,PRZ47,PRZ95,PRZ50,PRZ93,PRZ25,PRW5,PRW9,
PRW6,PRW1,PRW3,PRE5,PR1231,PR1204,PR1218,PR1220,PR1201,PR1217,PR1213 to R-short 19.0212 DVT
05 (38PCS)
change PRM8 to SD034487280
06 DDR sequence change PRM8 to 48.7K and PCM18 to 0.1u for sequence P.38 change PCM18 to SE102104K00 19.0215 DVT
change PCZ11 to 330PuF(SE074331K80)
07 CPU transient change R and C value for CPU transient test P.48 change PRZ45 to 63.4k ohm(SD03463K280)(U42) 19.0218 DVT
change PRZ49 to 5.49k ohm(SD034549180)
08 change PRM8 to SD028000080
DDR sequence change PRM8 to 0 ohm and del PCM18 for sequence P.38 del PCM18 19.0328 PVT
C C
P.48 change PHZ2,PHZ3 to SL200002I00,

09 VR thermal alert adjust change protect from 100c to 110c change PRZ51,PRZ66 to SD000000680, 19.0507 pre MP
change PRZ52,PRZ69 to SD034332280,
change PRZ67 to SD00000WS80,change PRZ63 to SD034130280,
change PRZ70 to SD034137180,change PRZ68 to SD034392180,
change PRZ64 to SD034976180,change PRZ71 to SD00000WS80,change PRZ74 to SD034165280
10
11
B B
12
13
14
15
16
17
18
A A
19
2018/12/27
Compal Secret Data
2019/12/27 Title
PIR
5 4 3 2 1
5 4 3 2 1
HW Schematic chang list (P.I.R)

Date Rev. Modify Item Date Rev. Modify Item
Add cnvi cap(CM4) as intel request
1/25 Swap JFP1 pin define
0.2 update JIO1 pin define
D D
update H12 hole,downsize C2034/C2750

update JIO1 pin define
1/29 0.2 change 0-ohm to R-short
remove SWK1
2/12 0.2 change RA3/RA4 to 0805 size
update UL2 pin28/pin29 pin define

3/13 1A Add DA3/DA4 for audio ESD protection
update JIO1 footprint
5/9 update RC262 75k for CML

1B
C C
B B
A A

HW-P.I.R page1
5 4 3 2 1
5 4 3 2 1
HW Schematic chang list (P.I.R)

Item Page Date Rev. Reason for change Modify Item
D D
C C
B B
A A

HW-P.I.R page2
5 4 3 2 1

Compal LA-H791P EH7LW - EH5LW - FH5TW - EH7LC - EH5LC Rev 2.0 Acer EX215-51K

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Compal LA-H791P EH7LW - EH5LW - FH5TW - EH7LC - EH5LC Rev 2.0 Acer EX215-51K

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A B C D E

Security Classification Compal Secret Data Compal Electronics, Inc.

HDMI Conn. eDP Interleaved Memory

DDR4-ON BOARD 4G 8Gbx16

Intel Whiskey lake U USB 3.0 USB 2.0 CMOS

RJ45 conn. LPC/eSPI BUS

page 33 CLK=24MHz 128Mb page 9

Power On/Off CKT.

Board ID Table for AD channel

+1.8VSDGPU_MAIN +1.8VS power rail for N17S(MAIN) ON*2 OFF OFF

+VGA_CORE Core power for discrete GPU ON*2 OFF OFF

43 level BOM table

431AHVBOL04 SMT MB AH791 EH7LW I58265U42 230 HDMI 8265U@/PCB@/WHL@/MEM@/SDP@/X76DHYN@/VGA@/G0@/X76VHYN@/NC10@/CNVI@/NCHG@/RD@/ODD@/3S@/LPC@/CMC@/255@/DVT@/X4E@/17@/

431AHVBOL05 SMT MB AH791 EH7LW I38145U22 230V8 HDMI 8145U@/PCB@/WHL@/MEM@/SDP@/X76DHYN@/VGA@/G0@/X76VSAM@/NC10@/CNVI@/NCHG@/RD@/ODD@/3S@/LPC@/CMC@/255@/DVT@/X4E@/17@/

431AHVBOL06 SMT MB AH791 EH7LW I58265U42 230V8 HDMI 8265U@/PCB@/WHL@/MEM@/SDP@/X76DHYN@/VGA@/G0@/X76VSAM@/NC10@/CNVI@/NCHG@/RD@/ODD@/3S@/LPC@/CMC@/255@/DVT@/X4E@/17@/

431AHVBOL51 SMT MB AH791 EH5LW I38145U22 230 HDMI 8145U@/PCB@/WHL@/MEM@/SDP@/X76DHYN@/VGA@/G0@/X76VHYN@/NC10@/CNVI@/NCHG@/NRD@/3S@/LPC@/CMC@/255@/DVT@/X4E@/15@/15DIS@/

431AHVBOL53 SMT MB AH791 EH5LW I38145U22 230V8 HDMI 8145U@/PCB@/WHL@/MEM@/SDP@/X76DHYN@/VGA@/G0@/X76VSAM@/NC10@/CNVI@/NCHG@/NRD@/3S@/LPC@/CMC@/255@/DVT@/X4E@/15@/15DIS@/

431AHVBOL54 SMT MB AH791 EH5LW I58265U42 230V8 HDMI 8265U@/PCB@/WHL@/MEM@/SDP@/X76DHYN@/VGA@/G0@/X76VSAM@/NC10@/CNVI@/NCHG@/NRD@/3S@/LPC@/CMC@/255@/DVT@/X4E@/15@/15DIS@/

Security Classification Compal Secret Data Compal Electronics, Inc.

+1.2VP (PJM3) +1.2V_VDDQ (RC464) +1.2V_VCCPLL_OC

JUMP SUSP# AOZ1331DI JUMP JUMP

0 ohm PEX_VDD_EN SY8032ABC JUMP

(PUM2) +2.5VP (RC154) +3VALW_SPI (RM9) +3VS_SSD_NGFF

SUSP# AOZ1331DI R-Short

EN_1VALW SY8288RAC JUMP R-Short

SUSP# AOZ1334DI-02 0 ohm

EN_12VSP HCB2012KF +INVPWR_B+

Security Classification Compal Secret Data Compal Electronics, Inc.

CN15 SOC_SML1CLK I2CS_SCL

77 EC_SMB_CK1 100 ohm EC_SMB_CK1-1 4

KBC SCL2 79 SOC_SML1CLK

I2C Address Table

I2C_0 (+3VS) Reserved

Security Classification Compal Secret Data Compal Electronics, Inc.

S IC CL8068404064409 SRFFW V0 1.8G ABO!

EC_SCI# SOC internal PU

#545659 PCH EDS1.51 P.131

1 2 H_PROCHOT#_R Y4 PECI CPU MISC JTAG

2 1 H_PROCHOT#_R RC7 2 @ 1 49.9_0402_1% EDRAM_OPIO_RCOMP L5 ZZZ

For Intel debug, place to CPU side. ZZZ

SMT EMC DIS AH791 EH5LC

+3VS #595182 P38 SM_RCOMP0 RC38 1 2 121_0402_1%

74AUP1G07SE-7_SOT353_5P DDR_VTT_CNTL to DDR

SOC_SMBCLK_1 RC222 1 2 2.2K_0402_5%

SOC_SML0CLK RC49 1 2 2.2K_0402_5%

SOC_SML1CLK RC267 1 2 2.2K_0402_5%

CL_RST# GPP_A9/CLKOUT_LPC0/ESPI_CLK BV30 +1.8VS_3VS_PGPPA

SML0ALERT# / GPP_C5 (Internal Pull Down):

PVT remove JC1 socket footprint

#575412 WHL DG p292_

Add PU resistor 12/20

1 = Enable TOP Swap Mode.

#575412 WHL DG p268

#575412 P31 SOC_XTAL24_IN RC235 1 2 33_0402_1% SOC_XTAL24_IN_R

1 2 563377 Intel MOW 33

1 2 EC_VCCST_PG SLP_SUS# 100K_0402_5% 1 2 RC301 Cannonlake U use 38.4M 30 ohm ESR

#575412 WHL DG p274 SOC_RTCX2

#575412 WHL-U schchecklist R0.8 PM_BATLOW# RC103 1 2 10K_0402_5%

PCH PLTRST Buffer SOC_VRALERT# RC115

ESD@ 1000P_0402_50V7K +3VS

ESD@ MC74VHC1G08DFT2G_SC70-5 100K_0402_5%

#543016 PDG2.0 P.599