Compal EH78F LA G161p r1c 0116 r0.1

A B C D E
1 1
Compal Confidential
EH78F MB Schematic Document
2 2
3
LA-G161P 3
Rev:1C
2019.01.16
4 4
Security Classification
2017/11/23
Compal Secret Data
2018/09/01 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom EH78F M/B LA-G161PR01 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, January 16, 2019 Sheet 1 of 102
A B C D E
A B C D E
eDP
eDP Panel 4 lane
eDP redriver RTC circuit Fan Control Thermal sensor Hall sensor
page 21 page 54 page 55 page 54
Conn. page 38 TUSB546 VBIOS ROM
page 41
1.8V 8Mbit
page 31
eDPx4
HDMI
1
HDMI 2.0 4 lane 260pin DDR4-SO-DIMM 1
PEG X16 (0~15) page 23
Conn. page <N18E-G3 8GT/s Memory BUS
40
witih GDDR6 *8> Dual Channel
CoffeeLake H PROCESSOR
page 25~37 1.2V DDR4 2400
DP BGA1440
Display Port 4 lane 260pin DDR4-SO-DIMM
(42X28) (CFL-H_6+2) page 24
Conn. x1 page 39
USB3.1 gen2 DP 4 lane DP 4 lane
Processor page 06~13
X4 DMI Offline USB Charger
USB3.1 Retimer Active MUX DPRedriver

ANX7440 TUSB546 USB3.0
ANX7490page 46 page 47 page 42 ON USB3.0_Audio/B ON XBOX/B
Conn.(M/B)
page 71
USB3.0
2 2
USB3.1
Passive MUX Silego USB charger USB3.0 USB2.0
USB2.0
ANX7428 Cannonlake PCH - H SLGC55544 Conn.(USB/B) Conn.(XBOX/B)
page 48 page 71 page 73 page 73
NV TYPE-C
DP/USB3.1 DP 4 lane
FCBGA(23X23) USB3.0 USB2.0
Conn. USB Bus
page 49 PD CCG4
M.2
page 49
837pin FCBGA FHD CAM Key Board
Thunderbolt Conn. Conn. Blue Tooth
TBT TYPE-C TBT/DP/USB2.0/USB3.1 AR4C PCIe x4 page 38 page 63 page 52
USB2.0 USB2.0 USB2.0
Conn. page 43, 44
page 45 PD TPS65982
page 45
HD Audio HDA Codec Ext Amp. Speaker
3.3V 24MHz ALC289 ALC1006 Conn.
page 56 page 57 page 56
3 3
Flexible I/O
PCIe x2 PCIe x1 6.0 Gb/s
PCIe x4 PCIe x4 Head Phone
page 14~21
LAN(GbE) SATA3.0 SATA3.0 Jack
M.2 WLAN Conn.
Killer Ethernet SPI
Dual Band
page 52 E3000 page 51 M.2 SSD M.2 SSD
802.11 ac/agn Conn. Conn.
page 68 page 68
SPI ROM MIC Jack
16M ON USB3.0_Audio/B
RJ45 page 16
Conn.
page 73
Conn.
page 51
LED driver
TLC59116 SMBUS ENE
SUB/B KB9022
page 62 page 58
4 4
G+Gyro-sensor/B Hall/B
page 38 page 66
Touch Pad Security Classification Compal Secret Data Compal Electronics, Inc.
page 63 2017/11/23 2018/09/01 Title
USB 3.0_Audio/B Macro Key Issued Date Deciphered Date Block Diagrams
page 73 page 77 I2C/PS2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH78F M/B LA-G161PR01
Date: Wednesday, January 16, 2019 Sheet 2 of 102
A B C D E
A B C D E
Board ID Table for AD channel Power State

Vcc 3.3V +/- 5% BOM Structure Table SIGNAL
Ra 100K +/- 5% STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Board ID Rb V BID min V BID typ V BID max EC AD BOM Option Table S0 (Full ON) HIGH HIGH HIGH ON ON ON ON
0 0 0.000 V 0.300 V 0x00 - 0x13 Item BOM Structure
1 12K +/- 1% 0.347 V 0.345 V 0.360 V 0x14 - 0x1E S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
Unpop @
2 15K +/- 1% 0.423 V 0.430 V 0.438 V 0x1F - 0x25 S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
Connector CONN@
1 3 20K +/- 1% 0.541 V 0.550 V 0.559 V 0x26 - 0x30 1
HDMI royalty 45@ S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
4 27K +/- 1% 0.691 V 0.702 V 0.713 V 0x31 - 0x3A
i5 CPU I5@
5 33K +/- 1% 0.807 V 0.819 V 0.831 V 0x3B - 0x45
i7 CPU I7@
6 43K +/- 1% 0.978 V 0.992 V 1.006 V 0x46 - 0x54
PCH PCH@
7 56K +/- 1% 1.169 V 1.185 V 1.200 V 0x55 - 0x64
CMC CMC@ Voltage Rails
8 75K +/- 1% 1.398 V 1.414 V 1.430 V 0x65 - 0x76 Power Plane Description
dGPU circuit VGA@ S0 S3 S4 S5
9 100K +/- 1% 1.634 V 1.650 V 1.667 V 0x77 - 0x87 +RTCVCC RTC Battery Power ON ON ON
OVRM-Onsemi onsemi@ ON
10 130K +/- 1% 1.849 V 1.865 V 1.881 V 0x88 - 0x96 +19V_VIN Adapter power supply N/A N/A N/A
OVRM-Onsemi upi@ N/A
11 160K +/- 1% 2.015 V 2.031 V 2.046 V 0x97 - 0xA4 +12.6V_BATT Battery power supply N/A N/A N/A
FGC6 FGC6@ N/A
12 200K +/- 1% 2.185 V 2.200 V 2.215 V 0xA5 - 0xAF +19VB AC or battery power rail for power circuit. N/A N/A N/A
NON FGC6 NFGC6@ N/A
13 240K +/- 1% 2.316 V 2.329 V 2.343 V 0xB0 - 0xB7 +3VLP +19VB to +3VLP power rail for suspend power
Intel CNVi (reserve) CNVI@ ON ON ON ON
14 270K +/- 1% 2.395 V 2.408 V 2.421 V 0xB8 - 0xBF +5VALW +5V Always power rail
USB charger CHG@ ON ON ON ON
15 330K +/- 1% 2.521 V 2.533 V 2.544 V 0xC0 - 0xC9 +3VALW System +3VALW always on power rail ON*
GSYNC GSYNC@ ON ON ON
16 430K +/- 1% 2.667 V 2.677 V 2.687 V 0xCA - 0xD4 +3VALW_DSW +3VALW power for PCH DSW rails
NON GSYNC NGSYNC@ ON ON ON ON
17 560K +/- 1% 2.791 V 2.800 V 2.808 V 0xD5 - 0xDD +3VALW_PCH_PRIM +3VALW power for PCH power rails
Thunderbolt TBT@ ON ON ON ON*
18 750K +/- 1% 2.905 V 2.912 V 2.919 V 0xDE - 0xF0 +3VALW_SPI +3VALW_PRIM supply for the SPI IO
NC Thermal sensor TMS@ ON ON ON ON
19 3.000 V 3.000 V 0xF1 - 0xFF +1.05VALW +1.05V Always power rail
for SW debug board UART@ ON ON ON ON
2 EMI/ESD requirement EMC@ +1.2V_VDDQ DDR4 +1.2V power rail ON ON OFF OFF 2
EMI/ESD require reserve XEMC@ +1.05V_VCCST Sustain voltage for processor in Standby modes
I2C Address Table DIS sequency control NGPK@ +5VS System +5V power rail
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
Address(8bit) M/B GSENSOR MBGSEN@ +3VS System +3V power rail ON OFF OFF OFF
BUS Device Address(7 bit)
Write Read GSENSOR ISH path ISHGSEN@ +1.05VS_VCCSTG +1.05VALW_PRIM Gated version of VCCST ON OFF OFF OFF
I2C_0 (+3VS) LIS2DH12TR (G-sensor) GSENSOR EC path ECGSEN@ +0.6VS_VTT DDR +0.6VS power rail for DDR terminator . ON OFF
OFF OFF
I2C_1 (+3VS) TM-03461-001 (Touch Pad) +VCC_CORE Core voltage for CPU ON OFF OFF OFF
+VCC_GT Sliced graphics power rail ON OFF OFF OFF
DIMM1 +VCCIO CPU IO +0.95VS power rail ON OFF OFF OFF
PCH_SMBCLK +VCC_SA System Agent power rail
(+3VALW) DIMM2 ON OFF OFF OFF
+1.8VSDGPU_AON +1.8VS power rail for GPU(AON rails) ON OFF OFF OFF
N18E-G3 (VGA) 0x9E +1.8VSDGPU_MAIN +1.8VS power rail for GPU GC6 ON OFF OFF OFF
TMS(NCT7718W )hot 0x98 +VGA_CORE Core voltage for VGA (merge core & core_s) ON OFF OFF OFF
PCH_SML1CLK +1.35VSDGPU +1.35VS power rail for GPU
EC_SMB_CK2 TMS(W83L771AWG-2 )cool 0x9A ON OFF OFF OFF
(+3VALW) LIS2DH12TR(M/B) +1.0VSDGPU +1.0VS power rail for GPU ON OFF OFF OFF
LIS2DH12TR(SUB/B) +1.8VALW System +1.8VALW always on power rail ON ON ON ON*
EC_SMB_CK1 ISL88739 (Charger IC) 0x11
(+3VLP) BATTERY PACK 0x16
3 3
EC_SMB_CK3 PD(TPS65982) 0x70

(+3VALW) LED driver 0xC0 Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
EC_SMB_CK4
(+3VALW)
BOARD ID Table
43 level BOM table Board ID PCB Revision Board ID PCB Revision

0 0.1 10
43 Level Description BOM Structure 1 1.0 11 1.0 w/ EC gensor
43 EH78F 1180 I7@/QNDQ@/CMC@/VGA@/NGPK@/CNVI@/CHG@/XBOX@/TBT@/EMC@ 2 1A 12
3 1B 13
4 1C 14
5 15
6 16
7 17
8 18
4
9 19 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/11/23 Deciphered Date 2018/09/01 Title
Notes List
Custom 0.1
A B C D E
5 4 3 2 1
EN:DGPU_PWR_EN
+1.8VSDGPU_AON
DC_IN GPU
+1.8VSDGPU_MAIN
PL101 UG27
PJP101
+19V_VIN
AC CONN.
+12.6V_BATT
+12.6V_BATT+ +1.8VDDA
BATTERY UQ2 +1.8VS RA3 CODEC
PL201,PL202
PJP201
+1.8VALWP
D IMVP8 +1.8VALW
D
PU7105 PJ7107 RH100 +1.8VALW _PRIM PCH

PU1802 +VCC_CORE
+19VB PU8103 PL8101,PL8104,PL8105,PL8106 CPU +2.5VP DIMM1
PU301 PU7102 PJ7103 +2.5V
PU8104 DDR4
DIMM2
PU8105 +1.0VSDGPUP +1.0VSDGPU
EN:VR_ON PU1401 PJ1401
GPU
PU8106 PL8107 +VCC_GT CPU

CHARGER +19VB UQ1 JPQ1 +3VS
EN:DRON UO1 SATA Re-driver
R19 +3VALW_TPM U5
TPM RZ1 G-SENSOR
+3VS_WLAN
UM1 JNGFF1 WLAN CARD (IOAC)
RM1 +3VS_SSD_NGFF JSSD1
PU8301 +VCC_SA +3V_LAN SSD
+19VB
PL8301 CPU UL2 UL2 LAN
EN:DRON R20 +3VS_TPM U5 TPM
UK1 +3V_PTP JTP1
TP +LCDVDD
UX1 JEDP1
+3VALWP +3VALW_PCH_PRIM +3VALW_SPI
PANEL
RH97 RH98 UH2
EN:3V_EN PJ401 +3VALW SPI +3VS_DVDDIO
RA2 +3VS_DVDDIO CODEC
+19VB
PU401 RS1 +3.3V_CC
EC,LID +3VLP +3VS_DVDD
RA4
C
+3VALW_HDA
+3VS_DVDD CODEC C
RH101 PCH
+1.2V_VDDQ_CPU
+1.2VP
+1.2V_VDDQ
JPC1,C2 CPU +3VALW_DSW
EN:SYSON PJ501 +1.2V_VCCPLL_OC
RH99 PCH
RC24 CPU +FP_VCC
+19VB UK2 FP
PU501
EN:SM_PG_CTRL
+0.6VSP
PJ502 +0.6VS_VTT +1.05VALW_PRIM
RH92 PCH
+1.05VALWP +1.05VALW_PCH
RH94 PCH
PU601 +1.05VALW
+19VB
PJ601 RH102
EN:+3VALW RH103
PCH
RH105
RH93 +1.05VALW _VCCMPHY PCH

+0.95VS_VCCIOP
PU7201 PJ7201 +VCCIO +1.05V_VCCST

+19VB CPU UQ2
EN:SUSP# CPU
UC4 RQ61 +1.05VS_VCCSTG
B B
US2 +5V_CC
JIO3
USB2.0 Conn/ IOB.
US2
+5VALWP +USB3_VCCC
US11 JTYPEC1
PU402 PJ402 +5VALW Type C Conn.
+19VB
US1 +USB_VCCA USB3.0 Conn.
UQ1
JPQ2 +5VS +VCC_FAN1
RF4 FAN1
+19VB_NVVDD RF7 +VCC_FAN2 FAN2

+19VB GPU
PL1502 PU1501 PL1501 +VGA_CORE +VDDA
PL1503 PU1502 PL1502 JPA1 UA1 CODEC
U4 +5VS_BL JBL1 KB BackLight
RO4 +5VS_HDD JHDD1

EN:1.35VS_DGPU_PG
HDD
+19VB +1.35VSDGPUP GPU +HDMI_5V_OUT
+1.35VSDGPU UY2 JHDMI1
A
PL1301 PJ1302 HDMI A
PJ1303 +TS_PWR
RX7 JEDP1
TS
+19VB →+19V_CPU
LX1 +INVPWR_B+
PANEL
2017/11/23
Compal Secret Data
2018/09/01 Title
Power Map
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
5 4 3 2 1
A B C D E
EH78F_EVT Power Sequence

1 BIOS : 0.05
EC : 0.05
Power On S3 S3 Resume Power Off 1
AC mode
Plug in
+3VLP
+3VLP
EC_ON
EC_ON → 353.6ms
+5VALW
+5VALW → 356.4ms
ON/OFFBTN#
ON/OFFBTN#
+3VALW → 94.89ms → 8.880s +3VALW
+1.8VALW → 96.19ms → 8.879s +1.8VALW
+1.05ALW → 97.17ms → 8.879S +1.05ALW
EC_RSMRST# → 42.10ms → 8.834 EC_RSMRST#

24ms
PBTN_OUT# → ←← → → 8.834 PBTN_OUT#
164.6ms
2 2
→ 19.08ms → 10.41ms PM_SLP_S4#

PM_SLP_S4#
→ 19.11ms → 10.27ms → 10.27ms PM_SLP_S3#
PM_SLP_S3#
→ 4.8ms → 10.42ms SYSON

SYSON
→ 299.4us → 97.92us +1.05V_VCCST
+1.05V_VCCST
→ 717.2us → 376.7us +1.2V_VDDQ
+1.2V_VDDQ
→ 1.006ms → 1.244ms +2.5V
+2.5V
→ 12.67ms → 13.89us → 48.05ms → 10.28ms SUSP
SUSP#
→ 8.417us → 55.56us → 8.7us → 73.86us +1.05VS_VCCSTG
+1.05VS_VCCSTG
→ 255.0us → 747.1us → 239.4us → 790.4us +VCCIO
+VCCIO
→ 955us → 401.1us → 939.9us → 598.9us +5VS
+5VS
→ 651.9us → 2.349ms → 704.1us → 2.47ms +3VS
+3VS
→ 460.4us → 1.169ms → 434.1us → 1.132ms +1.8VS
+1.8VS
→ 25.6ms → 8.782us → 32.16ms → 8.739us EC_VCCST_PG
3 EC_VCCST_PG 3
→ 25.38ms → 9.195us → 30.02ms → 9.244us SM_PG_CTRL

SM_PG_CTRL
→ 2.060us → 2.048ms → 2.78us → 596.1us +0.6VS_VTT
+0.6VS_VTT
→ 25.38ms → 19.21us → 30.02ms → 10.29ms VR_ON
VR_ON
→ 2.158ms → 60.60us → 2.163ms → 87.5us +VCC_SA
+VCC_SA
→ 12.36ms → 74.83us → 12.8ms → 74.11us PCH_PWROK
PCH_PWROK
→ 172.7ms → 89.21us → 176.2ms → 88.46us SYS_PWROK
SYS_PWROK
→ 1.098ms → 1.207ms PLT_RST#
PLT_RST#
→ 176.5ms → 812.8us → 179.9ms → 2.174ms +VCC_CORE
+VCC_CORE
→
4 4
2017/11/23
Compal Secret Data
2018/09/01 Title
Power Sequence
Custom 0.1
A B C D E
A B C D E
1 1
CFL-H
UC1D
K36 D29
K37 DDI1_TXP_0 EDP_TXP_0 E29
2 J35 DDI1_TXN_0 EDP_TXN_0 F28 2
J34 DDI1_TXP_1 EDP_TXP_1 E28
H37 DDI1_TXN_1 EDP_TXN_1 A29
DDI1_TXP_2 EDP_TXP_2
PCB DAZ H36
J37 DDI1_TXN_2 EDP_TXN_2
B29
C28
J38 DDI1_TXP_3 EDP_TXP_3 B28
DDI1_TXN_3 EDP_TXN_3
D27 C26
ZZZ DDI1_AUXP EDP_AUXP
E27 B26
DDI1_AUXN EDP_AUXN
H34
H33 DDI2_TXP_0
F37 DDI2_TXN_0 A33 +VCCIO
G38 DDI2_TXP_1 EDP_DISP_UTIL
PCB@ DAZ2HB00100 F34 DDI2_TXN_1
F35 DDI2_TXP_2 D37 DP_RCOMP RC1 1 2 24.9_0402_1%
PCB EH78F LA-G161P LS-G161P/G162P/G163P/G164P/G165P/G168P DDI2_TXN_2 DISP_RCOMP
E37
E36 DDI2_TXP_3 Trace Width/Space: 15 mil/ 20 mil
DDI2_TXN_3 Max Trace Length: 600 mil
F26
DDI2_AUXP
Coffee Lake-H CPU SKU E26
DDI2_AUXN
C34
UC1 D34 DDI3_TXP_0
B36 DDI3_TXN_0
B34 DDI3_TXP_1
F33 DDI3_TXN_1
E33 DDI3_TXP_2
3 C33 DDI3_TXN_2 3
B33 DDI3_TXP_3
CFL-H_BGA1440 DDI3_TXN_3 CPU_DISPA_BCLK_R
G27 CPU_DISPA_BCLK_R <18>
S IC CL8068403359524 SR3YY U0 2.2G ABO! PROC_AUDIO_CLK CPU_DISPA_SDO_R
A27 G25 CPU_DISPA_SDO_R <18>
SA0000BPZ40 DDI3_AUXP PROC_AUDIO_SDI CPU_DISPA_SDI CPU_DISPA_SDI_R
B27 G29 RC2 2 1 20_0402_5%
i7@ DDI3_AUXN 4 ofPROC_AUDIO_SDO
13 CPU_DISPA_SDI_R <18>
follow CRB
CFL-H_BGA1440
@
Cannon Lake PCH SKU
UH1
CFL-H_BGA1440
S IC FH82HM370 SR40B B0 BGA 874P PCH-H ABO!
SA0000BVP10
PCH@
NV N18E-G3 Need check USE QS PN

4
UG9 4
VGA@
S IC TU104-750-A1 FCBGA 2228 GPU ABO !

SA0000CD510
2017/11/23
Compal Secret Data
2018/09/01 Title
CFL-H(1/8)DDI/eDP
A B C D E
A B C D E
CHANNEL-A
Interleaved Memory
UC1A
CFL-H
DDR CHANNEL A
1 <23> DDR_A_D[0..63] 1
DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4
DDR_A_D0 BR6 AG1 DDR_A_CLK0
DDR0_DQ_0/DDR0_DQ_0 DDR0_CKP_0/DDR0_CKP_0 DDR_A_CLK0 <23>
DDR_A_D1 BT6 AG2 DDR_A_CLK#0
DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 DDR_A_CLK#0 <23>
DDR_A_D2 BP3 AK2 DDR_A_CLK1
DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_1/DDR0_CKP_1 DDR_A_CLK1 <23>
DDR_A_D3 BR3 AK1 DDR_A_CLK#1
DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 DDR_A_CLK#1 <23>
DDR_A_D4 BN5 AL3
DDR_A_D5 BP6 DDR0_DQ_4/DDR0_DQ_4 NC/DDR0_CKP_2 AK3
DDR_A_D6 BP2 DDR0_DQ_5/DDR0_DQ_5 NC/DDR0_CKN_2 AL2
DDR_A_D7 BN3 DDR0_DQ_6/DDR0_DQ_6 NC/DDR0_CKP_3 AL1
DDR_A_D8 BL4 DDR0_DQ_7/DDR0_DQ_7 NC/DDR0_CKN_3
DDR_A_D9 BL5 DDR0_DQ_8/DDR0_DQ_8 AT1 DDR_A_CKE0
DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_0/DDR0_CKE_0 DDR_A_CKE0 <23>
DDR_A_D10 BL2 AT2 DDR_A_CKE1
DDR0_DQ_10/DDR0_DQ_10 DDR0_CKE_1/DDR0_CKE_1 DDR_A_CKE1 <23>
DDR_A_D11 BM1 AT3
DDR_A_D12 BK4 DDR0_DQ_11/DDR0_DQ_11 DDR0_CKE_2/DDR0_CKE_2 AT5
DDR_A_D13 BK5 DDR0_DQ_12/DDR0_DQ_12 DDR0_CKE_3/DDR0_CKE_3
DDR_A_D14 BK1 DDR0_DQ_13/DDR0_DQ_13 AD5 DDR_A_CS#0
DDR0_DQ_14/DDR0_DQ_14 DDR0_CS#_0/DDR0_CS#_0 DDR_A_CS#0 <23>
DDR_A_D15 BK2 AE2 DDR_A_CS#1
DDR0_DQ_15/DDR0_DQ_15 DDR0_CS#_1/DDR0_CS#_1 DDR_A_CS#1 <23>
DDR_A_D16 BG4 AD2
DDR_A_D17 BG5 DDR0_DQ_16/DDR0_DQ_32 NC/DDR0_CS#_2 AE5
DDR_A_D18 BF4 DDR0_DQ_17/DDR0_DQ_33 NC/DDR0_CS#_3
DDR_A_D19 BF5 DDR0_DQ_18/DDR0_DQ_34 AD3 DDR_A_ODT0
DDR0_DQ_19/DDR0_DQ_35 DDR0_ODT_0/DDR0_ODT_0 DDR_A_ODT0 <23>
DDR_A_D20 BG2 AE4 DDR_A_ODT1
DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_ODT_1 DDR_A_ODT1 <23>
DDR_A_D21 BG1 AE1
DDR_A_D22 BF1 DDR0_DQ_21/DDR0_DQ_37 NC/DDR0_ODT_2 AD4
DDR_A_D23 BF2 DDR0_DQ_22/DDR0_DQ_38 NC/DDR0_ODT_3
DDR_A_D24 BD2 DDR0_DQ_23/DDR0_DQ_39 AH5 DDR_A_BA0
DDR0_DQ_24/DDR0_DQ_40 DDR0_CAB_4/DDR0_BA_0 DDR_A_BA0 <23>
DDR_A_D25 BD1 AH1 DDR_A_BA1
DDR0_DQ_25/DDR0_DQ_41 DDR0_CAB_6/DDR0_BA_1 DDR_A_BA1 <23>
DDR_A_D26 BC4 AU1 DDR_A_BG0
DDR0_DQ_26/DDR0_DQ_42 DDR0_CAA_5/DDR0_BG_0 DDR_A_BG0 <23>
2 DDR_A_D27 BC5 2
DDR_A_D28 BD5 DDR0_DQ_27/DDR0_DQ_43 AH4 DDR_A_MA16_RAS#
DDR0_DQ_28/DDR0_DQ_44 DDR0_CAB_3/DDR0_MA_16 DDR_A_MA16_RAS# <23>
DDR_A_D29 BD4 AG4 DDR_A_MA14_W E#
DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_2/DDR0_MA_14 DDR_A_MA14_W E# <23>
DDR_A_D30 BC1 AD1 DDR_A_MA15_CAS#
DDR0_DQ_30/DDR0_DQ_46 DDR0_CAB_1/DDR0_MA_15 DDR_A_MA15_CAS# <23>
DDR_A_D31 BC2
DDR_A_D32 AB1 DDR0_DQ_31/DDR0_DQ_47 AH3 DDR_A_MA0
DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_9/DDR0_MA_0 DDR_A_MA0 <23>
DDR_A_D33 AB2 AP4 DDR_A_MA1
DDR_A_D34 AA4 AN4 DDR_A_MA2
DDR_A_D35 AA5 AP5 DDR_A_MA3
DDR0_DQ_35/DDR1_DQ_3 NC/DDR0_MA_3 DDR_A_MA3 <23>
DDR0_DQ_36/DDR1_DQ_4 NC/DDR0_MA_4 DDR_A_MA4 <23>
DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_0/DDR0_MA_5 DDR_A_MA5 <23>
DDR_A_D38 AA2 AP3 DDR_A_MA6
DDR_A_D39 AA1 AN1 DDR_A_MA7
DDR_A_D40 V5 AN3 DDR_A_MA8
DDR_A_D41 V2 AT4 DDR_A_MA9
DDR_A_D42 U1 AH2 DDR_A_MA10
DDR_A_D43 U2 AN2 DDR_A_MA11
DDR_A_D44 V1 AU4 DDR_A_MA12
DDR_A_D45 V4 AE3 DDR_A_MA13
DDR_A_D46 U5 AU2 DDR_A_BG1
DDR0_DQ_46/DDR1_DQ_14 DDR0_CAA_9/DDR0_BG_1 DDR_A_BG1 <23>
DDR_A_D47 U4 AU3 DDR_A_ACT#
DDR0_DQ_47/DDR1_DQ_15 DDR0_CAA_8/DDR0_ACT# DDR_A_ACT# <23>
DDR_A_D48 R2
DDR_A_D49 P5 DDR0_DQ_48/DDR1_DQ_32 AG3 DDR_A_PAR
DDR0_DQ_49/DDR1_DQ_33 NC/DDR0_PAR DDR_A_PAR <23>
DDR_A_D50 R4 AU5 DDR_A_ALERT#
DDR0_DQ_50/DDR1_DQ_34 NC/DDR0_ALERT# DDR_A_ALERT# <23>
DDR_A_D51 P4
DDR_A_D52 R5 DDR0_DQ_51/DDR1_DQ_35 DDR4(IL)/LP3-DDR4(NIL)
DDR_A_D53 P2 DDR0_DQ_52/DDR1_DQ_36 BR5 DDR_A_DQS#0
DDR0_DQ_53/DDR1_DQ_37DDR0_DQSN_0/DDR0_DQSN_0 DDR_A_DQS#0 <23>
DDR_A_D54 R1 BL3 DDR_A_DQS#1
DDR_A_D55 P1 BG3 DDR_A_DQS#2
3 DDR0_DQ_55/DDR1_DQ_39DDR0_DQSN_2/DDR0_DQSN_4 DDR_A_DQS#2 <23> 3
DDR_A_D56 M4 BD3 DDR_A_DQS#3
DDR_A_D57 M1 AA3 DDR_A_DQS#4
DDR_A_D58 L4 U3 DDR_A_DQS#5
DDR_A_D59 L2 P3 DDR_A_DQS#6
DDR_A_D60 M5 L3 DDR_A_DQS#7
DDR_A_D61 M2
DDR_A_D62 L5 DDR0_DQ_61/DDR1_DQ_45 BP5 DDR_A_DQS0
DDR0_DQ_62/DDR1_DQ_46DDR0_DQSP_0/DDR0_DQSP_0 DDR_A_DQS0 <23>
DDR_A_D63 L1 BK3 DDR_A_DQS1
DDR0_DQ_63/DDR1_DQ_47DDR0_DQSP_1/DDR0_DQSP_1 DDR_A_DQS1 <23>
BF3 DDR_A_DQS2
DDR0_DQSP_2/DDR0_DQSP_4 DDR_A_DQS2 <23>
LP3/DDR4 BC3 DDR_A_DQS3
DDR0_DQSP_3/DDR0_DQSP_5 DDR_A_DQS3 <23>
BA2 AB3 DDR_A_DQS4
NC/DDR0_ECC_0 DDR0_DQSP_4/DDR1_DQSP_0 DDR_A_DQS4 <23>
BA1 V3 DDR_A_DQS5
AY4 R3 DDR_A_DQS6
AY5 M3 DDR_A_DQS7
BA5
BA4 NC/DDR0_ECC_4 AY3
AY1 NC/DDR0_ECC_5 DDR0_DQSP_8/DDR0_DQSP_8 BA3 For ECC DIMM
AY2 NC/DDR0_ECC_6 DDR0_DQSN_8/DDR0_DQSN_8
1 OF 13
For ECC DIMM NC/DDR0_ECC_7
CFL-H_BGA1440
@
4 4
2017/11/23
Compal Secret Data
2018/09/01 Title
CFL-H(2/8)DIMMA
A B C D E
A B C D E
CHANNEL-B
Interleaved Memory
UC1B
CFL-H
<24> DDR_B_D[0..63] DDR CHANNEL B

1 1
DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4
DDR_B_D0 BT11 AM9 DDR_B_CLK0
DDR1_DQ_0/DDR0_DQ_16 DDR1_CKP_0/DDR1_CKP_0 DDR_B_CLK0 <24>
DDR_B_D1 BR11 AN9 DDR_B_CLK#0
DDR1_DQ_1/DDR0_DQ_17 DDR1_CKN_0/DDR1_CKN_0 DDR_B_CLK#0 <24>
DDR_B_D2 BT9 AM7 DDR_B_CLK1
DDR1_DQ_2/DDR0_DQ_18 DDR1_CKP_1/DDR1_CKP_1 DDR_B_CLK1 <24>
DDR_B_D3 BR8 AM8 DDR_B_CLK#1
DDR1_DQ_3/DDR0_DQ_19 DDR1_CKN_1/DDR1_CKN_1 DDR_B_CLK#1 <24>
DDR_B_D4 BP11 AM11
DDR_B_D5 BN11 DDR1_DQ_4/DDR0_DQ_20 NC/DDR1_CKP_2 AM10
DDR_B_D6 BP8 DDR1_DQ_5/DDR0_DQ_21 NC/DDR1_CKN_2 AJ10
DDR_B_D7 BN8 DDR1_DQ_6/DDR0_DQ_22 NC/DDR1_CKP_3 AJ11
DDR_B_D8 BL12 DDR1_DQ_7/DDR0_DQ_23 NC/DDR1_CKN_3
DDR_B_D9 BL11 DDR1_DQ_8/DDR0_DQ_24 AT8 DDR_B_CKE0
DDR1_DQ_9/DDR0_DQ_25 DDR1_CKE_0/DDR1_CKE_0 DDR_B_CKE0 <24>
DDR_B_D10 BL8 AT10 DDR_B_CKE1
DDR1_DQ_10/DDR0_DQ_26 DDR1_CKE_1/DDR1_CKE_1 DDR_B_CKE1 <24>
DDR_B_D11 BJ8 AT7
DDR_B_D12 BJ11 DDR1_DQ_11/DDR0_DQ_27 DDR1_CKE_2/DDR1_CKE_2 AT11
DDR_B_D13 BJ10 DDR1_DQ_12/DDR0_DQ_28 DDR1_CKE_3/DDR1_CKE_3
DDR_B_D14 BL7 DDR1_DQ_13/DDR0_DQ_29 AF11 DDR_B_CS#0
DDR1_DQ_14/DDR0_DQ_30 DDR1_CS#_0/DDR1_CS#_0 DDR_B_CS#0 <24>
DDR_B_D15 BJ7 AE7 DDR_B_CS#1
DDR1_DQ_15/DDR0_DQ_31 DDR1_CS#_1/DDR1_CS#_1 DDR_B_CS#1 <24>
DDR_B_D16 BG11 AF10
DDR_B_D17 BG10 DDR1_DQ_16/DDR0_DQ_48 NC/DDR1_CS#_2 AE10
DDR_B_D18 BG8 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_CS#_3
DDR_B_D19 BF8 DDR1_DQ_18/DDR0_DQ_50 AF7 DDR_B_ODT0
DDR1_DQ_19/DDR0_DQ_51 DDR1_ODT_0/DDR1_ODT_0 DDR_B_ODT0 <24>
DDR_B_D20 BF11 AE8 DDR_B_ODT1
DDR1_DQ_20/DDR0_DQ_52 NC/DDR1_ODT_1 DDR_B_ODT1 <24>
DDR_B_D21 BF10 AE9
DDR_B_D22 BG7 DDR1_DQ_21/DDR0_DQ_53 NC/DDR1_ODT_2 AE11
DDR_B_D23 BF7 DDR1_DQ_22/DDR0_DQ_54 NC/DDR1_ODT_3
DDR_B_D24 BB11 DDR1_DQ_23/DDR0_DQ_55 AH10 DDR_B_MA16_RAS#
DDR1_DQ_24/DDR0_DQ_56 DDR1_CAB_3/DDR1_MA_16 DDR_B_MA16_RAS# <24>
DDR_B_D25 BC11 AH11 DDR_B_MA14_W E#
DDR1_DQ_25/DDR0_DQ_57 DDR1_CAB_2/DDR1_MA_14 DDR_B_MA14_W E# <24>
DDR_B_D26 BB8 AF8 DDR_B_MA15_CAS#
DDR1_DQ_26/DDR0_DQ_58 DDR1_CAB_1/DDR1_MA_15 DDR_B_MA15_CAS# <24>
2 DDR_B_D27 BC8 2
DDR_B_D28 BC10 DDR1_DQ_27/DDR0_DQ_59 AH8 DDR_B_BA0
DDR1_DQ_28/DDR0_DQ_60 DDR1_CAB_4/DDR1_BA_0 DDR_B_BA0 <24>
DDR_B_D29 BB10 AH9 DDR_B_BA1
DDR1_DQ_29/DDR0_DQ_61 DDR1_CAB_6/DDR1_BA_1 DDR_B_BA1 <24>
DDR_B_D30 BC7 AR9 DDR_B_BG0
DDR1_DQ_30/DDR0_DQ_62 DDR1_CAA_5/DDR1_BG_0 DDR_B_BG0 <24>
DDR_B_D31 BB7
DDR_B_D32 AA11 DDR1_DQ_31/DDR0_DQ_63 AJ9 DDR_B_MA0
DDR1_DQ_32/DDR1_DQ_16 DDR1_CAB_9/DDR1_MA_0 DDR_B_MA0 <24>
DDR_B_D33 AA10 AK6 DDR_B_MA1
DDR_B_D34 AC11 AK5 DDR_B_MA2
DDR_B_D35 AC10 AL5 DDR_B_MA3
DDR1_DQ_35/DDR1_DQ_19 NC/DDR1_MA_3 DDR_B_MA3 <24>
DDR_B_D36 AA7 AL6 DDR_B_MA4
DDR1_DQ_36/DDR1_DQ_20 NC/DDR1_MA_4 DDR_B_MA4 <24>
DDR_B_D37 AA8 AM6 DDR_B_MA5
DDR1_DQ_37/DDR1_DQ_21 DDR1_CAA_0/DDR1_MA_5 DDR_B_MA5 <24>
DDR_B_D38 AC8 AN7 DDR_B_MA6
DDR_B_D39 AC7 AN10 DDR_B_MA7
DDR_B_D40 W8 DDR4(IL)/LP3-DDR4(NIL) AN8 DDR_B_MA8
DDR_B_D41 W7 AR11 DDR_B_MA9
DDR_B_D42 V10 AH7 DDR_B_MA10
DDR_B_D43 V11 AN11 DDR_B_MA11
DDR_B_D44 W11 AR10 DDR_B_MA12
DDR_B_D45 W10 AF9 DDR_B_MA13
DDR_B_D46 V7 AR7 DDR_B_BG1
DDR1_DQ_46/DDR1_DQ_30 DDR1_CAA_9/DDR1_BG_1 DDR_B_BG1 <24>
DDR_B_D47 V8 AT9 DDR_B_ACT#
DDR1_DQ_47/DDR1_DQ_31 DDR1_CAA_8/DDR1_ACT# DDR_B_ACT# <24>
DDR_B_D48 R11
DDR_B_D49 P11 DDR1_DQ_48/DDR1_DQ_48 AJ7 DDR_B_PAR
DDR1_DQ_49/DDR1_DQ_49 NC/DDR1_PAR DDR_B_PAR <24>
DDR_B_D50 P7 AR8 DDR_B_ALERT#
DDR1_DQ_50/DDR1_DQ_50 NC/DDR1_ALERT# DDR_B_ALERT# <24>
DDR_B_D51 R8
DDR_B_D52 R10 DDR1_DQ_51/DDR1_DQ_51 DDR4(IL)/LP3-DDR4(NIL)
DDR_B_D53 P10 DDR1_DQ_52/DDR1_DQ_52 BN9 DDR_B_DQS#0
DDR1_DQ_53/DDR1_DQ_53DDR1_DQSN_0/DDR0_DQSN_2 DDR_B_DQS#0 <24>
DDR_B_D54 R7 BL9 DDR_B_DQS#1
3 DDR1_DQ_54/DDR1_DQ_54DDR1_DQSN_1/DDR0_DQSN_3 DDR_B_DQS#1 <24> 3
DDR_B_D55 P8 BG9 DDR_B_DQS#2
DDR_B_D56 L11 BC9 DDR_B_DQS#3
DDR_B_D57 M11 AC9 DDR_B_DQS#4
DDR_B_D58 L7 W9 DDR_B_DQS#5
DDR_B_D59 M8 R9 DDR_B_DQS#6
DDR_B_D60 L10 M9 DDR_B_DQS#7
DDR_B_D61 M10
DDR_B_D62 M7 DDR1_DQ_61/DDR1_DQ_61 BP9 DDR_B_DQS0
DDR1_DQ_62/DDR1_DQ_62DDR1_DQSP_0/DDR0_DQSP_2 DDR_B_DQS0 <24>
DDR_B_D63 L8 BJ9 DDR_B_DQS1
DDR1_DQ_63/DDR1_DQ_63DDR1_DQSP_1/DDR0_DQSP_3 DDR_B_DQS1 <24>
BF9 DDR_B_DQS2
DDR1_DQSP_2/DDR0_DQSP_6 DDR_B_DQS2 <24>
AW11 LP3/DDR4 BB9 DDR_B_DQS3
NC/DDR1_ECC_0 DDR1_DQSP_3/DDR0_DQSP_7 DDR_B_DQS3 <24>
AY11 AA9 DDR_B_DQS4
AY8 V9 DDR_B_DQS5
AW8 P9 DDR_B_DQS6
AY10 L9 DDR_B_DQS7
AW10
AY7 NC/DDR1_ECC_5 AW9
AW7 NC/DDR1_ECC_6 DDR1_DQSP_8/DDR1_DQSP_8 AY9 For ECC DIMM
For ECC DIMM NC/DDR1_ECC_7 DDR1_DQSN_8/DDR1_DQSN_8
RC3 1 2 121_0402_1% SM_RCOMP0 G1 BN13 +0.6V_VREFCA

+0.6V_VREFCA
RC4 1 2 75_0402_1% SM_RCOMP1 H1 DDR_RCOMP_0 DDR_VREF_CA BP13
RC5 1 2 100_0402_1% SM_RCOMP2 J2 DDR_RCOMP_1 2 OF 13 DDR0_VREF_DQ BR13 +0.6V_B_VREFDQ
DDR_RCOMP_2 DDR1_VREF_DQ +0.6V_B_VREFDQ
Trace Width/Space: 15 mil/ 25 mil CFL-H_BGA1440
Max Trace Length: 500 mil
4 @ 4
2017/11/23
Compal Secret Data
2018/09/01 Title
CFL-H(3/8)DIMMB
A B C D E
A B C D E
PEG&DMI
0806, chagne PEG AC cap to 0402 X7R 0806, chagne PEG AC cap to 0402 X7R
To DGPU
1 To DGPU PEG Lane Reversed
1
PEG Lane Reversed CFL-H

UC1C
CC1 VGA@ 1 2 0.22U_0402_16V7K PEG_CRX_GTX_P15 E25 B25 PEG_CTX_GRX_P15 0.22U_0402_16V7K 2 1VGA@ CC2
<25> PEG_CRX_C_GTX_P15 PEG_RXP_0 PEG_TXP_0 PEG_CTX_C_GRX_P15 <25>
CC3 VGA@ 1 2 0.22U_0402_16V7K PEG_CRX_GTX_N15 D25 A25 PEG_CTX_GRX_N15 0.22U_0402_16V7K 2 1VGA@ CC4
<25> PEG_CRX_C_GTX_N15 PEG_RXN_0 PEG_TXN_0 PEG_CTX_C_GRX_N15 <25>
CC6 VGA@ 1 2 0.22U_0402_16V7K PEG_CRX_GTX_N14 F24 C24 PEG_CTX_GRX_N14 0.22U_0402_16V7K 2 1VGA@ CC12
CC33 VGA@ 1 2 0.22U_0402_16V7K PEG_CRX_GTX_P7 D17 A17 PEG_CTX_GRX_P7 0.22U_0402_16V7K 2 1VGA@ CC34
2 CC35 VGA@ 1 2 0.22U_0402_16V7K PEG_CRX_GTX_N7 E17 B17 PEG_CTX_GRX_N7 0.22U_0402_16V7K 2 1VGA@ CC36 2
CC37 VGA@ 1 2 0.22U_0402_16V7K PEG_CRX_GTX_P6 F16 C16 PEG_CTX_GRX_P6 0.22U_0402_16V7K 2 1VGA@ CC38
CC39 VGA@ 1 2 0.22U_0402_16V7K PEG_CRX_GTX_N6 E16 B16 PEG_CTX_GRX_N6 0.22U_0402_16V7K 2 1VGA@ CC40
+VCCIO
RC6 1 2 24.9_0402_1% PEG_RCOMP G2
PEG_RCOMP
Trace Width/Space: 15 mil/ 15 mil
Max Trace Length: 600 mil
3 DMI_CRX_PTX_P0 D8 B8 DMI_CTX_PRX_P0 3
<14> DMI_CRX_PTX_P0 DMI_RXP_0 DMI_TXP_0 DMI_CTX_PRX_P0 <14>
DMI_CRX_PTX_N0 E8 A8 DMI_CTX_PRX_N0
<14> DMI_CRX_PTX_N0 DMI_RXN_0 DMI_TXN_0 DMI_CTX_PRX_N0 <14>
DMI_CRX_PTX_P1 E6 C6 DMI_CTX_PRX_P1
DMI_CRX_PTX_N1 F6 B6 DMI_CTX_PRX_N1
To PCH DMI_CRX_PTX_P2 D5 B5 DMI_CTX_PRX_P2 To PCH
DMI_CRX_PTX_N2 E5 A5 DMI_CTX_PRX_N2
DMI_CRX_PTX_P3 J8 D4 DMI_CTX_PRX_P3
<14> DMI_CRX_PTX_P3 DMI_RXP_3 3 OF 13 DMI_TXP_3
DMI_CTX_PRX_P3 <14>
DMI_CRX_PTX_N3 J9 B4 DMI_CTX_PRX_N3
CFL-H_BGA1440
@
4 4
2017/11/23
Compal Secret Data
2018/09/01 Title
CFL-H(4/8)PEG/DMI
A B C D E
A B C D E
CFL-H
UC1E
PCH_CPU_BCLK_P B31 BN25 CFG0 CFG0 RC7 1 @ 2 1K_0402_5%

<15> PCH_CPU_BCLK_P BCLKP CFG_0
PCH_CPU_BCLK_N A32 BN27 CFG2 RC8 1 2 1K_0402_5%
<15> PCH_CPU_BCLK_N BCLKN CFG_1 BN26 CFG2 CFG4 RC9 1 @ 2 1K_0402_5%
PCH_CPU_PCIBCLK_P D35 CFG_2 BN28 CFG3 CFG5 RC10 1 @ 2 1K_0402_5%
<15> PCH_CPU_PCIBCLK_P PCI_BCLKP CFG_3 TC22 TP@
PCH_CPU_PCIBCLK_N C36 BR20 CFG4 CFG6 RC11 1 @ 2 1K_0402_5%
<15> PCH_CPU_PCIBCLK_N PCI_BCLKN CFG_4 BM20 CFG5 CFG7 RC12 1 @ 2 1K_0402_5%
PCH_CPU_24M_CLK_P E31 CFG_5 BT20 CFG6
<15> PCH_CPU_24M_CLK_P CLK24P CFG_6
PCH_CPU_24M_CLK_N D31 BP20 CFG7
571391_CFL_H_PDG_Rev0p5 <15> PCH_CPU_24M_CLK_N CLK24N CFG_7
1. The total Length of Data and Clock (from CPU to each VR) must be equal (±0.1 inch). BR23
CFG_8 BR22
1 2. Route the Alert signal between the Clock and the Data signals. CFG_9 1
3. Place those resistors close CPU side. BT23 The CFG signals have a default value of '1' if not terminated on the board.
CFG_10 BT22 CFG[0]: Stall reset sequence after PCU PLL lock until de-asserted
CFG_11 BM19 * 1 = (Default) Normal Operation;
CFG_12 BR19 0 = Stall.
Sensitive CFG_13 BP19 CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.
CPU_SVID_ALERT# BH31 CFG_14 BT19 1 = Normal operation
CPU_SVID_CLK BH32 VIDALERT# CFG_15 disable eDP * 0 = Lane numbers reversed.
<89> CPU_SVID_CLK CPU_SVID_DAT VIDSCK
BH29 BN23 CFG[4]: eDP enable:
H_PROCHOT#_R BR30 VIDSOUT CFG_17 BP23 * 1 = Disabled.
PROCHOT# CFG_16 BP22 0 = Enabled.
DDR_PG_CTRL BT13 CFG_19 BN22 CFG[6:5]: PCI Express* Bifurcation:
DDR_VTT_CNTL CFG_18 00 = 1 x8, 2 x4 PCI Express*
01 = reserved
BR27 XDP_BPM#0 10 = 2 x8 PCI Express*
BPM#_0 TC1 TP@
BT27 XDP_BPM#1 TC2 TP@ * 11 = 1 x16 PCI Express*
Sensitive BPM#_1 BM31 XDP_BPM#2 TC3 TP@ CFG[7]: PEG Training:
EC_VCCST_PG H13 BPM#_2 BT30 XDP_BPM#3 * 1 = (default) PEG Train immediately following RESET# de assertion.
VCCST_PWRGD BPM#_3 TC4 TP@
0 = PEG Wait for BIOS for training.
H_CPUPW RGD BT31 *CFG Pin Use CMC debug on DDX03 R02 Schematic.
<18> H_CPUPW RGD PROCPWRGD
H_PLTRST_CPU# BP35 BT28 CPU_XDP_TDO
<17> H_PLTRST_CPU# RESET# PROC_TDO CPU_XDP_TDO <18>
H_PM_SYNC_R BM34 BL32 CPU_XDP_TDI
<17> H_PM_SYNC_R PM_SYNC PROC_TDI CPU_XDP_TDI <18>
H_PM_DOW N BP31 BP28 CPU_XDP_TMS
H_PECI PM_DOWN PROC_TMS CPU_XDP_TCK0 CPU_XDP_TMS <18>
BT34 BR28
<17,58> H_PECI H_THERMTRIP# PECI PROC_TCK CPU_XDP_TCK0 <18>
RC17 1 @ 2 0_0402_5% J31 To be confirm
<17> PCH_THERMTRIP#_R THERMTRIP# CPU_XDP_TRST#
BP30
PROC_TRST# XDP_PREQ# CPU_XDP_TRST# <21>
TP@ TC5 SKTOCC# BR33 BL30 TC19 TP@
BN1 SKTOCC# PROC_PREQ# BP27 XDP_PRDY#
PROC_SELECT# PROC_SELECT# PROC_PRDY# TC20 TP@
2
should be unconnected on CFL processor CATERR# BM30 2
TP@ TC6
EDS1.2 8/21 CATERR# BT25 CFG_RCOMP 1 RC18 2 49.9_0402_1% XDP_PREQ#
CFG_RCOMP XDP_PRDY# XDP_PREQ# <21>
AT13
XEMC@ AW13 ZVM# XDP_PRDY# <21>
.1U_0402_16V7K 1 2 CC65 H_CPUPW RGD MSM# Trace Width/Space: 4 mil/ 12 mil
AU13 Max Trace Length: 600 mil
EMC@ AY13 RSVD1
1000P_0402_50V7K 1 2 CC66 H_PROCHOT#_R RSVD2
5 OF 13
XEMC@ +1.05VS_VCCSTG
.1U_0402_16V7K 1 2 CC67 H_THERMTRIP# CFL-H_BGA1440 Place to CPU side
@
EMC@ RC76 2 CMC@ 1 51_0402_5% CPU_XDP_TMS
1000P_0402_50V7K 1 2 CC68 EC_VCCST_PG
RC77 2 CMC@ 1 51_0402_5% CPU_XDP_TDI
RC78 2 CMC@ 1 51_0402_5% CPU_XDP_TDO

Near CPU side
follow 1050 Request +3VS Place to CPU side
+1.2V_VDDQ
8/21 RC79 2 CMC@ 1 51_0402_5% CPU_XDP_TCK0
1
+1.05V_VCCST
RH1 1 2 1K_0402_5% H_THERMTRIP# RC23 RC81 2 @ 1 51_0402_5% CPU_XDP_TRST#
CC69
UC3 330K_0402_5%
1 5 2 1
NC VCC RC80 2 @ 1 51_0402_5% PCH_JTAG_TCK1
PCH_JTAG_TCK1 <18>
2
DDR_PG_CTRL 2 .1U_0402_16V7K
A 4 SM_PG_CTRL
Y SM_PG_CTRL <85>
3
3 +1.05VS_VCCSTG GND 3
PU 330K follow CRB
74AUP1G07GW _TSSOP5 Place to PCH side
8/21
1
RC21
1K_0402_5%
SVID
2
RC14 1 2 499_0402_1% H_PROCHOT#_R

<58,82,83> H_PROCHOT#
+1.05V_VCCST
+1.05V_VCCST
1
RC22
1K_0402_5%
RC19 RC20
56_0402_1% 100_0402_1%
2
RC15 1 2 60.4_0402_1% EC_VCCST_PG

<58,78> EC_VCCST_PG_R
RC16 1 2 20_0402_5% H_PM_DOW N RC13 1 2 220_0402_5% CPU_SVID_ALERT#

<17> H_PM_DOW N_R <89> CPU_SVID_ALERT#_R
4 4
1
CPU_SVID_DAT
<89> CPU_SVID_DAT
RH2
@ 13_0402_5%
2
2017/11/23
Compal Secret Data
2018/09/01 Title
CFL-H(5/8)CFG,SVID
A B C D E
A B C D E
Power delete GT Power 7/27 +VCC_CORE +VCC_CORE +VCC_CORE CFL-H +VCC_CORE

CFL-H CFL-H UC1J
UC1K UC1I
AT14
VCCGT1 VCCGT80
BD35 AA13
VCC1 VCC64
AH13 128000mA(Hexa Core GT2) K14
VCC1 VCC64
W35
AT31 BD36 AA31 AH14 L13 W36
AT32 VCCGT2 VCCGT81 BE31 AA32 VCC2 VCC65 AH29 L14 VCC2 VCC65 W37
AT33 VCCGT3 VCCGT82 BE32 AA33 VCC3 VCC66 AH30 N13 VCC3 VCC66 W38
AT34 VCCGT4 VCCGT83 BE33 AA34 VCC4 VCC67 AH31 N14 VCC4 VCC67 Y29
AT35 VCCGT5 VCCGT84 BE34 AA35 VCC5 VCC68 AH32 N30 VCC5 VCC68 Y30
AT36 VCCGT6 VCCGT85 BE35 AA36 VCC6 VCC69 AJ14 N31 VCC6 VCC69 Y31
1 1
AU14 VCCGT9 VCCGT88 BE38 AB29 VCC9 VCC72 AJ31 N36 VCC9 VCC72 Y34
AU29 VCCGT10 VCCGT89 BF13 AB30 VCC10 VCC73 AJ32 N37 VCC10 VCC73 Y35
AU30 VCCGT11 VCCGT90 BF14 AB31 VCC11 VCC74 AJ33 N38 VCC11 VCC74 Y36
AU31 VCCGT12 VCCGT91 BF29 AB32 VCC12 VCC75 AJ34 P13 VCC12 VCC75
AU32 VCCGT13 VCCGT92 BF30 AB35 VCC13 VCC76 AJ35 P14 VCC13
AU35 VCCGT14 VCCGT93 BF31 AB36 VCC14 VCC77 AJ36 P29 VCC14
AU36 VCCGT15 VCCGT94 BF32 AB37 VCC15 VCC78 AK31 P30 VCC15
AU37 VCCGT16 VCCGT95 BF35 AB38 VCC16 VCC79 AK32 P31 VCC16
AU38 VCCGT17 VCCGT96 BF36 AC13 VCC17 VCC80 AK33 P32 VCC17
AV29 VCCGT18 VCCGT97 BF37 AC14 VCC18 VCC81 AK34 P33 VCC18
AV30 VCCGT19 VCCGT98 BF38 AC29 VCC19 VCC82 AK35 P34 VCC19
AV31 VCCGT20 VCCGT99 BG29 AC30 VCC20 VCC83 AK36 P35 VCC20
AV32 VCCGT21 VCCGT100 BG30 AC31 VCC21 VCC84 AK37 P36 VCC21
AV33 VCCGT22 VCCGT101 BG31 AC32 VCC22 VCC85 AK38 R13 VCC22
AV34 VCCGT23 VCCGT102 BG32 AC33 VCC23 VCC86 AL13 R31 VCC23
AW14 VCCGT26 VCCGT105 BG35 AC36 VCC26 VCC89 AL31 R34 VCC26
AW31 VCCGT27 VCCGT106 BG36 AD13 VCC27 VCC90 AL32 R35 VCC27
AW32 VCCGT28 VCCGT107 BH33 AD14 VCC28 VCC91 AL35 R36 VCC28
AW35 VCCGT31 VCCGT110 BH36 AD33 VCC31 VCC94 AL38 T29 VCC31
AW36 VCCGT32 VCCGT111 BH37 AD34 VCC32 VCC95 AM13 T30 VCC32
AW37 VCCGT33 VCCGT112 BH38 AD35 VCC33 VCC96 AM14 T31 VCC33
AW38 VCCGT34 VCCGT113 BJ16 AD36 VCC34 VCC97 AM29 T32 VCC34
AY29 VCCGT35 VCCGT114 BJ17 AD37 VCC35 VCC98 AM30 T35 VCC35
AY30 VCCGT36 VCCGT115 BJ19 AD38 VCC36 VCC99 AM31 T36 VCC36
2 AY31 VCCGT37 VCCGT116 BJ20 AE13 VCC37 VCC100 AM32 T37 VCC37 2
AY32 VCCGT38 VCCGT117 BJ21 AE14 VCC38 VCC101 AM33 T38 VCC38
AY35 VCCGT39 VCCGT118 BJ23 AE30 VCC39 VCC102 AM34 U29 VCC39
AY38 VCCGT42 VCCGT121 BJ27 AE35 VCC42 VCC105 AN13 U32 VCC42
BA13 VCCGT43 VCCGT122 BJ37 AE36 VCC43 VCC106 AN14 U33 VCC43
BA14 VCCGT44 VCCGT123 BJ38 AE37 VCC44 VCC107 AN31 U34 VCC44
BA29 VCCGT45 VCCGT124 BK16 AE38 VCC45 VCC108 AN32 U35 VCC45
BA30 VCCGT46 VCCGT125 BK17 AF29 VCC46 VCC109 AN33 U36 VCC46
BA31 VCCGT47 VCCGT126 BK19 AF30 VCC47 VCC110 AN34 V13 VCC47
BA36 VCCGT52 VCCGT131 BK26 AF35 VCC52 VCC115 AP13 V34 VCC52
BB13 VCCGT53 VCCGT132 BK27 AF36 VCC53 VCC116 AP30 V35 VCC53
BB14 VCCGT54 VCCGT133 BL15 AF37 VCC54 VCC117 AP31 V36 VCC54
BB31 VCCGT55 VCCGT134 BL16 AF38 VCC55 VCC118 AP32 V37 VCC55
BB32 VCCGT56 VCCGT135 BL17 AG14 VCC56 VCC119 AP35 V38 VCC56
BB33 VCCGT57 VCCGT136 BL23 AG31 VCC57 VCC120 AP36 W13 VCC57
BB36 VCCGT60 VCCGT139 BL26 AG34 VCC60 VCC123 K13 W30 VCC60
BB37 VCCGT61 VCCGT140 BL27 AG35 VCC61 VCC124 W31 VCC61
BB38 VCCGT62 VCCGT141 BL28 AG36 VCC62 W32 VCC62 10 OF 13
BC29 VCCGT63 VCCGT142 BL36 VCC63 VCC63
BC30 VCCGT64 VCCGT143 BL37 CFL-H_BGA1440
BC31 VCCGT65 VCCGT144 BM15
3 VCCGT66 VCCGT145 @ 3
BC32 BM16 AG37 VCCSENSE
VCCGT67 VCCGT146 VCC_SENSE VCCSENSE <89>
BC35 BM17 9 OF 13 AG38 VSSSENSE
VCCGT68 VCCGT147 VSS_SENSE VSSSENSE <89>
BC36 BM36
BC37 VCCGT69 VCCGT148 BM37 CFL-H_BGA1440
BC38 VCCGT70 VCCGT149 BN15
VCCGT71 VCCGT150 @ 1. Vcc_SENSE/ Vss_SENSE Trace Length Match < 25 mils
BD13 BN16 2. Maintain 25-mil separation distance away from any other dynamic signals.
BD14 VCCGT72 VCCGT151 BN17
BD32 VCCGT76 VCCGT155 BP15
BP37 VCCGT79 VCCGT158 BR37
BP38 VCCGT159 VCCGT164 BT15
BR15 VCCGT160 VCCGT165 BT16
VCCGT163 VCCGT168
AH37
11 OFVSSGT_SENSE
13 AH38
VCCGT_SENSE
CFL-H_BGA1440 Reserve resistor to Gnd
@
@
RC82
CPU_VCCGT 1 2
4 4
0_0402_5%
2017/11/23
Compal Secret Data
2018/09/01 Title
CFL-H(6/8)VCC_CORE/GT
A B C D E
A B C D E
+1.2V_VDDQ@CPU
Max: 3300mA
+VCC_SA CFL-H +1.2V_VDDQ +1.2V_VDDQ

UC1L
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
+VCC_SA J30 AA6
VCCSA1 VDDQ1
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
Max: 11100mA K29 AE12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
K30 VCCSA2 VDDQ2 AF5
VCCSA3 VDDQ3
CC70
CC71
CC72
CC73
CC74
CC75
CC76
CC77
CC78
CC79
CC80
CC81
CC82
CC83
CC84
CC85
K31 AF6
K32 VCCSA4 VDDQ4 AG5
K33 VCCSA5 VDDQ5 AG9 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 1
K34 VCCSA6 VDDQ6 AJ12
K35 VCCSA7 VDDQ7 AL11
L31 VCCSA8 VDDQ8 AP6
L32 VCCSA9 VDDQ9 AP7
L35 VCCSA10 VDDQ10 AR12 571483_CFL_H_RVP_CRB_TDK_Rev0p5
L36 VCCSA11 VDDQ11 AR6 +1.2V_VDDQ@CPU: 10uF * 12 22uF * 4
L37 VCCSA12 VDDQ12 AT12
VCCSA13 VDDQ13 PLACE CAP BACKSIDE
L38 AW6
M29 VCCSA14 VDDQ14 AY6
M30 VCCSA15 VDDQ15 J5
M31 VCCSA16 VDDQ16 J6
M32 VCCSA17 VDDQ17 K12 +1.2V_VDDQ +1.2V_VCCPLL_OC
M33 VCCSA18 VDDQ18 K6 +VCCIO
M34 VCCSA19 VDDQ19 L12 RC24 1 @ 2 0_0402_5%
+VCC_IO M35 VCCSA20 VDDQ20 L6
VCCSA21 VDDQ21
1U_0201_6.3V6M
1U_0201_6.3V6M
Max: 6400mA M36 R6
VCCSA22 VDDQ22
10U_0402_6.3V6M
T6 1 1
+VCCIO VDDQ23
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
W6 1 1 1 1 @
VDDQ24
CC86
CC87
Y12
VDDQ25
CC88
CC89
CC90
CC91
AG12
G15 VCCIO1 +1.2V_VCCPLL_OC 2 2
G17 VCCIO2 +1.2V_VCCPLL_OC 2 2 2 2
G19 VCCIO3 BH13 Max: 130mA
G21 VCCIO4 VCCPLL_OC1 BJ13
H15 VCCIO5 VCCPLL_OC2 G11 +1.05V_VCCST
H16 VCCIO6 VCCPLL_OC3
H17 VCCIO7 H30 Max: 60mA +1.05VS_VCCSTG
H19 VCCIO8 VCCST 571483_CFL_H_RVP_CRB_TDK_Rev0p5 571483_CFL_H_RVP_CRB_TDK_Rev0p5
2 H20 VCCIO9 H29 Max: 20mA +1.2V_VCCPLL_OC: 1uF * 2 +0.95VS_VCCIO: 10uF * 12 22uF * 4 2
H21 VCCIO10 VCCSTG2
VCCIO11 +1.05V_VCCSFR
PLACE CAP BACKSIDE
H26 G30
H27 VCCIO12 VCCSTG1
J15 VCCIO13 H28 Max: 150mA
J16 VCCIO14 VCCPLL1 J28
J17 VCCIO15 VCCPLL2
J19 VCCIO16 +1.05V_VCCST +1.05V_VCCSFR
J20 VCCIO17 M38 VCCSA_SENSE
VCCIO18 VCCSA_SENSE VSSSA_SENSE VCCSA_SENSE <89>
J21 M37 RC25 1 @ 2 0_0402_5%
VCCIO19 VSSSA_SENSE VSSSA_SENSE <89>
J26 150mA
VCCIO20
1U_0201_6.3V6M
1U_0201_6.3V6M
J27 H14 VCCIO_SENSE
VCCIO21 VCCIO_SENSE VSSIO_SENSE VCCIO_SENSE <88>
J14 1 1
12 OF 13 VSSIO_SENSE VSSIO_SENSE <88>
CC92
CC93
CFL-H_BGA1440
1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils 2 2
@
2. Maintain 25-mil separation distance away from any other dynamic signals.
571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCST: 1uF * 1 571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCSFR: 1uF * 1
PLACE CAP BACKSIDE PLACE CAP BACKSIDE
+1.05VS_VCCSTG
3 3
1U_0201_6.3V6M
1
CC94
2
571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05VS_VCCSTG: 1uF * 1
4 4
2017/11/23
Compal Secret Data
2018/09/01 Title
CFL-H(7/8)VCCSA/VCCIO/VDDQ
A B C D E
A B C D E
CFL-H
CFL-H CFL-H UC1H CFL-H
UC1F UC1G BN4 F15 UC1M
A10 AK4 AW5 BJ15 BN7 VSS_325 VSS_409 F17
A12 VSS_1 VSS_82 AL10 AY12 VSS_163 VSS_244 BJ18 BP12 VSS_326 VSS_410 F19
A16 VSS_2 VSS_83 AL12 AY33 VSS_164 VSS_245 BJ22 BP14 VSS_327 VSS_411 F2 E2
VSS_3 VSS_84 VSS_165 VSS_246 VSS_328 VSS_412 Impedance Spectrum Tool Trigger TP@ TC7
IST_TRIG E3 RSVD_TP5
A18 AL14 AY34 BJ25 BP18 F21 TP@ TC8
A20 VSS_4 VSS_85 AL33 B9 VSS_166 VSS_247 BJ29 BP21 VSS_329 VSS_413 F23 E1 IST_TRIG
VSS_5 VSS_86 VSS_167 VSS_248 VSS_330 VSS_414 TP@ TC9 RSVD_TP4
A22 AL34 BA10 BJ30 BP24 F25 TP@ TC10 D1
A24 VSS_6 VSS_87 AL4 BA11 VSS_168 VSS_249 BJ31 BP25 VSS_331 VSS_415 F27 RSVD_TP3
A26 VSS_7 VSS_88 AL7 BA12 VSS_169 VSS_250 BJ32 BP26 VSS_332 VSS_416 F29 BR1 BK28
VSS_8 VSS_89 VSS_170 VSS_251 VSS_333 VSS_417 TP@ TC11 RSVD_TP1 RSVD11
1 A28 AL8 BA37 BJ33 BP29 F3 TP@ TC12 BT2 BJ28 1
A30 VSS_9 VSS_90 AL9 BA38 VSS_171 VSS_252 BJ34 BP33 VSS_334 VSS_418 F31 RSVD_TP2 RSVD10
A6 VSS_10 VSS_91 AM1 BA6 VSS_172 VSS_253 BJ35 BP34 VSS_335 VSS_419 F36 BN35
A9 VSS_11 VSS_92 AM12 BA7 VSS_173 VSS_254 BJ36 BP7 VSS_336 VSS_420 F4 RSVD15
AA12 VSS_12 VSS_93 AM2 BA8 VSS_174 VSS_255 BK13 BR12 VSS_337 VSS_421 F5 J24
AA29 VSS_13 VSS_94 AM3 BA9 VSS_175 VSS_256 BK14 BR14 VSS_338 VSS_422 F8 H24 RSVD28
AA30 VSS_14 VSS_95 AM37 BB1 VSS_176 VSS_257 BK15 BR18 VSS_339 VSS_423 F9 BN33 RSVD27
AB33 VSS_15 VSS_96 AM38 BB12 VSS_177 VSS_258 BK18 BR21 VSS_340 VSS_424 G10 BL34 RSVD14
AB34 VSS_16 VSS_97 AM4 BB2 VSS_178 VSS_259 BK22 BR24 VSS_341 VSS_425 G12 RSVD13
AB6 VSS_17 VSS_98 AM5 BB29 VSS_179 VSS_260 BK25 BR25 VSS_342 VSS_426 G14 N29
AC1 VSS_18 VSS_99 AN12 BB3 VSS_180 VSS_261 BK29 BR26 VSS_343 VSS_427 G16 R14 RSVD30
AC12 VSS_19 VSS_100 AN29 BB30 VSS_181 VSS_262 BK6 BR29 VSS_344 VSS_428 G18 AE29 RSVD31
AC2 VSS_20 VSS_101 AN30 BB4 VSS_182 VSS_263 BL13 BR34 VSS_345 VSS_429 G20 AA14 RSVD2
AC3 VSS_21 VSS_102 AN5 BB5 VSS_183 VSS_264 BL14 BR36 VSS_346 VSS_430 G22 AP29 RSVD1
AC37 VSS_22 VSS_103 AN6 BB6 VSS_184 VSS_265 BL18 BR7 VSS_347 VSS_431 G23 AP14 RSVD5
AC38 VSS_23 VSS_104 AP10 BC12 VSS_185 VSS_266 BL19 BT12 VSS_348 VSS_432 G24 A36 RSVD4
AC4 VSS_24 VSS_105 AP11 BC13 VSS_186 VSS_267 BL20 BT14 VSS_349 VSS_433 G26 VSS_A36
AC5 VSS_25 VSS_106 AP12 BC14 VSS_187 VSS_268 BL21 BT18 VSS_350 VSS_434 G28 A37
AC6 VSS_26 VSS_107 AP33 BC33 VSS_188 VSS_269 BL22 BT21 VSS_351 VSS_435 G4 VSS_A37
AD10 VSS_27 VSS_108 AP34 BC34 VSS_189 VSS_270 BL29 BT24 VSS_352 VSS_436 G5 PCH_TRIGOUT_R H23
VSS_28 VSS_109 VSS_190 VSS_271 VSS_353 VSS_437 <21> PCH_TRIGOUT_R PROC_TRIGIN
AD11 AP8 BC6 BL33 BT26 G6 RC26 1 2 30_0402_5% CPU_TRIGOUT J23
VSS_29 VSS_110 VSS_191 VSS_272 VSS_354 VSS_438 <21> CPU_TRIGOUT_R PROC_TRIGOUT
AD12 AP9 BD10 BL35 BT29 G8
AD29 VSS_30 VSS_111 AR1 BD11 VSS_192 VSS_273 BL38 BT32 VSS_355 VSS_439 G9 F30
AD30 VSS_31 VSS_112 AR13 BD12 VSS_193 VSS_274 BL6 BT5 VSS_356 VSS_440 H11 RSVD24
AD6 VSS_32 VSS_113 AR14 BD37 VSS_194 VSS_275 BM11 C11 VSS_357 VSS_441 H12
AD8 VSS_33 VSS_114 AR2 BD6 VSS_195 VSS_276 BM12 C13 VSS_358 VSS_442 H18 E30
AD9 VSS_34 VSS_115 AR29 BD7 VSS_196 VSS_277 BM13 C15 VSS_359 VSS_443 H22 RSVD23
AE33 VSS_35 VSS_116 AR3 BD8 VSS_197 VSS_278 BM14 C17 VSS_360 VSS_444 H25
AE34 VSS_36 VSS_117 AR30 BD9 VSS_198 VSS_279 BM18 C19 VSS_361 VSS_445 H32 B30 BL31
2 AE6 VSS_37 VSS_118 AR31 BE1 VSS_199 VSS_280 BM2 C21 VSS_362 VSS_446 H35 C30 RSVD7 RSVD12 AJ8 2
AF1 VSS_38 VSS_119 AR32 BE2 VSS_200 VSS_281 BM21 C23 VSS_363 VSS_447 J10 RSVD21 RSVD3 G13
AF12 VSS_39 VSS_120 AR33 BE29 VSS_201 VSS_282 BM22 C25 VSS_364 VSS_448 J18 RSVD25
AF13 VSS_40 VSS_121 AR34 BE3 VSS_202 VSS_283 BM23 C27 VSS_365 VSS_449 J22 G3
AF14 VSS_41 VSS_122 AR35 BE30 VSS_203 VSS_284 BM24 C29 VSS_366 VSS_450 J25 J3 RSVD26 C38
VSS_42 VSS_123 VSS_204 VSS_285 VSS_367 VSS_451 RSVD29 RSVD22 TC13 TP@
AF2 AR36 BE4 BM25 C31 J32 C1 TC14 TP@
AF3 VSS_43 VSS_124 AR37 BE5 VSS_205 VSS_286 BM26 C37 VSS_368 VSS_452 J33 RSVD20 BR2
VSS_44 VSS_125 VSS_206 VSS_287 VSS_369 VSS_453 RSVD17 TC15 TP@
AF4 AR38 BE6 BM27 C5 J36 BR35 BP1 TC16 TP@
AG10 VSS_45 VSS_126 AR4 BF12 VSS_207 VSS_288 BM28 C8 VSS_370 VSS_454 J4 BR31 RSVD19 RSVD16 B38
VSS_46 VSS_127 VSS_208 VSS_289 VSS_371 VSS_455 RSVD18 RSVD8 TC17 TP@
AG11 AR5 BF33 BM29 C9 J7 BH30 B2 TC18 TP@
AG13 VSS_47 VSS_128 AT29 BF34 VSS_209 VSS_290 BM3 D10 VSS_372 VSS_456 K1 RSVD9 RSVD6
AG29 VSS_48 VSS_129 AT30 BF6 VSS_210 VSS_291 BM33 D12 VSS_373 VSS_457 K10 13 OF 13
VSS_49 VSS_130 VSS_211 VSS_292 VSS_374 VSS_458 Add for Corner NCTF testing
AG30 AT6 BG12 BM35 D14 K11
AG6 VSS_50 VSS_131 AU10 BG13 VSS_212 VSS_293 BM38 D16 VSS_375 VSS_459 K2 CFL-H_BGA1440
AG7 VSS_51 VSS_132 AU11 BG14 VSS_213 VSS_294 BM5 D18 VSS_376 VSS_460 K3
VSS_52 VSS_133 VSS_214 VSS_295 VSS_377 VSS_461 @
AG8 AU12 BG37 BM6 D20 K38
AH12 VSS_53 VSS_134 AU33 BG38 VSS_215 VSS_296 BM7 D22 VSS_378 VSS_462 K4
AH33 VSS_54 VSS_135 AU34 BG6 VSS_216 VSS_297 BM8 D24 VSS_379 VSS_463 K5
AH34 VSS_55 VSS_136 AU6 BH1 VSS_217 VSS_298 BM9 D26 VSS_380 VSS_464 K7
AH35 VSS_56 VSS_137 AU7 BH10 VSS_218 VSS_299 BN12 D28 VSS_381 VSS_465 K8
AH36 VSS_57 VSS_138 AU8 BH11 VSS_219 VSS_300 BN14 D3 VSS_382 VSS_466 K9
AH6 VSS_58 VSS_139 AU9 BH12 VSS_220 VSS_301 BN18 D30 VSS_383 VSS_467 L29
AJ1 VSS_59 VSS_140 AV37 BH14 VSS_221 VSS_302 BN19 D33 VSS_384 VSS_468 L30
AJ13 VSS_60 VSS_141 AV38 BH2 VSS_222 VSS_303 BN2 D6 VSS_385 VSS_469 L33
AJ2 VSS_61 VSS_142 AW1 BH3 VSS_223 VSS_304 BN20 D9 VSS_386 VSS_470 L34
AJ3 VSS_62 VSS_143 AW12 BH4 VSS_224 VSS_305 BN21 E34 VSS_387 VSS_471 M12
AJ37 VSS_63 VSS_144 AW2 BH5 VSS_225 VSS_306 BN24 E35 VSS_388 VSS_472 M13
AJ38 VSS_64 VSS_145 AW29 BH6 VSS_226 VSS_307 BN29 E38 VSS_389 VSS_473 N10
AJ4 VSS_65 VSS_146 AW3 BH7 VSS_227 VSS_308 BN30 E4 VSS_390 VSS_474 N11
3 AJ5 VSS_66 VSS_147 AW30 BH8 VSS_228 VSS_309 BN31 E9 VSS_391 VSS_475 N12 3
AJ6 VSS_67 VSS_148 AW4 BH9 VSS_229 VSS_310 BN34 N3 VSS_392 VSS_476 N2
W4 VSS_68 VSS_149 U6 T2 VSS_230 VSS_311 P38 N33 VSS_393 VSS_477 BT8
W5 VSS_69 VSS_150 V12 T3 VSS_231 VSS_312 P6 N34 VSS_394 VSS_478 BR9
Y10 VSS_70 VSS_151 V29 T33 VSS_232 VSS_313 R12 N4 VSS_395 VSS_479
Y11 VSS_71 VSS_152 V30 T34 VSS_233 VSS_314 R29 N5 VSS_396 A3
Y13 VSS_72 VSS_153 A14 T4 VSS_234 VSS_315 AY14 N6 VSS_397 VSS_A3 A34
Y14 VSS_73 VSS_154 AD7 T5 VSS_235 VSS_316 BD38 N7 VSS_398 VSS_A34 A4
Y37 VSS_74 VSS_155 V6 T7 VSS_236 VSS_317 R30 N8 VSS_399 VSS_A4 B3
Y38 VSS_75 VSS_156 W1 T8 VSS_237 VSS_318 T1 N9 VSS_400 VSS_B3 B37
Y7 VSS_76 VSS_157 W12 T9 VSS_238 VSS_319 T10 P12 VSS_401 VSS_B37 BR38
Y8 VSS_77 VSS_158 W2 U37 VSS_239 VSS_320 T11 P37 VSS_402 VSS_BR38 BT3
Y9 VSS_78 VSS_159 W3 U38 VSS_240 VSS_321 T12 M14 VSS_403 VSS_BT3 BT35
AK29 VSS_79 VSS_160 W33 BJ12 VSS_241 VSS_322 T13 M6 VSS_404 VSS_BT35 BT36
AK30 VSS_80
6 OF VSS_161
13 W34 BJ14 VSS_2427 OF VSS_323
13 T14 N1 VSS_405 VSS_BT36 BT4
VSS_81 VSS_162 VSS_243 VSS_324 F11 VSS_406 VSS_BT4 C2
CFL-H_BGA1440 CFL-H_BGA1440 F13 VSS_4078 OF 13VSS_C2 D38
VSS_408 VSS_D38
@ @
CFL-H_BGA1440
@
4 4
2017/11/23
Compal Secret Data
2018/09/01 Title
CFL-H(8/8)GND/RSVD
A B C D E
A B C D E
CNP-H
UH1B
<9> DMI_CTX_PRX_N0
DMI_CTX_PRX_N0
DMI_CTX_PRX_P0
K34
DMI0_RXN USB2N_1
J3 USB20_N1
USB20_P1 USB20_N1 <71>
Raptor
<9> DMI_CTX_PRX_P0 J35 J2 USB3 MB
DMI_CRX_PTX_N0 DMI0_RXP USB2P_1 USB20_N2 USB20_P1 <71>
<9> DMI_CRX_PTX_N0 C33 N13
DMI_CRX_PTX_P0 DMI0_TXN USB2N_2 USB20_P2 USB20_N2 <48>
<9> DMI_CRX_PTX_P0 B33 N15 USB3 MB NV TypeC
DMI_CTX_PRX_N1 DMI0_TXP USB2P_2 USB20_N3 USB20_P2 <48>
<9> DMI_CTX_PRX_N1 G33 K4
DMI_CTX_PRX_P1 DMI1_RXN USB2N_3 USB20_P3 USB20_N3 <73>
<9> DMI_CTX_PRX_P1 F34 K3 USB3 SUB
DMI_CRX_PTX_N1 DMI1_RXP USB2P_3 USB20_P3 <73> +3VALW _PCH_PRIM
<9> DMI_CRX_PTX_N1 C32 M10
DMI_CRX_PTX_P1 B32 DMI1_TXN USB2N_4 L9
<9> DMI_CRX_PTX_P1 DMI1_TXP USB2P_4
DMI_CTX_PRX_N2 K32 M1 USB20_N5
<9> DMI_CTX_PRX_N2 DMI2_RXN USB2N_5 USB20_N5 <38>
DMI_CTX_PRX_P2 J32 L2 USB20_P5
<9> DMI_CTX_PRX_P2
DMI_CRX_PTX_N2 C31 DMI2_RXP USB2P_5 K7 USB20_N6 USB20_P5 <38> Camera
<9> DMI_CRX_PTX_N2 DMI2_TXN USB2N_6 USB20_N6 <38>
DMI_CRX_PTX_P2 B31 K6 USB20_P6
1 <9> DMI_CRX_PTX_P2
DMI_CTX_PRX_N3 G30 DMI2_TXP USB2P_6 L4
USB20_P6 <38> TS 1
<9> DMI_CTX_PRX_N3 DMI3_RXN USB2N_7
DMI_CTX_PRX_P3 F30 L3 USB_OC0# RH213 1 2 10K_0402_5%
<9> DMI_CTX_PRX_P3 DMI3_RXP USB2P_7
DMI_CRX_PTX_N3 C29 G4
<9> DMI_CRX_PTX_N3 DMI3_TXN USB2N_8
DMI_CRX_PTX_P3 B29 G5 USB_OC1# RH214 1 2 10K_0402_5%
<9> DMI_CRX_PTX_P3 DMI3_TXP USB2P_8
A25 M6
B25 RSVD USB2N_9 N8 USB_OC2# RH215 1 2 10K_0402_5%
P24 RSVD USB2P_9 H3 USB20_N10
RSVD USB2N_10 USB20_P10 USB20_N10 <63> USB_OC3# RH216
R24 H2 KB 1 2 10K_0402_5%
RSVD USB2P_10 USB20_P10 <63>
C26 R10
B26 RSVD USB2N_11 P9
F26 RSVD USB2P_11 G1
G26 RSVD USB2N_12 G2
RSVD USB2P_12 USB20_N13
FOR CNVI follow 571906_CNL_PCH_TA_WW11.pdf
B27 N3
RSVD USB2N_13 USB20_P13 USB20_N13 <73>
C27 N2 XBOX +3VALW
RSVD USB2P_13 USB20_N14 USB20_P13 <73>
L26 E5 X'tal Input:
RSVD USB2N_14 USB20_P14 USB20_N14 <52>
M26 F6 BT High: Differential
RSVD USB2P_14 USB20_P14 <52>
D29 Low: Single ended
RSVD
1
E28 AH36 USB_OC0#
K29 RSVD GPP_E9/USB2_OC0# AL40 USB_OC1#
RSVD GPP_E10/USB2_OC1# USB_OC1# <71> STRAP
M29 AJ44 USB_OC2# RH3
RSVD GPP_E11/USB2_OC2# AL41 USB_OC3# 10K_0402_5%
G17 GPP_E12/USB2_OC3# AV47
2
F16 PCIE1_RXN/USB31_7_RXN GPP_F15/USB2_OC4# AR35 USB_OC0# GPD_7
A17 PCIE1_RXP/USB31_7_RXP GPP_F16/USB2_OC5# AR37
PCIE1_TXN/USB31_7_TXN GPP_F17/USB2_OC6# 1
B17 AV43
PCIE1_TXP/USB31_7_TXP GPP_F18/USB2_OC7#
1
R21 CH76
P21 PCIE2_RXN/USB31_8_RXN F4 USB2_RCOMP RH4 1 2 113_0402_1% 0.1U_0201_10V6K RH7
B18 PCIE2_RXP/USB31_8_RXP USB2_COMP F3 USB2_VBUS_SENSE RH5 1 @ 2 0_0402_5% @ 2 10K_0402_5%
2 C18 PCIE2_TXN/USB31_8_TXN USB2_VBUSSENSE U13 @ 2
K18 PCIE2_TXP/USB31_8_TXP RSVD1 G3 USB2_ID RH6 1 @ 2 0_0402_5%
2
J18 PCIE3_RXN/USB31_9_RXN USB2_ID
B19 PCIE3_RXP/USB31_9_RXP BE41 GPD_7
C19 PCIE3_TXN/USB31_9_TXN GPD7
N18 PCIE3_TXP/USB31_9_TXP G45 PCIE_PTX_DRX_P24
PCIE4_RXN/USB31_10_RXN PCIE24_TXP PCIE_PTX_DRX_P24 <68>
R18 G46 PCIE_PTX_DRX_N24
PCIE4_RXP/USB31_10_RXP PCIE24_TXN PCIE_PTX_DRX_N24 <68>
D20 Y41 PCIE_PRX_DTX_P24 M.2 SSD-1 PCIE L3
C20 PCIE4_TXN/USB31_10_TXN PCIE24_RXP Y40 PCIE_PRX_DTX_N24 PCIE_PRX_DTX_P24 <68>
F20 PCIE4_TXP/USB31_10_TXP PCIE24_RXN G48 PCIE_PTX_DRX_P23 PCIE_PRX_DTX_N24 <68>
PCIE5_RXN PCIE23_TXP PCIE_PTX_DRX_P23 <68>
G20 G49 PCIE_PTX_DRX_N23
PCIE5_RXP PCIE23_TXN PCIE_PTX_DRX_N23 <68>
B21 W44 PCIE_PRX_DTX_P23 M.2 SSD-1 PCIE L2
A22 PCIE5_TXN PCIE23_RXP W43 PCIE_PRX_DTX_N23 PCIE_PRX_DTX_P23 <68>
K21 PCIE5_TXP PCIE23_RXN H48 PCIE_PTX_DRX_P22 PCIE_PRX_DTX_N23 <68>
PCIE6_RXN PCIE22_TXP PCIE_PTX_DRX_P22 <68>
J21 H47 PCIE_PTX_DRX_N22
PCIE6_RXP PCIE22_TXN PCIE_PTX_DRX_N22 <68>
D21 U41 PCIE_PRX_DTX_P22 M.2 SSD-1 PCIE L1
C21 PCIE6_TXN PCIE22_RXP U40 PCIE_PRX_DTX_N22 PCIE_PRX_DTX_P22 <68>
B23 PCIE6_TXP PCIE22_RXN F46 PCIE_PTX_DRX_P21 PCIE_PRX_DTX_N22 <68>
PCIE7_TXP PCIE21_TXP PCIE_PTX_DRX_P21 <68>
C23 G47 PCIE_PTX_DRX_N21
PCIE7_TXN PCIE21_TXN PCIE_PTX_DRX_N21 <68>
J24 R44 PCIE_PRX_DTX_P21 M.2 SSD-1 PCIE L0
L24 PCIE7_RXP PCIE21_RXP T43 PCIE_PRX_DTX_N21 PCIE_PRX_DTX_P21 <68>
F24 PCIE7_RXN PCIE21_RXN PCIE_PRX_DTX_N21 <68>
G24 PCIE8_RXN
B24 PCIE8_RXP
C24 PCIE8_TXN 2 OF 13
PCIE8_TXP
CNP-H_BGA874 Rev1.0
@
3 3
The 30 HSIO lanes on PCH-H supports the following configurations:

1. Up to 24 PCIe* Lanes
—A maximum of 16 PCIe* Ports (or devices) can be enabled
‧ When a GbE Port is enabled, the maximum number of PCIe* Ports (or
devices) that can be enabled reduces based off the following:
Max PCIe* Ports (or devices) = 16 - GbE (0 or 1)
— PCIe* Lanes 1-4 (PCIe* Controller #1), 5-8 (PCIe* Controller #2), 9-12 (PCIe*
Controller #3), 13-16 (PCIe* Controller #4), 17-20 (PCIe* Controller #5), and
21-24 (PCIe* Controller #6) can be individually configured
2. Up to 6 SATA Lanes
— A maximum of 6 SATA Ports (or devices) can be enabled
— SATA Lane 0 has the flexibility to be mapped to Flex I/O Lane 16 or 18
— SATA Lane 1 has the flexibility to be mapped to Flex I/O Lane 17 or 19
3. Up to 10 USB 3.1 Lanes
— A maximum of 10 USB 3.1 Ports (or devices) can be enabled
4. Up to 4 GbE Lanes
— A maximum of 1 GbE Port (or device) can be enabled
5. Supports up to 3 Remapped (IntelR Rapid Storage Technology) PCIe* storage
devices
— x2 and x4 PCIe* NVMe SSD
— x2 IntelR Optane? Memory Device
— See the “PCI Express* (PCIe*)” chapter for the PCH PCIe* Controllers,configurations
, and lanes that can be used for IntelR Rapid Storage Technology PCIe* storage support
4
6. For unused SATA/PCIe* Combo Lanes, Flex I/O Lanes that can be configured as PCIe* or SATA, 4
the lanes must be statically assigned to SATA or PCIe* via the SATA/PCIe Combo Port Soft
Straps discussed in the SPI Programming Guide and
through the IntelR Flash Image Tool (FIT) tool.
2017/11/23
Compal Secret Data
2018/09/01 Title
PCH(1/8)DMI/PCIE/USB2
A B C D E
A B C D E
PCH-H XTAL_IN/OUT POR is 24MHz for 571697_CNL_MOW_WW16_2017.pdf CNP-H
remove TP as C5PRH UH1G

XTAL_24M_PCH_OUT 1 EMC@ 2 XTAL_24M_PCH_OUT_R BE33
RH11 33_0402_1% GPP_A16/CLKOUT_48
PCH_CPU_24M_CLK_P D7 Y3
<10> PCH_CPU_24M_CLK_P CLKOUT_CPUNSSC_P CLKOUT_ITPXDP# TP@ TH2
PCH_CPU_24M_CLK_N C6 Y4
<10> PCH_CPU_24M_CLK_N CLKOUT_CPUNSSC# CLKOUT_ITPXDP_P TP@ TH3
1 2 XTAL_24M_PCH_IN 1 EMC@ 2 XTAL_24M_PCH_IN_R
RH8 1M_0402_5% RH9 33_0402_1% PCH_CPU_BCLK_P B8 B6 PCH_CPU_PCIBCLK_N
<10> PCH_CPU_BCLK_P PCH_CPU_BCLK_N CLKOUT_CPUBCLK_P CLKOUT_CPUPCIBCLK# PCH_CPU_PCIBCLK_P PCH_CPU_PCIBCLK_N <10>
C8 A6
<10> PCH_CPU_BCLK_N CLKOUT_CPUBCLK# CLKOUT_CPUPCIBCLK_P PCH_CPU_PCIBCLK_P <10>
YH1
24MHZ_18PF_XRCGB24M000F2P51R0 XTAL_24M_PCH_OUT_R U9 AJ6 CLK_PEG_VGA#
XTAL_24M_PCH_IN_R XTAL_OUT CLKOUT_PCIE_N0 CLK_PEG_VGA CLK_PEG_VGA# <25>
1 U10 AJ7 DGPU 1
XTAL_IN CLKOUT_PCIE_P0 CLK_PEG_VGA <25>
3 1
3 1
18P_0402_50V8J
18P_0402_50V8J
RH10 1 2 60.4_0402_1% XCLK_BIASREF T3 AH9 CLK_PCIE_LAN#
NC NC XCLK_BIASREF CLKOUT_PCIE_N1 CLK_PCIE_LAN CLK_PCIE_LAN# <51>
AH10 GLAN
CLKOUT_PCIE_P1 CLK_PCIE_LAN <51>
CH5
CH6
XCLK_BIASREF (PDG) PCH_RTCX1 BA49
4 2 Trace Width/Space: 15mil /15 mil PCH_RTCX2 BA48 RTCX1 AE14 CLK_PCIE_W LAN#
Max Trace Length: 1000 mil RTCX2 CLKOUT_PCIE_N2 CLK_PCIE_W LAN CLK_PCIE_W LAN# <52>
AE15 NGFF WL+BT(KEY E)
8/24 VGA_CLKREQ# CLKOUT_PCIE_P2 CLK_PCIE_W LAN <52>
<25> VGA_CLKREQ# BF31
LAN_CLKREQ# BE31 GPP_B5/SRCCLKREQ0# AE6 CLK_PCIE_NGFF1#
<51> LAN_CLKREQ# GPP_B6/SRCCLKREQ1# CLKOUT_PCIE_N3 CLK_PCIE_NGFF1# <68>
W LAN_CLKREQ# AR32 AE7 CLK_PCIE_NGFF1 M2-1 SSD
<52> W LAN_CLKREQ# GPP_B7/SRCCLKREQ2# CLKOUT_PCIE_P3 CLK_PCIE_NGFF1 <68>
SSD1_CLKREQ# BB30
<68> SSD1_CLKREQ# GPP_B8/SRCCLKREQ3#
TBT_CLKREQ# BA30 AC2 CLK_PCIE_TBT#
<43> TBT_CLKREQ# GPP_B9/SRCCLKREQ4# CLKOUT_PCIE_N4 CLK_PCIE_TBT# <43>
PCH_RTCX1 SSD2_CLKREQ# AN29 AC3 CLK_PCIE_TBT TBT
<68> SSD2_CLKREQ# GPP_B10/SRCCLKREQ5# CLKOUT_PCIE_P4 CLK_PCIE_TBT <43>
AE47
PCH_RTCX2 AC48 GPP_H0/SRCCLKREQ6# AB2 CLK_PCIE_NGFF2#
GPP_H1/SRCCLKREQ7# CLKOUT_PCIE_N5 CLK_PCIE_NGFF2 CLK_PCIE_NGFF2# <68>
AE41 AB3 M2-2 SSD
GPP_H2/SRCCLKREQ8# CLKOUT_PCIE_P5 CLK_PCIE_NGFF2 <68>
1 2 AF48
RH12 10M_0402_5% Raptor AC41 GPP_H3/SRCCLKREQ9#
GPP_H4/SRCCLKREQ10# CLKOUT_PCIE_N6
W4
AC39 W3
AE39 GPP_H5/SRCCLKREQ11# CLKOUT_PCIE_P6
AB48 GPP_H6/SRCCLKREQ12# W7
YH2
1 2 AC44 GPP_H7/SRCCLKREQ13# CLKOUT_PCIE_N7 W6
AC43 GPP_H8/SRCCLKREQ14# CLKOUT_PCIE_P7
GPP_H9/SRCCLKREQ15# Raptor
10P_0402_50V8J
10P_0402_50V8J
1 1 AC14
V2 CLKOUT_PCIE_N8 AC15
32.768KHZ_9PF_X1A000141000200
V3 CLKOUT_PCIE_N15 CLKOUT_PCIE_P8
CLKOUT_PCIE_P15
CH7
CH8
U2
2 Trace Space: 15 mil 2 T2 CLKOUT_PCIE_N9 U3
Max Trace Length: 1000 mil T1 CLKOUT_PCIE_N14 CLKOUT_PCIE_P9
2 CLKOUT_PCIE_P14 AC9 2
AA1 CLKOUT_PCIE_N10 AC11
Y2 CLKOUT_PCIE_N13 CLKOUT_PCIE_P10
CLKOUT_PCIE_P13 AE9
use same part w C5MMH AC7 CLKOUT_PCIE_N11 AE11
+3VS
+3VS Raptor AC6 CLKOUT_PCIE_N12
CLKOUT_PCIE_P12 7 OF 13
CLKOUT_PCIE_P11
REFCLK_CNV
R6
CLKIN_XTAL REFCLK_CNV <52>
CNP-H_BGA874 Rev1.0
1
RH217 1 2 10K_0402_5% LAN_CLKREQ# @
RH14
RH218 1 2 10K_0402_5% VGA_CLKREQ# RH221 1 2 10K_0402_5% SSD2_CLKREQ# 10K_0402_5%
RH219 1 2 10K_0402_5% W LAN_CLKREQ# RH222 1 2 10K_0402_5% TBT_CLKREQ#
2
RH220 1 2 10K_0402_5% SSD1_CLKREQ#
CNP-H
UH1M
AW13 BD4 CLK_CNV_PRX_DTX_N

GPP_G0/SD_CMD CNV_WR_CLKN CLK_CNV_PRX_DTX_N <52>
BE9 BE3 CLK_CNV_PRX_DTX_P
For DDX03 R02 GPP_G1/SD_DATA0 CNV_WR_CLKP CLK_CNV_PRX_DTX_P <52>
BF8
BF9 GPP_G2/SD_DATA1 BB3 CNV_PRX_DTX_N0
XTAL Frequency Select GPP_G3/SD_DATA2 CNV_WR_D0N CNV_PRX_DTX_N0 <52>
BG8 BB4 CNV_PRX_DTX_P0
+1.8VALW _PRIM GPP_G4/SD_DATA3 CNV_WR_D0P CNV_PRX_DTX_N1 CNV_PRX_DTX_P0 <52>
remove SD signal from PCH BE8 BA3
GPP_G5/SD_CD# CNV_WR_D1N CNV_PRX_DTX_P1 CNV_PRX_DTX_N1 <52>
BD8 BA2
GPP_G6/SD_CLK CNV_WR_D1P CNV_PRX_DTX_P1 <52>
AV13
GPP_G7/SD_WP BC5 CLK_CNV_PTX_DRX_N
3 CNV_WT_CLKN CLK_CNV_PTX_DRX_N <52> 3
RH15 1 2 4.7K_0402_5% CNV_BRI_PTX_DRX AP3 BB6 CLK_CNV_PTX_DRX_P
GPP_I11/M2_SKT2_CFG0 CNV_WT_CLKP CLK_CNV_PTX_DRX_P <52>
AP2
AN4 GPP_I12/M2_SKT2_CFG1 BE6 CNV_PTX_DRX_N0
This signal has a weak internal pull-down 20K. STRAP GPP_I13/M2_SKT2_CFG2 3.3V CNV_WT_D0N CNV_PTX_DRX_N0 <52>
AM7 BD7 CNV_PTX_DRX_P0
0 = 38.4/19.2MHz XTAL frequency selected. remove CPU_C10_GATE# GPP_I14/M2_SKT2_CFG3 CNV_WT_D0P BG6 CNV_PTX_DRX_N1
CNV_PTX_DRX_P0 <52>
1 = 24MHz XTAL frequency selected. (DDX03) CNV_WT_D1N CNV_PTX_DRX_N1 <52>
Notes: AV6 BF6 CNV_PTX_DRX_P1
GPP_J0/CNV_PA_BLANKING CNV_WT_D1P CNV_PTX_DRX_P1 <52>
1. The internal pull-down is disabled after RSMRST# AY3 BA1 CNV_W T_RCOMP RH16 1 2 150_0402_1%
de-asserts. AR13 GPP_J1/CPU_C10_GATE# CNV_WT_RCOMP
2. This signal is in the primary well. AV7 GPP_J11/A4WP_PRESENT B12 PCIE_RCOMPN RH17 1 2 100_0402_1%
AW3 GPP_J10 PCIE_RCOMPN A13 PCIE_RCOMPP
AT10 GPP_J_2 1.8V PCIE_RCOMPP BE5 SD_RCOMP_1P8 RH18 1 2 200_0402_1%
+1.8VALW _PRIM CNV_BRI_PTX_DRX AV4 GPP_J_3 SD_1P8_RCOMP BE4 SD_RCOMP_3P3 RH19 1 2 200_0402_1%
VCCPSPI Select <52> CNV_BRI_PTX_DRX CNV_BRI_PRX_DTX AY2 GPP_J4/CNV_BRI_DT/UART0B_RTS# SD_3P3_RCOMP BD1
checked CRB
<52> CNV_BRI_PRX_DTX CNV_RGI_PTX_DRX GPP_J5/CNV_BRI_RSP/UART0B_RXD GPPJ_RCOMP_1P81 GPPJ_RCOMP_1P8 RH20 1
BA4 BE1 2 200_0402_1%
<52> CNV_RGI_PTX_DRX CNV_RGI_PRX_DTX GPP_J6/CNV_RGI_DT/UART0B_TXD GPPJ_RCOMP_1P82
AV3 BE2
<52> CNV_RGI_PRX_DTX GPP_J7/CNV_RGI_RSP/UART0B_CTS# GPPJ_RCOMP_1P83
@ GPP_J9 AW2
RH21 1 2 4.7K_0402_5% GPP_J9 GPP_J8/CNV_MFUART2_RXD
AU9 Y35
The signal has a weak internal pull-down 20K GPP_J9/CNV_MFUART2_TXD RSVD2 Y36
STRAP RSVD3
0 = VCCPSPI is connected to 3.3V rail
1 = VCCPSPI is connected to 1.8V rail BC1
Note: If VCCPSPI is connected to 1.8V rail, this pin +1.8VALW _PRIM 13 OF 13 RSVD1 AL35
strap must be a ‘1’ for the proper functionality TP TP@ TH4
of the SPI (Flash) I/Os #571483_CFL_H_RVP_CRB_TDK_Rev0p5
CNP-H_BGA874 Rev1.0
Recommend external test point
+1.8VALW _PRIM RH181 1 CNVI@ 2 20K_0402_1% CNV_BRI_PRX_DTX @
M.2 CNV Mode Select
RH182 1 CNVI@ 2 20K_0402_1% CNV_RGI_PRX_DTX
571391_CFL_H_PDG_Rev0p71
To avoid floating input at the I/O pin BRI_RSP and RGI_RSP it is recommended to add
RH22 2 1 10K_0402_5% CNV_RGI_PTX_DRX a weak pull up resistor to the SoC pin with a recommended value of 20K ohm.
4 4
STRAP
RH23 2 @ 1 10K_0402_5%
An external pull-up or pull-down is required.
0 = Integrated CNVi enable.
1 = Integrated CNVi disable.
Pulled down by CRF CNVi RGI_DT pin Security Classification
2017/11/23
Compal Secret Data
2018/09/01 Title
PCH(2/8)CLK/CNVI/SD
A B C D E
A
CNP-H Raptor
Raptor: for GC 3.0 UH1E
AL13
GPP_I5/DDPB_CTRLCLK AR8 RX3
DP0_HPD_PCH RT881 1 @ 2 0_0402_5% AT6 GPP_I6/DDPB_CTRLDATA AN13 0_0402_5%
<39> DP0_HPD_PCH HDMI_HPD_PCH GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I7/DDPC_CTRLCLK CPU_EDP_HPD_R EDP_HPD_R
<40> HDMI_HPD_PCH AN10 AL10 1 @ 2 EDP_HPD_R <38>
CCG4_HOTPLUG_DET_3V3 RT880 1 @ 2 0_0402_5% AP9 GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I8/DDPC_CTRLDATA AL9
<49> CCG4_HOTPLUG_DET_3V3 TBT_DP4_HPD GPP_I2/DDPD_HPD2/DISP_MISC2 GPP_I9/DDPD_CTRLCLK
RT879 1 @ 2 0_0402_5% AL15 AR3
<42,43> TBT_DP4_HPD GPP_I3/DDPF_HPD3/DISP_MISC3 GPP_I10/DDPD_CTRLDATA
1
AN40
GPP_F23/DDPF_CTRLDATA AT49 RX4
GPP_F22/DDPF_CTRLCLK
100K_0402_5%
AP41
CPU_EDP_HPD_R AN6 GPP_F14/PS_ON#
can remove if no use DP
2
GPP_I4/EDP_HPD/DISP_MISC4
08/18 M45
GPP_K23/IMGCLKOUT1 L48
GPP_K22/IMGCLKOUT0 T45
remove PCH DP SCLK/SDATA GPP_K21 T46
5 OF 13 GPP_K20 AJ47
DDP[B..F]CTRLDATA GPP_H23/TIME_SYNC0 TBT_CIO_PLUG_EVENT# <43>
This signal has a weak internal Pull-down. CNP-H_BGA874 Rev1.0
0 = Port B~D is not detected. intel critical net recommend
1 = Port B,C,D is detected. (Default) @
RH198 1 2 100K_0201_5%
Notes:
1. The internal Pull-down is disabled after
CNP-H
Raptor TBT
PCH_PWROK de-asserts.
2. This signal is in the primary well. UH1A PLT_RST# CH9 1 2 100P_0402_50V8J
1 @ 2 EC_PME#_R BE36 AV29 PLT_RST#
<51,58> EC_PME# GPP_A11/PME#/SD_VDD2_PWR_EN# GPP_B13/PLTRST# PLT_RST# <58>
RH24 0_0402_5% XEMC@
R15 Y47
R13 RSVD2 GPP_K16/GSXCLK Y46 GPIO Serial Expander (GSX) is the capability
* wait confirm CG7 RSVD1 GPP_K12/GSXDOUT provided by the PCH to expand the GPIOs
PDG P348 quad mode support PH1K CRB connect GND Y48
GPP_K13/GSXSLOAD W46 on a platform that needs more GPIOs than the
CRB PU 20k GPP_K14/GSXDIN ones provided by the PCH.
+3VALW _SPI #571182_CFL_PCH_EDS_Rev1.0 recommend 100k RH186 1 @ 2 0_0402_5% AL37 AA45
#571391_CFL_H_PDG_Rev0p71 AN35 VSS GPP_K15/GSXSRESET#
TH6 TP@ TP
RH25 2 1 1K_0402_5% PCH_SPI_IO2 PCH_SPI_SI AU41 AL47
PCH_SPI_SO BA45 SPI0_MOSI GPP_E3/CPU_GP0 AM45
RH26 2 1 1K_0402_5% PCH_SPI_IO3 PCH_SPI_CS#0 AY47 SPI0_MISO GPP_E7/CPU_GP1 BF32 TP_INT# 2 1 +3VS
PCH_SPI_CLK SPI0_CS0# GPP_B3/CPU_GP2 TYPEC_1P5A DH1 EC_TP_INT# <58,63>
AW47 BC33
SPI0_CLK GPP_B4/CPU_GP3 TYPEC_1P5A <45,49>
AW48 RB751V-40_SOD323-2
RH27 2 1 1K_0402_5%PCH_SPI_SI SPI0_CS1# AE44 TP_INT# RH28 2 1 100K_0402_5%
PCH_SPI_IO2 AY48 GPP_H18/SML4ALERT# AJ46 TBT_FORCE_PW R
+3VALW _PCH_PRIM PCH_SPI_IO3 SPI0_IO2 GPP_H17/SML4DATA RTD3_CIO_PW R_EN TBT_FORCE_PW R <43>
BA46 AE43
SPI0_IO3 GPP_H16/SML4CLK GPP_H15 RTD3_CIO_PW R_EN <43>
AT40 AC47
RH29 2 1 100K_0402_5% GPP_H15 STRAP SPI0_CS2# GPP_H15/SML3ALERT# AD48
BE19 GPP_H14/SML3DATA AF47 Raptor TBT
#571182_CNL_PCH_H_EDS_V1_Rev0.7
External pull-up is required. Recommend 100K if pulled Raptor BF19 GPP_D1/SPI1_CLK/SBK1_BK1
GPP_D0/SPI1_CS#/SBK0_BK0
GPP_H13/SML3CLK
GPP_H12/SML2ALERT#
AB47 GPP_H12
GPP_H12 <19> +RTCVCC
up to 3.3V or 75K if pulled up to 1.8V. BF18 AD47
BE18 GPP_D3/SPI1_MOSI/SBK3_BK3 GPP_H11/SML2DATA AE48
571007_CFL_MOW_Archive_WW22_2017
STUFF R on GPP_H15 BC17 GPP_D2/SPI1_MISO/SBK2_BK2 GPP_H10/SML2CLK
PCH_HDD_PW RGT BD17 GPP_D22/SPI1_IO3 1 OF 13 BB44 SM_INTRUDER# 1M_0402_5% 2 1 RH30
TH50 TP@ GPP_D21/SPI1_IO2 INTRUDER#
CNP-H_BGA874 Rev1.0 RVP: 330K
A 1 M pull-up is used on the customer reference
1 @ board (CRB). This is needed to reduce leakage 1
from Coin Cell Battery in G3 state.
PCH_SPI_CLK RH195 1 @ 2 100K_0201_5%
intel critical net recommend
SPI ROM ( 16MByte )

+3VALW _SPI
+3VALW _SPI
CH10 0.1U_0201_10V6K
UH2 PCH_SPI_CS#0
1 2 1 @ 2
PCH_SPI_CS#0 1 8 RH31 4.7K_0402_5% PCH PLTRST Buffer RH32 1 @ 2 0_0402_5%
PCH_SPI_SO_0_R 2 /CS VCC 7 PCH_SPI_IO3_0_R
PCH_SPI_IO2_0_R 3 DO(IO1) /HOLD(IO3) 6 PCH_SPI_CLK_0_R +3VS
4 /WP(IO2) CLK 5 PCH_SPI_SI_0_R
GND DI(IO0)
W 25Q128FVSIQ_SO8 1
CH11 2
P/N: SA00005VV20 .1U_0402_16V7K
PCH_SPI_SI_0_R RH107 1 2 33_0402_1% PCH_SPI_SI
5
PCH_SPI_SO_0_R RH108 1 2 33_0402_1% PCH_SPI_SO UH3
@ @ PCH_SPI_IO3_0_R RH109 1 2 33_0402_1% PCH_SPI_IO3 PLT_RST# 1
P
PCH_SPI_CLK_0_R 1 2 1 2 PCH_SPI_CLK_0_R RH110 1 2 33_0402_1% PCH_SPI_CLK B 4
PCH_SPI_IO2_0_R PCH_SPI_IO2 Y PLT_RST_BUF# <25,43,49,51,52,68>
RH111 1 2 33_0402_1% 2
A
G
RH33 CH12
0_0402_5% 68P_0402_50V8J intel PDG 1.8 TC7SH08FU_SSOP5
3
33 ohm for 3.3V for singel load
place 500 mil from PCH
note : 1050 Use 8M rom
2017/11/23
Compal Secret Data
2018/09/01 Title
PCH(3/8)DDC/SPI
A
A B C D E
#571391_CFL_H_PDG_Rev0p5
‧ eSPI clock and eSPI data mismatched: <500 mils.
‧ eSPI clock and eSPI chip select mismatched: <500 mils.
‧ eSPI signal maximum 9 Vias
* If DATA signals are entirely routed on MS, stuff the resistor with 15 Ohm.
CNP-H
UH1F
F9 BB39 LPC_AD0
<71> USB3_PTX_DRX_N1 USB31_1_TXN GPP_A1/LAD0/ESPI_IO0 LPC_AD1 LPC_AD0 <58>
F7 1.8V AW37 LPC Bus check straps
<71> USB3_PTX_DRX_P1 USB31_1_TXP (eSPI) GPP_A2/LAD1/ESPI_IO1 LPC_AD2 LPC_AD1 <58>
USB3 MB <71> USB3_PRX_DTX_N1 D11 AV37
USB31_1_RXN GPP_A3/LAD2/ESPI_IO2 LPC_AD3 LPC_AD2 <58>
<71> USB3_PRX_DTX_P1 C11 BA38 LPC : +3.3V
USB31_1_RXP GPP_A4/LAD3/ESPI_IO3 LPC_AD3 <58>
C3
<47> USB3_PTX_DRX_N2 USB31_2_TXN LPC_FRAME#
D4 BE38
<47> USB3_PTX_DRX_P2 USB31_2_TXP GPP_A5/LFRAME#/ESPI_CS0# TPM_SERIRQ LPC_FRAME# <58>
1 USB3 NV TypeC <47> USB3_PRX_DTX_N2 B9 AW35 TPM_SERIRQ <58> +3VS 1
C9 USB31_2_RXN GPP_A6/SERIRQ/ESPI_CS1# BA36 LPC_PIRQA#
<47> USB3_PRX_DTX_P2 USB31_2_RXP GPP_A7/PIRQA#/ESPI_ALERT0# BE39 KBRST#
C17 GPP_A0/RCIN#/ESPI_ALERT1# BF38 ESPI_RST#
USB31_6_TXN GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RST# <58> TPM_SERIRQ
C16 2 1 RH37
G14 USB31_6_TXP BB36 CLK_LPC RH35 2 1 22_0402_5%
USB31_6_RXN GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_LPC_R <58> 10K_0402_5%
F14 BB34
C15 USB31_6_RXP GPP_A10/CLKOUT_LPC1
B15 USB31_5_TXN T48
J13 USB31_5_TXP GPP_K19/SMI# T47 LPC_PIRQA# 1 2 RH38
K13 USB31_5_RXN GPP_K18/NMI#
USB31_5_RXP Raptor 10K_0402_5%
G12 AH40
<73> USB3_PTX_DRX_P3 USB31_3_TXP GPP_E6/SATA_DEVSLP2 SSD_DEVSLP1
F11 AH35
<73> USB3_PTX_DRX_N3 USB31_3_TXN GPP_E5/SATA_DEVSLP1 SSD_DEVSLP1 <68>
USB3 SUB <73> USB3_PRX_DTX_P3 C10 AL48 KBRST# 1 2 RH248
B10 USB31_3_RXP GPP_E4/SATA_DEVSLP0 AP47
<73> USB3_PRX_DTX_N3 USB31_3_RXN GPP_F9/SATA_DEVSLP7
CONFIRM WITH SW 10K_0402_5%
AN37
C14 GPP_F8/SATA_DEVSLP6 AN46
B14 USB31_4_TXP GPP_F7/SATA_DEVSLP5 AR47 SSD_DEVSLP4
USB31_4_TXN GPP_F6/SATA_DEVSLP4 SSD_DEVSLP4 <68>
J15 AP48
K16 USB31_4_RXP 6 OF 13GPP_F5/SATA_DEVSLP3
USB31_4_RXN
CONFIRM WITH SW
CNP-H_BGA874 Rev1.0
@
Raptor
CNP-H
2 UH1C 2
CL_CLK AR2 G36 PCIE_PRX_DTX_N9
TH10 TP@ CL_CLK PCIE9_RXN PCIE_PRX_DTX_N9 <68>
CL_DATA AT5 F36 PCIE_PRX_DTX_P9
For Intel CLINK TH11 TP@ CL_DATA PCIE9_RXP PCIE_PRX_DTX_P9 <68>
CL_RST# AU4 C34 PCIE_PTX_DRX_N9 M.2 SSD-1 PCIE L3
TH12 TP@ CL_RST# PCIE9_TXN PCIE_PTX_DRX_N9 <68>
D34 PCIE_PTX_DRX_P9
P48 PCIE9_TXP PCIE_PTX_DRX_P9 <68>
V47 GPP_K8
V48 GPP_K9 K37 PCIE_PRX_DTX_N10
W47 GPP_K10 PCIE10_RXN J37 PCIE_PRX_DTX_P10 PCIE_PRX_DTX_N10 <68>
GPP_K11 PCIE10_RXP C35 PCIE_PTX_DRX_N10 PCIE_PRX_DTX_P10 <68>
PCIE10_TXN PCIE_PTX_DRX_N10 <68>
M.2 SSD-1 PCIE L2
L47 B35 PCIE_PTX_DRX_P10
L46 GPP_K0 PCIE10_TXP PCIE_PTX_DRX_P10 <68>
U48 GPP_K1 F44 PCIE_PRX_DTX_N15
U47 GPP_K2 PCIE15_RXN/SATA2_RXN E45 PCIE_PRX_DTX_P15 PCIE_PRX_DTX_N15 <52>
GPP_K3 PCIE15_RXP/SATA2_RXP PCIE_PRX_DTX_P15 <52> NGFF
N48 B40 PCIE_PTX_DRX_N15
N47 GPP_K4 PCIE_15_SATA_2_TXN C40 PCIE_PTX_DRX_P15 PCIE_PTX_DRX_N15 <52> WL+BT(KEY E)
P47 GPP_K5 PCIE15_TXP/SATA2_TXP PCIE_PTX_DRX_P15 <52>
R46 GPP_K6 L41
GPP_K7 PCIE16_RXN/SATA3_RXN M40
C36 PCIE16_RXP/SATA3_RXP B41
<68> PCIE_PTX_DRX_P11 B36 PCIE11_TXP/SATA0A_TXP PCIE16_TXN/SATA3_TXN C41
<68> PCIE_PTX_DRX_N11 F39 PCIE11_TXN/SATA0A_TXN PCIE16_TXP/SATA3_TXP
M.2 SSD-1 PCIE L1 <68> PCIE_PRX_DTX_P11 PCIE11_RXP/SATA0A_RXP
G38 K43 PCIE_PRX_DTX_N17
<68> PCIE_PRX_DTX_N11 PCIE11_RXN/SATA0A_RXN PCIE17_RXN/SATA4_RXN K44 PCIE_PRX_DTX_P17 PCIE_PRX_DTX_N17 <43>
AR42 PCIE17_RXP/SATA4_RXP A42 PCIE_PTX_DRX_N17 PCIE_PRX_DTX_P17 <43>
GPP_F10/SATA_SCLOCK PCIE17_TXN/SATA4_TXN PCIE_PTX_DRX_N17 <43>
TBT PCIE L0
AR48 B42 PCIE_PTX_DRX_P17
Raptor DGPU_PRSNT# AU47 GPP_F11/SATA_SLOAD
GPP_F13/SATA_SDATAOUT0
PCIE17_TXP/SATA4_TXP
PCIE_PRX_DTX_N18
PCIE_PTX_DRX_P17 <43>
+3VS
AU46 P41
GPP_F12/SATA_SDATAOUT1 PCIE18_RXN/SATA5_RXN R40 PCIE_PRX_DTX_P18 PCIE_PRX_DTX_N18 <43>
3 PCIE_PTX_DRX_N14 C39 PCIE18_RXP/SATA5_RXP C42 PCIE_PTX_DRX_N18 PCIE_PRX_DTX_P18 <43> 3
<51> PCIE_PTX_DRX_N14 PCIE14_TXN/SATA1B_TXN PCIE18_TXN/SATA5_TXN PCIE_PTX_DRX_N18 <43>
TBT PCIE L1
PCIE_PTX_DRX_P14 D39 D42 PCIE_PTX_DRX_P18
<51> PCIE_PTX_DRX_P14 PCIE_PRX_DTX_N14 PCIE14_TXP/SATA1B_TXP PCIE18_TXP/SATA5_TXP PCIE_PTX_DRX_P18 <43>
GLAN D46
<51> PCIE_PRX_DTX_N14 PCIE_PRX_DTX_P14 PCIE14_RXN/SATA1B_RXN
C47 AK48
<51> PCIE_PRX_DTX_P14 PCIE14_RXP/SATA1B_RXP GPP_E8/SATA_LED#
B38 AH41
C38 PCIE13_TXN/SATA0B_TXN GPP_E0/SATAXPCIE0/SATAGP0 AJ43 SATA_GP1
C45 PCIE13_TXP/SATA0B_TXP GPP_E1/SATAXPCIE1/SATAGP1 AK47 SATA_GP1 <68> SATA_GP1 RH201 2 1 10K_0402_5%
C46 PCIE13_RXN/SATA0B_RXN GPP_E2/SATAXPCIE2/SATAGP2 AN47 RH187 1 @ 2 10K_0402_5%
PCIE13_RXP/SATA0B_RXP GPP_F0/SATAXPCIE3/SATAGP_3 AM46
GPP_F1/SATAXPCIE4/SATAGP4 M.2 SSD PCIE/SATA select pin
E37 AM43 SATA_GP5 CONFIRM WITH SW
<68> PCIE_PTX_DRX_P12 PCIE12_TXP/SATA1A_TXP GPP_F2/SATAXPCIE5/SATAGP5 TP@ TH13
D38 AM47
<68> PCIE_PTX_DRX_N12 J41 PCIE12_TXN/SATA1A_TXN GPP_F3/SATAXPCIE6/SATAGP6 AM48
M.2 SSD-1 PCIE L0 <68> PCIE_PRX_DTX_P12 PCIE12_RXP/SATA_1A_RXP GPP_F4/SATAXPCIE7/SATAGP7
H42 @ DIS only
<68> PCIE_PRX_DTX_N12 PCIE12_RXN/SATA1A_RXN AU48 RH254 1 @ 2 100K_0402_5%
B44 GPP_F21/EDP_BKLTCTL AV46 RH255 1 @ 2 100K_0402_5%
<43> PCIE_PTX_DRX_P20 A44 PCIE20_TXP/SATA7_TXP GPP_F20/EDP_BKLTEN AV44 RH256 1 2 100K_0402_5%
<43> PCIE_PTX_DRX_N20 R37 PCIE20_TXN/SATA7_TXN GPP_F19/EDP_VDDEN
<43> PCIE_PRX_DTX_P20 PCIE20_RXP/SATA7_RXP #571391_CFL_H_PDG_Rev0p5.pdf
TBT PCIE L3 R35 AD3 PCH_THERMTRIP# RH40 1 2 620_0402_5%
<43> PCIE_PRX_DTX_N20 PCIE20_RXN/SATA7_RXN THRMTRIP# PCH_PECI PCH_THERMTRIP#_R <10>
D43 AF2 RH41 1 @ 2 13_0402_5% H_PECI
<43> PCIE_PTX_DRX_P19 PCIE19_TXP/SATA6_TXP PECI H_PM_SYNC H_PECI <10,58>
C44 AF3 RH42 1 2 30_0402_5% H_PM_SYNC_R
<43> PCIE_PTX_DRX_N19 PCIE19_TXN/SATA6_TXN PM_SYNC H_PLTRST_CPU# H_PM_SYNC_R <10>
N42 AG5
+3VALW _PCH_PRIM <43> PCIE_PRX_DTX_P19 PCIE19_RXP/SATA6_RXP 3 OF 13 PLTRST_CPU# H_PM_DOW N_R H_PLTRST_CPU# <10>
TBT PCIE L2 M44 AE2
<43> PCIE_PRX_DTX_N19 PCIE19_RXN/SATA6_RXN PM_DOWN H_PM_DOW N_R <10>
CNP-H_BGA874 Rev1.0
1
@
RH43 XEMC@
4
10K_0402_5% @
Vinafix.com H_PECI .1U_0402_16V7K 1 2 CH50
4
2
DGPU_PRSNT#
GPP_F13 Security Classification Compal Secret Data Compal Electronics, Inc.

1
RH44 DGPU_PRSNT# 2017/11/23 2018/09/01 Title

VGA@
10K_0402_5%
DIS,Optimus 0 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCIE/SATA/USB3/eSPI
2
Custom 0.1
UMA 1 Raptor DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A B C D E
A B C D E
+1.2V_VDDQ
<58> ME_EN 1 @ 2
RH45 0_0402_5%
2
RH226 1 2 33_0402_5% HDA_RST#
<56> HDA_RST#_R
RH46
RH227 1 2 33_0402_5% HDA_BIT_CLK 470_0402_1%
<56> HDA_BIT_CLK_R
RH228 1 2 33_0402_5% HDA_SDOUT
<56> HDA_SDOUT_R
1
DRAM_RESET# 1 2
HDA_SYNC DDR_DRAMRST#_R <23,24>
RH229 1 2 33_0402_5% RH47 0_0402_5%
<56> HDA_SYNC_R
Raptor
2 1 @
1 CH13 1U_0201_6.3V6M 1
100K_0201_5% 2 1RH196 HDA_BIT_CLK CNP-H
100K_0201_5% 2 1RH197 HDA_RST# UH1D
HDA_BIT_CLK BD11 BF36
HDA_SDIN0 BE11 HDA_BCLK/I2S0_SCLK GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF# AV32 PM_CLKRUN#
intel critical net recommend <56> HDA_SDIN0 HDA_SDOUT BF12 HDA_SDI0/I2S0_RXD GPP_A8/CLKRUN# Raptor TBT
HDA_SYNC BG13 HDA_SDO/I2S0_TXD BF41 LAN_DISABLE_N
HDA_SYNC/I2S0_SFRM GPD11/LANPHYPC TP@ TH14
del RF reserve cap on HDA HDA_RST# BE10 BD42 SLP_W LAN#
HDA_RST#/I2S1_SCLK GPD9/SLP_WLAN# TP@ TH15
BF10
BE12 HDA_SDI1/I2S1_RXD BB46 DRAM_RESET#
BD12 I2S1_TXD/SNDW2_DATA DRAM_RESET# BE32 PCH_VRALERT#
I2S1_SFRM/SNDW2_CLK GPP_B2/VRALERT# BF33 TYPEC_3A
GPP_B1/GSPI1_CS1#/TIME_SYNC1 TYPEC_3A <45,49>
BE29
<6> CPU_DISPA_SDO_R
RH48 1 2 30_0402_5% CPU_DISPA_SDO
CPU_DISPA_SDI_R
AM2
HDACPU_SDO
GPP_B0/GSPI0_CS1#
GPP_K17/ADR_COMPLETE
R47 PCH_GPP_K17
PCH_GPP_B11
TP@ TH19 Raptor TBT
AN3 AP29 TP@ TH20
<6> CPU_DISPA_SDI_R RH49 1 CPU_DISPA_BCLK HDACPU_SDI GPP_B11/I2S_MCLK SYS_PW ROK
2 30_0402_5% AM3 AU3 SYS_PW ROK <58,78>
<6> CPU_DISPA_BCLK_R HDACPU_SCLK SYS_PWROK
FOR Jefferson Peak RESET pin is glitch free,it AV18 BB47 W AKE# RH203 1 @ 2 0_0402_5%
GPP_D8/I2S2_SCLK WAKE# PM_SLP_A# TBT_PCIE_W AKE_N <43>
AW18 BE40
is recommended that a pull-down resistor of 75K CLKREQ_CNV# BA17 GPP_D7/I2S2_RXD GPD6/SLP_A# BF40 SLP_LAN#
TP@ TH37
ohm on GPP_D5(CNV_RF_RESET#) <52> CLKREQ_CNV# GPP_D6/I2S2_TXD/MODEM_CLKREQ SLP_LAN# TP@ TH21
CNV_RF_RESET# BE16 BC28 PM_SLP_S0#
<52> CNV_RF_RESET# GPP_D5/I2S2_SFRM/CNV_RF_RESET# GPP_B12/SLP_S0# PM_SLP_S3# PM_SLP_S0# <58>
<56> PCH_DMIC_DATA0 BF15 BF42
GPP_D20/DMIC_DATA0/SNDW4_DATA 1.8V GPD4/SLP_S3# PM_SLP_S4# PM_SLP_S3# <58,78>
BD16 BE42
<56> PCH_DMIC_CLK0 GPP_D19/DMIC_CLK0/SNDW4_CLK GPD5/SLP_S4# PM_SLP_S5# PM_SLP_S4# <58,78>
+RTCVCC TH22 TP@ AV16 BC42 TP@ TH23
AW15 GPP_D18/DMIC_DATA1/SNDW3_DATA GPD10/SLP_S5#
TH24 TP@ GPP_D17/DMIC_CLK1/SNDW3_CLK
PCH_SRTCRST# BE45 SUSCLK
RH50 1 2 20K_0402_1% GPD8/SUSCLK PM_BATLOW # SUSCLK <52,68>
BF44 RH261 1 @ 2 0_0402_5%
GPD0/BATLOW# SUSACK#_R TBT_BATLOW # <19,43>
BE35 TP@ T207
CH18 1 2 1U_0201_6.3V6M PCH_RTCRST# GPP_A15/SUSACK#
2 BE47 BC37 1 @ 2 2
<58> PCH_RTCRST# PCH_SRTCRST# RTCRST# GPP_A13/SUSWARN#/SUSPWRDNACK SUSPW RDNACK <58>
CLR ME BD46 RH51 0_0402_5%
SRTCRST#
Delay 18~25 ms
PCH_PW ROK AY42 BG44 LAN_W AKE#
<58,78> PCH_PW ROK PCH_PWROK GPD2/LAN_WAKE#
RH52 1 2 20K_0402_1% PCH_RTCRST# EC_RSMRST# BA47 BG42 AC_PRESENT_R 1 @ 2 AC_PRESENT
<58> EC_RSMRST# RSMRST# GPD1/ACPRESENT AC_PRESENT <58>
BD39 SLP_SUS# RH53
SLP_SUS# TP@ 0_0402_5% --No Support Deep Sx
BE46 PBTN_OUT#_R 1 2
@ T208 PBTN_OUT#
GPD3/PWRBTN# PBTN_OUT# <58>
CH19 1 2 1U_0201_6.3V6M PCH_DPW ROK AW41 AU2 SYS_RESET# RH54 0_0402_5%
PCH_SMBALERT# BE25 DSW_PWROK SYS_RESET# AW29 PCH_SPKR
ECLR CMOS <19> PCH_SMBALERT# GPP_C2/SMBALERT# GPP_B14/SPKR PCH_SPKR <19,56>
JCMOS1 1 @ 2 0_0603_5% Delay 18~25 ms PCH_SMBCLK BE26 AE3 H_CPUPW RGD
PCH_SMBDATA GPP_C0/SMBCLK CPUPWRGD H_CPUPW RGD <10>
BF26
PCH_SML0ALERT# BF24 GPP_C1/SMBDATA AL3 XDP_ITP_PMODE
<19> PCH_SML0ALERT# GPP_C5/SML0ALERT# ITP_PMODE TP@ T209
PCH_SML0CLK BF25 AH4 CPU_XDP_TCK0
GPP_C3/SML0CLK PCH_JTAGX CPU_XDP_TCK0 <10>
PCH_SML0DATA BE24 AJ4 CPU_XDP_TMS
PCH_SML1ALERT# BD33 GPP_C4/SML0DATA PCH_JTAG_TMS AH3 CPU_XDP_TDO CPU_XDP_TMS <10>
<19> PCH_SML1ALERT# PCH_SML1CLK BF27 GPP_B23/SML1ALERT#/PCHHOT# PCH_JTAG_TDO AH2 CPU_XDP_TDI CPU_XDP_TDO <10> Connect CPU & PCH
+3VALW _DSW GPP_C6/SML1CLK PCH_JTAG_TDI CPU_XDP_TDI <10>
PCH_SML1DATA BE27 4 OF 13 AJ3 PCH_JTAG_TCK1
GPP_C7/SML1DATA PCH_JTAG_TCK PCH_JTAG_TCK1 <10>
CNP-H_BGA874 Rev1.0
@
RH55 2 1 1K_0402_5% W AKE#
RH56 2 1 8.2K_0402_5% PM_BATLOW # +3VALW _DSW PM_SLP_S3# RH193 1 2 100K_0201_5%

+3VS PM_SLP_S4# RH194 1 2 100K_0201_5%
RH57 2 @ 1 100K_0402_5% AC_PRESENT_R
RH225 1 2 10K_0402_5% LAN_W AKE# intel critical net recommend
RH58 2 @ 1 100K_0402_5% PBTN_OUT#_R
5
G
QH7B
3 2N7002KDW _SOT363-6 EC_RSMRST# 1 @ 2 PCH_DPW ROK 3
(DDR)
RH59 0_0402_5%
PCH_SMBCLK 3 4 D_CK_SCLK
S
D_CK_SCLK <23,24>
D
+3VALW _PCH_PRIM PCH_PW ROK RH223 1 2 10K_0402_5%

G
QH7A
2N7002KDW _SOT363-6 2 1 SYS_RESET# EC_RSMRST# RH224 1 2 10K_0402_5%
RH183 10K_0402_5%
+3VS PCH_SMBDATA 6 1D_CK_SDATA
S
D_CK_SDATA <23,24>
D
100K_0402_5% 1 @ 2 RH184 SYS_PW ROK

RH60 2 1 8.2K_0402_5% PM_CLKRUN#
100K_0402_5% 1 @ 2 RH61 PCH_DPW ROK
RH191 2 1 2.2K_0402_5% D_CK_SCLK XEMC@

RH192 2 1 2.2K_0402_5% D_CK_SDATA .1U_0402_16V7K 1 2 CH20 SYS_RESET# +3VALW _PCH_PRIM
(EC, VGA, TMS1,TMS2)
XEMC@ PCH_VRALERT# RH62 2 @ 1 10K_0402_5%
PCH_SML1CLK 1 @ 2 .1U_0402_16V7K 1 2 CH21 SYS_PW ROK
+3VALW _PCH_PRIM EC_SMB_CK2 <25,38,58,66,73>
RH189 0_0402_5%
XEMC@
PCH_SML1DATA 1 @ 2 .1U_0402_16V7K 1 2 CH22 PCH_PW ROK
PCH_SMBCLK EC_SMB_DA2 <25,38,58,66,73>
RH230 2 1 2.2K_0402_5% RH190 0_0402_5%
XEMC@
RH231 2 1 2.2K_0402_5% PCH_SMBDATA .1U_0402_16V7K 1 2 CH51 EC_RSMRST#
RH232 2 1 2.2K_0402_5% PCH_SML1CLK

4 4
From ESD Team Request
RH233 2 1 2.2K_0402_5% PCH_SML1DATA
Near PCH side
2017/11/23
Compal Secret Data
2018/09/01 Title
1 2 PCH_SML0CLK PCH(5/8)PMU/HDA/SMBUS/DMIC
RH63 499_0402_1% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1 2 PCH_SML0DATA DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
RH64 499_0402_1% MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH78F M/B LA-G161PR01
A B C D E
A B C D E
Raptor:Intel sensor hub

+3VALW _PCH_PRIM
CNP-H
RH234 2 1 2.2K_0402_5% I2C_1_SCL UH1K
RH235 2 1 2.2K_0402_5% I2C_1_SDA +3VALW _PCH_PRIM
RH236 2 1 2.2K_0402_5% I2C_0_SCL GSPI1_MOSI BA26 BA20 VGA_ID1
RH237 2 1 2.2K_0402_5% I2C_0_SDA TP_EN_PCH BD30 GPP_B22/GSPI1_MOSI GPP_D9/ISH_SPI_CS#/GSPI2_CS0# BB20 VGA_ID2
<63> TP_EN_PCH EC_SCI# GPP_B21/GSPI1_MISO GPP_D10/ISH_SPI_CLK/GSPI2_CLK PROJECT_ID0 ISH_I2C0_SCL RH204
AU26 BB16 1 2 10K_0402_5%
<58> EC_SCI# TP_LED_EN_PCH# GPP_B20/GSPI1_CLK GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO PROJECT_ID1 ISH_I2C0_SDA RH205
AW26 AN18 1 2 10K_0402_5%
+3VS <63> TP_LED_EN_PCH# GPP_B19/GSPI1_CS0# GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI
GSPI0_MOSI BE30 BF14 ISHGSEN@
RH66 2 @ 1 10K_0402_5% EC_SCI# GC6_FB_EN BD29 GPP_B18/GSPI0_MOSI GPP_D16/ISH_UART0_CTS#/CNV_WCEN AR18 ISHGSEN@
TS_EN BF29 GPP_B17/GSPI0_MISO GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN BF17 SUB_DET
<38,58> TS_EN GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD/I2C2_SCL
1 RH68 2 1 49.9K_0402_1% UART_2_PRXD_DTXD RTD3_USB_PW R_EN BB26 BE17 GSYNC_ID
Gsensor use ISH path for PVT 1
<43> RTD3_USB_PW R_EN GPP_B15/GSPI0_CS0# GPP_D13/ISH_UART0_RXD/I2C2_SDA
RH69 2 1 49.9K_0402_1% UART_2_PTXD_DRXD RH262 1 @ 2 0_0402_5% TBT_BATLOW _R# BB24
<18,43> TBT_BATLOW # DGPU_AC_DETECT GPP_C9/UART0A_TXD
BE23
<25,58,82> DGPU_AC_DETECT GPP_C8/UART0A_RXD
RH70 2 @ 1 49.9K_0402_1% UART_2_PRTS_DCTS AP24
GPU_EVENT_R# BA24 GPP_C11/UART0A_CTS#
CG11 connect to GPP_B15 GPP_C10/UART0A_RTS#
RH71 2 @ 1 49.9K_0402_1% UART_2_PCTS_DRTS AG45 ISH_I2C0_SCL
GPP_H20/ISH_I2C0_SCL ISH_I2C0_SDA ISH_I2C0_SCL <38>
BD21 AH46
DGPU_PW R_EN GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H19/ISH_I2C0_SDA ISH_I2C0_SDA <38>
RH72 1 VGA@ 2 10K_0402_5% AW24
DGPU_HOLD_RST# AP21 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AH47
<25> DGPU_HOLD_RST# DGPU_PW R_EN GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_H22/ISH_I2C1_SCL
AU24 AH48
<25,37> DGPU_PW R_EN GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H21/ISH_I2C1_SDA
UART_2_PCTS_DRTS AV21
check needed? UART_2_PRTS_DCTS AW21 GPP_C23/UART2_CTS#
UART_2_PTXD_DRXD BE20 GPP_C22/UART2_RTS# AV34
<52> UART_2_PTXD_DRXD UART_2_PRXD_DTXD GPP_C21/UART2_TXD GPP_A23/ISH_GP5
BD20 AW32
<52> UART_2_PRXD_DTXD GPP_C20/UART2_RXD GPP_A22/ISH_GP4 BA33 Raptor: delete needless strap
I2C_1_SCL BE21 GPP_A21/ISH_GP3 BE34 G_INT
<63> I2C_1_SCL GPP_C19/I2C1_SCL GPP_A20/ISH_GP2
RH73 1 VGA@ 2 10K_0402_5% DGPU_HOLD_RST# <Touch PAD> I2C_1_SDA BF21 BD34 CODEC_ID TC21 TP@
<63> I2C_1_SDA I2C_0_SCL GPP_C18/I2C1_SDA GPP_A19/ISH_GP1
BC22 BF35
I2C_0_SDA BF23 GPP_C17/I2C0_SCL GPP_A18/ISH_GP0 BD38
GPP_C16/I2C0_SDA GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
BE15
+3VALW _PCH_PRIM BE14 GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4
11 OF 13
GPP_D23/ISH_I2C2_SCL/I2C3_SCL
CNP-H_BGA874 Rev1.0
RH74 1 @ 2 4.7K_0402_5% GPP_H12 @
GPP_H12 <16>
This signal has a weak internal pull-down. STRAP +1.8VALW _PRIM
2 0 = Master Attached Flash Sharing (MAFS) enabled (Default) Gsensor use ISH path for PVT 2
1 = Slave Attached Flash Sharing (SAFS) enabled. ECGSEN@ GSYNC@
Notes: GSYNC_ID 1 2 1K_0402_5%
1. This signal is in the primary well. ECGSEN@ RH208
Warning: This strap must be configured to ‘0’ if the ECGSEN@
eSPI or LPC strap is configured to ‘0’ RH207 1NGSYNC@ 2 10K_0402_5%
I2C_0_SCL RH247 1 2 0_0402_5% EC_G_SCL
I2C_0_SDA EC_G_SDA EC_G_SCL <58>
RH246 1 2 0_0402_5%
G_INT EC_G_INT# EC_G_SDA <58>
RH267 1 2 0_0402_5%
EC_G_INT# <58>
+3VALW _PCH_PRIM
FOR 40 PIN SUB/B +1.8VALW _PRIM
SUB_DET RH185 1 @ 2 1K_0402_5%
RH112 1 @ 2 4.7K_0402_5%
PCH_SMBALERT# <18>
SMBALERT# / GPP_C2 has a weak internal Pull-down.
0 = Disable Intel ME (TLS) (Default)
1 = Enable Intel ME (TLS) Raptor:delete needless vga/project id
+1.8VALW _PRIM
RH113 1 @ 2 4.7K_0402_5% GPU_EVENT_R# 1 2 GPU_EVENT# @
PCH_SML0ALERT# <18> GPU_EVENT# <25> PROJECT_ID0
RH200 0_0402_5% RH88 1 2 1K_0402_5%
SML0ALERT# / GPP_C5 has a weak internal Pull-down. GC6_FB_EN 1 2 GC6_FB_EN3V3
0 = LPC is selected (for EC 9022). GC6_FB_EN3V3 <25,37>
RH199 0_0402_5% RH89 1 2 10K_0402_5%
1 = eSPI is selected VBIOS select
+3VS
PROJECT_ID1 RH90 1 @ 2 1K_0402_5%
3 RH114 1 2 150K_0402_1% 3
PCH_SML1ALERT# <18>
2
RH91 1 2 10K_0402_5% @
SML1ALERT# / GPP_B23 has an internal pull-down. RH78
0 = Disable IntelR DCI-OOB (Default) +1.8VALW _PRIM
1 = Enable IntelR DCI-OOB
STRAP 1B 10K_0402_5%
VGA_ID1 RH84 1 @ 2 1K_0402_5%
Project_ID1 Project_ID0
1
G_INT
RH85 1 2 10K_0402_5% Project ID
GPP_D12 GPP_D11
2
+3VS VGA_ID2 RH86 1 @ 2 1K_0402_5%
*EH78F 0 0 RH79
@
RH87 1 2 10K_0402_5% Reserved 0 1 100K_0402_5%
RH77 1 @ 2 4.7K_0402_5% GSPI0_MOSI STRAP Reserved 1 0
1
The signal has a weak internal Pull-down.
0 = Disable “No Reboot” mode. (Default) Reserved 1 1
1 = Enable “No Reboot” mode (PCH will disable the
TCO Timer system reboot feature). This function is
useful when running ITP/XDP. VGA_ID2 VGA_ID1 SCI capability is available on all GPIOs
Notes: VGA ID PCH GPIOs that can be routed to generate SMI# or NMI:
‧ GPP_B14, GPP_B20, GPP_B23
1. The internal Pull-down is disabled after
PCH_PWROK is high. GPP_D10 GPP_D9 ‧ GPP_C[23:22]
2. This signal is in the primary well. ‧ GPP_D[4:0]
N18E-G3 0 0 ‧ GPP_E[8:0]
‧ GPP_I[3:0]
Reserved 0 1 ‧ GPP_G[7:0] (support SMI# only).
@ GSPI1_MOSI
RH80 1 2 150K_0402_1% STRAP Reserved 1 0 The voltage of all GPIO pads in each GPP group is determined by the voltage supplied to the group (either 3.3V or 1.8V),
except for GPP_I and GPD group, (which are 3.3V only), and GPP_J group (which is 1.8V only).
This Signal has a weak internal Pull-down.
4 0: SPI (Default) Reserved 1 1 All GPIOs have programmable internal pull-up/pull-down resistors which are off by default.
4
1: LPC The internal pull-up/pull-down for each GPIO can be enabled by BIOS programming.
Notes:
1. The internal Pull-down is disabled after PCH_PWROK is high.
2. This signal is in the primary well.
RH83 2 @ 1 100K_0402_5% PCH_SPKR

PCH_SPKR <18,56>
2017/11/23
Compal Secret Data
2018/09/01 Title
Top
0 =
Swap Override
Disable “Top Swap” mode. (Default)
STRAP PCH(6/8)GPIO/I2C/UART/STRAP
1 = Enable “Top Swap” mode. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
The internal Pull-down is disabled after PCH_PWROK is high.
A B C D E
A B C D E
GPIO Group Voltage
GPPA 3.3V
+1.05VALW_PCH_PRIM
+1.05VALW CNP-H +3VALW_PCH_PRIM
+1.05VALW_PCH_PRIM UH1H GPPB
5.95A AA22 AW9 0.182A GPPC 3.3V
@ JPH1 AA23 VCCPRIM_1P051 VCCPRIM_3P32
1 2 5.95A AB20 VCCPRIM_1P052 BF47 +VCCRTCEXT
1 2 HSIO for DMIU/USB3.1/PCIE=4162mA VCCPRIM_1P053 DCPRTC1 +VCCRTCEXT GPPD 3.3V
AB22 BG47 +VCCRTCEXT * 1.8V
VCCPRIM_1P054 DCPRTC2
1U_0201_6.3V6M
JUMP_43X79 1 AB23
AB27 VCCPRIM_1P055 V23 0.095A +3VALW_SPI
VCCPRIM_1P056 VCCPRIM_3P35
GPPE
CH23
AB28 3.3V
.1U_0402_16V7K
AB30 VCCPRIM_1P057 AN44 0.05A 1 GPPF
2 AD20 VCCPRIM_1P058 VCCSPI +RTCVCC
CH24
AD23 VCCPRIM_1P059 BC49
1 GPPG 3.3V 1
AD27 VCCPRIM_1P0510 VCCRTC1 BD49
VCCPRIM_1P0511 VCCRTC2 2
AD28
AD30 VCCPRIM_1P0512 AN21 0.145A GPPH 3.3V
AF23 VCCPRIM_1P0513 VCCPGPPG_3P3 AY8 GPPK
+1.05VALW_VCCMPHY AF27 VCCPRIM_1P0516 VCCPRIM_3P33 BB7 0.97A
@ JPH2 +1.05VALW_VCCMPHY AF30 VCCPRIM_1P0517 VCCPRIM_3P34
VCCPRIM_1P0518
GPPI 3.3V Only
1 2 6.6A AC35 0.262A
1 2 6.6A U26 VCCPGPPHK1 AC36
JUMP_43X79 U29 VCCPRIM_1P0523 VCCPGPPHK2 AE35 0.174A GPPJ 1.8V Only
V25 VCCPRIM_1P0524 VCCPGPPEF1 AE36
VCCPRIM_1P0525 VCCPGPPEF2 +1.8VALW_PRIM
22U_0603_6.3V6M
1U_0201_6.3V6M
1 V27
VCCPRIM_1P0526 GPD
1
V28 AN24 0.14A 3.3V Only
VCCPRIM_1P0527 VCCPGPPD +1.8VALW_PRIM
CH25
CH26
V30 AN26
2 +1.05VALW_PCH V31 VCCPRIM_1P0528 VCCPGPPBC1 AP26 0.343A
2 VCCPRIM_1P0529 VCCPGPPBC2
0.0012A AD31 AN32 0.101A
VCCPRIM_1P0514 VCCPGPPA
4.7U_0402_6.3V6M
1U_0201_6.3V6M
1 1
0.2A AE17 AT44 0.106A
VCCPRIM_1P0515 VCCPRIM_3P31
CH27
CH28
BE48
3-5MM FROM PACKAGE EDGE 0.42A W22 VCCDSW_3P31 BE49 0.113A
VCCDUSB_1P051 VCCDSW_3P32 +3VALW_DSW +3VALW_HDA 2 2
W23
+1.05VALW_PCH +1.05V_VCCDSW VCCDUSB_1P052 BB14 0.00767A
BG45 VCCHDA AG19
RH94 1 @ 2 0_0603_5% BG46 VCCDSW_1P051 VCCPRIM_1P83 AG20 +1.8VALW_PRIM
0.109A W31 VCCDSW_1P052 VCCPRIM_1P84 AN15 0.766A Close to BB11
+1.05VALW_VCCAZPLL VCCPRIM_MPHY_1P05 VCCPRIM_1P85 AR15
0.015A D1 VCCPRIM_1P86 BB11
E1 VCCPRIM_1P0521 VCCPRIM_1P87 +1.8V_PHVLDO +1.8VALW_PRIM
+1.05VALW_VCCAMPHYPLL 0.213A C49 VCCPRIM_1P0522 AF19 0.882A @ VCCPHVLDO_1P8
D49 VCCAMPHYPLL_1P051 VCCPRIM_1P81 AF20 +1.8V_PHVLDO RH242 1 2 0_0603_5% (External VRM mode RH172 unmount)
E49 VCCAMPHYPLL_1P052 VCCPRIM_1P82
+1.05VALW_PCH +1.05VALW_PCH +1.05V_VCCDSW VCCAMPHYPLL_1P053 AG31 0.193A
+1.05VALW_XTAL VCCPRIM_1P0520 +1.05VALW_PCH
0.00428A P2 AF31 0.0895A
VCCA_XTAL_1P051 VCCPRIM_1P0519 +1.05VALW_PCH
P3 AK22
0.169A W19 VCCA_XTAL_1P052 VCCPRIM_1P241 AK23 +1.24V_VCCLDOSRAM_IN +1.24V_PRIM_DPHY
2 VCCA_SRC_1P051 VCCPRIM_1P242 +1.24V_VCCLDOSRAM_IN 2
1U_0201_6.3V6M
1 W20
Short pins AJ22,AJ23,AK22,AK23 together
.1U_0402_16V7K
.1U_0402_16V7K
VCCA_SRC_1P052 AJ22
1 1 VCCDPHY_1P241 +1.24V_PRIM_DPHY at surface layer from PDG Rev0.71 RH96 1 2 0_0402_5%
CH31
0.0198A C1 AJ23 Internal LDO

CH29
CH30
C2 VCCAPLL_1P054 VCCDPHY_1P242 BG5 RH174 for 571391_CFL_H_PDG_Rev0p71.pdf

2 VCCAPLL_1P055 VCCDPHY_1P243 +1.24V_PRIM_MAR
0.0085A V19
2 2 VCCA_BCLK_1P05 K47 VCCMPHY_SENSE
VCCMPHY_SENSE TP@ TH27
0.021A B1 K46 VSSMPHY_SENSE For DDX03 R02
VCCAPLL_1P051 VSSMPHY_SENSE TP@ TH28
B2
B3 VCCAPLL_1P052 8 OF 13 +1.24V_PRIM_MAR
VCCAPLL_1P053
CNP-H_BGA874 Rev1.0
place near VCCDUSB 1-3MM FROM PACKAGE 1-3MM FROM PACKAGE EDGE
FOR W22/W23 VCCPRIM_MPHY W31 @
4.7U_0402_6.3V6M
1
CH32
+1.05VALW_PCH 2
+1.05VALW_PCH
+1.05VALW_PCH
1U_0201_6.3V6M
.1U_0402_16V7K
1
1 +3VALW_PCH_PRIM
1U_0201_6.3V6M
1
+3VALW_PCH_PRIM +3VALW_PCH_PRIM
CH33
CH34
+3VALW +3VALW_PCH_PRIM +3VALW_PCH_PRIM +3VALW_SPI

CH35
2
2
.1U_0402_16V7K
2
1U_0201_6.3V6M
1 1
.1U_0402_16V7K
RH97 1 2 0_0805_5% RH98 1 2 0_0603_5% 1
.1U_0402_16V7K
CH38
CH37
1
CH36
1-5MM FROM PACKAGE EDGE 1-3MM FROM PACKAGE EDGE 1-5MM FROM PACKAGE EDGE
CH39
+1.8VALW +1.8VALW_PRIM 2 2
FOR VCCAPLL C1/C2 FOR VCCA_BCLK V19 FOR VCCAPLL B1/B2/B3 +3VALW_DSW 2
@ 2
@
RH99 1 2 0_0402_5% RH100 1 2 0_0603_5%
.1U_0402_16V7K
1
CH40
3 3
1-3MM FROM PACKAGE 1-3MM FROM PACKAGE 1-3MM FROM PACKAGE
2 FOR PGPPEF AE35/AE37 FOR PGPPHK AC35/AC36 FOR VCCPRIM AY8/BB7
+1.05VALW_PCH +3VALW_HDA
@
+1.05VALW_VCCAZPLL RH101 1 2
Raptor:use chargeable RTC, JRTC on POWER side
@
RH102 1 2 0_0402_5% 0_0402_5%
1P_0402_50V8
1P_0402_50V8
1 1
RTC Battery
1P_0402_50V8
1P_0402_50V8
CH41
CH42
1 1
CH43
CH44
2 2
@ @
+RTCBATT +CHGRTC W=20mils
2 2 DH2
@ @ reserve filter folloe CRB +RTCVCC
2
8/21 W=20mil
1-3MM FROM PACKAGE EDGE 1
W=20mils
3
+1.05VALW_VCCAMPHYPLL BAS40-04_SOT23-3
.1U_0402_16V7K
1U_0201_6.3V6M
RH103 1 2 0_0402_5% 1 1
CH48
22U_0603_6.3V6M
1U_0201_6.3V6M
CH47
1 1
2 2
CH45
CH46
2 2
LC filter colse to pin
@
1uF 1-3MM FROM PACKAGE EDGE
4 4
+1.05VALW_XTAL
RH105 1 2 0_0402_5%
22U_0603_6.3V6M
1
CH49
2 Issued Date 2017/11/23 Deciphered Date 2018/09/01 Title
@
PCH(7/8)Power
Custom 0.1
A B C D E
A B C D E
CNP-H
UH1L CNP-H
CNP-H UH1J
UH1I BG3 M24 Y14
A2 AL12 BG33 VSS VSS M32 RSVD7 Y15
A28 VSS VSS AL17 BG37 VSS VSS M34 RSVD8 U37
1 1
A3 VSS VSS AL21 BG4 VSS VSS M49 RSVD6 U35
A33 VSS VSS AL24 BG48 VSS VSS M5 RSVD5
A37 VSS VSS AL26 C12 VSS VSS N12 N32
A4 VSS VSS AL29 C25 VSS VSS N16 RSVD3 R32
A45 VSS VSS AL33 C30 VSS VSS N34 RSVD4
A46 VSS VSS AL38 C4 VSS VSS N35 AH15
A47 VSS VSS AM1 C48 VSS VSS N37 RSVD2 AH14
A48 VSS VSS AM18 C5 VSS VSS N38 RSVD1
A5 VSS VSS AM32 D12 VSS VSS P26
A8 VSS VSS AM49 D16 VSS VSS P29
AA19 VSS VSS AN12 D17 VSS VSS P4 AL2 XDP_PREQ#
VSS VSS VSS VSS PREQ# XDP_PRDY# XDP_PREQ# <10>
AA20 AN16 D30 P46 AM5 XDP_PRDY# <10>
AA25 VSS VSS AN34 D33 VSS VSS R12 PRDY# AM4 CPU_XDP_TRST#
VSS VSS VSS VSS CPU_TRST# CPU_XDP_TRST# <10>
AA27 AN38 D8 R16 AK3 PCH_TRIGOUTRH106 1 2 30_0402_5% PCH_TRIGOUT_R
VSS VSS VSS VSS TRIGGER_OUT CPU_TRIGOUT_R PCH_TRIGOUT_R <13>
AA28 AP4 E10 R26 AK2
VSS VSS VSS VSS TRIGGER_IN CPU_TRIGOUT_R <13>
AA30 AP46 E13 R29
AA31 VSS VSS AR12 E15 VSS VSS R3 10 OF 13
AA49 VSS VSS AR16 E17 VSS VSS R34 CNP-H_BGA874 Rev1.0
AA5 VSS VSS AR34 E19 VSS VSS R38
VSS VSS VSS VSS @
AB19 AR38 E22 R4
AB25 VSS VSS AT1 E24 VSS VSS T17
AB31 VSS VSS AT16 E26 VSS VSS T18
AC12 VSS VSS AT18 E31 VSS VSS T32
AC46 VSS VSS AT32 E8 VSS VSS U12
2 AD1 VSS VSS AT34 F41 VSS VSS U15 2
AD19 VSS VSS AT45 F43 VSS VSS U17
AD2 VSS VSS AV11 F47 VSS VSS U21
AD22 VSS VSS AV39 G44 VSS VSS U24
AD25 VSS VSS AW10 G6 VSS VSS U33
AD49 VSS VSS AW4 H8 VSS VSS U38
AE12 VSS VSS AW40 J10 VSS VSS V20
AE33 VSS VSS AW46 J26 VSS VSS V22
AE38 VSS VSS B47 J29 VSS VSS V4
AE4 VSS VSS B48 J4 VSS VSS V46
AE46 VSS VSS B49 J40 VSS VSS W25
AF22 VSS VSS BA12 J46 VSS VSS W27
AG1 VSS VSS BA5 J9 VSS VSS Y10
AG22 VSS VSS BA6 K11 VSS VSS Y12
AG23 VSS VSS BB41 K39 VSS VSS Y17
AG25 VSS VSS BB43 M16 VSS VSS Y33
AG27 VSS VSS BB9 M18 VSS VSS Y38
AG28 VSS VSS BC10 M21 VSS 12 OF 13 VSS Y9
AG30 VSS VSS BC13 VSS VSS
AG49 VSS VSS BC15 CNP-H_BGA874 Rev1.0
AH12 VSS VSS BC19
VSS VSS @
AH17 BC24
AH33 VSS VSS BC26
AH38 VSS VSS BC31
AJ19 VSS VSS BC35
AJ20 VSS VSS BC40
AJ25 VSS VSS BC45
3 AJ27 VSS VSS BC8 3
AJ28 VSS VSS BD43
AJ30 VSS VSS BE44
AJ31 VSS VSS BF1
AK19 VSS VSS BF2
AK20 VSS VSS BF3
AK25 VSS VSS BF48
AK27 VSS VSS BF49
AK28 VSS VSS BG17
AK30 VSS VSS BG2
AK31 VSS VSS BG22
AK4 VSS VSS BG25
AK46 VSS 9 OF 13 VSS BG28
VSS VSS
CNP-H_BGA874 Rev1.0
4 4
2017/11/23
Compal Secret Data
2018/09/01 Title
PCH(8/8)GND/RSVD
A B C D E
A B C D E
+3VS +3V_OVRM
RG3014 1 upi@ 2 0_0402_5%

+3V_OVRM
CSSP_B+ RG2895 1 VGA@ 2 75K_0402_1% PFM_CH1_BS_IN1 +3VLP
1
CG2780 RG2896
2K_0402_5%
RG2975
2K_0402_5%
RG2976
2K_0402_5%
RG2977
2K_0402_5%
RG2978
1 2 1 1 2 RG3015 1 onsemi@2 0_0402_5% 1
649_0402_1%
1000P_0402_50V7K onsemi@ VGA@ VGA@ VGA@ VGA@
VGA@
2
PFM_CH1_SH_IN_P3
CSSP_NVVDD RG2897 1 VGA@ 2 75K_0402_1% PFM_CH1_BS_IN2 1B PFM_CH1_SH_IN_N3
SNN_PFM_CH1_SH_IN_P4
CG2781 RG2898 SNN_PFM_CH1_SH_IN_N4
2 1 1 2 0730 FAE CF suggest
2
649_0402_1% +3V_OVRM
0_0402_5%
RG2903
0_0402_5%
RG2900
1000P_0402_50V7K
VGA@
onsemi@ 0727 FAE CF suggest
1
1
1015 follow NV PGM V05 latest recommend vaule VGA@
VGA@ VGA@
CG2782
UG108 1U_0201_6.3V6M
2
3 27
6 BS_IN1 VCC
PFM_CH1_BS_IN3 11 BS_IN2 2 PFM_CH1_SH_IN_P1 RG2902 1 VGA@ 2 100_0402_1% CSSP_B+
PFM_CH1_BS_IN4 14 BS_IN3 SH_IN_P1 PFM_CH1_SH_IN_N1 CSSN_B+ CSSP_B+ <94>
1 RG2904 1 VGA@ 2 0_0402_5%
BS_IN4 SH_IN_N1 PFM_CH1_SH_IN_P2 CSSP_NVVDD CSSN_B+ <94>
5 RG2905 1 VGA@ 2 100_0402_1%
SH_IN_P2 PFM_CH1_SH_IN_N2 CSSN_NVVDD CSSP_NVVDD <94>
4 RG2907 1 VGA@ 2 0_0402_5%
PFM_FILTER_GND_FET SH_IN_N2 PFM_CH1_SH_IN_P3 CSSN_NVVDD <94>
@1 RG2906 2 9 12
GND_FET SH_IN_P3 13 PFM_CH1_SH_IN_N3
0_0402_5% SH_IN_N3 15 SNN_PFM_CH1_SH_IN_P4
RG2910 1 onsemi@2 169_0402_1% 32 SH_IN_P4 16 SNN_PFM_CH1_SH_IN_N4
RG2911 1 onsemi@2 169_0402_1% 7 SH_O1 SH_IN_N4 VGA@
2 RG2912 1 @ 2 169_0402_1% 10 SH_O2 20 ADC_IN_P RG2913 1 VGA@ 2 0_0402_5% CG2784 1 2 47P_0402_50V8J 2
RG2914 1 @ 2 169_0402_1% 17 SH_O3 DIFF_OUT_P 19 ADC_IN_N RG2915 1 VGA@ 2 0_0402_5% CG2785 1 2 47P_0402_50V8J
SH_O4 DIFF_OUT_N VGA@
1 1 1 1
0.015U_0402_16V7K
0.015U_0402_16V7K
0.015U_0402_16V7K
0.015U_0402_16V7K
VGA@ 30 PFM_PF_BSOK_R
BS_OK ADC_IN_P <25>
CG2786
CG2787
CG2788
CG2789
RG2916
ADC_IN_N <25>
1 2 PFM_ADC_MUX_SEL_R 29 8 SNN_ADC_CUSTOM8
2 2 2 2 0_0402_5% MUX_SEL NC 18 SNN_ADC_CUSTOM18
NC 21 SNN_ADC_CUSTOM21
PFM_ADC_FILTER_EN 28 NC 31 SNN_ADC_CUSTOM31
ENABLE NC onsemi@
23 PFM_BG_REF_OUT R2917 1 2 243K_0402_1%
PFM_SKIP_R 25 BG_REF_OUT 24 PFM_BS_REF
@ @ VGA@ VGA@ SKIP BS_REF 22 PFM_CM_REF_IN
GPIO28_OC_W ARN# CM_REF_IN RG2918
1 1 1
<25> GPIO28_OC_W ARN#
1000P_0402_50V7K
CG2790
1000P_0402_50V7K
CG2791
1000P_0402_50V7K
CG2792
PFM_ADC_FILTER_MODE
26 33 1 2
MODE_SEL GND 365K_0402_1%
1
2 2 2 VGA@ 1
681K_0402_1%
RG2920
10K_0402_1%
RG2921
1000P_0402_50V7K
CG2793
NCP45491XMNTW G_QFN32_4X4
VGA@ +3V_OVRM
1B SA0000C9Q00 2
onsemi@ VGA@ VGA@ VGA@
1
+3V_OVRM RG2926
+3V_OVRM VGA@ 10K_0402_1%
VGA@
VGA@
2
1
RG2923 RG2924
@ 10K_0402_1% 1K_0402_1% PFM_PF_BSOK_R
3 3
0730 FAE CF suggest ,

2
PFM_ADC_FILTER_EN
VGA@ PFM_SKIP_R reserve pull high only
1
D
RG2925 2
10K_0402_1% G
OVRM_EN <58> 0727 FAE CF suggest
1
upi@ S
3
onsemi@ QG548 RG3016

1019 Colay uPI and Onsemi, value follow NV PGM-08866-001_v05
2
SB00001GE00 100K_0402_5%
L2N7002W T1G_SC-70-3
onsemi@ RG2898 RG2910 R2917
2
uPI
487_0402_1% 127_0402_1% 324K_0402_1%
UG108
S RES 1/16W 487 +-1% 0402 S RES 1/16W 127 +-1% 0402 S RES 1/16W 324K +-1% 0402
upi@ upi@ upi@
+3V_OVRM RG2896 RG2911
US5650PQKI
S IC US5650QQKI W QFN 32P POW ER MONITOR
1
RG2928 SA0000CMA00
upi@
@
4 10K_0402_1% 1C 487_0402_1% 127_0402_1% 4
S RES 1/16W 487 +-1% 0402 S RES 1/16W 127 +-1% 0402
2
PFM_ADC_FILTER_MODE upi@ upi@

1
RG2929
@
10K_0402_1%
2017/11/23
Compal Secret Data
2018/09/01 Title
OVR-M
2
A B C D E
5 4 3 2 1
CHANNEL-A TOP REVERSE (4mm) <7>

<7>
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK0
DDR_A_CLK#0
137
139
JDIMM1A
CK0(T)
CK0#(C)
REVERSE
DQ0
DQ1
8
7
DDR_A_D0
DDR_A_D1
DDR_A_CLK1 DDR_A_D2
Interleaved Memory <7> DDR_A_CLK1

138 20
DDR_A_CLK#1 140 CK1(T) DQ2 21 DDR_A_D3
<7> DDR_A_CLK#1 CK1#(C) DQ3 DDR_A_D4
4
DDR_A_CKE0 109 DQ4 3 DDR_A_D5
<7> DDR_A_CKE0 DDR_A_CKE1 CKE0 DQ5 DDR_A_D6
110 16
TOP: JDIMM1 CONN Non-ECC DIMM <7> DDR_A_D[0..15]
<7> DDR_A_CKE1
<7> DDR_A_CS#0
DDR_A_CS#0 149
CKE1
S0#
DQ6
DQ7
DQS0(T)
17
13
DDR_A_D7
DDR_A_DQS0
DDR_A_DQS0 <7>
DDR_A_CS#1 157 11 DDR_A_DQS#0
<7> DDR_A_D[16..31] <7> DDR_A_CS#1 S1# DQS0#(C) DDR_A_DQS#0 <7>
D
162 D
+3VS +3VS +3VS 165 S2#/C0 28 DDR_A_D8
<7> DDR_A_D[32..47] S3#/C1 DQ8 29 DDR_A_D9
DDR_A_ODT0 155 DQ9 41 DDR_A_D10
<7> DDR_A_D[48..63] <7> DDR_A_ODT0 ODT0 DQ10
1
1
DDR_A_ODT1 161 42 DDR_A_D11
<7> DDR_A_ODT1 ODT1 DQ11 DDR_A_D12
RD4 RD1 RD5 24
@ 0_0402_5% @ 0_0402_5% @ 0_0402_5% JDIMM1B DDR_A_BG0 115 DQ12 25 DDR_A_D13
REVERSE <7> DDR_A_BG0 DDR_A_BG1 113 BG0 DQ13 38 DDR_A_D14
111 141 <7> DDR_A_BG1 DDR_A_BA0 150 BG1 DQ14 37 DDR_A_D15
+1.2V_VDDQ +1.2V_VDDQ <7> DDR_A_BA0
2
2
SA0_CHA_DIM1 SA1_CHA_DIM1 SA2_CHA_DIM1 112 VDD1 VDD11 142 DDR_A_BA1 145 BA0 DQ15 34 DDR_A_DQS1
VDD2 VDD12 <7> DDR_A_BA1 BA1 DQS1(T) DDR_A_DQS#1 DDR_A_DQS1 <7>
117 147 32
118 VDD3 VDD13 148 DDR_A_MA0 144 DQS1#(C) DDR_A_DQS#1 <7>
VDD4 VDD14 <7> DDR_A_MA0 A0
1
1
123 153 DDR_A_MA1 133 50 DDR_A_D16
VDD5 VDD15 <7> DDR_A_MA1 DDR_A_MA2 A1 DQ16 DDR_A_D17
RD3 RD6 RD2 124 154 132 49
0_0402_5% 0_0402_5% 0_0402_5% 129 159 131 62
130 160 128 63
135 VDD8 VDD18 163 <7> DDR_A_MA4 DDR_A_MA5 126 A4 DQ19 46 DDR_A_D20
<7> DDR_A_MA5
2
2
+3VS 136 VDD9 VDD19 DDR_A_MA6 127 A5 DQ20 45 DDR_A_D21
VDD10 <7> DDR_A_MA6 DDR_A_MA7 A6 DQ21 DDR_A_D22
122 58
<7> DDR_A_MA7 DDR_A_MA8 A7 DQ22 DDR_A_D23
255 258 125 59
VDDSPD VTT +0.6VS_VTT <7> DDR_A_MA8 DDR_A_MA9 121 A8 DQ23 55 DDR_A_DQS2
<7> DDR_A_MA9 A9 DQS2(T) DDR_A_DQS2 <7>
.1U_0402_16V7K
164 257 DDR_A_MA10 146 53 DDR_A_DQS#2
2.2U_0402_6.3V6M
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM 2 2
+0.6V_DDR_VREFCA VREFCA VPP1 259 +2.5V <7> DDR_A_MA10 DDR_A_MA11 120 A10_AP DQS2#(C) DDR_A_DQS#2 <7>
VPP2 <7> DDR_A_MA11 DDR_A_MA12 A11 DDR_A_D24
119 70
<7> DDR_A_MA12 A12 DQ24
CD1
CD2
1 99 DDR_A_MA13 158 71 DDR_A_D25
VSS VSS <7> DDR_A_MA13 DDR_A_MA14_WE# A13 DQ25 DDR_A_D26
2 102 151 83
1 1 VSS VSS <7> DDR_A_MA14_WE# DDR_A_MA15_CAS# A14_WE# DQ26 DDR_A_D27
5 103 156 84
SPD ADDRESS FOR CHANNEL A : 6 VSS
VSS
VSS
VSS
106 <7>
<7>
DDR_A_MA15_CAS#
DDR_A_MA16_RAS#
DDR_A_MA16_RAS# 152 A15_CAS#
A16_RAS#
DQ27
DQ28
66 DDR_A_D28
DDR_A_D29
9 107 67
WRITE ADDRESS: 0XA0 PLACE NEAR TO PIN
10
14
VSS
VSS
VSS
VSS
167
168
<7> DDR_A_ACT#
DDR_A_ACT# 114
ACT#
DQ29
DQ30
79
80
DDR_A_D30
DDR_A_D31
READ ADDRESS: 0XA1 15
18
VSS
VSS
VSS
VSS
171
172 <7> DDR_A_PAR
DDR_A_PAR
DDR_A_ALERT#
143
116 PARITY
DQ31
DQS3(T)
76
74
DDR_A_DQS3
DDR_A_DQS#3 DDR_A_DQS3 <7>
SA0 = 0; SA1 = 0; SA2 = 0. 19
22
VSS
VSS
VSS
VSS
175
176 +1.2V_VDDQ RD7 2 <7> DDR_A_ALERT#
1 240_0402_1% DIMM1_CHA_EVENT#
DDR_DRAMRST#_R
134
108
ALERT#
EVENT#
DQS3#(C)
174 DDR_A_D32
DDR_A_DQS#3 <7>
C
DDR4 POR OPERATING SPEED: 1867 MT/S 23
26
VSS
VSS
VSS
VSS
180
181
<18,24> DDR_DRAMRST#_R RESET# DQ32
DQ33
173
187
DDR_A_D33
DDR_A_D34 C
STRETCH GOAL IS 2133 MT/S 27

30
VSS
VSS
VSS
VSS
184
185 <18,24> D_CK_SDATA
254
253 SDA
DQ34
DQ35
186
170
DDR_A_D35
DDR_A_D36
VSS VSS <18,24> D_CK_SCLK SCL DQ36 DDR_A_D37
31 188 169
35 VSS VSS 189 SA2_CHA_DIM1 166 DQ37 183 DDR_A_D38
36 VSS VSS 192 SA1_CHA_DIM1 260 SA2 DQ38 182 DDR_A_D39
Layout Note: Layout Note: VSS VSS SA0_CHA_DIM1 SA1 DQ39 DDR_A_DQS4
39 193 256 179
Place near JDIMM1.257,259 Place near JDIMM1.258 40 VSS VSS 196 SA0 DQS4(T) 177 DDR_A_DQS#4 DDR_A_DQS4 <7>
43 VSS VSS 197 DQS4#(C) DDR_A_DQS#4 <7>
44 VSS VSS 201 92 195 DDR_A_D40
47 VSS VSS 202 91 CB0_NC DQ40 194 DDR_A_D41
48 VSS VSS 205 101 CB1_NC DQ41 207 DDR_A_D42
+2.5V +0.6VS_VTT 51 VSS VSS 206 105 CB2_NC DQ42 208 DDR_A_D43
10uF*2 10uF*2 VSS VSS CB3_NC DQ43 DDR_A_D44
52 209 88 191
1uF*2 1uF*1 56 VSS VSS 210 87 CB4_NC DQ44 190 DDR_A_D45
57 VSS VSS 213 For ECC DIMM 100 CB5_NC DQ45 203 DDR_A_D46
VSS VSS CB6_NC DQ46
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
60 214 104 204 DDR_A_D47

1 1 1 1 1 1 1 VSS VSS CB7_NC DQ47
61 217 97 200 DDR_A_DQS5
VSS VSS DQS8(T) DQS5(T) DDR_A_DQS5 <7>
CD3
CD4
CD5
CD6
CD7
CD8
CD9
64 218 95 198 DDR_A_DQS#5

VSS VSS DQS8#(C) DQS5#(C) DDR_A_DQS#5 <7>
65 222
2 2 2 2 2 2 2 68 VSS VSS 223 216 DDR_A_D48
69 VSS VSS 226 12 DQ48 215 DDR_A_D49
72 VSS VSS 227 +1.2V_VDDQ 33 DM0#/DBI0# DQ49 228 DDR_A_D50
73 VSS VSS 230 54 DM1#/DBI1# DQ50 229 DDR_A_D51
85 VSS VSS 239 DDR_DRAMRST#_R 241 DM6#/DBI6# DQ55 221 DDR_A_DQS6
VSS VSS DM7#/DBI7# DQS6(T) DDR_A_DQS#6 DDR_A_DQS6 <7>
86 243 96 219
VSS VSS DM8#/DBI8# DQS6#(C) DDR_A_DQS#6 <7>
.1U_0402_16V7K
89 244
90 VSS VSS 247
Layout Note: VSS VSS 2
93 248 @
PLACE THE CAP near JDIMM1. 164 VSS VSS
CD10
94 251 237 DDR_A_D56
98 VSS VSS 252 DQ56 236 DDR_A_D57
B VSS VSS 1 DQ57 249 DDR_A_D58 B
262 261 DQ58 250 DDR_A_D59
GND GND DQ59 232 DDR_A_D60
DQ60 233 DDR_A_D61
+0.6V_DDR_VREFCA LOTES_ADDR0206-P001A DQ61 245 DDR_A_D62
2.2uF*1 DQ62 DDR_A_D63
CONN@ 246
0.1uF*1 PLACE NEAR TO SODIMM DQ63 242 DDR_A_DQS7
DQS7(T) DDR_A_DQS#7 DDR_A_DQS7 <7>
2 2 240
DQS7#(C) DDR_A_DQS#7 <7>
CD11 CD12
.1U_0402_16V7K 2.2U_0402_6.3V6M
Part Number:SP07001CY00
1 1 Part Value:S SOCKET LOTES ADDR0206-P001A 260P DDR4 LOTES_ADDR0206-P001A
CONN@
+1.2V_VDDQ
Connector follow 2018V-VX

DIMM Side CPU Side
2
RD8 +0.6V_DDR_VREFCA +0.6V_VREFCA
Layout Note:
Place near JDIMM1 @ 2 1K_0402_1%
CD13
1
.1U_0402_16V7K
1
1 RD9 2
VREF traces should be at least 20 mils
10uF*6 2_0402_1% wide with 20 mils spacing to other
1uF*8 1 signals
+1.2V_VDDQ +1.2V_VDDQ 2
2
330uF*1 +1.2V_VDDQ CD15

RD10 CD14 0.022U_0402_16V7K
2
1K_0402_1% .1U_0402_16V7K
1
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
2
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
CD16
CD17
CD18
CD19
CD20
CD21
CD22
CD23
A + CD32 RD11 A
CD24
CD25
CD26
CD27
CD28
CD29
CD30
CD31
330U_D2_2V_Y 24.9_0402_1%
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1
@ @

DDRIV_CHA: DIMM0
0.1
5 4 3 2 1
5 4 3 2 1
CHANNEL-B TOP REV (8mm)

TOP: JDIMM2 CONN Non-ECC DIMM Interleaved Memory <8> DDR_B_D[0..15]
<8>
<8>
<8>
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1
137
139
138
140
JDIMM2A
CK0(T)
CK0#(C)
CK1(T)
RESERVE
DQ0
DQ1
DQ2
8
7
20
21
DDR_B_D0
DDR_B_D1
DDR_B_D3
DDR_B_D7
<8> DDR_B_CLK#1 CK1#(C) DQ3 DDR_B_D4
4
+3VS +3VS +3VS <8> DDR_B_D[16..31] DDR_B_CKE0 109 DQ4 3 DDR_B_D5
<8> DDR_B_CKE0 DDR_B_CKE1 CKE0 DQ5 DDR_B_D2
110 16
<8> DDR_B_D[32..47] <8> DDR_B_CKE1 CKE1 DQ6 17 DDR_B_D6
DQ7
1
1
DDR_B_CS#0 149 13 DDR_B_DQS0
D <8> DDR_B_D[48..63] <8> DDR_B_CS#0 DDR_B_CS#1 157 S0# DQS0(T) 11 DDR_B_DQS#0 DDR_B_DQS0 <8> D
RD12 RD13 RD14
<8> DDR_B_CS#1 162 S1# DQS0#(C) DDR_B_DQS#0 <8>
0_0402_5% 0_0402_5% @ 0_0402_5% JDIMM2B
@ S2#/C0 DDR_B_D8
RESERVE 165 28
111 141 S3#/C1 DQ8 29 DDR_B_D9
+1.2V_VDDQ +1.2V_VDDQ
2
2
SA0_CHB_DIM3 SA1_CHB_DIM3 SA2_CHB_DIM3 112 VDD1 VDD11 142 DDR_B_ODT0 155 DQ9 41 DDR_B_D11
117 VDD2 VDD12 147 <8> DDR_B_ODT0 DDR_B_ODT1 161 ODT0 DQ10 42 DDR_B_D15
VDD3 VDD13 <8> DDR_B_ODT1 ODT1 DQ11
1
118 148 24 DDR_B_D14

VDD4 VDD14 DQ12
1
1
RD16 123 153 DDR_B_BG0 115 25 DDR_B_D10
124 VDD5 VDD15 154 <8> DDR_B_BG0 DDR_B_BG1 113 BG0 DQ13 38 DDR_B_D12
RD15 @ 0_0402_5% RD17
VDD6 VDD16 <8> DDR_B_BG1 DDR_B_BA0 BG1 DQ14 DDR_B_D13
0_0402_5% 0_0402_5% 129 159 150 37
130 VDD7 VDD17 160 <8> DDR_B_BA0 DDR_B_BA1 145 BA0 DQ15 34 DDR_B_DQS1
<8> DDR_B_BA1 DDR_B_DQS1 <8>
2
135 VDD8 VDD18 163 BA1 DQS1(T) 32 DDR_B_DQS#1

DDR_B_DQS#1 <8>
2
2
+3VS 136 VDD9 VDD19 DDR_B_MA0 144 DQS1#(C)
VDD10 <8> DDR_B_MA0 DDR_B_MA1 A0 DDR_B_D16
133 50
<8> DDR_B_MA1 DDR_B_MA2 A1 DQ16 DDR_B_D17
255 258 132 49
VDDSPD VTT +0.6VS_VTT <8> DDR_B_MA2 DDR_B_MA3 131 A2 DQ17 62 DDR_B_D19
<8> DDR_B_MA3 A3 DQ18
.1U_0402_16V7K
164 257 DDR_B_MA4 128 63 DDR_B_D20
2.2U_0402_6.3V6M
+0.6V_DDRB_VREFCA VREFCA VPP1 259 +2.5V <8> DDR_B_MA4 DDR_B_MA5 126 A4 DQ19 46 DDR_B_D22
2 2 VPP2 <8> DDR_B_MA5 A5 DQ20
DDR_B_MA6 127 45 DDR_B_D18
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM <8> DDR_B_MA6 A6 DQ21
CD33
CD34
1 99 DDR_B_MA7 122 58 DDR_B_D23
2 VSS VSS 102 <8> DDR_B_MA7 DDR_B_MA8 125 A7 DQ22 59 DDR_B_D21
1 1 5 VSS VSS 103 <8> DDR_B_MA8 DDR_B_MA9 121 A8 DQ23 55 DDR_B_DQS2
VSS VSS <8> DDR_B_MA9 A9 DQS2(T) DDR_B_DQS2 <8>
SPD ADDRESS FOR CHANNEL B : 6
9 VSS VSS
106
107 <8> DDR_B_MA10
DDR_B_MA10
DDR_B_MA11
146
120 A10_AP DQS2#(C)
53 DDR_B_DQS#2
DDR_B_DQS#2 <8>
VSS VSS <8> DDR_B_MA11 A11
WRITE ADDRESS: 0XA4 PLACE NEAR TO PIN
10
14 VSS VSS
167
168 <8> DDR_B_MA12
DDR_B_MA12
DDR_B_MA13
119
158 A12 DQ24
70
71
DDR_B_D30
DDR_B_D27
VSS VSS <8> DDR_B_MA13 A13 DQ25
READ ADDRESS: 0XA3 15
18 VSS VSS
171
172 <8>
<8>
DDR_B_MA14_WE#
DDR_B_MA15_CAS#
DDR_B_MA14_WE#
DDR_B_MA15_CAS#
151
156 A14_WE# DQ26
83
84
DDR_B_D26
DDR_B_D24
VSS VSS DDR_B_MA16_RAS# A15_CAS# DQ27 DDR_B_D25
SA0 = 0; SA1 = 1; SA2 = 0. 19
22 VSS
VSS
VSS
VSS
175
176
<8> DDR_B_MA16_RAS#
152
A16_RAS# DQ28
DQ29
66
67 DDR_B_D28
23 180 DDR_B_ACT# 114 79 DDR_B_D29
DDR4 POR OPERATING SPEED: 1867 MT/S 26 VSS
VSS
VSS
VSS
181 <8> DDR_B_ACT# ACT# DQ30
DQ31
80 DDR_B_D31
27 184 DDR_B_PAR 143 76 DDR_B_DQS3
STRETCH GOAL IS 2133 MT/S 30 VSS
VSS
VSS
VSS
185 <8> DDR_B_PAR
<8> DDR_B_ALERT#
DDR_B_ALERT# 116 PARITY
ALERT#
DQS3(T)
DQS3#(C)
74 DDR_B_DQS#3 DDR_B_DQS3
DDR_B_DQS#3
<8>
<8>
31 188 2 RD18 1 DIMM3_CHB_EVENT# 134
C 35 VSS VSS 189 +1.2V_VDDQ 240_0402_1% DDR_DRAMRST#_R 108 EVENT# 174 DDR_B_D34 C
VSS VSS <18,23> DDR_DRAMRST#_R RESET# DQ32 DDR_B_D35
Layout Note: Layout Note: 36 192 173
39 VSS VSS 193 DQ33 187 DDR_B_D36
Place near JDIMM2.257,259 Place near JDIMM2.258 40 VSS VSS 196 254 DQ34 186 DDR_B_D32
VSS VSS <18,23> D_CK_SDATA SDA DQ35 DDR_B_D39
43 197 253 170
44 VSS VSS 201 <18,23> D_CK_SCLK SCL DQ36 169 DDR_B_D38
47 VSS VSS 202 SA2_CHB_DIM3 166 DQ37 183 DDR_B_D37
48 VSS VSS 205 SA1_CHB_DIM3 260 SA2 DQ38 182 DDR_B_D33
+2.5V +0.6VS_VTT 51 VSS VSS 206 SA0_CHB_DIM3 256 SA1 DQ39 179 DDR_B_DQS4
10uF*2 10uF*2 VSS VSS SA0 DQS4(T) DDR_B_DQS#4 DDR_B_DQS4 <8>
52 209 177
1uF*2 1uF*1 56 VSS VSS 210 DQS4#(C) DDR_B_DQS#4 <8>
57 VSS VSS 213 92 195 DDR_B_D40
VSS VSS CB0_NC DQ40
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
60 214 91 194 DDR_B_D41

1 1 1 1 1 1 1 VSS VSS CB1_NC DQ41
61 217 101 207 DDR_B_D42
VSS VSS CB2_NC DQ42
CD35
CD36
CD37
CD38
CD39
CD40
CD41
64 218 105 208 DDR_B_D43

65 VSS VSS 222 88 CB3_NC DQ43 191 DDR_B_D44
2 2 2 2 2 2 2 68 VSS VSS 223 87 CB4_NC DQ44 190 DDR_B_D45
69 VSS VSS 226
For ECC DIMM 100 CB5_NC DQ45 203 DDR_B_D47
72 VSS VSS 227 104 CB6_NC DQ46 204 DDR_B_D46
73 VSS VSS 230 97 CB7_NC DQ47 200 DDR_B_DQS5
VSS VSS DQS8(T) DQS5(T) DDR_B_DQS#5 DDR_B_DQS5 <8>
77 231 95 198
78 VSS VSS 234 DQS8#(C) DQS5#(C) DDR_B_DQS#5 <8>
81 VSS VSS 235 216 DDR_B_D48
82 VSS VSS 238 12 DQ48 215 DDR_B_D52
85 VSS VSS 239
+1.2V_VDDQ 33 DM0#/DBI0# DQ49 228 DDR_B_D50
86 VSS VSS 243 54 DM1#/DBI1# DQ50 229 DDR_B_D55
Layout Note:
PLACE THE CAP WITHIN 200 MILS Raptor 98 VSS
VSS
VSS
VSS
252 241 DM6#/DBI6#
DM7#/DBI7#
DQ55
DQS6(T)
221 DDR_B_DQS6
DDR_B_DQS#6 DDR_B_DQS6 <8>
96 219
FROM THE JDIMM2 DM8#/DBI8# DQS6#(C) DDR_B_DQS#6 <8>
262 261
GND GND
B DDR_DRAMRST#_R LOTES_ADDR0070-P009A 237 DDR_B_D61 B

DQ56 236 DDR_B_D57
CONN@ DQ57
+0.6V_DDRB_VREFCA
.1U_0402_16V7K
249 DDR_B_D60
2.2uF*1 DQ58 DDR_B_D56
2 250
0.1uF*1 XEMC@ DQ59 232 DDR_B_D59
DQ60
CD64
233 DDR_B_D62
2
CD42
2
CD43 1
Connector follow 2018V-VX DQ61
DQ62
245
246
DDR_B_D63
DDR_B_D58
DQ63 242 DDR_B_DQS7
.1U_0402_16V7K 2.2U_0402_6.3V6M DQS7(T) DDR_B_DQS7 <8>
1 1 +1.2V_VDDQ 240 DDR_B_DQS#7
DQS7#(C) DDR_B_DQS#7 <8>
LOTES_ADDR0070-P009A
CONN@
PLACE NEAR TO JDIMM2
2
Layout Note: DIMM Side CPU Side
2
CD44
Place near JDIMM2 @ RD19
.1U_0402_16V7K
1
1K_0402_1%
+0.6V_DDRB_VREFCA +0.6V_B_VREFDQ
1
10uF*6
1 RD20 2
+1.2V_VDDQ 1uF*8 +1.2V_VDDQ 2_0402_1%
330uF*1 VREF traces should be at least 20 mils
2 wide with 20 mils spacing to other
2
2 1
signals
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
RD21 CD45
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CD51 1K_0402_1% .1U_0402_16V7K CD55

1
CD46
CD47
CD48
CD49
CD50
CD52
CD53
CD54
.1U_0402_16V7K 0.022U_0402_16V7K
1 2
CD56
CD57
CD58
CD59
CD60
CD61
CD62
CD63
A A
2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
RD22
24.9_0402_1%
@ @
1
DDRIV_CHB: DIMM0
0.1
5 4 3 2 1
5 4 3 2 1
Raptor: use 1060 sequence +1.8VSDGPU_AON +3VS
1
+1.0VSDGPU
1
CG942 NGPK@ RG2879 UG9A
0.1U_0201_10V6K +3VS 10K_0201_5%
VGA@ 1/22 PCI_EXPRESS
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
2
CG1060
CG1061
CG1062
CG1063
CG1077
CG1078
CG1079
1 1 1 1 1 1 1 2 2 2
2
5
1
1.8VSDGPU_MAIN_EN3V3 BK44
CG5
CG14
CG7
CG1076
CG1080
1.8VSDGPU_MAIN_EN3V3 <37> +1.8VSDGPU_AON PEX_WAKE_N
RG2878 BB35
GND VCC
DGPU_HOLD_RST# 1 100K_0201_5% DGPU_PEX_RST# 1 @ 2 DGPU_PEX_RST#_R BK26 PEX_DVDD_1 BB36 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2
<19> DGPU_HOLD_RST# IN B 4 DGPU_PEX_RST# PEX_RST_N PEX_DVDD_2 BC35 2 2 2 2 2 2 2 1 1 1
VGA@ RG4 0_0402_5%
OUT Y PEX_DVDD_3
6
PLT_RST_BUF# 2 PEX_CLKREQ# BL26 BC36
2
<16,43,49,51,52,68> PLT_RST_BUF# IN A 2
D PEX_CLKREQ_N PEX_DVDD_4 BD33
G QG545B VGA@
UG105 BM26 PEX_DVDD_5 BD36
S
PJT138KA_SOT363-6 <15> CLK_PEG_VGA
2
NL17SZ08DFT2G_SC70-5 0809 NV PGOOD change to +1.8VS BM27 PEX_REFCLK PEX_DVDD_6
1
<15> CLK_PEG_VGA# PEX_REFCLK_N BB33
NGPK@ RG3 VGA@
PEX_CVDD_1
3
10K_0201_5% BG26 BC33
<9> PEG_CRX_C_GTX_P0
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
1.8VSDGPU_MAIN_EN 5
D
NV_PGOOD BH26 PEX_TX0 PEX_CVDD_2
CG1068
CG1069
CG1070
CG1071
CG1073
CG1072
CG1074
CG1075
CG1064
CG1065
CG1066
CG1067
1 1 1 1 1 1 1 1 1 1 1 1
G
S
<9> PEG_CRX_C_GTX_N0 PEX_TX0_N
1
QG545A BL27
4
<9> PEG_CTX_C_GRX_P0 PEX_RX0
2
VGA@ BK27 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
D <9> PEG_CTX_C_GRX_N0 PEX_RX0_N 2 2 2 2 2 2 2 2 2 2 2 2 D
RG3007 PJT138KA_SOT363-6 2
Gate BF26
100K_0201_5% <9> PEG_CRX_C_GTX_P1 PEX_TX1
@ 1 BE26 BB26
<15> VGA_CLKREQ# Drain <9> PEG_CRX_C_GTX_N1 PEX_TX1_N PEX_HVDD_1 BB27
1
1.8VSDGPU_MAIN_EN3V3 3 PEX_CLKREQ# BK29 PEX_HVDD_2 BB29
+1.8VSDGPU_AON Source <9> PEG_CTX_C_GRX_P1 PEX_RX1 PEX_HVDD_3
BL29 BB32
<9> PEG_CTX_C_GRX_N1 PEX_RX1_N PEX_HVDD_4 BC26 +1.8VSDGPU_MAIN
QG16
LBSS139WT1G_SC70-3 BF27 PEX_HVDD_5 BC27
1 <9> PEG_CRX_C_GTX_P2 PEX_TX2 PEX_HVDD_6
+3VS CG920 NGPK@ VGA@ BG27 BC29
<9> PEG_CRX_C_GTX_N2 PEX_TX2_N PEX_HVDD_7 BC30
UG103 NGPK@ 0.1U_0201_10V6K
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
PEX_HVDD_8
5
NL17SZ08DFT2G_SC70-5 BM29 BC32
CG1081
CG1083
CG1082
CG1084
CG1085
CG1086
CG1088
CG1087
CG1089
CG1090
<58> GPU_OVERT# 2 <9> PEG_CTX_C_GRX_P2 PEX_RX2 PEX_HVDD_9 1 1 1 1 1 1 1 1 1 1
BM30 BD27
GND VCC
<9> PEG_CTX_C_GRX_N2 PEX_RX2_N PEX_HVDD_10
1 BD30
<19,37> DGPU_PWR_EN
2 IN B 4 RG202 1 @ 2 0_0201_5% 1VSDGPU_EN_1V8 BG29 PEX_HVDD_11 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
1 2 2 OUT Y <9> PEG_CRX_C_GTX_P3 BH29 PEX_TX3 2 2 2 2 2 2 2 2 2 2
+1.8VSDGPU_AON +1.8VSDGPU_MAIN RG183
IN A <9> PEG_CRX_C_GTX_N3 PEX_TX3_N
10K_0201_5% DG4
NGPK@ RB751S40T1G_SOD523-2 DG3 NGPK@ BL30
RB751S40T1G_SOD523-2 BK30
1
3
<9> PEG_CTX_C_GRX_N3
2
1 2 1 2 PEX_RX3_N
1
RG39 RG182 RG190 1 NFGC6@ BF29

<9> PEG_CRX_C_GTX_P4 PEX_TX4
10K_0201_5% 100K_0201_5% NGPK@ 20K_0402_1% 1 2 BE29
VGA@ NGPK@ NGPK@ CG928 NGPK@ RG2994 0_0201_5%
6
0.22U_0402_16V7K BK32
1
2
D
2 DG28 <9> PEG_CTX_C_GRX_P4 BL32 PEX_RX4
G
QG12B
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
1VSDGPU_EN_3V3 2 <9> PEG_CTX_C_GRX_N4 PEX_RX4_N
S
PJT138KA_SOT363-6 1 1 2 2 2
1
NGPK@ 1 BF30
CG20
CG11
CG12
CG21
CG24
CG1093
CG1094
1
GPU_FB_EN_FGC6_AND_3V3 3 1VSDGPU_EN <37,99> <9> PEG_CRX_C_GTX_P5 BG30 PEX_TX5

@
3
DG23 BB30 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2
OVERT# 5 G
D
QG12A RB751S40T1G_SOD523-2 BAV70W_SOT323-3 BM32 PEX_PLL_HVDD 2 2 1 1 1
<9> PEG_CTX_C_GRX_P5 BM33 PEX_RX5
S
PJT138KA_SOT363-6 FGC6@ <9> PEG_CTX_C_GRX_N5 PEX_RX5_N
NGPK@ 2 1
4
NVVDD1_EN <37,93> BG32

BH32
0803 NV reivew del NVPG protect circuit

1
RG191
2
15K_0402_1%
1
1.0VSDGPU_EN_FGC6 <9> PEG_CTX_C_GRX_P6
<9> PEG_CTX_C_GRX_N6
BL33
BK33 PEX_RX6
PEX_RX6_N
NGPK@ CG929 NGPK@ BF32
<9> PEG_CRX_C_GTX_P7 BE32 PEX_TX7
.1U_0402_16V7K <9> PEG_CRX_C_GTX_N7 PEX_TX7_N
2 +1.8VSDGPU_AON
BK35
<9> PEG_CTX_C_GRX_P7 BL35 PEX_RX7 +PEX_PLL_HVDD 1 2
@ +1.8VSDGPU_MAIN
<9> PEG_CTX_C_GRX_N7 PEX_RX7_N RG3001 0_0402_5%
BF33
0.47U_0201_4VAN
0.47U_0201_4VAN
4.7U_0402_6.3V6M
DG22 <9> PEG_CRX_C_GTX_P8 BG33 PEX_TX8
CG1095
CG1096
<9> PEG_CRX_C_GTX_N8 PEX_TX8_N 1 1 1
1VSDGPU_PG 2
CG1097
<99> 1VSDGPU_PG 1 BM35
1.35VSDGPU_EN <37,98> <9> PEG_CTX_C_GRX_P8
+3VS GC6_FB_EN3V3 3
to EC <9> PEG_CTX_C_GRX_N8
BM36 PEX_RX8 VGA@ VGA@ VGA@
5
QG6A PEX_RX8_N 2 2 2 0803 NV reivew
BAV70W_SOT323-3 RG29 NGPK@ PJT138KA 2N SOT363-6 BG35
G
1
C
100K_0201_5% VGA_SMB_CK2 4 3 BH35 C
NGPK@ EC_SMB_CK2 <18,38,58,66,73> <9> PEG_CRX_C_GTX_N9 PEX_TX9_N DGPU_ENVDD
D
RG31
2
+3VS 10K_0201_5% VGA@ BL36
2
<9> PEG_CTX_C_GRX_P9 BK36 PEX_RX9
NGPK@ QG6B
G
VGA_SMB_DA2 1 6 PJT138KA 2N SOT363-6 <9> PEG_CTX_C_GRX_N9 PEX_RX9_N
2
EC_SMB_DA2 <18,38,58,66,73>
1
+3VS
D
BF35
GC6_FB_EN3V3 <19,37> <9> PEG_CRX_C_GTX_P10 BE35 PEX_TX10
RG34 VGA@ <9> PEG_CRX_C_GTX_N10 PEX_TX10_N +1.8VSDGPU_AON
100K_0201_5%
1
NGPK@ BK38
6
BL38 RG517
2
<9> PEG_CTX_C_GRX_N10 PEX_RX10_N
1
2
D
G QG14B NGPK@ 10K_0201_5%
BF36 QG523
S
PJT138KA_SOT363-6 RG502 VGA@
BG36 10K_0201_5% 2
1
2
<9> PEG_CRX_C_GTX_N11 PEX_TX11_N Gate
3
BM38 1
2
GPU_GC6_FB_EN <9> PEG_CTX_C_GRX_P11 PEX_RX11 Drain G-SYNC# <38>
5
D
G +1.8VSDGPU_AON BM39
S
<9> PEG_CTX_C_GRX_N11 PEX_RX11_N FRAME_LOCK# VGA@ 3
NGPK@ QG14A BG38 Source
4
0.1U_0201_10V6K
PJT138KA_SOT363-6 1 BH38
<9> PEG_CRX_C_GTX_N12 PEX_TX12_N LBSS139WT1G_SC70-3
CG2812
FGC6@
BL39 VGA@
<9> PEG_CTX_C_GRX_P12 BK39 PEX_RX12
5
2
FP_FUSE, change to GS7616 follow CRB BF38
GND VCC
GPU_GC6_FB_EN 1 <9> PEG_CRX_C_GTX_P13 BE38 PEX_TX13
+1.8VSDGPU_AON IN B GPU_FB_EN_FGC6_AND <9> PEG_CRX_C_GTX_N13 PEX_TX13_N
4
GPU_GPIO20_FGC6 2 OUT Y BK41 +3VS
IN A <9> PEG_CTX_C_GRX_P13 PEX_RX13 +3VS
BL41
1
1
CG1176 BF39
3
2.2U_0402_6.3V6M UG109 FGC6@ BG39 RG704
<9> PEG_CRX_C_GTX_N14
1
VGA@ NL17SZ08DFT2G_SC70-5 PEX_TX14_N 10K_0201_5%
2 UC5 BM41 RG794
6 1 FP_FUSE_GPU <9> PEG_CTX_C_GRX_P14 BM42 PEX_RX14
100K_0201_5%
2
5 VIN1 VOUT1 2 FP_FUSE_GPU <30> <9> PEG_CTX_C_GRX_N14 PEX_RX14_N
VIN2 VOUT2 VGA@ DGPU_ENBKL <38>
1
1 BH41
2
<9> PEG_CRX_C_GTX_P15
6
4 3 CG1178 RG2836 BG41 PEX_TX15
VSS EN <9> PEG_CRX_C_GTX_N15 PEX_TX15_N VGA@ GPU_ENBKL#
2
D
2.2U_0402_6.3V6M 2.21K_0402_1% G QG526B
GS7616SC-R_SOT363-6 VGA@ VGA@ BL42 BL44 2 1 S
PJT138KA 2N SOT363-6
2 <9> PEG_CTX_C_GRX_P15 BK42 PEX_RX15 PEX_TERMP
2
1
3
RG23
GPU_ENBKL 5
D VGA@
RG10 2.49K_0402_1% G
QG526A
GPIO26_FP_FUSE 2 1 GPIO26_FP_FUSE_R +1.8VSDGPU_AON
to NVVDD controller NV_PGOOD VGA@ S
4
0_0402_5% 1 N18E-G3-ES-A1_FCBGA2228
VGA@
2
@ +3VS +3VS +1.8VS @

10K_0201_5%
VGA@
CG1179
RG2837
VGA@ 0.1U_0201_10V6K
2
1
10K_0201_5%
10K_0201_5%
1
1
1
B B
NV Carter0822 : unstuff, ALERT# no function no need
10K_0201_5%
5
QG547A RG2840 RG2841 CG1180 VGA@

PJT138KA 2N SOT363-6 @ @ RG2842
G
.1U_0402_16V7K
VGA_I2CC_SCL 4 3 UV2 2 VGA@ DGPU_PEX_RST#
0.2
2
VGA_I2CC_SCL_PWR <93>
S
VGA@
2
2
5
VGA@ MC74VHC1G09DFT2G_SC70-5
QG547B 1VSDGPU_PG 1 +1.8VSDGPU_AON QG15
eDP HPD
G
Raptor:Low active
G VCC
VGA_I2CC_SDA 1 6 PJT138KA 2N SOT363-6 B 4 NV_PGOOD 2
VGA_I2CC_SDA_PWR <93> NVVDD1_PG Y Gate
S
UG9T 2
<93> NVVDD1_PG A
1
12/22 MISC 1 VGA@ 1
Drain GPU_ALERT <58>
RG807
3
10K_0402_5% ALERT# 3
OVERT# BG5 BJ8 VGA_SMB_CK2 VGA@ Source
OVERT I2CS_SCL BH8 VGA_SMB_DA2 +1.8VSDGPU_AON LBSS139WT1G_SC70-3
2
I2CS_SDA
@
BF12 +1.8VSDGPU_AON DGPU_EDP_HPD#
TS_VREF
I2CC_SCL
BG9
BH9
VGA_I2CC_SCL
VGA_I2CC_SDA
RG11
RG12
2 VGA@
2 VGA@
1 2.2K_0402_5%
1 2.2K_0402_5% PG pull up at PWR side
1
I2CC_SDA D
QG527 2 DGPU_EDP_HPD
1.8VSDGPU_MAIN_EN DGPU_EDP_HPD <38,41>
BG8 RG19 2 VGA@ 1 2.2K_0402_5% RG2884 1 VGA@ 2 10K_0201_5% +3VS +3VS L2N7002LT1G_SOT23-3 G
I2CB_SCL BF8 RG20 2 VGA@ 1 2.2K_0402_5% S
3
I2CB_SDA
1
GPU_EVENT#_D RG8 1 VGA@ 2 10K_0201_5%
VGA@
1
RG2845 RG2766 GPIO12 2 1
DGPU_AC_DETECT <19,58,82>
1
BJ1 GPIO12 RG2887 1 VGA@ 2 10K_0201_5% RG2844 10K_0201_5% 100K_0402_5%
BJ2
THERMDN
DG use 2.2K VGA_SMB_CK2 RG17 1 VGA@ 2 1.8K_0402_5%
10K_0201_5%
@
VGA@
VGA@
DG18
RB751S40T1G_SOD523-2
2
THERMDP
6
VGA@
2
VGA_SMB_DA2 RG18 1 VGA@ 2 1.8K_0402_5% 2 G
D
QG539B
2
S
PJT138KA_SOT363-6
BD6 NVVDD_VID VGA@
1
GPIO0 BB5 GPU_GC6_FB_EN NVVDD_VID <93>
GPIO1
3
BD1 GPU_EVENT#_D 2 1 NVVDD_PSI RG15 1 VGA@ 2 10K_0201_5%
BJ9 GPIO2 BE4 GPU_EVENT# <19> 1.35VSDGPU_PG 5 G
D
QG539A
PU +LCDVDD on panel side
<22> ADC_IN_P BJ11 ADC_IN GPIO3 BE1 1.8VSDGPU_MAIN_EN 1 VGA@ 2 <37,98> 1.35VSDGPU_PG
DG2 ALERT# RG504 10K_0201_5% S
PJT138KA_SOT363-6
<22> ADC_IN_N ADC_IN_N GPIO4 FRAME_LOCK# 1.8VSDGPU_MAIN_EN <37> +3VS
BG2 RB751S40T1G_SOD523-2 VGA@
4
GPIO5 BD2 NVVDD_PSI GPIO28_OC_WARN# RG692 1 VGA@ 2 10K_0201_5% +3VS
GPIO6 NVVDD_PSI <93> VGA@
BD7 GPU_INV_PWM
1
GPIO7 BH4 VRAM_VDD_CTL FBVDDQ_PSI RG2952 1 VGA@ 2 10K_0201_5%
GPIO8 VRAM_VDD_CTL <98>
1
BJ3 ALERT# RG2852
GPIO9 BD3 MEM_VREF VRAM_VDD_CTL RG2953 1 @ 2 10K_0201_5% +3VS 10K_0201_5%
JTAG_TCLK BK24 GPIO10 BH3 DGPU_ENVDD MEM_VREF <33,34,35,36> +3VS
@ T59 PAD~D VGA@ RG2784
JTAG_TMS JTAG_TCK GPIO11 DGPU_ENVDD <38> GPU_GPIO15
@ T60 PAD~D BL23 BE6 GPIO12 RG3002 1 VGA@ 2 10K_0201_5% 2.2K_0402_5% @
2
1
@ T61 PAD~D JTAG_TDI BM23 JTAG_TMS GPIO12 BB1 1VSDGPU_EN_3V3
2
JTAG_TDI GPIO13
1
@ T62 PAD~D JTAG_TDO BM24 BG4 GPU_DP0_HPD# GPU_GPIO22 RG3003 2 VGA@ 1 2.2K_0402_5% RG2853
JTAG_TRST# JTAG_TDO GPIO14 GPU_GPIO15 GPU_DP0_HPD# <39> +3VS
1 2 BL24 BG1 100K_0201_5% RG2783
JTAG_TRST_N GPIO15 BE2 DGPU_INV_PWM <38>
VGA@ 100K_0201_5%
GPIO16
6
RG518 BH1 DGPU_EDP_HPD# VRAM_VDD_CTL RG2954 1 @ 2 10K_0201_5% VGA@
2
1
6
10K_0201_5% GPIO17 BE3 GPU_DP4_HPD# 2 G
D
QG543B VGA@
2
BK23 GPIO18 BD4 GPU_DP4_HPD# <43> GPU_GPIO20_FGC6 RG2888 1 VGA@ 2 2
D
VGA@ 10K_0201_5% RG2851 S

PJT138KA_SOT363-6 G QG531B VGA@
A NVJTAG_SEL GPIO19 BE5 GPU_GPIO20_FGC6 +3VS 10K_0201_5% A
S
PJT138KA_SOT363-6
1
GPIO20 BA5 GPU_ENBKL GPU_GC6_FB_EN RG22 1 VGA@ 2 10K_0201_5% FGC6@
1
GPIO21
3
BB6 GPU_GPIO22
PWR check the FBVDDQ_PSI if need
2
1
3
GPIO22 BG3 GPU_GPIO23 MEM_VREF RG2885 1 VGA@ 2 1K_0402_5% GPU_FB_EN_FGC6_AND_3V3 1VSDGPU_EN_1V8 5 G
D
RG26
10K_0201_5%
GPIO23
GPIO24
BD5
BB2
GPU_DP5_HPD#
FBVDDQ_PSI GPU_DP5_HPD# <49> N17E 1M DGPU_PEX_RST# RG25 1 VGA@ 2 100K_0201_5%
RG2850
100K_0201_5%
GPU_FB_EN_FGC6_AND_3V3 <37> S VGA@
QG543A
GPU_INV_PWM 5 G
D
4
FBVDDQ_PSI <98>
2
VGA@ GPIO25 BE7 GPIO26_FP_FUSE FGC6@ PJT138KA_SOT363-6 VGA@ QG531A
4
GPIO26
6
BA4 HDMI_HPD_GPU# GPU_INV_PWM RG150 1 VGA@ 2 100K_0201_5% RG3006 PJT138KA_SOT363-6
2
GPIO27 BB4 GPIO28_OC_WARN# HDMI_HPD_GPU# <40> 2

D
G
QG542B FGC6@ 100K_0201_5%
GPIO28 BA3 GPIO29_IDLE_IN_SW GPIO28_OC_WARN# <22> DGPU_ENVDD RG2886 1 VGA@ 2 10K_0201_5% S
PJT138KA_SOT363-6 @
GPIO29 BB3
1
1
GPIO30 0803 NV reivew, and need FAE double check DG GPU_ENBKL RG501 1 VGA@ 2 100K_0201_5%
3
GPU_GPIO23 RG3004 1 VGA@ 2 100K_0201_5% GPU_FB_EN_FGC6_AND 5 G

D
FGC6@
4
2
N18E-G3-ES-A1_FCBGA2228 GPIO29_IDLE_IN_SW RG2883 1 VGA@ 2 10K_0201_5% QG542A

@ RG3005 PJT138KA_SOT363-6
100K_0201_5% Issued Date 2017/11/23 Deciphered Date 2017/12/31 Title
@
N18E-G3(1/8) PCIE,GPIO
1
NV checking function THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number
EH78F M/B LA-G161PR01

Rev
0.1

5 4 3 2 1
5 4 3 2 1
UG9N
7/22 IFPAB
DL-DVI DVI/HDMI DP DP0-DP VGA@

UG9Q
10/22 IFPE DP4-TBT
DVI/HDMI DP
RG38
BH11 1K_0402_1%
SDA SDA IFPA_AUX_SDA_N DP0_AUXN <39> IFPEF_RSET
BG11 2 1 BD17 SDA
BL8
SCL SCL IFPA_AUX_SCL DP0_AUXP <39> IFPE_RSET IFPE_AUX_SDA_N BK8 DP4_AUXN <42,43>
SCL IFPE_AUX_SCL DP4_AUXP <42,43>
RG679
1K_0402_1% BF21 DP0_TXN3 <39>
2 1 IFPAB_RSET BD23 TXC TXC IFPA_L3_N BG21 BG14
IFPAB_RSET TXC TXC IFPA_L3 DP0_TXP3 <39> TXC IFPE_L3_N DP4_TXN3 <42>
BD15 BH14
+GPU_PLLVDD_XS_SP IFPE_PLLVDD TXC IFPE_L3 DP4_TXP3 <42>
VGA@
0.47U_0201_4VAN
BG23 BF14
CG1228
D TXD0 TXD0 IFPA_L2_N DP0_TXN2 <39> 1 TXD0 IFPE_L2_N DP4_TXN2 <42> D
TXD0 TXD0
BH23 DP0_TXP2 <39> TXD0 BE14 DP4_TXP2 <42>
BD21 IFPA_L2 IFPE_L2
+GPU_PLLVDD_XS_SP IFPAB_PLLVDD VGA@ BF15
0.47U_0201_4VAN
2 TXD1 IFPE_L1_N DP4_TXN1 <42>
BF23 BG15
CG1227
1 TXD1 TXD1 IFPA_L1_N DP0_TXN1 <39> TXD1 IFPE_L1 DP4_TXP1 <42>
TXD1 TXD1 IFPA_L1
BE23 DP0_TXP1 <39> IFPE
BG17 DP4_TXN0 <42>
TXD2 IFPE_L0_N
VGA@ TXD2 BH17 DP4_TXP0 <42>
2 BF24 IFPE_L0
TXD2 TXD2 IFPA_L0_N DP0_TXN0 <39>
BG24
TXD2 TXD2 IFPA_L0 DP0_TXP0 <39>
+1.0VSDGPU
BC21
BC23 IFP_IOVDD_9
4.7U_0402_6.3V6M
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
IFP_IOVDD_10
CG1196
CG1197
CG1198
1 1 1 1
CG1195
Under GPU SDA IFPB_AUX_SDA_N
BG12
BH12
VGA_NV_MASTER_SDA
VGA_NV_MASTER_SCL
VGA@
2
VGA@
2
VGA@
2
VGA@
2
N18E-G3-ES-A1_FCBGA2228 Raptor
SCL IFPB_AUX_SCL @
BL18 DP4_AUXN
BB18 TXC IFPB_L3_N BK18
+1.0VSDGPU IFP_IOVDD_2 TXC IFPB_L3
BB17 DP4_AUXP
4.7U_0402_6.3V6M
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
IFP_IOVDD_1
CG1184
CG1185
CG1186
CG1187
1 1 1 1 1
1
BB20 BK20
CG1188
IFP_IOVDD_3 TXD3 TXD0 IFPB_L2_N

BB21 BL20 RG2839 RG2838
VGA@
2
VGA@
2
VGA@
2
VGA@
2
VGA@
2
IFP_IOVDD_4 TXD3 TXD0 IFPB_L2 Raptor 100K_0402_5% 100K_0402_5%
VGA@ VGA@
BM20
2
TXD4 TXD1 IFPB_L1_N BM21
TXD4 TXD1 IFPB_L1 DP0_AUXN
BL21 DP0_AUXP
TXD5 TXD2 IFPB_L0_N
TXD5 TXD2
BK21
IFPB_L0
1
C
IFPAB RG2767 RG2768
C
100K_0402_5% 100K_0402_5%
@ @
N18E-G3-ES-A1_FCBGA2228
2
+1.8VSDGPU_AON
@
+1.8VSDGPU_AON
2.2K_0402_5%
2.2K_0402_5%
1
1
+1.0VSDGPU
RG2824
RG2823
22U_0603_6.3V6M
10U_0402_6.3V6M
4.7U_0402_6.3V6M
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
5
QG535A
CG1207
CG1200
CG1201
CG1202
CG1203
CG1204
CG1205
2 1 1 1 1 1 1 1
2
1
CG1206
CG1199
G
VGA_NV_MASTER_SDA VGA@ VGA@ 4 3 NV_MASTER_SDA
NV_MASTER_SDA <49>
D
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2
2
1 2 2 2 2 2 2 2 VGA@
UG9R
G
6/22 IFPF/USB-C AC cap on 7440 side VGA_NV_MASTER_SCL 1 6 NV_MASTER_SCL
NV_MASTER_SCL <49>
D
USB-C DP VGA@ QG535B
+1.8VSDGPU_AON BB15 BM9

BC15 USB_DVDD_1
USB_DVDD_2
SBU2
SBU1
IFPF_AUX_SDA_N
IFPF_AUX_SCL
BM8 DP5_AUXN
DP5_AUXP
<47>
<47>
USB-C_GPU master
22U_0603_6.3V6M
10U_0402_6.3V6M
4.7U_0402_6.3V6M
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
CG1212
CG1209
CG1210
CG1211
2 1 1 1 1
1
BK11
CG1213
CG1208
RX1 IFPF_L3_N DP5_TXN3 <47> +1.8VSDGPU_AON

BL11 DP5_TXP3 <47>
RX1 IFPF_L3
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2
1 2 2 2 2 BM11 +1.8VSDGPU_AON
TX1 IFPF_L2_N DP5_TXN2 <47>
BM12 DP5_TXP2 <47>
TX1 IFPF_L2
B B
BL12 DP5_TXN1 <47>
TX2 IFPF_L1_N BK12
TX2 IFPF_L1 DP5_TXP1 <47>
AW10
2.2K_0402_5%
2.2K_0402_5%
USB_HVDD_1
1
AW11 BK14 DP5_TXN0 <47>
USB_HVDD_2 RX2 IFPF_L0_N BL14
RG2822
RG2821
RX2 IFPF_L0 DP5_TXP0 <47>
AW9
0.47U_0201_4VAN
0.47U_0201_4VAN
USB_PLL_HVDD
CG1214
CG1215
1 1
5
QG534A
2
BA1 PJT138KA 2N SOT363-6
G
USB_L0_N NV_SSTXN <46> VGA_CCG4_MASTER_SDA CCG4_MASTER_SDA
VGA@ VGA@ BA2 NV_SSTXP <46> VGA@ VGA@ 4 3
2 2 USB_L0 CCG4_MASTER_SDA <46,47,48,49,100>
D
2
BA7 VGA@
USB_L1_N NV_SSRXN <46>
BA8
G
+3VSDGPU USB_L1 NV_SSRXP <46> VGA_CCG4_MASTER_SCL CCG4_MASTER_SCL
1 6
CCG4_MASTER_SCL <46,47,48,49,100>
D
BE12
USB_VDDP
VGA@ QG534B
1U_0201_6.3V6M
4.7U_0402_6.3V6M
0.47U_0201_4VAN
0.47U_0201_4VAN
CG1216
CG1218
1 1 1 1
CG1217
CG1219
USB-C_GPU Slave
VGA@ VGA@ VGA@ VGA@
2 2 2 2
Raptor
BB8 VGA_CCG4_MASTER_SCL
USB_SCL BB7 VGA_CCG4_MASTER_SDA
VGA@ USB_SDA
RG2854 1 2 2.49K_0402_1% BG6 DP5_AUXN
VGA@ USB_TERMP0
RG2855 1 2 2.49K_0402_1% BH6 DP5_AUXP
VGA@ USB_TERMP1
1
RG2856 1 2 1K_0402_5% BA6
USB_RBIAS
IFPF/USB-C RG2769 RG2770
100K_0402_5% 100K_0402_5%
A @ @ A
2
@

N18E-G3(2/8) DP
0.1
5 4 3 2 1
5 4 3 2 1
UG9O
RG37 8/22 IFPC
1K_0402_1%
2 1 IFPCD_RSET BD20
IFPCD_RSET
DVI/HDMI DP
VGA@
D +GPU_PLLVDD_XS_SP BD18 BL9 D

IFPCD_PLLVDD SDA IFPC_AUX_SDA_N GPU_DP2_CTRL_DAT <40>
BK9
0.47U_0201_4VAN
SCL IFPC_AUX_SCL GPU_DP2_CTRL_CLK <40>
CG1229
1
TXC
BF17
IFPC_L3_N GPU_DP2_N3 <40>
VGA@ TXC
BE17
2 IFPC_L3 GPU_DP2_P3 <40>
BF18 GPU_DP2_N2 <40>
IFPC
TXD0
TXD0
IFPC_L2_N
IFPC_L2
BG18
BG20
GPU_DP2_P2 <40> HDMI 2.0
TXD1 IFPC_L1_N GPU_DP2_N1 <40>
TXD1 BH20 GPU_DP2_P1 <40>
IFPC_L1
BF20 GPU_DP2_N0 <40>
TXD2 IFPC_L0_N BE20
TXD2 IFPC_L0 GPU_DP2_P0 <40>
+1.0VSDGPU BB23
BC17 IFP_IOVDD_5
4.7U_0402_6.3V6M
0.47U_0201_4VAN
0.47U_0201_4VAN
IFP_IOVDD_6
CG1189
CG1191
1 1 1
CG1190
VGA@ VGA@ VGA@ @
2 2 2
C C
UG9P
9/22 IFPD
DVI/HDMI DP
Under GPU BF11 GPU_EDP_AUXN

SDA IFPD_AUX_SDA_N GPU_EDP_AUXP GPU_EDP_AUXN <38>
BE11
SCL IFPD_AUX_SCL GPU_EDP_AUXP <38>
BM14 GPU_EDP_TXN3
TXC IFPD_L3_N GPU_EDP_TXN3 <41>
BM15 GPU_EDP_TXP3
TXC IFPD_L3 GPU_EDP_TXP3 <41>
TXD0
TXD0
IFPD_L2_N
IFPD_L2
BL15
BK15
GPU_EDP_TXN2
GPU_EDP_TXP2
GPU_EDP_TXN2 <41>
GPU_EDP_TXP2 <41>
eDP
IFPD BK17 GPU_EDP_TXN1
TXD1 IFPD_L1_N GPU_EDP_TXN1 <41>
TXD1 BL17 GPU_EDP_TXP1
IFPD_L1 GPU_EDP_TXP1 <41>
B BM17 GPU_EDP_TXN0 B
TXD2 IFPD_L0_N GPU_EDP_TXN0 <41>
BM18 GPU_EDP_TXP0
TXD2 IFPD_L0 GPU_EDP_TXP0 <41>
+1.0VSDGPU BC18
BC20 IFP_IOVDD_7
4.7U_0402_6.3V6M
0.47U_0201_4VAN
0.47U_0201_4VAN
IFP_IOVDD_8
CG1192
CG1194
1 1 1
CG1193
VGA@ VGA@ VGA@ @
2 2 2
Raptor
GPU_EDP_AUXN
GPU_EDP_AUXP
1
RG2968 RG2969
100K_0402_5% 100K_0402_5%
VGA@ VGA@
2
A A

N18E-G3(3/8) eDP,HDMI
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
5 4 3 2 1
5 4 3 2 1
D D
UG9B UG9C UG9D UG9E

2/22 FBA 3/22 FBB 4/22 FBC 5/22 FBD
U51 Y51 H32 B35 C6 C11 AK8 AD2

<33> FBA_D0 FBA_D0 FBA_CMD0 FBA_CMD1 FBA_CMD0 <33> <34> FBB_D0 FBB_D0 FBB_CMD0 FBB_CMD1 FBB_CMD0 <34> <35> FBC_D0 FBC_D0 FBC_CMD0 FBC_CMD1 FBC_CMD0 <35> <36> FBD_D0 FBD_D0 FBD_CMD0 FBD_CMD1 FBD_CMD0 <36>
U48 Y52 D32 A35 D6 B11 AK4 AD1
<33> FBA_D1 FBA_D1 FBA_CMD1 FBA_CMD2 FBA_CMD1 <33> <34> FBB_D1 FBB_D1 FBB_CMD1 FBB_CMD2 FBB_CMD1 <34> <35> FBC_D1 FBC_D1 FBC_CMD1 FBC_CMD2 FBC_CMD1 <35> <36> FBD_D1 FBD_D1 FBD_CMD1 FBD_CMD2 FBD_CMD1 <36>
U50 Y49 A33 D35 A6 A11 AK2 AD4
<33> FBA_D2 U49 FBA_D2 FBA_CMD2 AA52 FBA_CMD2 <33> <34> FBB_D2 B32 FBB_D2 FBB_CMD2 A36 FBB_CMD2 <34> <35> FBC_D2 B6 FBC_D2 FBC_CMD2 D11 FBC_CMD2 <35> <36> FBD_D2 AK3 FBD_D2 FBD_CMD2 AC1 FBD_CMD2 <36>
<33> FBA_D3 FBA_D3 FBA_CMD3 FBA_CMD3 <33> <34> FBB_D3 FBB_D3 FBB_CMD3 FBB_CMD3 <34> <35> FBC_D3 FBC_D3 FBC_CMD3 FBC_CMD3 <35> <36> FBD_D3 FBD_D3 FBD_CMD3 FBD_CMD3 <36>
R51 AA51 E32 B36 B4 A12 AK5 AC2
R50 AA50 G32 C36 A4 B12 AK6 AC3
R47 AC50 J30 C38 B3 C12 AK9 AA3
U46 AC51 F32 B38 C4 C14 AK7 AA2
<33> FBA_D7 V46 FBA_D7 FBA_CMD7 AC52 FBA_CMD7 <33> <34> FBB_D7 H36 FBB_D7 FBB_CMD7 A38 FBB_CMD7 <34> <35> FBC_D7 D9 FBC_D7 FBC_CMD7 B14 FBC_CMD7 <35> <36> FBD_D7 AG4 FBD_D7 FBD_CMD7 AA1 FBD_CMD7 <36>
<33> FBA_D8 Y45 FBA_D8 FBA_CMD8 AC49 FBA_CMD8 <33> <34> FBB_D8 G36 FBB_D8 FBB_CMD8 D38 FBB_CMD8 <34> <35> FBC_D8 C9 FBC_D8 FBC_CMD8 A14 FBC_CMD8 <35> <36> FBD_D8 AF9 FBD_D8 FBD_CMD8 AA4 FBD_CMD8 <36>
<33> FBA_D9 Y47 FBA_D9 FBA_CMD9 AD52 FBA_CMD9 <33> <34> FBB_D9 J36 FBB_D9 FBB_CMD9 A39 FBB_CMD9 <34> <35> FBC_D9 E9 FBC_D9 FBC_CMD9 D14 FBC_CMD9 <35> <36> FBD_D9 AG6 FBD_D9 FBD_CMD9 Y1 FBD_CMD9 <36>
Y46 AD51 F36 B39 B9 A15 AG7 Y2
V50 AD50 F33 C39 B8 B15 AJ4 Y3
<33> FBA_D12 V47 FBA_D12 FBA_CMD12 AF50 FBA_CMD12 <33> <34> FBB_D12 D33 FBB_D12 FBB_CMD12 C41 FBB_CMD12 <34> <35> FBC_D12 A8 FBC_D12 FBC_CMD12 C15 FBC_CMD12 <35> <36> FBD_D12 AJ5 FBD_D12 FBD_CMD12 V3 FBD_CMD12 <36>
U52 AF51 J32 B41 F6 C17 AJ6 V2
V51 AF52 G33 A41 E6 B17 AG5 V1
AJ44 AN50 E45 B49 F18 B24 Y6 L3
<33> FBA_D16 AG48 FBA_D16 FBA_CMD16 AN51 FBA_CMD17 FBA_CMD16 <33> <34> FBB_D16 D45 FBB_D16 FBB_CMD16 A49 FBB_CMD17 FBB_CMD16 <34> <35> FBC_D16 G18 FBC_D16 FBC_CMD16 A24 FBC_CMD17 FBC_CMD16 <35> <36> FBD_D16 Y5 FBD_D16 FBD_CMD16 L2 FBD_CMD17 FBD_CMD16 <36>
<33> FBA_D17 AJ45 FBA_D17 FBA_CMD17 AN52 FBA_CMD18 FBA_CMD17 <33> <34> FBB_D17 F45 FBB_D17 FBB_CMD17 A48 FBB_CMD18 FBB_CMD17 <34> <35> FBC_D17 E18 FBC_D17 FBC_CMD17 D23 FBC_CMD18 FBC_CMD17 <35> <36> FBD_D17 V5 FBD_D17 FBD_CMD17 L1 FBD_CMD18 FBD_CMD17 <36>
AG49 AM49 G45 D47 H18 A23 Y4 M4
AF46 AM52 D42 A47 D15 B23 AA6 M1
AF47 AM51 E42 B47 E15 C23 AA5 M2
AF48 AM50 F42 C47 G17 C21 AC5 M3
<33> FBA_D22 AD47 FBA_D22 FBA_CMD22 AK50 FBA_CMD22 <33> <34> FBB_D22 H41 FBB_D22 FBB_CMD22 C45 FBB_CMD22 <34> <35> FBC_D22 H17 FBC_D22 FBC_CMD22 B21 FBC_CMD22 <35> <36> FBD_D22 AC4 FBD_D22 FBD_CMD22 P3 FBD_CMD22 <36>
AD49 AK51 E41 B45 J15 A21 AD7 P2
AD48 AK52 F39 A45 H15 D20 AC6 P1
AC46 AJ49 E39 D44 E14 A20 AF6 R4
AC47 AJ52 D39 A44 F14 B20 AD6 R1
<33> FBA_D27 AA47 FBA_D27 FBA_CMD27 AJ51 FBA_CMD27 <33> <34> FBB_D27 F38 FBB_D27 FBB_CMD27 B44 FBB_CMD27 <34> <35> FBC_D27 H11 FBC_D27 FBC_CMD27 C20 FBC_CMD27 <35> <36> FBD_D27 AF7 FBD_D27 FBD_CMD27 R2 FBD_CMD27 <36>
AA46 AJ50 E38 C44 G11 C18 AF8 R3
AA45 AG50 D36 C42 F11 B18 AF2 U3
<33> FBA_D30 Y44 FBA_D30 FBA_CMD30 AG51 FBA_CMD30 <33> +1.35VSDGPU <34> FBB_D30 E36 FBB_D30 FBB_CMD30 B42 FBB_CMD30 <34> +1.35VSDGPU <35> FBC_D30 E11 FBC_D30 FBC_CMD30 A18 FBC_CMD30 <35> +1.35VSDGPU <36> FBD_D30 AF3 FBD_D30 FBD_CMD30 U2 FBD_CMD30 <36> +1.35VSDGPU
AW51 AF49 M50 D41 J29 A17 F4 V4
<33> FBA_D32 BA52 FBA_D32 FBA_CMD32 AG52 FBA_CMD32 <33> <34> FBB_D32 P48 FBB_D32 FBB_CMD32 A42 FBB_CMD32 <34> <35> FBC_D32 F30 FBC_D32 FBC_CMD32 D17 FBC_CMD32 <35> <36> FBD_D32 E1 FBD_D32 FBD_CMD32 U1 FBD_CMD32 <36>
AW50 Y50 FBA_DEBUG0 RG2930 2 @ 1 60.4_0201_1% M51 C35 FBB_DEBUG0 RG2932 2 @ 1 60.4_0201_1% H29 A9 FBC_DEBUG0 RG2934 2 @ 1 60.4_0201_1% F3 AD3 FBD_DEBUG0 RG2936 2 @ 1 60.4_0201_1%
<33> FBA_D34 BA51 FBA_D34 FBA_CMD34 AR50 FBA_DEBUG1 <34> FBB_D34 FBB_D34 FBB_CMD34 FBB_DEBUG1 <35> FBC_D34 FBC_D34 FBC_CMD34 FBC_DEBUG1 <36> FBD_D34 FBD_D34 FBD_CMD34 FBD_DEBUG1
RG2931 2 @ 1 60.4_0201_1% M49 B50 RG2933 2 1 60.4_0201_1% G30 C24 RG2935 2 @ 1 60.4_0201_1% F5 J3 RG2937 2 @ 1 60.4_0201_1%
<33> FBA_D35 FBA_D35 FBA_CMD35 <34> FBB_D35 FBB_D35 FBB_CMD35 <35> FBC_D35 FBC_D35 FBC_CMD35 <36> FBD_D35 FBD_D35 FBD_CMD35
BA50 P47 @ B30 D2
<33> FBA_D36 BB50 FBA_D36 <34> FBB_D36 P52 FBB_D36 <35> FBC_D36 A30 FBC_D36 <36> FBD_D36 D1 FBD_D36
<33> FBA_D37 BA49 FBA_D37 <34> FBB_D37 R46 FBB_D37 <35> FBC_D37 H30 FBC_D37 <36> FBD_D37 C3 FBD_D37
<33> FBA_D38 FBA_D38 <34> FBB_D38 FBB_D38 <35> FBC_D38 FBC_D38 <36> FBD_D38 FBD_D38
AW49 AA44 P46 J35 C30 J14 C2 AC9
<33> FBA_D39 FBA_D39 FBA_DBG_RFU1 <34> FBB_D39 FBB_D39 FBB_DBG_RFU1 <35> FBC_D39 FBC_D39 FBC_DBG_RFU1 <36> FBD_D39 FBD_D39 FBD_DBG_RFU1
AV48 AN44 L50 J41 D27 J23 J5 P9
<33> FBA_D40 FBA_D40 FBA_DBG_RFU2 <34> FBB_D40 FBB_D40 FBB_DBG_RFU2 <35> FBC_D40 FBC_D40 FBC_DBG_RFU2 <36> FBD_D40 FBD_D40 FBD_DBG_RFU2
AT49 L51 J26 J4
<33> FBA_D41 <34> FBB_D41 <35> FBC_D41 <36> FBD_D41
C
<33>
<33>
FBA_D42
FBA_D43
AT47
AT48
AT46
FBA_D41
FBA_D42
FBA_D43 AG45
0803 NV review <34>
<34>
FBB_D42
FBB_D43
L52
L49
M46
FBB_D41
FBB_D42
FBB_D43 H42
0803 NV review <35>
<35>
FBC_D42
FBC_D43
F27
G27
C27
FBC_D41
FBC_D42
FBC_D43 G15 0803 NV review <36>
<36>
FBD_D42
FBD_D43
L8
J2
F1
FBD_D41
FBD_D42
FBD_D43 Y8 0803 NV review
C
<33> FBA_D44 FBA_D44 FBA_CLK0 FBA_CLK0 <33> <34> FBB_D44 FBB_D44 FBB_CLK0 FBB_CLK0 <34> <35> FBC_D44 FBC_D44 FBC_CLK0 FBC_CLK0 <35> <36> FBD_D44 FBD_D44 FBD_CLK0 FBD_CLK0 <36>
AV51 AG46 L47 G42 B27 F15 F2 Y7
<33> FBA_D45 FBA_D45 FBA_CLK0_N FBA_CLK0# <33> <34> FBB_D45 FBB_D45 FBB_CLK0_N FBB_CLK0# <34> <35> FBC_D45 FBC_D45 FBC_CLK0_N FBC_CLK0# <35> <36> FBD_D45 FBD_D45 FBD_CLK0_N FBD_CLK0# <36>
AV52 AK46 M48 F47 A27 H21 H4 R8
<33> FBA_D46 FBA_D46 FBA_CLK1 FBA_CLK1 <33> <34> FBB_D46 FBB_D46 FBB_CLK1 FBB_CLK1 <34> <35> FBC_D46 FBC_D46 FBC_CLK1 FBC_CLK1 <35> <36> FBD_D46 FBD_D46 FBD_CLK1 FBD_CLK1 <36>
AV49 AK45 M47 E47 G29 J21 H5 R7
<33> FBA_D47 AJ48 FBA_D47 FBA_CLK1_N FBA_CLK1# <33> <34> FBB_D47 D48 FBB_D47 FBB_CLK1_N FBB_CLK1# <34> <35> FBC_D47 H20 FBC_D47 FBC_CLK1_N FBC_CLK1# <35> <36> FBD_D47 V7 FBD_D47 FBD_CLK1_N FBD_CLK1# <36>
<33> FBA_D48 AJ46 FBA_D48 <34> FBB_D48 C50 FBB_D48 <35> FBC_D48 D18 FBC_D48 <36> FBD_D48 V8 FBD_D48
AJ47 C48 G20 V6
AK49 C49 E20 V9
AM47 E49 F23 U4
<33> FBA_D52 AM46 FBA_D52 <34> FBB_D52 E50 FBB_D52 <35> FBC_D52 E21 FBC_D52 <36> FBD_D52 R5 FBD_D52
AN48 F49 D21 R6
AN49 F48 E23 U8
<33> FBA_D55 AM44 FBA_D55 U45 <34> FBB_D55 F50 FBB_D55 J33 <35> FBC_D55 G24 FBC_D55 F8 <36> FBD_D55 P6 FBD_D55 AJ8
<33> FBA_D56 FBA_D56 FBA_WCK01 FBA_WCK01 <33> <34> FBB_D56 FBB_D56 FBB_WCK01 FBB_WCK01 <34> <35> FBC_D56 FBC_D56 FBC_WCK01 FBC_WCK01 <35> <36> FBD_D56 FBD_D56 FBD_WCK01 FBD_WCK01 <36>
AM45 U44 D52 H33 H26 G8 R9 AJ7
<33> FBA_D57 AN45 FBA_D57 FBA_WCK01_N V45 FBA_WCK01# <33> <34> FBB_D57 J50 FBB_D57 FBB_WCK01_N G35 FBB_WCK01# <34> <35> FBC_D57 F24 FBC_D57 FBC_WCK01_N G9 FBC_WCK01# <35> <36> FBD_D57 P4 FBD_D57 FBD_WCK01_N AG8 FBD_WCK01# <36>
<33> FBA_D58 FBA_D58 FBA_WCKB01 FBA_WCKB01 <33> <34> FBB_D58 FBB_D58 FBB_WCKB01 FBB_WCKB01 <34> <35> FBC_D58 FBC_D58 FBC_WCKB01 FBC_WCKB01 <35> <36> FBD_D58 FBD_D58 FBD_WCKB01 FBD_WCKB01 <36>
AN46 V44 H48 H35 G26 F9 P5 AG9
<33> FBA_D59 FBA_D59 FBA_WCKB01_N FBA_WCKB01# <33> <34> FBB_D59 FBB_D59 FBB_WCKB01_N FBB_WCKB01# <34> <35> FBC_D59 FBC_D59 FBC_WCKB01_N FBC_WCKB01# <35> <36> FBD_D59 FBD_D59 FBD_WCKB01_N FBD_WCKB01# <36>
AR48 AC45 H51 J39 F26 H12 L7 AD8
<33> FBA_D60 AN47 FBA_D60 FBA_WCK23 AC44 FBA_WCK23 <33> <34> FBB_D60 J51 FBB_D60 FBB_WCK23 H39 FBB_WCK23 <34> <35> FBC_D60 D26 FBC_D60 FBC_WCK23 G12 FBC_WCK23 <35> <36> FBD_D60 L6 FBD_D60 FBD_WCK23 AD9 FBD_WCK23 <36>
<33> FBA_D61 FBA_D61 FBA_WCK23_N FBA_WCK23# <33> <34> FBB_D61 FBB_D61 FBB_WCK23_N FBB_WCK23# <34> <35> FBC_D61 FBC_D61 FBC_WCK23_N FBC_WCK23# <35> <36> FBD_D61 FBD_D61 FBD_WCK23_N FBD_WCK23# <36>
AR47 AD46 H49 F41 B26 G14 L4 AC7
<33> FBA_D62 AR46 FBA_D62 FBA_WCKB23 AD45 FBA_WCKB23 <33> <34> FBB_D62 H52 FBB_D62 FBB_WCKB23 G41 FBB_WCKB23 <34> <35> FBC_D62 C26 FBC_D62 FBC_WCKB23 H14 FBC_WCKB23 <35> <36> FBD_D62 L5 FBD_D62 FBD_WCKB23 AC8 FBD_WCKB23 <36>
<33> FBA_D63 FBA_D63 FBA_WCKB23_N AV47 FBA_WCKB23# <33> <34> FBB_D63 FBB_D63 FBB_WCKB23_N L46 FBB_WCKB23# <34> <35> FBC_D63 FBC_D63 FBC_WCKB23_N J27 FBC_WCKB23# <35> <36> FBD_D63 FBD_D63 FBD_WCKB23_N J6 FBD_WCKB23# <36>
FBA_WCK45 FBA_WCK45 <33> FBB_WCK45 FBB_WCK45 <34> FBC_WCK45 FBC_WCK45 <35> FBD_WCK45 FBD_WCK45 <36>
AV46 L45 H27 J7
FBA_WCK45_N FBA_WCK45# <33> FBB_WCK45_N FBB_WCK45# <34> FBC_WCK45_N FBC_WCK45# <35> FBD_WCK45_N FBD_WCK45# <36>
U47 AW48 C32 M44 A5 E29 AJ1 H7
<33> FBA_DBI0 FBA_DQM0 FBA_WCKB45 FBA_WCKB45 <33> <34> FBB_DBI0 FBB_DQM0 FBB_WCKB45 FBB_WCKB45 <34> <35> FBC_DBI0 FBC_DQM0 FBC_WCKB45 FBC_WCKB45 <35> <36> FBD_DBI0 FBD_DQM0 FBD_WCKB45 FBD_WCKB45 <36>
Y48 AW47 E33 M45 C8 F29 AG1 H6
<33> FBA_DBI1 AG47 FBA_DQM1 FBA_WCKB45_N AR45 FBA_WCKB45# <33> <34> FBB_DBI1 E44 FBB_DQM1 FBB_WCKB45_N H47 FBB_WCKB45# <34> <35> FBC_DBI1 J18 FBC_DQM1 FBC_WCKB45_N G23 FBC_WCKB45# <35> <36> FBD_DBI1 AA7 FBD_DQM1 FBD_WCKB45_N P8 FBD_WCKB45# <36>
<33> FBA_DBI2 FBA_DQM2 FBA_WCK67 FBA_WCK67 <33> <34> FBB_DBI2 FBB_DQM2 FBB_WCK67 FBB_WCK67 <34> <35> FBC_DBI2 FBC_DQM2 FBC_WCK67 FBC_WCK67 <35> <36> FBD_DBI2 FBD_DQM2 FBD_WCK67 FBD_WCK67 <36>
AC48 AR44 G39 H46 F12 H23 AD5 P7
<33> FBA_DBI3 BB51 FBA_DQM3 FBA_WCK67_N AT45 FBA_WCK67# <33> <34> FBB_DBI3 P49 FBB_DQM3 FBB_WCK67_N J47 FBB_WCK67# <34> <35> FBC_DBI3 D29 FBC_DQM3 FBC_WCK67_N H24 FBC_WCK67# <35> <36> FBD_DBI3 D3 FBD_DQM3 FBD_WCK67_N M7 FBD_WCK67# <36>
<33> FBA_DBI4 FBA_DQM4 FBA_WCKB67 FBA_WCKB67 <33> <34> FBB_DBI4 FBB_DQM4 FBB_WCKB67 FBB_WCKB67 <34> <35> FBC_DBI4 FBC_DQM4 FBC_WCKB67 FBC_WCKB67 <35> <36> FBD_DBI4 FBD_DQM4 FBD_WCKB67 FBD_WCKB67 <36>
AV50 AT44 L48 J46 E27 J24 H3 M8
<33> FBA_DBI5 FBA_DQM5 FBA_WCKB67_N FBA_WCKB67# <33> <34> FBB_DBI5 FBB_DQM5 FBB_WCKB67_N FBB_WCKB67# <34> <35> FBC_DBI5 FBC_DQM5 FBC_WCKB67_N FBC_WCKB67# <35> <36> FBD_DBI5 FBD_DQM5 FBD_WCKB67_N FBD_WCKB67# <36>
AM48 D50 F20 U5
<33> FBA_DBI6 AR49 FBA_DQM6 <34> FBB_DBI6 H50 FBB_DQM6 <35> FBC_DBI6 E26 FBC_DQM6 <36> FBD_DBI6 M9 FBD_DQM6
<33> FBA_DBI7 FBA_DQM7 <34> FBB_DBI7 FBB_DQM7 <35> FBC_DBI7 FBC_DQM7 <36> FBD_DBI7 FBD_DQM7
R48 B33 D5 AJ3

<33> FBA_EDC0 V48 FBA_DQS_WP0 <34> FBB_EDC0 E35 FBB_DQS_WP0 <35> FBC_EDC0 D8 FBC_DQS_WP0 <36> FBD_EDC0 AG2 FBD_DQS_WP0
<33> FBA_EDC1 AF44 FBA_DQS_WP1 +FBX_PLLAVDD <34> FBB_EDC1 G44 FBB_DQS_WP1 +FBX_PLLAVDD <35> FBC_EDC1 E17 FBC_DQS_WP1 +FBX_PLLAVDD <36> FBD_EDC1 AA9 FBD_DQS_WP1 +FBX_PLLAVDD
<33> FBA_EDC2 FBA_DQS_WP2 <34> FBB_EDC2 FBB_DQS_WP2 <35> FBC_EDC2 FBC_DQS_WP2 <36> FBD_EDC2 FBD_DQS_WP2
AA48 H38 E12 AF4
<33> FBA_EDC3 BB52 FBA_DQS_WP3 <34> FBB_EDC3 P50 FBB_DQS_WP3 <35> FBC_EDC3 E30 FBC_DQS_WP3 <36> FBD_EDC3 E3 FBD_DQS_WP3
AT50 J48 B29 H2
AK48 D51 G21 U6
<33> FBA_EDC6 AR51 FBA_DQS_WP6 AN42 <34> FBB_EDC6 F51 FBB_DQS_WP6 L38 <35> FBC_EDC6 E24 FBC_DQS_WP6 L17 <36> FBD_EDC6 M5 FBD_DQS_WP6 V11
<33> FBA_EDC7 FBA_DQS_WP7 FBA_PLL_AVDD <34> FBB_EDC7 FBB_DQS_WP7 FBB_PLL_AVDD <35> FBC_EDC7 FBC_DQS_WP7 FBC_PLL_AVDD <36> FBD_EDC7 FBD_DQS_WP7 FBD_PLL_AVDD
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
W45 Y16 Y24 Y32
CG54
CG1102
CG1103
CG1104
GND_694 1 GND_702 1 GND_710 1 GND_0718 1
W47 Y17 Y25 Y33
W49 GND_695 Y18 GND_703 Y26 GND_711 Y34 GND_0719
W51 GND_696 VGA@ Y19 GND_704 VGA@ Y27 GND_712 VGA@ Y35 GND_0720 VGA@
W6 GND_697 2 Y20 GND_705 2 Y28 GND_713 2 Y36 GND_0721 2
W8 GND_698 Y21 GND_706 Y29 GND_714 Y37 GND_0722
Y14 GND_699 Y22 GND_707 Y30 GND_715 Y38 GND_0723
+FBX_PLLAVDD Y15 GND_700 Y23 GND_708 Y31 GND_716 Y39 GND_0724
GND_701 GND_709 GND_717 GND_0725
AF42
L29 FB_REFPLL_AVDD0 Under GPU N18E-G3
0.47U_0201_4VAN
0.47U_0201_4VAN
FB_REFPLL_AVDD1
CG1100
CG1101
1 1
VGA@ VGA@ N18E-G3-ES-A1_FCBGA2228 N18E-G3-ES-A1_FCBGA2228

Under GPU N18E-G3-ES-A1_FCBGA2228
Under GPU FBD N/A
Under GPU
2 2 +1.8VSDGPU_MAIN
@ @ @ @
B VGA@ B
1 2
LG6
PBY160808T-300Y-N_2P
22U_0603_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
1 1
1
CG1099
CG1098
CG55
+1.35VSDGPU VGA@ VGA@ VGA@

2
2 2 +1.35VSDGPU
+1.35VSDGPU +1.35VSDGPU
CKE CKE CKE

2
VGA@ 10K_0402_5% 10K_0402_5% VGA@ 10K_0402_5% 10K_0402_5% CKE
2
RG53 RG54 RG55 RG56
VGA@ VGA@
1
FBA_CMD10 FBB_CMD10 VGA@ 10K_0402_5% 10K_0402_5% VGA@ 10K_0402_5% 10K_0402_5%

RG57 RG58 RG450 RG453
FBA_CMD26 FBB_CMD26 VGA@ VGA@
1
FBC_CMD10 FBD_CMD10
FBA_CMD2 FBB_CMD2
FBC_CMD26 FBD_CMD26
FBA_CMD18 FBB_CMD18
FBC_CMD2 FBD_CMD2
2
FBC_CMD18 FBD_CMD18
VGA@ 10K_0402_5% 10K_0402_5% VGA@ 10K_0402_5% 10K_0402_5%
2
RG47 RG48 RG49 RG50
VGA@ VGA@
1
VGA@ 10K_0402_5% 10K_0402_5% VGA@ 10K_0402_5% 10K_0402_5%

RG51 RG52 RG451 RG452
VGA@ VGA@
1
Reset Reset Reset
Reset
at the end of this trace. (VRAM) at the end of this trace. (VRAM) at the end of this trace. (VRAM)
at the end of this trace. (VRAM)
A A

Issued Date 2017/11/23 2017/12/31 Title
Deciphered Date
N18E-G3(4/8) MEM
5 4 3 2 1
5 4 3 2 1
+NVVDD1 +NVVDD1
UG9J +NVVDD1 +NVVDD1 +1.35VSDGPU +1.35VSDGPU

18/22 VDD_2/3 UG9M UG9L
22/22 VDD_3/3 19/22 FBVDDQ
AH39 AP23
AH40 VDD_145 VDD_219 AP24 AA10 AT43
AJ13 VDD_146 VDD_220 AP25 BG45 R23 AA11 FBVDDQ_01 FBVDDQ_32 K12
AJ40 VDD_147 VDD_221 AP26 BG46 VDD_382 VDD_465 R24 AA42 FBVDDQ_02 FBVDDQ_33 K14
AK13 VDD_148 VDD_222 AP27 BG47 VDD_383 VDD_466 R25 AA43 FBVDDQ_03 FBVDDQ_34 K15
D
AK14 VDD_149 VDD_223 AP28 BG48 VDD_384 VDD_467 R26 AC10 FBVDDQ_04 FBVDDQ_35 K17 D
AK15 VDD_150 VDD_224 AP29 BG49 VDD_385 VDD_468 R27 AC11 FBVDDQ_05 FBVDDQ_36 K18
AK18 VDD_153 VDD_227 AP32 BG52 VDD_388 VDD_471 R30 AD10 FBVDDQ_08 FBVDDQ_39 K23
AK19 VDD_154 VDD_228 AP33 BH44 VDD_389 VDD_472 R31 AD11 FBVDDQ_09 FBVDDQ_40 K24
AK22 VDD_157 VDD_231 AP36 BH48 VDD_392 VDD_475 R34 AF10 FBVDDQ_12 FBVDDQ_43 K29
AK23 VDD_158 VDD_232 AP37 BH49 VDD_393 VDD_476 R35 AF43 FBVDDQ_13 FBVDDQ_44 K30
AK24 VDD_159 VDD_233 AP38 BH50 VDD_394 VDD_477 R36 AG10 FBVDDQ_14 FBVDDQ_45 K32
AK27 VDD_162 VDD_236 AR13 BJ44 VDD_397 VDD_480 R39 AG43 FBVDDQ_17 FBVDDQ_48 K36
AK28 VDD_163 VDD_237 AR40 BJ45 VDD_398 VDD_481 R40 AJ10 FBVDDQ_18 FBVDDQ_49 K38
AK29 VDD_164 VDD_238 AT13 BJ46 VDD_399 VDD_482 T13 AJ11 FBVDDQ_19 FBVDDQ_50 K39
AK30 VDD_165 VDD_239 AT14 BJ47 VDD_400 VDD_483 T40 AJ42 FBVDDQ_20 FBVDDQ_51 K41
AK31 VDD_166 VDD_240 AT15 BJ48 VDD_401 VDD_484 U13 AJ43 FBVDDQ_21 FBVDDQ_52 L14
AK32 VDD_167 VDD_241 AT16 BJ49 VDD_402 VDD_485 U14 AK10 FBVDDQ_22 FBVDDQ_53 L15
AK36 VDD_171 VDD_245 AT20 BK47 VDD_406 VDD_489 U18 AM42 FBVDDQ_26 FBVDDQ_57 L23
AK37 VDD_172 VDD_246 AT21 BK48 VDD_407 VDD_490 U19 AM43 FBVDDQ_27 FBVDDQ_58 L24
AK38 VDD_173 VDD_247 AT22 BK49 VDD_408 VDD_491 U20 AN43 FBVDDQ_28 FBVDDQ_59 L26
AK39 VDD_174 VDD_248 AT23 BK50 VDD_409 VDD_492 U21 AR42 FBVDDQ_29 FBVDDQ_60 L27
AK40 VDD_175 VDD_249 AT24 BK51 VDD_410 VDD_493 U22 AR43 FBVDDQ_30 FBVDDQ_61 L30
AL13 VDD_176 VDD_250 AT25 BK52 VDD_411 VDD_494 U23 R42 FBVDDQ_31 FBVDDQ_62 L32
AL40 VDD_177 VDD_251 AT26 BL46 VDD_412 VDD_495 U24 R43 FBVDDQ_76 FBVDDQ_63 L33
AM13 VDD_178 VDD_252 AT27 BL47 VDD_413 VDD_496 U25 U10 FBVDDQ_77 FBVDDQ_64 L35
AM16 VDD_181 VDD_255 AY26 BL50 VDD_416 VDD_499 U28 V10 FBVDDQ_80 FBVDDQ_67 M10
AM17 VDD_182 VDD_321 AY27 BL51 VDD_417 VDD_500 U29 V42 FBVDDQ_81 FBVDDQ_68 M43
AM18 VDD_183 VDD_322 AY28 BL52 VDD_418 VDD_501 U30 V43 FBVDDQ_82 FBVDDQ_69 P10
AM19 VDD_184 VDD_323 AY29 BM47 VDD_419 VDD_502 U31 Y10 FBVDDQ_83 FBVDDQ_70 P11
AM20 VDD_185 VDD_324 AY30 BM48 VDD_420 VDD_503 U32 Y11 FBVDDQ_84 FBVDDQ_71 P42
C AM21 VDD_186 VDD_325 AY31 BM49 VDD_421 VDD_504 U33 Y42 FBVDDQ_85 FBVDDQ_72 P43 C
AM22 VDD_187 VDD_326 AY32 BM50 VDD_422 VDD_505 U34 Y43 FBVDDQ_86 FBVDDQ_73 R10
AM23 VDD_188 VDD_327 AY33 BM51 VDD_423 VDD_506 U35 FBVDDQ_87 FBVDDQ_74 R11
VDD_189 VDD_328 VDD_424 VDD_507 FBVDDQ_75
470U_X_2VY_R9M
10U_0402_6.3V6M
AM24 AY34 N13 U36 1
VDD_190 VDD_329 VDD_425 VDD_508
CG242
AM25 AY35 N14 U37 1
VDD_191 VDD_330 VDD_426 VDD_509
CG243
AM26 AY36 N15 U38 +
AM27 VDD_192 VDD_331 AY37 N16 VDD_427 VDD_510 U39 TC23
AM28 VDD_193 VDD_332 AY38 N17 VDD_428 VDD_511 U40 E52
VDD_194 VDD_333 VDD_429 VDD_512 2 2 FBVDDQ_SENSE FB_VDDQ_SENSE <98>
AM29 AY39 N18 V13
AM30 VDD_195 VDD_334 AY40 N19 VDD_430 VDD_513 V40
AM31 VDD_196 VDD_335 AY43 N20 VDD_431 VDD_514 W13
VDD_197 VDD_336 VDD_432 VDD_515 FB_VREF TP@ 1019 NV update change to 49.9
AM32 AY45 N21 W14 VGA@ VGA@ P45
AM33 VDD_198 VDD_337 BA43 N22 VDD_433 VDD_516 W15 FB_VREF FB_VREF
AM34 VDD_199 VDD_338 BA44 N23 VDD_434 VDD_517 W16 +1.35VSDGPU
VDD_200 VDD_339 VDD_435 VDD_518
2
AM35 BA45 N24 W17 1
VDD_201 VDD_340 VDD_436 VDD_519
49.9_0402_1%
RG2881
AM36 BA46 N25 W18
VDD_202 VDD_341 VDD_437 VDD_520
3.9P_0402_50V8C
AM37 BA47 N26 W19 VGA@
VDD_203 VDD_342 VDD_438 VDD_521 R44 FBCAL_VDDQ RG67 1 VGA@
CG2778
AM38 BB38 N27 W20 2 40.2_0402_1% VGA@
AM39 VDD_204 VDD_343 BB39 N28 VDD_439 VDD_522 W21 FB_CAL_PD_VDDQ 2
1
AM40 VDD_205 VDD_344 BB45 N29 VDD_440 VDD_523 W22 P44 FBCAL_GND RG68 1 VGA@ 2 40.2_0402_1%
AN13
AN40
AP13
VDD_206
VDD_207
VDD_208
VDD_345
VDD_346
VDD_347
BB46
BB47
BB48
N30
N31
N32
VDD_441
VDD_442
VDD_443
VDD_524
VDD_525
VDD_526
W23
W24
W25
eagle HW reserved FB_CAL_PU_GND
FB_CAL_TERM_GND
R45 FBCAL_TERM RG69 1 VGA@ 2 40.2_0402_1%
AP14
AP15
AP16
VDD_209
VDD_210
VDD_211
VDD_348
VDD_349
VDD_350
BC38
BC39
BC40
N33
N34
N35
VDD_444
VDD_445
VDD_446
VDD_527
VDD_528
VDD_529
W26
W27
W28 N18E-G3-ES-A1_FCBGA2228
N18E CRB probe circuit
AP17 VDD_212 VDD_351 BC41 N36 VDD_447 VDD_530 W29 @
AP18
AP19
AP20
VDD_213
VDD_214
VDD_215
VDD_352
VDD_353
VDD_354
BC45
BC47
BC49
N37
N38
N39
VDD_448
VDD_449
VDD_450
VDD_531
VDD_532
VDD_533
W30
W31
W32
N18E CRB change to 40.2
AP21 VDD_216 VDD_355 BD39 N40 VDD_451 VDD_534 W33
AP22 VDD_217 VDD_356 BE48 P13 VDD_452 VDD_535 W34
BD41 VDD_218 VDD_369 BE49 P40 VDD_453 VDD_536 W35
BD46 VDD_357 VDD_370 BE50 R13 VDD_454 VDD_537 W36
BD49 VDD_360 VDD_373 BF42 R16 VDD_457 VDD_540 W39
BD50 VDD_361 VDD_374 BF44 R17 VDD_458 VDD_541 W40
B
BD51 VDD_362 VDD_375 BF45 R18 VDD_459 VDD_542 Y13 B
BE41 VDD_363 VDD_376 BF47 R19 VDD_460 VDD_543 Y40
BE42
BE43
BE46
VDD_364
VDD_365
VDD_366
VDD_377
VDD_378
VDD_379
BF49
BF51
BG43
R20
R21
R22
VDD_461
VDD_462
VDD_463
VDD_544
near GPU
BE47 VDD_367 VDD_380 BG44 VDD_464
VDD_368 VDD_381
+1.35VSDGPU
BK45
VDD_SENSE NVVDD1_VCC_SENSE <93>
470U_X_2VY_R9M
10U_0402_6.3V6M
1 BL45
GND_SENSE NVVDD1_VSS_SENSE <93>
CG244
1
CG245
CG216
CG217
CG218
CG219
CG220
CG221
CG222
CG223
CG224
CG225
CG226
CG227
CG228
VGA@ VGA@ N18E-G3-ES-A1_FCBGA2228 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2
@
@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
eagle HW reserved
FBA FBC
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
CG1105
CG1106
CG1107
CG1108
CG1110
CG1109
CG1111
CG1112
CG1114
CG1113
CG1116
CG1115
CG1117
CG1118
CG1147
CG1148
CG1150
CG1149
CG1152
CG1151
CG1153
CG1154
CG1156
CG1155
CG1158
CG1157
CG1159
CG1160
1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 2 2
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2 2 2 2 2 2 2 2 2 2 2 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 1 1
A A
FBB FBD
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
CG1119
CG1120
CG1122
CG1121
CG1124
CG1123
CG1125
CG1126
CG1128
CG1127
CG1130
CG1129
CG1131
CG1132
CG1133
CG1134
CG1136
CG1135
CG1138
CG1137
CG1139
CG1140
CG1142
CG1141
CG1144
CG1143
CG1145
CG1146
1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2 2 2 2 2 2 2 2 2 2 2 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 1 1
N18E-G3(5/8) Power
0.1
5 4 3 2 1
5 4 3 2 1
+NVVDD1 +NVVDD1
UG9K +1.8VSDGPU_AON UG9I UG9F UG9G UG9H

20/22 NC/1V8 17/22 VDD_1/3 15/22 GND_1/3 16/22 GND_2/3 21/22 GND_3/3
BA10 AA13 AE28 A2 AH6 AR20 B52 BL40 N51

1V8_AON_1 BB14 AA14 VDD_001 VDD_076 AE29 A26 GND_001 GND_122 AH8 AR21 GND_238 GND_361 B7 BL43 GND_482 GND_592 N6
1V8_AON_2 BC14 AA15 VDD_002 VDD_077 AE30 A29 GND_002 GND_123 AJ14 AR22 GND_239 GND_362 BA48 BL5 GND_483 GND_593 N8
1V8_AON_3 AA16 VDD_003 VDD_078 AE31 A3 GND_003 GND_124 AJ15 AR23 GND_240 GND_363 BA9 BL7 GND_484 GND_594 P14
D
FP_FUSE_GPU AA17
AA18
AA19
VDD_004
VDD_005
VDD_006
VDD_079
VDD_080
VDD_081
AE32
AE33
AE34
A32
A50
A51
GND_004
GND_005
GND_006
GND_125
GND_126
GND_127
AJ16
AJ17
AJ18
AR24
AR25
AR26
GND_241
GND_242
GND_243
GND_364
GND_365
GND_366
BB49
BC13
BC16
BM2
BM3
C1
GND_485
GND_486
GND_487
GND_595
GND_596
GND_597
P15
P16
P17
D
BD14 BD24 SNN_SYM21_NC1 AA20 VDD_007 VDD_082 AE35 AA49 GND_007 GND_128 AJ19 AR27 GND_244 GND_367 BC19 C29 GND_488 GND_598 P18
<25> FP_FUSE_GPU FP_FUSE_SRC NC_1 SNN_SYM21_NC2 VDD_008 VDD_083 GND_008 GND_129 GND_245 GND_368 GND_489 GND_599
BM44 AA21 AE36 AA8 AJ2 AR28 BC2 C33 P19
NC_2 BM45 SNN_SYM21_NC3 AA22 VDD_009 VDD_084 AE37 AB10 GND_009 GND_130 AJ20 AR29 GND_246 GND_369 BC22 C5 GND_490 GND_600 P20
NC_3 AA23 VDD_010 VDD_085 AE38 AB14 GND_010 GND_131 AJ21 AR30 GND_247 GND_370 BC25 C51 GND_491 GND_601 P21
AA24 VDD_011 VDD_086 AE39 AB15 GND_011 GND_132 AJ22 AR31 GND_248 GND_371 BC28 C52 GND_492 GND_602 P22
AA25 VDD_012 VDD_087 AE40 AB16 GND_012 GND_133 AJ23 AR32 GND_249 GND_372 BC31 D10 GND_493 GND_603 P23
AA26 VDD_013 VDD_088 AF13 AB17 GND_013 GND_134 AJ24 AR33 GND_250 GND_373 BC34 D12 GND_494 GND_604 P24
N18E-G3-ES-A1_FCBGA2228 AA29 VDD_016 VDD_091 AF16 AB2 GND_016 GND_137 AJ27 AR36 GND_253 GND_376 BC51 D19 GND_497 GND_607 P27
@ VDD_018 VDD_093 GND_018 GND_139 GND_255 GND_378 GND_499 GND_609
AA31 AF18 AB21 AJ29 AR38 BC8 D24 P29
AA32 VDD_019 VDD_094 AF24 AB22 GND_019 GND_140 AJ30 AR39 GND_256 GND_379 BD26 D25 GND_500 GND_610 P30
AA36 VDD_023 VDD_098 AF31 AB26 GND_023 GND_144 AJ34 AT4 GND_260 GND_383 BD38 D34 GND_504 GND_614 P34
AA37 VDD_024 VDD_099 AF32 AB27 GND_024 GND_145 AJ35 AT5 GND_261 GND_384 BD52 D37 GND_505 GND_615 P35
AA38 VDD_025 VDD_100 AF33 AB28 GND_025 GND_146 AJ36 AT51 GND_262 GND_385 BE10 D4 GND_506 GND_616 P36
AB13 VDD_028 VDD_103 AG13 AB31 GND_028 GND_149 AJ39 AU10 GND_265 GND_388 BE16 D46 GND_509 GND_619 P39
AB40 VDD_029 VDD_104 AG19 AB32 GND_029 GND_150 AJ9 AU14 GND_266 GND_389 BE18 D49 GND_510 GND_620 P51
+1.8VSDGPU_AON AC13 VDD_030 VDD_105 AG20 AB33 GND_030 GND_151 AK1 AU15 GND_267 GND_390 BE19 D7 GND_511 GND_621 R49
AC14 VDD_031 VDD_106 AG21 AB34 GND_031 GND_152 AK44 AU16 GND_268 GND_391 BE21 E2 GND_512 GND_622 R52
AC15 VDD_032 VDD_107 AG22 AB35 GND_032 GND_153 AK47 AU17 GND_269 GND_392 BE22 E4 GND_513 GND_623 T10
AC16 VDD_033 VDD_108 AG23 AB36 GND_033 GND_154 AL10 AU18 GND_270 GND_393 BE24 E48 GND_514 GND_624 T14
VDD_034 VDD_109 GND_034 GND_155 GND_271 GND_394 GND_515 GND_625
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
AC17 AG27 AB37 AL14 AU19 BE25 E5 T15
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
AC18 VDD_035 VDD_110 AG28 AB38 GND_035 GND_156 AL15 AU2 GND_272 GND_395 BE27 E51 GND_516 GND_626 T16
CG1161
CG1163
CG1162
CG1181
CG1182
CG1183
1 1 1 1 1 1 1 1 1 VDD_036 VDD_111 GND_036 GND_157 GND_273 GND_396 GND_517 GND_627

CG291
CG1173
CG1174
AC19 AG29 AB39 AL16 AU20 BE28 E8 T17
AC20 VDD_037 VDD_112 AG35 AB4 GND_037 GND_158 AL17 AU21 GND_274 GND_397 BE30 F10 GND_518 GND_628 T18
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ AC21 VDD_038 VDD_113 AG36 AB43 GND_038 GND_159 AL18 AU22 GND_275 GND_398 BE31 F13 GND_519 GND_629 T19
2 2 2 2 2 2 2 2 2 AC22 VDD_039 VDD_114 AG37 AB45 GND_039 GND_160 AL19 AU23 GND_276 GND_399 BE33 F16 GND_520 GND_630 T2
C
AC26 VDD_043 VDD_118 AH13 AB6 GND_043 GND_164 AL22 AU27 GND_280 GND_403 BE39 F22 GND_524 GND_634 T23 C
AC27 VDD_044 VDD_119 AH14 AB8 GND_044 GND_165 AL23 AU28 GND_281 GND_404 BE40 F25 GND_525 GND_635 T24
AC28 VDD_045 VDD_120 AH15 AD14 GND_045 GND_166 AL24 AU29 GND_282 GND_405 BF2 F28 GND_526 GND_636 T25
AC32 VDD_049 VDD_124 AH19 AD18 GND_049 GND_170 AL28 AU33 GND_286 GND_409 BG10 F37 GND_530 GND_640 T29
AC39 VDD_056 VDD_131 AH26 AD25 GND_056 GND_177 AL35 AU4 GND_293 GND_416 BG31 G2 GND_537 GND_647 T36
AC40 VDD_057 VDD_132 AH27 AD26 GND_057 GND_178 AL36 AU45 GND_294 GND_417 BG34 G38 GND_538 GND_648 T37
AD13 VDD_058 VDD_133 AH28 AD27 GND_058 GND_179 AL37 AU47 GND_295 GND_418 BG37 G4 GND_539 GND_649 T38
AD40 VDD_059 VDD_134 AH29 AD28 GND_059 GND_180 AL38 AU49 GND_296 GND_419 BG40 G47 GND_540 GND_650 T39
AE13 VDD_060 VDD_135 AH30 AD29 GND_060 GND_181 AL39 AU51 GND_297 GND_420 BG42 G49 GND_541 GND_651 T4
AE14 VDD_061 VDD_136 AH31 AD30 GND_061 GND_182 AL4 AU6 GND_298 GND_421 BG7 G51 GND_542 GND_652 T43
AE15 VDD_062 VDD_137 AH32 AD31 GND_062 GND_183 AL43 AU8 GND_299 GND_422 BH15 G6 GND_543 GND_653 T45
AE16 VDD_063 VDD_138 AH33 AD32 GND_063 GND_184 AL45 AV4 GND_300 GND_423 BH18 H1 GND_544 GND_654 T47
AE19 VDD_066 VDD_141 AH36 AD35 GND_066 GND_187 AL51 AW14 GND_303 GND_426 BH24 H16 GND_547 GND_657 T6
AE20 VDD_067 VDD_142 AH37 AD36 GND_067 GND_188 AL6 AW15 GND_304 GND_427 BH27 H19 GND_548 GND_658 T8
AE21 VDD_068 VDD_143 AH38 AD37 GND_068 GND_189 AL8 AW16 GND_305 GND_428 BH30 H22 GND_549 GND_659 U7
AE22 VDD_069 VDD_144 AV28 AD38 GND_069 GND_190 AM4 AW17 GND_306 GND_429 BH33 H25 GND_550 GND_660 U9
AE23 VDD_070 VDD_286 AV29 AD39 GND_070 GND_191 AM9 AW18 GND_307 GND_430 BH36 H28 GND_551 GND_661 V14
AE24 VDD_071 VDD_287 AV30 AD44 GND_071 GND_192 AN14 AW19 GND_308 GND_431 BH39 H31 GND_552 GND_662 V15
AE25 VDD_072 VDD_288 AV31 AE10 GND_072 GND_193 AN15 AW20 GND_309 GND_432 BH42 H34 GND_553 GND_663 V16
AE26 VDD_073 VDD_289 AV32 AE2 GND_073 GND_194 AN16 AW21 GND_310 GND_433 BH5 H37 GND_554 GND_664 V17
AE27 VDD_074 VDD_290 AV33 AE4 GND_074 GND_195 AN17 AW22 GND_311 GND_434 BJ10 H40 GND_555 GND_665 V18
AT30 VDD_075 VDD_291 AV34 AE43 GND_075 GND_196 AN18 AW23 GND_312 GND_435 BJ12 H43 GND_556 GND_666 V19
AT31 VDD_256 VDD_292 AV35 AE45 GND_076 GND_197 AN19 AW24 GND_313 GND_436 BJ13 J1 GND_557 GND_667 V20
B B
AT37 VDD_262 VDD_298 AV42 AF1 GND_082 GND_203 AN25 AW30 GND_319 GND_442 BJ19 J52 GND_563 GND_673 V26
AT38 VDD_263 VDD_299 AV43 AF19 GND_083 GND_204 AN26 AW31 GND_320 GND_443 BJ20 K13 GND_564 GND_674 V27
AT39 VDD_264 VDD_300 AV44 AF20 GND_084 GND_205 AN27 AW32 GND_321 GND_444 BJ21 K16 GND_565 GND_675 V28
AT40 VDD_265 VDD_301 AW13 AF21 GND_085 GND_206 AN28 AW33 GND_322 GND_445 BJ22 K19 GND_566 GND_676 V29
AT42 VDD_266 VDD_302 AW40 AF22 GND_086 GND_207 AN29 AW34 GND_323 GND_446 BJ23 K2 GND_567 GND_677 V30
AU13 VDD_267 VDD_303 AW42 AF23 GND_087 GND_208 AN30 AW35 GND_324 GND_447 BJ24 K22 GND_568 GND_678 V31
AV13 VDD_270 VDD_306 AW45 AF29 GND_090 GND_211 AN33 AW38 GND_327 GND_450 BJ27 K31 GND_571 GND_681 V34
AV14 VDD_271 VDD_307 AY13 AF35 GND_091 GND_212 AN34 AW39 GND_328 GND_451 BJ28 K34 GND_572 GND_682 V35
AV20 VDD_277 VDD_313 AY19 AF5 GND_097 GND_218 AN4 AY10 GND_334 GND_457 BJ34 K49 GND_578 GND_688 V52
AV21 VDD_278 VDD_314 AY20 AG14 GND_098 GND_219 AN5 AY2 GND_335 GND_458 BJ35 K51 GND_579 GND_689 W10
AV22 VDD_279 VDD_315 AY21 AG15 GND_099 GND_220 AN8 AY4 GND_336 GND_459 BJ36 K6 GND_580 GND_690 W2
AV23 VDD_280 VDD_316 AY22 AG16 GND_100 GND_221 AP10 AY47 GND_337 GND_460 BJ37 K8 GND_581 GND_691 W4
AV24 VDD_281 VDD_317 AY23 AG17 GND_101 GND_222 AP2 AY49 GND_338 GND_461 BJ38 M52 GND_582 GND_692 W43
AV25 VDD_282 VDD_318 AY24 AG18 GND_102 GND_223 AP4 AY51 GND_339 GND_462 BJ39 M6 GND_583 GND_693 Y9
AV26 VDD_283 VDD_319 AY25 AG24 GND_103 GND_224 AP43 AY6 GND_340 GND_463 BJ40 N10 GND_584 GND_726
AV27 VDD_284 VDD_320 AG25 GND_104 GND_225 AP45 AY8 GND_341 GND_464 BJ41 N2 GND_585
VDD_285 AG26 GND_105 GND_226 AP47 B1 GND_342 GND_465 BJ42 N4 GND_586
AG3 GND_106 GND_227 AP49 B10 GND_343 GND_466 BJ43 N43 GND_587
AG30 GND_107 GND_228 AP51 B13 GND_344 GND_467 BJ7 N45 GND_588
N18E-G3-ES-A1_FCBGA2228 AG31 GND_108 GND_229 AP6 B16 GND_345 GND_468 BK1 N47 GND_589
AG32 GND_109 GND_230 AP8 B19 GND_346 GND_469 BL1 N49 GND_590
@ GND_110 GND_231 GND_347 GND_470 GND_591
AG33 AR14 B2 BL10 BL37
AG34 GND_111 GND_232 AR15 B22 GND_348 GND_471 BL13 GND_481
AG44 GND_112 GND_233 AR16 B25 GND_349 GND_472 BL16
AH10 GND_113 GND_234 AR17 B28 GND_350 GND_473 BL19 N18E-G3-ES-A1_FCBGA2228
AH2 GND_114 GND_235 AR18 B31 GND_351 GND_474 BL2
GND_115 GND_236 GND_352 GND_475 @
AH4 AR19 B34 BL22
AH43 GND_116 GND_237 BL34 B37 GND_353 GND_476 BL25
AH45 GND_117 GND_480 BC24 B40 GND_354 GND_477 BL28
AH47 GND_118 GND_F B43 GND_355 GND_478 BL31
AH49 GND_119 B46 GND_356 GND_479 B5
A
AH51 GND_120 B48 GND_357 GND_359 B51 A
GND_121 GND_358 GND_360
N18E-G3-ES-A1_FCBGA2228 N18E-G3-ES-A1_FCBGA2228
@ @

N18E-G3(6/8) Power,GND
5 4 3 2 1
5 4 3 2 1
+1.8VSDGPU_AON
+1.8VSDGPU_AON
2
UG9U
14/22 MISC 2 @ @ @
RG78 RG79 RG80 RG81 RG82 RG83 RG84 RG85 RG86
100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% BJ4 ROM_CS# 100K_0402_1% 10K_0402_5% 100K_0402_1%
ROM_CS_N
1
BK2 ROM_SI
D X76@ @ @ VGA@ @ VGA@ ROM_SI BK4 ROM_SO D
STRAP0 BL3 ROM_SO BK3 ROM_SCLK

STRAP1 BL4 STRAP0 ROM_SCLK
STRAP2 BM4 STRAP1
STRAP3 BM5 STRAP2
STRAP3
2
STRAP4 BK5
STRAP5 BJ5 STRAP4
STRAP5 RG87 RG88 RG89
100K_0402_1% 10K_0402_5% 100K_0402_1%
2
@
1
BF9 GPU_BUFRST# T63
BUFRST_N VGA@ VGA@
RG90 RG91 RG92 @ RG93 RG94 RG95 PAD~D VGA@
100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1%
1
X76@ VGA@ VGA@ VGA@ @
@
The Strap for ROM_SO should be 10K while all others are 100K.
(LSB) (MSB) (LSB) (MSB)
G-sync with VGA device Strap0 Strap1 Strap2 Strap3 Strap4 Strap5 ROM_SO ROM_SI ROM_SCLK
PU PD PD PU PD PU PD PD PD
MICRON 100kOhm 100kOhm 100kOhm 100kOhm 100kOhm 100kOhm 10kOhm 100kOhm 100kOhm +1.8VSDGPU_AON
MT61K256M32JE-14:A N18E CS# add 33ohm +1.8VSDGPU_AON
PD PD PD PU PD PU PD PD PD
Samsung 100kOhm 100kOhm 100kOhm 100kOhm 100kOhm 100kOhm 10kOhm 100kOhm 100kOhm
1
C C
K4Z80325BC-HC14 VGA@ 1 VGA@
RG74 CG66
VGA@ 10K_0402_5% .1U_0402_16V7K
RG2964
2
33_0402_5% UG13 2 VGA@
ROM_CS# 1 2 ROM_CS_R# 1 8 RG75
ROM_SO 1 2 ROM_SO_R 2 CS# VCC 7 33_0402_5%
RG76 3 DO(IO1) HOLD#(IO3) 6 ROM_SCLK_R 1 2 ROM_SCLK
0_0402_5% 4 WP#(IO2) CLK 5 ROM_SI_R 1 2 ROM_SI
VGA@ GND DI(IO0)
W25Q80EWSSIG_SO8 RG77
VGA@ 33_0402_5%
VGA@
DGPU VBIOS ROM 8Mb
+1.8VSDGPU_MAIN +GPU_PLLVDD_XS_SP UG9V

13/22 XTAL/PLL
1 2 BD12
SP_PLLVDD
22U_0603_6.3V6M
4.7U_0402_6.3V6M
0.47U_0201_4VAN
0.47U_0201_4VAN
LG4 BC12
CG1220
CG1222
1 1 1 VID_PLLVDD
1
PBY160808T-300Y-N_2P
CG1223
CG1221
VGA@
VGA@ VGA@ VGA@ VGA@
2
2 2 2
B B
0803 NV review
U42
GPCPLL_AVDD0
AF11
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
GPCPLL_AVDD1 +1.8VSDGPU_AON
CG1226
CG1224
CG1225
1 1 1
BB24
XSN_PLLVDD
2
VGA@ VGA@ VGA@ @
2 2 2 RG2882
100K_0402_1%
1
BJ6 BK6 XTALOUTBUFF_R

EXT_REFCLK_FL XTAL_OUTBUFF
BL6 BM6
XTAL_IN XTAL_OUT
1
RG101 RG98
10K_0402_5% @ N18E-G3-ES-A1_FCBGA2228 100K_0201_5%
VGA@
2
VGA@
RG99 1 @ 2 10M_0402_5%
1
RG199 VGA@
VGA@ 330_0402_1%
YG1
27MHZ_10PF_XRCGB27M000F2P18R0
A
Raptor: change to follow 2018 VX SJ10000UI00 A
2
XTALIN 1 3 XTALOUT
1
NC NC
3 P/N: SJ10000UI00 (S CRYSTAL 27MHZ 10PF XRCGB27M000F2P18R0)
2 2
CG76 VGA@
CG75 VGA@ 2 4 15P_0402_50V8J
15P_0402_50V8J
1 1

N18E-G3(7/8) Strap,ROM
0.1
5 4 3 2 1
5 4 3 2 1
Pull down NVHS_DVDD, NVHS_CVDD, NVHS_HVDD,

NVHS_PLL_HVDD rails to GND with 10K Resistor
D D
UG9S
11/22 NVHS
AM1
NVHS0_RX0 AN1
NVHS0_RX0_N
AN2
+1.0VSDGPU +NVHS_DVDD NVHS0_RX1 AN3
RG2996 1 @ 2 0_0603_5% NVHS0_RX1_N
AR3
NVHS0_RX2
1
AR2
RG2890 NVHS0_RX2_N
10K_0402_5% AR1
VGA@ NVHS0_RX3 AT1
NVHS0_RX3_N
2
AT10 AT2
AT9 NVHS_DVDD_1 NVHS0_RX4 AT3
AV10 NVHS_DVDD_2 NVHS0_RX4_N
AV11 NVHS_DVDD_3 AV3
+1.0VSDGPU NVHS_DVDD_4 NVHS0_RX5 AV2
AR10 NVHS0_RX5_N
AT11 NVHS_CVDD_1 AV1
0.47U_0201_4VAN
0.47U_0201_4VAN
NVHS_CVDD_2 NVHS0_RX6 AW1
CG2837
CG2838
1 1 NVHS0_RX6_N
AW2
VGA@ VGA@ NVHS0_RX7 AW3
2 2 NVHS0_RX7_N
C AM7 C
NVHS0_TX0 AM8
NVHS0_TX0_N
AN7
NVHS0_TX1 AN6
+1.8VSDGPU_MAIN +NVHS_HVDD NVHS0_TX1_N
RG2997 1 @ 2 0_0603_5% AM10 AR6
AM11 NVHS_HVDD_1 NVHS0_TX2 AR5
NVHS_HVDD_2 NVHS0_TX2_N
1
RG2892 AN10
10K_0402_5% AN11 NVHS_HVDD_3 AR7
VGA@ AR11 NVHS_HVDD_4 NVHS0_TX3 AR8
NVHS_HVDD_5 NVHS0_TX3_N
AN9 AT7
2
NVHS_PLL_HVDD NVHS0_TX4 AT6

NVHS0_TX4_N
AV6
NVHS0_TX5 AV5
NVHS0_TX5_N
+NVHS_PLL_HVDD AV7
RG2998 1 @ 2 0_0603_5% NVHS0_TX6 AV8
NVHS0_TX6_N
1
AW7
RG2893 NVHS0_TX7 AW6
NVHS0_TX7_N
10K_0402_5%
VGA@
2
AM3 AM6
NVHS_TERMP NVHS_REFCLK AM5
NVHS_REFCLK_N
B B
AM2
EXT_REFCLK_SLI
N18E-G3
NVHS RX/TX N/A
@
A A

N18E-G3(8/8) NVLINK
5 4 3 2 1
5 4 3 2 1
UG1 MF=1 UG2 MF=2

C2 B4 C2 B4
<28> FBA_EDC0 C13 EDC0_A DQ0_A A3 FBA_D4 <28> <28> FBA_EDC4 C13 EDC0_A DQ0_A A3 FBA_D39 <28>
<28> FBA_EDC1 EDC1_A DQ1_A FBA_D7 <28> <28> FBA_EDC5 EDC1_A DQ1_A FBA_D35 <28>
T2 B3 T2 B3
<28> FBA_EDC3 T13 EDC0_B DQ2_A B2 FBA_D1 <28> <28> FBA_EDC7 T13 EDC0_B DQ2_A B2 FBA_D32 <28>
<28> FBA_EDC2 EDC1_B DQ3_A FBA_D5 <28> <28> FBA_EDC6 EDC1_B DQ3_A FBA_D38 <28>
E3 E3
DQ4_A E2 FBA_D3 <28> DQ4_A E2 FBA_D34 <28>
D2 DQ5_A F2 FBA_D6 <28> D2 DQ5_A F2 FBA_D33 <28>
<28> FBA_DBI0 DBI0#_A DQ6_A FBA_D2 <28> <28> FBA_DBI4 DBI0#_A DQ6_A FBA_D37 <28>
D13 G2 D13 G2
<28> FBA_DBI1 R2 DBI1#_A DQ7_A B11 FBA_D0 <28> <28> FBA_DBI5 R2 DBI1#_A DQ7_A B11 FBA_D36 <28>
<28> FBA_DBI3 DBI0#_B DQ8_A FBA_D8 <28> <28> FBA_DBI7 DBI0#_B DQ8_A FBA_D43 <28>
R13 A12 R13 A12
<28> FBA_DBI2 DBI1#_B DQ9_A B12 FBA_D15 <28> <28> FBA_DBI6 DBI1#_B DQ9_A B12 FBA_D46 <28>
DQ10_A B13 FBA_D13 <28> DQ10_A B13 FBA_D44 <28>
D DQ11_A FBA_D14 <28> DQ11_A FBA_D42 <28> D
J10 E12 J10 E12
<28> FBA_CLK0 K10 CK DQ12_A E13 FBA_D12 <28> <28> FBA_CLK1 K10 CK DQ12_A E13 FBA_D45 <28>
<28> FBA_CLK0# CK# DQ13_A FBA_D10 <28> <28> FBA_CLK1# CK# DQ13_A FBA_D40 <28>
G10 F13 G10 F13
<28> FBA_CMD10 M10 CKE#_A DQ14_A G13 FBA_D11 <28> <28> FBA_CMD26 M10 CKE#_A DQ14_A G13 FBA_D41 <28>
CKE#_B DQ15_A FBA_D9 <28> CKE#_B DQ15_A FBA_D47 <28>
U4 U4
DQ0_B V3 FBA_D30 <28> DQ0_B V3 FBA_D57 <28>
DQ1_B FBA_D29 <28> DQ1_B FBA_D56 <28>
U3 U3
J5 DQ2_B U2 FBA_D28 <28> J5 DQ2_B U2 FBA_D59 <28>
<28> FBA_CMD6 K5 CABI#_A DQ3_B P3 FBA_D31 <28> <28> FBA_CMD22 K5 CABI#_A DQ3_B P3 FBA_D58 <28>
CABI#_B DQ4_B FBA_D25 <28> CABI#_B DQ4_B FBA_D61 <28>
P2 P2
DQ5_B N2 FBA_D27 <28> DQ5_B N2 FBA_D60 <28>
DQ6_B FBA_D24 <28> DQ6_B FBA_D63 <28>
M2 M2
DQ7_B U11 FBA_D26 <28> DQ7_B U11 FBA_D62 <28>
DQ8_B V12 FBA_D23 <28> DQ8_B V12 FBA_D49 <28>
DQ9_B FBA_D22 <28> DQ9_B FBA_D50 <28>
RG2857 2 VGA@ 1 121_0402_1% J14 U12 RG2939 2 VGA@ 1 121_0402_1% J14 U12
2 VGA@ 1 K14 ZQ_A DQ10_B U13 FBA_D20 <28> 2 VGA@ 1 K14 ZQ_A DQ10_B U13 FBA_D53 <28>
RG108 121_0402_1% RG2938 121_0402_1%
ZQ_B DQ11_B FBA_D17 <28> ZQ_B DQ11_B FBA_D48 <28>
P12 P12
DQ12_B P13 FBA_D21 <28> DQ12_B P13 FBA_D52 <28>
DQ13_B N13 FBA_D16 <28> DQ13_B N13 FBA_D51 <28>
DQ14_B FBA_D19 <28> DQ14_B FBA_D54 <28>
M13 M13
DQ15_B FBA_D18 <28> DQ15_B FBA_D55 <28>
SNN_FBAL_TCK_M N5 H3 SNN_FBAU_TCK N5 H3
SNN_FBAL_TDI_M F10 TCK CA0_A G11 FBA_CMD0 <28> SNN_FBAU_TDI F10 TCK CA0_A G11 FBA_CMD20 <28>
SNN_FBAL_TDO_M TDI CA1_A FBA_CMD9 <28> SNN_FBAU_TDO TDI CA1_A FBA_CMD28 <28>
N10 G4 N10 G4
SNN_FBAL_TMS_M F5 TDO CA2_A H12 FBA_CMD8 <28> SNN_FBAU_TMS F5 TDO CA2_A H12 FBA_CMD21 <28>
TMS CA3_A FBA_CMD7 FBA_CMD32 <28> TMS CA3_A FBA_CMD23 FBA_CMD29 <28>
H5 H5
CA4_A H10 FBA_CMD11 FBA_CMD7 <28> CA4_A H10 FBA_CMD27 FBA_CMD23 <28>
CA5_A J12 FBA_CMD15 FBA_CMD11 <28> CA5_A J12 FBA_CMD30 FBA_CMD27 <28>
CA6_A FBA_CMD14 FBA_CMD15 <28> CA6_A FBA_CMD31 FBA_CMD30 <28>
J11 J11
CA7_A J4 FBA_CMD3 FBA_CMD14 <28> CA7_A J4 FBA_CMD19 FBA_CMD31 <28>
CA8_A FBA_CMD1 FBA_CMD3 <28> CA8_A FBA_CMD17 FBA_CMD19 <28>
J3 J3
CA9_A FBA_CMD1 <28> CA9_A FBA_CMD17 <28>
L3 L3
FBA_WCK01 CA0_B FBA_CMD4 <28> FBA_WCK45 CA0_B FBA_CMD16 <28>
D4 M11 D4 M11
<28> FBA_WCK01 FBA_WCK01# D5 WCK_A CA1_B M4 FBA_CMD12 <28> <28> FBA_WCK45 FBA_WCK45# D5 WCK_A CA1_B M4 FBA_CMD25 <28>
<28> FBA_WCK01# FBA_WCK23 WCK#_A CA2_B FBA_CMD5 <28> <28> FBA_WCK45# FBA_WCK67 WCK#_A CA2_B FBA_CMD24 <28>
R11 L12 R11 L12
<28> FBA_WCK23 FBA_WCK23# R10 WCK_B CA3_B L5 FBA_CMD7 FBA_CMD13 <28> <28> FBA_WCK67 FBA_WCK67# R10 WCK_B CA3_B L5 FBA_CMD23 FBA_CMD33 <28>
<28> FBA_WCK23# WCK#_B CA4_B L10 FBA_CMD11 <28> FBA_WCK67# WCK#_B CA4_B L10 FBA_CMD27
CA5_B K12 FBA_CMD15 CA5_B K12 FBA_CMD30
+FBA_VREFC K1 CA9_B +1.35VSDGPU +FBA_VREFC K1 CA9_B +1.35VSDGPU
VREFC VREFC
C1 C1
J1 VDDQ1 E1 J1 VDDQ1 E1
<28> FBA_CMD2 RESET# VDDQ2 H1 <28> FBA_CMD18 RESET# VDDQ2 H1
VDDQ3 L1 VDDQ3 L1
C B1 VDDQ4 P1 B1 VDDQ4 P1 C
D1 VSS1 VDDQ5 T1 D1 VSS1 VDDQ5 T1
F1 VSS2 VDDQ6 J2 F1 VSS2 VDDQ6 J2
G1 VSS3 VDDQ7 K2 G1 VSS3 VDDQ7 K2
M1 VSS4 VDDQ8 C4 M1 VSS4 VDDQ8 C4
N1 VSS5 VDDQ9 F4 N1 VSS5 VDDQ9 F4
R1 VSS6 VDDQ10 N4 R1 VSS6 VDDQ10 N4
Checklist 0723 update U1
A2
VSS7
VSS8
VDDQ11
VDDQ12
T4
B5
U1
A2
VSS7
VSS8
VDDQ11
VDDQ12
T4
B5
use GDDR6 internal, PD 1k to GND V2 VSS9
VSS10
VDDQ13
VDDQ14
U5 V2 VSS9
VSS10
VDDQ13
VDDQ14
U5
C3 B10 C3 B10
D3 VSS11 VDDQ15 U10 D3 VSS11 VDDQ15 U10
+1.35VSDGPU F3 VSS12 VDDQ16 C11 F3 VSS12 VDDQ16 C11
G3 VSS13 VDDQ17 F11 G3 VSS13 VDDQ17 F11
M3 VSS14 VDDQ18 N11 M3 VSS14 VDDQ18 N11
VSS15 VDDQ19 VSS15 VDDQ19
1
N3 T11 N3 T11
RG110 R3 VSS16 VDDQ20 J13 R3 VSS16 VDDQ20 J13
@ 549_0402_1% T3 VSS17 VDDQ21 K13 T3 VSS17 VDDQ21 K13
A4 VSS18 VDDQ22 C14 A4 VSS18 VDDQ22 C14
E4 VSS19 VDDQ23 E14 E4 VSS19 VDDQ23 E14
2
H4 VSS20 VDDQ24 H14 H4 VSS20 VDDQ24 H14

1 2 +FBA_VREFC W=16mils L4 VSS21
VSS22
VDDQ25
VDDQ26
L14 L4 VSS21
VSS22
VDDQ25
VDDQ26
L14
P4 P14 P4 P14
RG111 V4 VSS23 VDDQ27 T14 V4 VSS23 VDDQ27 T14
CG78
CG79
1 1
820P_0402_25V7
820P_0402_25V7

2
931_0402_1% C5 C5
1K_0402_5%
VSS25 VSS25
1
T5 T5
RG2875
@ VSS26 VSS26
VGA@ @ @ C10 A1 C10 A1
Drain
Source
2 2 T10 VSS27 VDD1 V1 T10 VSS27 VDD1 V1

Gate
A11 VSS28 VDD2 H2 A11 VSS28 VDD2 H2

1
@ E11 VSS29 VDD3 L2 E11 VSS29 VDD3 L2

H11 VSS30 VDD4 E5 H11 VSS30 VDD4 E5
2
QG2 L11 VSS31 VDD5 P5 L11 VSS31 VDD5 P5

P11 VSS32 VDD6 E10 P11 VSS32 VDD6 E10
<25,34,35,36> MEM_VREF LBSS139WT1G_SC70-3 VSS33 VDD7 VSS33 VDD7
V11 P10 V11 P10
C12 VSS34 VDD8 H13 C12 VSS34 VDD8 H13
D12 VSS35 VDD9 L13 D12 VSS35 VDD9 L13
F12 VSS36 VDD10 A14 F12 VSS36 VDD10 A14
G12 VSS37 VDD11 V14 G12 VSS37 VDD11 V14
M12 VSS38 VDD12 +1.8VSDGPU_AON M12 VSS38 VDD12 +1.8VSDGPU_AON
N12 VSS39 N12 VSS39
R12 VSS40 A5 R12 VSS40 A5
T12 VSS41 VPP1 V5 T12 VSS41 VPP1 V5
A13 VSS42 VPP2 A10 A13 VSS42 VPP2 A10
V13 VSS43 VPP3 V10 V13 VSS43 VPP3 V10
B14 VSS44 VPP4 B14 VSS44 VPP4
D14 VSS45 R4 FBA_WCKB23 D14 VSS45 R4 FBA_WCKB67
F14 VSS46 WCK0_t_B,NC R5 FBA_WCKB23# FBA_WCKB23 <28> F14 VSS46 WCK0_t_B,NC R5 FBA_WCKB67# FBA_WCKB67 <28>
VSS47 WCK0_c_B,NC FBA_WCKB23# <28> VSS47 WCK0_c_B,NC FBA_WCKB67# <28>
G14 G14
M14 VSS48 G5 SNN_FBAL_RFU_A_M M14 VSS48 G5 SNN_FBAU_RFU_A
N14 VSS49 RFU_A,NC M5 SNN_FBAL_RFU_B_M N14 VSS49 RFU_A,NC M5 SNN_FBAU_RFU_B
B R14 VSS50 RFU_B,NC R14 VSS50 RFU_B,NC B
U14 VSS51 D10 FBA_WCKB01# U14 VSS51 D10 FBA_WCKB45#
180-BALL FBA_WCKB01# <28> 180-BALL FBA_WCKB45# <28>
VSS52 SGRAM GDDR6 WCK1_c_A,NC D11 FBA_WCKB01 VSS52 SGRAM GDDR6 WCK1_c_A,NC D11 FBA_WCKB45
WCK1_t_A,NC FBA_WCKB01 <28> WCK1_t_A,NC FBA_WCKB45 <28>
K4Z80325BC-HC14_FBGA180~D K4Z80325BC-HC14_FBGA180~D
X76@ X76@
+1.35VSDGPU
+1.35VSDGPU
Close to DRAM Close to DRAM
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
CG1305
CG1311
CG1313
CG1312
CG1314
CG1315
CG1316
CG1317
CG1319
CG1318
CG1320
CG1321
1 1 1 1 1 1 1 1 1 1 1 1
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
CG1302
CG1301
CG1303
CG2817
CG2816
CG2818
2 2 2 2 2 2
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
CG1234
CG1235
CG1236
CG1237
CG1239
CG1238
CG1240
CG1241
CG1243
CG1242
CG1244
CG1245
1 1 1 1 1 1 1 1 1 1 1 1
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
2 2 2 2 2 2 2 2 2 2 2 2 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@

CG1276
CG1275
CG1277
CG2814
CG2813
CG2815
2 2 2 2 2 2 1 1 1 1 1 1
1 1 1 1 1 1
+1.35VSDGPU Right under DRAM +1.35VSDGPU

around DRAM
around DRAM
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
CG1322
CG1323
CG1324
CG1325
CG1326
CG1327
CG1329
CG1328
CG1331
CG1330
CG1332
CG1333
1 1 1 1 1 1 1 1 1 1 1 1
1
CG1304
CG1306
CG1307
CG1308
CG1309
CG1310
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
CG1246
CG1247
CG1249
CG1248
CG1250
CG1251
CG1252
CG1253
CG1255
CG1254
CG1256
CG1257
1 1 1 1 1 1 1 1 1 1 1 1
2
1
2 2 2 2 2 2 2 2 2 2 2 2
CG1278
CG1279
CG1280
CG1281
CG1282
CG1283
2
2 2 2 2 2 2 2 2 2 2 2 2
+1.35VSDGPU Close to DRAM +1.8VSDGPU_AON
A +1.35VSDGPU Close to DRAM +1.8VSDGPU_AON A
4.7U_0402_6.3V6M
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
CG1285
CG1284
CG1286
CG1288
CG1287
CG1289
CG1292
CG1290
CG1293
CG1291
CG1294
CG1295
CG1298
CG1296
CG1297
CG1299
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CG1300
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
4.7U_0402_6.3V6M
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
CG1258
CG1259
CG1260
CG1261
CG1262
CG1263
CG1265
CG1264
CG1267
CG1266
CG1268
CG1269
CG1271
CG1270
CG1272
CG1273
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CG1274
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

N18E-GDDR6_A
5 4 3 2 1
5 4 3 2 1
UG3 MF=1 UG4 MF=2

C2 B4 C2 B4
<28> FBB_EDC0 C13 EDC0_A DQ0_A A3 FBB_D1 <28> <28> FBB_EDC4 C13 EDC0_A DQ0_A A3 FBB_D35 <28>
<28> FBB_EDC1 EDC1_A DQ1_A FBB_D6 <28> <28> FBB_EDC5 EDC1_A DQ1_A FBB_D33 <28>
T2 B3 T2 B3
<28> FBB_EDC3 T13 EDC0_B DQ2_A B2 FBB_D2 <28> <28> FBB_EDC7 T13 EDC0_B DQ2_A B2 FBB_D32 <28>
<28> FBB_EDC2 EDC1_B DQ3_A FBB_D4 <28> <28> FBB_EDC6 EDC1_B DQ3_A FBB_D36 <28>
E3 E3
DQ4_A E2 FBB_D5 <28> DQ4_A E2 FBB_D39 <28>
D2 DQ5_A F2 FBB_D3 <28> D2 DQ5_A F2 FBB_D34 <28>
<28> FBB_DBI0 DBI0#_A DQ6_A FBB_D0 <28> <28> FBB_DBI4 DBI0#_A DQ6_A FBB_D37 <28>
D13 G2 D13 G2
<28> FBB_DBI1 R2 DBI1#_A DQ7_A B11 FBB_D7 <28> <28> FBB_DBI5 R2 DBI1#_A DQ7_A B11 FBB_D38 <28>
<28> FBB_DBI3 DBI0#_B DQ8_A FBB_D13 <28> <28> FBB_DBI7 DBI0#_B DQ8_A FBB_D42 <28>
R13 A12 R13 A12
<28> FBB_DBI2 DBI1#_B DQ9_A B12 FBB_D14 <28> <28> FBB_DBI6 DBI1#_B DQ9_A B12 FBB_D43 <28>
DQ10_A B13 FBB_D12 <28> DQ10_A B13 FBB_D40 <28>
D DQ11_A FBB_D11 <28> DQ11_A FBB_D45 <28> D
J10 E12 J10 E12
<28> FBB_CLK0 K10 CK DQ12_A E13 FBB_D15 <28> <28> FBB_CLK1 K10 CK DQ12_A E13 FBB_D41 <28>
<28> FBB_CLK0# CK# DQ13_A FBB_D8 <28> <28> FBB_CLK1# CK# DQ13_A FBB_D44 <28>
G10 F13 G10 F13
<28> FBB_CMD10 M10 CKE#_A DQ14_A G13 FBB_D9 <28> <28> FBB_CMD26 M10 CKE#_A DQ14_A G13 FBB_D46 <28>
CKE#_B DQ15_A FBB_D10 <28> CKE#_B DQ15_A FBB_D47 <28>
U4 U4
DQ0_B V3 FBB_D24 <28> DQ0_B V3 FBB_D62 <28>
DQ1_B FBB_D30 <28> DQ1_B FBB_D59 <28>
U3 U3
J5 DQ2_B U2 FBB_D29 <28> J5 DQ2_B U2 FBB_D57 <28>
<28> FBB_CMD6 K5 CABI#_A DQ3_B P3 FBB_D31 <28> <28> FBB_CMD22 K5 CABI#_A DQ3_B P3 FBB_D63 <28>
CABI#_B DQ4_B FBB_D25 <28> CABI#_B DQ4_B FBB_D56 <28>
P2 P2
DQ5_B N2 FBB_D26 <28> DQ5_B N2 FBB_D61 <28>
DQ6_B FBB_D27 <28> DQ6_B FBB_D60 <28>
M2 M2
DQ7_B U11 FBB_D28 <28> DQ7_B U11 FBB_D58 <28>
DQ8_B V12 FBB_D21 <28> DQ8_B V12 FBB_D55 <28>
DQ9_B FBB_D16 <28> DQ9_B FBB_D48 <28>
RG2943 2 VGA@ 1 121_0402_1% J14 U12 RG2940 2 VGA@ 1 121_0402_1% J14 U12
2 VGA@ 1 K14 ZQ_A DQ10_B U13 FBB_D20 <28> 2 VGA@ 1 K14 ZQ_A DQ10_B U13 FBB_D52 <28>
RG2942 121_0402_1% RG2941 121_0402_1%
ZQ_B DQ11_B FBB_D17 <28> ZQ_B DQ11_B FBB_D50 <28>
P12 P12
DQ12_B P13 FBB_D18 <28> DQ12_B P13 FBB_D49 <28>
DQ13_B N13 FBB_D22 <28> DQ13_B N13 FBB_D51 <28>
DQ14_B FBB_D23 <28> DQ14_B FBB_D53 <28>
M13 M13
DQ15_B FBB_D19 <28> DQ15_B FBB_D54 <28>
SNN_FBBL_TCK_M N5 H3 SNN_FBBU_TCK N5 H3
SNN_FBBL_TDI_M F10 TCK CA0_A G11 FBB_CMD0 <28> SNN_FBBU_TDI F10 TCK CA0_A G11 FBB_CMD20 <28>
SNN_FBBL_TDO_M TDI CA1_A FBB_CMD9 <28> SNN_FBBU_TDO TDI CA1_A FBB_CMD28 <28>
N10 G4 N10 G4
SNN_FBBL_TMS_M F5 TDO CA2_A H12 FBB_CMD8 <28> SNN_FBBU_TMS F5 TDO CA2_A H12 FBB_CMD21 <28>
TMS CA3_A FBB_CMD7 FBB_CMD32 <28> TMS CA3_A FBB_CMD23 FBB_CMD29 <28>
H5 H5
CA4_A H10 FBB_CMD11 FBB_CMD7 <28> CA4_A H10 FBB_CMD27 FBB_CMD23 <28>
CA5_A J12 FBB_CMD15 FBB_CMD11 <28> CA5_A J12 FBB_CMD30 FBB_CMD27 <28>
CA6_A FBB_CMD14 FBB_CMD15 <28> CA6_A FBB_CMD31 FBB_CMD30 <28>
J11 J11
CA7_A J4 FBB_CMD3 FBB_CMD14 <28> CA7_A J4 FBB_CMD19 FBB_CMD31 <28>
CA8_A FBB_CMD1 FBB_CMD3 <28> CA8_A FBB_CMD17 FBB_CMD19 <28>
J3 J3
CA9_A FBB_CMD1 <28> CA9_A FBB_CMD17 <28>
L3 L3
FBB_WCK01 CA0_B FBB_CMD4 <28> FBB_WCK45 CA0_B FBB_CMD16 <28>
D4 M11 D4 M11
<28> FBB_WCK01 FBB_WCK01# D5 WCK_A CA1_B M4 FBB_CMD12 <28> <28> FBB_WCK45 FBB_WCK45# D5 WCK_A CA1_B M4 FBB_CMD25 <28>
<28> FBB_WCK01# FBB_WCK23 WCK#_A CA2_B FBB_CMD5 <28> <28> FBB_WCK45# FBB_WCK67 WCK#_A CA2_B FBB_CMD24 <28>
R11 L12 R11 L12
<28> FBB_WCK23 FBB_WCK23# R10 WCK_B CA3_B L5 FBB_CMD7 FBB_CMD13 <28> <28> FBB_WCK67 FBB_WCK67# R10 WCK_B CA3_B L5 FBB_CMD23 FBB_CMD33 <28>
<28> FBB_WCK23# WCK#_B CA4_B L10 FBB_CMD11 <28> FBB_WCK67# WCK#_B CA4_B L10 FBB_CMD27
CA5_B K12 FBB_CMD15 CA5_B K12 FBB_CMD30
+FBB_VREFC K1 CA9_B +1.35VSDGPU +FBB_VREFC K1 CA9_B +1.35VSDGPU
VREFC VREFC
C1 C1
<28> FBB_CMD2 RESET# VDDQ2 H1 <28> FBB_CMD18 RESET# VDDQ2 H1
VDDQ3 L1 VDDQ3 L1
Checklist 0723 update M1 VSS4
VSS5
VDDQ8
VDDQ9
C4 M1 VSS4
VSS5
VDDQ8
VDDQ9
C4
N1 F4 N1 F4
use GDDR6 internal, PD 1k to GND R1 VSS6
VSS7
VDDQ10
VDDQ11
N4 R1 VSS6
VSS7
VDDQ10
VDDQ11
N4
U1 T4 U1 T4
+1.35VSDGPU A2 VSS8 VDDQ12 B5 A2 VSS8 VDDQ12 B5
V2 VSS9 VDDQ13 U5 V2 VSS9 VDDQ13 U5
C3 VSS10 VDDQ14 B10 C3 VSS10 VDDQ14 B10
1

RG121 F3 VSS12 VDDQ16 C11 F3 VSS12 VDDQ16 C11
549_0402_1% G3 VSS13 VDDQ17 F11 G3 VSS13 VDDQ17 F11
N3 VSS15 VDDQ19 T11 N3 VSS15 VDDQ19 T11
2
R3 VSS16 VDDQ20 J13 R3 VSS16 VDDQ20 J13

1 2
@ +FBB_VREFC W=16mils T3
A4
VSS17
VSS18
VDDQ21
VDDQ22
K13
C14
T3
A4
VSS17
VSS18
VDDQ21
VDDQ22
K13
C14
RG122 E4 VSS19 VDDQ23 E14 E4 VSS19 VDDQ23 E14
CG113
CG114
1 1
820P_0402_25V7
820P_0402_25V7

2
931_0402_1% H4 H14 H4 H14

1K_0402_5%
L4 VSS21 VDDQ25 L14 L4 VSS21 VDDQ25 L14

RG2874
@ VSS22 VDDQ26 VSS22 VDDQ26

1
VGA@ @ @ P4 P14 P4 P14

2 2 V4 VSS23 VDDQ27 T14 V4 VSS23 VDDQ27 T14
Drain
Source
C5 VSS24 VDDQ28 C5 VSS24 VDDQ28

Gate
T5 VSS25 T5 VSS25
@ C10 VSS26 A1 C10 VSS26 A1
T10 VSS27 VDD1 V1 T10 VSS27 VDD1 V1
2
QG3 A11 VSS28 VDD2 H2 A11 VSS28 VDD2 H2

E11 VSS29 VDD3 L2 E11 VSS29 VDD3 L2
H11 E5 H11 E5
L11 VSS31 VDD5 P5 L11 VSS31 VDD5 P5
V11 VSS33 VDD7 P10 V11 VSS33 VDD7 P10
N12 VSS39 N12 VSS39
D14 VSS45 R4 FBB_WCKB23 D14 VSS45 R4 FBB_WCKB67
F14 VSS46 WCK0_t_B,NC R5 FBB_WCKB23# FBB_WCKB23 <28> F14 VSS46 WCK0_t_B,NC R5 FBB_WCKB67# FBB_WCKB67 <28>
VSS47 WCK0_c_B,NC FBB_WCKB23# <28> VSS47 WCK0_c_B,NC FBB_WCKB67# <28>
G14 G14
M14 VSS48 G5 SNN_FBBL_RFU_A_M M14 VSS48 G5 SNN_FBBU_RFU_A
N14 VSS49 RFU_A,NC M5 SNN_FBBL_RFU_B_M N14 VSS49 RFU_A,NC M5 SNN_FBBU_RFU_B
U14 VSS51 D10 FBB_WCKB01# U14 VSS51 D10 FBB_WCKB45#
180-BALL 180-BALL FBB_WCKB45# <28>
VSS52 SGRAM GDDR6 WCK1_c_A,NC D11 FBB_WCKB01 FBB_WCKB01# <28> VSS52 SGRAM GDDR6 WCK1_c_A,NC D11 FBB_WCKB45
WCK1_t_A,NC FBB_WCKB01 <28> WCK1_t_A,NC FBB_WCKB45 <28>
X76@ X76@ additional, X5R
+1.35VSDGPU
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
+1.35VSDGPU
CG1405
CG1411
CG1413
CG1412
CG1414
CG1415
CG1416
CG1417
CG1419
CG1418
CG1420
CG1421
1 1 1 1 1 1 1 1 1 1 1 1
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
CG1402
CG1401
CG1403
CG2823
CG2822
CG2824
2 2 2 2 2 2
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN

CG1355
CG1361
CG1363
CG1362
CG1364
CG1365
CG1366
CG1367
CG1369
CG1368
CG1370
CG1371
1 1 1 1 1 1 1 1 1 1 1 1
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1 1 1 1 1 1
CG1352
CG1351
CG1353
CG2820
CG2819
CG2821
2 2 2 2 2 2
1 1 1 1 1 1

around DRAM
Right under DRAM
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
CG1422
CG1423
CG1424
CG1425
CG1426
CG1427
CG1429
CG1428
CG1431
CG1430
CG1432
CG1433
1 1 1 1 1 1 1 1 1 1 1 1
around DRAM
1
CG1404
CG1406
CG1407
CG1408
CG1409
CG1410
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
2 2 2 2 2 2 2 2 2 2 2 2
CG1372
CG1373
CG1374
CG1375
CG1376
CG1377
CG1379
CG1378
CG1381
CG1380
CG1382
CG1383
1 1 1 1 1 1 1 1 1 1 1 1
1
1
CG1354
CG1356
CG1357
CG1358
CG1359
CG1360
2
2 2 2 2 2 2 2 2 2 2 2 2
Close to DRAM
4.7U_0402_6.3V6M
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
A +1.35VSDGPU +1.8VSDGPU_AON A
CG1385
CG1384
CG1386
CG1388
CG1387
CG1389
CG1392
CG1390
CG1393
CG1391
CG1394
CG1395
CG1398
CG1396
CG1397
CG1399
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CG1400
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
4.7U_0402_6.3V6M
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CG1335
CG1334
CG1336
CG1338
CG1337
CG1339
CG1342
CG1340
CG1343
CG1341
CG1344
CG1345
CG1348
CG1346
CG1347
CG1349
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CG1350
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

N18E-GDDR6_B
5 4 3 2 1
5 4 3 2 1
0805 follow CRB_004
UG5 MF=1 UG6 MF=2

C2 B4 C2 B4
<28> FBC_EDC0 C13 EDC0_A DQ0_A A3 FBC_D1 <28> <28> FBC_EDC4 C13 EDC0_A DQ0_A A3 FBC_D38 <28>
<28> FBC_EDC1 EDC1_A DQ1_A FBC_D7 <28> <28> FBC_EDC5 EDC1_A DQ1_A FBC_D34 <28>
T2 B3 T2 B3
<28> FBC_EDC3 T13 EDC0_B DQ2_A B2 FBC_D5 <28> <28> FBC_EDC7 T13 EDC0_B DQ2_A B2 FBC_D36 <28>
<28> FBC_EDC2 EDC1_B DQ3_A FBC_D4 <28> <28> FBC_EDC6 EDC1_B DQ3_A FBC_D39 <28>
E3 E3
DQ4_A E2 FBC_D6 <28> DQ4_A E2 FBC_D35 <28>
D2 DQ5_A F2 FBC_D3 <28> D2 DQ5_A F2 FBC_D32 <28>
<28> FBC_DBI0 DBI0#_A DQ6_A FBC_D0 <28> <28> FBC_DBI4 DBI0#_A DQ6_A FBC_D33 <28>
D13 G2 D13 G2
<28> FBC_DBI1 R2 DBI1#_A DQ7_A B11 FBC_D2 <28> <28> FBC_DBI5 R2 DBI1#_A DQ7_A B11 FBC_D37 <28>
<28> FBC_DBI3 DBI0#_B DQ8_A FBC_D14 <28> <28> FBC_DBI7 DBI0#_B DQ8_A FBC_D40 <28>
R13 A12 R13 A12
<28> FBC_DBI2 DBI1#_B DQ9_A B12 FBC_D15 <28> <28> FBC_DBI6 DBI1#_B DQ9_A B12 FBC_D43 <28>
DQ10_A B13 FBC_D8 <28> DQ10_A B13 FBC_D46 <28>
D DQ11_A FBC_D12 <28> DQ11_A FBC_D42 <28> D
J10 E12 J10 E12
<28> FBC_CLK0 K10 CK DQ12_A E13 FBC_D13 <28> <28> FBC_CLK1 K10 CK DQ12_A E13 FBC_D44 <28>
<28> FBC_CLK0# CK# DQ13_A FBC_D9 <28> <28> FBC_CLK1# CK# DQ13_A FBC_D45 <28>
G10 F13 G10 F13
<28> FBC_CMD10 M10 CKE#_A DQ14_A G13 FBC_D11 <28> <28> FBC_CMD26 M10 CKE#_A DQ14_A G13 FBC_D47 <28>
CKE#_B DQ15_A FBC_D10 <28> CKE#_B DQ15_A FBC_D41 <28>
U4 U4
DQ0_B V3 FBC_D25 <28> DQ0_B V3 FBC_D56 <28>
DQ1_B FBC_D29 <28> DQ1_B FBC_D57 <28>
U3 U3
J5 DQ2_B U2 FBC_D28 <28> J5 DQ2_B U2 FBC_D58 <28>
<28> FBC_CMD6 K5 CABI#_A DQ3_B P3 FBC_D31 <28> <28> FBC_CMD22 K5 CABI#_A DQ3_B P3 FBC_D59 <28>
CABI#_B DQ4_B FBC_D26 <28> CABI#_B DQ4_B FBC_D60 <28>
P2 P2
DQ5_B N2 FBC_D24 <28> DQ5_B N2 FBC_D61 <28>
DQ6_B FBC_D30 <28> DQ6_B FBC_D62 <28>
M2 M2
DQ7_B U11 FBC_D27 <28> DQ7_B U11 FBC_D63 <28>
DQ8_B V12 FBC_D23 <28> DQ8_B V12 FBC_D51 <28>
DQ9_B FBC_D20 <28> DQ9_B FBC_D50 <28>
RG2947 2 VGA@ 1 121_0402_1% J14 U12 RG2944 2 VGA@ 1 121_0402_1% J14 U12
2 VGA@ 1 K14 ZQ_A DQ10_B U13 FBC_D22 <28> 2 VGA@ 1 K14 ZQ_A DQ10_B U13 FBC_D48 <28>
RG2946 121_0402_1% RG2945 121_0402_1%
ZQ_B DQ11_B FBC_D21 <28> ZQ_B DQ11_B FBC_D49 <28>
P12 P12
DQ12_B P13 FBC_D18 <28> DQ12_B P13 FBC_D53 <28>
DQ13_B N13 FBC_D19 <28> DQ13_B N13 FBC_D52 <28>
DQ14_B FBC_D17 <28> DQ14_B FBC_D55 <28>
M13 M13
DQ15_B FBC_D16 <28> DQ15_B FBC_D54 <28>
SNN_FBCL_TCK_M N5 H3 SNN_FBCU_TCK N5 H3
SNN_FBCL_TDI_M F10 TCK CA0_A G11 FBC_CMD0 <28> SNN_FBCU_TDI F10 TCK CA0_A G11 FBC_CMD20 <28>
SNN_FBCL_TDO_M TDI CA1_A FBC_CMD9 <28> SNN_FBCU_TDO TDI CA1_A FBC_CMD28 <28>
N10 G4 N10 G4
SNN_FBCL_TMS_M F5 TDO CA2_A H12 FBC_CMD8 <28> SNN_FBCU_TMS F5 TDO CA2_A H12 FBC_CMD21 <28>
TMS CA3_A FBC_CMD7 FBC_CMD32 <28> TMS CA3_A FBC_CMD23 FBC_CMD29 <28>
H5 H5
CA4_A H10 FBC_CMD11 FBC_CMD7 <28> CA4_A H10 FBC_CMD27 FBC_CMD23 <28>
CA5_A J12 FBC_CMD15 FBC_CMD11 <28> CA5_A J12 FBC_CMD30 FBC_CMD27 <28>
CA6_A FBC_CMD14 FBC_CMD15 <28> CA6_A FBC_CMD31 FBC_CMD30 <28>
J11 J11
CA7_A J4 FBC_CMD3 FBC_CMD14 <28> CA7_A J4 FBC_CMD19 FBC_CMD31 <28>
CA8_A FBC_CMD1 FBC_CMD3 <28> CA8_A FBC_CMD17 FBC_CMD19 <28>
J3 J3
CA9_A FBC_CMD1 <28> CA9_A FBC_CMD17 <28>
L3 L3
FBC_WCK01 CA0_B FBC_CMD4 <28> FBC_WCK45 CA0_B FBC_CMD16 <28>
D4 M11 D4 M11
<28> FBC_WCK01 FBC_WCK01# D5 WCK_A CA1_B M4 FBC_CMD12 <28> <28> FBC_WCK45 FBC_WCK45# D5 WCK_A CA1_B M4 FBC_CMD25 <28>
<28> FBC_WCK01# FBC_WCK23 WCK#_A CA2_B FBC_CMD5 <28> <28> FBC_WCK45# FBC_WCK67 WCK#_A CA2_B FBC_CMD24 <28>
R11 L12 R11 L12
<28> FBC_WCK23 FBC_WCK23# R10 WCK_B CA3_B L5 FBC_CMD7 FBC_CMD13 <28> <28> FBC_WCK67 FBC_WCK67# R10 WCK_B CA3_B L5 FBC_CMD23 FBC_CMD33 <28>
<28> FBC_WCK23# WCK#_B CA4_B L10 FBC_CMD11 <28> FBC_WCK67# WCK#_B CA4_B L10 FBC_CMD27
CA5_B K12 FBC_CMD15 CA5_B K12 FBC_CMD30
+FBC_VREFC K1 CA9_B +1.35VSDGPU +FBC_VREFC K1 CA9_B +1.35VSDGPU
VREFC VREFC
C1 C1
<28> FBC_CMD2 RESET# VDDQ2 H1 <28> FBC_CMD18 RESET# VDDQ2 H1
VDDQ3 L1 VDDQ3 L1
R1 VSS6 VDDQ10 N4 R1 VSS6 VDDQ10 N4
Checklist 0723 update U1
A2
VSS7
VSS8
VDDQ11
VDDQ12
T4
B5
U1
A2
VSS7
VSS8
VDDQ11
VDDQ12
T4
B5
use GDDR6 internal, PD 1k to GND V2 VSS9
VSS10
VDDQ13
VDDQ14
U5 V2 VSS9
VSS10
VDDQ13
VDDQ14
U5
C3 B10 C3 B10
+1.35VSDGPU F3 VSS12 VDDQ16 C11 F3 VSS12 VDDQ16 C11
1
N3 T11 N3 T11
RG132 R3 VSS16 VDDQ20 J13 R3 VSS16 VDDQ20 J13
@ 549_0402_1% T3 VSS17 VDDQ21 K13 T3 VSS17 VDDQ21 K13
2
H4 VSS20 VDDQ24 H14 H4 VSS20 VDDQ24 H14

1 2 +FBC_VREFC L4 VSS21 VDDQ25 L14 L4 VSS21 VDDQ25 L14
P4 VSS22 VDDQ26 P14 P4 VSS22 VDDQ26 P14
RG133 V4 VSS23 VDDQ27 T14 V4 VSS23 VDDQ27 T14
CG148
CG149
1 1
820P_0402_25V7
820P_0402_25V7

2
931_0402_1% C5 C5
1K_0402_5%
T5 VSS25 T5 VSS25
RG2873
@ VSS26 VSS26
VGA@ @ @ C10 A1 C10 A1
VSS27 VDD1 VSS27 VDD1
1
2 2 T10 V1 T10 V1
Drain
Source
E11 VSS29 VDD3 L2 E11 VSS29 VDD3 L2

Gate

@ L11 VSS31 VDD5 P5 L11 VSS31 VDD5 P5
2
QG4 V11 VSS33 VDD7 P10 V11 VSS33 VDD7 P10

D12 L13 D12 L13
N12 VSS39 N12 VSS39
D14 VSS45 R4 FBC_WCKB23 D14 VSS45 R4 FBC_WCKB67
F14 VSS46 WCK0_t_B,NC R5 FBC_WCKB23# FBC_WCKB23 <28> F14 VSS46 WCK0_t_B,NC R5 FBC_WCKB67# FBC_WCKB67 <28>
VSS47 WCK0_c_B,NC FBC_WCKB23# <28> VSS47 WCK0_c_B,NC FBC_WCKB67# <28>
G14 G14
M14 VSS48 G5 SNN_FBCL_RFU_A_M M14 VSS48 G5 SNN_FBCU_RFU_A
N14 VSS49 RFU_A,NC M5 SNN_FBCL_RFU_B_M N14 VSS49 RFU_A,NC M5 SNN_FBCU_RFU_B
U14 VSS51 D10 FBC_WCKB01# U14 VSS51 D10 FBC_WCKB45#
180-BALL FBC_WCKB01# <28> 180-BALL FBC_WCKB45# <28>
VSS52 SGRAM GDDR6 WCK1_c_A,NC D11 FBC_WCKB01 VSS52 SGRAM GDDR6 WCK1_c_A,NC D11 FBC_WCKB45
WCK1_t_A,NC FBC_WCKB01 <28> WCK1_t_A,NC FBC_WCKB45 <28>
X76@ X76@
+1.35VSDGPU
+1.35VSDGPU
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
CG1505
CG1511
CG1513
CG1512
CG1514
CG1515
CG1516
CG1517
CG1519
CG1518
CG1520
CG1521
1 1 1 1 1 1 1 1 1 1 1 1
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
CG1502
CG1501
CG1503
CG2829
CG2828
CG2830
2 2 2 2 2 2
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
CG1455
CG1461
CG1463
CG1462
CG1464
CG1465
CG1466
CG1467
CG1469
CG1468
CG1470
CG1471
1 1 1 1 1 1 1 1 1 1 1 1
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
CG1452
CG1451
CG1453
CG2826
CG2825
CG2827
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@

VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ 1 1 1 1 1 1
1 1 1 1 1 1

around DRAM
around DRAM
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
CG1522
CG1523
CG1524
CG1525
CG1526
CG1527
CG1529
CG1528
CG1531
CG1530
CG1532
CG1533
1 1 1 1 1 1 1 1 1 1 1 1
1
CG1504
CG1506
CG1507
CG1508
CG1509
CG1510
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
CG1472
CG1473
CG1474
CG1475
CG1476
CG1477
CG1479
CG1478
CG1481
CG1480
CG1482
CG1483
1 1 1 1 1 1 1 1 1 1 1 1
1
CG1454
CG1456
CG1457
CG1458
CG1459
CG1460
2
2 2 2 2 2 2 2 2 2 2 2 2
2
2 2 2 2 2 2 2 2 2 2 2 2
A A
4.7U_0402_6.3V6M
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
CG1485
CG1484
CG1486
CG1488
CG1487
CG1489
CG1492
CG1490
CG1493
CG1491
CG1494
CG1495
CG1498
CG1496
CG1497
CG1499
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CG1500
4.7U_0402_6.3V6M
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
CG1435
CG1434
CG1436
CG1438
CG1437
CG1439
CG1442
CG1440
CG1443
CG1441
CG1444
CG1445
CG1448
CG1446
CG1447
CG1449
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CG1450
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

additional, X5R 2017/11/23 2017/12/31 Title
N18E-GDDR6_C
5 4 3 2 1
5 4 3 2 1
UG7 MF=1 UG8 MF=2

C2 B4 C2 B4
<28> FBD_EDC0 C13 EDC0_A DQ0_A A3 FBD_D5 <28> <28> FBD_EDC4 C13 EDC0_A DQ0_A A3 FBD_D35 <28>
<28> FBD_EDC1 EDC1_A DQ1_A FBD_D1 <28> <28> FBD_EDC5 EDC1_A DQ1_A FBD_D33 <28>
T2 B3 T2 B3
<28> FBD_EDC3 T13 EDC0_B DQ2_A B2 FBD_D0 <28> <28> FBD_EDC7 T13 EDC0_B DQ2_A B2 FBD_D32 <28>
<28> FBD_EDC2 EDC1_B DQ3_A FBD_D3 <28> <28> FBD_EDC6 EDC1_B DQ3_A FBD_D37 <28>
E3 E3
DQ4_A E2 FBD_D6 <28> DQ4_A E2 FBD_D34 <28>
D2 DQ5_A F2 FBD_D7 <28> D2 DQ5_A F2 FBD_D39 <28>
<28> FBD_DBI0 DBI0#_A DQ6_A FBD_D2 <28> <28> FBD_DBI4 DBI0#_A DQ6_A FBD_D36 <28>
D13 G2 D13 G2
<28> FBD_DBI1 R2 DBI1#_A DQ7_A B11 FBD_D4 <28> <28> FBD_DBI5 R2 DBI1#_A DQ7_A B11 FBD_D38 <28>
<28> FBD_DBI3 DBI0#_B DQ8_A FBD_D13 <28> <28> FBD_DBI7 DBI0#_B DQ8_A FBD_D43 <28>
R13 A12 R13 A12
<28> FBD_DBI2 DBI1#_B DQ9_A B12 FBD_D14 <28> <28> FBD_DBI6 DBI1#_B DQ9_A B12 FBD_D41 <28>
DQ10_A B13 FBD_D8 <28> DQ10_A B13 FBD_D42 <28>
D DQ11_A FBD_D12 <28> DQ11_A FBD_D40 <28> D
J10 E12 J10 E12
<28> FBD_CLK0 K10 CK DQ12_A E13 FBD_D10 <28> <28> FBD_CLK1 K10 CK DQ12_A E13 FBD_D46 <28>
<28> FBD_CLK0# CK# DQ13_A FBD_D15 <28> <28> FBD_CLK1# CK# DQ13_A FBD_D44 <28>
G10 F13 G10 F13
<28> FBD_CMD10 M10 CKE#_A DQ14_A G13 FBD_D9 <28> <28> FBD_CMD26 M10 CKE#_A DQ14_A G13 FBD_D47 <28>
CKE#_B DQ15_A FBD_D11 <28> CKE#_B DQ15_A FBD_D45 <28>
U4 U4
DQ0_B V3 FBD_D30 <28> DQ0_B V3 FBD_D56 <28>
DQ1_B FBD_D28 <28> DQ1_B FBD_D59 <28>
U3 U3
J5 DQ2_B U2 FBD_D26 <28> J5 DQ2_B U2 FBD_D58 <28>
<28> FBD_CMD6 K5 CABI#_A DQ3_B P3 FBD_D31 <28> <28> FBD_CMD22 K5 CABI#_A DQ3_B P3 FBD_D60 <28>
CABI#_B DQ4_B FBD_D25 <28> CABI#_B DQ4_B FBD_D57 <28>
P2 P2
DQ5_B N2 FBD_D27 <28> DQ5_B N2 FBD_D62 <28>
DQ6_B FBD_D29 <28> DQ6_B FBD_D61 <28>
M2 M2
DQ7_B U11 FBD_D24 <28> DQ7_B U11 FBD_D63 <28>
DQ8_B V12 FBD_D23 <28> DQ8_B V12 FBD_D49 <28>
DQ9_B FBD_D21 <28> DQ9_B FBD_D48 <28>
RG2951 2 VGA@ 1 121_0402_1% J14 U12 RG2948 2 VGA@ 1 121_0402_1% J14 U12
2 VGA@ 1 K14 ZQ_A DQ10_B U13 FBD_D22 <28> 2 VGA@ 1 K14 ZQ_A DQ10_B U13 FBD_D52 <28>
RG2950 121_0402_1% RG2949 121_0402_1%
ZQ_B DQ11_B FBD_D20 <28> ZQ_B DQ11_B FBD_D50 <28>
P12 P12
DQ12_B P13 FBD_D17 <28> DQ12_B P13 FBD_D55 <28>
DQ13_B N13 FBD_D19 <28> DQ13_B N13 FBD_D53 <28>
DQ14_B FBD_D16 <28> DQ14_B FBD_D51 <28>
M13 M13
DQ15_B FBD_D18 <28> DQ15_B FBD_D54 <28>
SNN_FBDL_TCK_M N5 H3 SNN_FBDU_TCK N5 H3
SNN_FBDL_TDI_M F10 TCK CA0_A G11 FBD_CMD0 <28> SNN_FBDU_TDI F10 TCK CA0_A G11 FBD_CMD20 <28>
SNN_FBDL_TDO_M TDI CA1_A FBD_CMD9 <28> SNN_FBDU_TDO TDI CA1_A FBD_CMD28 <28>
N10 G4 N10 G4
SNN_FBDL_TMS_M F5 TDO CA2_A H12 FBD_CMD8 <28> SNN_FBDU_TMS F5 TDO CA2_A H12 FBD_CMD21 <28>
TMS CA3_A FBD_CMD7 FBD_CMD32 <28> TMS CA3_A FBD_CMD23 FBD_CMD29 <28>
H5 H5
CA4_A H10 FBD_CMD11 FBD_CMD7 <28> CA4_A H10 FBD_CMD27 FBD_CMD23 <28>
CA5_A J12 FBD_CMD15 FBD_CMD11 <28> CA5_A J12 FBD_CMD30 FBD_CMD27 <28>
CA6_A FBD_CMD14 FBD_CMD15 <28> CA6_A FBD_CMD31 FBD_CMD30 <28>
J11 J11
CA7_A J4 FBD_CMD3 FBD_CMD14 <28> CA7_A J4 FBD_CMD19 FBD_CMD31 <28>
CA8_A FBD_CMD1 FBD_CMD3 <28> CA8_A FBD_CMD17 FBD_CMD19 <28>
J3 J3
CA9_A FBD_CMD1 <28> CA9_A FBD_CMD17 <28>
L3 L3
FBD_WCK01 CA0_B FBD_CMD4 <28> FBD_WCK45 CA0_B FBD_CMD16 <28>
D4 M11 D4 M11
<28> FBD_WCK01 FBD_WCK01# D5 WCK_A CA1_B M4 FBD_CMD12 <28> <28> FBD_WCK45 FBD_WCK45# D5 WCK_A CA1_B M4 FBD_CMD25 <28>
<28> FBD_WCK01# FBD_WCK23 WCK#_A CA2_B FBD_CMD5 <28> <28> FBD_WCK45# FBD_WCK67 WCK#_A CA2_B FBD_CMD24 <28>
R11 L12 R11 L12
<28> FBD_WCK23 FBD_WCK23# R10 WCK_B CA3_B L5 FBD_CMD7 FBD_CMD13 <28> <28> FBD_WCK67 FBD_WCK67# R10 WCK_B CA3_B L5 FBD_CMD23 FBD_CMD33 <28>
<28> FBD_WCK23# WCK#_B CA4_B L10 FBD_CMD11 <28> FBD_WCK67# WCK#_B CA4_B L10 FBD_CMD27
CA5_B K12 FBD_CMD15 CA5_B K12 FBD_CMD30
+FBD_VREFC K1 CA9_B +1.35VSDGPU +FBD_VREFC K1 CA9_B +1.35VSDGPU
VREFC VREFC
C1 C1
<28> FBD_CMD2 RESET# VDDQ2 H1 <28> FBD_CMD18 RESET# VDDQ2 H1
VDDQ3 L1 VDDQ3 L1
Checklist 0723 update R1 VSS6
VSS7
VDDQ10
VDDQ11
N4 R1 VSS6
VSS7
VDDQ10
VDDQ11
N4
U1 T4 U1 T4
use GDDR6 internal, PD 1k to GND A2 VSS8
VSS9
VDDQ12
VDDQ13
B5 A2 VSS8
VSS9
VDDQ12
VDDQ13
B5
V2 U5 V2 U5
C3 VSS10 VDDQ14 B10 C3 VSS10 VDDQ14 B10
+1.35VSDGPU D3 VSS11 VDDQ15 U10 D3 VSS11 VDDQ15 U10
F3 VSS12 VDDQ16 C11 F3 VSS12 VDDQ16 C11
1
M3 N11 M3 N11
RG155 N3 VSS15 VDDQ19 T11 N3 VSS15 VDDQ19 T11
@ 549_0402_1% R3 VSS16 VDDQ20 J13 R3 VSS16 VDDQ20 J13
T3 VSS17 VDDQ21 K13 T3 VSS17 VDDQ21 K13
2

1 2 +FBD_VREFC W=16mils H4 VSS20
VSS21
VDDQ24
VDDQ25
H14 H4 VSS20
VSS21
VDDQ24
VDDQ25
H14
L4 L14 L4 L14
RG156 P4 VSS22 VDDQ26 P14 P4 VSS22 VDDQ26 P14
CG256
CG265
1 1
820P_0402_25V7
820P_0402_25V7
2
931_0402_1% V4 VSS23 VDDQ27 T14 V4 VSS23 VDDQ27 T14

1K_0402_5%
C5 VSS24 VDDQ28 C5 VSS24 VDDQ28

RG2872
@ VSS25 VSS25
1
VGA@ @ @ T5 T5
2 2 C10 VSS26 A1 C10 VSS26 A1
Drain
Source
T10 VSS27 VDD1 V1 T10 VSS27 VDD1 V1

Gate

@ E11 VSS29 VDD3 L2 E11 VSS29 VDD3 L2
2
QG8 L11 VSS31 VDD5 P5 L11 VSS31 VDD5 P5

V11 P10 V11 P10
N12 VSS39 N12 VSS39
D14 VSS45 R4 FBD_WCKB23 D14 VSS45 R4 FBD_WCKB67
F14 VSS46 WCK0_t_B,NC R5 FBD_WCKB23# FBD_WCKB23 <28> F14 VSS46 WCK0_t_B,NC R5 FBD_WCKB67# FBD_WCKB67 <28>
VSS47 WCK0_c_B,NC FBD_WCKB23# <28> VSS47 WCK0_c_B,NC FBD_WCKB67# <28>
G14 G14
M14 VSS48 G5 SNN_FBDL_RFU_A_M M14 VSS48 G5 SNN_FBDU_RFU_A
N14 VSS49 RFU_A,NC M5 SNN_FBDL_RFU_B_M N14 VSS49 RFU_A,NC M5 SNN_FBDU_RFU_B
U14 VSS51 D10 FBD_WCKB01# U14 VSS51 D10 FBD_WCKB45#
180-BALL FBD_WCKB01# <28> 180-BALL FBD_WCKB45# <28>
VSS52 SGRAM GDDR6 WCK1_c_A,NC D11 FBD_WCKB01 VSS52 SGRAM GDDR6 WCK1_c_A,NC D11 FBD_WCKB45
WCK1_t_A,NC FBD_WCKB01 <28> WCK1_t_A,NC FBD_WCKB45 <28>
+1.35VSDGPU +1.35VSDGPU +1.35VSDGPU +1.35VSDGPU
Close to DRAM Close to DRAM additional, X5R
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
CG1555
CG1561
CG1563
CG1562
CG1564
CG1565
CG1566
CG1567
CG1569
CG1568
CG1570
CG1571
CG1605
CG1611
CG1613
CG1612
CG1614
CG1615
CG1616
CG1617
CG1619
CG1618
CG1620
CG1621
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
CG1552
CG1551
CG1553
CG2832
CG2831
CG2833
CG1602
CG1601
CG1603
CG2835
CG2834
CG2836
2 2 2 2 2 2 2 2 2 2 2 2
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2 2 2 2 2 2 2 2 2 2 2 2 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ 2 2 2 2 2 2 2 2 2 2 2 2 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
1 1 1 1 1 1 1 1 1 1 1 1
+1.35VSDGPU Right under DRAM +1.35VSDGPU +1.35VSDGPU Right under DRAM +1.35VSDGPU
around DRAM around DRAM
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
CG1572
CG1573
CG1574
CG1575
CG1576
CG1577
CG1579
CG1578
CG1581
CG1580
CG1582
CG1583
CG1622
CG1623
CG1624
CG1625
CG1626
CG1627
CG1629
CG1628
CG1631
CG1630
CG1632
CG1633
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
1
CG1554
CG1556
CG1557
CG1558
CG1559
CG1560
CG1604
CG1606
CG1607
CG1608
CG1609
CG1610
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2
2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A A
+1.35VSDGPU Close to DRAM +1.8VSDGPU_AON +1.35VSDGPU Close to DRAM +1.8VSDGPU_AON
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
0.47U_0201_4VAN
CG1535
CG1534
CG1536
CG1538
CG1537
CG1539
CG1542
CG1540
CG1543
CG1541
CG1544
CG1545
CG1548
CG1546
CG1547
CG1549
CG1585
CG1584
CG1586
CG1588
CG1587
CG1589
CG1592
CG1590
CG1593
CG1591
CG1594
CG1595
CG1598
CG1596
CG1597
CG1599
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CG1550
CG1600
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

N18E-GDDR6_D
5 4 3 2 1
A B C D E F G H
+1.8VALW to +1.8VSDGPU_AON & +3VS to +3VSDGPU <0.2 modify>

DG8
DGPU_PWR_EN 3
<19,25> DGPU_PWR_EN 1 1V8_AON_EN
RG3008
1.35VSDGPU_PG 1 2 1.35VSDGPU_PG_R 2
<25,98> 1.35VSDGPU_PG
1
100K_0402_1% BAV70W_SOT323-3
1
VGA@ NGPK@ RG2771NGPK@
1 CG2839 100K_0402_5% CG2840 1
0.22U_0402_16V7K 1U_0201_6.3V6M +1.8VALW +1.8VSDGPU_AON +1.8VSDGPU_AON
2
VGA@ VGA@ UG27
2
2 1 1 14
2 VIN1 VOUT1 13
VIN1 VOUT1 1
10U_0402_6.3V6M
CG334 VGA@
CG335 220P_0402_50V7K @ CG936
+5VALW 1V8_AON_EN 3 12 1 2 0.1U_0201_10V6K
ON1 CT1 1
+3VS +1.8VSDGPU_AON VGA@
4 11 2
@ VBIAS GND CG336 220P_0402_50V7K
RG3009 1 2 0_0402_5% RB751S40T1G_SOD523-2 3VSDGPU_EN_GC6 5 10 1 2 2
VGA@ DG30 ON2 CT2 VGA@ +3VSDGPU
NGPK@ 1 +3VS
RG3010 1 2 0_0402_5% 1 2 VGA@ CG337 6 9
0.1U_0201_10V6K 7 VIN2 VOUT2 8 +3VSDGPU
VIN2 VOUT2
10U_0402_6.3V6M
UG19
2
CG338 VGA@
RG2778 15 1
VCC
DGPU_PWR_EN GPAD
1U_0201_6.3V6M
CG339 VGA@
1 24.9K_0402_1% 1
IN B 4 3VSDGPU_EN_3V3 1 2 3VSDGPU_EN_R_3V3 EM5209VF_DFN14_2X3
OUT Y 1
1.8VSDGPU_MAIN_EN3V3 2 GND NGPK@ @ CG935
IN A VGA@ 2
1 0.1U_0201_10V6K
CG315 NGPK@ 2
NL17SZ08DFT2G_SC70-5 0.1U_0201_10V6K 2
3
NGPK@
2
DG26
GC6_FB_EN3V3 3
<19,25> GC6_FB_EN3V3 1 3VSDGPU_EN_GC6
3VSDGPU_EN_R_3V3 2 3VSDGPU_EN_GC6 <39>
BAV70W_SOT323-3
2 2
NGPK@
+1.8VALW to +1.8VSDGPU_MAIN +1.8VALW +1.8VSDGPU_MAIN
1.8VSDGPU_MAIN_EN3V3
<25> 1.8VSDGPU_MAIN_EN3V3 UG20
1 6
NFGC6@ 2 IN OUT
IN
1
VGA@ CG314 3 7 1 1
+5VALW VBIASVCC_PAD +1.8VALW
10U_0402_6.3V6M
CG945
0.1U_0201_10V6K
CG317
1 2 22U_0603_6.3V6M 1.8VSDGPU_MAIN_EN3V3_FGC6 4 5
RG2995 0_0201_5% ON GND
2
AOZ1334DI-02_DFN8-7_3X3
DG27 2 2
1 VGA@
1.8VSDGPU_MAIN_EN1 @ 2 1.8VSDGPU_MAIN_EN3V3 3 VGA@ CG319
<25> 1.8VSDGPU_MAIN_EN SA000070V00
VGA@
VGA@
RG200 0_0201_5% 1 1.8VSDGPU_MAIN_EN3V3_FGC6 0.1U_0201_10V6K
GPU_FB_EN_FGC6_AND_3V3 2
<25> GPU_FB_EN_FGC6_AND_3V3 2
BAV70W_SOT323-3
FGC6@
3
For Power down sequence +3VSD_GPU discharge if need 3
+NVVDD1
+3VSDGPU
1
+1.0VSDGPU +5VS
RG194 VGA@
+5VS 1_0603_5%
2
1
+5VS
2
RG192 RG2847 VGA@
2
1_0603_5% VGA@ RG2779 1_0603_5%
2
100K_0402_5%
2
RG193 VGA@ VGA@ QG20B
1
2
100K_0402_5% PJT138KA_SOT363-6 VGA@ RG2846
1
VGA@
6
100K_0402_5%
+1.35VSDGPU NVVDD1_EN# 2 G
D
VGA@ QG540B
1
S PJT138KA_SOT363-6
6
1VSDGPU_EN#2
D
G QG18B VGA@ VGA@ QG20A
1
2
3VSDGPU_EN_GC6#
2
D
S PJT138KA_SOT363-6 PJT138KA_SOT363-6 G
3
+5VS R40 VGA@ S
1
NVVDD1_EN 5
D
20_0402_5%
G
VGA@ QG540A
1
<25,93> NVVDD1_EN
VGA@ QG18A S PJT138KA_SOT363-6
3
PJT138KA_SOT363-6 +1.8V/+3.3V level
1
4
3
3VSDGPU_EN_GC6 5
D
G
1VSDGPU_EN
D
5 G
RG195 VGA@ S
<25,99> 1VSDGPU_EN S 100K_0402_5% +1.8V/+3.3V level
4
+1.8V/+3.3V level
4
QG19B VGA@
1
D 2N7002KDW_SOT363-6
1.35VSDGPU_EN# 5
4 G 4
S
4
VGA@ QG19A
6
2N7002KDW_SOT363-6 D
1.35VSDGPU_EN 2
<25,98> 1.35VSDGPU_EN G
+3.3V level S
1
N18E-GPU Power control
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
A B C D E F G H
A B C D E
SM01000EJ00 3000ma
LCD POWER CIRCUIT +3VS
220ohm@100mhz
DCR 0.04 Place closed to
1U_0201_6.3V6M
CX2
1
+LCDVDD +19VB +INVPW R_B+ JEDP1 +LCDVDD
UX1 +3VS
5 1
W=60mils
2 IN OUT W=60mils LX1 EMC@
W=60mils
0.1U_0201_10V6K
0.1U_0201_10V6K
@ 2 1 1 HCB2012KF-221T30_0805 CX7 1 1 1
GND 1 2 @
DGPU_ENVDD 1 RX521 2 DGPU_ENVDD_R 4 3 CX3 CX4 1 CX8 CX1
<25> DGPU_ENVDD EN OC 10U_0402_6.3V6M 0.1U_0201_10V6K 1 CX6 10U_0402_6.3V6M
0_0402_5% SY6288C20AAC_SOT23-5 2 2 CX5 1000P_0402_50V7K 2 2 2
1 @ 1
1
68P_0402_50V8J EMC@
RX1 XEMC@ 2
2
100K_0402_5%
@
2
10k PD on GPU side
<25,41> DGPU_EDP_HPD
DGPU_EDP_HPD RX517 1 @ 2 0_0402_5% EDP_HPD_R Camera Raptor
1
+LCDVDD
EDP_HPD_R
RX518 PD at VGA side <14> USB20_N5
USB20_N5 RX8 1 @ 2 0_0402_5% USB20_N5_CAMERA
DGPU_INV_PW M
@ 100K_0402_5% 1 2
<16> EDP_HPD_R USB20_P5 RX9 1 @ 2 0_0402_5% USB20_P5_CAMERA RA92 2.2K_0402_5%
<14> USB20_P5
2
<G-Sensor> Gsensor use ISH path for PVT
+3VS Raptor
RH257 2 1 2.2K_0402_5% G_SCL_R
RH258 2 1 2.2K_0402_5% G_SDA_R JEDP1
USB Touch Screen +INVPW R_B+
W=60mils
ISHGSEN@ 1
ISHGSEN@ +TS_PW R 2 GND
ISH_I2C0_SCL RH244 1 2 0_0402_5% G_SCL +5VS +3VS 3 BATT_WHITE_LED
<19> ISH_I2C0_SCL ISH_I2C0_SDA G_SDA BATT_YELLOW_LED
2
<19> ISH_I2C0_SDA RH245 1 2 0_0402_5% RX6 1 @ 2 0_0603_5% 4 2
5 BREATH_WHITE_LED
EC_SMB_CK2 G_SCL <25> G-SYNC# EDP_BKL_PW M VR_SRC
RH269 1 2 0_0402_5% RX519 1 2 0_0603_5% 6
<18,25,58,66,73> EC_SMB_CK2 EC_SMB_DA2 G_SDA BKOFF_R# VR_SRC
<18,25,58,66,73> EC_SMB_DA2 RH268 1 2 0_0402_5% 7
+LCDVDD EDP_HPD_R 8 VR_SRC
ECGSEN@ 9 NC
+3VS ECGSEN@ 10 DISP_ON/OFF#
11 PWM
eDP RD SUB, Camera DMIC_DATA_R
12 CONNTST_GND
VR_GND
13
<56> DMIC_DATA_R VR_GND
5
+3VS_PANEL EDP_AUXN_C 14
G
QH8B +3VS +3V_eDPRD EDP_AUXP_C 15 VR_GND

2N7002KDW _SOT363-6 RX522 1 @ 2 0_0603_5% 16 LCD_B_CLK+
EDP_TXP0 CX41 1 2 .1U_0402_16V7K EDP_TXP0_C 17 LCD_B_CLK-
G_SCL G_SCL_R <41> EDP_TXP0 EDP_TXN0 EDP_TXN0_C GND
3 4 RX523 1 2 0_0603_5% CX42 1 2 .1U_0402_16V7K 18
S
G_SCL_R <66> <41> EDP_TXN0 LVDS_B2+

19
D
EDP_TXP1 CX43 1 2 .1U_0402_16V7K EDP_TXP1_C 20 LVDS_B2-

<41> EDP_TXP1 EDP_TXN1 EDP_TXN1_C LVDS_B1+
RH265 1 @ 2 0_0402_5% CX44 1 2 .1U_0402_16V7K 21
<41> EDP_TXN1 LVDS_B1-
22
EDP_TXP2 CX45 1 2 .1U_0402_16V7K EDP_TXP2_C 23 LVDS_B0+
<41> EDP_TXP2 LVDS_B0-
2
EDP_TXN2 CX46 1 2 .1U_0402_16V7K EDP_TXN2_C 24

G
<41> EDP_TXN2 GND

QH8A 25
2N7002KDW _SOT363-6 EDP_TXP3 CX47 1 2 .1U_0402_16V7K EDP_TXP3_C 26 LVDS_A_CLK+
<41> EDP_TXP3 EDP_TXN3 EDP_TXN3_C LVDS_A_CLK-
CX48 1 2 .1U_0402_16V7K 27
G_SDA G_SDA_R <41> EDP_TXN3 GND
6 1 G_SDA_R <66> 28
S
USB20_P6 29 LVDS_A2+
D
For <14> USB20_P6 LVDS_A2-

USB20_N6 30
TS <14> USB20_N6 LVDS_A1+
RH266 1 @ 2 0_0402_5% G_SCL_R 31
G_SDA_R 32 LVDS_A1-
3 33 LVDS_A0+ 3
For +TS_PW R LVDS_A0-
Gsensor +3VS_PANEL 34
35 EDID_DATA
From GPU +3VS_PANEL EDID_CLK
For +3VS_PANEL 36
USB20_N5_CAMERA 37 BIST 44
Camera V_EDID MGND4
GPU_EDP_AUXN CX50 1 2 .1U_0402_16V7K EDP_AUXN_C RX524 1 @ 2 0_0201_5% USB20_P5_CAMERA 38 43
<27> GPU_EDP_AUXN RD_EDP_AUXN_C <41> LCD_VDD MGND3
GPU_EDP_AUXP CX49 1 2 .1U_0402_16V7K EDP_AUXP_C RX525 1 @ 2 0_0201_5% TS_EN 39 42
<27> GPU_EDP_AUXP RD_EDP_AUXP_C <41> <19,58> TS_EN LCD_VDD MGND2
DMIC_CLK_R 40 41
From GPU to Panel to TUSB546 (reserve) <56> DMIC_CLK_R CONNTST MGND1
STARC_115B40-000000-G4-R
DGPU_INV_PW M RH249 1 @ 2 0_0402_5% EDP_BKL_PW M CONN@
<25> DGPU_INV_PWM
SP01001BS00
0809, NV suggest to use dGPU directly control,default use EC To EC DMIC_CLK_R
DGPU_ENBKL RH250 1 2 0_0402_5% ENBKL DMIC_DATA_R

<25> DGPU_ENBKL ENBKL <58>
FOR VGA OUTPUT
2
RH260 1 @ 2 0_0402_5% +3VS
DX1
YSLC05CH_SOT23-3
From EC RG196 1 2 100K_0201_5% EDP_AUXN_C XEMC@
XEMC@ RG197 1 2 100K_0201_5% EDP_AUXP_C
RH259 1 2 0_0402_5% BKOFF_R# CX10 1 2 220P_0402_50V7K
<58> BKOFF#
1
4 4
RX5 1 @ 2 10K_0402_5%
Conn
EDP_BKL_PW M
1
XEMC@ RX516 2017/11/23 2018/09/01 Title

EDP_BKL_PW M CX9 1 2 220P_0402_50V7K
10K_0402_5%
eDP CONN.
2
A B C D E
A B C D E
Raptor:check pin13
to GPU
+1.8VSDGPU_AON
to PCH +3VS +3VS

Display Port
1
JDP1
2
1 RX7 1
10K_0402_5% DP0_HPD 18
HOT PLUG DP_PWR
20 W=40mils +3VS_DP
RY26 19
Return
2
1M_0402_5% DP0_AUXP_C_SW 15 16
G
2
QY3A DP0_AUXN_C_SW 17 AUX_CH_P GND 14
<25> GPU_DP0_HPD#
1
2N7002KDW _SOT363-6 AUX_CH_N GND 13 DP_CA_DET
QY3B GND
2
CV38 2 1 .1U_0402_16V7K DP0_TXP3_C 10 11
<26> DP0_TXP3 LANE3_P GND
3
D 2N7002KDW _SOT363-6 1 6 DP0_HPD CV39 2 1 .1U_0402_16V7K DP0_TXN3_C 12 8
S
<16> DP0_HPD_PCH <26> DP0_TXN3 LANE3_N GND
D
5 DP0_HPD 5
RV907
1M_0402_5%
G CV40 2 1 .1U_0402_16V7K DP0_TXP2_C 7 GND 2
<26> DP0_TXP2 LANE2_P GND
2
CV37 2 1 .1U_0402_16V7K DP0_TXN2_C 9
<26> DP0_TXN2
1
S R396 RY25 @ LANE2_N 21
4
CV42 2 1 .1U_0402_16V7K DP0_TXP1_C 4 GND1 22

100K_0402_5% 100K_0402_5% <26> DP0_TXP1 LANE1_P GND2
CV41 2 1 .1U_0402_16V7K DP0_TXN1_C 6 23
<26> DP0_TXN1 LANE1_N GND3 24
1
CV44 2 1 .1U_0402_16V7K DP0_TXP0_C 1 GND4
<26> DP0_TXP0 DP0_TXN0_C LANE0_P
CV43 2 1 .1U_0402_16V7K 3
<26> DP0_TXN0 LANE0_N
TAIW I_DP008-207CRL-TW
CONN@
DC06000DJ00
2 2
DP++ and isolated circuit

+3VSDGPU
+5VS
CV339
1 2
100K_0402_5%
100K_0402_5%
100K_0402_5%
+5VS
1
0.1U_0201_10V6K
1
RV320
RV318
RV319
+5VS R4080
10K_0402_5%
1
2
R4081
2
10K_0402_5% DP_AUX_PROT UV42

16
Vcc 4 DP0_AUXP_C_SW
2
DP0_AUXP_PROT CV337 1 2 0.1U_0201_10V6K DP0_AUXP_C 2 1A 7 DP0_AUXN_C_SW

0.2 1B1 2A
1
C 3 9
2 Q46 DP0_AUXN_PROT CV338 1 2 0.1U_0201_10V6K DP0_AUXN_C 5 1B2 3A 12
2B1 4A
100K_0402_5%
B MMBT3904_SOT23-3 6
2B2
1
E 11 15
3
3B1 OE
RV322
10 1 DP_CA_DET
R521 3B2 S
1
3 C 14 3
1 2 2 Q45 13 4B1 8
<37> 3VSDGPU_EN_GC6 B MMBT3904_SOT23-3 4B2 GND 17
0:DP
1:HDMI
2
E T-PAD
3
10K_0402_5% SN74CBT3257CRGYR_QFN16_4X3P5
QY4A
2N7002KDW _SOT363-6 W=40mils W=40mils INPUT/OUTPUT
OE# S A Function
DP0_AUXP 1 6 DP0_AUXP_PROT +3VALW +3VS_DP
D
<26> DP0_AUXP
S
CV56
.1U_0402_16V7K UV3
2 1 5 1 L L B1 A=B1
IN OUT
G
2
L H B2 A=B2
.1U_0402_16V7K
1
2
GND
CV27
SUSP# 4 3
<41,43,58,68,78,83,85,88> SUSP# EN OC
DP_AUX_PROT
1
SY6288C20AAC_SOT23-5 2 H X Z NC
C2776
0.01U_0402_16V7K
2
5
G
4 4
0921 change souce to +3VALW, CTRL to SUSP#
DP0_AUXN 4 3 DP0_AUXN_PROT
S
<26> DP0_AUXN
D
QY4B Security Classification Compal Secret Data Compal Electronics, Inc.

2N7002KDW _SOT363-6 2017/11/23 2017/12/31 Title
DP CONN
A B C D E
A B C D E
Raptor
CY22 1 2 .1U_0402_16V7K HDMI_CLKP HDMI_CLKN RY27 1 2 499_0402_1% HDMI_GND

<27> GPU_DP2_P3 HDMI_CLKN HDMI_CLKP
CY24 1 2 .1U_0402_16V7K RY28 1 2 499_0402_1%
<27> GPU_DP2_N3 HDMI_TX_N0 RY29 1 2 499_0402_1%
CY16 1 2 .1U_0402_16V7K HDMI_TX_P0 HDMI_TX_P0 RY30 1 2 499_0402_1%
<27> GPU_DP2_P2 HDMI_TX_N0
1 CY17 1 2 .1U_0402_16V7K W=40mils 1
<27> GPU_DP2_N2 +5VS +HDMI_5V_OUT
CY18 1 2 .1U_0402_16V7K HDMI_TX_P1
<27> GPU_DP2_P1 HDMI_TX_N1
CY19 1 2 .1U_0402_16V7K
<27> GPU_DP2_N1 HDMI_TX_N1 UY2
RY31 1 2 499_0402_1%
CY20 1 2 .1U_0402_16V7K HDMI_TX_P2 HDMI_TX_P1 RY32 1 2 499_0402_1%
<27> GPU_DP2_P0 HDMI_TX_N2 HDMI_TX_N2
CY21 1 2 .1U_0402_16V7K RY33 1 2 499_0402_1% 3
<27> GPU_DP2_N0 HDMI_TX_P2 OUT
RY34 1 2 499_0402_1% 1
1
IN CY23
HDMI_CLKP RY15 1 2 6.04_0402_1% HDMI_R_CLKP 2 0.1U_0201_10V6K
GND 2
2
3
XEMC@ CY26 D AP2330W -7_SC59-3
3.3P_0402_50V8 +1.8VSDGPU_AON 5 QY2B
+3VS
G 2N7002KDW _SOT363-6
1
4
HDMI_CLKN RY14 1 2 6.04_0402_1% HDMI_R_CLKN
5
QY1A
PJT138KA_SOT363-6
G
4 3 HDMI_CTRL_CLK
HDMI_TX_P0 HDMI_R_TX_P0 <27> GPU_DP2_CTRL_CLK
D
RY16 1 2 6.04_0402_1%
HDMI_TX_N0 RY17 1 2 6.04_0402_1% HDMI_R_TX_N0

Raptor, follow eagle and 1060 MP 2.2K
2
QY1B
PJT138KA_SOT363-6
G
1 6 HDMI_CTRL_DAT
<27> GPU_DP2_CTRL_DAT
D
2 2
HDMI_TX_P1 RY18 1 2 6.04_0402_1% HDMI_R_TX_P1
3ohm/10pF +HDMI_5V_OUT
HDMI_TX_N1 RY19 1 2 6.04_0402_1% HDMI_R_TX_N1
HDMI_CTRL_DAT RH238 2 1 3.3K_0402_5%
HDMI_CTRL_CLK RH239 2 1 3.3K_0402_5%
DY2 EMC@
HDMI_R_CLKP 1 9 HDMI_R_CLKP +1.8VSDGPU_AON
HDMI_R_CLKN 2 8 HDMI_R_CLKN GPU_DP2_CTRL_CLK RH240 2 1 2.2K_0402_5%

GPU_DP2_CTRL_DAT RH241 2 1 2.2K_0402_5%
HDMI_TX_P2 RY20 1 2 6.04_0402_1% HDMI_R_TX_P2 HDMI_R_TX_N04 7 HDMI_R_TX_N0
HDMI_TX_N2 RY22 1 2 6.04_0402_1% HDMI_R_TX_N2 HDMI_R_TX_P05 6 HDMI_R_TX_P0
TVW DF1004AD0_DFN9
+1.8VSDGPU_AON SC300003Z00
to GPU +HDMI_5V_OUT HDMI connector
1
DY3 EMC@ JHDMI1

RY24 HDMI_R_TX_N11 9 HDMI_R_TX_N1 HDMI_HPD 19
VGA@ 18 HP_DET
10K_0402_5% +5V
HDMI_R_TX_P12 8 HDMI_R_TX_P1 17
HDMI_CTRL_DAT 16 DDC/CEC_GND
2
3 HDMI_R_TX_P24 7 HDMI_R_TX_P2 HDMI_CTRL_CLK 15 SDA 3

HDMI_HPD_GPU# 14 SCL
<25> HDMI_HPD_GPU# HDMI_R_TX_N25 HDMI_R_TX_N2 Reserved
6 13
HDMI_R_CLKN 12 CEC
CK-
1
D 11 23
QY5 2 HDMI_HPD HDMI_R_CLKP 10 CK_shield GND 22
L2N7002LT1G_SOT23-3 G 3 HDMI_R_TX_N0 9 CK+ GND 21
8 D0- GND 20
S
3
D0_shield GND
1
TVW DF1004AD0_DFN9 HDMI_R_TX_P0 7

VGA@ RG2967 HDMI_R_TX_N1 6 D0+
SC300003Z00 5 D1-
100K_0402_5%
change PN follow USB3 HDMI_R_TX_P1 4 D1_shield
HDMI_R_TX_N2 3 D1+
2
DY1 2 D2-
HDMI_HPD 6 3 HDMI_CTRL_DAT HDMI_R_TX_P2 1 D2_shield
I/O4 I/O2 D2+
ACON_HMR2D-AK120C
CONN@
5 2 DC232000R00
VDD GND
to PCH +3VS +3VS
HDMI_CTRL_CLK 4 1 ZZZ2
I/O3 I/O1 +HDMI_5V_OUT
2
AZC099-04S.R7G_SOT23-6
RY35 EMC@
2
1M_0402_5%
G
P/N: SC300002900, S DIO(BR) AZC199-04S.R7G SOT23-6 ESD

1
4
HDMI_ROYALTY 4
ROYALTY HDMI W /LOGO+HDCP
1 6 HDMI_HPD RO0000003HM
S
<16> HDMI_HPD_PCH
D
45@
QY2A
2
2N7002KDW _SOT363-6 RY11 @

100K_0402_5%
HDMI CONN.
1
A B C D E
A B C D E
+3VS +3V_eDPRD
1012 check Ti if need +3V_eDPRD
LV1
1 2 +3V_eDPRD CTL1_HPDIN RV908 1 2 1K_0402_5%
@
PBY160808T-600Y-N_2P I2C_EN RV909 1 2 1K_0402_5% @
0.2 RV910 1 2 1K_0402_5%
1B RV911 1 2 1K_0402_5%
+3V_eDPRD
I2C Programming or pin strap programming select. @
1
Rerserve for 3V power supply CTL0_EDPRD_SDA RV912 1 2 1K_0402_5% 1
I2C is only disable when this pin is '0'
+5VALW 0 : Pin Strap(I2C disable)(Default)
R : TI test mode(I2C enable at 3.3V) RV913 1 2 1K_0402_5%
F : I2C enabled at 1.8V
1
+3V_eDPRD 1 : I2C enabled at 3.3V
UV46 +3V_eDPRD
2.2U_0402_6.3V6M
CV968
1 5
0.2 @
VIN VOUT FLIP_EDPRD_CLK RV914 1 2 1K_0402_5%
2 2
1U_0201_6.3V6M
GND 1
CV969
3 4 RV915 1 2 1K_0402_5%
EN NC
G9091-330TA1U_SC70-5 2
@
RV928 1 2 0_0402_5% +3VSEDPRD_ON
8,83,85,88> SUSP# 1B +3V_eDPRD
@
1 DPEQ0_A1_EDPRD RV916 1 2 1K_0402_5%
1B @
CV970 @
0.1U_0201_10V6K RV917 1 2 1K_0402_5%
2
+3V_eDPRD
@
2 DPEQ1_EDPRD RV918 1 2 1K_0402_5% 2
RV920 1 2 1K_0402_5%
+3V_eDPRD DPEQ0,DPEQ1 : DP Receiver equalization gain

F,F(Default)
When I2C_EN is not '0' DPEQ0 sets I2C adress
10U_0402_6.3V6M
1U_0201_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1 1 1 1 1
CV955 CV956 CV957 CH75 CV958 CV959
+3V_eDPRD
@
2 2 2 2 2 2
A0_EDPRD RV919 1 2 1K_0402_5%
@
RV921 1 2 1K_0402_5%
UV43
1 35 TP1 TP@
6 VCC EQ1 38
VCC EQ0 TP2 TP@
20 SSEQ0,SSEQ1 : USB receiver equalizer gain
28 VCC 17 I2C_EN
VCC I2C_EN for upstream facing SSTXP/N
2 DPEQ1_EDPRD F,F(Default)
GPU_EDP_TXP0 CV960 1 GPU_EDP_TXP0_C DPEQ1 DPEQ0_A1_EDPRD
<27> GPU_EDP_TXP0
2 .1U_0402_16V7K 9
DP0p DPEQ0/A1
14 When I2C_EN is not '0' SSEQ0 sets I2C adress
GPU_EDP_TXN0 CV961 1 2 .1U_0402_16V7K GPU_EDP_TXN0_C 10
3 <27> GPU_EDP_TXN0 DP0n 3
3 TP3 TP@
GPU_EDP_TXP1 CV962 1 2 .1U_0402_16V7K GPU_EDP_TXP1_C 12 SSEQ1 11 A0_EDPRD
<27> GPU_EDP_TXP1 GPU_EDP_TXN1 CV963 1 GPU_EDP_TXN1_C DP1p SSEQ0/A0
2 .1U_0402_16V7K 13
<27> GPU_EDP_TXN1 DP1n
GPU_EDP_TXP2 CV964 1 2 .1U_0402_16V7K GPU_EDP_TXP2_C 15 21 FLIP_EDPRD_CLK
<27> GPU_EDP_TXP2 GPU_EDP_TXN2 CV965 1 GPU_EDP_TXN2_C DP2p FLIP/SCL
2 .1U_0402_16V7K 16
<27> GPU_EDP_TXN2 DP2n CTL0_EDPRD_SDA
22
GPU_EDP_TXP3 CV966 1 2 .1U_0402_16V7K GPU_EDP_TXP3_C 18 CTL0/SDA
<27> GPU_EDP_TXP3 GPU_EDP_TXN3 CV967 1 GPU_EDP_TXN3_C DP3p CTL1_HPDIN
2 .1U_0402_16V7K 19 23
<27> GPU_EDP_TXN3 DP3n CTL1
+3V_eDPRD
EDP_TXN3 31 34 EDP_TXN2
<38> EDP_TXN3 RX1n TX1n EDP_TXN2 <38>
EDP_TXP3 30 33 EDP_TXP2
<38> EDP_TXP3 RX1p TX1p EDP_TXP2 <38>
1
EDP_TXN0 39 37 EDP_TXP1 RV925
<38> EDP_TXN0 RX2n TX2p EDP_TXP1 <38>
EDP_TXP0 40 36 EDP_TXN1 100K_0402_5%
<38> EDP_TXP0 RX2p TX2n EDP_TXN1 <38>
2
+3V_eDPRD 8 5
SSTXp SSRXp RD_EDP_AUXN_C @
RV922 1 2 4.7K_0402_5% 7 4
SSTXn SSRXn RD_EDP_AUXP_C
@
1
RV923 1 2 4.7K_0402_5% 29 27 TP4 TP@
32 RESVD1 SBU1 26 RV926
RESVD2 SBU2 TP5 TP@
100K_0402_5%
RV924 24 RD_EDP_AUXP_C
DGPU_EDP_HPD DGPU_EDP_RD_HPD AUXp RD_EDP_AUXN_C RD_EDP_AUXP_C <38>
1 @ 2 41 25
<25,38> DGPU_EDP_HPD RD_EDP_AUXN_C <38>
2
PAD AUXn
@
4
0_0402_5% 4
TUSB546_QFN40_4X6
1
RV927
@ 100K_0402_5%
2

eDP redriver(TUSB546)
A B C D E
A B C D E
+3V_TYPEC_DP
TBT@
+3V_TYPEC_DP CTL1_TBT_HPDIN RT843 1 2 1K_0402_5%
@
I2C_EN_TBT RT844 1 2 1K_0402_5% @
1012 check Ti if need RT845 1 2 1K_0402_5%
+3VS +3V_TYPEC_DP
RT846 1 2 1K_0402_5%
LT39
1 2 TBT@ +3V_TYPEC_DP
I2C Programming or pin strap programming select. @
1 PBY160808T-600Y-N_2P CTL0_TBT_SDA RT900 1 2 1K_0402_5% 1
I2C is only disable when this pin is '0'
TBT@
0 : Pin Strap(I2C disable)(Default)
R : TI test mode(I2C enable at 3.3V) RT847 1 2 1K_0402_5%
F : I2C enabled at 1.8V
TBT@
1 : I2C enabled at 3.3V
+3V_TYPEC_DP
@
FLIP_TBT_CLK RT848 1 2 1K_0402_5%
TBT@
RT849 1 2 1K_0402_5%
+3V_TYPEC_DP
TBT@
+3V_TYPEC_DP DPEQ0_A1_TBT RT850 1 2 1K_0402_5%
@
RT851 1 2 1K_0402_5%
10U_0402_6.3V6M
1U_0201_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1 1 1 1 1
CT305 CT306 CT307 CH74 CT308 CT309
+3V_TYPEC_DP
TBT@ @ @
2 2 2 2 2 2 2 DPEQ1_TBT RT852 1 2 1K_0402_5% 2
TBT@
RT853 1 2 1K_0402_5%
TBT@ TBT@ TBT@ TBT@
UT11 DPEQ0,DPEQ1 : DP Receiver equalization gain
1 35 F,F(Default)
VCC EQ1 TH41 TP@
6 38 TH40 TP@
When I2C_EN is not '0' DPEQ0 sets I2C adress
20 VCC EQ0
28 VCC 17 I2C_EN_TBT
VCC I2C_EN
2 DPEQ1_TBT +3V_TYPEC_DP
CT310 1 2 0.1U_0201_10V6K DP4_TXP0_C 9 DPEQ1 14 DPEQ0_A1_TBT
<26> DP4_TXP0 DP0p DPEQ0/A1
CT311 1 2 0.1U_0201_10V6K DP4_TXN0_C 10 TBT@
<26> DP4_TXN0 DP0n A0_TBT
TBT@ 3 TH42 TP@ RT854 1 2 1K_0402_5%
CT312 1 2 0.1U_0201_10V6K DP4_TXP1_C 12 SSEQ1 11 A0_TBT
<26> DP4_TXP1 TBT@
CT313 1 2 0.1U_0201_10V6K DP4_TXN1_C 13 DP1p SSEQ0/A0 @
<26> DP4_TXN1 DP1n
TBT@ RT855 1 2 1K_0402_5%
CT314 1 2
TBT@ 0.1U_0201_10V6K DP4_TXP2_C 15 21 FLIP_TBT_CLK
<26> DP4_TXP2 DP2p FLIP/SCL
CT315 1 2 0.1U_0201_10V6K DP4_TXN2_C 16
<26> DP4_TXN2 DP2n CTL0_TBT_SDA
TBT@ 22
CT316 1 2 0.1U_0201_10V6K DP4_TXP3_C 18 CTL0/SDA
<26> DP4_TXP3 TBT@
CT317 1 2 0.1U_0201_10V6K DP4_TXN3_C 19 DP3p 23 CTL1_TBT_HPDIN
<26> DP4_TXN3 DP3n CTL1 SSEQ0,SSEQ1 : USB receiver equalizer gain
TBT@ for upstream facing SSTXP/N
TBT@
TBT_DP4_N3 31 34 TBT_DP4_N2 F,F(Default)
<43> TBT_DP4_N3 TBT_DP4_P3 RX1n TX1n TBT_DP4_P2 TBT_DP4_N2 <43>
<43> TBT_DP4_P3
30
RX1p TX1p
33
TBT_DP4_P2 <43> When I2C_EN is not '0' SSEQ0 sets I2C adress
3 TBT_DP4_N0 39 37 TBT_DP4_P1 3
<43> TBT_DP4_N0 TBT_DP4_P0 RX2n TX2p TBT_DP4_N1 TBT_DP4_P1 <43>
40 36
<43> TBT_DP4_P0 RX2p TX2n TBT_DP4_N1 <43>
TBT@ 8 5
RT856 1 2 4.7K_0402_5% 7 SSTXp SSRXp 4
+3V_TYPEC_DP SSTXn SSRXn
@
RT857 1 2 4.7K_0402_5% 29 27 TH43 TP@
32 RESVD1 SBU1 26
RESVD2 SBU2 TH44 TP@
+3V_TYPEC_DP
24 RD_DP4_AUXP_C 0.1U_0201_10V6K 2 1 CT318 DP4_AUXP
TBT_DP4_HPD RT858 TBT_DP4_HPD_R AUXp RD_DP4_AUXN_C DP4_AUXN DP4_AUXP <26,43>
1 @ 2 0_0402_5% 41 25 0.1U_0201_10V6K 2 1 CT319
<16,43> TBT_DP4_HPD PAD AUXn DP4_AUXN <26,43>
1
TBT@
TBT@ RT859
TUSB546_QFN40_4X6
100K_0402_5%
TBT@
2
RD_DP4_AUXN_C TBT@
RD_DP4_AUXP_C
1
RT860
100K_0402_5%
2
TBT@
4 4

TBT DP redriver
A B C D E
5 4 3 2 1
+3.3V_TBT_SX
1
+3VS
R265
TBT@ 10K_0402_5%
2
G
2
3 1 PCIE_TBT_CLKREQ#
<15> TBT_CLKREQ#
D
PU at PCH side.
Q34 Raptor: CAP change to 0201 Raptor: CAP change to 0201
L2N7002WT1G_SC-70-3 U36A
SB00001GE00 PCIE_PTX_DRX_P17 PCIE_PTX_C_DRX_P17 PCIE_PRX_C_DTX_P17 0.22U_0201_6.3V6K 2 PCIE_PRX_DTX_P17
C844 TBT@ 1 2 0.22U_0201_6.3V6K Y23 V23 1 TBT@ C271
<17> PCIE_PTX_DRX_P17 PCIE_PTX_DRX_N17 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_N17 Y22 PCIE_RX0_P PCIE_TX0_P V22 PCIE_PRX_C_DTX_N17 0.22U_0201_6.3V6K 2 1 TBT@ C272 PCIE_PRX_DTX_N17 PCIE_PRX_DTX_P17 <17>
C845 TBT@
<17> PCIE_PTX_DRX_N17 PCIE_RX0_N PCIE_TX0_N PCIE_PRX_DTX_N17 <17>
PCIE_PTX_DRX_P18 C846 TBT@ 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_P18 T23 P23 PCIE_PRX_C_DTX_P18 0.22U_0201_6.3V6K 2 1 TBT@ C273 PCIE_PRX_DTX_P18
+3.3V_LC <17> PCIE_PTX_DRX_P18 PCIE_PTX_DRX_N18 PCIE_PTX_C_DRX_N18 PCIE_RX1_P PCIE_TX1_P PCIE_PRX_C_DTX_N18 0.22U_0201_6.3V6K 2 PCIE_PRX_DTX_N18 PCIE_PRX_DTX_P18 <17>
D C847 TBT@ 1 2 0.22U_0201_6.3V6K T22 P22 1 TBT@ C274 D
PCIe GEN3
PCIE X4 Bus PCIE_PTX_DRX_P19 PCIE_PTX_C_DRX_P19 PCIE_PRX_C_DTX_P19 0.22U_0201_6.3V6K 2 PCIE_PRX_DTX_P19
(Link to PCH Port 21~24) C848 TBT@ 1 2 0.22U_0201_6.3V6K M23 K23 1 TBT@ C397
<17> PCIE_PTX_DRX_P19 PCIE_PTX_DRX_N19 PCIE_PTX_C_DRX_N19 PCIE_RX2_P PCIE_TX2_P PCIE_PRX_C_DTX_N19 0.22U_0201_6.3V6K 2 PCIE_PRX_DTX_N19 PCIE_PRX_DTX_P19 <17>
C849 TBT@ 1 2 0.22U_0201_6.3V6K M22 K22 1 TBT@ C398
R268 R269 R270 R271 PCIE_PTX_DRX_P20 C850 TBT@ 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_P20 H23 F23 PCIE_PRX_C_DTX_P20 0.22U_0201_6.3V6K 2 1 TBT@ C399 PCIE_PRX_DTX_P20
<17> PCIE_PTX_DRX_P20 PCIE_RX3_P PCIE_TX3_P PCIE_PRX_DTX_P20 <17>
1
PCIE_PTX_DRX_N20 C851 TBT@ 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_N20 H22 F22 PCIE_PRX_C_DTX_N20 0.22U_0201_6.3V6K 2 1 TBT@ C400 PCIE_PRX_DTX_N20
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

TBT@ TBT@ TBT@ TBT@ PCIE CLK V19 L4 TBT_RST#_R R264 2 @ 1 0_0402_5%
<15> CLK_PCIE_TBT PCIE_REFCLK_100_IN_P PERST_N PLT_RST_BUF# <16,25,49,51,52,68>
(From PCH CLKOUT6) T19
<15> CLK_PCIE_TBT# PCIE_TBT_CLKREQ# PCIE_REFCLK_100_IN_N PCIE_RBIAS
AC5 N16 R266 1 TBT@ 2 3.01K_0402_1%
2
PCIE_CLKREQ_N PCIE_RBIAS
TBT_TDI DDC:3.3V C275 TBT@ 1 2 0.1U_0402_16V7K TBT_DP4_P0_C AB7 R2
<42> TBT_DP4_P0 DPSNK0_ML0_P DPSRC_ML0_P
TBT_TMS PU @ SOC side <42> TBT_DP4_N0 C277 TBT@ 1 2 0.1U_0402_16V7K TBT_DP4_N0_C AC7
DPSNK0_ML0_N DPSRC_ML0_N
R1 POC_GPIO_0 interrupt from port power switch
TBT_TCK
TBT_TDO C279 TBT@ 1 2 0.1U_0402_16V7K TBT_DP4_P1_C AB9 N2
<42> TBT_DP4_P1
C281 TBT@ 1 2 0.1U_0402_16V7K TBT_DP4_N1_C AC9 DPSNK0_ML1_P DPSRC_ML1_P N1
POC_GPIO_1 interrupt from port power switch
Raptor <42> TBT_DP4_N1 DPSNK0_ML1_N DPSRC_ML1_N
SOURCE PORT 0
C282 TBT@ 1 2 0.1U_0402_16V7K TBT_DP4_P2_C AB11 L2
POC_GPIO_2 rtd3 power enable for USB mode
SINK PORT 0
<42> TBT_DP4_P2 DPSNK0_ML2_P DPSRC_ML2_P
<42> TBT_DP4_N2 C284 TBT@ 1 2 0.1U_0402_16V7K TBT_DP4_N2_C AC11 L1 POC_GPIO_3 force full power on
DPSNK0_ML2_N DPSRC_ML2_N
<42> TBT_DP4_P3 C286 TBT@ 1 2 0.1U_0402_16V7K TBT_DP4_P3_C AB13 J2 POC_GPIO_4 battery low indication
C287 TBT@ 1 2 0.1U_0402_16V7K TBT_DP4_N3_C AC13 DPSNK0_ML3_P DPSRC_ML3_P J1
<42> TBT_DP4_N3 DPSNK0_ML3_N DPSRC_ML3_N
+1.8VSDGPU_AON 2 0.1U_0402_16V7K TBT_DP4_AUXP_C
POC_GPIO_5 slp_s3 system indication
C291 TBT@ 1 Y11 W19
<26,42> DP4_AUXP DPSNK0_AUX_P DPSRC_AUX_P
C292 TBT@ 1 2 0.1U_0402_16V7K TBT_DP4_AUXN_C W11 Y19 POC_GPIO_6 rtd3 power enable for cio mode
<26,42> DP4_AUXN DPSNK0_AUX_N DPSRC_AUX_N
TBT_DP4_HPD AA2 G1 DPSRC_HPD R410 1 TBT@ 2 1M_0402_1%
<16,42> TBT_DP4_HPD DPSNK0_HPD DPSRC_HPD
1
R810 SNK0_DDC_CLK Y5 N6 DPSRC_RBIAS R267 1 TBT@ 2 14K_0402_1%

TBT@ 10K_0402_5% SNK0_DDC_DATA R4 DPSNK0_DDC_CLK DPSRC_RBIAS
DPSNK0_DDC_DATA U1
GPIO_0 TBT_I2C_SDA1 <45>
AB15 U2
TBT_I2C_SCL1 <45>
2
AC15 DPSNK1_ML0_P GPIO_1 V1 TBT_EE_WP_N TBT_PCIE_WAKE_N to CPU wake#

<25> GPU_DP4_HPD# DPSNK1_ML0_N GPIO_2 TBT_TMU_CLK_OUT TBT_PCIE_WAKE_N <18>
LC GPIO
V2 @ T24
QV97B AB17 GPIO_3 W1 TBT_PCIE_WAKE_N R272 1 @ 2 0_0402_5% to EC
DPSNK1_ML1_P GPIO_4 EC_TBT_WAKE# <58>
3
D 2N7002KDW_SOT363-6 AC17 W2 TBT_CIO_PLUG_EVENT#

TBT_DP4_HPD DPSNK1_ML1_N GPIO_5 HDMI_SDATA TBT_CIO_PLUG_EVENT# <16>
5 Y1 to CPU GPP_D0 (PCH supports SCI function pin)3/3
GPIO_6 HDMI_SCLK @ T67
G AB19 Y2 @ T68
DPSNK1_ML2_P GPIO_7
1
C TBT_SRC_CFG1 C
AC19 AA1
SINK PORT 1
S R397 DPSNK1_ML2_N GPIO_8 J4 TBTA_I2C_INT1
TBTA_I2C_INT1 <45>
4
AB21 POC_GPIO_0 E2 TBT_POC_GPIO_1

100K_0402_5% DPSNK1_ML3_P POC_GPIO_1 RTD3_USB_PWR_EN_R
POC GPIO
TBT@ AC21 D4 R273 1 @ 2 0_0402_5%
DPSNK1_ML3_N POC_GPIO_2 RTD3_USB_PWR_EN <19>
2
TBT@ H4 TBT_FORCE_PWR_R R274 1 @ 2 0_0402_5%

G
TBT_FORCE_PWR <16>
2
Y12 POC_GPIO_3 F2 BATLOW# R275 1 @ 2 0_0402_5% non Sx systems don’t connect it

DPSNK1_AUX_P POC_GPIO_4 SLP_S3# TBT_BATLOW# <18,19>
W12 D2 R276 1 @ 2 0_0402_5% non Sx systems don’t connect it
DPSNK1_AUX_N POC_GPIO_5 RTD3_CIO_PWR_EN_R SUSP# <39,41,58,68,78,83,85,88>
F1 R277 1 @ 2 0_0402_5% RTD3_CIO_PWR_EN <16>
1 6 R4133 2 @ 1 0_0402_5% Y6 POC_GPIO_6
S
DPSNK1_HPD
D
E1 TBT_TEST_EN R278 1 TBT@ 2 100_0402_5%

TBT_SNK1_DDC_CLK Y8 TEST_EN Y1
QV97A DPSNK1_DDC_CLK
Misc
SNK0_CONFIG1 N4 AB5 TBT_TEST_PWG R279 1 TBT@ 2 100_0402_5% SJ10000UH00
2N7002KDW_SOT363-6 DPSNK1_DDC_DATA TEST_PWR_GOOD S CRYSTAL 25MHZ 20PF XRCGB25M000F2P18R0
TBT@ 2 TBT@ 1 DPSNK_RBIAS Y18 F4 25MHZ_20PF_XRCGB25M000F2P18R0
DPSNK_RBIAS RESET_N TBT_RESET_N <45>
R280 14K_0402_1%
TBT_TDI Y4 D22 TBT_XTAL_25_IN R4129 1 TBT@ 2 33_0402_1% 1 3 R4130 1 TBT@ 2 33_0402_1%
TBT_TMS V4 TDI XTAL_25_IN D23 TBT_XTAL_25_OUT 1 3
TBT_TCK T4 TMS XTAL_25_OUT NC NC
TCK 1 1
TBT_TDO W4 MISC AB3 C293 TBT@ C294
TDO EE_DI TBT_EE_DI <45> 2 4
AC4 27P_0402_50V8J 27P_0402_50V8J
TBT_RBIAS EE_DO TBT_EE_DO <45>
2 TBT@ 1 H6 AC3 TBT@ TBT@
RBIAS EE_CS_N TBT_EE_CS_N <45> 2 2
R285 4.75K_0402_0.5% TBT_RSENSE J6 AB4
TBT_EE_CLK <45>
RSENSE EE_CLK
A15 B7
<45> USB3_A_TRX_DTX_P1 PA_RX1_P PB_RX1_P
B15 A7
<45> USB3_A_TRX_DTX_N1 PA_RX1_N PB_RX1_N
C295 TBT@ 1 2 0.22U_0201_6.3V6K USB3_A_TTX_DRX_P1A17 A9
<45> USB3_A_TTX_C_DRX_P1 PA_TX1_P PB_TX1_P
<45> USB3_A_TTX_C_DRX_N1 C296 TBT@ 1 2 0.22U_0201_6.3V6K USB3_A_TTX_DRX_N1B17 B9
PA_TX1_N PB_TX1_N
C297 TBT@ 1 2 0.22U_0201_6.3V6K USB3_A_TTX_DRX_P0A19 A11
<45> USB3_A_TTX_C_DRX_P0
<45> USB3_A_TTX_C_DRX_N0 C299 TBT@ 1 2 0.22U_0201_6.3V6K USB3_A_TTX_DRX_N0B19 PA_TX0_P
PA_TX0_N
PB_TX0_P
PB_TX0_N
B11 Raptor: change to xtal vendor suggest
P/N: SJ10000UH00 (S CRYSTAL 25MHZ 20PF XRCGB25M000F2P18R0)
TBT PORTS
B21 A13
<45> USB3_A_TRX_DTX_P0 PA_RX0_P PB_RX0_P
A21 B13
<45> USB3_A_TRX_DTX_N0 PA_RX0_N PB_RX0_N
Port A
PORT B
+3VS_TBT C300 TBT@ 1 2 0.1U_0402_16V7K TBT_A_AUX_P Y15 Y16
<45> TBT_A_AUX_P_C TBT_A_AUX_N PA_DPSRC_AUX_P PB_DPSRC_AUX_P
<45> TBT_A_AUX_N_C C302 TBT@ 1 2 0.1U_0402_16V7K W15 W16
PA_DPSRC_AUX_N PB_DPSRC_AUX_N
Follow Intel recommend, 5/4.
B E20 E19 B
<45> TBT_A_USB20_P PA_USB2_D_P PB_USB2_D_P
<45> TBT_A_USB20_N D20 D19
HDMI_SCLK R281 2 TBT@ 1 2.2K_0402_5% PA_USB2_D_N PB_USB2_D_N
HDMI_SDATA R282 2 TBT@ 1 2.2K_0402_5% A5 B4 PB_LSTX
<45> TBTA_LSTX PA_LSTX PB_LSTX PB_LSRX
A4 B5
POC
POC
RTD3_CIO_PWR_EN_R <45> TBTA_LSRX PA_LSRX PB_LSRX PB_DPSRC_HPD
R283 2 TBT@ 1 10K_0402_5% <45> TBTA_HPD
M4 G2
PA_DPSRC_HPD PB_DPSRC_HPD
RTD3_USB_PWR_EN_R R284 2 @ 1 10K_0402_5% 2 TBT@ 1 PA_USB2_RBIAS H19 F19 PB_USB2_RBIAS 1 TBT@ 2
R409 2 TBT@ 1 10K_0402_5% R297 499_0402_1% PA_USB2_RBIAS PB_USB2_RBIAS R298 499_0402_1%
AC23 D6
AB23 THERMDA MONDC_SVR
Follow Intel recommend, 4/28. THERMDA A23
+3.3V_TBT_SX V18 ATEST_P B23
PCIE_ATEST ATEST_N
TBT_I2C_SDA1 R286 2 TBT@ 1 2.2K_0402_5% AC1 DEBUG E18
TBT_I2C_SCL1 R287 2 TBT@ 1 2.2K_0402_5% TEST_EDM USB2_ATEST
TBT_PCIE_WAKE_N R288 2 TBT@ 1 10K_0402_5% L15 W13
TBT_CIO_PLUG_EVENT# R289 2 TBT@ 1 10K_0402_5% N15 FUSE_VQPS_64 MONDC_DPSNK_0 +3.3V_FLASH
SLP_S3# R290 2 TBT@ 1 10K_0402_5% FUSE_VQPS_128 W18
BATLOW# R291 2 TBT@ 1 10K_0402_5% C23 MONDC_DPSNK_1
TBTA_I2C_INT1 R292 2 TBT@ 1 10K_0402_5% C22 MONDC_CIO_0 AB2
TBT_POC_GPIO_1 R293 2 TBT@ 1 10K_0402_5% MONDC_CIO_1 MONDC_DPSRC
1
1
3.3K_0402_5%
AR4C_FC-CSP337
TBT_SRC_CFG1 R294 2 @ 1 10K_0402_5% R310 R307 R308 C305 R311
CFG1 PU is HDMI MODE R369 2 TBT@ 1 1M_0402_5% 3.3K_0402_5% 3.3K_0402_5% .1U_0402_16V7K 3.3K_0402_5%
CFG1 PL if DPSRC NOT IN USE @ TBT@ 2
TBT_SRC_CFG1="0" => AUX CONNECTS TO AR Raptor: intel AR SP refe to 1M TBT@ TBT@
U37
TBT@
2
TBT_SRC_CFG1="1" => DDC CONNECTS TO AR TBT_EE_CS_N 1 8
3/3 PB_LSTX R843 1 TBT@ 2 1M_0402_1% TBT_EE_DO 2 CS# VCC 7
TBT_TMU_CLK_OUT R295 1 TBT@ 2 100K_0402_5% PB_LSRX R844 1 TBT@ 2 1M_0402_1% TBT_EE_WP_N 3 DO(IO1) HOLD#(IO3) 6 TBT_EE_CLK
TBT_FORCE_PWR_R R296 1 TBT@ 2 100K_0402_5% PB_DPSRC_HPD R309 1 TBT@ 2 100K_0402_5% 4 WP#(IO2) CLK 5 TBT_EE_DI
GND DI(IO0)
W25Q80DVSSIG_SO8
Ref B 10k PL / BAD40 100K PL 3/3 TBT@
GPU_DP4_HPD# R299 1 @ 2 100K_0402_5%
SNK0_DDC_CLK R388 1 TBT@ 2 100K_0402_5%
TBTA_LSTX R300 1 TBT@ 2 1M_0402_1% SNK0_DDC_DATA R389 1 TBT@ 2 100K_0402_5%
TBTA_HPD R301 1 TBT@ 2 100K_0402_5%
A TBTA_LSRX A
R302 1 TBT@ 2 1M_0402_1%
TBT_SNK1_DDC_CLK R303 1 TBT@ 2 100K_0402_5%
SNK0_CONFIG1 R304 1 TBT@ 2 100K_0402_5% SNK0_DDC_connect 2k PU only if SRC0 is connected HDMI
otherrise can be 100k PD
U36 TBT@

S IC JHL6540 SLLSN C1 FC-CSP THUNDERBOLT THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TBT AR(1/2)
SA00009ZV70 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
5 4 3 2 1
5 4 3 2 1
+3VALW +3.3V_TBT_SX
1 2
R312 0_0603_5%
2
TBT@
R313
0_0603_5%
+3.3V_LC +3.3V_TBT_SX +3.3V_TBT_S0 +3VS_TBT
+3VS +3VS_TBT TBT@
1
1 2
R314 0_0603_5%
0.1U_0201_10V6K
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
@
1 1 1 1 1 1 1
Option 1 for wake support over TBT: C306 C307 C308 C309 C310 C311 C312
1.Connect R312 and R313,
2.Simple BIOS implementation TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ TBT@
D 2 2 2 2 2 2 2 D
Option 2 for wake support over TBT:
1.Connect R312 and R314
R13
+0.9V_DP
R6
H9
F8
2.Bios need to implement Sx emtry pre-notice flow by PCIe2TBT
U36B
Option 3 No wake support at all from AR L8 A2
VCC3P3_SX
VCC3P3A
VCC3P3_LC
VCC3P3_S0
VCC0P9_DP VCC3P3_SVR
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1. Connect R313 and R314 L11 A3
L12 VCC0P9_DP VCC3P3_SVR B3
1 1 1 1 1 1 1 VCC0P9_DP VCC3P3_SVR
C313 C314 C320 C315 C321 C322 C316 M8
T11 VCC0P9_DP
TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ T12 VCC0P9_DP L9 +0.9V_SVR
2 2 2 2 2 2 2 VCC0P9_DP VCC0P9_SVR
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
L6 M9
M6 VCC0P9_ANA_DPSRC VCC0P9_SVR E12
VCC0P9_ANA_DPSRC VCC0P9_SVR_ANA 1 1 1 1 1 1 1
V11 E13 C317 C323 C324 C325 C326 C327 C318
V12 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F11
+0.9V_PCIE V13 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F12 TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ Share same GND plane
VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F13 2 2 2 2 2 2 2
M13 VCC0P9_SVR_ANA F15
VCC0P9_PCIE VCC0P9_SVR_ANA
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
M15 J9
M16 VCC0P9_PCIE VCC0P9_SVR_SENSE
1 1 1 1 VCC0P9_PCIE
C319 C328 C329 C330 L19 L13 0.6UH_MND-04ABIR60M-XGL_20%
N19 VCC0P9_ANA_PCIE_1 C1 TBT_SVR_IND 1 2
TBT@ TBT@ TBT@ TBT@ L18 VCC0P9_ANA_PCIE_1 SVR_IND C2 TBT@
2 2 2 2 VCC0P9_ANA_PCIE_2 SVR_IND
47U_0805_6.3V6M
47U_0805_6.3V6M
47U_0805_6.3V6M
M18 D1 1 1 1
+0.9V_USB VCC0P9_ANA_PCIE_2 SVR_IND
C331
C332
C333
N18 6/3, Change PN
VCC
VCC0P9_ANA_PCIE_2
R15 A1 to SHI000MD00 TBT@ TBT@ TBT@
1U_0201_6.3V6M VCC0P9_USB SVR_VSS 2 2 2
1U_0201_6.3V6M
R16 B1
+0.9V_CIO VCC0P9_USB SVR_VSS B2
1 1 SVR_VSS
C334 C335 R8
R9 VCC0P9_CIO
TBT@ TBT@ R11 VCC0P9_CIO
2 2 VCC0P9_CIO
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
R12 F18 +0.9V_LVR_OUT
VCC0P9_CIO VCC0P9_LVR
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 H18
C336 C337 C338 +3.3V_ANA_PCIE L16 VCC0P9_LVR J11
VCC3P3_ANA_PCIE VCC0P9_LVR 1 1 1 1
+3.3V_ANA_USB2 J16 H11 C339 C340 C341 C342
C
TBT@ TBT@ TBT@ VCC3P3_ANA_USB2 VCC0P9_LVR_SENSE C
2 2 2
1U_0201_6.3V6M
1U_0201_6.3V6M
A6 V5 TBT@ TBT@ TBT@ TBT@
A8 VSS_ANA VSS_ANA V6 2 2 2 2
1 1 VSS_ANA VSS_ANA
C343 C344 A10 V8
A12 VSS_ANA VSS_ANA V9
TBT@ TBT@ A14 VSS_ANA VSS_ANA V15
2 2 A16 VSS_ANA VSS_ANA V16
A18 VSS_ANA VSS_ANA V20
A20 VSS_ANA VSS_ANA W5
A22 VSS_ANA VSS_ANA W6
B6 VSS_ANA VSS_ANA W8
B16 VSS_ANA VSS_ANA Y9
B22 VSS_ANA VSS_ANA AA22
D8 VSS_ANA VSS_ANA AA23
D9 VSS_ANA VSS_ANA AB6
+3.3V_TBT_S0 +3VS_TBT D13 VSS_ANA VSS_ANA AB12
L14 D16 VSS_ANA VSS_ANA AB16
GND
1UH +-20% LQM18PN1R0MFHD D18 VSS_ANA VSS_ANA AB18
1 2 E8 VSS_ANA VSS_ANA AB20
VSS_ANA VSS_ANA
1U_0201_6.3V6M
TBT@ E9 AB22
VSS_ANA VSS_ANA
47U_0805_6.3V6M
47U_0805_6.3V6M
1 1 1 E11 AC6
VSS_ANA VSS_ANA
C346
C347
C345 E15 AC8

E16 VSS_ANA VSS_ANA AC10
TBT@ TBT@ TBT@ E22 VSS_ANA VSS_ANA AC12
2 2 2 E23 VSS_ANA VSS_ANA AC14
F9 VSS_ANA VSS_ANA AC16
B F16 VSS_ANA VSS_ANA AC18 B
F20 VSS_ANA VSS_ANA AC20
G22 VSS_ANA VSS_ANA AC22
G23 VSS_ANA VSS_ANA D5
H1 VSS_ANA VSS E4
H2 VSS_ANA VSS E5
H12 VSS_ANA VSS E6
H13 VSS_ANA VSS F5
H15 VSS_ANA VSS F6
H16 VSS_ANA VSS H5
H20 VSS_ANA VSS H8
J5 VSS_ANA VSS J8
J18 VSS_ANA VSS J12
J19 VSS_ANA VSS J13
J20 VSS_ANA VSS J15
J22 VSS_ANA VSS L13
J23 VSS_ANA VSS M11
K1 VSS_ANA VSS M12
K2 VSS_ANA VSS N8
L5 VSS_ANA VSS N9
L20 VSS_ANA VSS N11
L22 VSS_ANA VSS N12
L23 VSS_ANA VSS N13
M1 VSS_ANA VSS T6
M2 VSS_ANA VSS T8
M5 VSS_ANA VSS T9
M19 VSS_ANA VSS T13
M20 VSS_ANA VSS T15
N5 VSS_ANA VSS T16
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
N20 VSS_ANA VSS T18

N22 VSS_ANA VSS AB1
N23 VSS_ANA VSS AC2
VSS_ANA VSS
AR4C_FC-CSP337
P1
P2
R5
R18
R19
R20
R22
R23
T1
T2
T5
T20
U22
U23
A A
@

TBT AR(2/2)
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Primary
@
+TBTA_VBUS +TBTA_VBUS
C2788
1 2
+3VALW +3VALW_PD
22U_0603_6.3V6M
R315 1 @ 2 0_0402_5%
W=120mils JUSB1
A1 B12
+5VALW +5VALW_PD GND1 GND3
1 @ J29 <43> USB3_A_TTX_C_DRX_P0
A2 B11 USB3_A_TRX_DTX_P0 <43>
JUMP_43X79 A3 SSTXP1 SSRXP1 B10
D +3VALW +3VALW_PD <43> USB3_A_TTX_C_DRX_N0 SSTXN1 SSRXN1 USB3_A_TRX_DTX_N0 <43> D
C348 1 2 H35 H36 H37
1 2 0.47U_0201_25V 2 1 C349 A4 B9 0.47U_0201_25V 2 1 C350 H_2P5X1P0 H_2P5X1P0 H_2P5X1P0
.1U_0402_16V7K
2 TBT@ VBUS1 VBUS3 TBT@
TBT@ TBTA_CC1 TBTA_SBU2
A5 B8
1
CC1 SUB2
2.2K_0402_5%
R806
2.2K_0402_5%
R807
1
TBT_A_USB20_PT A6 B7 TBT_A_USB20_NB
TBT_A_USB20_NT A7 DP1 DN2 B6 TBT_A_USB20_PB
2
DN1 DP2 @ @ @
G
TBT@ TBT@ TBTA_SBU1 A8 B5 TBTA_CC2
Bottom
2
2
SUB1 CC2 H38 H39 H40
0.47U_0201_25V 2 1 C357 A9 B4 0.47U_0201_25V 2 1 C358
TOP
H_2P5X1P0 H_2P5X1P0 H_2P5X1P0
6 1 TBT_I2C_SCL2 TBT@ VBUS2 VBUS4 TBT@
<58,62> EC_SMB_CK3
S
A10 B3
D
+5VALW_PD +20V_HV_SYS <43> USB3_A_TRX_DTX_N1 SSRXN2 SSTXN2 USB3_A_TTX_C_DRX_N1 <43>

<43> USB3_A_TRX_DTX_P1
A11 B2 USB3_A_TTX_C_DRX_P1 <43>
1
Q38A SSRXP2 SSTXP2
2N7002KDW_SOT363-6 A12 B1
TBT@ GND2 GND4 @ @ @
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
4.7U_0603_25V6K
1 1 1 1 1
5
2
C351 C352 C353 C354 C355 1 4
G
1
GND5 GND8
SDM10U45-7_SOD523-2~D
L30ESD24VC3-2_SOT23-3
@ 2 5
1
GND6 GND9
D31
D19
TBT@ TBT@ TBT@ TBT@ C356 3 6
2 2 2 2 2 1U_0603_25V6K GND7 GND10
2
3 4 TBT_I2C_SDA2 TBT@
<58,62> EC_SMB_DA3
S
TBT@
EMC@
D
CONN@
2
Q38B TBTA_LDO_BMC SP060008H0L
2N7002KDW_SOT363-6 +1.8VD_TBTA_LDO JAE_DX07S024JJ2R1300~D
1
1
TBT@ +1.8VA_TBTA_LDO
0_0402_5%
R425
1 1 1
C360 C361 @
C359
2.2U_0402_10V6M
2.2U_0402_10V6M
2.2U_0402_6.3V6M TBT@ TBT@ EMC@ D23
2
2 2 2 USB3_A_TTX_C_DRX_P0 D20 1 EMC@ 2 TBTA_SBU1 6 3 TBT_A_USB20_PT
TBT@ +3VALW_PD I/O4 I/O2
PESD5V0H1BSF SOD962
+5VALW
USB3_A_TTX_C_DRX_N0 D21 1 EMC@ 2 5 2
1 VDD GND
10U_0402_6.3V6M
C362
PESD5V0H1BSF SOD962
TBT@
2 USB3_A_TRX_DTX_P0 D22 1 EMC@ 2 TBT_A_USB20_NT 4 1 TBTA_CC1
H10
C11
D11
A11
B11
B10
A10
I/O3 I/O1
H1
B1
K1
A2
E1
A6
A7
A8
B7
B9
A9
C C
U39 PESD5V0H1BSF SOD962 AZC099-04SP.R7G_SOT23-6
F1 SC300003S00
VIN_3V3
VDDIO
LDO_1V8A
PP_CABLE
PP_5V0
PP_5V0
PP_5V0
PP_5V0
PP_HV
PP_HV
PP_HV
PP_HV
SENSEP
HV_GATE1
HV_GATE2
LDO_1V8D
LDO_BMC
SENSEN
I2C_ADDR USB3_A_TRX_DTX_N0 D24 1 EMC@ 2
D1 +3.3V_TBT_SX_R SC300003S00
<43> TBT_I2C_SDA1 I2C_SDA1 AZC099-04SP.R7G_SOT23-6
<43> TBT_I2C_SCL1
D2 PESD5V0H1BSF SOD962
C1 I2C_SCL1 TBTA_SBU2 1 4 TBT_A_USB20_NB
<43> TBTA_I2C_INT1 I2C_IRQ1_N USB3_A_TTX_C_DRX_P1 I/O1 I/O3
D25 1 EMC@ 2
TBT_I2C_SDA2 A5 PESD5V0H1BSF SOD962 +5VALW

TBT_I2C_SCL2 B5 I2C_SDA2 H11 +3.3V_FLASH 2 5
PD_IRQ# B6 I2C_SCL2 VBUS J10 USB3_A_TTX_C_DRX_N1 D26 1 EMC@ 2 GND VDD
<58> PD_IRQ# I2C_IRQ2_N VBUS
PD_IRQ# PU at EC side J11
1
B2 VBUS K11 PESD5V0H1BSF SOD962

R319 C2 GPIO0 VBUS TBT_A_USB20_PB 3 6 TBTA_CC2
GPIO1 1 I/O2 I/O4
@ 10K_0402_5% D10 USB3_A_TRX_DTX_P1 D27 1 EMC@ 2
GPIO2 1
G11 C363 D28 EMC@
C10 GPIO3 C364 PESD5V0H1BSF SOD962
<43> TBTA_HPD 1U_0201_6.3V6M
2
E10 GPIO4 H2 2
TBT@ 10U_0402_6.3V6M
G10 GPIO5 VOUT_3V3 2 USB3_A_TRX_DTX_N1 D29 1 EMC@ 2
GPIO6 TBT@
D7
GPIO8_CFG H6 GPIO7 PESD5V0H1BSF SOD962
GPIO8 G1
A3 LDO_3V3
<43> TBT_EE_CLK SPI_CLK
<43> TBT_EE_DI B4
A4 SPI_MOSI
<43> TBT_EE_DO SPI_MISO TBT_A_USB20_PT
B3 K6
<43> TBT_EE_CS_N SPI_SS_N C_USB_TP TBT_A_USB20_NT
L6
TBT_A_USB20_P L5 C_USB_TN
<43> TBT_A_USB20_P TBT_A_USB20_N USB_RP_P
K5
<43> TBT_A_USB20_N USB_RP_N
TBT_A_USB20_PB
Raptor: default use PD 65982 path
R320 1 2 E2 K7
Raptor: FAE review F2 UART_TX
UART_RX
C_USB_BP
C_USB_BN
L7 TBT_A_USB20_NB
100K_0402_5% TBT@
TBT@ F4 C365 2 1 220P_0402_50V8J
G4 SWD_DATA
SWD_CLK L9 TBTA_CC1
C_CC1 L10 TBTA_CC2 +5VALW_PD +TBTA_VBUS
C_CC2 TBT@
2 TBT@ 1 TBT_MRESET E11 C366 2 1 220P_0402_50V8J
R321 100K_0402_5% MRESET US13
K9 RPD_G1 R322 1 @ 2 0_0402_5% @
R323 1 @ 2 0_0402_5% L4 RPD_G1 K10 RPD_G2 R324 1 @ 2 0_0402_5% 6 1
B <43> TBTA_LSTX B
R325 1 @ 2 0_0402_5% K4 TBT_LSTX/R2P RPD_G2 R423 1 TBT@ 2 0_0402_5% IN OUT
<43> TBTA_LSRX TBT_LSRX/P2R R424 1 TBT@ 2 0_0402_5%
+3.3V_FLASH RSET_TBT 5 2
+3.3V_TBT_SX R326 2 TBT@ 1 100K_0402_5%TBTA_DIG_AUD_P L3 E4 DEBUG_CTL1 R327 2 TBT@ 1 10K_0402_5% SET GND
R328 2 TBT@ 1 100K_0402_5%TBTA_DIG_AUD_N K3 DIG_AUD_P/DEBUG3 DEBUG_CTL1 D5 DEBUG_CTL2 R329 2 1 10K_0402_5%
DIG_AUD_N/DEBUG4 DEBUG_CTL2 TBT@ R4039 2 @ 1VBUSEN 4 3
<58> EC_TYPEC_EN
1
0_0402_5% EN FLAG
R330 R331 2 TBT@ 1 100K_0402_5%TBTA_DEBUG1 L2 SY6861B1ABC_TSOT23-6
R332 2 TBT@ 1 100K_0402_5%TBTA_DEBUG2 K2 DEBUG1
100K_0402_5%
DEBUG2
TBT@ TBTA_SBU1
K8 R333 1 @ 2 0_0402_5%
2
J1 C_SBU1
<43> TBT_A_AUX_P_C AUX_P TBTA_SBU2 RSET_TBT
J2 L8 R334 1 @ 2 0_0402_5%
<43> TBT_A_AUX_N_C AUX_N C_SBU2
1
+3.3V_FLASH
1
R335 1 TBT@ 2 BUSPOWER# F10
R336 0_0402_5% BUSPOWER_N F11 R337 1 @ 2 0_0402_5% RS113 RS109 RS110
100K_0402_5% TBT_RESET_N <43>
RESET_N 6.2K_0402_5% 8.2K_0402_5% 4.3K_0402_5%
TBT@ TBTA_ROSC G2 @ @ @
2
+1.8VS R_OSC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3 2
1 @ 2 1 TBT@ 2 R339
EC_TBT_RESET <58>
1
R338 0_0402_5% 0_0402_5% D

R340 TBT@ 5
TYPEC_3A <18,49>
A1
D6
E5
E6
E7
F5
G5
H4
H5
B8
D8
E8
F6
F7
F8
G6
G7
G8
H7
H8
L1
L11
2
15K_0402_1% TPS65982_BGA96 G
R341 TBT@
0_0402_5% S QS6B
2
4
6
@ D 2N7002KDW_SOT363-6
SA0000CN200 2
@
TYPEC_1P5A <16,49>
1
TI suggest reserve 0ohm to 1.8V,3.3V,GND G

S IC TPS65982DDZBHR NFBGA 96P USD-PD CTRL
SS
<58> TBT_HRESET checked bios

1 S QS6A
1
1
2N7002KDW_SOT363-6
R418 C367 Raptor:TPS65982DD (use TPS65982 symbol) @
100K_0402_5% 0.22U_0402_16V7K
+3.3V_FLASH 2
TBT@ TBT@
G518 MOS Current Limit
2
GPP_B1 GPP_B4 RSET(kΩ) MODE limit point

1
(TYPEC_1P5A) (TYPEC_3A)
R420 L L 6.2 0.9A 1.09A
10K_0402_5%
A H 3.53 1.5A 1.92A A
L
2
GPIO8_CFG
H L 2.54 2A 2.67A
TI suggest
1
*H H 1.94 3A 3.5A
R421
@ 10K_0402_5%
2
2017/11/23
Compal Secret Data
2017/12/31 Title
TBT PD+USB TYPE C
Custom 0.1
5 4 3 2 1
A B C D E
+1.8VS_7490
+3VS +3VS_7490 +1.8VS +1.8VS_7490

+VDD09_LEX
.1U_0402_16V7K
1U_0201_6.3V6M
RG2803 RG2804
1000P_0402_50V7K
1 2 1 2 1 1 1
LG7
CG998
CG997
7490_+AVDD09
CG996
0_0603_5% 0_0603_5% 1 2
@ @ 2 2 2
0.01U_0402_16V7K
4.7U_0402_6.3V6M
BLM18SG221TN1D_2P
+3VALW +1.8VALW
1000P_0402_50V7K
1 1
1
1 220ohm_2.5A 1
CG1000
CV953
DCR=0.04ohm
CG999
RG2962 RG2963
1 2 1 2
2
2 2
0_0603_5% 0_0603_5%
+1.8VS_7490 +3VS_7490
.1U_0402_16V7K
1U_0201_6.3V6M
1000P_0402_50V7K
1 1 1
1U_0201_6.3V6M
CG1005
1000P_0402_50V7K
CG1001
CG1004
1 1
CG1002
2 2 2
CG1003
2 2
U2621
28
36
25
16
33
40
5
3
6
1017, Analogix suggest
DVDD09
DVDD09
AVDD09
AVDD09
VDD18
VDD18
VDD18
AVDD18
AVDD18
VDD33
14 NV_RT_SSTXP_C CG2808 1 2 0.22U_0201_6.3V6K NV_RT_SSTXP
TX1P NV_RT_SSTXP <48>
15 NV_RT_SSTXN_C CG2809 1 2 0.22U_0201_6.3V6K NV_RT_SSTXN
TX1N NV_RT_SSTXN <48>
2 2
11 NV_RT_SSRXN_C CG2810 1 2 0.22U_0201_6.3V6K NV_RT_SSRXN
RX1N NV_RT_SSRXP_C NV_RT_SSRXP NV_RT_SSRXN <48>
12 CG2811 1 2 0.22U_0201_6.3V6K
RX1P NV_RT_SSRXP <48>
1017, Analogix suggest +1.8VS_7490
L27 1 2
.1U_0402_16V7K
22U_0603_6.3V6M
0731, Analogix suggest HCB2012VF-601T20_2P
1000P_0402_50V7K
10U_0402_6.3V6M
1 1 1 1
CG1007
CG1009
CG1006
Connect to chipset’s SSRXP
CG1008
NV_SSRXN CG2795 1 2 0.22U_0201_6.3V6K NV_SSRXN_C 38 2 2 2 2
<26> NV_SSRXN SSTXN
NV_SSRXP CG2794 1 2 0.22U_0201_6.3V6K NV_SSRXP_C 39
<26> NV_SSRXP SSTXP
NV_SSTXN CG1010 1 2 0.22U_0201_6.3V6K NV_SSTXN_C 34
<26> NV_SSTXN NV_SSTXP NV_SSTXP_C SSRXN
CG1011 1 2 0.22U_0201_6.3V6K 35
<26> NV_SSTXP
MUX1
Connect to chipset’s SSTXP SSRXP
4
<49> USB3_RT_POWER_EN POWER_EN
18 Reference use 3.3uH
TEST_R 9 +VDD09_LEX
VIN
CCG4_MASTER_SDA 26 LG8 1 2
<26,47,48,49,100> CCG4_MASTER_SDA CCG4_MASTER_SCL SDA
24 3.3UH_UHP252010BF-3R3M_20%
<26,47,48,49,100> CCG4_MASTER_SCL SCL
.1U_0402_16V7K
22U_0603_6.3V6M
30
29 TEST_0
TEST_1 1 1
CG1012
CG1013
8
3 VX 3
19 10 2 2
TEST6 VFB
NV_RT_ADDSEL0 23
NV_RT_ADDSEL1 22 I2C_ADR_SEL0
I2C_ADR_SEL1 7 NV_RT_DCDC_GND
VGND
21 NV_RT_XTALO
DVSS(THERMAL_PAD)
32 XTAL_O
+1.8VS_7490 31 DCI_CLK
DCI_DAT 20 NV_RT_XTALI
XTAL_I 1 2
27 RG2786 1M_0402_5%
TEST_EN
1
1
AVSS
AVSS
AVSS
AVSS
RG3012
RG2955 RG2957 680_0402_1%
4.7K_0402_5% 4.7K_0402_5% YG2
41
ANX7490QN-CB-R_QFN40_5X5 24MHZ_18PF_XRCGB24M000F2P51R0
2
13
17
37
2
2
NV_RT_ADDSEL0 3 1
3 1
NC NC
33P_0402_50V8J
33P_0402_50V8J
NV_RT_ADDSEL1
4 2
CG1015
CG1016
@ @
I2C address: 0x2E
1
4 4
RG2956 RG2958
4.7K_0402_5% 4.7K_0402_5%
RG2992
2
1 2
Signal GND and Security Classification Compal Secret Data Compal Electronics, Inc.
0_0603_5%
GND_DCDC must be
separated. They
are connected at THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV USB-C ANX7490
a single point. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A B C D E
A B C D E
18P_0402_50V8J
DP5_AUXP Note:
+3VS +3VS_7440 +VDD09_LEX_7440
1. These capacitors are used to reduce the
CG1050
near +1.8VS_7440
RG2805 pin21 DP5_AUXN slew rate of AUX CH to meet the DP V1.4 AUX CH
LG9
1 2 requirement.
1 2 7440_+AVDD09
0_0603_5%
2. These capacitors are mandatory for HBR3
0.01U_0402_16V7K
4.7U_0402_6.3V6M
.1U_0402_16V7K
1U_0201_6.3V6M
@ BLM18SG221TN1D_2P
application, for HBR2 and lower, the caps are optional.
1000P_0402_50V7K
1000P_0402_50V7K
18P_0402_50V8J
1 1 1 1 1 UTC_A8_SBU1_AUX
CG1021
220ohm_2.5A
+3VALW
CG1018
CV954
CG1020
CG1051
DCR=0.04ohm
CG1017
CG1019
UTC_B8_SBU2_AUX 3. Both the upstream and downstream port
2
RG2960 2 2 2 2 2 need to add the
1 2 capacitor for HBR3 application.
1
0731, Vendor suggest 1
0_0603_5%
+3VS_7440 +1.8VS_7440 +ANX7440_DVDD_IO
+ANX7440_DVDD_IO RG2991
1 2
+1.8VS +1.8VS_7440 0_0603_5%
1U_0201_6.3V6M
RG2806
0808, FAE suggest, follow NV design
1U_0201_6.3V6M
.1U_0402_16V7K
1000P_0402_50V7K
1 2 1 1
1000P_0402_50V7K
CG1022
1 1 1
CG1023
CG1026
0_0603_5%
+3VS
CG1025
CG1024
@ 2 2
2 2 2
1
+1.8VALW
RG2787
RG2961 100K_0402_5%
1 2
10
41
21
51
22
32
48
60
11
39
54
2
1
0_0603_5% U2622
DP5_AUXN_C @
DVDD09_10
DVDD09_41
AVDD09_1
AVDD09_21
AVDD09_51
VDD18_22
VDD18_32
VDD18_48
VDD18_60
VDD_IO_11
VDD_IO_39
VDD33
DP5_AUXP_C
1
19 UTC_A2_SSTXp1
TX1P UTC_A2_SSTXp1 <49>
CG1031 1 2 0.1U_0201_10V6K DP5_TXP0_C 55 20 UTC_A3_SSTXn1 RG2788
<26> DP5_TXP0 ML0P TX1N UTC_A3_SSTXn1 <49>
CG1027 1 2 0.1U_0201_10V6K DP5_TXN0_C 56 100K_0402_5%
<26> DP5_TXN0 DP5_TXP1_C ML0N UTC_B10_SSRXn1
CG1028 1 2 0.1U_0201_10V6K 58 16
<26> DP5_TXP1 DP5_TXN1_C ML1P RX1N UTC_B11_SSRXp1 UTC_B10_SSRXn1 <49>
CG1032 1 2 0.1U_0201_10V6K 59 17
<26> DP5_TXN1 UTC_B11_SSRXp1 <49>
2
2 CG1029 1 2 0.1U_0201_10V6K DP5_TXP2_C 2 ML1N RX1P 2
<26> DP5_TXP2
CG1030 1 2 0.1U_0201_10V6K DP5_TXN2_C 3 ML2P Analogix Semi @
<26> DP5_TXN2 DP5_TXP3_C ML2N UTC_B2_SSTXp2
CG1033 1 2 0.1U_0201_10V6K 5 24
<26>
<26>
DP5_TXP3
DP5_TXN3
CG1034 1 2 0.1U_0201_10V6K DP5_TXN3_C 6 ML3P
ML3N
TX2P
TX2N
23 UTC_B3_SSTXn2
UTC_B2_SSTXp2 <49>
UTC_B3_SSTXn2 <49>
0801, Analogix suggest unpop
26 UTC_A10_SSRXn2
DP5_AUXP DP5_AUXP_C RX2N UTC_A11_SSRXp2 UTC_A10_SSRXn2 <49>
CG1035 1 2 .1U_0402_16V7K 8 27
<26> DP5_AUXP DP5_AUXN DP5_AUXN_C AUXP RX2P UTC_A11_SSRXp2 <49>
CG1036 1 2 .1U_0402_16V7K 9
<26> DP5_AUXN AUXN UTC_A8_SBU1_AUX
34 CG1037 1 2 .1U_0402_16V7K UTC_A8_SBU1_AUX <49> +1.8VS_7440
SBU1 33 CG1038 1 2 .1U_0402_16V7K UTC_B8_SBU2_AUX
SBU2 UTC_B8_SBU2_AUX <49>
USB3_PRX_DTX_N2 CG1039 1 2 0.22U_0201_6.3V6K USB3_PRX_DTX_N2_C 52
<17> USB3_PRX_DTX_N2 SSTXN
USB3_PRX_DTX_P2 CG1040 1 2 0.22U_0201_6.3V6K USB3_PRX_DTX_P2_C 53 L28 1 2
<17> USB3_PRX_DTX_P2 SSTXP
USB3_PTX_DRX_N2 CG2796 1 2 0.22U_0201_6.3V6K USB3_PTX_DRX_N2_C 49 45 RG2790 1 2 100K_0402_5%
<17> USB3_PTX_DRX_N2 SSRXN PULL_1
.1U_0402_16V7K
22U_0603_6.3V6M
USB3_PTX_DRX_P2 CG2797 1 2 0.22U_0201_6.3V6K USB3_PTX_DRX_P2_C 50 44 RG2791 1 2 100K_0402_5% HCB2012VF-601T20_2P
<17> USB3_PTX_DRX_P2 SSRXP PULL_2
1000P_0402_50V7K
10U_0402_6.3V6M
1 1 1 1
1017, Analogix suggest
CG1042
CG1044
DP_USB_MUX_POW ER_EN
CG1041
7
<49> DP_USB_MUX_POWER_EN POWER_EN
CG1043
28
TEST_R 14 2 2 2 2
+3VS_7440 VIN
RG2793 1 @ 2 1.8K_0402_5% 38 Reference use 3.3uH
37 SDA +VDD09_LEX_7440
RG2792 1 @ 2 1.8K_0402_5% SCL
LG10 1 2
43 3.3UH_UHP252010BF-3R3M_20%
OP_MODE_0
.1U_0402_16V7K
22U_0603_6.3V6M
CCG4_MASTER_SDA 42 13
<26,46,48,49,100> CCG4_MASTER_SDA CCG4_MASTER_SCL OP_MODE_1 VX
<26,46,48,49,100> CCG4_MASTER_SCL 1 1
29 15
FLIP VFB
CG1045
CG1046
3 +1.8VS_7440 Raptor: I2C PU at CCG4 side 36
I2C_ADR_SEL0 2 2
3
35
RG2808 1 2 4.7K_0402_5% 7440_OP_MODE_0 I2C_ADR_SEL1 12 NV_ACTMUX_DCDC_GND
RG2809 1 2 4.7K_0402_5% 7440_OP_MODE_1 VGND
RG2810 1 2 4.7K_0402_5% 7440_FLIP

31 NV_MUX_XTALO
47 XTAL_O
46 DCI_CLK
NV_MUX_ADDSEL0 DCI_DAT 30 NV_MUX_XTALI
NV_MUX_ADDSEL1 XTAL_I 1 2
40 RG2795 1M_0402_5%
TEST_EN
AVSS_18
AVSS_25
AVSS_57
1
AVSS_4
EPAD
RG3011
680_0402_1%
YG3
+1.8VS_7440 24MHZ_18PF_XRCGB24M000F2P51R0
4
18
25
57
61
2
ANX7440QN-CB-R_QFN60_7X7
3 1
+3VS 3 1
I2C address: 0x2C NC NC
33P_0402_50V8J
33P_0402_50V8J
1
4 2
CG1048
CG1049
RG2789
RG2813 RG2815 RG2981 1 2
4.7K_0402_5% 4.7K_0402_5% @ 1M_0402_5%
Signal GND and 0_0603_5%
GND_DCDC must be
2
NV_MUX_ADDSEL0
4 4
DP5_AUXP separated. They
NV_MUX_ADDSEL1 DP5_AUXN are connected at
a single point.
2
@ @ RG2982
1
@ 1M_0402_5%
RG2814 RG2816 Security Classification Compal Secret Data Compal Electronics, Inc.
4.7K_0402_5% 4.7K_0402_5% Issued Date 2017/11/23 Deciphered Date 2018/09/01 Title
1
NV USB-C ANX7440
2
0809, NV FAE suggest no stuff

A B C D E
A B C D E
+3VS_7428
+3VALW
RG2959
1 2
0_0603_5%
+3VS
1 RG2807 +3VALW @ 1
1 2 RG2999
1 2
0_0603_5% 0_0603_5%
@
+3VS_7428
+1.8VALW +ANX7428_DVDD_IO
LG11
RG2797
1 2 +3VS_7428_AVDD33 1 2
0_0603_5%
1U_0201_6.3V6M
.1U_0402_16V7K
BLM18SG221TN1D_2P
1000P_0402_50V7K
1 1 1
CG1052
CG1053
+ANX7428_DVDD_IO
CG1054
The DVDD_IO can be power supplied by 1.8V ~ 3.3V:
2 2 2 If AP's IO type is 1.8V, select 1.8V power for DVDD_IO;
If AP's IO type is 3.3V, select 3.3V power for DVDD_IO.
1U_0201_6.3V6M
.1U_0402_16V7K
1000P_0402_50V7K
1 1 1
CG1055
CG1056
CG1057
2 2 2
U2623
13 25 UTC_A6
AVDD33 SSTXP1 UTC_A6 <49>
24 26 UTC_A7
AVDD33 SSTXN1 UTC_A7 <49>
40 31
2 1 DVDD_IO SSRXP1 32 2
2 DP_LN_0P SSRXN1 30 UTC_B6
DP_LN_0N SSTXP2 UTC_B6 <49>
NV_RT_SSRXP 7 29 UTC_B7
<46> NV_RT_SSRXP DP_LN_1P SSTXN2 UTC_B7 <49>
NV_RT_SSRXN 8 36
<46> NV_RT_SSRXN NV_RT_SSTXP DP_LN_1N SSRXP2
9 35
<46> NV_RT_SSTXP NV_RT_SSTXN DP_LN_2P SSRXN2
10 19
<46> NV_RT_SSTXN DP_LN_2N SBU1
3 18 0731, Analogix suggest to NC
4 DP_LN_3P SBU2 21
16 DP_LN_3N CC1 20 @
0809, follow NV ref design AUXP CC2
17 22 CG1059 1 2 1000P_0402_50V7K
37 AUXN CC_CAP 42
USB20_P2 12 HPD M_SDA/GPIO_5 43 ANX7428_VBUS_CTRL RG3000 1 2 4.7K_0402_5%
<14> USB20_P2 USB20_N2 SSTX_P M_SCL/GPIO_4 ANX7428_ADR1
11 47
<14> USB20_N2 SSTX_N I2C_ADR_1/GPIO_3 ANX7428_ADR0
6 48
5 SSRX_P I2C_ADR_0/INTP_IN/GPIO_2 44
USB3O2_MUX_RESET_N RG2800 1 2 0_0402_5% USB3O2_MUX_RESET_R_N 33 SSRX_N VCONN2_EN/GPIO_1 45
<49> USB3O2_MUX_RESET_N RESET_N VCONN1_EN/GPIO_0
34 15
RG2811 1 2 4.7K_0402_5% 7428_DRP_EN 28 TEST_EN VBUS_DIV6 41 RG2812 1 2 4.7K_0402_5%
38 DRP_EN INTP_OUT 14
39 CFG_SDA CABLE_DET 27 USB3O2_MUX_PW R_EN
CFG_SCL PWR_EN USB3O2_MUX_PWR_EN <49>
23 46
NC DVSS 49
0801, Analogix suggest to pop GND
ANX7428QN-AA-R_QFN48_6X6
RESET_N pin: SA000094H10

Controlled by AP or CPU +ANX7428_DVDD_IO
Logic 1: Set chip to normal mode. I2C address: 0x80
3 3
Logic 0: Set chip to reset mode.
1
@ @
RG2798 RG2799
4.7K_0402_5% 4.7K_0402_5%
CCG4_MASTER_SDA
<26,46,47,49,100> CCG4_MASTER_SDA
Raptor: I2C PU at CCG4 side
2
CCG4_MASTER_SCL ANX7428_ADR1
<26,46,47,49,100> CCG4_MASTER_SCL
ANX7428_ADR0
I2C_ADR_1 and I2C_ADR_0 pin:
1. The I2C address is determined approximately 500ns after RESET_N turns from 0 to 1,
1
these two pins' input should be kept at a stable value during this period.
2. There are internal pull-down resistors on I2C_ADR_0 and I2C_ADR_1 pins. RG2990 RG2989
3. If external pull-up resistor is not populated, the I2C_ADR_0 or I2C_ADR_1 is logic 0. 4.7K_0402_5% 4.7K_0402_5%
4. If external pull-up is populated, the I2C_ADR_0 or I2C_ADR_1 is logic 1.
2
4 4

NV USB-C ANX7428
A B C D E
5 4 3 2 1
+1.8V_CCG4
TypeC NV +3V_CCG4
+1.8V_CCG4
CCG4 Master, to 7440, 7428, NV GPU,
1
2.2K_0402_5%
R4067
R4072
1
2.2K_0402_5%
R4066
@ +3V_CCG4 1 2 PS_VBUS_ALT
.1U_0402_16V7K
.1U_0402_16V7K
+3VS 100K_0402_1%
1U_0201_6.3V6M
1 1 1
C2755
C2756
C2757
R4062
2
1 2
2
0_0603_5%
2 2 2 R4116 +5V_CC
1 2 PPC_FW_ID CCG4_MASTER_SDA_R R4118 1 @ 2 0_0402_5% CCG4_MASTER_SDA
+3VALW CCG4_MASTER_SDA <26,46,47,48,100>
10K_0402_5%
R4046
.1U_0402_16V7K
1 2 +1.8V_CCG4 CCG4_MASTER_SCL_R R4119 1 @ 2 0_0402_5% CCG4_MASTER_SCL
1 CCG4_MASTER_SCL <26,46,47,48,100>
C2752
0_0603_5%
D D
2
.1U_0402_16V7K
.1U_0402_16V7K
1U_0201_6.3V6M
1 1 1
+1.8V_CCG4
C2767
C2765
C2766
2 2 2 U2624
to NV GPU
1
+1.8VALW +1.8V_CCG4
2.2K_0402_5%
R4068
2.2K_0402_5%
R4069
20 5
VDDD V5V
RG2993 21 6 NV_CC1_R R4123 1 @ 2 0_0402_5% NV_CC1
1 2 VDDIO CC1
C2768 1 2 .1U_0402_16V7K CCG4_VCCD_SUPPLY 22 4 NV_CC2_R R4124 1 @ 2 0_0402_5% NV_CC2
2
0_0603_5% VCCD CC2
390P_0402_50V8K
390P_0402_50V8K
1 1
NV_VBUS_PWR_EN 24 9 NV_MASTER_SDA NV_MASTER_SDA
C2770
C2771
<100> NV_VBUS_PWR_EN P1.1/GPIO/SWD_DATA P0.0/SCB0_I2C_SDA NV_MASTER_SDA <26>
1 10 NV_MASTER_SCL
PS_VBUS_ALT R4121 1 @ 2 0_0402_5% PS_VBUS_ALT_R P1.2/GPIO/SWD_CLK P0.1/SCB0_I2C_SCL 2 2 NV_MASTER_SCL
<100> PS_VBUS_ALT CCG4_MASTER_SDA_R NV_MASTER_SCL <26>
16
P3.2/SCB3_I2C_SDA
NV_VBUS_MON 2 17 CCG4_MASTER_SCL_R
+3V_CCG4 +NV_VBUS USB_AUX_SW_V1

P1.3/GPIO P3.3/SCB3_I2C_SCL
+3VS
HPD +NV_VBUS_CONN
3
T373 @ P1.5/GPIO CCG4_HOTPLUG_DET
11
1C
1
PPC_FW_ID 8 P2.3/HPD
P1.7/GPIO 12 PPC_VDDD_A +1.8VSDGPU_AON +1.8VS
@ T374 ANX_PWR_EN <58>
1
NV_VBUS_FET_EN 14 P2.5/VBUS_DISCHARGE R4041 330_0402_1%
2
P2.6/GPIO R4115
1
R4071 R4065 13 PPC_DVDD_IO_13 10K_0402_5%
@ T375
2
348K_0402_1% NV_USB_RESET# R4122 1 2 0_0402_5% NV_USB_RESET_R# 7 P3.0/GPIO R390 R4135
4.7K_0402_5%
XRES 15 USB_DSCH_CTL @ 10K_0402_5% 10K_0402_5%
2
P3.1/GPIO @
.1U_0402_16V7K
<16> CCG4_HOTPLUG_DET_3V3
1
R4120 1 2 0_0402_5% 19 18 PPC_I2CS_SCL_18 R4128 1 2 0_0402_5% ANX_PWR_EN

1
2
6
1
GND P3.4/GPIO
C2787
CCG4_XRES NV_VBUS_MON PPC_P36
D
@ 25 23 QV98B 2 Q44
Drain
G
Source
VSS P3.6/GPIO @ T377
PJT138KA 2N SOT363-6 LBSS139WT1G_SC70-3
Gate
S
1
2
.1U_0402_16V7K
.1U_0402_16V7K
1
1
3
1 1 CYPD4126-24LQXIT_QFN24_4X4 R4117
CCG4_HOTPLUG_DET
D
5
C2772
C2769
R4064 100K_0402_5% QV98A G
3
49.9K_0402_1% SA0000C9C00 PJT138KA 2N SOT363-6 S
USB_DSCH_CTL
4
C C
1
2 2 S IC CYPD4136-24LQXQT QFN 24P USB TYPE-C CTRL
2
R398
use CYPD4136 P/N, Symbol/Footprint use CYPD4126 <25> GPU_DP5_HPD# 100K_0402_5%
2
+1.8V_CCG4
+1.8V_CCG4 R4089 1 2 0_0402_5% USB3_RT_POWER_EN <46>
C2780
1 2 C2781
1 2
R4090 1 2 0_0402_5% DP_USB_MUX_POWER_EN <47> default use NV design +NV_VBUS +NV_VBUS_CONN
.1U_0402_16V7K D58 QV99A QV99B

5
.1U_0402_16V7K R4091 1 2 0_0402_5% 2 1 EMF20B02V_EDFN3X3-8 EMF20B02V_EDFN3X3-8

USB3O2_MUX_PWR_EN <48>
5
6 1 3 5
D
VCC
D
PLT_RST_BUF# 1 6 5
S
1
VCC
<16,25,43,51,52,68> PLT_RST_BUF#
1
IN B NV_USB_RESET#
0.33U_0402_10V6K
C2782
4 1 RB751S40T1G_SOD523-2
OUT Y IN B ANX_PWR_EN QV100
8.87K_0402_1%
R4114
2 4
GND
IN A OUT Y NV_VBUS_FET_EN
G
2 2
G
GND
IN A 2 Gate
4
1
R4087 R4088 1 USB_FET_EN_R#
1
3
1
Drain
100K_0402_5%
RV931
0.1U_0402_25V6
CV971
U2627 100K_0402_1% 100K_0402_1%
3
NL17SZ08DFT2G_SC70-5
200K_0402_1%
RV929
U2628 3
2
NL17SZ08DFT2G_SC70-5 Source
R4092 1 2 0_0402_5% LBSS139WT1G_SC70-3 2
2
1
14K_0402_1%
1
R4113
D59
RB751S40T1G_SOD523-2 1 RV930 2
2
49.9K_0402_1%
2
USB3O2_MUX_RESET_N <48> +NV_VBUS_CONN
1
+NV_VBUS_CONN
1U_0201_6.3V6M
C2783
3
B 1 1 1 B
2
0.1U_0402_25V6
C23
10U_0603_25V6M
C24
10U_0603_25V6M
C2774
DS19 EMC@
L30ESD24VC3-2_SOT23-3
2 2 2
+5VALW +5V_CC
Raptor: for HV protect +NV_VBUS_CONN
US2
+NV_VBUS
@
1
6 1 US15
IN OUT
1
RS116 1 2 100K_0402_5% 5 2 6 1 JUSB2
SET GND IN OUT
150U_D2_6.3VY_R15M
CS90 1 A1 B12
GND GND
.1U_0402_16V7K
0.1U_0402_25V6
22U_0805_25V6M
RS126 1 2 1K_0402_5% 4 3 22U_0805_25V6M CS105 0.22U_0402_16V7K CS114 0.33U_0402_10V6K

+3VALW .1U_0402_16V7K 1 1 1 1
EN(/EN) FLAG 2
CS95
CS96
CS97 @
CS98
+ RSET 5 2 CS99 UTC_A2_SSTXp1 1 2 UTC_A2_SSTXp1_C A2 B11 UTC_B11_SSRXp1_C 1 2 UTC_B11_SSRXp1

SET GND <47> UTC_A2_SSTXp1 UTC_A3_SSTXn1 UTC_A3_SSTXn1_C SSTXp1 SSRXp1 UTC_B11_SSRXp1 <47>
<47> UTC_A3_SSTXn1
1 2 A3 B10 UTC_B10_SSRXn1_C 1 2 UTC_B10_SSRXn1
SSTXn1 SSRXn1 UTC_B10_SSRXn1 <47>
1 G527ATP1U_TSOT23-6 CS106 0.22U_0402_16V7K
@ 2 2 NV_VBUS_FET_EN 4 3 2 2 2 A4 B9 CS115 0.33U_0402_10V6K
CS101 EN FLAG VBUS VBUS
2.2U_0402_6.3V6M SY6861B1ABC_TSOT23-6 NV_CC1 A5 B8 UTC_B8_SBU2_AUX
1
2 CC1 SBU2 UTC_B8_SBU2_AUX <47>

RS131 UTC_A6 RS127 1 2 0_0201_5% UTC_A6_R A6 B7 UTC_B7_R RS129 1 2 0_0201_5% UTC_B7
<48> UTC_A6 UTC_A7 UTC_A7_R Dp1 Dn2 UTC_B6_R UTC_B6 UTC_B7 <48>
100K_0402_5% <48> UTC_A7 RS128 1 2 0_0201_5% A7 B6 RS130 1 2 0_0201_5% UTC_B6 <48>
@ Dn1 Dp2
R101 1 2 0_0402_5% UTC_A8_SBU1_AUX A8 B5 NV_CC2
2
<58> EC_TYPEC_EN_S <47> UTC_A8_SBU1_AUX SBU1 CC2

@
A9 B4
RSET CS104 0.33U_0402_10V6K VBUS VBUS CS112 0.22U_0402_16V7K
UTC_A10_SSRXn2 1 2 UTC_A10_SSRXn2_C A10 B3 UTC_B3_SSTXn2_C 1 2 UTC_B3_SSTXn2
<47> UTC_A10_SSRXn2 UTC_A11_SSRXp2 UTC_A11_SSRXp2_C SSRXn2 SSTXn2 UTC_B2_SSTXp2_C UTC_B2_SSTXp2 UTC_B3_SSTXn2 <47>
1 2 A11 B2 1 2
<47> UTC_A11_SSRXp2 UTC_B2_SSTXp2 <47>
1
EMC@ D47 EMC@ D57 SSRXp2 SSTXp2 CS111 0.22U_0402_16V7K

RS117 RS119 RS118 CS113 0.33U_0402_10V6K A12 B1
6.2K_0402_5% 8.2K_0402_5% 4.3K_0402_5% UTC_A2_SSTXp1_C 1 10 UTC_A2_SSTXp1_C UTC_A6 1 10 UTC_A6 GND GND
@ @ @ 9 UTC_A3_SSTXn1_C 9 UTC_A7
UTC_A3_SSTXn1_C 2 7 UTC_A10_SSRXn2_C UTC_A7 2 7 UTC_B7 1 4
2
3 2
6 UTC_A11_SSRXp2_C 6 UTC_B6 2 GND GND 5

D 3 GND GND 6
5 UTC_A10_SSRXn2_C GND GND UTC_B11_SSRXp1_C
TYPEC_3A <18,45> UTC_A10_SSRXn2_C UTC_B7 UTC_A11_SSRXp2_C UTC_B10_SSRXn1_C
G 4 8 4 8
3 3 SIMUL_MJ8E0B-T280-422
S QS9B UTC_A11_SSRXp2_C 5 UTC_B6 5
SIMUL_MJ8E0B-T280-422_24P-T
4
6
D 2N7002KDW_SOT363-6
@
1
1
A 2 CONN@ A
TYPEC_1P5A <16,45>
G PUSB3FR4_DFN2510A10-10 PUSB3FR4_DFN2510A10-10 RS122 RS123 RS124 RS125
checked bios SCA00003W00 SCA00003W00 220K_0402_5% 220K_0402_5% 220K_0402_5% 220K_0402_5%
S QS9A H42 H45 H41 H43 H46 H44
1
2N7002KDW_SOT363-6 H_2P5X1P0 H_2P5X1P0 H_2P5X1P0 H_2P5X1P0 H_2P5X1P0 H_2P5X1P0

@
2
2
EMC@ D48
EMC@ D49
UTC_B11_SSRXp1_C 1 10 UTC_B11_SSRXp1_C UTC_A8_SBU1_AUX 6 3 NV_CC1
1
9 UTC_B10_SSRXn1_C I/O4 I/O2
G518 MOS Current Limit UTC_B10_SSRXn1_C UTC_B3_SSTXn2_C
2 7
GPP_B1 GPP_B4 6 UTC_B2_SSTXp2_C +5VALW @ @ @ @ @ @
RSET(kΩ) MODE limit point
(TYPEC_1P5A) (TYPEC_3A) 5 2
VDD GND
L L 6.2 0.9A 1.09A UTC_B3_SSTXn2_C 4 8
3
2017/11/23
Compal Secret Data
2017/12/31 Title
L H 3.53 1.5A 1.92A UTC_B2_SSTXp2_C UTC_B8_SBU2_AUX NV_CC2 Issued Date Deciphered Date
5 4 1
H L 2.54 2A 2.67A
I/O3 I/O1
NV USB-C CCG4+USB TYPE C
AZC099-04SP.R7G_SOT23-6 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
*H H 1.94 3A 3.5A PUSB3FR4_DFN2510A10-10 SC300003S00 Custom 0.1
SCA00003W00
5 4 3 2 1
A B C D E
1 1
2 2
Reserve Page
3 3
4 4
2017/11/23
Compal Secret Data
2018/09/01 Title
Reserve Page
A B C D E
5 4 3 2 1
+3VALW
1 1
CL118 CL117
4.7U_0402_6.3V6M
0.1U_0402_16V7K
2 2 +3VALW_LAN
UL14
5 1
IN OUT
22U_0603_6.3V6M
CL120
2 1
GND
4 3 1 2
<58> LAN_PWR_EN EN OC +3VS
RL69
SY6288C20AAC_SOT23-5 10K_0402_5% 2
1
CL119
0.1U_0402_16V7K
D 2 D
EVT BOM changed to SY6288C20 (high active)
UL1
+DVDD3318 +3VALW_LAN
PCIE_PRX_DTX_P14 PCIE_PRX_C_DTX_P14 +DVDD09
3
.
3
V
RL17 1 @ 2 0_0402_5% +VDD18_LAN <17> PCIE_PRX_DTX_P14
CL1 2 1 0.1U_0402_16V7K 57
HSOP DVDD09_1
33 +3VALW_LAN
PCIE_PRX_DTX_N14 CL2 2 1 0.1U_0402_16V7K PCIE_PRX_C_DTX_N14 56 44
<17> PCIE_PRX_DTX_N14 HSON DVDD09_2
RL16 1 @ 2 0_0402_5% 50
CL42 1 CL41 1 PCIE_PTX_DRX_P14 CL39 2 1 0.1U_0402_16V7K PCIE_PTX_C_DRX_P14 61 DVDD09_3 51 +AVDD33 RL30 1 @ 2
<17> PCIE_PTX_DRX_P14 PCIE_PTX_DRX_N14 PCIE_PTX_C_DRX_N14 HSIP DVDD09_4
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
CL40 2 1 0.1U_0402_16V7K 62 72 CL123 CL122 CL121 CL43 CL44

<17> PCIE_PTX_DRX_N14 HSIN DVDD09_5 73 0_0603_5%
DVDD09_6 1 1 1 1 1
58
2 2 Close to DVDD3318 <15> CLK_PCIE_LAN REFCLK_P +DVDD18
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
59 35
pin41, 46 <15> CLK_PCIE_LAN#
PLT_RST_BUF# 45
REFCLK_N DVDD18_1
DVDD18_2
52
70
Power Sequence for measurement 2 2 2 2 2 2 10uF close to AVDD33
<16,25,43,49,52,68> PLT_RST_BUF# PERSTB DVDD18_3
<15> LAN_CLKREQ#
42
CLKREQB pin 4, 12, 20, 28, 84
34 +DVDD33
RL11 1 2 2.49K_0402_1% 82 DVDD33_1 71 +3VALW Rising time (10%~90%)>0.5mS, <100mS
RSET DVDD33_2
+VDD25 Rising time (10%~90%)>0.5mS, <100mS
41 +DVDD3318
+3VALW_LAN DVDD3318_1 46 +VDD18 Rising time (10%~90%)>0.5mS, <100mS
LAN_PME# DVDD3318_2
<16,58> EC_PME# RL10
1 @ 2
0_0402_5% ISOLATE#
43
49 LANWAKEB 1 +AVDD09
+VDD09 Rising time (10%~90%)>0.5mS, <100mS
RL15 1 @ 2 4.7K_0402_5% POW_MODE1 1 2 ISOLATEB AVDD09_1 7
+3VALW_LAN AVDD09_2
RL1 4.7K_0402_5%~D 17 +DVDD33 RL44 1 @ 2
RL4 1 2 4.7K_0402_5% CKXTAL1 RL12 1 2 0_0402_5% CKXTAL1_R 79 AVDD09_3 23
CKXTAL2 RL13 1 2 1K_0402_5% CKXTAL2_R 78 CKXTAL1 AVDD09_4 80 The power sequence : CL45 1 CL46 1 0_0603_5%
CKXTAL2 AVDD09_5
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
TP@ PAD~D T360 76
CK25_XTAL 3 +AVDD18 +3VALW>+VDD25>+VDD18>+VDD09
AVDD18_1 5 Close to DVDD33
AVDD18_2 2 2
LAN_ACTIVITY# 31 AVDD18_3
19
21
pin34, 71
TP@ PAD~D T364
LAN_SPISCK LED0/GPIO2 AVDD18_4
+DVDD3318 TP@ PAD~D T365 32
LED1/EESK/SPISCK/GPIO3 AVDD18_5
81
TP@ PAD~D T370 LAN_SPICS# 37
C TP@ PAD~D T366 LAN_SPISO 38 SPICSB/GPIO5 C
RL5 1 2 4.7K_0402_5% LAN_GPI TP@ PAD~D T367 LAN_SPISI 39 LED2/EEDO/SPISO/GPIO6 2 CL90 1 2 1U_0201_6.3V6M
TP@ PAD~D T371 LAN_GPIO8 40 LED3/EEDI/SPISI/GPIO7 AVDD18_LDO_OUT_1 6 CL91 1 2 1U_0201_6.3V6M
RL6 1 2 4.7K_0402_5% LAN_PME# GPIO8 AVDD18_LDO_OUT_2 11 CL92 1 2 1U_0201_6.3V6M
LAN power Noise for measurement AVDD18_LDO_OUT_3
2
.
5
V
AVDD18_LDO_OUT_4
13 CL93 1 2 1U_0201_6.3V6M +VDD25_LAN
@ RL58 1 2 10K_0402_5% LAN_CLKREQ# 18 CL94 1 2 1U_0201_6.3V6M
LAN_MDIP0 87 AVDD18_LDO_OUT_5 22 CL95 1 2 1U_0201_6.3V6M
@ RL8 1 2 4.7K_0402_5% PLT_RST_BUF# LAN_MDIN0 88 MDIP0 AVDD18_LDO_OUT_6 27 CL96 1 2 1U_0201_6.3V6M +AVDD25 RL45 1 @ 2
+3VALW < 30mV (Vpeak to Vpeak) LAN_MDIP1 8 MDIN0 AVDD18_LDO_OUT_7 77 CL97 1 2 1U_0201_6.3V6M CL47 CL48 CL49 CL50 CL51
LAN_MDIN1 MDIP1 AVDD18_LDO_OUT_8
+3VS
+VDD25 < 30mV (Vpeak to Vpeak) LAN_MDIP2
9
15 MDIN1 AVDD18_LDO_OUT_9
85 CL98 1 2 1U_0201_6.3V6M 1 1 1 1 1 0_0603_5%
+VDD18 < 30mV (Vpeak to Vpeak) LAN_MDIN2 MDIP2 +AVDD25
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
16 10
LAN_MDIP3 24 MDIN2 AVDD25_1 14
RL9 1 2 1K_0402_5% ISOLATE# +VDD09 < 30mV (Vpeak to Vpeak) LAN_MDIN3 25 MDIP3 AVDD25_2 26 2 2 2 2 2 Close to AVDD25
MDIN3 AVDD25_3
RL62 1 2 15K_0402_5%
AVDD25_4
83
86
pin10, 14, 26, 83, 86
RL14 1 2 4.7K_0402_1% 69 AVDD25_5
POW_MODE1 68 SCANM 4 +AVDD33
LAN_PWR_EXT_SWR POW_MODE1 AVDD33_1
+3VALW_LAN <101> LAN_PWR_EXT_SWR
67
POW_EXT_SWR AVDD33_2
12
20
TP@ PAD~D T361 LAN_GPI 48 AVDD33_3 28
RL52 1 @ 2 10K_0402_5% LAN_GPIO0 TP@ PAD~D T368 LAN_GPIO0 29 GPI AVDD33_4 84
RL51 1 @ 2 10K_0402_5% TP@ PAD~D T369 LAN_GPIO1 30 GPIO0/PPS_PIN AVDD33_5
TP@ PAD~D T362 LAN_GPIO4 36 GPIO1 53 +EVDD18 +DVDD25_UPS RL46 1 @ 2
GPIO4/EECS/SCL EVDD18
47 54 +EVDD09 CL52 1 CL53 1 0_0603_5%
NC1 EVDD09_1
0.1U_0402_16V7K~D
+3VALW_LAN 74
NC2 EVDD09_2
55
10U_0402_6.3V6M
75 63
NC3 EVDD09_3 Close to DVDD25_UPS
RL54 1 @ 2 10K_0402_5% LAN_GPIO1 60 66 +DVDD25_UPS 2 2
pin66
RL53 1 @ 2 10K_0402_5% 89 GND1 DVDD25_UPS 65 +DVDD18_UPS
GND2 DVDD18_UPS 64 CL99 1 2 1U_0201_6.3V6M
DVDD09_UPS
RTL8125-CG_QFN88_10X10
+VDD18_LAN
S IC E3000-CG QFN 88P E-LAN CTRL
YL2
I/O PADS 3.3V IO 1.8V IO SA0000CAO10 +AVDD18
1
.
8
V
25MHZ_20PF_XRCGB25M000F2P18R0 RL47 1 @ 2
CL54 CL55 CL56 CL57 CL58
CKXTAL1 3 1 CKXTAL2 ISOLATEB RL1, RL4 connect RL1, RL4 NC 1 1 1 1 1 0_0603_5%
3 1
NC NC CLKREQB RL2, RL3 NC RL2, RL3 connect use RTL8125 symbol, HW same design
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
CL3 CL4 LANWAKEB
18P_0402_50V8J 4 2 18P_0402_50V8J PERSTB 2 2 2 2 2 Close to AVDD18
GPI pin3, 5, 19, 21, 81
GPIO8
P/N: SJ10000UP00 (S CRYSTAL 25MHZ 10PF XRCGB25M000F2P34R0)
0
.
9
V
B B
+VDD09_LAN
+DVDD18 RL48 1 @ 2
+AVDD09 RL38 1 @ 2 CL59 1 CL60 1 CL61 1 0_0603_5%
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
CL66 CL67 CL68 CL69 CL70
Raptor: change to follow 2018 VX SJ10000UP00 1 1 1 1 1 0_0603_5%
Close to DVDD18
2 2 2
pin35, 52, 70
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
2 2 2 2 2 Close to AVDD09
pin1, 7, 17, 23, 80
JRJ45
+VDD25_LAN
0727 FAE Whiter suggest reserve
+EVDD18 RL50 1 @ 2
RJ45_MDIN3 8
RL70 1 2 0_0402_5% PR4- +DVDD09 RL39 1 @ 2 CL62 1 CL63 1 0_0603_5%
UL2 RJ45_MDIP3
0.1U_0402_16V7K~D
10U_0402_6.3V6M
7
1 24 RJ45_CT3 1 2 PR4+ CL72 CL71 2 CL73 2 CL74 2 CL75 2 CL76 2 0_0603_5%
TDCT1 TXCT 2
RL18 75_0402_1%~D RJ45_MDIN1 6
LAN_MDIN3 2 23 RJ45_MDIN3 PR2- Close to EVDD18 2 2
TD1+ TX1+ RJ45_MDIN2 Close to DVDD09 pin53
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
5
LAN_MDIP3 RJ45_MDIP3 PR3- 1 1 1 1 1 1
3
TD1- TX1-
22
RJ45_MDIP2 4
pin33, 44, 50, 51, 72, 73
4 21 RJ45_CT2 RL63 1 2 75_0402_1%~D PR3+
TDCT2 TXCT2 RJ45_MDIP1 3
LAN_MDIN2 5 20 RJ45_MDIN2 PR2+
TD2+ TX2+ RJ45_MDIN0 2
LAN_MDIP2 6 19 RJ45_MDIP2 PR1- 10
TD2- TX2- RJ45_MDIP0 1 SHLD2 9 +DVDD18_UPS RL49 1 @ 2
7 18 RJ45_CT1 RL61 1 2 75_0402_1%~D PR1+ SHLD1
TDCT3 TXCT3 CL64 1 CL65 1 0_0603_5%
LAN_MDIN1 RJ45_MDIN1 +EVDD09
0.1U_0402_16V7K~D
10U_0402_6.3V6M
8 17 RL40 1 @ 2
TD3+ TX3+
LAN_MDIP1 9 16 RJ45_MDIP1 CL77 1 CL78 1 CL79 1 CL80 1 CL81 1 CL82 1 0_0603_5% Close to DVDD18_UPS
TD3- TX3- 2 2
pin65
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
SANTA_130452-0E1
10 15 RJ45_CT0 RL64 1 2 75_0402_1%~D RJ45_GND
TDCT4 TXCT4 CONN@ Place 0.1uF x 2 close to each
LAN_MDIN0 11
TD4+ TX4+
14 RJ45_MDIN0 DC234006L00 2 2 2 2 2 2
pin54, 55, 63
LAN_MDIP0 12 13 RJ45_MDIP0
TD4- TX4-
RJ45_GND 1 2 LANGND
A BOTH_QVP2014R C67 A
SP050009L00 10P_0402_50V8J
40mil
EVT SP050009K00
DVT SP050009L00 LANGND
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
1
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
@
J5 EMC@ JP1
JUMP_43X118 XEMC@
B88069X9231T203_4P5X3P2-2
2
1 1 1 1 1 1 1 1 D1
AZ5125-02S.R7G_SOT23-3
1
SCA00001A00
2 2 2 2 2 2 2 2
CL9
EMC@ CL110
EMC@ CL111
EMC@ CL112
EMC@ CL113
EMC@ CL114
EMC@ CL115
EMC@ CL116

EMC@
LAN Killer E3000
5 4 3 2 1
A B C D E
Wireless LAN
+3VALW W=60mils +3VS_W LAN
UM1
1U_0201_6.3V6M
CM15
5 1
IN OUT
1
2
@ GND
1 1
4 3
2 <58> W LAN_ON EN OC
SY6288C20AAC_SOT23-5
CNVI@
+3VALW +3VS_W LAN
RM55 1 @ 2 0_0805_5% NGFF WL+BT (KEY E)

+3VS
RM11 1 @ 2 0_0805_5% UART_2_PRXD_R_DTXD RM42 1 UART@ 2 0_0402_5%

UART_2_PTXD_R_DRXD UART_2_PRXD_DTXD <19>
1 1 1 RM43 1 UART@ 2 0_0402_5%
UART_2_PTXD_DRXD <19>
CM12 @ CM13
60mil 4.7U_0402_6.3V6M 0.1U_0201_10V6K CM14 Co-layout with CNVi PH +3VS at SOC side,
0.1U_0201_10V6K for win7 USB3 debug
2 2 2
KEY E +3VS_W LAN
JNGFF1
1 2
USB20_P14 GND_1 3.3VAUX_2 CNVI@
3 4 1 RM41 2
<14> USB20_P14 USB20_N14 USB_D+ 3.3VAUX_4
USB2 Port.14 5 6 @ T52 75K_0402_1%
<14> USB20_N14 USB_D- LED1#
7 8
(For BT) RM22 1 2 0_0201_5% CNV_PRX_R_DTX_N1 9 GND_7 PCM_CLK 10 CNV_RF_RESET#_R RM34 1 2 0_0201_5%
<15> CNV_PRX_DTX_N1 SDIO_CLK PCM_SYNC CNV_RF_RESET# <18>
2
<15> CNV_PRX_DTX_P1 RM23 1 2 0_0201_5% CNV_PRX_R_DTX_P1 11 12 2
13 SDIO_CMD PCM_OUT 14 CLKREQ_CNV#_R RM35 1 2 0_0201_5% 1017 RF intel recommned
SDIO_DAT0 PCM_IN CLKREQ_CNV# <18>
<15> CNV_PRX_DTX_N0 RM24 1 2 0_0201_5% CNV_PRX_R_DTX_N0 15 16 @ T53 reserve
RM25 1 2 0_0201_5% CNV_PRX_R_DTX_P0 17 SDIO_DAT1 LED2# 18 RM57 1 @ 2 71.5K_0402_1%
<15> CNV_PRX_DTX_P0 SDIO_DAT2 GND_18
19 20
RM26 1 2 0_0201_5% CLK_CNV_PRX_R_DTX_N 21 SDIO_DAT3 UART_WAKE 22 UART_2_PRXD_R_DTXD RM36 1 CNVI@ 2 0_0402_5%
<15> CLK_CNV_PRX_DTX_N SDIO_WAKE UART_TX CNV_BRI_PRX_DTX <15>
RM27 1 2 0_0201_5% CLK_CNV_PRX_R_DTX_P 23
<15> CLK_CNV_PRX_DTX_P SDIO_RST
24 UART_2_PTXD_R_DRXD RM37 1 CNVI@ 2 0_0402_5%
UART_RX CNV_RGI_PRX_R_DTX CNV_RGI_PTX_DRX <15>
25 26 RM38 1 2 0_0201_5%
PCIE_PTX_C_DRX_P15 GND_33 UART_RTS CNV_BRI_PTX_R_DRX CNV_RGI_PRX_DTX <15>
CM18 2 1 0.1U_0402_16V7K 27 28 RM39 1 2 0_0201_5% CNV_BRI_PTX_DRX <15>
<17> PCIE_PTX_DRX_P15 PCIE_PTX_C_DRX_N15 PET_RX_P0 UART_CTS E51TXD_P80DATA_R
CM19 2 1 0.1U_0402_16V7K 29 30 RM12 2 @ 1 0_0402_5%
<17> PCIE_PTX_DRX_N15 PET_RX_N0 CLink_RST E51RXD_P80CLK_R E51TXD_P80DATA <58>
31 32 RM13 2 @ 1 0_0402_5%
PCIE_PRX_DTX_P15 GND_39 CLink_DATA E51RXD_P80CLK <58>
(link to PICE Port 3) <17> PCIE_PRX_DTX_P15 33 34
PCIE_PRX_DTX_N15 35 PER_TX_P0 CLink_CLK 36
PCIE X1 <17> PCIE_PRX_DTX_N15 PER_TX_N0 COEX3
37 38
CLK_PCIE_W LAN 39 GND_45 COEX2 40
<15> CLK_PCIE_W LAN CLK_PCIE_W LAN# REFCLK_P0 COEX1 SUSCLK_R
41 42 RM14 1 @ 2 0_0402_5%
<15> CLK_PCIE_W LAN# REFCLK_N0 SUSCLK(32KHz) W L_RST#_R SUSCLK <18,68>
(From PCH CLKOUT2) 43 44 RM15 1 @ 2 0_0402_5%
W LAN_CLKREQ# GND_51 PERST0# BT_ON PLT_RST_BUF# <16,25,43,49,51,68>
PCIE CLK <15> W LAN_CLKREQ# 45 46
W LAN_PME# CLKREQ0# W_DISABLE2# W L_OFF# BT_ON <58>
47 48
<58> W LAN_PME# PEWAKE0# W_DISABLE1# W L_OFF# <58>
49 50
RM28 1 2 0_0201_5% CNV_PTX_R_DRX_N1 51 GND_57 I2C_DAT 52
<15> CNV_PTX_DRX_N1 RSVD/PCIE_RX_P1 I2C_CLK
RM29 1 2 0_0201_5% CNV_PTX_R_DRX_P1 53 54 RM40 0_0201_5%
<15> CNV_PTX_DRX_P1 RSVD/PCIE_RX_N1 I2C_IRQ REFCLK_CNV_R
55 56 1 2 REFCLK_CNV <15>
RM30 1 2 0_0201_5% CNV_PTX_R_DRX_N0 57 GND_63 RSVD_64 58
<15> CNV_PTX_DRX_N0 RSVD/PCIE_TX_P1 RSVD_66 For CNVi Feature
RM31 1 2 0_0201_5% CNV_PTX_R_DRX_P0 59 60
<15> CNV_PTX_DRX_P0 RSVD/PCIE_TX_N1 RSVD_68
61 62 1 XEMC@
RM32 1 2 0_0201_5% CLK_CNV_PTX_R_DRX_N 63 GND_69 RSVD_70 64 CM17
3 <15> CLK_CNV_PTX_DRX_N RSVD_71 3.3VAUX_72 3
RM33 1 2 0_0201_5% CLK_CNV_PTX_R_DRX_P 65 66 0.1U_0201_10V6K
<15> CLK_CNV_PTX_DRX_P RSVD_73 3.3VAUX_74
67 For ESD req reserve LC filter
GND_75 68 2
69 GND1 close PCH
GND2
BELLW _80152-3221
CONN@ E51TXD_P80DATA_R
SP070013E00
1
RM19
2 1 W LAN_PME#
Connector follow 2018V-VX 100K_0402_5%
+3VS_W LAN
RM16 10K_0402_5%
2
2 1 BT_ON
RM56 10K_0402_5%
4 4

WLAN M.2
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4
2017/11/23
Compal Secret Data
2018/09/01 Title
Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4
2017/11/23
Compal Secret Data
2018/09/01 Title
Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4
2017/11/23
Compal Secret Data
2018/09/01 Title
Reserve Page
A B C D E
A B C D E
Raptor
+5VS +VDDA
40mil
J18 JSPK1
1 2 299_SPKL+ LA7 1 EMC@ 2 PBY160808T-121Y-N_2P 299_SPK_L+ 1
299_SPKL- LA8 1 EMC@ 2 PBY160808T-121Y-N_2P 299_SPK_L- 2 1
SM01000EJ00 3000ma 220ohm@100mhz 2
+5VS_AVDD JUMP_43X118 LA9 1 EMC@ 2 PBY160808T-121Y-N_2P 1006_SPK_L+ 3
DCR 0.04 +VDDA <57> 1006_SPKL+ 3
2 0.1_0402_1% 1006_SPK_L-_R
22U_0603_6.3V6M
@ LA10 1 EMC@ 2 PBY160808T-121Y-N_2P RA62 1 4
<57> 1006_SPKL- 4
LA2 1 5
<57> 1006_SPK_L+ <57> 1006_SPK_L-_R 5
1 2 1 1 6
<57> 1006_SPK_L- 6
CA82
HCB2012KF-221T30_2P_0805 @ 7
CA65 CA66 8 7
SM01000EJ00 3000ma 220ohm@100mhz 1 1 1 1
2 8
+VDDA +5VS_PVDD
10U_0402_6.3V6M
CA14
.1U_0402_16V7K
CA15
10U_0402_6.3V6M
CA11
.1U_0402_16V7K
CA13
DCR 0.05 680P_0402_50V7K 680P_0402_50V7K 9
LA1 XEMC@ 2 2 XEMC@ 10 GND
1 2 reserve for prevent noise issue GND
HCB2012KF-221T30_2P_0805 2 2 2 2 299_SPKR+ LA3 1 EMC@ 2 PBY160808T-121Y-N_2P 299_SPK_R+ ACES_50278-00801-001
299_SPKR- LA4 1 EMC@ 2 PBY160808T-121Y-N_2P 299_SPK_R- CONN@
1 1 1 1 1 1
1006_SPK_R+
10U_0402_6.3V6M
CA3
.1U_0402_16V7K
CA4
10U_0402_6.3V6M
CA5
.1U_0402_16V7K
CA6
10U_0402_6.3V6M
CA7
.1U_0402_16V7K
CA8
1 LA5 1 EMC@ 2 PBY160808T-121Y-N_2P SP02000HC10 1
<57> 1006_SPKR+ 1006_SPK_R-_R
near Pin40 LA15 1 EMC@ 2 PBY160808T-121Y-N_2P RA61 1 2 0.1_0402_1%
<57> 1006_SPKR-
GNDA <57> 1006_SPK_R+ 1 1 <57> 1006_SPK_R-_R
2 2 2 2 2 2
<57> 1006_SPK_R-
CA63 CA64
+1.8VS_AVDD 680P_0402_50V7K 680P_0402_50V7K
+1.8VS XEMC@ 2 2 XEMC@
near Pin41 near Pin46 1 @ 2
RA56 0_0402_5%
1 1 DA3 DA5
299_SPK_R+ 299_SPK_L+
10U_0402_6.3V6M
CA16
.1U_0402_16V7K
CA17
CA10 1 2 .1U_0402_16V7K 2 2
near Pin18 1 1
CA9 1 2 10U_0402_6.3V6M 3 299_SPK_R- 3 299_SPK_L-
2 2
1 @ 2 +3VS_DVDDIO MESC5V02BD03_SOT23-3 MESC5V02BD03_SOT23-3
+3VS
RA5 0_0402_5% XEMC@ XEMC@
+5VALW +5VS
+3VS_DVDD GNDA DA4 DA6
2 1006_SPK_R+ 2 1006_SPK_L+
1 @ 2
near Pin20 1 1
+3VS
1
RA1 0_0402_5% 1
10U_0402_6.3V6M
1 3 1006_SPK_R-_R 3 1006_SPK_L-_R
CA1
.1U_0402_16V7K
CA2
10K_0402_5%
10K_0402_5%
RA90
RA95
MESC5V02BD03_SOT23-3 MESC5V02BD03_SOT23-3
@ XEMC@ XEMC@
2 2 Raptor
2
Raptor:vendor suggest
18
41
46
40
20
33
3
near Pin3 UA1 TO eDP cable
DMIC_DATA 2 1 DMIC_DATA_R
DVDD-IO
PVDD1
PVDD2
AVDD1
CPVDD/AVDD2
5VSTB/AUX MODE
DVDD
RA89 0_0402_5% DMIC_DATA_R <38>
CA79 EMC@ RA85 EMC@
330P_0402_50V7K 100_0402_5% PCH_DMIC_DATA0 2 @ 1
<18> PCH_DMIC_DATA0
2 1 2 1 DMIC_CLK RA88 33_0402_5%
LINE1_L 36
LINE1_R 35 LINE1-L(PORT-C-L) PCH_DMIC_CLK0 2 @ 1
+3VS_DVDD LINE1-R(PORT-C-R) <18> PCH_DMIC_CLK0
CA32 EMC@ RA87 33_0402_5%
10P_0402_50V8J
2 299_SPKL- DMIC_CLK DMIC_CLK_R 2
30 43 2 1 2 1
31 MIC2-L(PORT-F-L) /RING2 SPK-OUT-L- 42 299_SPKL+ LA6 EMC@ BLM15PX221SN1D_2P DMIC_CLK_R <38>
MIC2-R(PORT-F-R) /SLEEVE SPK-OUT-L+
4.7K_0402_5%
RA23
4.7K_0402_5%
RA21
SM01000Q500
1
45 299_SPKR+
DMIC_DATA 4 SPK-OUT-R+ 44 299_SPKR-
change PN to SM01000Q500
1 GPIO0/DMIC-DATA12 SPK-OUT-R-
DMIC_CLK 5 GPIO2/DMIC-DATA34
GPIO1/DMIC-CLK 27 HPOUT_L <73>
2
SML1CLK_AUDIO 7 HPOUT-L(PORT-I-L) 26
<57> SML1CLK_AUDIO SML1DATA_AUDIO I2C-CLK HPOUT-R(PORT-I-R) HPOUT_R <73>
6
<57> SML1DATA_AUDIO I2C-DATA HDA_SYNC_R HDA_BIT_CLK_R
15
AUDIOLINK:SYNC
AUDIOLINK:BCLK
14 HDA_BIT_CLK_R HDA_SYNC_R <18>
HDA_BIT_CLK_R <18>
Headphone Out XEMC@ Place near codec.
1
I2S_MCLK 11 17 HDA_SDOUT_R HPOUT_L CA76 1 2 330P_0402_50V7K
I2S_DIN_R 8 I2S-MCLK AUDIOLINK:SDATA-OUT 16 HDA_SDIN0_AUDIO 1 2 HDA_SDOUT_R <18> RA83 EMC@
I2S_LRCK I2S-IN AUDIOLINK:SDATA-IN HDA_SDIN0 <18> HPOUT_R
12 RA17 33_0402_5% 100_0402_5% CA77 1 2 330P_0402_50V7K
I2S_BCLK 10 I2S-LRCK
I2S_DOUT 9 I2S-BCLK 29 XEMC@
+MIC2_VREFO_R
2
I2S-OUT MIC2-VREFO-R 28
MIC2-VREFO-L +MIC2_VREFO_L
1 Reserved by vendor request, 5/9. GNDA
Raptor:289 CA80 1 2 2.2U_0402_6.3V6M 23

CBP LDO1-CAP
39 CA78 EMC@
24 21 330P_0402_50V7K
CBN LDO2-CAP 19 2
MONO_IN
LDO3-CAP MIC-IN +MIC2_VREFO_R
1 2
34 RA15 2.2K_0402_5%
PCBEEP
1
CODEC_VREF
10U_0402_6.3V6M
CA24
10U_0402_6.3V6M
CA25
10U_0402_6.3V6M
CA26
100K_0402_5%
RA18
1 @ 2 38 1 1 1 1 2
+3VS_DVDD VREF +MIC2_VREFO_L
RA75 100K_0402_1% RA16 2.2K_0402_5%
<57> EAPD 13
MUTE# 2 DC-DET/EAPD
PDB 25 CPVEE 2 2 2 LINE1_L CA21 1 2 4.7U_0402_6.3V6M 1 2
2
LINE1_JD1 CPVEE MIC_IN_L <73>
48 RA8 1K_0402_5%
HP/LINE1-JD(JD1) LINE1_R CA22 1
2.2U_0402_6.3V6M
CA28
47 37 1 1 2 4.7U_0402_6.3V6M 1 2
I2S-IN/I2S-OUT-JD(JD2) AVSS1 MIC_IN_R <73>
2.2U_0402_6.3V6M
22 CA81
RA9 1K_0402_5%
32 AVSS2 49
MIC2-CAP Thermal Pad
1 2 2
+3VS_DVDD GNDA GNDA
CA29 ALC299-CG_MQFN48_6X6
Raptor:289 10U_0402_6.3V6M
3 2 SA0000BOS00 GNDA GNDA GNDA JACK Detect +3VS_DVDD 3
1
+3VS_DVDD
GNDA
1
RA91
1
10K_0402_5% RA12
Raptor:ALC289 use 299 symbol, RA73 100K_0402_1%
2
RA6 2 1 10K_0402_5% @ 100K_0402_1%

<58> EC_MUTE#
RA7 2 @ 1 10K_0402_5%
MUTE# <57>
Raptor:289 HPOUT_JD_R
2
<18> HDA_RST#_R LINE1_JD1 2 1 HPOUT_JD_R
2
1
D 200K_0402_1% RA13
1
1
CA20
.1U_0402_16V7K
2 @
G HPOUT_JD <73> 2 1 MIC_JD_R
@ RA4 @S QA2 JD1 100K_0402_1% RA14
3
L2N7002WT1G_SC-70-3 2
10K_0402_5%
HP-JD LINE1-JD
2
1 @ 2
200K 100K
RA76 0_0402_5%
RA19
1K_0402_5% +3VS_DVDD
J19 1 2 BEEP#_R 1 2 MONO_IN
<58> BEEP#
JUMP_43X39
1
1 2 CA30 .1U_0402_16V7K I2S_MCLK RA28 1 2 33_0402_5% I2S_MCLK_R
I2S_MCLK_R <57>
@ 1 2 1 2 RA74
<18,19> PCH_SPKR
1
J20 MIC_JD_R @ 100K_0402_1% I2S_LRCK RA29 1 2 33_0402_5% I2S_LRCK_R

1 I2S_LRCK_R <57>
JUMP_43X39 RA20 CA33
1
1 2 1K_0402_5% RA22 D I2S_BCLK RA30 1 2 33_0402_5% I2S_BCLK_R

I2S_BCLK_R <57>
2
@ 1 2 100P_0402_50V8J 10K_0402_5% 2
J21 2 G MIC_JD <73> I2S_DOUT RA31 1 2 33_0402_5% I2S_DOUT_R
@ I2S_DOUT_R <57>
2
JUMP_43X39 S QA3
3
1 2 @ L2N7002WT1G_SC-70-3 I2S_DIN_R
I2S_DIN_R <57>
@ 1 2
J22 1 1 1 1
22P_0402_50V8J
CA35
22P_0402_50V8J
CA36
22P_0402_50V8J
CA37
22P_0402_50V8J
CA38
JUMP_43X39
1 2 1 @ 2
@ 1 2 RA77 0_0402_5%
J31 2 2 2 2
4 4
XEMC@
XEMC@
XEMC@
XEMC@
JUMP_43X39
1 2
@ 1 2 Close Type = reverse
J30
JUMP_43X39 Open type = bypass*
1 2
@ 1 2 Place Close Codec
J32
JUMP_43X39
1 2
@ 1 2
1 @ 2
0_0402_5% RA86 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Audio Codec_ALC289
GND GNDA MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH78F M/B LA-G161PR01
A B C D E
5 4 3 2 1
For SPK Conn. +5VS
1
J28
2
+5VS_PVDD_AMP
JUMP_43X118
@
UA2
+3VS +3VS_DVDDIO_AMP +1.8VS +1.8VS_AVDD_AMP LDO_1V5_UA2 13 44
+1.8VS_DVDD_AMP DVDD PVDD_R +5VS_PVDD_AMP
D +3VS_DVDDIO_AMP 12 47 D
1 @ 2 1 @ 2 DVDD_IO PGND_R
RA72 0_0402_5% RA71 0_0402_5% 1 1 +1.8VS_AVDD_AMP 17 25
AVDD2 RISENSE-/RVSENSE+ 1006_SPK_R-_R <56>
CA50
10U_0402_6.3V6M
.1U_0402_16V7K
CA49
1 1 1 1
10U_0402_6.3V6M
CA40
.1U_0402_16V7K
CA39
10U_0402_6.3V6M
CA46
.1U_0402_16V7K
CA45
LDO_1V5_UA2 18 SPK R 46
LDO_A1.5 OUT_RN 1006_SPKR- <56> +5VS_PVDD_AMP +5VS_PVDD_AMP
2 2 24
2 2 2 2 3 RISENSE+ 1006_SPK_R- <56>
<56> SML1DATA_AUDIO 4 SDA 26
<56> SML1CLK_AUDIO SCL RVSENSE- 1006_SPK_R+ <56>
45 1006_SPKR+ <56> 1 1 1 1
OUT_RP
CA51
10U_0402_6.3V6M
.1U_0402_16V7K
CA52
CA53
10U_0402_6.3V6M
.1U_0402_16V7K
CA54
I2S_MCLK_R 5
I2S_BCLK_R 6 MCLK 41
BCLK PVDD_L +5VS_PVDD_AMP
I2S_LRCK_R 7 38
I2S_DOUT_R 8 LRCLK PGND_L 2 2 2 2
I2S_DIN 10 DACDAT 22
+1.8VS +1.8VS_DVDD_AMP +3VS_DVDDIO_AMP +5VS_PVDD_AMP 9 SPDIF_OUT/I2S_DATAOUT LISENSE-/LVSENSE+ 1006_SPK_L-_R <56>
SPDIF_IN 39
OUT_LN 1006_SPKL- <56>
1 @ 2 AMP_PD 11
PBD_JD
1
1
RA70 0_0402_5% SPK L 21
LISENSE+ 1006_SPK_L- <56>
RA52 RA58 near Pin43/44 near Pin41/42
10K_0402_5% 10K_0402_5% ASEL1 14 23
30 ASEL LVSENSE- 1006_SPK_L+ <56>
1 @ @ PBTL
GND
.1U_0402_16V7K
CA41
40
1006_SPKL+ <56>
2
2
OUT_LP
Hi:0x26 ASEL1 PBTL 1 2 19

2 CA55 1U_0201_6.3V6M VREF 43
Low:0x24 1 2 2 AVDD1_43 42
+5VS_PVDD_AMP
BYPASS_2 AVDD1_42 +5VS_PVDD_AMP
1
1
close IC CA56 2.2U_0402_6.3V6M
RA53 RA57 1 2 28 1
CA57 2.2U_0402_6.3V6M BYPASS_28 NC_1 27
10K_0402_5% 0_0402_5% NC_27 29 I2S_MCLK_R
NC_29 <56> I2S_MCLK_R
15 37 I2S_BCLK_R
<56> I2S_BCLK_R
2
DVSS NC_37 36 I2S_LRCK_R

NC_36 <56> I2S_LRCK_R I2S_DOUT_R
16 35
AGND_16 NC_35 <56> I2S_DOUT_R I2S_DIN_R I2S_DIN
34 RA32 1 2
C Address Setting Output Mode Selection 20 NC_34 33
<56> I2S_DIN_R
1 33_0402_5% C
AGND_20 NC_33
Low:0x24
22P_0402_50V8J
CA34
Low:BTL NC_32
32
31
NC_31
Hi:PBTL NC_48
48
49 2
E_PAD
XEMC@
2
2
ALC1006-CG_QFN48_6X6
+3VS_DVDDIO_AMP J33 J34 close AMP
2
JUMP_43X39 JUMP_43X39
1
1
RA78
DA1
1
100K_0402_1% @ @
2
<56> EAPD
2
1 AMP_PD
GNDA GND
3
<56> MUTE#
BAT54ATB_SOT-523-3
Raptor:Realtek update the design connect to GND, default J34
B B
A A

Audio Amplifier ALC1006
Custom 0.1
5 4 3 2 1
A B C D E
Board ID
+3VLP_EC
RB4 1 @ 2 47K_0402_5% EC_PME# +3VLP_EC
+3VLP_EC +3VLP_ECA
2
+3VLP LB1
JPB1 FBMA-L11-160808-800LMT_0603 RB1
1 2 1 2 +3VLP_ECA 100K_0402_1%
Prevent EC CLK test mode issue 1 2 Ra
JUMP_43X39
1
0.1U_0201_10V6K
0.1U_0201_10V6K
@ 1 1 1 AD_BID
CB1
CB2
EC_RST# CB3
1
1
1 For Power consumption @ RB2 0.1U_0201_10V6K RB3 @ CB4 1
2 2 2
0.1U_0201_10V6K
1 0_0402_5% 27K_0402_1% Rb 0.1U_0201_10V6K

Measurement
CB10
ECAGND 2
ECAGND <82>
2
2 +3VLP_LPC
111
125
22
33
96
67
Analog Board ID definition,
9
UB1 1C
ESPI Bus Pin : 1~5.7.8.10.12.14 Please see page 3.
0.2
VCC_LPC
VCC
VCC
VCC
VCC
AVCC
VCC0
LPC Bus Pin : 3~5.7.8.10.12.13
For turn off internal LPC module of KB9032 SUSPWRDNACK 1 21 EC_VCCST_PG_R

<18> SUSPWRDNACK CHG_CTL3 GATEA20/GPIO00 EC_VCCST_PG/GPIO0F EC_VCCST_PG_R <10,78>
2 23 BEEP#
<71> CHG_CTL3 TPM_SERIRQ 3 KBRST#/GPIO01 BEEP#/GPIO10 26 FAN_PWM1 BEEP# <56>
XEMC@
1 2 100P_0402_50V8J PLT_RST# <17> TPM_SERIRQ LPC_FRAME# 4 SERIRQ EC_FAN_PWM/GPIO12 27 FAN_PWM2 FAN_PWM1 <77>
CB5 PWM Output
<17> LPC_FRAME# LPC_AD3 LPC_FRAME# AC_OFF/GPIO13 FAN_PWM2 <77>
5 near SOC
<17> LPC_AD3 LPC_AD2 LPC_AD3 PCH_RTCRST# <18>
7
<17> LPC_AD2 LPC_AD2
1
CB6 1 2 100P_0402_50V8J AC_IN LPC_AD1 8 63 BATT_TEMP D
<17> LPC_AD1 LPC_AD0 10 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38 64 CHG_CTL1 BATT_TEMP <82,83> EC_CLR_CMOS 2
LPC & MISC QB6
<17> LPC_AD0 LPC_AD0 VCIN1_BATT_DROP/AD1/GPIO39 65 ADP_I CHG_CTL1 <71>
G L2N7002WT1G_SC-70-3
ADP_I/AD2/GPIO3A ADP_I <82,83>
1
XEMC@ XEMC@ CLK_LPC_R 12 66 AD_BID
AD Input S SB00001GE00
3
2 1 2 1 CLK_LPC_R <17> CLK_LPC_R PLT_RST# 13 CLK_PCI_EC AD_BID/AD3/GPIO3B 75 WLAN_PME# RB26
<16> PLT_RST# EC_RST# PCIRST#/GPIO05 AD4/GPIO42 EC_PME# WLAN_PME# <52>
CB7 RB6 37 76 10K_0402_5%
<77> EC_RST# EC_SCI# EC_RST# AD5/GPIO43 EC_PME# <16,51>
22P_0402_50V8J 33_0402_5% 20
<19> EC_SCI# WLAN_ON EC_SCI#/GPIO0E
38
<52> WLAN_ON
2
CLKRUN#/GPIO1D
68 LAN_PWR_EN
DA0/GPIO3C EC_TP_INT# LAN_PWR_EN <51>
DA Output 70
EN_DFAN1/DA1/GPIO3D VR_PWRGD EC_TP_INT# <16,63>
Raptor: EC suggest NC 55 71
FAN_EN 56 KSI0/GPIO30 DA2/GPIO3E 72 KBL_CTRL
+3VLP_EC <86> FAN_EN KSI1/GPIO31 DA3/GPIO3F KBL_CTRL <63>
57
RB80 0_0402_5% 58 KSI2/GPIO32 83 EC_G_SCL
EC_SMB_CK1 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A EC_G_SDA EC_G_SCL <19> SYS_PWROK_R
RB10 1 2 2.2K_0402_5% 2 @ 1 KSI4 59 84 1 @ 2 SYS_PWROK <18,78>
2 EC_SMB_DA1 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B EC_SMB_CK3 EC_G_SDA <19> 2
RB11 1 2 2.2K_0402_5% KSI5 60 85 RB7 0_0402_5%
KSI5/GPIO35 PSCLK2/GPIO4C EC_SMB_DA3 EC_SMB_CK3 <45,62>
RB81 0_0402_5% KSI6 61 PS2 Interface 86
KSI6/GPIO36 PSDAT2/GPIO4D CHG_EN EC_SMB_DA3 <45,62>
2 @ 1 KSI7 62 87
KSI7/GPIO37 TP_CLK/GPIO4E WL_OFF# CHG_EN <71>
39 88
KSO0/GPIO20 TP_DATA/GPIO4F WL_OFF# <52> +3VS
40
Raptor: EC suggest NC 41 KSO1/GPIO21
42 KSO2/GPIO22 97 ENBKL
TP_LED_EN# KSO3/GPIO23 ENKBL/GPXIOA00 TP_PWR_EN ENBKL <38> GPU_ALERT
43 98 RB9 1 VGA@ 2 10K_0402_5%
<63> TP_LED_EN# TP_LED_PWR_EN 44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 ME_EN TP_PWR_EN <63>
<63> TP_LED_PWR_EN EC_TBT_WAKE# 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH ME_EN <18> GPU_OVERT# RB12 1 VGA@ 2 10K_0402_5%
<43> EC_TBT_WAKE#
46 KSO6/GPIO26 Matrix VCIN0_PH1/GPXIOD00 VCIN0_PH <82>
EC_TYPEC_EN 47 KSO7/GPIO27
<45> EC_TYPEC_EN EC_TYPEC_EN_S KSO8/GPIO28 SPI Device Interface PD_IRQ#
48 119 Raptor: 3V/5V combine solution
<49> EC_TYPEC_EN_S TBT_HRESET KSO9/GPIO29 MISO/GPIO5B BT_ON PD_IRQ# non-FP
<45> +3VLP_EC
49 120
<45> TBT_HRESET KSO10/GPIO2A MOSI/GPIO5C EC_CLR_CMOS BT_ON <52>
50 SPI Flash ROM 126 EC Internal PU
51 KSO11/GPIO2B SPICLK/GPIO58 128 EC_G_INT#
52 KSO12/GPIO2C SPICS#/GPIO5A EC_G_INT# <19> LID_SW# RB13 1 2 100K_0402_1%
53 KSO13/GPIO2D
OVRM_EN RB85 1 2 0_0402_5% OVRM_EN_R 54 KSO14/GPIO2E 73 GPU_ALERT
<22> OVRM_EN KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 GPU_ALERT <25>
ANX_PWR_EN RB84 1 2 0_0402_5% EC_ANX_PWR_EN 81 74 SYS_PWROK_R
<49> ANX_PWR_EN USBKB_EN KSO16/GPIO48 SYS_PWROK/AD7/GPIO41 BATT_4S
Raptor: 3V/5V combine solution 82 89
<63> USBKB_EN KSO17/GPIO49 GPIO50 90 LEDPWR_EN BATT_4S <83>
For abnormal shutdown BATT_CHG_LED#/GPIO52 91 EC_TBT_RESET LEDPWR_EN <62>
For Thermal Portect Shutdown
EC_SMB_CK1 CAPS_LED#/GPIO53 XBOX_USB_EN EC_TBT_RESET <45>
77 GPIO 92
SPOK_3V_5V 1 EC_RSMRST# <82,83> EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CLK1/GPIO44 PWR_LED#/GPIO54 USB_EN XBOX_USB_EN <73>
2 78 93
<82,83> EC_SMB_DA1 EC_SMB_DAT1/GPIO45 BATT_LOW_LED#/GPIO55 USB_EN <73>
DB2 RB751V-40_SOD323-2 79 95 SYSON DB1
<18,25,38,66,73> EC_SMB_CK2 80 EC_SMB_CLK2/GPIO46 SYSON/GPIO56 121 VR_ON SYSON <78,85>
RB751V-40_SOD323-2
<18,25,38,66,73> EC_SMB_DA2 EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 CHG_ILMSEL VR_ON <78,88,89> 3V_EN
127 MAINPWON 1 2
PCH_PWROK DPWROK_EC/GPIO59 CHG_ILMSEL <71> 3V_EN <84>
1 2 PU at CPU side SM Bus 1
DB3 RB751V-40_SOD323-2 RB14
PM_SLP_S3# 6 100 EC_RSMRST# CB8 3V_EN_R 1 2 RB15 1 2
<18,78> PM_SLP_S3# ESPI_RST# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 DGPU_AC_DETECT EC_RSMRST# <18>
Raptor: 3V/5V combine solution 14 101 .1U_0402_16V7K 1M_0402_5%
EC_VCCST_PG_R <17> ESPI_RST# SPOK_3V_5V GPIO07 GPXIOA04 VCIN1_ADP_PROCHOT DGPU_AC_DETECT <19,25,82> 2
1 2 15 102 1K_0402_5%
<84,87> SPOK_3V_5V TP_EN GPIO08 VCIN1_ADP_PROCHOT/GPXIOA05 VCOUT1_PROCHOT VCIN1_ADP_PROCHOT <82> XEMC@
DB4 RB751V-40_SOD323-2 16 103
<63> TP_EN EC_ESB_CLK GPIO0A VCOUT1_PROCHOT#/GPXIOA06
17 104 MAINPWON
<77> EC_ESB_CLK EC_ESB_DAT 18 GPIO0B VCOUT0_MAIN_PWR_ON/GPXIOA07 105 MAINPWON <77,82,84>
3 BKOFF# 3
<77> EC_ESB_DAT AC_PRESENT GPIO0C BKOFF#/GPXIOA08 THERMAL_ALERT# BKOFF# <38>
19 GPIO GPO 106
<18> AC_PRESENT GPU_OVERT# AC_PRESENT/GPIO0D GPXIOA09 3V_EN_R THERMAL_ALERT# <66>
25 107
<25> GPU_OVERT# FAN_SPEED1 PWM2/GPIO11 PCH_PWR_EN/GPXIOA10 PM_SLP_S0#
28 108
VCOUT1_PROCHOT <77> FAN_SPEED1 FAN_SPEED2 FAN_SPEED1/GPIO14 PWR_VCCST_PG/GPXIOA11 PM_SLP_S0# <18>
29
<77> FAN_SPEED2 E51TXD_P80DATA 30 FANFB1/GPIO15
<52> E51TXD_P80DATA EC_TX/GPIO16
2
E51RXD_P80CLK 31 110 AC_IN

<52> E51RXD_P80CLK PCH_PWROK EC_RX/GPIO17 VCIN1_AC_IN/GPXIOD01 EC_ON AC_IN <82,83>
RB19 32 112
<18,78> PCH_PWROK EC_MUTE# PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON <84>
@ 0_0402_5% 34 114 ON/OFFBTN#
<56> EC_MUTE# TS_EN SUSP_LED#/GPIO19 ON/OFF#/GPXIOD03 LID_SW# ON/OFFBTN# <77>
36 GPI 115
<19,38> TS_EN NUM_LED#/GPIO1A LID_SW#/GPXIOD04 116 LID_SW# <66>
SUSP# Raptor: delete VR_HOT2#
SUSP# <39,41,43,68,78,83,85,88>
1
SUSP#/GPXIOD05 117 SW_PROCHOT#

DGPU_AC_DETECT SW_PROCHOT# GPXIOD06 118 EC_PECI 1 2
PBTN_OUT# PECI/GPXIOD07 H_PECI <10,17>
122 RB16 33_0402_1%
<18> PBTN_OUT# PM_SLP_S4# PBTN_OUT#/GPIO5D
@ @ 123 124
<18,78> PM_SLP_S4# PM_SLP_S4#/GPIO5E V18R/VCC_IO2 +3VLP_EC
QB1A QB1B @ RB17
6
AGND
2N7002KDW_SOT363-6 D D 2N7002KDW_SOT363-6 0_0402_5%

GND
GND
GND
GND
GND
VCOUT1_PROCHOT 2 5 VCOUT1_PROCHOT 1 2 VR_HOT#

G G VR_HOT# <89>
KB9022QD_LQFP128_14X14 @ RB18
11
24
35
94
113
ECAGND 69
S S 0_0402_5%
CO-LAY with KB9032QA (SA000080J00) 20mil
1
Raptor: need Check H_PROCHOT# 1 2 SW_PROCHOT#

<10,82,83> H_PROCHOT#
CB9 1 2 BATT_TEMP
100P_0402_50V8J
for marco key 3810 LB2 2 1
FBMA-L11-160808-800LMT_0603
+3VLP_EC
Raptor +5VALW
R426 2 1 4.7K_0402_5% EC_ESB_CLK
EC_ESB_DAT
2015/1/9 acer require: EC_SMB_CK3
R427 2 1 4.7K_0402_5% 4.7K_0402_5% 2 1 R2783
reserved protact circuit when EC_SMB_DA3 4.7K_0402_5% 2 1 R2782
adaptor 107% happen
+3VS
Reserve
4 PD_IRQ# RB82 1 @ 2 10K_0402_5% 4
Raptor: delete VCCSA PGD
+3VLP_EC
PD_IRQ# RB83 1 TBT@ 2 10K_0402_5%
RB76 1 @ 2 0_0402_5% VR_PWRGD

<89> VCCCORE_VR_PWRGD
EC ENE-KB9022
check VR_PWRGD IS AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
AND BY CORE_PWRGD & SA_PWRGD DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4
2017/11/23
Compal Secret Data
2018/09/01 Title
Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4
2017/11/23
Compal Secret Data
2018/09/01 Title
Reserve Page
A B C D E
5 4 3 2 1
2.2K 2.2K
+3VALW_PCH_PRIM
+3VS
2.2K +3VS 2.2K
PCH_SMBCLK D_CK_SCLK
2N7002DW
PCH_SMBDATA D_CK_SDATA SO-DIMM A & B
PCH_SML0CLK 499
+3VALW_PCH_PRIM 2.2K
D
PCH_SML0DATA 499 D
Skylake-H 2.2K +1.8VSDGPU_AON 1.8K 1.8K
PCH 2.2K 2.2K
+3VALW_PCH_PRIM +1.8VSDGPU_AON
+3VSDGPU
2.2K +3VS +1.8VSDGPU_MAIN 1.8K 1.8K
+3VS 2.2K +1.8VSDGPU_MAIN
PCH_SML1CLK EC_SMB_CK2 VGA_SMB_CK2 I2CC_SCL_R I2CC_SCL
2N7002DW PJT138KA PJT138KA

PCH_SML1DATA EC_SMB_DA2 VGA_SMB_DA2 I2CC_SDA_R I2CC_SCL Current Sensor
1.8K
2.2K
+3VLP_EC +1.8VSDGPU_AON
2.2K 1.8K
N17E-G1
EC_SMB_CK1 100 ohm EC_SMB_CK1-1
BATTERY
EC_SMB_DA1 100 ohm EC_SMB_DA1-1 CONN
4.7K
KB9022 0 ohm EC_SMB_CK1_CHGR
0 ohm EC_SMB_DA1_CHGR Charger +3VS
4.7K
EC_SMB_CK2
C EC_SMB_DA2 THERMAL SENSOR USB CC EJ179F C
B B
A A

N17 Sequence
5 4 3 2 1
LED driver +5VALW
UE3
+5V_LEDPWR
2 1 5 1
IN OUT
CE105 2
+5V_LEDPWR
AD3 AD2 AD1 AD0 0.1U_0201_10V6K GND
+5V_LEDPWR 4 3
0 0 0 0 EN OC
1
RE62 SY6288C20AAC_SOT23-5
4.7K_0402_1% 1 <58> LEDPWR_EN
1 @ 2
CE2 RE20 0_0402_5%
UE1 .1U_0402_16V7K
follow ECON
2
24 27 2
RESET Vcc
3 TP_LED_R_DRV#
EC_SMB_CK3 RE102 1 2 0_0402_5% EC_SMB_CK3_LEDPWR 25 OUT0 4 TP_LED_G_DRV# +5VS
Reserve, default bypass

<45,58> EC_SMB_CK3
<45,58> EC_SMB_DA3
EC_SMB_DA3 RE103 1 2 0_0402_5% EC_SMB_DA3_LEDPWR 26 SCL
SDA
OUT1
OUT2
5
6
TP_LED_B_DRV#
FAN1_LED_R_DRV#
T/P
RE3 1 2 4.7K_0402_1%~D AD0 31 OUT3 8 FAN1_LED_G_DRV#
+5V_LEDPWR +5V_LEDPWR RE4
RE5
1
1
2
2
4.7K_0402_1%~D
4.7K_0402_1%
AD1
AD2
32
1
A0
A1
OUT4
OUT5
9
10
FAN1_LED_B_DRV#
LB_LED_R_DRV#
FAN-CPU RE78 1 @ 2 0_0603_5%
FAN-CPU
RE6 1 2 4.7K_0402_1% AD3 2 A2 OUT6 11 LB_LED_G_DRV# JFANBL3
A3 OUT7
OUT8
14 LB_LED_B_DRV# LED/B
1
2.2K_0402_5%
RE60
2.2K_0402_5%
RE61
12 15 PWR_LED_R_DRV#_A# +5V_CPULED 1
13 N.C. OUT9 16 PWR_LED_G_DRV#_A# FAN1_LED_R_DRV#_R 2 1
28 N.C.
N.C.
OUT10
OUT11
17 PWR_LED_B_DRV#_A# PWR LED FAN1_LED_G_DRV#_R 3 2
3 G1
5
5
29 19 BATT_LED_R_DRV#_A# FAN1_LED_B_DRV#_R 4 6
G
@ @ 30 N.C. OUT12 20 BATT_LED_G_DRV#_A# 4 G2

BATT LED
2
N.C. OUT13 21 BATT_LED_B_DRV#_A#
OUT14
1
22 PWRBTN_LED_DRV# ACES_50524-00401-P01
EC_SMB_CK3 3 4 EC_SMB_CK3_LEDPWR RE7 OUT15
SP01001UE00
PWRBTN LED
S
@ 7 23
D
10K_0402_5% GND GND

18 33 CONN@
QE1B GND GND
set RE7 to 10k / output = 1.875mA
2
2N7002KDW_SOT363-6
@ TLC59116FIRHBR_VQFN32_5X5
2
LED/B
G
EC_SMB_DA3 6 1 EC_SMB_DA3_LEDPWR JLED1

S
1
D
QE1A
Raptor: NC for 59116F +5VALW
LB_LED_R_DRV#_A#
2 1
2
3
2N7002KDW_SOT363-6 LB_LED_G_DRV#_A# 4 3
LB_LED_B_DRV#_A# 5 4
@
6 5
7 6
8 7
8
9
1B LED/B 10 GND1
GND2
T/P +5V_LEDPWR
STARC_106A08-001020-A2-R
SP01001PD00
R4019
TP_LED_R_DRV# 1 2 TP_LED_R_DRV#_A#_R <63> +5V_LEDPWR CONN@
1
0_0402_5% RE100 LB_LED_R_DRV#_A#
1
@ 1K_0402_5%
1
R4020 RE101 D
PWRBTN LED
2
TP_LED_G_DRV# 1 2 TP_LED_G_DRV#_A#_R <63> 4.7K_0402_5% LB_LED_R_DRV 2 QE103
@ G AO3418L_SOT23-3
2
0_0402_5% S
3
3
D PWRBTN_LED_DRV# R4034 1 2 100_0402_1% PWRBTN_LED_DRV#_R PWRBTN_LED_DRV#_R <77>
LB_LED_R_DRV# @
5 QE102B
R4125 G 2N7002KDW_SOT363-6
TP_LED_B_DRV# 1 2 TP_LED_B_DRV#_A#_R <63>
S
4
0_0402_5%
@
PWR LED BATT LED
+5VALW +5VALW
LTST-C19HBGEW-C1_RGB
LTST-C19HBGEW-C1_RGB
4
4
LED1 LED2
+5V_LEDPWR
FAN-CPU +5V_LEDPWR
1
RE96 LB_LED_G_DRV#_A# R G B R G B
1
FAN1_LED_R_DRV# R4022 1 2 100_0402_1% FAN1_LED_R_DRV#_R 1K_0402_5%

@
3
FAN1_LED_G_DRV# R4023 1 2 100_0402_1% FAN1_LED_G_DRV#_R RE97 1 D
2
LB_LED_G_DRV 2
PWR_G1
4.7K_0402_5% QE99
PWR_R1
PWR_B1
@
BATT_G1
BATT_R1
FAN1_LED_B_DRV# FAN1_LED_B_DRV#_R
BATT_B1
R4024 1 2 100_0402_1% G AO3418L_SOT23-3
2
S
3
6
D
LB_LED_G_DRV# @
2 QE102A
G 2N7002KDW_SOT363-6
S
1
200_0402_1% R4030 200_0402_1% R4033

@ PWR_LED_R_DRV#_A# PWR_R1 BATT_LED_R_DRV#_A# BATT_R1
2 1 2 1
200_0402_1% R4029 200_0402_1% R4031

PWR_LED_G_DRV#_A# 2 1 PWR_G1 BATT_LED_G_DRV#_A# 2 1 BATT_G1
200_0402_1% R4028 200_0402_1% R4032

PWR_LED_B_DRV#_A# 2 1 PWR_B1 BATT_LED_B_DRV#_A# 2 1 BATT_B1
+5V_LEDPWR
+5V_LEDPWR
1
RE98 LB_LED_B_DRV#_A#
1
1K_0402_5% D45 XEMC@ D46 XEMC@

@ 6 3 PWR_LED_G_DRV#_A# 6 3 BATT_LED_G_DRV#_A#
I/O4 I/O2 I/O4 I/O2
1
RE99 D
2
4.7K_0402_5% LB_LED_B_DRV 2 QE101

@ G AO3418L_SOT23-3
2
S
+5VALW
5 2 +5VALW
5 2
3
VDD GND VDD GND

3
D
LB_LED_B_DRV# 5 @
QE100B
G 2N7002KDW_SOT363-6
PWR_LED_B_DRV#_A# 4 1 PWR_LED_R_DRV#_A# BATT_LED_B_DRV#_A# 4 1 BATT_LED_R_DRV#_A#
S I/O3 I/O1 I/O3 I/O1
4
AZC099-04S.R7G_SOT23-6 AZC099-04S.R7G_SOT23-6
@
@
2
G

6 1 2017/11/23 2018/09/01 Title
Issued Date
S
Deciphered Date
D
QE100A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LEDs(TLC59116F)
2N7002KDW_SOT363-6 Custom 0.1
KB Conn. +5V_KB When RGB are WHITE input current <500mA
+5VALW
6
D44 XEMC@
3 USB20_N10_R
C100 EMC@
.1U_0402_16V7K U12
+5V_KB
W=100mils +5V_KB Raptor
I/O4 I/O2 1 2 5 1 JKB1
W=60mils 1 1 I = 0.5A
1
USB20_N10 1 @ 2 USB20_N10_R IN OUT C437 C101 C102 1 7
<14> USB20_N10 USB20_N10_R 1 G1
R96 0_0402_5% 2 EMC@ 2
5 2 GND @ USB20_P10_R 3 2
22U_0603_6.3V6M
.1U_0402_16V7K
47U_0805_6.3V6M~D
+5V_KB
2
USB20_P10 1 @ 2 USB20_P10_R VDD GND USBKB_EN 4 3 2 2 4 3
<14> USB20_P10 <58> USBKB_EN EN OC KBL_CTRL 4
R97 0_0402_5% 5
<58> KBL_CTRL 5
SY6288C20AAC_SOT23-5 6 8
4 1 USB20_P10_R 6 G2
I/O3 I/O1 SA000079400 ACES_50278-00601-001
AZC099-04S.R7G_SOT23-6
support wake follow SYSON CONN@
SC300001G00 SP020019S00
Touch Pad
+3V_PTP +3V_PTP
1
1
2
RK8 RK9
G
QK1A
2N7002KDW_SOT363-6
2.2K_0402_5% 2.2K_0402_5%
Raptor:for TP LED +3V_PTP
+3V_PTP
2
6 1 I2C_1_SCL_R 2 @ 1
+3VALW
S
<19> I2C_1_SCL
2
+5VALW +5V_TPLED 0_0402_5% RK5
D
1 @ 2 2 @ 1
+3VS
RK12 0_0402_5% RK7 0_0402_5% RK6
10K_0402_5% Raptor
5
+3VALW +3V_PTP @ CK1

G
CK8
1
QK1B UK3 EC_TP_INT# 0.1U_0201_10V6K JTP1
4.7U_0402_6.3V6M
2N7002KDW_SOT363-6 1 2 5 1 2 1 +3V_PTP 1
IN OUT CK3 I2C_1_SCL_R 2 1
1 2
I2C_1_SDA_R
CK9
3 4 2 UK1 I2C_1_SDA_R 3
<19> I2C_1_SDA PCH I2C
S
1U_0201_6.3V6M GND EC_TP_INT# 3
4.7U_0402_6.3V6M
1 2 5 1 4
D
IN OUT <16,58> EC_TP_INT# TP_EN_R# 4

1 2 4 3 1 5
@ 0_0402_5% EN OC 2 5
CK2
RK13 1U_0201_6.3V6M 2 +5V_TPLED 6
SY6288C20AAC_SOT23-5 GND 7 6
4 3 8 7
<58> TP_PWR_EN EN OC 2 TP_LED_R_DRV#_A#_R 8
<62> TP_LED_R_DRV#_A#_R
9
SY6288C20AAC_SOT23-5 TP_LED_G_DRV#_A#_R 10 9 13
<62> TP_LED_G_DRV#_A#_R TP_LED_B_DRV#_A#_R 10GND 14
<62> TP_LED_B_DRV#_A#_R
11
TP_LED_EN_R# 12 11GND
12
<58> TP_LED_PWR_EN TP_PWR_EN follow SYSON behavior
CVILU_CF61122D0R0-05-NH
CONN@
SP010025L00
+5V_TPLED
+3V_PTP
Raptor:waiting more spec for check
2
W=100mils
RK18
10K_0402_5% Default use EC control
1 1
1
1
C859 C857 C858 TP_LED_EN_R#

EMC@
@
22U_0603_6.3V6M
.1U_0402_16V7K
47U_0805_6.3V6M~D
2
2 2 RK14 1 @ 2 0_0402_5% TP_LED_EN_R#

EC <58> TP_LED_EN#
<19> TP_LED_EN_PCH# RK15 1 @ 2 0_0402_5%
+3V_PTP
PCH
2
RK19 EC RK16 1 @ 2 0_0402_5% TP_EN_R#
<58> TP_EN
10K_0402_5%
<19> TP_EN_PCH RK17 1 @ 2 0_0402_5%
1
TP_EN_R# PCH

KB/TP
A B C D E
1 1
2 2
Reserve Page
3 3
4 4
2017/11/23
Compal Secret Data
2018/09/01 Title
Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4
2017/11/23
Compal Secret Data
2018/09/01 Title
Reserve Page
A B C D E
A B C D E
THERMAL SENSOR
+3VS +3VS
1
1 1
RF9
RF10 2.2K_0402_5%
5
TMS@ 2.2K_0402_5% TMS@
G
QF1B TMS@
2
2N7002KDW _SOT363-6
<18,25,38,58,73> EC_SMB_CK2 3 4 TMS_SMB_CLK
S
D
2
TMS@
G
QF1A
2N7002KDW _SOT363-6
6 1 TMS_SMB_DATA
<18,25,38,58,73> EC_SMB_DA2
S
D
+3VS
+3VS +3VS
+3VS
.1U_0402_16V7K
2
C823
.1U_0402_16V7K
1
C2775
1 U2626 R4075
TMS@ R798 1 8 TMS_SMB_CLK TMS@ 10K_0402_5%
TMS@ TMS@ VDD SCL
10K_0402_5%
2 U52 2 7 TMS_SMB_DATA
1
1 8 TMS_SMB_CLK 2 D+ SDA
1
2 VDD SCL 7 TMS_SMB_DATA 3 6 THERMAL_ALERT#
D+ SDA D- ALERT# THERMAL_ALERT# <58>
2 3 6 THERMAL_SYS_ALERT# 2
1 TMS@2 TH_SYS_THERM# 4 D- ALERT 5 1 TMS@2 TH_VGA_THERM# 4 5
+3VS T_CRIT_A GND +3VS T_CRIT# GND
R801 10K_0402_5% R4076 10K_0402_5%
W 83L771AW G-2_TSSOP8
SA00003PU00 NCT7718W _MSOP8
S IC W 83L771AW G-2 TSSOP 8P SENSOR SA000067P00
TMS@ S IC NCT7718W MSOP 8P THEMAL SENSOR
TMS@
Part Number SMBUS ADDRESS

NCT7718W 1001_1000b
W83L771AWG-2 1001_1010b
3 To Hall sensor/B M/B Gsensor 3
+3VS
+3VS
Raptor U2629
+3VS
9
10 VDD
VDD_IO
1
+3VLP 12
0.1U_0201_10V6K
0.1U_0201_10V6K
JHS1 R4131 G_SCL_R 1 INT1 11
1U_0201_6.3V6M
<38> G_SCL_R SCL/SPC INT2 1 1 1
MBGSEN@ 0_0402_5% G_SDA_R 4
<38> G_SDA_R SDA/SDI/SDO
1 Gsen_AD0 3
C2784
C2785
C2786
LID_SW # 2 1 2 SA0/SDO 6
<58> LID_SW#
2
3 2 5 CS GND 7 2 2 2
4 3 G1 6 Gsen_AD0 5 GND 8
4 G2 RES GND
@ MBGSEN@
MBGSEN@
LIS2DH12TR_LGA12_2X2
1
ACES_50524-00401-P01 R4132
SP01001UE00 0_0402_5%
SA0000BAE00
@ MBGSEN@
CONN@
Near Pin9 and Pin10
2
4 4

Sensors
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4
2017/11/23
Compal Secret Data
2018/09/01 Title
Reserve Page
A B C D E
5 4 3 2 1
Raptor
SSD
Raptor:LANE REVERSAL for SATA/PCIe NGFF Slot_1 Key M (left side)
+3VS_NGFF PWR
Combo Lanes +3VALW
+3VS_NGFF1 +3VS_NGFF1
JSSD1
1 2 U43 J17
3 GND 3P3VAUX 4 1 14 +3V_NGFF_1 1 2
PCIE_PRX_DTX_N9 5 GND 3P3VAUX 6 2 VIN1 VOUT1 13
<17> PCIE_PRX_DTX_N9 PCIE_PRX_DTX_P9 PERn3 NC VIN1 VOUT1
C386
.1U_0402_16V7K
7 8 R351 0_0402_5% C832 JUMP_43X118 1
<17> PCIE_PRX_DTX_P9 9 PERp3 NC 10 2 1 +3V_NGFF_GATE 3 12 1 2
@ @
GND DAS/DSS# <39,41,43,58,78,83,85,88> SUSP# ON1 CT1
CN7 1 2 0.22U_0402_16V7KPCIE_PTX_C_DRX_N9 11 12 1000P_0402_50V7K
<17> PCIE_PTX_DRX_N9 PETn3 3P3VAUX
1
D CN8 1 2 0.22U_0402_16V7KPCIE_PTX_C_DRX_P9 13 14 4 11 D
<17> PCIE_PTX_DRX_P9 PETp3 3P3VAUX +5VALW VBIAS GND 2
0.01U_0402_16V7K
15 16 C829
PCIE_PRX_DTX_N10 17 GND 3P3VAUX 18 C388 5 10 1 2
<17> PCIE_PRX_DTX_N10
2
PCIE_PRX_DTX_P10 19 PERn2 3P3VAUX 20 ON2 CT2 1000P_0402_50V7K
<17> PCIE_PRX_DTX_P10 PERp2 NC
21 22 6 9
CN5 1 2 0.22U_0402_16V7KPCIE_PTX_C_DRX_N10 23 GND NC 24 7 VIN2 VOUT2 8 +3VS_NGFF2
<17> PCIE_PTX_DRX_N10 PETn2 NC VIN2 VOUT2
CN6 1 2 0.22U_0402_16V7KPCIE_PTX_C_DRX_P10 25 26 +3VALW +3VALW
<17> PCIE_PTX_DRX_P10 27 PETp2 NC 28 15 J27
PCIE_PRX_DTX_N11 29 GND NC 30 GPAD +3V_NGFF_2 1 2
<17> PCIE_PRX_DTX_N11 PCIE_PRX_DTX_P11 PERn1 NC
31 32 1 1 EM5209VF_DFN14_2X3
1U_0201_6.3V6M
1U_0201_6.3V6M
C830
.1U_0402_16V7K
33 34 20mohm/6A per channel JUMP_43X118 1
2 0.22U_0402_16V7KPCIE_PTX_C_DRX_N11 GND NC
C843
C826
CN3 1 35 36 @
<17> PCIE_PTX_DRX_N11 1 2 0.22U_0402_16V7KPCIE_PTX_C_DRX_P11 37 PETn1 NC 38
CN4
<17> PCIE_PTX_DRX_P11
PCIE_PRX_DTX_P12
39
41
PETp1
GND
DEVSLP
NC
40
42
SSD_DEVSLP1 <17> 2 2 SHORT DEFAULT 2
<17> PCIE_PRX_DTX_P12 PCIE_PRX_DTX_N12 PERn0/SATA-B+ NC
43 44
<17> PCIE_PRX_DTX_N12 45 PERp0/SATA-B- NC 46
CN1 1 2 0.22U_0402_16V7KPCIE_PTX_C_DRX_N12 47 GND NC 48
<17> PCIE_PTX_DRX_N12 1 2 0.22U_0402_16V7KPCIE_PTX_C_DRX_P12 49 PETn0/SATA-A- NC 50 PLT_RST_BUF#
CN2
<17> PCIE_PTX_DRX_P12 PETp0/SATA-A+ PERST# SSD1_CLKREQ#_R PLT_RST_BUF# <16,25,43,49,51,52>
51 52 1 @ 2
<15> CLK_PCIE_NGFF1#
CLK_PCIE_NGFF1#
CLK_PCIE_NGFF1
53 GND
REFCLKN
CLKREQ#
PEWake#
54 RN20 0_0402_5%
SSD1_CLKREQ# <15>
Raptor:Use +3VS
55 56
<15> CLK_PCIE_NGFF1 57 REFCLKP NC 58
GND NC
+3VS_NGFF1 67 68 SUSCLK_SSD1 1 @ 2
69 NC SUSCLK(32kHz) 70 SUSCLK <18,52>
PEDET0 RN3 0_0402_5%
71 PEDET(NC-PCIE/GND-SATA) 3P3VAUX 72
GND 3P3VAUX
1
@ 73 74
0920 Pull high at PCH side RN4
10K_0402_5%
75 GND
GND
3P3VAUX
76
GND1 77
GND2 PLT_RST_BUF#
2
1 @ 2 LOTES_APCI0172-P001A
<17> SATA_GP1
RN5 0_0402_5%
close to JSSD1
CONN@ 1
C
DC04000KY00 EMC@ CN49
C
1000P_0402_50V7K~D
2
1
D
@ Q35 2
BSS138W-7-F_SOT323-3 G
S
Raptor:reserve for ESD
3
Raptor Raptor:reserve for optane +3VS_NGFF1
SSD +3VS 1
10U_0402_6.3V6M
10U_0402_6.3V6M
0.1U_0201_10V6K
1 1 2
NGFF Slot_2 Key M (left side) SSD2_CLKREQ#_R
SSD1_CLKREQ#_R
RN22
RN23
1
1
@
@ 2 10K_0402_5%
2 10K_0402_5%
@
CN47 CN43 CN42
+ CN41
150U_D2_6.3VY_R15M
2 2 1 2
SGA00003700
+3VS_NGFF2
JSSD2
1 2
PCIE_PRX_DTX_N24
3
5
GND
GND
3P3VAUX
3P3VAUX
4
6
placement close PCIE SSD side
<14> PCIE_PRX_DTX_N24 PCIE_PRX_DTX_P24 7 PERn3 NC 8
9 10
<14> PCIE_PTX_DRX_N24
CN9 1 2 0.22U_0402_16V7KPCIE_PTX_C_DRX_N24 11 GND
PETn3
DAS/DSS#
3P3VAUX
12 Raptor:reserve
CN10 1 2 0.22U_0402_16V7KPCIE_PTX_C_DRX_P24 13 14
<14> PCIE_PTX_DRX_P24 PETp3 3P3VAUX
15 16
PCIE_PRX_DTX_N23 17 GND 3P3VAUX 18
<14> PCIE_PRX_DTX_P23
PCIE_PRX_DTX_P23 19 PERn2
PERp2
3P3VAUX
NC
20
PLT_RST_BUF#
PEDET Module Type
21 22
CN12 1 2 0.22U_0402_16V7KPCIE_PTX_C_DRX_P23 25 PETn2 NC 26
close to JSSD2
B
<14> PCIE_PTX_DRX_P23
PCIE_PRX_DTX_N22
27 PETp2
GND
NC
NC
28
1
0 SATA B
29 30 EMC@ CN50
<14> PCIE_PRX_DTX_N22 PCIE_PRX_DTX_P22 PERn1 NC
31 32 1000P_0402_50V7K~D
<14> PCIE_PRX_DTX_P22 33 PERp1 NC 34 2
CN13 1 2 0.22U_0402_16V7KPCIE_PTX_C_DRX_N22
2 0.22U_0402_16V7KPCIE_PTX_C_DRX_P22
35 GND
PETn1
NC
NC
36 1 PCIE
CN14 1 37 38
<14> PCIE_PTX_DRX_P22 PETp1 DEVSLP SSD_DEVSLP4 <17>
39 40
PCIE_PRX_DTX_P21 41 GND NC 42
<14> PCIE_PRX_DTX_P21
PCIE_PRX_DTX_N21 43 PERn0/SATA-B+
PERp0/SATA-B-
NC
NC
44 Raptor:reserve for ESD
45 46
<14> PCIE_PTX_DRX_N21 2 0.22U_0402_16V7KPCIE_PTX_C_DRX_P21 PETn0/SATA-A- NC PLT_RST_BUF#
CN16 1 49 50
<14> PCIE_PTX_DRX_P21 PETp0/SATA-A+ PERST# SSD2_CLKREQ#_R
51 52 1 @ 2
CLK_PCIE_NGFF2# 53 GND CLKREQ# 54 SSD2_CLKREQ# <15> +3VS_NGFF2
RN21 0_0402_5%
<15> CLK_PCIE_NGFF2# CLK_PCIE_NGFF2 REFCLKN PEWake#
55 56
<15> CLK_PCIE_NGFF2 57 REFCLKP NC 58
GND NC
1
10U_0402_6.3V6M
10U_0402_6.3V6M
0.1U_0201_10V6K
1 1 2
@ + CN44
67 68 SUSCLK_SSD2 1 @ 2 SUSCLK CN48 CN46 CN45 150U_D2_6.3VY_R15M
PEDET1 69 NC SUSCLK(32kHz) 70 RN8 0_0402_5%
T372 TP@ PEDET(NC-PCIE/GND-SATA) 3P3VAUX 2 2 1 2
SGA00003700
71 72
73 GND 3P3VAUX 74
75 GND 3P3VAUX
GND
GND1
76
77
placement close PCIE SSD side
GND2
LOTES_APCI0172-P001A
CONN@ Raptor:reserve
DC04000KY00
A
PEDET

Compal EH78F LA G161p r1c 0116 r0.1

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Compal EH78F LA G161p r1c 0116 r0.1

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A B C D E

X4 DMI Offline USB Charger

USB3.1 Retimer Active MUX DPRedriver

Board ID Table for AD channel Power State

EC_SMB_CK3 PD(TPS65982) 0x70

43 level BOM table Board ID PCB Revision Board ID PCB Revision

Security Classification Compal Secret Data Compal Electronics, Inc.

PU7105 PJ7107 RH100 +1.8VALW _PRIM PCH

PU8106 PL8107 +VCC_GT CPU

RH93 +1.05VALW _VCCMPHY PCH

PU7201 PJ7201 +VCCIO +1.05V_VCCST

+19VB_NVVDD RF7 +VCC_FAN2 FAN2

U4 +5VS_BL JBL1 KB BackLight

RO4 +5VS_HDD JHDD1

PL1301 PJ1302 HDMI A

EH78F_EVT Power Sequence

+3VALW → 94.89ms → 8.880s +3VALW

+1.8VALW → 96.19ms → 8.879s +1.8VALW

+1.05ALW → 97.17ms → 8.879S +1.05ALW

EC_RSMRST# → 42.10ms → 8.834 EC_RSMRST#

→ 19.08ms → 10.41ms PM_SLP_S4#

→ 4.8ms → 10.42ms SYSON

→ 25.38ms → 9.195us → 30.02ms → 9.244us SM_PG_CTRL

NV N18E-G3 Need check USE QS PN

S IC TU104-750-A1 FCBGA 2228 GPU ABO !

<24> DDR_B_D[0..63] DDR CHANNEL B

RC3 1 2 121_0402_1% SM_RCOMP0 G1 BN13 +0.6V_VREFCA

PEG Lane Reversed CFL-H

PCH_CPU_BCLK_P B31 BN25 CFG0 CFG0 RC7 1 @ 2 1K_0402_5%

RC78 2 CMC@ 1 51_0402_5% CPU_XDP_TDO

RC14 1 2 499_0402_1% H_PROCHOT#_R

RC15 1 2 60.4_0402_1% EC_VCCST_PG

RC16 1 2 20_0402_5% H_PM_DOW N RC13 1 2 220_0402_5% CPU_SVID_ALERT#

Power delete GT Power 7/27 +VCC_CORE +VCC_CORE +VCC_CORE CFL-H +VCC_CORE

+VCC_SA CFL-H +1.2V_VDDQ +1.2V_VDDQ

PLACE CAP BACKSIDE PLACE CAP BACKSIDE

The 30 HSIO lanes on PCH-H supports the following configurations:

PCH-H XTAL_IN/OUT POR is 24MHz for 571697_CNL_MOW_WW16_2017.pdf CNP-H

remove TP as C5PRH UH1G

RH219 1 2 10K_0402_5% W LAN_CLKREQ# RH222 1 2 10K_0402_5% TBT_CLKREQ#

AW13 BD4 CLK_CNV_PRX_DTX_N

PCH_SPI_CLK RH195 1 @ 2 100K_0201_5%

intel critical net recommend

SPI ROM ( 16MByte )

note : 1050 Use 8M rom

GPP_F13 Security Classification Compal Secret Data Compal Electronics, Inc.

RH44 DGPU_PRSNT# 2017/11/23 2018/09/01 Title

RH56 2 1 8.2K_0402_5% PM_BATLOW # +3VALW _DSW PM_SLP_S3# RH193 1 2 100K_0201_5%

+3VALW _PCH_PRIM PCH_PW ROK RH223 1 2 10K_0402_5%

100K_0402_5% 1 @ 2 RH184 SYS_PW ROK

100K_0402_5% 1 @ 2 RH61 PCH_DPW ROK

RH191 2 1 2.2K_0402_5% D_CK_SCLK XEMC@

RH232 2 1 2.2K_0402_5% PCH_SML1CLK

Raptor:Intel sensor hub

SUB_DET RH185 1 @ 2 1K_0402_5%

RH77 1 @ 2 4.7K_0402_5% GSPI0_MOSI STRAP Reserved 1 0

RH83 2 @ 1 100K_0402_5% PCH_SPKR

GPIO Group Voltage

0.0198A C1 AJ23 Internal LDO

C2 VCCAPLL_1P054 VCCDPHY_1P242 BG5 RH174 for 571391_CFL_H_PDG_Rev0p71.pdf

+3VALW +3VALW_PCH_PRIM +3VALW_PCH_PRIM +3VALW_SPI

2 Issued Date 2017/11/23 Deciphered Date 2018/09/01 Title

RG3014 1 upi@ 2 0_0402_5%