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    This document is a schematic for a Kaby Lake Y MB project with the model name KBL-Y. It shows the block diagram for a Kaby Lake Y 2+2 configuration with LPDDR3L memory and optimized for premium power segments, modern standby, and C10 low power modes. The diagram outlines the main components including the Intel Kaby Lake Y dual core processor, audio codec, memory, storage, wireless modules, displays, cameras, sensors and ports.

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    9e744f4167e95c5096648b92d04d7a7c6cf703cc

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    This document is a schematic for a Kaby Lake Y MB project with the model name KBL-Y. It shows the block diagram for a Kaby Lake Y 2+2 configuration with LPDDR3L memory and optimized for premium power segments, modern standby, and C10 low power modes. The diagram outlines the main components including the Intel Kaby Lake Y dual core processor, audio codec, memory, storage, wireless modules, displays, cameras, sensors and ports.

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    © All Rights Reserved
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    21 views55 pages

    6 CF 703 CC

    Uploaded by

    HDTalentDuel Channel
    This document is a schematic for a Kaby Lake Y MB project with the model name KBL-Y. It shows the block diagram for a Kaby Lake Y 2+2 configuration with LPDDR3L memory and optimized for premium power segments, modern standby, and C10 low power modes. The diagram outlines the main components including the Intel Kaby Lake Y dual core processor, audio codec, memory, storage, wireless modules, displays, cameras, sensors and ports.

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    of 55

    A B C D E

    1 1

    2
    Compal Confidential 2

    KBL-Y MB Schematic Document


    EPS30 LA-F803P
    3

    Rev: 0.3 3

    2018.06.08

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2017/03/20 Deciphered Date 2020/03/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Cover Sheet
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 1 of 55
    A B C D E
    A B C D E

    Compal Confidential
    Model Name: KBL-Y Kaby Lake Y Block Diagram
    Project Name: LA-F803P
    (KBL-Y 2+2 w/ LPDDR3L x64, Modern Standby )

    1
    Follow Premiun Power Segment, S0ix & C10 optimized 1

    HDA Memory Bus


    FPC Audio Codec Dual Channel LPDDR3L Memory Down 64bit x 2
    P. 19 ~ 21

    Combo Jack 1866HMz


    Realtek ALC3292
    P. 27 I2S
    PCIe x4 SSD (PCIe)
    Sub-Board Port 5 ~ 8
    LS-F803P TouchScreen Controller NGFF Key M P. 24
    eKTH6315 Speaker AMP Speaker AMP
    TAS2557 TAS2557
    P. 28 P. 28

    SPI0_CS0# System BIOS ROM


    Sub-Board Speaker_L Speaker_R 8MB (TBD)
    P. 28 P. 28 P. 7
    LS-F801P JTS2 Intel Kaby Lake Y

    PCIe Port 10
    2 2+2 USB2.0 Port 3 WLAN + BT 2
    eDP conn

    Headphone
    Windstorm Peak
    JLCD1 SD1216
    P. 23
    40 pin eDP 1.3 x4
    P. 22
    eDP Redriver
    SN75DP130 I2C
    Dual Core
    JSIM

    HD + IR Camera
    40pin Conn.

    USB2.0 Port 9 TPD 4.5W


    WWAN M.2 Conn.

    G-Sensor 40 pin ISH I2C USB2.0 Port 7


    HP9DS1TR PCIe Redriver
    SN75LVPE801DRFR PCIe
    PCIe Redriver Port 9
    P. 26 P. 25

    SN75LVPE801DRFR USB3.1 Port 3 USB3.1 / DP Mux & Redriver TX/RX USB3.1 Type-C Conn.
    DP TI TUSB546A-DCIRNQR SUB1/2 P. 36
    P. 37
    3
    USB2.0 Port 1,5 I2C
    3

    TX/RX USB3.1 Type-C PD Controller CC1 / CC2


    USB3.1 PCIe x4 TI TPS65987D Power Path
    Port 1 MUX/DEMUX AUX Port 1~4
    P. 36
    Type-C Conn. SBU1/2 TS3DS10224RUKR
    P. 38
    LSTX/RX Thunderbolt 3 DDI_1 DDI_2
    P. 38
    Alpine Ridge DP SPI ROM
    P. 5 ~ 18
    TX/RX 2M-bit
    USB3.1 DP
    Port 5 MUX/DEMUX AUX
    Type-C Conn. SBU1/2 TS3DS10224RUKR LPC
    P. 38 LSTX/RX P. 33~34
    P. 38
    KBC SMBus Thermal Sensor DC/DC Circuit
    P. 39
    ENE KB9022 F75303M P. 31
    P. 29
    I2C SPI ROM
    8M-bit Power Circuit
    PS/2 P. 40 ~ 53
    4 4

    I2C/SMBus ClickPad Int. KBD


    P. 30 P. 30
    CC1/2 USB3.1 Type-C PD Controller
    CC1/2 TI TPS65988
    P. 35
    Security Classification
    2017/03/20
    Compal Secret Data
    2020/03/20 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    CNL-Y_2+2 Block Diagrams
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 2 of 55
    A B C D E
    A

    Board ID Table for AD channel USB2.0 Port Table SOC SMBUS Address Table (TBC)
    Vcc 3.3V Address (8bit)
    Ra 100K +/- 1% USB2.0 Port Device NOTE SOC_SMBUS Net Name Power Rail Device Address (7 bit)
    Write Read
    Board ID /PCB Revision Rb V BID min V BID TYP V BID Max EC AD3 1 USB2.0 (MB) USB3.1 Type-C + PD
    0 / 0.2 0 0V 0.300 V 0x00 - 0x0B SOC_SMBCLK
    SOC_SMBDATA +3V_PRIM Track PAD TBC TBC TBC
    1 / 0.3 15K +/- 1% 0.423 V 0.430 V 0.438 V 0x1D - 0x26
    5 USB2.0 (MB) USB3.1 Type-C + PD
    2 / 0.4 27K +/- 1% 0.691 V 0.702 V 0.713 V 0x31 - 0x3B
    SOC_SML0CLK
    4 / 1.0 43K +/- 1% 0.978 V 0.992 V 1.006 V 0x47 - 0x54 SOC_SML0DATA +3VS N/A N/A N/A N/A
    7 USB2.0 (MB) USB3.1 Type-C + PD
    SML1_SMBCLK
    3 Blue Tooth WLAN 8265 SML1_SMBDAT +3VS EC TBC TBC TBC

    BOM Structure Table 9 IR Camera


    EC SMBUS Address Table (TBC)
    Function Stuff Un-Stuff Address (8bit)
    S0IX Mode S0IX@ NDSX@
    HSIO Port Table 2 X EC_SMBUS Port Power Rail Device Address (7 bit)
    Write Read
    Non-S0IX Mode NDSX@ S0IX@
    HSIO Port Capable Device PCIe CLK NOTE BATT 0x0B 0x16 0x17
    LPC 1.8V LPC@ SMBUS Port 1 +3V_SMBUS
    LPC 3.3V LPC@ 0 USB3.1 #1 Charger 0x09 0x12 0x13
    Panel PWM control @CPUPWM@ @ECPWM@
    TPS65988(1) 0x25 TBC TBC
    RF Componets RF@ @RF@ 1 USB3.1 #2
    EMI Components EMI@ @EMI@ TPS65988(2) 0x21 TBC TBC
    USB3.1 Type-C DP
    ESD Components ESD@ @ESD@ 2 USB3.1 #3 USB3.1 Type-C with Mux + PD SMBUS Port 2 +3VL_EC
    TPS65987D 0x23 TBC TBC
    ME Cnnector CONN@
    3 USB3.1 #4 F75303M 1001_101xb
    Power CHIP TBC TBC TBC
    4 USB3.1 #5 / PCIE #1
    SN75DP130
    5 USB3.1 #6 / PCIE #2
    Thunderbolt, Alpine Rodge CLK4 & Codec
    CLKREQ#4 TBC TBC TBC
    SMBUS Port 3 +3VALW
    @ 6 PCIE #3 / GbE
    Un-stuff SPK AMP TBC TBC TBC
    Components TP@
    Rshort@ 7 PCIE #4 / GbE
    Remove in MP MP@ (TBC)
    8 PCIE #5 / GbE I2C/ISH Address Table
    Address (8bit)
    I2C Port Power Rail Device Address (7 bit)
    9 PCIE #6 Write Read
    SSD (NGFF_Key M) CLK2 & PCIe/SATA interface
    CLKREQ#2 I2C 0 +3VS Track PAD(Reserved) 0x2C TBC TBC
    10 PCIE #7 / SATA #0
    I2C 1 +3V_PRIM Touch Screen 0x10b TBC TBC
    11 PCIE #8 / SATA #1
    1101011xb
    1
    ISH_I2C 0 +3VALW HP9DS1TR 0011110xb TBC TBC 1

    12 PCIE #9 / GbE WWAN CLK1 &


    CLKREQ#1

    13 PCIE #10 / GbE WLAN CLK3 &


    CLKREQ#3

    Power State
    SIGNAL
    STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
    +5VS
    Power +3VS
    S0 (Full ON) HIGH HIGH HIGH ON ON ON ON +3VALW_DSW +3V_PCH +1.2V_DDR +1.8VS
    plane +5VALW +1.8V_PRIM +3.3V_CV2 +1.0V_VCCSTG
    +3VALW +1.0V_PRIM +1.8V_MEM +0.85VS_VCCIO
    S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF +1.8VALW +1.0VA_GATE +1.0V_VCCST +0.6VS_VTT
    State +3VLP +VCC_PRIM +VCC_SA
    +VCC_GT
    S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF +VCC_CORE

    S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF R1I5@


    UC1
    R1I7@
    UC1
    S0 ON ON ON ON
    Load BOM Option Table
    S3 /AC ON ON ON OFF
    BOM Number Load BOM Option DS3 ON OFF ON OFF
    SA0000ADW00 SA0000ADS30
    S IC HE8067702739826 SR345 H0 1.2G BGA S IC HE8067702739526 SR33X H0 1.3G BGA S5 S4/AC ON OFF OFF OFF
    431ACZ32L01 @CPUPWM@/LPC@/MP@/S0IX@/X4E@/RF@/R1Mi@/R1I7@
    R3I5@ R3I7@
    UC1 UC1 S5 S4/AC doesn't exist OFF OFF OFF OFF
    431ACZ32L02 @CPUPWM@/LPC@/MP@/S0IX@/X4E@/RF@/R1Hy@/R1I5@

    431ACZ32L03 @CPUPWM@/LPC@/MP@/S0IX@/X4E@/RF@/R1Mi16@/R1I7@
    SA0000ADW10 SA0000ADS40
    S IC HE8067702739826 SR345 H0 1.2G A32 ! S IC HE8067702739526 SR33X H0 1.3G A32 !
    R1Mi@ R1Hy@ R1Mi16@ R1Sam@
    431ACZ32L04 @CPUPWM@/LPC@/MP@/S0IX@/X4E@/RF@/R1Sam@/R1I5@ ZZZ ZZZ ZZZ ZZZ
    R1I5R@ R1I7R@
    UC1 UC1
    431ACZ32L05 @CPUPWM@/LPC@/MP@/S0IX@/X4E@/RF@/R1Mi16@/R1I7R@

    X7676632L21 X7676632L22 X7676632L23 X7676632L24


    431ACZ32L06 @CPUPWM@/LPC@/MP@/S0IX@/X4E@/RF@/R1Mi16@/R1I5R@
    SA0000C4Q00 SA0000C4P00
    S IC A32 HE8067702739846 QLKW H0 1.3G BGA 1515 S IC A32 HE8067702739858 QQF4 H0 1.5G BGA 1515
    431ACZ32L07 @CPUPWM@/LPC@/MP@/S0IX@/X4E@/RF@/R1Hy@/R1I7R@

    DAX
    431ACZ32L08 @CPUPWM@/LPC@/MP@/S0IX@/X4E@/RF@/R1Mi@/R1I5R@

    431ACZ32L09 @CPUPWM@/LPC@/MP@/S0IX@/X4E@/RF@/R1Sam@/R1I7R@
    PCB
    Part Number = DAA000H5000
    PCB 2DC LA-F803P REV0 M/B
    431ACZ32L10 @CPUPWM@/LPC@/MP@/S0IX@/X4E@/RF@/R1Hy@/R1I5R@
    X4E@
    ZZZ
    431ACZ32L11 @CPUPWM@/LPC@/MP@/S0IX@/X4E@/RF@/R1Mi@/R1I7R@ Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2017/03/20 Deciphered Date 2020/03/20 Title

    431ACZ32L12 @CPUPWM@/LPC@/MP@/S0IX@/X4E@/RF@/R1Sam@/R1I5R@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Notes List
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    X4EACZ32L01 Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 3 of 55
    A
    5 4 3 2 1

    [EPDS30-Power Map_KBL-Y2+2_LPDDR3L_Premium_S0ix]
    +8.4V PUZ1 +VCCIN
    PWM (33A)
    MP2940-0020
    DC1 Page. 50
    +3V_LID(Battery Cell) +3VL_RTC

    PU1001 +1.05V_PRIM
    PWM (4.91A)
    SY8286RAC
    D D
    DC2 Page. 48
    +3VL
    +1.0V_PRIM UC5 +1.0VS_VCCSTG
    Loadswitch
    PUH1 +1.05V_PRIM_CORE TPS22922YZPR
    PWM (2.31A)
    NB681GD-Z Page. 12
    D2 Page. 44
    Premium +1.2V_VDDQ UC7 +1.2V_VCCPLL_OC
    Loadswitch
    TPS22907YZTR
    PUM1 +0.6VS_VTT
    PWM
    C10 Page. 12
    SY8210DQVC +1.1V_VDDQ
    D4 Page. 39
    +3V_SMBUS +3VL

    PU301 +3VALW
    Regulator (0.15A)
    SY8286BRAC
    Page. 33 +1.8V_PRIM
    PU1801 +1.8PRIM UD5 +1.8V_MEM
    PWM Loadswitch
    G5719CTB1U TPS22913CYZVR
    SYSON
    Page. 40 (PM_SLP_S4#) Page. 21

    UC18 +3V_PRIM +3VALW UA4


    Loadswitch LDO +1.8VALW_AUDIO
    TPS22907YZTR (3.2A) G9090-180TO1U
    Page. 29 Page. 28

    For SPK AMP register value keep.


    C
    [EPS30-SMBus Map] PU302
    Regulator
    SY8286BRAC
    +5VALW
    C

    Page. 33
    UC1 +3VS_AUDIO
    UV2 +5VS_SUB U7
    MOSFET +3VALW Loadswitch
    +3V_PRIM +3VALW_TP +3VALW_TP G527ATP1U (2A) TPS22907YZTR
    Page. 29 SUSP# Page. 39 +1.8VS_AUDIO
    (AUDIO_PWREN)
    R=1K R=2.2K
    AC12 SOC_SMBCLK TP_SMBCLK
    W6 SOC_SMBDATA TP_SMBDAT
    Touch Pad
    +3V_PRIM
    CPU W4 SOC_SML0CLK
    R=1K +3VS
    Q2

    +3VALW_TP
    +3VALW

    NGFF_SSD_PWREN
    US1
    Loadswitch
    TPS22922YZPR
    Page. 24
    +3VS_SSD

    AC10 SOC_SML0DATA
    R=1K
    CY10 I2C_0_SCL +3VALW
    UN2
    CW9 I2C_0_SDA Loadswitch +3VS_WLAN
    WLAN_PWR_EN TPS22922YZPR
    +3V_PRIM Q3 @
    Page. 23

    Premium
    R=1K
    AB11 I2C_1_SCL_TS
    AB9 I2C_1_SDA_TS
    Touch Screen +3VALW +3VS
    U6
    Load Switch
    +5VALW +5VS
    +3V_PRIM EM5209VF
    B
    +3VS B
    SUSP#
    (PM_SLP_S3#)
    R=1K R=2.2K
    AA4 SOC_SML1CLK SMB_CK2
    W10 SOC_SML1DATA SMB_DA2 Thermal Sensor :F75303M
    Address : 1001_101xb
    QC3 @

    TPS65988/TPS65987
    +3VS R: Address : 0x4B
    JTYPEC1 Address : 0x25 W: Address : 0x4A

    +3VL_EC R: Address : 0x43


    JTYPEC2 Address : 0x21 W: Address : 0x42
    UK1:+3VALW_EC (+3VL)
    QK3
    R=2.2K
    B8 EC_SMB_CK2 R: Address : 0x47
    A6 EC_SMB_DA2 JTYPEC3 Address : 0x23 W: Address : 0x46

    EC_SMB_CK1_R

    EC A8 EC_SMB_CK1
    +3V_SMBUS

    R=2.2K
    EC_SMB_DA1_R
    R=100 BAT 0x09
    +3VALW
    +3VALW

    A7 EC_SMB_DA1 SCL_CHG R=10K


    SDA_CHG SMB_BS_CLK SCL_P_MP2940
    R=0 Charger 0x09 SMB_BS_DAT SDA_P_MP2940
    A
    R=0 MP2940 A
    D6 +3VALW
    Address : 0x1A/0X19 E7
    QK5 +3VS_EDP_RE
    R=4.7K
    EC_SMB_CK3
    EC_SMB_DA3 RE_CL R=10K
    SPK AMP*2 RE_DA
    R=0 SN75DP130
    Security Classification Compal Secret Data Compal Electronics, Inc.
    R=0@ 2017/03/20 2020/03/20 Title
    Codec:ALC3292 Issued Date Deciphered Date
    Power MAP
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    LA-F801P 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, June 08, 2018 Sheet 4 of 55
    5 4 3 2 1
    5 4 3 2 1

    +3VS

    RC6 1 @ 2 2.2K_0201_5% SOC_DP1_CTRL_CLK PDG_Processor strap CFG[4] should be pulled


    RC16 1 2 2.2K_0201_5% SOC_DP1_CTRL_DATA low to enable embedded DisplayPort*
    1 2 SOC_DP2_CTRL_CLK SKYLAKE_ULX
    RC32 @ 2.2K_0201_5% @ UC1A
    RC33 1 2 2.2K_0201_5% SOC_DP2_CTRL_DATA DISPLAY Rev0.87
    SOC_DP1_N0 A46 H45 EDP_TXN0
    (33) SOC_DP1_N0 SOC_DP1_P0 DDI1_TXN[0] EDP_TXN[0] EDP_TXP0 EDP_TXN0 (22)
    C46 F45
    (33) SOC_DP1_P0 SOC_DP1_N1 C48 DDI1_TXP[0] EDP_TXP[0] J44 EDP_TXN1 EDP_TXP0 (22)
    (33) SOC_DP1_N1 SOC_DP1_P1 A48 DDI1_TXN[1] EDP_TXN[1] G44 EDP_TXP1 EDP_TXN1 (22)
    (33) SOC_DP1_P1 SOC_DP1_N2 DDI1_TXP[1] EDP_TXP[1] EDP_TXN2 EDP_TXP1 (22)
    PV: HPD double pull down B45 J46
    (33) SOC_DP1_N2 SOC_DP1_P2 D45 DDI1_TXN[2] EDP_TXN[2] G46 EDP_TXP2 EDP_TXN2 (22)
    (33) SOC_DP1_P2 SOC_DP1_N3 DDI1_TXP[2] EDP_TXP[2] EDP_TXN3 EDP_TXP2 (22) <eDP>
    B47 H43
    (33) SOC_DP1_N3 SOC_DP1_P3 D47 DDI1_TXN[3] EDP_TXN[3] F43 EDP_TXP3 EDP_TXN3 (22)
    eDP
    (33) SOC_DP1_P3 DDI1_TXP[3] EDP_TXP[3] EDP_TXP3 (22)

    D
    Functional Strap Definitions (33) SOC_DP2_N0
    SOC_DP2_N0
    SOC_DP2_P0
    A42
    DDI2_TXN[0]
    DDI

    EDP_AUXN
    J42 EDP_AUXN
    EDP_AUXP EDP_AUXN (22) D
    C42 G42
    (33) SOC_DP2_P0 SOC_DP2_N1 A44 DDI2_TXP[0] EDP_AUXP EDP_AUXP (22)

    GPP_E19 (Internal Pull Down): DDPB_CTRLDATA


    Alpine Ridge (33) SOC_DP2_N1 SOC_DP2_P1 C44 DDI2_TXN[1] A40 EDP_DISP RC2 2 @ 1
    (33) SOC_DP2_P1 SOC_DP2_N2 DDI2_TXP[1] EDP_DISP_UTIL
    B41 0_0201_5%
    (33) SOC_DP2_N2 SOC_DP2_P2 DDI2_TXN[2] SOC_DP1_AUXN
    D41 H41 SOC_DP1_AUXN (33)
    (33) SOC_DP2_P2 DDI2_TXP[2] <DDI1> DDI1_AUXN
    0 = Port B is not detected. (33) SOC_DP2_N3
    SOC_DP2_N3 B43
    DDI2_TXN[3] DDI1_AUXP
    F41 SOC_DP1_AUXP
    SOC_DP1_AUXP (33)
    SOC_DP2_P3 D43 J40 SOC_DP2_AUXN
    (33) SOC_DP2_P3 DDI2_TXP[3] DDI2_AUXN SOC_DP2_AUXP SOC_DP2_AUXN (33) TBT
    <DDI2> G40
    1 = Port B is detected. SOC_DP1_CTRL_CLK L6 DDI2_AUXP SOC_DP2_AUXP (33)
    SOC_DP1_CTRL_DATA H6 GPP_E18/DDPB_CTRLCLK C11 SOC_DP1_HPD
    GPP_E19/DDPB_CTRLDATA <DDI1> <DDI1> GPP_E13/DDPB_HPD0 SOC_DP2_HPD SOC_DP1_HPD (33)
    <DDI2> L10
    SOC_DP2_CTRL_CLK H4 GPP_E14/DDPC_HPD1 M7 EC_SCI# SOC_DP2_HPD (33)
    SOC_DP2_CTRL_DATA GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 EC_SCI# (29)
    GPP_E21 (Internal Pull Down): DDPC_CTRLDATA F4 <DDI2> F6
    GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 A7 EDP_HPD
    GPP_E17/EDP_HPD EDP_HPD (22)
    M5
    0 = Port C is not detected. +0.85VS_VCCIO L4 GPP_E22 D4 SOC_ENBKL
    PV: delete TS_RST#_PCH GPP_E23 EDP_BKLEN B6 SOC_BKL_PWM SOC_ENBKL (22,29)
    +EDP_COM EDP_BKLCTL SOC_ENVDD SOC_BKL_PWM (22)
    RC4 2 1 A50 DISPLAY SIDEBANDS D3
    1 = Port C is detected. 24.9_0402_1% EDP_RCOMP EDP_VDDEN SOC_ENVDD (22)
    1 OF 20
    RC4 Width 20 mils, Spacing 25 mils, KBL-Y_BGA1515
    Length < 100 mil
    +3VS

    RC1 1 @ 2 100K_0201_5% TP_INT#

    RC71 1 @ 2 10K_0201_5% TS_INT#

    RC485 1 2 10K_0201_5% EC_SCI#


    SKYLAKE_ULX
    @ UC1D
    Rev0.87
    +1.0V_VCCST H_CATERR# H49 D53 CPU_XDP_TCK0
    H_PECI F49 CATERR# PROC_TCK C54 SOC_XDP_TDI
    C H_THERMTRIP# (29) H_PECI H_PROCHOT# H_PROCHOT#_R PECI PROC_TDI SOC_XDP_TDO C
    RC95 1 2 1K_0201_5% (29,49) H_PROCHOT# RC8 1 2 499_0402_1% J48 G48
    H_THERMTRIP# H47 PROCHOT# PROC_TDO C59 SOC_XDP_TMS
    RC80 1 @ 2 49.9_0402_1% H_CATERR# 2 @ 1 SKTOCC# B62 THERMTRIP# PROC_TMS F47 SOC_XDP_TRST#
    RC67 0_0402_5% SKTOCC# PROC_TRST#
    XDP_BPM#0_R H51 JTAG B53 PCH_JTAG_TCK1
    TC69 @
    +1.0VS_VCCSTG TC68 @ XDP_BPM#1_R J50 BPM#[0] PCH_JTAG_TCK C50 SOC_XDP_TDI
    TC6 @ XDP_BPM#2_R F51 BPM#[1] PCH_JTAG_TDI B51 SOC_XDP_TDO
    RC13 1 2 1K_0201_5% H_PROCHOT# TC7 @ XDP_BPM#3_R G50 BPM#[2] PCH_JTAG_TDO A52 SOC_XDP_TMS
    BPM#[3] PCH_JTAG_TMS C52 SOC_XDP_TRST#
    E11 PCH_TRST# B49 CPU_XDP_TCK0
    TS_INT# M9 GPP_E3/CPU_GP0 JTAGX
    (22) TS_INT# TP_INT# GPP_E7/CPU_GP1
    BD8
    (30) TP_INT# NMI_DBG#_CPU BC11 GPP_B3/CPU_GP2
    (29) NMI_DBG#_CPU GPP_B4/CPU_GP3
    +3V_PRIM RC14 2 1 49.9_0402_1% CPU_POPIRCOMP BN17
    RC15 2 1 49.9_0402_1% PCH_OPIRCOMP BP16 PROC_POPIRCOMP
    PCH_OPIRCOMP
    CPU MISC
    RC490 1 2 10K_0201_5% NMI_DBG#_CPU 4 OF 20
    KBL-Y_BGA1515

    +1.0VS_VCCSTG
    Place to CPU side

    RC390 2 @ 1 51_0402_5% SOC_XDP_TMS

    RC389 2 @ 1 51_0402_5% SOC_XDP_TDI

    RC391 2 1 51_0402_1% SOC_XDP_TDO

    B B
    RC399 2 @ 1 51_0402_5% PCH_JTAG_TCK1

    RC398 2 1 51_0402_1% CPU_XDP_TCK0

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2041/09/08 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL Y(1/13) DDI,MSIC,XDP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 5 of 55
    5 4 3 2 1
    5 4 3 2 1

    Non-Interleave Memory

    D D

    SKYLAKE_ULX SKYLAKE_ULX
    (19) DDR_A_D[0..15] @ UC1B @ UC1C
    DDR_A_D0 AG61 Rev0.87 Rev0.87
    DDR0_DQ[0] (20) DDR_B_D[0..15]
    DDR_A_D1 AH60 BC62 M_CLK_A_DDR#0 DDR_B_D0 BC41 interleave / Non-lnterleaved BK36 M_CLK_B_DDR#0
    DDR0_DQ[1] DDR0_CKN[0] M_CLK_A_DDR#0 (19) M_CLK_B_DDR#0 (20)
    DDR_A_D2 AK62 BC60 M_CLK_A_DDR0
    M_CLK_A_DDR0 (19)
    DDR_B_D1 BC39 DDR0_DQ[32]/DDR1_DQ[0] DDR1_CKN[0] BM36 M_CLK_B_DDR0
    M_CLK_B_DDR0 (20)
    DDR_A_D3 AK60 DDR0_DQ[2] DDR0_CKP[0] BA60 M_CLK_A_DDR#1 DDR_B_D2 BG41 DDR0_DQ[33]/DDR1_DQ[1] DDR1_CKP[0] BD32 M_CLK_B_DDR#1
    DDR0_DQ[3] DDR0_CKN[1] M_CLK_A_DDR#1 (19) M_CLK_B_DDR#1 (20)
    DDR_A_D4 AH62 BA62 M_CLK_A_DDR1
    M_CLK_A_DDR1 (19)
    DDR_B_D3 BE39 DDR0_DQ[34]/DDR1_DQ[2] DDR1_CKN[1] BF32 M_CLK_B_DDR1
    M_CLK_B_DDR1 (20)
    DDR_A_D5 AG63 DDR0_DQ[4] DDR0_CKP[1] DDR_B_D4 BF42 DDR0_DQ[35]/DDR1_DQ[3] DDR1_CKP[1]
    DDR_A_D6 AL61 DDR0_DQ[5] BB57 DDR_A_CKE0 DDR_B_D5 BD42 DDR0_DQ[36]/DDR1_DQ[4] BN33 DDR_B_CKE0
    DDR0_DQ[6] DDR0_CKE[0] DDR_A_CKE0 (19) DDR_B_CKE0 (20)
    DDR_A_D7 AL63 BC58 DDR_A_CKE1
    DDR_A_CKE1 (19)
    DDR_B_D6 BG39 DDR0_DQ[37]/DDR1_DQ[5] DDR1_CKE[0] BK32 DDR_B_CKE1
    DDR_B_CKE1 (20)
    DDR_A_D8 AM60 DDR0_DQ[7] DDR0_CKE[1] BE57 DDR_A_CKE2 DDR_B_D7 BE41 DDR0_DQ[38]/DDR1_DQ[6] DDR1_CKE[1] BG33 DDR_B_CKE2
    DDR0_DQ[8] DDR0_CKE[2] DDR_A_CKE2 (19) DDR_B_CKE2 (20)
    DDR_A_D9 AM62 AW61 DDR_A_CKE3
    DDR_A_CKE3 (19)
    DDR_B_D8 BC43 DDR0_DQ[39]/DDR1_DQ[7] DDR1_CKE[2] BH30 DDR_B_CKE3
    DDR_B_CKE3 (20)
    DDR_A_D10 AT60 DDR0_DQ[9] DDR0_CKE[3] DDR_B_D9 BD46 DDR0_DQ[40]/DDR1_DQ[8] DDR1_CKE[3]
    DDR_A_D11 AR61 DDR0_DQ[10] AW63 DDR_A_CS0# DDR_B_D10 BG43 DDR0_DQ[41]/DDR1_DQ[9] BM30 DDR_B_CS0#
    DDR0_DQ[11] DDR0_CS#[0] DDR_A_CS0# (19) DDR_B_CS0# (20)
    DDR_A_D12 AN61 BJ57 DDR_A_CS1#
    DDR_A_CS1# (19)
    DDR_B_D11 BG45 DDR0_DQ[42]/DDR1_DQ[10] DDR1_CS#[0] BJ33 DDR_B_CS1#
    DDR_B_CS1# (20)
    DDR_A_D13 AN63 DDR0_DQ[12] DDR0_CS#[1] BN61 DDR_A_ODT0 DDR_B_D12 BC45 DDR0_DQ[43]/DDR1_DQ[11] DDR1_CS#[1] BC35 DDR_B_ODT0
    DDR0_DQ[13] DDR0_ODT[0] DDR_A_ODT0 (19) DDR_B_ODT0 (20)
    DDR_A_D14 AR63 DDR_B_D13 BE43 DDR0_DQ[44]/DDR1_DQ[12] DDR1_ODT[0]
    DDR_A_D15 AT62 DDR0_DQ[14] DDR_B_D14 BE45 DDR0_DQ[45]/DDR1_DQ[13]
    DDR0_DQ[15] DDR3L / LPDDR3 / DDR4
    AW59 DDR_A_CAA_0 DDR_B_D15 BF46 DDR0_DQ[46]/DDR1_DQ[14]
    DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR_A_CAA_0 (19) (20) DDR_B_D[16..31] DDR3L / LPDDR3 / DDR4
    (19) DDR_A_D[16..31]
    AW55 DDR_A_CAA_1 DDR_B_D16 BM28 DDR0_DQ[47]/DDR1_DQ[15] BK30 DDR_B_CAA_0
    Interleave/Non-lnterleaved DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR_A_CAA_1 (19) DDR_B_CAA_0 (20)
    DDR_A_D16 AT56 BF62 DDR_A_CAA_2 DDR_B_D17 BN27 DDR1_DQ[32]/DDR1_DQ[16] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] BN31 DDR_B_CAA_1
    DDR1_DQ[0]/DDR0_DQ[16] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR_A_CAA_2 (19) DDR_B_CAA_1 (20)
    DDR_A_D17 AR55 AV56 DDR_A_CAA_3 DDR_B_D18 BK28 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BM32 DDR_B_CAA_2
    DDR1_DQ[1]/DDR0_DQ[17] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR_A_CAA_3 (19) DDR_B_CAA_2 (20)
    DDR_A_D18 AN57 AW57 DDR_A_CAA_4 DDR_B_D19 BL25 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BL37 DDR_B_CAA_3
    DDR1_DQ[2]/DDR0_DQ[18] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR_A_CAA_4 (19) DDR_B_CAA_3 (20)
    DDR_A_D19 AN55 AV58 DDR_A_CAA_5 DDR_B_D20 BN25 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] BG31 DDR_B_CAA_4
    DDR1_DQ[3]/DDR0_DQ[19] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR_A_CAA_5 (19) DDR_B_CAA_4 (20)
    DDR_A_D20 AR57 BA56 DDR_A_CAA_6 DDR_B_D21 BL27 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] BN37 DDR_B_CAA_5
    DDR1_DQ[4]/DDR0_DQ[20] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR_A_CAA_6 (19) DDR_B_CAA_5 (20)
    DDR_A_D21 AT58 BD59 DDR_A_CAA_7 DDR_B_D22 BJ25 DDR1_DQ[37]/DDR1_DQ[21] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] BJ37 DDR_B_CAA_6
    DDR1_DQ[5]/DDR0_DQ[21] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR_A_CAA_7 (19) DDR_B_CAA_6 (20)
    DDR_A_D22 AM58 BD61 DDR_A_CAA_8 DDR_B_D23 BJ27 DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] BJ35 DDR_B_CAA_7
    DDR1_DQ[6]/DDR0_DQ[22] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR_A_CAA_8 (19) DDR_B_CAA_7 (20)
    DDR_A_D23 AM56 BG61 DDR_A_CAA_9 DDR_B_D24 BM24 DDR1_DQ[39]/DDR1_DQ[23] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] BM34 DDR_B_CAA_8
    DDR1_DQ[7]/DDR0_DQ[23] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_CAA_9 (19) DDR_B_CAA_8 (20)
    DDR_A_D24 AL55 BK59 DDR_A_CAB_0 DDR_B_D25 BK24 DDR1_DQ[40]/DDR1_DQ[24] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# BN35 DDR_B_CAA_9
    DDR1_DQ[8]/DDR0_DQ[24] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR_A_CAB_0 (19) DDR_B_CAA_9 (20)
    DDR_A_D25 AL57 BL62 DDR_A_CAB_1 DDR_B_D26 BN21 DDR1_DQ[41]/DDR1_DQ[25] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] BG37 DDR_B_CAB_0
    DDR1_DQ[9]/DDR0_DQ[25] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR_A_CAB_1 (19) DDR_B_CAB_0 (20)
    C DDR_A_D26 AH58 BJ61 DDR_A_CAB_2 DDR_B_D27 BJ23 DDR1_DQ[42]/DDR1_DQ[26] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] BE37 DDR_B_CAB_1 C
    DDR1_DQ[10]/DDR0_DQ[26] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR_A_CAB_2 (19) DDR_B_CAB_1 (20)
    DDR_A_D27 AH56 AV60 DDR_A_CAB_3 DDR_B_D28 BL23 DDR1_DQ[43]/DDR1_DQ[27] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] BC37 DDR_B_CAB_2
    DDR1_DQ[11]/DDR0_DQ[27] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR_A_CAB_3 (19) DDR_B_CAB_2 (20)
    DDR_A_D28 AK58 BN62 DDR_A_CAB_4 DDR_B_D29 BN23 DDR1_DQ[44]/DDR1_DQ[28] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] BF34 DDR_B_CAB_3
    DDR1_DQ[12]/DDR0_DQ[28] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR_A_CAB_4 (19) DDR_B_CAB_3 (20)
    DDR_A_D29 AK56 BB61 DDR_A_CAB_5 DDR_B_D30 BJ21 DDR1_DQ[45]/DDR1_DQ[29] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BC33 DDR_B_CAB_4
    DDR1_DQ[13]/DDR0_DQ[29] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDR_A_CAB_5 (19) DDR_B_CAB_4 (20)
    DDR_A_D30 AG55 BL61 DDR_A_CAB_6
    (20) DDR_B_D[32..47]
    DDR_B_D31 BL21 DDR1_DQ[46]/DDR1_DQ[30] DDR1_BA[0] /DDR1_CAB[4]/DDR1_BA[0] BF30 DDR_B_CAB_5
    DDR1_DQ[14]/DDR0_DQ[30] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR_A_CAB_6 (19) DDR_B_CAB_5 (20)
    (19) DDR_A_D[32..47]
    DDR_A_D31 AG57 BM59 DDR_A_CAB_7 DDR_B_D32 BN45 DDR1_DQ[47]/DDR1_DQ[31] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BD36 DDR_B_CAB_6
    DDR1_DQ[15]/DDR0_DQ[31] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR_A_CAB_7 (19) DDR_B_CAB_6 (20)
    DDR_A_D32 BE55 BN58 DDR_A_CAB_8 DDR_B_D33 BM46 DDR0_DQ[48]/DDR1_DQ[32] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] BG35 DDR_B_CAB_7
    DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR_A_CAB_8 (19) DDR_B_CAB_7 (20)
    DDR_A_D33 BC55 AV62 DDR_A_CAB_9 DDR_B_D34 BL43 DDR0_DQ[49]/DDR1_DQ[33] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] BC31 DDR_B_CAB_8
    DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR_A_CAB_9 (19) DDR_B_CAB_8 (20)
    DDR_A_D34 BG53 DDR_B_D35 BK46 DDR0_DQ[50]/DDR1_DQ[34] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BF36 DDR_B_CAB_9
    DDR0_DQ[18]/DDR0_DQ[34] DDR_B_CAB_9 (20)
    DDR_A_D35 BE53 BB63 DDR_B_D36 BN43 DDR0_DQ[51]/DDR1_DQ[35] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
    DDR_A_D36 BC53 DDR0_DQ[19]/DDR0_DQ[35] DDR0_MA[3] BL57 DDR_B_D37 BL45 DDR0_DQ[52]/DDR1_DQ[36] BJ31
    DDR_A_D37 BG55 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[4] AJ61 DDR_A_DQS#0 DDR_B_D38 BJ45 DDR0_DQ[53]/DDR1_DQ[37] DDR1_MA[3] BK34
    DDR_A_D38 BD52 DDR0_DQ[21]/DDR0_DQ[37] DDR0_DQSN[0] AJ63 DDR_A_DQS0 DDR_A_DQS#0 (19) DDR_B_D39 BJ43 DDR0_DQ[54]/DDR1_DQ[38] DDR1_MA[4]
    DDR0_DQ[22]/DDR0_DQ[38] DDR0_DQSP[0] DDR_A_DQS0 (19)
    DDR_A_D39 BF52 AP62 DDR_A_DQS#1 DDR_B_D40 BM42 DDR0_DQ[55]/DDR1_DQ[39]
    DDR0_DQ[23]/DDR0_DQ[39] DDR0_DQSN[1] DDR_A_DQS#1 (19)
    DDR_A_D40 BC51 AP60 DDR_A_DQS1 DDR_B_D41 BN41 DDR0_DQ[56]/DDR1_DQ[40] interleave / Non-lnterleaved BD40 DDR_B_DQS#0
    DDR0_DQ[24]/DDR0_DQ[40] DDR0_DQSP[1] DDR_A_DQS1 (19) DDR_B_DQS#0 (20)
    DDR_A_D41 BE51 DDR_B_D42 BJ41 DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQSN[4]/DDR1_DQSN[0] BF40 DDR_B_DQS0
    DDR0_DQ[25]/DDR0_DQ[41] DDR_B_DQS0 (20)
    DDR_A_D42 BC49 DDR_B_D43 BN39 DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQSP[4]/DDR1_DQSP[0] BD44 DDR_B_DQS#1
    DDR0_DQ[26]/DDR0_DQ[42] Interleave/Non-lnterleaved DDR_B_DQS#1 (20)
    DDR_A_D43 BE49 AP56 DDR_A_DQS#2 DDR_B_D44 BK42 DDR0_DQ[59]/DDR1_DQ[43] DDR0_DQSN[5]/DDR1_DQSN[1] BF44 DDR_B_DQS1
    DDR0_DQ[27]/DDR0_DQ[43] DDR1_DQSN[0]/DDR0_DQSN[2] DDR_A_DQS#2 (19) DDR_B_DQS1 (20)
    DDR_A_D44 BG51 AP58 DDR_A_DQS2 DDR_B_D45 BL41 DDR0_DQ[60]/DDR1_DQ[44] DDR0_DQSP[5]/DDR1_DQSP[1] BK26 DDR_B_DQS#2
    DDR0_DQ[28]/DDR0_DQ[44] DDR1_DQSP[0]/DDR0_DQSP[2] DDR_A_DQS2 (19) DDR_B_DQS#2 (20)
    DDR_A_D45 BG49 AJ57 DDR_A_DQS#3 DDR_B_D46 BL39 DDR0_DQ[61]/DDR1_DQ[45] DDR1_DQSN[4]/DDR1_DQSN[2] BM26 DDR_B_DQS2
    DDR0_DQ[29]/DDR0_DQ[45] DDR1_DQSN[1]/DDR0_DQSN[3] DDR_A_DQS#3 (19) DDR_B_DQS2 (20)
    DDR_A_D46 BF48 AJ55 DDR_A_DQS3 DDR_B_D47 BJ39 DDR0_DQ[62]/DDR1_DQ[46] DDR1_DQSP[4]/DDR1_DQSP[2] BM22 DDR_B_DQS#3
    DDR_A_D47 DDR0_DQ[30]/DDR0_DQ[46] DDR1_DQSP[1]/DDR0_DQSP[3] DDR_A_DQS#4 DDR_A_DQS3 (19) DDR0_DQ[63]/DDR1_DQ[47] DDR1_DQSN[5]/DDR1_DQSN[3] DDR_B_DQS3 DDR_B_DQS#3 (20)
    (19) DDR_A_D[48..63] BD48 BD54 BK22
    DDR_A_D48 DDR0_DQ[31]/DDR0_DQ[47] DDR0_DQSN[2]/DDR0_DQSN[4] DDR_A_DQS4 DDR_A_DQS#4 (19) DDR1_DQSP[5]/DDR1_DQSP[3] DDR_B_DQS#4 DDR_B_DQS3 (20)
    BJ55 BF54 BK44
    DDR_A_D49 DDR1_DQ[16]/DDR0_DQ[48] DDR0_DQSP[2]/DDR0_DQSP[4] DDR_A_DQS#5 DDR_A_DQS4 (19) (20) DDR_B_D[48..63] DDR_B_D48 DDR0_DQSN[6]/DDR1_DQSN[4] DDR_B_DQS4 DDR_B_DQS#4 (20)
    BL55 BF50 BF28 BM44
    DDR_A_D50 DDR1_DQ[17]/DDR0_DQ[49] DDR0_DQSN[3]/DDR0_DQSN[5] DDR_A_DQS5 DDR_A_DQS#5 (19) DDR_B_D49 DDR1_DQ[48] DDR0_DQSP[6]/DDR1_DQSP[4] DDR_B_DQS#5 DDR_B_DQS4 (20)
    BJ53 BD50 BD28 BM40
    DDR_A_D51 BL53 DDR1_DQ[18]/DDR0_DQ[50] DDR0_DQSP[3]/DDR0_DQSP[5] BM54 DDR_A_DQS#6 DDR_A_DQS5 (19) DDR_B_D50 BG25 DDR1_DQ[49] DDR0_DQSN[7]/DDR1_DQSN[5] BK40 DDR_B_DQS5 DDR_B_DQS#5 (20)
    DDR_A_D52 DDR1_DQ[19]/DDR0_DQ[51] DDR1_DQSN[2]/DDR0_DQSN[6] DDR_A_DQS6 DDR_A_DQS#6 (19) DDR_B_D51 DDR1_DQ[50] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_B_DQS5 (20)
    BN55 BK54 BC27
    DDR_A_D53 DDR1_DQ[20]/DDR0_DQ[52] DDR1_DQSP[2]/DDR0_DQSP[6] DDR_A_DQS#7 DDR_A_DQS6 (19) DDR_B_D52 DDR1_DQ[51]
    BN53 BK50 BG27
    DDR_A_D54 DDR1_DQ[21]/DDR0_DQ[53] DDR1_DQSN[3]/DDR0_DQSN[7] DDR_A_DQS7 DDR_A_DQS#7 (19) DDR_B_D53 DDR1_DQ[52] DDR_B_DQS#6
    BM52 BM50 BE27 BD26
    DDR_A_D55 DDR1_DQ[22]/DDR0_DQ[54] DDR1_DQSP[3]/DDR0_DQSP[7] DDR_A_DQS7 (19) DDR_B_D54 DDR1_DQ[53] DDR1_DQSN[6] DDR_B_DQS6 DDR_B_DQS#6 (20)
    BK52 BE25 BF26
    DDR_A_D56 DDR1_DQ[23]/DDR0_DQ[55] DDR0_ALERT# DDR_B_D55 DDR1_DQ[54] DDR1_DQSP[6] DDR_B_DQS#7 DDR_B_DQS6 (20)
    BL51 BG57 TP@ T273
    BC25 BF22
    DDR_A_D57 BJ51 DDR1_DQ[24]/DDR0_DQ[56] DDR0_ALERT# BM56 DDR_B_D56 BF24 DDR1_DQ[55] DDR1_DQSN[7] BD22 DDR_B_DQS7 DDR_B_DQS#7 (20)
    DDR1_DQ[25]/DDR0_DQ[57] DDR0_PAR TP@ T86 DDR1_DQ[56] DDR1_DQSP[7] DDR_B_DQS7 (20)
    DDR_A_D58 BL49 DDR_B_D57 BD24 BD34 DDR1_ALERT#
    DDR_A_D59 DDR1_DQ[26]/DDR0_DQ[58] DDR_B_D58 DDR1_DQ[57] DDR1_ALERT# T91
    BJ49 AR53 BG21 BD30
    DDR1_DQ[27]/DDR0_DQ[59] DDR_VREF_CA +0.6V_VREFCA DDR1_DQ[58] DDR1_PAR TP@ T87
    DDR_A_D60 BN49 AN53 DDR_B_D59 BC23 BP20 DDR3_DRAMRST#
    DDR_A_D61 DDR1_DQ[28]/DDR0_DQ[60] DDR0_VREF_DQ +0.6V_A_VREFDQ DDR_B_D60 DDR1_DQ[59] DRAM_RESET# SM_RCOMP0 TP@ T274
    B BN51 AW53 +0.6V_B_VREFDQ
    BE23 BF64 RC45 1 2 200_0402_1% B
    DDR_A_D62 BK48 DDR1_DQ[29]/DDR0_DQ[61] DDR CH-A DDR1_VREF_DQ DDR_B_D61 BG23 DDR1_DQ[60] DDR CH-B DDR_RCOMP[0] BJ64 SM_RCOMP1 RC46 1 2 80.6_0402_1%
    DDR_A_D63 BM48 DDR1_DQ[30]/DDR0_DQ[62] BN47 DDR_VTT_CNTL Trace width/Spacing >= 20mils DDR_B_D62 BC21 DDR1_DQ[61] DDR_RCOMP[1] BC64 SM_RCOMP2 RC47 1 2 162_0402_1%
    DDR1_DQ[31]/DDR0_DQ[63] 2 OF 20 DDR_VTT_CNTL DDR_B_D63 BE21 DDR1_DQ[62] 3 OF 20 DDR_RCOMP[2]
    DDR1_DQ[63]
    KBL-Y_BGA1515 KBL-Y_BGA1515

    SC03
    2 1 DDR3_DRAMRST#

    0.1U_0201_16V6K
    @ESD@

    Reserve
    DDR_VTT_CNTL RC48 1 short@ 2 0_0201_5%
    SM_PG_CTRL (44)
    DDR0_ALERT# RC540 1 short@ 2 0_0201_5%

    DDR1_ALERT# RC524 1 short@ 2 0_0201_5%

    A A

    2016-08-24
    Modify-Follow TD team

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2041/09/08 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL Y(2/13) DDRIII
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 6 of 55
    5 4 3 2 1
    5 4 3 2 1

    Functional Strap Definitions


    GPP_C2 (Internal Pull Down): SMBALERT#

    @ UC1E SKYLAKE_ULX 0 = Disable Intel ME Crypto Transport Layer Security


    Rev0.87 (TLS) cipher suite (no confidentiality).
    50MHz PCH_SPI_CLK AU10 AC12
    PCH_SPI_SO SPI0_CLK GPP_C0/SMBCLK SOC_SMBCLK (30) 1 = Enable Intel ME Crypto Transport Layer Security
    AU12 W6 Connect TP
    PCH_SPI_SI SPI0_MISO GPP_C1/SMBDATA SOC_SMBALERT# SOC_SMBDATA (30)
    AT3
    SPI0_MOSI GPP_C2/SMBALERT#
    W8 (TLS) cipher suite (with confidentiality). Must be
    PCH_SPI_IO2 AV11 pulled up to support Intel AMT with TLS and Intel
    PCH_SPI_IO3 AV13 SPI0_IO2 SPI - FLASH SMBUS, SMLINK W4 SOC_SML0CLK
    D
    PCH_SPI_CS0# SPI0_IO3 GPP_C3/SML0CLK SOC_SML0DATA
    SBA (Small Business Advantage) with TLS. D
    AU4 AC10
    PCH_SPI_CS1# AU6 SPI0_CS0# GPP_C4/SML0DATA AA6 GPP_C5
    T13 TP@ SPI0_CS1# GPP_C5/SML0ALERT# +3V_PRIM
    PCH_SPI_CS2# AU8
    T369 TP@ SPI0_CS2# AA4 PCH_TBT_RST# RH101
    SPI - TOUCH GPP_C6/SML1CLK TBT_W AKE# PCH_TBT_RST# (33)
    W10 PV: modify for RTD3 2 1 SOC_SMBALERT#
    GPP_C7/SML1DATA SOC_SML1ALERT# TBT_W AKE# (33)
    T15 TP@ P9 BB6 2.2K_0201_5%
    W W AN_DISABLE# N8 GPP_D1 GPP_B23/SML1ALERT#/PCHHOT#
    (26) W W AN_DISABLE# GPP_D2/SPI1_MISO @
    W W AN_PW REN P3 BK11 LPC_AD0 RC446 1 LPC@ 2 0_0201_5% LPC_AD0_R
    (26) W W AN_PW REN GPP_D3 GPP_A1/LAD0/ESPI_IO0 LPC_AD1 LPC_AD1_R LPC_AD0_R (29)
    W12 BJ8 RC447 1 LPC@ 2 0_0201_5%
    (26) CAMERA_PW REN GPP_D21 LPC GPP_A2/LAD1/ESPI_IO1 LPC_AD2 LPC_AD2_R LPC_AD1_R (29)
    V7 BG10 RC448 1 LPC@ 2 0_0201_5%
    (25) W W AN_PREN GPP_D22 GPP_A3/LAD2/ESPI_IO2 LPC_AD3 LPC_AD3_R LPC_AD2_R (29)
    T370 TP@ N6 BP5 RC449 1 LPC@ 2 0_0201_5%
    GPP_D0 GPP_A4/LAD3/ESPI_IO3 LPC_AD3_R (29)
    PV: control WWAN BP7
    CL_CK GPP_A5/LFRAME#/ESPI_CS# LPC_FRAME# (29)
    T21 TP@ F12 C LINK BJ6
    CL_DATA D12 CL_CLK GPP_A14/SUS_STAT#/ESPI_RESET#
    T22 TP@ CL_DATA
    CL_RST_N B12 BJ10 CLK_LPC_EC RH20 1 EMI@ 2 22_0201_5% CLK_LPC_EC_R
    T24 TP@ CL_RST# GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_LPC_EC_R (29)
    BF5 CLKOUT_LPC1
    GPP_A10/CLKOUT_LPC1 TP@ T23
    BH11 LPC_CLKRUN#
    EC_KBRST# GPP_A8/CLKRUN# LPC_CLKRUN# (29)
    (29) EC_KBRST# BL10
    LPC_SERIRQ BN8 GPP_A0/RCIN#
    To EC (29) LPC_SERIRQ GPP_A6/SERIRQ 1
    5 OF 20 CH47
    RF@
    LPC Mode KBL-Y_BGA1515
    2

    68P_0201_50V8J
    PIR29 SI: pop CH47
    Functional Strap Definitions
    GPP_C5 (Internal Pull Down): SML0ALERT#
    C C

    0 = LPC Is selected for EC.

    1 = eSPI Is selected for EC.


    +3V_PRIM
    @ RH98
    2 1 GPP_C5
    10K_0201_5%
    +3V_PRIM +3.3V_SPI
    RH470
    1 2
    @ 0_0402_5%
    Closed to ROM
    PCH_SPI_SI 2 1 SPI_SI_VROM0
    PCH_SPI_CLK RC454 2 EMI@ 1 33_0201_5% SPI_CLK_VROM0 GPP_B23 :SML1ALERT#
    16M SPI ROM(Support ISH)
    From CPU PCH_SPI_SO
    PCH_SPI_IO2
    PCH_SPI_IO3
    RC455 2
    RC456 2
    RC457 2
    1
    1
    1
    33_0201_5%
    33_0201_5%
    33_0201_5%
    SPI_SO_VROM0
    SPI_IO2_VROM0
    SPI_IO3_VROM0 +3.3V_SPI
    ‧alternate
    If USB 3.0 Port 1 is used for 4-wire DCI.OOB (BSSB), and
    functionality is also used on the pin, pull up
    UC2
    RC539 33_0201_5% to V3.3S with >100K resistor to avoid noise.

    EC_SPI_SO 2 LPC@ 1 SPI_SO_VROM0


    To SPI ROM PCH_SPI_CS0#
    SPI_SO_VROM0
    SPI_IO2_VROM0
    1
    2
    3
    CS#
    DO
    VCC
    HOLD#_RESET#
    8
    7
    6
    SPI_IO3_VROM0
    SPI_CLK_VROM0
    1
    CH35
    ‧BSSB,
    If USB 3.0 Port 1 is used for DCI.OOB (BSSB) 4-wire
    and NO alternate functionality is used, leave float.

    ‧V3.3S
    (29) EC_SPI_SO EC_SPI_SI SPI_SI_VROM0 WP# CLK SPI_SI_VROM0
    RC458 2 LPC@ 1 33_0201_5% 4 5
    From EC (29) EC_SPI_SI EC_SPI_CLK_R RC459 2 LPC@ SPI_CLK_VROM0 GND DI If DCI.OOB (BSSB) 2+2 functionality is used, pull up to
    1 33_0201_5% 9 0.1U_0201_10V6K
    (For share ROM) (29) EC_SPI_CLK_R EC_SPI_CS#0 RC460 2 LPC@ PCH_SPI_CS0# ThemalPad 2 with a 4.7K resistor.
    1 33_0201_5%
    (29) EC_SPI_CS#0
    RC461 33_0201_5%
    B W 25Q128FVPIQ_W SON8_6X5 B
    SA00007XA10 +3V_PRIM

    SOC_SML1ALERT# RH102 1 2 4.7K_0402_5%


    PIR24 SI: Change to 16M
    PCH_TBT_RST# RH96 1 @ 2 10K_0201_5%
    TBT_W AKE# RH97 1 2 10K_0201_5%

    SOC_SML0CLK RH99 1 2 1K_0201_5%


    SOC_SML0DATA RH100 1 2 1K_0201_5%

    SOC_SMBCLK RH94 1 2 1K_0201_5%


    SOC_SMBDATA RH95 1 2 1K_0201_5%

    +3VS

    LPC_CLKRUN# RH13 1 2 8.2K_0201_5%

    LPC_SERIRQ RH472 1 2 10K_0201_5%

    EC_KBRST# RH473 1 2 10K_0201_5%


    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2041/09/08 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL Y(3/13) SPI,SMB
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 7 of 55
    5 4 3 2 1
    5 4 3 2 1

    SKYLAKE_ULX
    @ UC1G
    A00_0906: EMI Request RH109 33chnage 56ohm Rev0.87
    AH9
    HDA_SYNC BJ19 GPP_G0/SD_CMD AH11
    HDA_BIT_CLK BK18 HDA_SYNC/I2S0_SFRM GPP_G1/SD_DATA0 AG12
    HDA_SDOUT BK16 HDA_BLK/I2S0_SCLK GPP_G2/SD_DATA1 AF9
    HDA_SDIN0 BL15 HDA_SDO/I2S0_TXD GPP_G3/SD_DATA2 AF11
    BL17 HDA_SDI0/I2S0_RXD GPP_G4/SD_DATA3 AG8
    HDA_RST# BL19 HDA_SDI1/I2S1_RXD GPP_G5/SD_CD# AG10
    RTD3_USB_PW R_EN V5 HDA_RST#/I2S1_SCLK SDIO/SDXC GPP_G6/SD_CLK AE12
    (33) RTD3_USB_PW R_EN GPP_D23/I2S_MCLK GPP_G7/SD_WP
    D BL12 D
    BK14 I2S1_SFRM BL4
    AUDIO
    I2S1_TXD GPP_A17/SD_PWR_EN#/ISH_GP7 BN4
    GPP_A16/SD_1P8_SEL @
    W LAN_TRANSMIT_OFF# AT13 BF1 SDIO_RCOMP RC60 2 1 200_0201_1%
    (23) W LAN_TRANSMIT_OFF# SOC_GPIOF0 GPP_F1/I2S2_SFRM SD_RCOMP
    T30 TP@ AT11
    BT_ON AP11 GPP_F0/I2S2_SCLK
    (23) BT_ON SOC_GPIOF3 GPP_F2/I2S2_TXD
    T127 TP@ AT5 AJ8
    GPP_F3/I2S2_RXD GPP_F23
    SOC_DMIC_CLK0 V3
    (22) SOC_DMIC_CLK0
    SOC_DMIC_DATA0 V11 GPP_D19/DMIC_CLK0 <+3V_1.8V_PGPPD> 561280_KBL UY PDG Rev2_0
    Camera (22) SOC_DMIC_DATA0 GPP_D20/DMIC_DATA0
    if SDXC interface is not used,
    AUDIO_PW REN U12
    (39) AUDIO_PW REN
    (26) W W AN_ASPM_CTRL
    W W AN_ASPM_CTRL U8 GPP_D17/DMIC_CLK1
    GPP_D18/DMIC_DATA1
    the SD_RCOMP pin does not need to be connected to a RCOMP resistor.
    (27) SPKR SPKR AV3
    GPP_B14/SPKR
    7 OF 20
    KBL-Y_BGA1515

    Functional Strap Definitions


    To Enable ME Override
    GPP_B14 (Internal Pull Down): SPKR HDA for AUDIO (29) ME_EN 1 @ 2
    RC501 100K_0201_5%
    TOP Swap Override
    0 = Disable TOP Swap mode.---> AAU30 Use (27) HDA_BIT_CLK_R 2 EMI@ 1 HDA_BIT_CLK RC507 1 @ 2 0_0201_5%
    RC462 2 1 33_0201_5% HDA_SYNC
    C
    1 = Enable TOP Swap Mode. (27) HDA_SYNC_R
    RC463 2 1 33_0201_5% HDA_SDOUT
    2
    C
    (27) HDA_SDOUT_R
    RC464 2 1 33_0201_5% HDA_RST#
    +3V_PRIM (27) HDA_RST#_R
    RC499 33_0201_5%
    RC83
    1 @ 2 SPKR 1 MP@ 1 MP@ 1 RF@ 1 2 1 3 HDA_SDOUT
    +3V_HDA
    100K_0201_5% RC500 1K_0201_1%

    2.2P_0201_25V
    CC171

    2.2P_0201_25V
    CC170

    10P_0201_25V8
    CC140
    2 2 2 QC1
    VGS(Max) : <1.5 V
    PJE138K 1N SOT-523-3

    +3V_PRIM

    HDA_SDIN0
    (27) HDA_SDIN0 HDA_SDO / I2S0_TXD (Internal Pull Down)(Primary well):
    Flash Descriptor Security Override
    0 = Enable (Default)
    RTD3_USB_PW R_EN 1 @ 2
    RC577 49.9K_0201_1%
    1 = Disable (Override)
    The internal pull-down is disabled after PCH_PWROK is High.

    SKYLAKE_ULX
    @ UC1I
    B Rev0.87 DDR Memory Configuratino Type Strap pin B
    H29 H31
    F29 CSI2_DN0 CSI2_CLKN0 F31
    F33 CSI2_DP0 CSI2_CLKP0 D31 +1.8V_PRIM
    H33 CSI2_DN1 CSI2_CLKN1 B31
    J30 CSI2_DP1 CSI2_CLKP1 C34 SKU RAM_ID2/1/0 Config P/N Describtion Matched Resister
    G30 CSI2_DN2 CSI2_CLKN2 A34
    J32 CSI2_DP2
    CSI2_DN3
    CSI-2 CSI2_CLKP2
    CSI2_CLKN3
    D39 RAM ID S IC D3 512M64

    2
    MT52L512M64D4PQ-107WT:B

    1K_0201_1%

    1K_0201_1%

    1K_0201_1%
    G32 B39 RC138 RC510 RC511 L01 000 Micron 8G R1 RC509 RC508 RC512
    CSI2_DP3 CSI2_CLKP3 A11 CSI2_COMP RC64 2 1 100_0201_1% LPDDR3L SA00009Z800
    D29 CSI2_COMP N4 @ @ @ S IC D3 32G/1866
    B29 CSI2_DN4 GPP_D4/FLASHTRIG L02 001 Hynix 8G R1 H9CCNNNCPTALBR-NUD RC138 RC508 RC512
    C32 CSI2_DP4 eMMC LPDDR3L SA000092J20 FBGA

    1
    A32 CSI2_DN5 AN12 RAM_ID0 RAM_ID0 S IC D3 32G/1866
    C30 CSI2_DP5 GPP_F13/EMMC_DATA0 AP9 RAM_ID1 RAM_ID1 L04 010 SAMSUNG 8GB R1 K3QF4F40BM-AGCF RC509 RC510 RC512
    A30 CSI2_DN6 GPP_F14/EMMC_DATA1 AN10 RAM_ID2 RAM_ID2 LPDDR3L SA00009DC00 FBGA
    D33 CSI2_DP6 GPP_F15/EMMC_DATA2 AJ10 S IC D3 64G/1866
    CSI2_DN7 GPP_F16/EMMC_DATA3 2

    2
    MT52L1G64D8QC-107 WT:B
    1K_0201_1%

    1K_0201_1%

    1K_0201_1%
    B33 AM9 RC509 RC508 RC512 L03 011 Micron 16G R1 RC138 RC510 RC512
    CSI2_DP7 GPP_F17/EMMC_DATA4 AL12 LPDDR3L SA0000C1800
    D35 GPP_F18/EMMC_DATA5 AJ12 @ @ @
    B35 CSI2_DN8 GPP_F19/EMMC_DATA6 AN8
    C36 CSI2_DP8 GPP_F20/EMMC_DATA7
    1

    1
    A36 CSI2_DN9 AL10 S IC D3
    D37 CSI2_DP9 GPP_F21/EMMC_RCLK AL8 Micron 8GB R3 MT52L512M64D4PQ-107WT:B
    B37 CSI2_DN10 GPP_F22/EMMC_CLK AM11 LPDDR3L SA00009Z810 A32!
    C38 CSI2_DP10 GPP_F12/EMMC_CMD S IC D3 32G/1866
    A38 CSI2_DN11 BC1 EMMC_RCOMP RC61 2 1 200_0201_1% Hynix 4GB R3 H9CCNNNCPTALBR-NUD
    CSI2_DP11 EMMC_RCOMP LPDDR3L SA000092J30 FBGA A32 !
    9 OF 20 S IC D3 32G/1866
    A K3QF4F40BM-AGCF A
    KBL-Y_BGA1515 SAMSUNG 4GB R3
    LPDDR3L SA00009DC10 A32 !

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2041/09/08 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL Y(4/13) HDA,EMMC,SDIO
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 8 of 55
    5 4 3 2 1
    5 4 3 2 1

    +3VL_RTC

    RC514 1 2 20K_0201_5% SOC_SRTCRST#


    SKYLAKE_ULX
    @ UC1J
    CC6 1 2 1U_0201_6.3V6M Rev0.87
    CLOCK SIGNALS
    CLRP1 1 2 SHORT PADS CLR ME CLK_PCIE_N1 H35 J34
    (26) CLK_PCIE_N1 CLK_PCIE_P1 CLKOUT_PCIE_N1 CLKOUT_ITPXDP_N
    WWAN F35 G34
    (26) CLK_PCIE_P1 CLKREQ_PCIE#1 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_P
    (26) CLKREQ_PCIE#1 AV9
    RC513 1 2 20K_0201_5% SOC_RTCRST# GPP_B6/SRCCLKREQ1# BA15 SUSCLK_S RH76 1 2 SUSCLK
    CLK_PCIE_N2 GPD8/SUSCLK SUSCLK (23)
    D J36 0_0402_5% D
    (24) CLK_PCIE_N2 CLK_PCIE_P2 CLKOUT_PCIE_N2 XTAL24_IN
    CC277 1 2 1U_0201_6.3V6M NVMe SSD G36 M1 CH46 1
    (24) CLK_PCIE_P2 CLKREQ_PCIE#2 CLKOUT_PCIE_P2 XTAL24_IN XTAL24_OUT
    (24) CLKREQ_PCIE#2 BD10 L2
    GPP_B7/SRCCLKREQ2# XTAL24_OUT

    0.1U_0201_10V6K
    CLRP2 1 2 SHORT PADS CLR CMOS RH78 @EMI@
    CLK_PCIE_N3 J38 P1 XCLK_BIASREF 1 2
    (23) CLK_PCIE_N3 CLKOUT_PCIE_N3 XCLK_BIASREF +1.0V_PRIM 2
    Wireless LAN CLK_PCIE_P3 G38 2.7K_0201_1%
    SM_INTRUDER# (23) CLK_PCIE_P3 CLKREQ_PCIE#3 CLKOUT_PCIE_P3 PCH_RTCX1
    RC54 1 2 1M_0201_5% (23) CLKREQ_PCIE#3 AV5 BN19
    GPP_B8/SRCCLKREQ3# RTCX1 BP18 PCH_RTCX2
    +3VS CLK_PCIE_N4 H37 RTCX2
    (33) CLK_PCIE_N4 CLK_PCIE_P4 CLKOUT_PCIE_N4 SOC_SRTCRST#
    AR F37 BH18
    (33) CLK_PCIE_P4 CLKREQ_PCIE#4 CLKOUT_PCIE_P4 SRTCRST# SOC_RTCRST# SOC_SRTCRST# (29)
    (33) CLKREQ_PCIE#4 AV7 BN12
    GPP_B9/SRCCLKREQ4# RTCRST# SOC_RTCRST# (29)
    RC474 1 @ 2 10K_0201_5% CLKREQ_PCIE#5 CLK_PCIE_N5 H39
    T33 TP@
    CLK_PCIE_P5 F39 CLKOUT_PCIE_N5 RTC_RST# by PWR BTN
    T34 TP@ CLKOUT_PCIE_P5
    RC475 1 2 10K_0201_5% CLKREQ_PCIE#1 CLKREQ_PCIE#5 BC5
    GPP_B10/SRCCLKREQ5#
    RC476 1 2 10K_0201_5% CLKREQ_PCIE#2 +3VS RC75 1 @ 2 10K_0201_5% BB10
    GPP_B5/SRCCLKREQ0#
    RC477 1 @ 2 10K_0201_5% CLKREQ_PCIE#3 CLKREQ_PCIE#3 use PU RN19. 10 OF 20
    KBL-Y_BGA1515
    RC478 1 2 10K_0201_5% CLKREQ_PCIE#4
    D16
    EC_RSMRST# 1 2 PCH_PW ROK
    RB751S40T1G_SOD523-2 PCH_RTCX2
    2 1 SYS_RESET# D15
    +3V_PRIM CLRP4 SHORT PADS 2 1
    PW R_3V5V_PG (43)
    RB751S40T1G_SOD523-2
    RH114 1 @ 2 10K_0201_5% PCH_SUSW ARN# PCH_RTCX1
    RH208 1 2 10K_0201_5% VRALERT# PV: D15,D16 pop
    C RH132 1 2 10K_0201_5% SYS_RESET# 1 2 C
    RC58 10M_0402_5%

    RH44 1 2 100K_0201_5% PCH_PW ROK XTAL24_OUT RC50 1 EMI@ 2 XTAL24_OUT_R


    33_0201_1%
    +3V_PRIM XTAL24_IN RC195 1 EMI@ 2 XTAL24_IN_R RC563 1 2
    33_0201_1% 1M_0402_1% YC2 1 2
    +3VALW _DSW TC7SH08FU_SSOP5
    YC1

    5
    UH1 SJ10000SK00
    RH115 1 2 10K_0201_5% AC_PRESENT_R 1 PCH_PLTRST# 1 4 32.768KHZ_9PF

    P
    B X'tal G

    6.8P_0402_50V8C

    6.8P_0402_50V8C
    RH210 1 2 10K_0201_5% PCH_GPD11 4 1 1
    (22,23,24,29,31,33) PLT_RST# O
    RH117 1 2 10K_0201_5% BATLOW # 2
    A

    G
    1

    CC14

    CC12
    RH82 1 2 10K_0201_5% LAN_W AKE#
    RH471 1 2 1K_0201_5% SOC_PCIE_W AKE# RH46 2 3

    3
    RH68 1 2 2.2K_0201_5% PBTN_OUT#_R G X'tal 2 2

    22P_0402_50V8J

    22P_0402_50V8J
    100K_0201_5%
    CC8 24MHZ_8PF_8Y24080002 CC7
    2

    SJ10000PS00

    RH50 1 2 100K_0201_5% PCH_DPW ROK_R


    RH49 1 2 10K_0201_5% EC_RSMRST#
    CC278 1 2 100P_0201_50V8J
    SKYLAKE_ULX
    @ UC1K
    ESD@ Rev0.87
    SYSTEM POWER MANAGEMENT

    PCH_PLTRST# BB8 BC9 PM_SLP_S0#


    SYS_RESET# GPP_B13/PLTRST# GPP_B12/SLP_S0# PM_SLP_S3# PM_SLP_S0# (11,12,29,47,49)
    H2 AY14
    EC_RSMRST# SYS_RESET# GPD4/SLP_S3# PM_SLP_S4# PM_SLP_S3# (12,29,33,39)
    (29) EC_RSMRST# BJ12 BF16
    RSMRST# GPD5/SLP_S4# PM_SLP_S5# PM_SLP_S4# (21,29)
    BH14 TP@ T392
    B TC67 @ H_CPUPW RGD_R A62 GPD10/SLP_S5# B
    EC_VCCST_PG B61 PROCPWRGD BN10 SLP_SUS#
    VCCST_PWRGD SLP_SUS# SLP_LAN# SLP_SUS# (29)
    BP11 TP@ T35
    J1 SLP_LAN# BH16 SLP_W LAN#
    (29) SYS_PW ROK SYS_PWROK GPD9/SLP_WLAN# SLP_W LAN# (23) PDG_ internal pull-up resistor, nterna
    PCH_PW ROK BP14 BE17 PM_SLP_A#
    (29) PCH_PW ROK
    PCH_DPW ROK_R BN15 PCH_PWROK GPD6/SLP_A# TP@ T395 16 ms de-bounce on the input.
    DSW_PWROK BF14 PBTN_OUT#_R
    PCH_SUSW ARN# BL6 GPD3/PWRBTN# BD14 AC_PRESENT_R
    (29) PCH_SUSW ARN# SUSACK#_R GPP_A13/SUSWARN#/SUSPWRDNACK GPD1/ACPRESENT
    (29) SUSACK# RH60 1 short@ 2 0_0201_5% BF9 BD16 BATLOW #
    GPP_A15/SUSACK# GPD0/BATLOW#
    SOC_PCIE_W AKE# BP9 BF7 @ TC63
    PV: remove TBT_WAKE# LAN_W AKE# BE15 WAKE# GPP_A11/PME# BG19 SM_INTRUDER#
    PCH_GPD11 BC15 GPD2/LAN_WAKE# INTRUDER#
    BB16 GPD11/LANPHYPC BC7
    GPD7/RSVD GPP_B11/EXT_PWR_GATE# BD6 VRALERT#
    GPP_B2/VRALERT#
    11 OF 20
    RC516 2 1 0_0201_5% PBTN_OUT#_R KBL-Y_BGA1515
    (29) PBTN_OUT#
    RC515 2 1 0_0201_5% AC_PRESENT_R
    (29) ACIN

    (29) DPW ROK_EC RC69 2 1 0_0201_5% PCH_DPW ROK_R PDG_DPWROK connect to VccDSW3_3 power rail monitoring circuit to
    support Deep Sx state.This signal can be tied to RSMRST# for platforms
    that do not support the Deep Sx state.The DSW rails must be stable
    for at least 10 ms before DPWROK is asserted to PCH.
    +1.0V_VCCST PDG_SUSACK#, this signal is driven from the platform EC to PCH to acknowledge
    that EC has received the SUSWARN# signals and it is preparing to go into DeepSx
    A mode.for at least 10 ms before DPWROK is asserted to PCH. A
    1

    RH66
    PDG_SLP_SUS#, a low on this signal indicates that PCH is in Deep Sx state and that SLP_W LAN# @ TC11
    1K_0201_5% EC/platform logic does not need to keep the Primary Rails ON.
    2

    RC79
    1 2 EC_VCCST_PG Security Classification Compal Secret Data Compal Electronics, Inc.
    60.4_0402_1% 2041/09/08 2013/10/28 Title
    Issued Date Deciphered Date
    R03_0629 For Thermal diode placement del UH2 RH4
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL Y(5/13) CLK,GPIO
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    (29) EC_VCCST_PG_R
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 9 of 55
    5 4 3 2 1
    5 4 3 2 1

    SKYLAKE_ULX
    @ UC1F
    Rev0.87
    LPSS ISH

    PV: delete TS_STOP#_PCH BC3


    AW10 GPP_B15/GSPI0_CS# P11
    AW6 GPP_B16/GSPI0_CLK GPP_D9 T7
    GPP_B18 Strap Pin BB4 GPP_B17/GSPI0_MISO GPP_D10 T5
    GPP_B18/GSPI0_MOSI GPP_D11 MUX_DCI_CLK (37)
    T11
    GPP_D12 MUX_DCI_DAT (37)
    D BB2 D
    W W AN_W AKE# AW12 GPP_B19/GSPI1_CS# P7 ISH_I2C_0_SDA_R
    (26) W W AN_W AKE# GPP_B20/GSPI1_CLK GPP_D5/ISH_I2C0_SDA +3V_PRIM
    AW4 P5 ISH_I2C_0_SCL_R
    GPP_B22 Strap Pin AW8 GPP_B21/GSPI1_MISO GPP_D6/ISH_I2C0_SCL 9x-Sensor, ACCEL2
    PV: delete TS_PWREN_PCH GPP_B22/GSPI1_MOSI T9 @ TC41
    GPP_D7/ISH_I2C1_SDA

    2
    (33) TBT_CIO_PLUG_EVENT# AC8 T3 @ TC42
    AA8 GPP_C8/UART0_RXD GPP_D8/ISH_I2C1_SCL RH142 @
    (33) TBT_FORCE_PW R GPP_C9/UART0_TXD
    To TBT. AA10 AM7 100K_0201_5%
    (33) PM_BATLOW # GPP_C10/UART0_RTS# GPP_F10/I2C5_SDA/ISH_I2C2_SDA
    AA12 1.8V AT9
    (33) RTD3_CIO_PW R_EN GPP_C11/UART0_CTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL

    1
    UART_2_CRXD_DTXD AD5 U10 DDR_CHB_EN BID_BC
    UART_2_CTXD_DRXD AD7 GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA U4 DDR_CHA_EN
    AD3 GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK U6 BID_BC
    GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS#

    2
    AD9 V9
    GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT# RH143 @
    I2C_0_SDA AD11 AC6
    Track Pad (30) I2C_0_SDA I2C_0_SCL AB3 GPP_C16/I2C0_SDA GPP_C12/UART1_RXD/ISH_UART1_RXD AC4
    100K_0201_5%
    (Reserved) (30) I2C_0_SCL GPP_C17/I2C0_SCL GPP_C13/UART1_TXD/ISH_UART1_TXD AB7 NGFF_SSD_W AKE#
    NGFF_SSD_W AKE# (24)

    1
    I2C_1_SDA_TS AB9 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB5 NGFF_SSD_PW REN
    (22) I2C_1_SDA_TS I2C_1_SCL_TS GPP_C18/I2C1_SDA GPP_C15/UART1_CTS#/ISH_UART1_CTS# NGFF_SSD_PW REN (24)
    Touch Screen AB11
    (22) I2C_1_SCL_TS GPP_C19/I2C1_SCL INT1_A_G
    BF11 INT1_A_G (26)
    AP3 GPP_A18/ISH_GP0 BD2 W W AN_RESET#
    GPP_F4/I2C2_SDA GPP_A19/ISH_GP1 INT2_A_G W W AN_RESET# (26)
    AP7 BJ1 INT2_A_G (26)
    GPP_F5/I2C2_SCL GPP_A20/ISH_GP2 BL3
    AP5 GPP_A21/ISH_GP3 BJ3
    GPP_F6/I2C3_SDA 1.8V GPP_A22/ISH_GP4 PV: change pin define from GPP_F4 to GPP_A19
    AT7 BD4 +3VS
    (23,26) COEX1 GPP_F7/I2C3_SCL GPP_A23/ISH_GP5 BJ4
    AN4 Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY#/ISH_GP6
    (23,26) COEX2 GPP_F8/I2C4_SDA
    AN6 W W AN_W AKE# RC572 1 @ 2 10K_0201_5%
    (23,26) COEX3 GPP_F9/I2C4_SCL
    C NGFF_SSD_W AKE# RC570 1 @ 2 10K_0201_5% C
    6 OF 20 DDR_CHA_EN RH140 1 2 100K_0201_5%
    DDR_CHB_EN RH141 1 2 100K_0201_5%
    KBL-Y_BGA1515 INT1_A_G RC441 1 2 10K_0201_5%
    INT2_A_G RC440 1 2 10K_0201_5%

    +3V_PRIM

    ISH_I2C_0_SCL_R DDR_CHA_EN @ RH61 1 2 SHORT PADS


    DDR_CHB_EN @ RH65 1 2 SHORT PADS

    1
    +3V_PRIM 2
    S1

    G1
    PIR1 SI: PU 10Kohm D1 6
    ISH_I2C_0_SDA_R ISH_I2C_0_SCL (26)
    PV: change PU +3V_PRIM 4
    S2
    5
    RC580 1 2 10K_0201_5% PM_BATLOW # DMN63D8LV-7_SOT563-6 G2

    RC200 1 2 49.9K_0201_1% UART_2_CRXD_DTXD QC4


    D2
    To Sub/B (In +3VALW plan)

    3
    RC201 1 2 49.9K_0201_1% UART_2_CTXD_DRXD
    +3V_PRIM
    ISH_I2C_0_SDA (26)
    ISH_I2C_0_SDA_R 1 2
    RC78 1K_0201_5%
    ISH_I2C_0_SCL_R 1 2
    PV: delete TS_STOP#_PCH RC503 1K_0201_5%
    PV: delete TS_PWREN_PCH RTD3_CIO_PW R_EN 1 2
    RC145 10K_0201_5%
    B B
    TBT_CIO_PLUG_EVENT#1 2
    RC582 10K_0201_5%
    PIR5 PV: Add PU 10Kohm
    W W AN_W AKE# 1 2
    RC583 10K_0201_5%
    Functional Strap Definitions Functional Strap Definitions PIR6 PV: PU +3V_PRIM 10K

    GPP_B18 (Internal Pull Down): GSSPIO_MOSI GPP_B22 (Internal Pull Down): GSSPI1_MOSI
    No Reboot Boot BIOS Strap Bit
    0 = Disable No Reboot mode. --> AAU30 Use 0 = SPI Mode --> AAU30 Use
    1 = Enable No Reboot Mode. (PCH will disable the TCO 1 = LPC Mode
    Timer system reboot feature). This function is useful
    when running ITP/XDP.

    +3V_PRIM +3V_PRIM
    RC84 RC85
    1 @ 2 GPP_B18 1 @ 2 GPP_B22
    150K_0201_5% 150K_0201_5%

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2041/09/08 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL Y(6/13) GPIO,LPIO,I2C
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 10 of 55
    5 4 3 2 1
    5 4 3 2 1

    SKYLAKE_ULX
    @ UC1H
    Rev0.87
    C20 C16 USB3_CRX_DTX_N1 RC203 1 @ 2 0_0201_5%
    (33) PCIE_CRX_TTX_N1 PCIE1_RXN/USB3_5_RXN USB3_1_RXN
    A20 A16 USB3_CRX_DTX_P1
    (33) PCIE_CRX_TTX_P1 PCIE1_RXP/USB3_5_RXP USB3_1_RXP
    D G20 G16 USB3_CTX_DRX_N1 RC204 1 @ 2 0_0201_5% D
    (33) PCIE_CTX_TRX_N1 PCIE1_TXN/USB3_5_TXN USB3_1_TXN USB3_CTX_DRX_P1
    J20 J16
    (33) PCIE_CTX_TRX_P1 PCIE1_TXP/USB3_5_TXP SSIC / USB3 USB3_1_TXP
    (33) PCIE_CRX_TTX_N2 B19 B15
    D19 PCIE2_RXN/USB3_6_RXN USB3_2_RXN/SSIC_1_RXN D15
    (33) PCIE_CRX_TTX_P2 PCIE2_RXP/USB3_6_RXP USB3_2_RXP/SSIC_RXP
    F19 F15
    (33) PCIE_CTX_TRX_N2 PCIE2_TXN/USB3_6_TXN USB3_2_TXN/SSIC_TXN
    H19 H15 USB3.1 Type-C Full function (SUB/B)
    (33) PCIE_CTX_TRX_P2 PCIE2_TXP/USB3_6_TXP USB3_2_TXP/SSIC_TXP
    Alpine Ridge C22 C18
    PCIe Gen3 x 4 (33) PCIE_CRX_TTX_N3 PCIE3_RXN USB3_3_RXN USB3_CRX_DTX_N3 (37)
    (33) PCIE_CRX_TTX_P3 A22 A18 USB3_CRX_DTX_P3 (37)
    G22 PCIE3_RXP USB3_3_RXP/SSIC_2_RXP G18
    (33) PCIE_CTX_TRX_N3 PCIE3_TXN USB3_3_TXN USB3_CTX_DRX_N3 (37)
    J22 J18
    (33) PCIE_CTX_TRX_P3 PCIE3_TXP USB3_3_TXP USB3_CTX_DRX_P3 (37)

    (33) PCIE_CRX_TTX_N4 B21 B17


    D21 PCIE4_RXN USB3_4_RXN D17
    (33) PCIE_CRX_TTX_P4 PCIE4_RXP USB3_4_RXP
    F21 F17
    (33) PCIE_CTX_TRX_N4 PCIE4_TXN USB3_4_TXN
    H21 H17
    (33) PCIE_CTX_TRX_P4 PCIE4_TXP USB3_4_TXP

    (24) PCIE_CRX_DTX_N5 C24 AJ6


    PCIE5_RXN USB2N_1 USB20_N1 (35,38)
    (24) PCIE_CRX_DTX_P5 A24 AJ4 USB3.1 Type-C
    PCIE5_RXP USB2P_1 USB20_P1 (35,38)
    G24
    (24) PCIE_CTX_DRX_N5 PCIE5_TXN
    J24 AH5
    (24) PCIE_CTX_DRX_P5 PCIE5_TXP USB2N_5 USB20_N5 (35,38)
    NVMe SSD AH3 USB3.1 Type-C
    USB2P_5 USB20_P5 (35,38)
    B23
    (PICe Interface) (24) PCIE_CRX_DTX_N6
    D23 PCIE6_RXN PCIE/USB3/SATA AF5
    (24) PCIE_CRX_DTX_P6 PCIE6_RXP USB2N_7 USB20_N7 (36)
    F23 AF3 USB3.1 Type-C
    (24) PCIE_CTX_DRX_N6 PCIE6_TXN USB2 USB2P_7 USB20_P7 (36)
    M.2 SSD H23
    (24) PCIE_CTX_DRX_P6 PCIE6_TXP AL6
    PCIe Gen3 x 4 C26 USB2N_3 AL4
    USB20_N3 (23)
    C
    (24) PCIE_CRX_DTX_N7
    A26 PCIE7_RXN/SATA0_RXN USB2P_3 USB20_P3 (23) Bluetooth C
    (24) PCIE_CRX_DTX_P7 PCIE7_RXP/SATA0_RXP
    G26 AG6
    (24) PCIE_CTX_DRX_N7 PCIE7_TXN/SATA0_TXN USB2N_9 USB20_N9 (26)
    J26 AG4 IR Camera
    (24) PCIE_CTX_DRX_P7 PCIE7_TXP/SATA0_TXP USB2P_9 USB20_P9 (26)

    (24) PCIE_CRX_DTX_N8 B25 AM3


    D25 PCIE8_RXN/SATA1A_RXN USB2N_2 AM5
    (24) PCIE_CRX_DTX_P8 PCIE8_RXP/SATA1A_RXP USB2P_2
    F25
    (24) PCIE_CTX_DRX_N8 PCIE8_TXN/SATA1A_TXN USB2_COMP
    H25 N2 RC87 1 2 113_0402_1%
    (24) PCIE_CTX_DRX_P8 PCIE8_TXP/SATA1A_TXP USB2_COMP USB_ID
    AF7
    C28 USB2_ID AE6 USB2_VBUSSENSE
    (25) PCIE_CRX_DTX_N9 A28 PCIE9_RXN USB2_VBUSSENSE
    (25) PCIE_CRX_DTX_P9 G28 PCIE9_RXP N12 USB_OC0#
    (26) PCIE_CTX_DRX_N9 J28 PCIE9_TXN GPP_E9/USB2_OC0# M11 USB_OC1#
    WWAN (26) PCIE_CTX_DRX_P9 PCIE9_TXP GPP_E10/USB2_OC1# USB_OC2#
    F8
    B27 GPP_E11/USB2_OC2# B8 PRIM_CORE_OPT
    (23) PCIE_CRX_DTX_N10 PCIE10_RXN GPP_E12/USB2_OC3#
    WLAN (23) PCIE_CRX_DTX_P10 D27
    F27 PCIE10_RXP F10 DEVSLP0
    PCIe Gen2 x 1 (23) PCIE_CTX_DRX_N10 PCIE10_TXN GPP_E4/DEVSLP0 T60 TP@
    H27 H10 DEVSLP1 DEVSLP1 (24) for SATA SSD
    (23) PCIE_CTX_DRX_P10 PCIE10_TXP GPP_E5/DEVSLP1 L8
    RC88 1 2 100_0201_1% PCIE_RCOMPN A9 GPP_E6/DEVSLP2
    PCIE_RCOMPP B10 PCIE_RCOMPN G11 SATA_GP0
    PCIE_RCOMPP GPP_E0/SATAXPCIE0/SATAGP0 J11 SATA_GP1
    D51 GPP_E1/SATAXPCIE1/SATAGP1 N10 SATA_GP2
    SATA_GP1 (24) for SATA SSD
    PROC_PRDY# GPP_E2/SATAXPCIE2/SATAGP2 T371 TP@
    B55
    PCH_GPIOA7 BF3 PROC_PREQ# H8
    GPP_A7/PIRQA# GPP_E8/SATALED#
    8 OF 20
    KBL-Y_BGA1515 +3V_PRIM

    B USB_OC0# RH122 1 2 10K_0201_5% B


    USB_OC1# RH123 1 2 10K_0201_5%
    USB_OC2# RH124 1 2 10K_0201_5%
    PRIM_CORE_OPT RH125 1 2 10K_0201_5%
    DEVSLP1 RH155 1 2 10K_0201_5%
    SATA_GP0 RH469 1 2 10K_0201_5%
    PIR11 SI: pop RH125
    +3VS

    PCH_GPIOA7 RC90 1 2 10K_0201_5%


    SATA_GP2 RC569 1 @ 2 10K_0201_5%

    USB_ID RH153 1 2 1K_0201_5%


    USB2_VBUSSENSE RH154 1 2 1K_0201_5%

    +3V_PRIM

    PIR26 SI: pop UH3 , un-pop RC579

    5
    UH3
    PRIM_CORE_OPT 1

    P
    INA 4
    O PRIM_CORE_LPM (48)
    PM_SLP_S0# 2
    (9,12,29,47,49) PM_SLP_S0# INB

    G
    MC74VHC1G32DFT2G_SC70-5

    3
    A A

    RC579 2 @ 1 0_0201_5%

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2041/09/08 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL Y(7/13) PCIE,USB
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 11 of 55
    5 4 3 2 1
    5 4 3 2 1

    +1.2V_VDDQ SKYLAKE_ULX +0.85VS_VCCIO (5,18,47) +0.85VS_VCCIO +0.85VS_VCCIO


    @ UC1N +1.2V_VDDQ
    Rev0.87 (18,19,20,21,44) +1.2V_VDDQ
    (13,23,24,25,28,29,30,33,34,38,39,43,44,45,47,48,49,50) +3VALW +3VALW
    AH64 AC23 +3V_PRIM
    VDDQ VCCIO (5,7,8,9,10,11,13,24,25,26,29,30,33) +3V_PRIM
    BA27 AF24 +1.0V_VCCST
    VDDQ VCCIO (5,9,14,49) +1.0V_VCCST
    BA37 AN26
    BA49 VDDQ 1.2V@ 2A VCCIO AC24
    VDDQ VCCIO (9,13,17,46) +1.0V_PRIM +1.0V_PRIM
    BP32 AF26 +1.0VS_VCCSTG
    VDDQ VCCIO (5,14) +1.0VS_VCCSTG
    BP50 AR26
    AK64 VDDQ VCCIO AE23
    BA29 VDDQ VCCIO AH26
    BA41 VDDQ VCCIO AT26
    D D

    VDDQC trace
    BA51
    BP34
    BP56
    VDDQ
    VDDQ
    VDDQ
    VDDQ
    0.85V@3A
    VCCIO
    VCCIO
    VCCIO
    VCCIO
    AE24
    AK26
    AE26
    +3VALW TO +3V_PRIM
    filter width = 6mm AT64
    VDDQ VCCIO
    AL26
    +3VALW
    BA31
    Total etch length BA43 VDDQ AV26
    VDDQ VCCIO_DDR +3V_PRIM
    = 186.94mils BN64
    BP40 VDDQ VCCIO_DDR
    AV36
    AV46
    PDG P597 BP58 VDDQ
    VDDQ
    VCCIO_DDR
    VCCIO_DDR
    AW31

    1
    AV64 AW41
    VDDQ VCCIO_DDR

    1U_0201_6.3V6M
    CC50
    BA33 AW51
    +1.2V_VDDQ +VDDQ_CPU_CLK BA45 VDDQ VCCIO_DDR AV28

    2
    LC1 BP24 VDDQ VCCIO_DDR AV38
    VDDQ VCCIO_DDR

    0.1U_0402_25V6

    1.8P_0201_50V8J

    68P_0201_50V8J

    0.1U_0201_6.3V6K
    1 2 BP42 AV48 1 1 1 1
    VDDQ VCCIO_DDR

    CC316

    CC314

    RF@

    CC387

    RF@

    CC388

    RF@
    1NH +-0.3NH HCI1005F-1N0S BP64 AW33 UC9
    BA25 VDDQ VCCIO_DDR AW43
    1 VDDQ VCCIO_DDR
    CC9 BA35 AV30 1 7
    BA47 VDDQ VCCIO_DDR AV40 2 VIN VOUT 8 2 2 2 2
    0.1U_0201_10V6K BP26 VDDQ VCCIO_DDR AV50 VIN VOUT
    2 BP48 VDDQ VCCIO_DDR AW35 1 short@ 2 EN_3V_PRIM 3 6 CC315 1 2
    Backside cap VDDQ VCCIO_DDR (29,39,45,46,48) PCH_PW R_EN ON CT
    BA39 AW45 RC562 0_0201_5% 1000P_0402_50V7K
    VDDQC VCCIO_DDR AV32
    V26 VCCIO_DDR AV42 4
    VCCST : Sustain voltage for processor standby +1.0V_VCCST
    Y26 VCCST VCCIO_DDR AW27
    +5VALW VBIAS 5
    modes VCCST 1.0V@100mA (60mA) VCCIO_DDR GND PIR30 SI: pop CC387,CC388
    AW37 +0.85VS_VCCIO 9
    VCCIO_DDR GND

    1
    1U_0201_6.3V6M
    CC317
    VCCSTG : Gated sustain voltage for processor standby +1.0VS_VCCSTG R26 AW47
    T26 VCCSTG VCCIO_DDR AV34
    modes VCCSTG 1.0V@20mA VCCIO_DDR

    1
    AV44 SA00006U600

    2
    C AE27 VCCIO_DDR AW29 RC538 AOZ1336_DFN8_2X2 C
    +1.2V_VCCPLL_OC VCCPLL_OC VCCIO_DDR
    AF27 1.2V@100mA AW39 @ 100_0201_1%
    VCCPLL_OC VCCIO_DDR AW49
    R27 VCCIO_DDR
    +1.0V_VCCPLL

    2
    T27 VCCPLL AT24
    +1.0V_VCCST +1.0V_VCCPLL VCCPLL 1.0V@100mA VCCIO_SENSE AR24
    VCCIO_SENSE (47)
    VSSIO_SENSE VSSIO_SENSE (47)

    1
    1 short@ 2 CPU POWER 3 OF 4
    RC106 0_0201_5%
    BSC Side RC98 +1.0V_VCCST
    1
    CC280 1 14 OF 20 @ 0_0201_5%
    CC17
    0.1U_0201_10V6K KBL-Y_BGA1515 Intel recommand RON(Max) : 70m ohm

    2
    2

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K
    0.1U_0201_10V6K 1 1 1

    1
    2

    C279

    1U_0201_6.3V6M
    C285

    CC357 @RF@

    CC358 @RF@
    2
    2 2 2

    PIR8 SI: From SE000000K80 to SE00000QL10


    +1.0V_PRIM +1.0V_VCCST
    C5245 U27
    +1.0V_PRIM TO +1.0VS_VCCSTG 1U_0402_10V6K
    1 2 1 7
    tCPU26:CPU_C10_GATE# de-assertion 2 VIN VOUT 8
    VIN VOUT
    +1.0V_PRIM
    to VCCSTG stable = 10us<Tr<65us(S0i3)
    3 6 C284 1 2 1000P_0402_50V7K
    (21,29,44) SYSON ON CT @
    B B
    UC5 +1.0VS_VCCSTG +1.0VS_VCCSTG +3VALW 4
    VBIAS
    1U_0201_6.3V6M

    1 5
    A2 A1 GND 9
    VIN VOUT GND
    CC319

    B2 B1 BSC Side
    VIN VOUT
    1U_0201_6.3V6M

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    2 1 1 1 1
    CC30

    CC359 @RF@

    CC360 @RF@

    C2 C1 CC18 AOZ1336DI_DFN8_2X2
    CT PG
    SA00006U600
    0.1U_0201_10V6K
    2 @ 2 2 2
    EN_VCCSTG_VCCPLL_OC D2 D1 For Modern Standby
    ON GND +1.2V_VDDQ +1.2V_VCCPLL_OC
    UC7
    S0IX@
    S0IX@
    A2 A1 +1.1V_VCCPLL_OC RC136 1 2
    TPS22971YZPT_DSBGA8 B2 VIN VOUT B1 0_0402_5%
    VIN VOUT
    1 C2 C1
    CC320 CT PG
    RC578 1 NDSX@
    2 0_0201_5% 1U_0201_6.3V6M +1.2V_VDDQ

    2 NDSX@
    D2 D1 RC137 1 2
    ON GND 0_0402_5%
    AND GATE +3V_PRIM

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K
    SUSP# RC108 1 2 0_0201_5% BSC Side 1 1 1 1
    (29,39,44,47) SUSP#

    1U_0201_6.3V6M
    CC321

    CC337 RF@

    CC338 @RF@

    CC339 @RF@
    PM_SLP_S3# @ UC6 CC318 EN_VCCSTG_VCCPLL_OC
    RC109 1 2 0_0201_5%
    (9,29,33,39) PM_SLP_S3#
    1 6 1 2 TPS22971YZPT_DSBGA8
    A VCC 2 2 2 2
    PM_SLP_S0# RC110 1 S0IX@ 2 0_0201_5% 2 5 S0IX@ 0.1U_0201_10V6K
    A (9,11,29,47,49) PM_SLP_S0# B NC A

    3 4 EN_VCCSTG_VCCPLL_OC
    GND Y
    74LVC1G08FZ4-7_X2-DFN1410-6
    SA00007YD00
    S0IX@ Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2041/09/08 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL Y(8/13) Power
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 12 of 55
    5 4 3 2 1
    5 4 3 2 1

    (5,7,8,9,10,11,12,24,25,26,29,30,33) +3V_PRIM +3V_PRIM


    (9,12,17,46) +1.0V_PRIM +1.0V_PRIM (9) +3VL_RTC +3VL_RTC
    +1.0V_PRIM (48) +VCCPRIM_CORE +VCCPRIM_CORE (9) +3VALW _DSW +3VALW _DSW
    (8,21,26,39,45) +1.8V_PRIM +1.8V_PRIM

    1 1 1 1 1 RTC Logic Primary Well 3.3 V. This power supplies the RTC internal VRM. It will
    CC32 CC48 CC34 CC35 CC325 be off during Deep Sx mode.
    +3V_PRIM
    SKYLAKE_ULX
    0.1U_0201_10V6K 0.1U_0201_10V6K 0.1U_0201_10V6K 0.1U_0201_10V6K 0.1U_0201_10V6K @ UC1P
    2 2 2 2 2 Primary Well 1.0 V : For I/O blocks, ungated Rev0.87
    +1.0V_PRIM AH18 ISH SRAM power, USB AFE Digital Logic, AT1 1.8V/0.009A
    1.0V/0.599A AH19 VCCPRIM_1P0 JTAG, Thermal Sensor and MIPI DPHY. VCCPGPPA AU2
    Close to Pin AH18 Close to Pin AH13 Close to Pin AR21 Close to Pin AA15 Close to Pin V1 VCCPRIM_1P0 VCCPGPPA
    AK18 1.0V@ AV1 3.3V/0.004A
    AL18 VCCPRIM_1P0 DCPDSW_1P0 Deep Sx Well 1.0 V: This rail is generated by on VCCPGPPB AW2
    D VCCPRIM_1P0 VCCPGPPB D
    die DSW low dropout (LDO) linear voltage regulator to supply AH1 3.3V/0.006A
    +VCCPRIM_CORE AE18 DSW GPIOs, DSW core logic and DSW USB2 logic. Board VCCPGPPC AJ2
    DCPDSW _1P0 1.1A AE19 VCCPRIM_CORE needs to connect 1 uF capacitor to this rail and power should VCCPGPPC AF1 3.3V/0.008A
    AF18 VCCPRIM_CORE NOT be driven from the board. When primary well power is VCCPGPPD AG2
    1 VCCPRIM_CORE up, this rail is ypassed from VCCPRIM_1p0. VCCPGPPD
    +VCCPRIM_CORE AF19 AA2 3.3V/0.006A
    AR16 VCCPRIM_CORE VCCPGPPE AB1
    CC334
    VCCPRIM_CORE 1.0V/0.85V@ VCCPGPPE
    0.1U_0201_6.3V6K AT16 AN2 +1.8V_PRIM 1.8V/0.033A
    2 VCCPRIM_CORE VCCPGPPF AP1
    1 1 VCCPGPPF
    CC129 CC130 Close to Pin AL2 DCPDSW _1P0 AL2 AN15 3.3V/0.041A
    AM1 DCPDSW_1P0 VCCPGPPG AP13
    0.1U_0201_10V6K 0.1U_0201_10V6K DCPDSW_1P0 VCCPGPPG
    2 2 +1.0V_PRIM V1 Mod PHY Always On Primary 1.0 V: Always on primary AC2 +3V_PRIM
    +1.0V_PRIM 1.0V/0.022A W2 VCCMPHYAON_1P0 supply for PCIe/DMI/USB3/SATA/MIPI MPHY logic VCCPRIM_3P3 AD1 3.3V/0.075A
    Close to Pin AE18 and AR16 VCCMPHYAON_1P0 VCCPRIM_3P3
    +3V_PRIM +3VALW +3VALW _DSW
    T1 AA15 +1.0V_PRIM
    1.0V/1.6A T15 VCCMPHYGT_1P0 Mod PHY Externally Gated Primary 1.0 V: VCCPRIM_1P0 AA16 1.0V/0.599A
    R213 1 2 0_0402_5% T16 VCCMPHYGT_1P0 Externally gated primary supply for VCCPRIM_1P0 Thermal Sensor Primary Well 1.8 V
    R212 1 2 0_0402_5% +1.0V_PRIM U2 VCCMPHYGT_1P0 PCIe/DMI/USB3/SATA/MIPI MPHY logic. AE15 +1.8V_PRIM
    +1.0V_PRIM @ VCCMPHYGT_1P0 VCCATS_1P8 AE16 1.8V/0.006A RTC Well Supply. This rail can drop
    V15 Analog supply for USB3, PCIe Gen 2/Gen 3, SATA3 and VCCATS_1P8 to 2.0 V if all other planes are off.
    1.0V/0.088A V16 VCCAMPHYPLL_1P0 MIPI PLL 1.0V: This AK19 +3V_PRIM This power
    VCCAMPHYPLL_1P0 rail is from externally gated domain. Filtering required. VCCRTCPRIM_3P3 AL19 3.3V/0.001A is not expected to be shut off
    1 1 1 VCCRTCPRIM_3P3 unless the RTC battery is removed
    CC19 +1.0V_APLL AA18
    AA19 VCCAPLL_1P0 AR19 or drained.
    CC332 CC1 1.0V/0.026A Analog supply for OPI, USB2 and Audio PLL +3VL_RTC
    0.1U_0201_10V6K VCCAPLL_1P0 Primary 1.0V: Filtering required. VCCRTC AT19 3.3V/0.001A
    22U_0402_6.3V6M 0.1U_0201_6.3V6K VCCRTC
    2 2 2 +1.0V_PRIM AH13
    +3VALW _DSW 1.0V/0.599A AH15 VCCPRIM_1P0 RTC de-coupling capacitor AT18 1 2
    VCCPRIM_1P0 only. This rail should NOT DCPRTC AV18 CC326 0.1U_0201_10V6K +1.0V_PRIM
    Close to Pin T1 and T15 DCPRTC
    AL15 be driven. Close to Pin AT18
    3.3V/0.071A AM13 VCCDSW_3P3 Deep Sx Well for GPD GPIOs and USB2 V18
    1 VCCDSW_3P3 VCCCLK1
    +1.0V_PRIM CC131 Close to Pin AL15 1.0V/0.035A Y18 1.0V/0.035A
    C AT23 VCCCLK1 C
    +3V_PRIM +3V_HDA VCCHDA
    0.1U_0201_10V6K 3.3V/0.068A AV22 HD Audio Power 3.3 V, 1.8 V, 1.5 V19
    2 VCCHDA V. For Intel High Definition Audio Clock Buffers Primary 1.0 V VCCCLK2 Y19 1.0V/0.029A
    1 1 1 1 VCCCLK2
    CC285 CC284 CC281 CC286 AT15 1.0V/0.029A
    3.3V/0.011A AV15 VCCSPI SPI Primary Well 3.3 V or 1.8 V V23
    1 VCCSPI VCCCLK3
    0.1U_0201_10V6K 22U_0603_6.3V6M 0.1U_0201_10V6K 0.1U_0201_10V6K CC289 +1.0V_PRIM Clock Buffers Primary 1.0 V Y23 1.0V/0.024A
    2 2 2 2 AA21 1.0V/0.024A VCCCLK3
    0.1U_0201_10V6K 1.0V/0.565A AA23 VCCSRAM_1P0 SRAM Primary Well 1.0 V. Dedicated V21
    Close to Pin V15 2 1 VCCSRAM_1P0 SRAM rail and can have on board VCCCLK4
    Close to Pin AT15 CC29 AK23 Clock Buffers Primary 1.0 V Y21 1.0V/0.033A
    AL23 VCCSRAM_1P0 power down gate control. 1.0V/0.033A VCCCLK4
    0.1U_0201_10V6K AN23 VCCSRAM_1P0 R21
    +1.0V_PRIM 2 AR23 VCCSRAM_1P0 VCCCLK5 R23 1.0V/0.004A
    PIR7 SI: From SM01000HC00 to SM01000NY00 Close to Pin AA21 VCCSRAM_1P0
    Clock Buffers Primary 1.0 V
    VCCCLK5
    LC3 1.0V/0.004A
    1 2 +1.0V_APLL +3V_PRIM AH21 R19
    3.3V/0.075A AK21 VCCPRIM_3P3 Primary Well 3.3 V Clock Buffers Primary 1.0 V VCCCLK6 T19 1.0V/0.01A
    1 1 VCCPRIM_3P3 VCCCLK6
    BLM15PX221SN1D 1.0V/0.010A
    CC329 CC328 AR21 PCH POWER BA13
    +1.0V_PRIM VCCPRIM_1P0 GPP_B0/CORE_VID0 CORE_VID0 (48)
    22U_0402_6.3V6M 22U_0402_6.3V6M AT21 1.0V/0.599A BB12
    2 2 VCCPRIM_1P0 GPP_B1/CORE_VID1 CORE_VID1 (48)
    +1.0V_PRIM R15
    1.0V/0.033A R16 VCCAPLLEBB_1P0
    VCCAPLLEBB_1P0 16 OF 20
    PIR7 SI: From SM01000HC00 to SM01000NY00
    KBL-Y_BGA1515
    +3V_PRIM +3V_PRIM +3V_HDA PDG_place as close as ball +3VL_RTC +1.0V_PRIM
    L24
    1 2 PDG_VCCHDA design for HD Audio VCCHDA should be
    1 1 1 1 1 Close to Pin AT23 connected to 3.3V or 1.5V, or designed for I2S VCCHDA 1 1 1
    1

    CC324 CC323 CC322 CC333 CC53 2 BLM15PX221SN1D CC23 should be connected to 1.8V or 3.3V. CC327 CC290
    CC336
    0.1U_0201_10V6K 0.1U_0201_10V6K 0.1U_0201_10V6K 1U_0201_6.3V6M 0.1U_0201_10V6K CC169 0.1U_0201_10V6K 0.1U_0201_6.3V6K 0.1U_0201_10V6K 0.1U_0201_10V6K
    2

    2 2 2 2 2 2 2 2
    1
    2.2P_0201_25V Close to Pin R15
    B Close to Pin AH21 Close to Pin AC2 Close to Pin AK19 Close to Pin AK19 Close to Pin AR19 B

    +3V_PRIM
    +1.8V_PRIM +VCCPRIM_CORE
    PIR20 SI: pop Cap.
    1 1 1 1 1 1
    +1.0V_PRIM CC291 CC292 CC293 CC294 CC295 CC296
    1 1 1 1 1 1 1 1 1 1 1
    CC399 CC389 CC390 CC391 CC392 CC393 CC394 CC395 CC396 CC397 CC398 0.1U_0201_10V6K 0.1U_0201_10V6K 0.1U_0201_10V6K 0.1U_0201_10V6K 0.1U_0201_10V6K 0.1U_0201_10V6K
    RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ 2 2 2 2 2 2
    1 1 1
    CC39 CC282 Close to Pin AV1 Close to Pin AH1 Close to Pin AF1 Close to Pin AA2 Close to Pin AT1 Close to Pin AN15
    2 2 2 2 2 2 2 2 2 2 2
    68P_0201_50V8J

    68P_0201_50V8J

    68P_0201_50V8J

    0.1U_0201_6.3V6K

    0.1U_0201_6.3V6K

    68P_0201_50V8J

    68P_0201_50V8J

    68P_0201_50V8J

    0.1U_0201_6.3V6K

    0.1U_0201_6.3V6K

    0.1U_0201_6.3V6K

    CC330
    0.1U_0201_10V6K 0.1U_0201_10V6K 22U_0402_6.3V6M
    2 2 2
    Close to Pin R21
    Close to Pin V21 Close to Pin R19
    +1.8V_PRIM

    CC283 1 2 EMI@
    +1.0V_PRIM +3V_HDA
    1 1 2.2P_0201_25V
    CC297
    CC335
    0.1U_0201_10V6K 0.1U_0201_6.3V6K +1.0V_APLL CC168 1 2 EMI@
    RTC Battery FF:38.2 1
    CC24
    1
    CC38
    1
    CC331
    2 2 2.2P_0201_25V
    Close to Pin AN2 Close to Pin AE15
    Battery Module MAX. 8000mil 0.1U_0201_10V6K 0.1U_0201_10V6K 22U_0402_6.3V6M
    2 2 2

    DC1 Close to Pin V19 Close to Pin V18 Close to Pin V23
    +3V_LID W=20mils
    A 1 2 2 1 W=40mils +3VL_RTC A
    RC116 1K_0402_5% A K
    2mA

    BAT54LPS-7_X2-DFN1006-2-2
    SCS0000AO00

    +3VL DC2
    Security Classification Compal Secret Data Compal Electronics, Inc.
    2 1 2041/09/08 2013/10/28 Title
    A K Issued Date Deciphered Date
    W=20mils THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL Y(9/13) Power
    BAT54LPS-7_X2-DFN1006-2-2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    SCS0000AO00 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 13 of 55
    5 4 3 2 1
    5 4 3 2 1

    (49,50,51) +VCC_CORE +VCC_CORE


    (49,50,51) +VCC_GT +VCC_GT
    (5,9,12,49) +1.0V_VCCST +1.0V_VCCST

    +VCC_CORE +VCC_CORE +VCC_GT +VCC_GT


    SKYLAKE_ULX SKYLAKE_ULX
    @ UC1L @ UC1M
    Rev0.87 Rev0.87
    A64 M58 AA53 AC53
    AE32 VCC VCC N34 AB62 VCCGT VCCGT AC63
    AE40 VCC VCC N54 AC47 VCCGT VCCGT AD62
    AH41 VCC VCC N63 AC55 VCCGT VCCGT AE59
    AN32 VCC VCC P64 AD54 VCCGT VCCGT AF46
    D
    AT33 VCC VCC R61 AD64 VCCGT 1.5V@24A VCCGT AG53
    D

    AT41 VCC
    VCC
    1.5V@24A VCC
    VCC
    V41 AE61 VCCGT
    VCCGT
    VCCGT
    VCCGT
    AK47
    J64 AC41 AF47 AN44
    L48 VCC VCC AE38 AJ53 VCCGT VCCGT AN51
    M33 VCC VCC AH32 AK49 VCCGT VCCGT AT49
    M43 VCC VCC AL41 AN46 VCCGT VCCGT N48
    M53 VCC VCC AT32 AT43 VCCGT VCCGT T44
    M64 VCC VCC AT40 AT50 VCCGT VCCGT T51
    N40 VCC VCC H63 N50 VCCGT VCCGT U59
    N59 VCC VCC L46 T46 VCCGT VCCGT V58
    P60 VCC VCC L63 T54 VCCGT VCCGT W55
    R57 VCC VCC M41 U61 VCCGT VCCGT Y43
    T41 VCC VCC M51 V60 VCCGT VCCGT Y50
    AA32 VCC VCC M62 W57 VCCGT VCCGT Y60
    AE33 VCC VCC N38 Y44 VCCGT VCCGT AB56
    AE41 VCC VCC N57 Y51 VCCGT VCCGT AC43
    AK32 VCC VCC P58 Y62 VCCGT VCCGT AC50
    AN41 VCC VCC R41 AB54 VCCGT VCCGT AC59
    AT35 VCC VCC T32 AB64 VCCGT VCCGT AD58
    B64 VCC VCC Y41 AC49 VCCGT VCCGT AE55
    L40 VCC VCC AC32 AC57 VCCGT VCCGT AF43
    L50 VCC VCC AE36 AD56 VCCGT VCCGT AF50
    M35 VCC VCC AF41 AE53 VCCGT VCCGT AK44
    M45 VCC VCC AL32 AE63 VCCGT VCCGT AK51
    M56 VCC VCC AR41 AF49 VCCGT VCCGT AN49
    N32 VCC VCC AT38 AK43 VCCGT VCCGT AT46
    N42 VCC VCC F64 AK50 VCCGT VCCGT N44
    N61 VCC VCC L44 +VCC_CORE AN47 VCCGT VCCGT R53
    P62 VCC VCC L54 AT44 VCCGT VCCGT T49
    C
    VCC VCC PIR21 SI: un-pop RC147,RC148 VCCGT VCCGT
    C
    R59 M39 AT51 U55
    VCC VCC VCCGT VCCGT

    1
    V32 M49 R51 V54
    AA41 VCC VCC M60 RC147 T47 VCCGT VCCGT V64
    AE35 VCC VCC N36 @ U53 VCCGT VCCGT W61
    AF32 VCC VCC N55 100_0201_1% U63 VCCGT VCCGT Y47
    VCC VCC Trace Length < 25 mils VCCGT VCCGT
    AK41 V62 Y56

    2
    AR32 VCC L34 W59 VCCGT VCCGT AN50
    VCC VCC_SENSE VCCSENSE (49) VCCGT VCCGT
    AT36 L32 Y46 AT47
    VCC VSS_SENSE VSSSENSE (49) VCCGT VCCGT
    D64 Y54 N46
    VCC VCCGT VCCGT

    2
    L42 Y64 T43
    L52 VCC RC148 AB58 VCCGT VCCGT T50
    M37 VCC B58 SOC_SVID_ALERT# @ AC44 VCCGT VCCGT U57 +VCC_GT
    M47 VCC VIDALERT# A56 SOC_SVID_CLK_R 100_0201_1% AC51 VCCGT VCCGT V56
    R63 VCC VIDSCK A58 SOC_SVID_DAT_R AC61 VCCGT VCCGT W53

    1
    VCC VIDSOUT VCCGT VCCGT

    1
    P56 AD60 W63
    R32 VCC AA26 RC526 AE57 VCCGT VCCGT Y49 RC139
    Y32 VCC VCCSTG AC26 1 short@ 2 AF44 VCCGT VCCGT Y58 @
    VCC VCCSTG +1.0VS_VCCSTG VCCGT VCCGT
    AF51 AN43 Close CPU 100_0201_1%
    0_0201_5% AK46 VCCGT VCCGT

    2
    CPU POWER 1 OF 4 VCCGT
    AB60 N52
    VCCGT VCCGT_SENSE VCCGT_SENSE (49)
    AC46 P52
    12 OF 20 VCCGT VSSGT_SENSE VSSGT_SENSE (49)

    2
    KBL-Y_BGA1515 CPU POWER 2 OF 4
    Trace Length < 25 mils
    13 OF 20 RC141
    KBL-Y_BGA1515 @
    100_0201_1%

    teknisi indonesia

    1
    B B

    SVID ALERT SVID CLK


    +1.0V_VCCST
    Place the PU
    resistors close to CPU
    1

    RC142

    56_0201_5% (To VR)


    RC143 RC525
    2

    SOC_SVID_ALERT# 1 2 SOC_SVID_ALERT#_R SOC_SVID_CLK_R 1 short@ 2 SVID_CLK


    SOC_SVID_ALERT#_R (49) SOC_SVID_CLK (49)
    220_0201_5%
    0_0201_5%

    SVID DATA
    +1.0V_VCCST
    Place the PU
    resistors close to CPU
    A A
    2

    RC144

    100_0201_1% (To VR)


    RC146
    1

    SOC_SVID_DAT_R 1 short@ 2 SOC_SVID_DAT


    SOC_SVID_DAT (49) Security Classification Compal Secret Data Compal Electronics, Inc.
    0_0201_5% 2041/09/08 2013/10/28 Title
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL Y(10/13) Power
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 14 of 55
    5 4 3 2 1
    5 4 3 2 1

    D (49,50,51) +VCC_SA +VCC_SA D


    (18) +VCCCOREG0 +VCCCOREG0
    (18) +VCCCOREG1 +VCCCOREG1

    1.0V@4.1A
    +VCC_SA +VCCCOREG0
    SKYLAKE_ULX
    @ UC1O
    Rev0.87
    AA29 AA35
    AF30 VCCSA VCCG0 R38
    AN29 VCCSA VCCG0 Y35
    L30 VCCSA VCCG0 AA38
    T30 VCCSA VCCG0 T35
    AC29 VCCSA VCCG0 Y38
    AH29 VCCSA VCCG0 AC35
    AN30 VCCSA VCCG0 T38
    +VCC_SA M31 VCCSA VCCG0 AC38
    V29 VCCSA VCCG0 V35
    AC30 VCCSA VCCG0 R35
    AK29 VCCSA VCCG0 V38 +VCCCOREG1
    CC59 AR29 VCCSA VCCG0
    2 CC60 2 CC61 1 VCCSA
    C @ N30 AF35 C
    Y29 VCCSA VCCG1 AK38
    VCCSA VCCG1

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    22U_0603_6.3V6M
    AE29 AR35
    1 1 2 AK30 VCCSA VCCG1 AF38
    R29 VCCSA VCCG1 AL35
    +VCC_SA Y30 VCCSA VCCG1 AR38
    AF29 VCCSA VCCG1 AH35
    AL29 VCCSA VCCG1 AL38
    VCCSA VCCG1

    1
    T29 AH38
    RC149 VCCSA VCCG1 AN35
    AT29 VCCG1 AK35
    100_0201_1% AT30 VCCSA_DDR VCCG1 AN38
    2 VCCSA_DDR VCCG1

    (49) VCCSA_SENSE M29


    N28 VCCSA_SENSE
    (49) VSSSA_SENSE VSSSA_SENSE
    2

    CPU POWER 4 OF 4
    RC150
    15 OF 20
    100_0201_1% KBL-Y_BGA1515
    1

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2041/09/08 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL Y(11/13) Power
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 15 of 55
    5 4 3 2 1
    5 4 3 2 1

    SKYLAKE_ULX SKYLAKE_ULX SKYLAKE_ULX


    @ UC1Q @ UC1R @ UC1S
    D Rev0.87 Rev0.87 Rev0.87 D
    A14 K23 BH20 AR50 AF33 R46
    AA36 VSS VSS K33 BH32 VSS VSS AT27 AF58 VSS VSS R6
    AA47 VSS VSS K43 BH42 VSS VSS AU59 AH16 VSS VSS T23
    AA57 VSS VSS K53 BH52 VSS VSS AV24 AH33 VSS VSS T56
    AC15 VSS VSS L61 BJ47 VSS VSS AW21 AH46 VSS VSS V13
    AC27 VSS VSS N20 BL1 VSS VSS AY26 AH54 VSS VSS V36
    AE10 VSS VSS R10 BL47 VSS VSS AY36 AK15 VSS VSS V47
    AE43 VSS VSS R24 BM18 VSS VSS AY46 AK33 VSS VSS Y11
    AE50 VSS VSS R40 BN6 VSS VSS BA1 AK7 VSS VSS Y27
    AF16 VSS VSS R49 BP38 VSS VSS BA58 AL27 VSS VSS Y5
    AF40 VSS VSS T13 BP60 VSS VSS BB22 AL43 VSS VSS BB26
    AF62 VSS VSS T33 E16 VSS VSS BB32 AL50 VSS VSS BB36
    AH24 VSS VSS T60 E26 VSS VSS BB42 AM64 VSS VSS BB46
    AH40 VSS VSS V27 E36 VSS VSS BB52 AN24 VSS VSS BB59
    AH49 VSS VSS V43 E46 VSS VSS BC47 AN59 VSS VSS BD38
    AK1 VSS VSS V50 E56 VSS VSS BE12 AR15 VSS VSS BE31
    AK24 VSS VSS Y15 J3 VSS VSS BE47 AR33 VSS VSS BF38
    AK40 VSS VSS Y33 K15 VSS VSS BG12 AR44 VSS VSS BG17
    AL16 VSS VSS Y9 K25 VSS VSS BG4 AR51 VSS VSS BG63
    AL33 VSS VSS AA24 K35 VSS VSS BH22 AT54 VSS VSS BH26
    AL46 VSS VSS AA40 K45 VSS VSS BH34 AU61 VSS VSS BH38
    AL53 VSS VSS AA49 K55 VSS VSS BH44 AV52 VSS VSS BH48
    AN18 VSS VSS AA59 M3 VSS VSS BH54 AW23 VSS VSS BH59
    AN33 VSS VSS AC16 N22 VSS VSS BJ62 AY28 VSS VSS BK38
    AP64 VSS VSS AC33 R30 VSS VSS BL29 AY38 VSS VSS BL33
    AR2 VSS VSS AE2 R43 VSS VSS BL8 AY48 VSS VSS BM14
    AR4 VSS VSS AE44 R50 VSS VSS BM20 BA11 VSS VSS BN29
    AR47 VSS VSS AE51 T18 VSS VSS BP22 BA64 VSS VSS BP30
    C AR6 VSS VSS AF21 T36 VSS VSS BP44 BB24 VSS VSS BP52 C
    AU55 VSS VSS AF54 T62 VSS VSS D6 BB34 VSS VSS C40
    AV16 VSS VSS AF64 V30 VSS VSS E18 BB44 VSS VSS D8
    AW17 VSS VSS AH27 V44 VSS VSS E28 BB54 VSS VSS E22
    AY16 VSS VSS AH43 V51 VSS VSS E38 BD20 VSS VSS E32
    AY32 VSS VSS AH50 Y16 VSS VSS E48 BE29 VSS VSS E42
    AY42 VSS VSS AK11 Y36 VSS VSS E59 BF20 VSS VSS E52
    AY52 VSS VSS AK27 Y7 VSS VSS J5 BG15 VSS VSS G14
    BA5 VSS VSS AK5 AA27 VSS VSS K17 BG6 VSS VSS J7
    BA9 VSS VSS AL21 AA43 VSS VSS K27 BH24 VSS VSS K21
    BB28 VSS VSS AL36 AA50 VSS VSS K37 BH36 VSS VSS K31
    BB38 VSS VSS AL47 AA61 VSS VSS K47 BH46 VSS VSS K41
    BB48 VSS VSS AL59 AC18 VSS VSS L14 BH56 VSS VSS K51
    BC17 VSS VSS AN19 AC36 VSS VSS N14 BK20 VSS VSS L59
    BD56 VSS VSS AN36 AE21 VSS VSS N24 BL31 VSS VSS N18
    BE33 VSS VSS AR10 AE46 VSS VSS R33 BM11 VSS VSS P54
    BF56 VSS VSS AR27 AE8 VSS VSS R44 BM38 VSS VSS R2
    BG2 VSS VSS AR40 AF23 VSS VSS R55 BP28 VSS VSS R4
    BG8 VSS VSS AR49 AF56 VSS VSS T21 BP46 VSS VSS R47
    BH28 VSS VSS AR8 AG59 VSS VSS T40 C14 VSS VSS R8
    BH40 VSS VSS AU57 AH30 VSS VSS T64 D62 VSS VSS T24
    BH50 VSS VSS AV20 AH44 VSS VSS V33 E20 VSS VSS T58
    BJ29 VSS VSS AW19 AH51 VSS VSS V46 E30 VSS VSS Y3
    BK56 VSS VSS AY24 AK13 VSS VSS Y1 E40 VSS VSS AA33
    BL35 VSS VSS AY34 AK3 VSS VSS Y24 E50 VSS VSS AA46
    BM16 VSS VSS AY44 AK54 VSS VSS Y40 F62 VSS VSS AA55
    BP36 VSS VSS BA53 AL24 VSS VSS AA30 J62 VSS VSS AB13
    BP54 VSS VSS BB20 AL40 VSS VSS AA44 K19 VSS VSS AC21
    D10 VSS VSS BB30 AL49 VSS VSS AA51 K29 VSS VSS AD13
    B E14 VSS VSS BB40 AM54 VSS VSS AA63 K39 VSS VSS AE4 B
    E24 VSS VSS BB50 AN21 VSS VSS AC19 K49 VSS VSS AE49
    E34 VSS VSS BC29 AN40 VSS VSS AC40 L57 VSS VSS AF15
    E44 VSS VSS BD63 AR12 VSS VSS AE30 N16 VSS VSS AF36
    E54 VSS VSS BE35 AR30 VSS VSS AE47 N26 VSS VSS AF60
    J14 VSS VSS BF59 AR43 VSS VSS AF13 R18 VSS VSS AH23
    J9 VSS VSS BG29 AP54 VSS VSS AU53 R36 VSS VSS BP1
    AH47 VSS VSS AL30 AR18 VSS VSS AU63 AY40 VSS VSS A5
    AJ59 VSS VSS AL44 AR36 VSS VSS AV54 V49 VSS VSS D1
    AK16 VSS VSS AL51 AR46 VSS VSS AW25 Y13 VSS VSS
    AK36 VSS VSS AN16 AR59 VSS VSS AY30 AH36 VSS BP62
    AK9 VSS VSS AN27 BA3 VSS VSS AY50 V40 VSS VSS
    V24 VSS VSS BA7 VSS VSS VSS
    GND 3 OF 3
    VSS VSS
    GND 1 OF 3 GND 2 OF 3 19 OF 20
    KBL-Y_BGA1515
    17 OF 20 18 OF 20
    KBL-Y_BGA1515 KBL-Y_BGA1515

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2041/09/08 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL Y(12/13) GND
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 16 of 55
    5 4 3 2 1
    5 4 3 2 1

    D D

    SKYLAKE_ULX
    @ UC1T
    Rev0.87
    G52 BL64
    F53 CFG[0] RSVD_TP BG47
    J52 CFG[1] RSVD_TP
    +1.0V_PRIM H53 CFG[2] BA17
    CFG4 H55 CFG[3] RSVD_TP AY18
    XDP_ITP_PMODE 1 @ 2 D55 CFG[4] RSVD_TP
    RC567 1K_0201_5% C56 CFG[5] BF18
    F55 CFG[6] RSVD BE19
    D61 CFG[7] RSVD
    G58 CFG[8]
    D57 CFG[9] BA23
    F61 CFG[10] TP5 AY22
    J60 CFG[11] TP6
    J58 CFG[12]
    H61 CFG[13] R12
    H59 CFG[14] RSVD P13
    CFG[15] RSVD M15
    J54 RSVD L16
    G54 CFG[16] RSVD
    CFG[17] L18
    G56 RSVD M17
    J56 CFG[18] RSVD
    CFG[19] AH7
    C RC151 2 1 49.9_0402_1% CFG_RCOMP A54 RSVD C
    CFG_RCOMP K12
    XDP_ITP_PMODE A60 RSVD H12
    ITP_PMODE RSVD
    RC152 1 2 1K_0201_1% CFG4 B4 BN3
    B3 RSVD RSVD BP3
    RSVD RSVD
    F3 L22
    F1 RSVD RSVD M23
    Functional Strap Definitions RSVD RSVD
    L36 BN1
    L38 RSVD TP4
    RSVD AY20
    CFG[4] : Display Port Presence strap BA19 RSVD BA21
    0 = Enabled - A Display Port device is connected to the Embedded Display Port. BB18 RSVD RSVD
    No connect for disable. RSVD BB14 RC153 1 short@ 2 0_0201_5%
    BC19 RSVD
    1 = Disabled - No Physical Display Port attached to Embedded DisplayPort*. BD18 RSVD M25
    Pull-down to GND through a 1 K? +-5% resistor to enable port. RSVD RSVD L24
    D49 RSVD
    M21 RSVD L28
    L20 RSVD RSVD M27
    M19 RSVD RSVD
    RSVD BJ15
    L26 TP1 BJ17
    RSVD RESERVED SIGNALS TP2

    20 OF 20
    KBL-Y_BGA1515
    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2041/09/08 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL Y(13/13) RSVD
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 17 of 55
    5 4 3 2 1
    A B C D E

    (15) +VCCCOREG0 +VCCCOREG0


    (15) +VCCCOREG1 +VCCCOREG1
    (12,19,20,21,44) +1.2V_VDDQ +1.2V_VDDQ
    (5,12,47) +0.85VS_VCCIO +0.85VS_VCCIO

    1 1
    +VCCCOREG0 +1.2V_VDDQ

    2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
    CC62 CC63 CC64 CC65 CC66 CC67 CC68 CC69 CC70 CC71 CC72 CC73 CC74 CC75 CC76 CC77 CC78 CC79 CC80 CC81 CC82 CC83 CC84 CC85 CC86 CC87 CC88 CC89 CC90 CC91

    1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K
    Backside cap Backside cap

    +VCCCOREG1 +0.85VS_VCCIO +0.85VS_VCCIO

    PIR8 SI: From SE000000K80 to SE00000QL10


    2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 2
    CC92 CC93 CC94 CC95 CC96 CC97 CC98 CC99 CC100 CC101 CC102 CC103 CC104 CC105 CC106 CC107 CC108 CC109 CC110 CC111 CC112 CC113 CC114 CC115 CC116 CC117 CC118
    @
    1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2
    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    1U_0402_10V6K

    22U_0603_6.3V6M
    Backside cap Backside cap Primary side
    cap

    +0.85VS_VCCIO +1.2V_VDDQ
    PIR19 SI: pop Cap. PIR19 SI: pop Cap.

    2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
    CC365 CC363 CC362 CC369 CC368 CC366 CC361 CC367 CC364 CC370 CC349 CC345 CC341 CC354 CC355 CC350 CC340 CC353 CC346 CC356
    3 RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ 3

    1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K
    PIR18 SI: Add CC400~CC404
    PIR19 SI: pop Cap. close to CC379~CC383

    1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
    CC374 CC375 CC376 CC377 CC378 CC379 CC380 CC381 CC382 CC383 CC400 CC401 CC402 CC403 CC404
    RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@
    2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
    68P_0201_50V8J

    68P_0201_50V8J

    68P_0201_50V8J

    68P_0201_50V8J

    68P_0201_50V8J

    0.1U_0201_6.3V6K

    0.1U_0201_6.3V6K

    0.1U_0201_6.3V6K

    0.1U_0201_6.3V6K

    0.1U_0201_6.3V6K

    12P_0201_50V8J

    12P_0201_50V8J

    12P_0201_50V8J

    12P_0201_50V8J

    12P_0201_50V8J
    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2041/09/08 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SKL Y -PROCESSOR DECOUPLING
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 18 of 55
    A B C D E
    5 4 3 2 1

    (12,18,20,21,44) +1.2V_VDDQ +1.2V_VDDQ


    UD1A
    (20,21) +1.8V_MEM +1.8V_MEM
    R114 1 @ 2 243_0201_1% C11 C8
    M0_A_ZQ0 NC CK_C_A M_CLK_A_DDR#0 (6)
    R115 1 2 243_0201_1% B11 B8 +VREFCA
    ZQ0_A CK_T_A M_CLK_A_DDR0 (6) (20,21) +VREFCA
    R116 1 @ 2 243_0201_1% E3 H2 +VREFDQ_A
    M0_B_ZQ0 NC CK_C_B M_CLK_A_DDR#1 (6) (21) +VREFDQ_A
    R110 1 2 243_0201_1% E2 H3
    ZQ0_B CK_T_B M_CLK_A_DDR1 (6)

    D D
    B5
    (6) DDR_A_CAA_0 C5 CA0_A C7 +1.8V_MEM +1.2V_VDDQ
    (6) DDR_A_CAA_1 CA1_A CKE0_A DDR_A_CKE0 (6)
    D5 D7
    (6) DDR_A_CAA_2 CA2_A NC DDR_A_CKE1 (6) UD1C
    B6
    (6) DDR_A_CAA_3 CA3_A
    C6 A15 A6
    (6) DDR_A_CAA_4 CA4_A VDD1_0 VDDCA0
    C9 J3 A16 A9
    (6) DDR_A_CAA_5 D9 CA5_A CKE0_B J4 DDR_A_CKE2 (6) B2 VDD1_1 VDDCA1 B9
    (6) DDR_A_CAA_6 CA6_A NC DDR_A_CKE3 (6) VDD1_2 VDDCA2
    B10 R1 E1
    (6) DDR_A_CAA_7 C10 CA7_A D6 T1 VDD1_3 VDDCA3 G2
    (6) DDR_A_CAA_8 CA8_A CS0_N_A DDR_A_CS0# (6) VDD1_4 VDDCA4
    D10 B7 +1.2V_VDDQ T16 K1
    (6) DDR_A_CAA_9 CA9_A NC DDR_A_CS1# (6) VDD1_5 VDDCA5 +1.2V_VDDQ

    K4 DDR_A_CS0# A7 A13
    CS0_N_B J2 DDR_A_CS1# A11 VDD2_0 VDDQ0 B12
    L2 NC B17 VDD2_1 VDDQ1 C12
    (6) DDR_A_CAB_0 CA0_B VDD2_2 VDDQ2
    L3 C3 E17
    (6) DDR_A_CAB_1 CA1_B VDD2_3 VDDQ3
    L4 C17 G12
    (6) DDR_A_CAB_2 CA2_B VDD2_4 VDDQ4
    K2 N6 H1 G17
    (6) DDR_A_CAB_3 CA3_B DM0_A VDD2_5 VDDQ5
    K3 P8 H16 U14
    (6) DDR_A_CAB_4 CA4_B DM1_A VDD2_6 VDDQ6
    G3 P4 L1 K12
    (6) DDR_A_CAB_5 CA5_B DM2_A VDD2_7 VDDQ7
    G4 P11 R15 K17
    (6) DDR_A_CAB_6 CA6_B DM3_A VDD2_8 VDDQ8
    F2 T8 L17
    (6) DDR_A_CAB_7 CA7_B VDD2_9 VDDQ9
    F3 U2 M2
    (6) DDR_A_CAB_8 CA8_B VDD2_10 VDDQ10
    F4 H14 U3 M3
    (6) DDR_A_CAB_9 CA9_B DM0_B VDD2_11 VDDQ11
    F13 M7
    DM1_B L14 D8 VDDQ12 M10
    N8 DM2_B D14 D11 RFU0 VDDQ13 M12
    (6) DDR_A_ODT0 ODT_A DM3_B RFU1 VDDQ14
    H13 E4 N1
    ODT_B H4 RFU2 VDDQ15 P17
    J12 RFU3 VDDQ16 U5
    M9 RFU4 VDDQ17 U7
    RFU5 VDDQ18 U10
    N4 L15 VDDQ19 U11
    (6) DDR_A_D33 DQ0_A DQ0_B DDR_A_D5 (6) VDDQ20
    (6) DDR_A_D34 T5 L16 DDR_A_D0 (6)
    R5 DQ1_A DQ1_B K13 +VREFCA
    C (6) DDR_A_D35 DQ2_A DQ2_B DDR_A_D7 (6) C
    P5 K14
    32-39 (6)
    (6)
    DDR_A_D38
    DDR_A_D36 N5
    T6
    DQ3_A
    DQ4_A
    DQ3_B
    DQ4_B
    K15
    K16
    DDR_A_D6
    DDR_A_D4
    (6)
    (6) 0-7 A1
    A17 NC0 VREF_CA_A
    A10
    J1
    (6) DDR_A_D39 DDR_A_D1 (6)

    0.047U_0402_25V7K

    0.047U_0402_25V7K
    R6 DQ5_A DQ5_B J15 U1 NC1 VREF_CA_B +VREFDQ_A
    (6) DDR_A_D37 DQ6_A DQ6_B DDR_A_D3 (6) NC2

    1
    (6) DDR_A_D32 P6 J16 DDR_A_D2 (6) U17
    T9 DQ7_A DQ7_B F14 NC3 U8 C4057 C4058
    (6) DDR_A_D56 DQ8_A DQ8_B DDR_A_D29 (6) VREF_DQ_A
    (6) DDR_A_D61 R9 F15 DDR_A_D30 (6) H17

    0.047U_0402_25V7K

    0.047U_0402_25V7K

    2
    T10 DQ9_A DQ9_B F16 VREF_DQ_B
    (6) DDR_A_D60 DQ10_A DQ10_B DDR_A_D31 (6)

    1
    R10 E13
    56-63 (6)
    (6)
    DDR_A_D58
    DDR_A_D57 P10 DQ11_A
    DQ12_A
    DQ11_B
    DQ12_B
    E14
    DDR_A_D24
    DDR_A_D28
    (6)
    (6)
    24-31 H9CCNNN8KTMLBR-NTM FBGA C4059 C4060
    (6) DDR_A_D59 N10 E15 DDR_A_D27 (6) @

    2
    T11 DQ13_A DQ13_B E16
    (6) DDR_A_D63 DQ14_A DQ14_B DDR_A_D26 (6)
    (6) DDR_A_D62 R11 D13 DDR_A_D25 (6)
    T2 DQ15_A DQ15_B P15
    (6) DDR_A_D55 DQ16_A DQ16_B DDR_A_D22 (6)
    (6) DDR_A_D51 R2 P16 DDR_A_D23 (6)
    P2 DQ17_A DQ17_B N14
    (6) DDR_A_D52 DQ18_A DQ18_B DDR_A_D21 (6)
    (6) DDR_A_D49 N2 N15 DDR_A_D18 (6)
    T3 DQ19_A DQ19_B N16
    48-55 (6)
    (6)
    DDR_A_D54
    DDR_A_D53 R3 DQ20_A
    DQ21_A
    DQ20_B
    DQ21_B
    M13
    DDR_A_D19
    DDR_A_D16
    (6)
    (6) 16-23
    (6) DDR_A_D50 P3 M14 DDR_A_D17 (6)
    N3 DQ22_A DQ22_B L13
    (6) DDR_A_D48 DQ23_A DQ23_B DDR_A_D20 (6)
    (6) DDR_A_D40 N11 C13 DDR_A_D10 (6)
    N12 DQ24_A DQ24_B C14
    (6) DDR_A_D41 DQ25_A DQ25_B DDR_A_D11 (6)
    (6) DDR_A_D44 P12 C15 DDR_A_D13 (6)
    T13 DQ26_A DQ26_B C16
    (6) DDR_A_D43 DDR_A_D9 (6)
    40-47 (6)
    (6)
    DDR_A_D45
    DDR_A_D46
    R13
    P13
    T14
    DQ27_A
    DQ28_A
    DQ29_A
    DQ27_B
    DQ28_B
    DQ29_B
    B13
    B14
    B15
    DDR_A_D15
    DDR_A_D14
    (6)
    (6) 8-15 follow 561280_KBL UY PDG Rev2_0, remove RTT & VTT
    (6) DDR_A_D42 DQ30_A DQ30_B DDR_A_D12 (6)
    (6) DDR_A_D47 R14 B16 DDR_A_D8 (6)
    DQ31_A DQ31_B

    N7 J13
    (6) DDR_A_DQS#4 DQS0_C_A DQS0_C_B DDR_A_DQS#0 (6)
    P7 J14
    B
    (6) DDR_A_DQS4 DQS0_T_A DQS0_T_B DDR_A_DQS0 (6) UD1B B
    A2 G16
    A3 VSS0 VSS34 H5
    N9 G13 A4 VSS1 VSS35 H12
    (6) DDR_A_DQS#7 DQS1_C_A DQS1_C_B DDR_A_DQS#3 (6) VSS2 VSS36
    P9 G14 A5 H15
    (6) DDR_A_DQS7 DQS1_T_A DQS1_T_B DDR_A_DQS3 (6) VSS3 VSS37
    A8 J5
    A12 VSS4 VSS38 K5
    A14 VSS5 VSS39 L5
    B1 VSS6 VSS40 L12
    R4 M15 B3 VSS7 VSS41 M1
    (6) DDR_A_DQS#6 DQS2_C_A DQS2_C_B DDR_A_DQS#2 (6) VSS8 VSS42
    T4 M16 B4 M4
    (6) DDR_A_DQS6 DQS2_T_A DQS2_T_B DDR_A_DQS2 (6) VSS9 VSS43
    C1 M5
    C2 VSS10 VSS44 M6
    C4 VSS11 VSS45 M8
    D1 VSS12 VSS46 M11
    R12 D15 D2 VSS13 VSS47 M17
    (6) DDR_A_DQS#5 DQS3_C_A DQS3_C_B DDR_A_DQS#1 (6) VSS14 VSS48
    T12 D16 D3 N13
    (6) DDR_A_DQS5 DQS3_T_A DQS3_T_B DDR_A_DQS1 (6) VSS15 VSS49
    D4 N17
    D12 VSS16 VSS50 P1
    D17 VSS17 VSS51 P14
    E5 VSS18 VSS52 R7
    E6 VSS19 VSS53 R8
    E7 VSS20 VSS54 R16
    H9CCNNN8KTMLBR-NTM FBGA VSS21 VSS55
    E8 R17
    @ E9 VSS22 VSS56 T7
    E10 VSS23 VSS57 T15
    E11 VSS24 VSS58 T17
    E12 VSS25 VSS59 U4
    F1 VSS26 VSS60 U6
    F5 VSS27 VSS61 U9
    F12 VSS28 VSS62 U12
    F17 VSS29 VSS63 U13
    G1 VSS30 VSS64 U15
    G5 VSS31 VSS65 U16
    G15 VSS32 VSS66 J17
    VSS33 VSS67
    A A

    H9CCNNN8KTMLBR-NTM FBGA
    @

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2015/10/22 Deciphered Date 2017/10/22 Title
    LPDDR3 (CH0)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 19 of 55
    5 4 3 2 1
    5 4 3 2 1

    (12,18,19,21,44) +1.2V_VDDQ +1.2V_VDDQ

    (19,21) +1.8V_MEM +1.8V_MEM

    (19,21) +VREFCA +VREFCA

    UD2A +1.8V_MEM +1.2V_VDDQ


    R121 1 @ 2 243_0201_1% C11 C8
    D
    M1_A_ZQ0 NC CK_C_A M_CLK_B_DDR#0 (6) UD2C D
    R122 1 2 243_0201_1% B11 B8
    ZQ0_A CK_T_A M_CLK_B_DDR0 (6)
    A15 A6
    R124 1 @ 2 243_0201_1% E3 H2 A16 VDD1_0 VDDCA0 A9
    M1_B_ZQ0 NC CK_C_B M_CLK_B_DDR#1 (6) VDD1_1 VDDCA1
    R126 1 2 243_0201_1% E2 H3 B2 B9
    ZQ0_B CK_T_B M_CLK_B_DDR1 (6) VDD1_2 VDDCA2
    R1 E1
    T1 VDD1_3 VDDCA3 G2
    B5 T16 VDD1_4 VDDCA4 K1
    (6) DDR_B_CAA_0 C5 CA0_A C7 VDD1_5 VDDCA5
    +1.2V_VDDQ +1.2V_VDDQ
    (6) DDR_B_CAA_1 D5 CA1_A CKE0_A D7 DDR_B_CKE0 (6)
    (6) DDR_B_CAA_2 CA2_A NC DDR_B_CKE1 (6)
    B6 A7 A13
    (6) DDR_B_CAA_3 C6 CA3_A A11 VDD2_0 VDDQ0 B12
    (6) DDR_B_CAA_4 C9 CA4_A J3 B17 VDD2_1 VDDQ1 C12
    (6) DDR_B_CAA_5 CA5_A CKE0_B DDR_B_CKE2 (6) VDD2_2 VDDQ2
    D9 J4 C3 E17
    (6) DDR_B_CAA_6 CA6_A NC DDR_B_CKE3 (6) VDD2_3 VDDQ3
    B10 C17 G12
    (6) DDR_B_CAA_7 CA7_A VDD2_4 VDDQ4
    C10 D6 H1 G17
    (6) DDR_B_CAA_8 D10 CA8_A CS0_N_A B7 DDR_B_CS0# (6) H16 VDD2_5 VDDQ5 U14
    (6) DDR_B_CAA_9 CA9_A NC DDR_B_CS1# (6) L1 VDD2_6 VDDQ6 K12
    R15 VDD2_7 VDDQ7 K17
    K4 DDR_B_CS0# T8 VDD2_8 VDDQ8 L17
    CS0_N_B J2 DDR_B_CS1# U2 VDD2_9 VDDQ9 M2
    NC VDD2_10 VDDQ10

    Vinafix.com
    L2 U3 M3
    (6) DDR_B_CAB_0 L3 CA0_B VDD2_11 VDDQ11 M7
    (6) DDR_B_CAB_1 CA1_B VDDQ12
    L4 D8 M10
    (6) DDR_B_CAB_2 CA2_B RFU0 VDDQ13
    K2 N6 D11 M12
    (6) DDR_B_CAB_3 CA3_B DM0_A RFU1 VDDQ14
    K3 P8 E4 N1
    (6) DDR_B_CAB_4 G3 CA4_B DM1_A P4 H4 RFU2 VDDQ15 P17
    (6) DDR_B_CAB_5 CA5_B DM2_A RFU3 VDDQ16
    G4 P11 J12 U5
    (6) DDR_B_CAB_6 CA6_B DM3_A RFU4 VDDQ17
    F2 M9 U7
    (6) DDR_B_CAB_7 CA7_B RFU5 VDDQ18
    F3 U10
    (6) DDR_B_CAB_8 CA8_B VDDQ19
    F4 H14 U11
    (6) DDR_B_CAB_9 CA9_B DM0_B F13 VDDQ20
    DM1_B L14 +VREFCA
    N8 DM2_B D14
    (6) DDR_B_ODT0 ODT_A DM3_B
    H13 A1 A10
    ODT_B A17 NC0 VREF_CA_A J1

    0.047U_0402_25V7K

    0.047U_0402_25V7K
    C U1 NC1 VREF_CA_B +VREFDQ_B C
    NC2

    1
    U17
    NC3 U8 C4061 C4062
    N4 L15 VREF_DQ_A H17
    (6) DDR_B_D28 DDR_B_D35 (6)

    0.047U_0402_25V7K

    0.047U_0402_25V7K

    2
    T5 DQ0_A DQ0_B L16 VREF_DQ_B
    (6) DDR_B_D25 DQ1_A DQ1_B DDR_B_D38 (6)

    1
    (6) DDR_B_D31 R5 K13 DDR_B_D34 (6)
    P5 DQ2_A DQ2_B K14 C4063 C4064
    (6) DDR_B_D29 DQ3_A DQ3_B DDR_B_D33 (6) H9CCNNN8KTMLBR-NKM_FBGA253
    N5 K15
    24-31 (6) DDR_B_D24 DDR_B_D32 (6)
    32-39

    2
    T6 DQ4_A DQ4_B K16 @
    (6) DDR_B_D30 DQ5_A DQ5_B DDR_B_D37 (6)
    (6) DDR_B_D27 R6 J15 DDR_B_D36 (6)
    P6 DQ6_A DQ6_B J16
    (6) DDR_B_D26 DQ7_A DQ7_B DDR_B_D39 (6)
    (6) DDR_B_D60 T9 F14 DDR_B_D6 (6)
    R9 DQ8_A DQ8_B F15
    (6) DDR_B_D61 DQ9_A DQ9_B DDR_B_D2 (6)
    (6) DDR_B_D58 T10 F16 DDR_B_D4 (6)
    R10 DQ10_A DQ10_B E13
    56-63 (6)
    (6)
    DDR_B_D63
    DDR_B_D57 P10 DQ11_A
    DQ12_A
    DQ11_B
    DQ12_B
    E14
    DDR_B_D0
    DDR_B_D3
    (6)
    (6) 0-7
    (6) DDR_B_D56 N10 E15 DDR_B_D7 (6)
    T11 DQ13_A DQ13_B E16
    (6) DDR_B_D59 DQ14_A DQ14_B DDR_B_D5 (6)
    (6) DDR_B_D62 R11 D13 DDR_B_D1 (6)
    T2 DQ15_A DQ15_B P15
    (6) DDR_B_D50 DQ16_A DQ16_B DDR_B_D9 (6)
    (6) DDR_B_D54 R2 P16 DDR_B_D15 (6)
    P2 DQ17_A DQ17_B N14
    (6) DDR_B_D53 DDR_B_D12 (6)
    48-55 (6)
    (6)
    DDR_B_D51
    DDR_B_D55
    N2
    T3
    R3
    DQ18_A
    DQ19_A
    DQ20_A
    DQ18_B
    DQ19_B
    DQ20_B
    N15
    N16
    M13
    DDR_B_D14
    DDR_B_D11
    (6)
    (6)
    8-15
    follow 561280_KBL UY PDG Rev2_0, remove RTT & VTT
    (6) DDR_B_D52 DQ21_A DQ21_B DDR_B_D10 (6)
    (6) DDR_B_D48 P3 M14 DDR_B_D8 (6)
    N3 DQ22_A DQ22_B L13
    (6) DDR_B_D49 DQ23_A DQ23_B DDR_B_D13 (6)
    (6) DDR_B_D20 N11 C13 DDR_B_D42 (6)
    N12 DQ24_A DQ24_B C14 UD2B
    (6) DDR_B_D23 DQ25_A DQ25_B DDR_B_D46 (6)
    (6) DDR_B_D19 P12 C15 DDR_B_D41 (6) A2 G16
    T13 DQ26_A DQ26_B C16 A3 VSS0 VSS34 H5
    (6)
    (6)
    DDR_B_D22
    DDR_B_D21 R13
    P13
    DQ27_A
    DQ28_A
    DQ27_B
    DQ28_B
    B13
    B14
    DDR_B_D40
    DDR_B_D47
    (6)
    (6) 40-47 A4
    A5
    VSS1
    VSS2
    VSS35
    VSS36
    H12
    H15
    16-23 (6)
    (6)
    DDR_B_D17
    DDR_B_D18 T14 DQ29_A
    DQ30_A
    DQ29_B
    DQ30_B
    B15
    DDR_B_D43
    DDR_B_D45
    (6)
    (6) A8 VSS3
    VSS4
    VSS37
    VSS38
    J5
    (6) DDR_B_D16 R14 B16 DDR_B_D44 (6) A12 K5
    B DQ31_A DQ31_B A14 VSS5 VSS39 L5 B
    B1 VSS6 VSS40 L12
    B3 VSS7 VSS41 M1
    B4 VSS8 VSS42 M4
    N7 J13 C1 VSS9 VSS43 M5
    (6) DDR_B_DQS#3 P7 DQS0_C_A DQS0_C_B J14 DDR_B_DQS#4 (6) C2 VSS10 VSS44 M6
    (6) DDR_B_DQS3 DQS0_T_A DQS0_T_B DDR_B_DQS4 (6) VSS11 VSS45
    C4 M8
    D1 VSS12 VSS46 M11
    D2 VSS13 VSS47 M17
    N9 G13 D3 VSS14 VSS48 N13
    (6) DDR_B_DQS#7 P9 DQS1_C_A DQS1_C_B G14 DDR_B_DQS#0 (6) D4 VSS15 VSS49 N17
    (6) DDR_B_DQS7 DQS1_T_A DQS1_T_B DDR_B_DQS0 (6) VSS16 VSS50
    D12 P1
    D17 VSS17 VSS51 P14
    E5 VSS18 VSS52 R7
    E6 VSS19 VSS53 R8
    R4 M15 E7 VSS20 VSS54 R16
    (6) DDR_B_DQS#6 DQS2_C_A DQS2_C_B DDR_B_DQS#1 (6) VSS21 VSS55
    T4 M16 E8 R17
    (6) DDR_B_DQS6 DQS2_T_A DQS2_T_B DDR_B_DQS1 (6) VSS22 VSS56
    E9 T7
    E10 VSS23 VSS57 T15
    E11 VSS24 VSS58 T17
    E12 VSS25 VSS59 U4
    R12 D15 F1 VSS26 VSS60 U6
    (6) DDR_B_DQS#2 DQS3_C_A DQS3_C_B DDR_B_DQS#5 (6) VSS27 VSS61
    T12 D16 F5 U9
    (6) DDR_B_DQS2 DQS3_T_A DQS3_T_B DDR_B_DQS5 (6) VSS28 VSS62
    F12 U12
    F17 VSS29 VSS63 U13
    G1 VSS30 VSS64 U15
    G5 VSS31 VSS65 U16
    G15 VSS32 VSS66 J17
    VSS33 VSS67
    H9CCNNN8KTMLBR-NKM_FBGA253
    @ H9CCNNN8KTMLBR-NKM_FBGA253
    @

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2015/10/22 Deciphered Date 2017/10/22 Title
    LPDDR3 (CH1)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 20 of 55
    5 4 3 2 1
    5 4 3 2 1

    <LPDDR3_A_DQ> <LPDDR3_B_DQ> <LPDDR3_A_CA>


    <LPDDR3_B_CA> (12,18,19,20,44) +1.2V_VDDQ +1.2V_VDDQ

    (19,20) +1.8V_MEM +1.8V_MEM


    +1.2V_VDDQ +0.6V_A_VREFDQ +1.2V_VDDQ +0.6V_B_VREFDQ +1.2V_VDDQ +0.6V_VREFCA
    (19,20) +VREFCA +VREFCA

    1
    RD97 RD111 RD113
    8.2K_0201_1% (20) +VREFDQ_B +VREFDQ_B
    8.2K_0201_1% 8.2K_0201_1%

    D 2 D

    2
    RD100 +VREFDQ_A
    (19) +VREFDQ_A
    +VREFDQ_A 1 RD99 2 +VREFDQ_B 1 RD115 2 +VREFCA 1 2
    10_0201_1% 1 10_0201_1% 1 5.11_0402_1% 1

    1
    CD248 CD122 CD249
    1

    0.022U_0201_10V5R RD112 0.022U_0201_10V5R RD114 0.022U_0201_10V5R


    2 2 2
    RD110 8.2K_0201_1% PIR6 SI: change from 6.3V to 10V 8.2K_0201_1% PIR6 SI: change from 6.3V to 10V

    1
    8.2K_0201_1% PIR6 SI: change from 6.3V to 10V
    RD103 RD108 RD104

    2
    24.9_0402_1%
    2

    2 24.9_0402_1% 24.9_0402_1%

    2
    VDDQ DECAPS
    VDD1 DECAPS
    C C
    +1.2V_VDDQ +1.2V_VDDQ
    +1.2V_VDDQ
    +1.8V_MEM +1.8V_MEM
    CD10

    CD250

    CD170

    CD251

    CD171

    CD252

    CD196

    CD253

    CD197

    CD254

    CD198

    CD255

    CD199

    CD256

    CD200

    CD257

    CD246

    10U_0402_6.3V6M

    CD244

    10U_0402_6.3V6M

    CD245

    10U_0402_6.3V6M

    CD247

    10U_0402_6.3V6M

    CD236

    10U_0402_6.3V6M
    CD237

    10U_0402_6.3V6M
    CD238

    10U_0402_6.3V6M
    CD239

    10U_0402_6.3V6M
    CD240

    10U_0402_6.3V6M
    CD241

    10U_0402_6.3V6M
    CD242

    10U_0402_6.3V6M
    CD243

    10U_0402_6.3V6M

    CD211

    10U_0402_6.3V6M
    CD212

    10U_0402_6.3V6M
    CD213

    10U_0402_6.3V6M
    CD214

    10U_0402_6.3V6M
    CD215

    10U_0402_6.3V6M
    CD216

    10U_0402_6.3V6M
    CD217

    10U_0402_6.3V6M
    CD218

    10U_0402_6.3V6M
    1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
    @RF@

    @RF@

    @RF@

    @RF@

    @RF@

    @RF@

    @RF@

    @RF@

    1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

    2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
    10U_0402_6.3V6M

    68P_0201_50V8J

    10U_0402_6.3V6M

    68P_0201_50V8J

    10U_0402_6.3V6M

    68P_0201_50V8J

    10U_0402_6.3V6M

    68P_0201_50V8J

    10U_0402_6.3V6M

    68P_0201_50V8J

    10U_0402_6.3V6M

    68P_0201_50V8J

    10U_0402_6.3V6M

    68P_0201_50V8J

    10U_0402_6.3V6M

    68P_0201_50V8J

    2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

    B B

    +1.8V_PRIM TO +1.8V_MEM
    Imax : 0.38 A
    UD5 +1.8V_MEM
    +1.8V_PRIM
    @
    A2 A1 +1.8V_MEM_OUT 1 2
    1 2 VIN VOUT RD30 0_0402_5%
    CD169 1U_0201_6.3V6M 1
    CD168 @
    1U_0201_6.3V6M
    SYSON RD28 1 @ 2 0_0402_5% 2
    (12,29,44) SYSON PM_SLP_S4# RD29 1 2 0_0402_5% B2 B1
    (9,29) PM_SLP_S4# EN GND

    G5178BBE1U_W LCSP2X2-4
    I (Max) : 0.38 A (95mA x4 pcs)
    RON(Max) : 130m ohm @ 1.8V
    V drop : 0.05 V(2.74%)

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2015/10/22 Deciphered Date 2017/10/22 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    LPDDR3 VREF
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-F803P 0.1
    Date: Friday, June 08, 2018 Sheet 21 of 55
    5 4 3 2 1
    5 4 3 2 1

    (27,29,30,39) +5VS +5VS


    @ESD@
    ESD request
    DV1
    (5,7,9,10,11,24,27,29,31,36,37,39,47,48) +3VS +3VS
    I2C_1_SCL_TS 1 1 10 9 I2C_1_SCL_TS

    eDP Control:1.2/4.12 I2C_1_SDA_TS 2 2 9 8 I2C_1_SDA_TS

    P
    TS_RST# 4 4 7 7 TS_RST#

    TS_STOP# 5 5 6 6 TS_STOP#

    D 3 3 D

    H
    RV9
    1 @ 2 TS_INT#_R 8
    <CPU> (5) TS_INT#
    0_0201_5% CV14

    r
    1
    68P_0201_25V8 L05ESDL5V0NA-4_SLP2510P8-10-9
    @RF@ SC300002C00

    fo
    2

    <EC CTRL> (29) EC_BKOFF#


    RV12
    1 @

    0_0201_5%
    2

    1
    RV15
    DISPOFF#
    I (Max) : 2A
    RON(Max) : 70m ohm
    V drop : 0.14 V(=2.8%)

    +5VALW TO +5VS_SUB
    PIR38 SI: Remove +5VS_SUB
    PV: delete +5V_SUB critical

    u i t
    For IR camera & HP AMP

    c
    10K_0201_5%

    r
    2

    <CPU> (5) SOC_BKL_PW M RV16 1 2 0_0201_5%


    @CPUPW M@
    INVTPW M

    l ci C

    ia
    1

    RV17
    Head phone AMP JLCD1
    @ 100K_0201_5% GNDA

    t
    40 45
    (27) PLUG_IN# 39 40 G5 44
    (27) HP_OUT_L
    2

    38 39 G4 43
    (27) HP_OUT_R 38 G3

    n
    37 42
    36 37 G2 41
    (27) INT_MIC 36 G1
    PV: remove TS_INT#_EC 35
    35

    e
    PV: change from TS_PWREN_PCH to PLT_RST# PV: delete +5V_SUB critical 34
    33 34
    RV30 1 2 0_0201_5% W W AN_PLT_RST# 32 33
    (9,23,24,29,31,33) PLT_RST# (29) IR_GPIO 32

    id
    SOC_DMIC_DATA0_R 31
    SOC_DMIC_CLK0_R 30 31
    PV: delete TS_PWREN_EC 30
    I2C_1_SDA_TS 29
    (10) I2C_1_SDA_TS 29
    I2C_1_SCL_TS 28
    (10) I2C_1_SCL_TS 28

    f
    Touch Screen TS_INT#_R 27
    EDP_HPD TS_RST# 26 27
    <CPU> (5) EDP_HPD PV: delete TS_RST#_PCH 26
    TS_STOP# 25
    25

    n
    RV28 1 2 0_0201_5% TS_RST# W W AN_PLT_RST# 24
    (29) TS_RST#_EC 24
    1

    23
    (5,29) SOC_ENBKL 23
    RV19 22
    (5) SOC_ENVDD 22
    21

    co
    100K_0201_5% PV: delete TS_STOP#_PCH INVTPW M
    21
    EDP_HPD RV10 1 @ 2 0_0201_5% +3VS_EDP_HPD 20
    B RV26 1 2 0_0201_5% TS_STOP# 19 20 B
    (29) TS_STOP#_EC Pin swap.
    2

    DISPOFF# 18 19
    EDP_AUXN 17 18
    (5) EDP_AUXN EDP_AUXP 17
    16
    (5) EDP_AUXP 16
    15
    EDP_TXP0 14 15
    (5) EDP_TXP0 EDP_TXN0 14
    13

    L
    SOC_DMIC_DATA0_R (5) EDP_TXN0 13
    (8) SOC_DMIC_DATA0 RA59 1 2 0_0402_5% 12
    EDP_TXP1 11 12
    (5) EDP_TXP1 EDP_TXN1 11
    10
    SOC_DMIC_CLK0_R (5) EDP_TXN1 10
    (8) SOC_DMIC_CLK0 BLM15PX221SN1D 2 1 LA5 9
    9

    A
    EMI@ EDP_TXP2 8
    (5) EDP_TXP2 EDP_TXN2 8
    7
    (5) EDP_TXN2 EDP_TXP3 7
    6
    (5) EDP_TXP3 EDP_TXN3 6
    RA60 1 2 0_0402_5% 5

    P
    (27) CODEC_DMIC_DATA (5) EDP_TXN3 5
    4
    +3VL 3 4
    eDP capacitor move to Sub/B
    LID_SW 1# 3
    (27) CODEC_DMIC_CLK BLM15PX221SN1D 2 1 LA11 2
    EMI@ (29) LID_SW 1# 1 2
    1

    M
    1 1 2 2 1 CV32
    100P_0201_25V7K ACES_50398-04041-001

    0.1U_0201_10V6K
    CC372 @RF@

    0.1U_0201_10V6K
    CC373 @RF@
    CV25 CV26 RF@ CONN@
    22P_0201_25V8 22P_0201_25V8 RV29 1 2 100K_0201_5%
    @RF@ 2 2 @EMI@ 1 1 2

    EDP_AUXN
    EDP_AUXP
    C
    22P_0201_25V8 2
    22P_0201_25V8 2
    O
    @RF@
    1 CV28
    1 CV29

    @RF@
    Security Classification
    Issued Date 2017/03/20
    Compal Secret Data
    Deciphered Date 2020/03/20 Title
    Compal Electronics, Inc.
    A

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    LVDS/eDP CONN
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    LA-F803P 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, June 08, 2018 Sheet 22 of 55
    5 4 3 2 1
    5 4 3 2 1

    +3VS_WLAN (12,13,24,25,28,29,30,33,34,38,39,43,44,45,47,48,49,50) +3VALW +3VALW

    FF:30.3

    1
    10K_0201_5%
    RN1

    10K_0201_5%
    RN19

    10K_0201_5%
    RN20
    +3VS_WLAN @
    CLKREQ_PCIE#3_WLAN
    +3VS_WLAN
    UN1

    1
    4
    5 3.3V 2 S1

    P
    72 3.3V 29 EC_PCIE_WAKE#_WLAN 2 1 EC_PCIE_WAKE# G1
    D1 6 CLKREQ_PCIE#3
    3.3V PEWAKE# CLKREQ_PCIE#3_WLAN CLKREQ_PCIE#3 EC_PCIE_WAKE# (29) EC_PCIE_WAKE#_WLAN
    73 30 0_0201_5% 2 1 RN2 CLKREQ_PCIE#3 (9)
    4
    3.3V CLKREQ# 31 PLT_RST#_WLAN 0_0201_5% 2 1 RN3 PLT_RST# 5 S2

    PERST# PLT_RST# (9,22,24,29,31,33) G2


    0_0201_5% RN14 D2

    D
    1 DMN63D8LV-7_SOT563-6 D

    3
    UIM_POWER_SRC/GPIO1

    H
    2 27 SUSCLK SUSCLK (9) QN1
    3 UIM_POWER_SNK SUSCLK(32KHZ)
    UIM_SWP @ EC_PCIE_WAKE#
    14
    0_0201_5% 2 1 RN24 WLAN_COEX1 11 SYSCLK/GNSS0 15

    r
    (10,26) COEX1 WLAN_COEX2 COEX1 TX_BLANKING/GNSS1
    0_0201_5% 2 1 RN25 12
    (10,26) COEX2 2 1 RN26 WLAN_COEX3 13 COEX2 +3VALW
    0_0201_5%
    (10,26) COEX3 COEX3 +3VALW +3VS_WLAN
    7
    NFC_RESET#
    To WWAN module.

    fo
    16
    18 RESERVED/VDDIO18
    RESERVED/ISH2_UART_RXD(I)(0/1.8V) 1@ 1@ 1@ 1
    19 6 CN3 @ JPHW10
    RESERVED/ISH2_UART_TXD(O)(0/1.8V) GND

    10U_0402_6.3V6M
    CN4

    4.7U_0402_6.3V6M
    CN1

    0.1U_0201_6.3V6K
    CN2
    66 17 0.1U_0201_6.3V6K 1 2
    67 RESERVED/ISH2_UART_RTS(O)(0/1.8V) GND 20 @ 1 2
    RESERVED/ISH2_UART_CTS(I)(0/1.8V) GND 23 2 2 2 2 JUMP_43X79
    21 GND 26

    t
    22 ISH1_UART_CTS(I)(0/1.8V) GND 32
    ISH1_UART_RTS(O)(0/1.8V) GND UN2
    24 35

    i
    25 ISH1_UART_RXD(I)(0/1.8V) GND 38
    ISH1_UART_TXD(O)(0/1.8V) GND 41 A2 A1
    GND 62 VIN VOUT
    CLK_PCIE_N3 33 GND 68

    u
    (9) CLK_PCIE_N3 CLK_PCIE_P3 REFCLKN0 GND
    34 71 CN5 CN6 CN14 CN15
    (9) CLK_PCIE_P3 REFCLKP0 GND

    CN8

    0.1U_0201_6.3V6K

    CN9

    0.01U_0402_16V7K

    10P_0201_50V8J
    74 1 1 1 1 CN10 1 1 1
    GND

    0.1U_0201_6.3V6K

    0.01U_0402_16V7K

    10U_0402_6.3V6M

    10U_0402_6.3V6M
    PCIE_CRX_DTX_N10 36 75

    ri c
    (11) PCIE_CRX_DTX_N10 PCIE_CRX_DTX_P10 PETN0 GND
    37 76
    (11) PCIE_CRX_DTX_P10 PETP0 GND WLAN_PWR_EN WLAN_PWR_EN_R
    77 (29) WLAN_PWR_EN
    2 1 B2 B1 RF@
    PCIE_CTX_DRX_N10 CN12 1 2 0.1U_0201_6.3V6K PCIE_CTX_C_DRX_N10 39 GND 78 0_0201_5% RN15 EN GND 2 2 2 2 2 2 2
    (11) PCIE_CTX_DRX_N10 PCIE_CTX_DRX_P10 PERN0 GND
    CN13 1 2 0.1U_0201_6.3V6K PCIE_CTX_C_DRX_P10 40 79
    (11) PCIE_CTX_DRX_P10 PERP0 GND 80 (9) SLP_WLAN#
    2 @ 1
    GND 81 0_0201_5% RN16 G5192DB11U_WLCSP4
    42 GND 82
    CLINK_CLK GND I (Max) : 2A
    43 83
    CLINK_DATA GND RON(Max) : 43m ohm @3.6V

    c
    44 84
    C-LINK is for Intel AMT CLINK_RESET GND 85 V drop : 0.086 V(=2.6%)
    C GND 86 C
    45 GND 87
    SDIO_RESET#(I) GND +3VALW TO +3VS_WLAN

    l
    46 88
    47 SDIO_WAKE#(O) GND 89
    48 SDIO_DATA3(IO)/WIGIG_UART_RXD(I) GND 90
    49 SDIO_DATA2(IO)/WIGIG_UART_TDX(O) GND 91

    a
    SDIO is not support for JfP 50 SDIO_DATA1(IO)/WIGIG_UART_RTS(O)
    SDIO_DATA0(IO)/WIGIG_UART_CTS(I)
    GND
    GND
    92 Spec:3.3V +/-0.165V , 2A.
    51 93
    Rise time:<10ms

    i
    52 SDIO_CMD(IO) GND 94
    SDIO_CLK(I) GND 95
    Max ripple:200mV,10-500KHz

    t
    53 GND 96
    UART WAKE#(3.3V) GND
    54
    55 LPSS_UART_CTS GND
    97
    98 Noise:300mV
    56 LPSS_UART_TXD GND 99
    Co-Lay

    n
    57 LPSS_UART_RXD GND 100
    LPSS_UART_RTS GND 101
    GND 102
    GND

    e
    58 103
    59 PCM_SYNC/I2S_WS GND 104 RN8 1 2 0_0402_5%
    60 PCM_IN/I2S_SD_IN GND 105
    61 PCM_OUT/I2S_SD_OUT GND 106 RN9 1 2 0_0402_5%
    PCM_CLK/I2S_SCK GND

    id
    107
    GND 108
    WLAN_TRANSMIT_OFF# 28 GND LN1
    (8) WLAN_TRANSMIT_OFF# BT_ON W_DISABLE1# USB20_P3_R
    63 (11) USB20_P3
    1 2
    (8) BT_ON W_DISABLE2#

    f
    +3VS_WLAN RN10 1 2 10K_0201_5%
    65 4 3 USB20_N3_R
    LED1# (11) USB20_N3
    RN21 1 2 10K_0201_5% 64
    LED2# DLP11TB800UL2L_4P

    n
    @RF@
    USB20_N3_R 69
    USB20_P3_R 70 USB_D-
    USB_D+

    o
    8
    B 9 ALERT# B
    10 I2C_CLK
    I2C_DATA

    c
    PK32000HP00 W/L_BT 8265.D2WMLG.NVH _ 953395 0FH

    A L
    P
    A

    O M A

    C Security Classification
    Issued Date 2017/03/20

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Compal Secret Data
    Deciphered Date 2020/03/20 Title

    Size Document Number


    Compal Electronics, Inc.

    LA-F803P
    WLAN+BT
    Rev
    0.1

    Date: Friday, June 08, 2018 Sheet 23 of 55


    5 4 3 2 1
    5 4 3 2 1

    (5,7,9,10,11,27,29,31,36,37,39,47,48) +3VS +3VS

    +3VS_SSD

    D
    It inverted the PCIe lane polarity of pin41 and pin43
    for PCIe/SATA auto switchable.

    (11) PCIE_CRX_DTX_N5
    (11) PCIE_CRX_DTX_P5
    PCIE_CRX_DTX_N5
    PCIE_CRX_DTX_P5
    1
    3
    5
    7
    9
    JSSD1
    GND
    GND
    PERn3
    PERp3
    3.3VAUX
    3.3VAUX
    N/C
    N/C
    2
    4
    6
    8
    10

    H P D

    r
    CS11 1 2 0.22U_0201_6.3V6MPCIE_CTX_C_DRX_N5 11 GND DAS/DSS# 12
    (11) PCIE_CTX_DRX_N5 PETn3 3.3VAUX
    CS12 1 2 0.22U_0201_6.3V6MPCIE_CTX_C_DRX_P5 13 14
    (11) PCIE_CTX_DRX_P5 PETp3 3.3VAUX
    15 16

    fo
    PCIE_CRX_DTX_N6 17 GND 3.3VAUX 18
    (11) PCIE_CRX_DTX_N6 PCIE_CRX_DTX_P6 PERn2 3.3VAUX
    19 20 DEVSLP1 1 @ 2
    (11) PCIE_CRX_DTX_P6 PERp2 N/C
    21 22 RS46 10K_0201_5%
    CS13 1 2 0.22U_0201_6.3V6MPCIE_CTX_C_DRX_N6 23 GND N/C 24
    (11) PCIE_CTX_DRX_N6 PETn2 N/C
    (11) PCIE_CTX_DRX_P6 CS14 1 2 0.22U_0201_6.3V6MPCIE_CTX_C_DRX_P6 25 26 RF@
    27 PETp2 N/C 28 CLKREQ_PCIE#2 CS25 1 2 10P_0201_25V8

    t
    PCIE_CRX_DTX_N7 29 GND N/C 30
    (11) PCIE_CRX_DTX_N7 PERn1 N/C

    i
    PCIE_CRX_DTX_P7 31 32
    (11) PCIE_CRX_DTX_P7 PERp1 N/C
    33 34
    CS21 1 2 0.22U_0201_6.3V6MPCIE_CTX_C_DRX_N7 35 GND N/C 36
    (11) PCIE_CTX_DRX_N7 PETn1 N/C
    CS22 1 2 0.22U_0201_6.3V6MPCIE_CTX_C_DRX_P7 37 38

    u
    (11) PCIE_CTX_DRX_P7 PETp1 DEVSLP DEVSLP1 (11)
    39 40
    PCIE_CRX_DTX_P8 41 GND N/C 42
    (11) PCIE_CRX_DTX_P8 PCIE_CRX_DTX_N8 PERn0/SATA B+ N/C

    c
    43 44
    (11) PCIE_CRX_DTX_N8 PERp0/SATA B- N/C
    45 46
    CS23 1 2 0.22U_0201_6.3V6MPCIE_CTX_C_DRX_N8 47 GND N/C 48

    r
    (11) PCIE_CTX_DRX_N8 PETn0/SATA A- N/C
    (11) PCIE_CTX_DRX_P8 CS24 1 2 0.22U_0201_6.3V6MPCIE_CTX_C_DRX_P8 49 50 PLT_RST#_SSD 0_0201_5% 2 @ 1 RS20 PLT_RST# (9,22,23,29,31,33)
    PETp0/SATA A+ PERST#

    ci
    51 52 CLKREQ_PCIE#2
    CLK_PCIE_N2 GND CLKREQ# NGFF_SSD_W AKE#_R 0_0201_5% 2 CLKREQ_PCIE#2 (9)
    53 54 @ 1 RS47
    (9) CLK_PCIE_N2 REFCLKn PEWake# NGFF_SSD_W AKE# (10)
    CLK_PCIE_P2 55 56
    (9) CLK_PCIE_P2 REFCLKp N/C
    57 58
    GND N/C
    C C
    +3V_PRIM 67 68

    l
    69 N/C SUSCLK 70
    1 2 71 PEDET 3.3VAUX 72
    GND 3.3VAUX

    ia
    RS22 100K_0201_5% 73 74
    GND 3.3VAUX
    2

    75
    RS21 GND
    100K_0201_5% SSD_PDET 77 76

    t
    MTG77 MTG76
    1

    1 @ 2
    (11) SATA_GP1

    n
    RS49 0_0201_5% LOTES_APCI0146-P008A
    2

    1 @EMI@ CONN@
    DS1

    e
    CK0402101V05_0402-2
    2

    id
    1

    QS1
    3 PJE138K 1N SOT-523-3

    f
    SB00001KM00

    n
    I (Max) : 3 A
    RON(Max) : 43m ohm @ 3.6V
    V drop : 0.129V (=3.9%)

    o
    +3VS +3VALW
    B +3VS_SSD B
    US1

    A2
    VIN VOUT
    A1

    c
    2

    RS48

    L
    100K_0201_5%
    1

    (10) NGFF_SSD_PW REN B2 B1


    EN GND

    G5192DB11U_W LCSP4

    +3VS_SSD
    P A
    M 1
    CS7 CS8 CS9
    1 1
    1
    10U_0603_6.3V6M

    0.1U_0201_10V6K

    1U_0201_6.3V6M

    O
    1 CS5 1 CS6 RF@ CS10
    10P_0201_25V8
    2

    2 2 2
    68P_0201_50V8J

    68P_0201_50V8J

    RF@ RF@

    C
    A A
    2 2

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2017/03/20 Deciphered Date 2020/03/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    NGFF_M.2_SSD
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 24 of 55
    5 4 3 2 1
    5 4 3 2 1

    +3VALW
    FF:32.3 +3VALW _W W AM

    +3V_PRIM
    0_0402_5%

    UW 1
    2

    @
    1
    RW 35

    Imax:40mA
    +3VALW _W W AM

    CW 21 1

    CW 22 1

    H P
    2 0.01U_0201_6.3V7K

    2 0.1U_0201_6.3V6K
    D

    A2
    VIN VOUT
    A1

    r
    CW 23 1 2 1U_0201_6.3V6M

    2
    fo
    R5802
    10K_0201_5%
    I (Max) : 0.04A
    RON(Max) : 95m ohm @ 3.6V

    1
    V drop : 0.0038 V(=0.12%)

    t
    W W AN_PW REN B2 B1
    (7) W W AN_PREN EN GND
    +3VALW TO +3VALW_WWAM
    G5178BBE1U_W LCSP2X2-4

    PV: un-pop RW35, UW1/R5802 pop

    u i
    r c
    C

    From module
    +3VALW _W W AM

    l ci C

    ia
    UW 4

    t
    1 8 W W AN_DE
    VCC DE
    0.47U_0402_6.3V6K 2 1 CW 17 PCIE_CRX_RD_DTX_P9 2 7 PCIE_CRX_C_RD_DTX_P9 0.22U_0402_6.3V6K 2 1 CW 19
    (26) PCIE_CRX_C_DTX_P9 RX+ TX+ PCIE_CRX_DTX_P9 (11)

    n
    0.47U_0402_6.3V6K 2 1 CW 18 PCIE_CRX_RD_DTX_N9 3 6 PCIE_CRX_C_RD_DTX_N9 0.22U_0402_6.3V6K 2 1 CW 20
    (26) PCIE_CRX_C_DTX_N9 RX- TX- PCIE_CRX_DTX_N9 (11)

    e
    W W AN_EQ 4 5
    EQ GND
    9
    GPAD

    id To CPU
    1

    1
    51_0402_1%
    RW37

    51_0402_1%
    RW36

    SN75LVPE801DRFR_W SON8_2X2

    f
    2

    o n B

    L c PIR5 SI: WWAN Pcie change EQ setting

    P A +3VALW _W W AM +3VALW _W W AM
    1

    1
    RW 6 RW 18
    @ 10K_0201_5% @ 10K_0201_5%

    M
    2

    2
    W W AN_EQ W W AN_DE
    1

    RW 7 1 RW 19

    O
    10K_0201_5% 10K_0201_5%
    2

    A A

    C Security Classification
    Issued Date 2017/03/20
    Compal Secret Data
    Deciphered Date 2020/03/20

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Title

    Size
    Compal Electronics, Inc.

    Document Number
    Custom
    PCIe redriver
    LA-F803P
    Rev
    0.1

    Date: Friday, June 08, 2018 Sheet 25 of 55


    5 4 3 2 1
    A B C D E

    +1.8V_PRIM

    +3V_PRIM

    PV: UW2 move to sub/B

    1
    2
    RW 32
    100K_0201_5%
    1

    2
    UW 3

    NC1

    A
    @
    VCC

    NC2
    6

    H P 1

    1
    W W AN_ASPM_CTRL 2 1 W W AN_PCIE_RESET# 3 4 @

    r
    (8) W W AN_ASPM_CTRL GND Y
    0_0201_5% RW 3 RW 38 RW 31
    @ 100K_0201_5% 100K_0201_5%
    74AUP1G07FZ4-7_X2-DFN1410-6
    To Module 50pin

    fo
    SA00007YE00

    2
    t
    W W AN_RESET# 2 1 W W AN_RESET#_CONN

    i
    (10) W W AN_RESET#
    0_0201_5% RW 34
    To Module 67pin

    PV: delete RW29

    ri c u
    +8.4VB

    RV32 1 @ 2 0_0805_5%
    +8.4VB_CONN

    c
    RV33 1 @ 2 0_0805_5%
    2 2
    RV34 1 @ 2 0_0805_5%
    To Module 54pin
    (10) W W AN_W AKE#

    RC483 reserved PU
    W W AN_W AKE#
    0_0201_5%
    2 1
    RW 5
    W W AN_W AKE#_A

    i a l RV35 1 @ 2 0_0805_5%

    40
    JW W AN1

    40 G5
    45

    t
    39 44
    38 39 G4 43
    1 1 38 G3
    RF@ RF@ 37 42
    37 G2

    n
    CW 25 CW 24 36 41
    35 36 G1
    68P_0201_50V8J 68P_0201_25V8 35
    2 2 34
    34

    e
    33
    32 33
    31 32
    PV: add SUB_EN To EC (29,49) SMB_BS_CLK 31

    id
    30
    2 @ 1 (29,49) SMB_BS_DATA 29 30
    (43) 5V_3V_EN 29
    0_0201_5% RW 40 28
    2 1 (29) BATT_SHIP# W W AN_PW REN 27 28
    (29) SUB_EN (7) W W AN_PW REN 27

    f
    0_0201_5% RW 39 26
    (7) CAMERA_PW REN 26
    25
    USB20_P9_R 24 25
    24

    n
    USB20_N9_R 23
    PCIE_CTX_DRX_P9 22 23
    From CPU (11) PCIE_CTX_DRX_P9
    (11) PCIE_CTX_DRX_N9
    PCIE_CTX_DRX_N9 21 22
    20 21

    co
    PCIE_CRX_C_DTX_P9 19 20
    3 To Redriver (25) PCIE_CRX_C_DTX_P9
    (25) PCIE_CRX_C_DTX_N9
    PCIE_CRX_C_DTX_N9 18 19 3
    17 18
    CLK_PCIE_P1 16 17
    (9) CLK_PCIE_P1 CLK_PCIE_N1 16
    15
    (9) CLK_PCIE_N1 15
    14
    W W AN_PCIE_RESET# 13 14
    12 13

    L
    (9) CLKREQ_PCIE#1 W W AN_W AKE#_A 12
    11
    W W AN_SAR 10 11

    IR Camera
    (29) W W AN_SAR W W AN_RESET#_CONN 10
    9
    W W AN_DISABLE# 8 9
    (7) W W AN_DISABLE# 8

    A
    7
    (10,23) COEX1 7
    6
    (10,23) COEX2 6
    EMI@ 5
    LV1 (10,23) COEX3 ISH_I2C_0_SCL 5
    4

    P
    USB20_N9_R (10) ISH_I2C_0_SCL ISH_I2C_0_SDA 4
    1 2 3
    (11) USB20_N9 1 2 (10) ISH_I2C_0_SDA 3
    2
    (10) INT1_A_G 1 2
    4 3 USB20_P9_R (10) INT2_A_G 1
    (11) USB20_P9 4 3
    ACES_50398-04041-001

    M
    DLM0NSN900HY2D_4P CONN@
    SM070005U00

    C O
    PIR14 SI: remove D6
    Security Classification
    Issued Date 2017/03/20
    Compal Secret Data
    Deciphered Date 2020/03/20 Title
    FF:32.3
    Compal Electronics, Inc.
    4

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    WWAN CONN
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 26 of 55
    A B C D E
    5 4 3 2 1

    FF:10.6 RTD3 support +3VS_AUDIO

    1 @
    Codec IO power
    2
    +DVDD
    Codec HDA-link power
    +3VDS_AUDIO

    1 2
    +3VS_AUDIO

    LA1

    0.1U_0201_6.3V6K
    CA1

    10U_0402_6.3V6M
    CA2

    0.1U_0201_6.3V6K
    CA3

    10U_0402_6.3V6M
    CA4
    RA3 SUPPRE_ KC FBMA-10-100505-101T 0402

    P
    0_0603_5% 1 1 1 1 PCB Footprint = R_0402

    +5VS_AVDD
    UA1 2 2 2 2
    D D

    H
    INT_MIC_R 33 3
    5VSTB/AUX_MODE DVDD +DVDD
    18
    DVDD_IO +3VDS_AUDIO
    30
    GNDA MIC2_L/RING2
    RA4 1 2 2.2K_0201_5% INT_MIC_R 31 40 Place near Pin3 Place near Pin18
    +5VS_AVDD

    r
    MIC2_R/SLEEVE AVDD1 20
    AVDD2 +1.8VS_AVDD
    29
    28 MIC2_VREFO_R 41
    +MIC2_VREFO MIC2_VREFO_L PVDD1 +5VS_PVDD
    CA5 1 2 10U_0402_6.3V6M AMIC2_CAP 32 46

    fo
    GNDA MIC2_CAP PVDD2
    To SPK Amp 45
    (28) I2S_MCLK_R
    I2S_MCLK_R RA1 1 2 33_0201_5% I2S_MCLK 11
    I2S_MCLK/GPIO3
    SPK_OUT_R+
    SPK_OUT_R-
    44 SPK_OUT_R+ (28)
    SPK_OUT_R- (28)
    Codec ADCs/DACs power
    I2S_BCLK_R RA2 1 2 33_0201_5% I2S_BCLK 10 +1.8VS_AVDD +1.8VS_AUDIO
    (28) I2S_BCLK_R I2S_OUT_R I2S_OUT I2S_BCLK/DSD-SCLK
    RA5 1 2 33_0201_5% 9 42
    (28) I2S_OUT_R I2S_LRCK_R I2S_LRCK I2S_OUT/DSD-R SPK_OUT_L+ SPK_OUT_L+ (28)
    RA6 1 2 33_0201_5% 12 43 1 @ 2
    (28) I2S_LRCK_R I2S_IN_R I2S_IN I2S_LRCK/DSD-L SPK_OUT_L- SPK_OUT_L- (28)
    RA7 1 2 8

    t
    33_0201_5% 2014-09-18: HP_OUT
    (28) I2S_IN_R I2S_IN With Headphone Amp. : 0 ohm

    0.1U_0201_6.3V6K
    CA13

    10U_0402_6.3V6M
    CA14
    CA6

    CA7

    CA8

    CA9

    CA10

    No Amp. : 75 or 100 ohm LA3


    0_0402_5%

    i
    1 1 1 1 1 1 2
    RA8 1 @ 2 0_0201_5% 7 26 HPOUT_R RA9 1 2 33_0201_5% HP_OUTR
    (28,29) EC_SMB_CK3 I2C_CLK HPOUT_R HPOUT_L HP_OUTL
    RA10 1 @ 2 0_0201_5% 6 27 RA11 1 2 33_0201_5% Headphone
    (28,29) EC_SMB_DA3 I2C_DATA HPOUT_L
    22P_0201_25V8

    22P_0201_25V8

    22P_0201_25V8

    22P_0201_25V8

    22P_0201_25V8

    2 2 2 2 2 2 1

    u
    17
    AUDIOLINK:SDATA_OUT HDA_SDIN0_R RA12 1 HDA_SDOUT_R (8)
    35 16 2 33_0201_5%
    LINE2_R AUDIOLINK:SDATA_IN HDA_SDIN0 (8)
    36 CA93 1 2 2.2P_0201_25V

    c
    LINE2_L 14 HDA_BIT_CLK_R
    AUDIOLINK:BCLK
    MP@
    HDA_BIT_CLK_R (8) Place near Pin20
    RA14 1 2 100K_0201_5% CA15 1 @ 2 22P_0201_25V8
    GNDA

    r
    GNDA CA16 1 2 4.7U_0402_6.3V6M LDO1_CAP 39 2 PDB RA15 1 @ 2 0_0201_5%
    CA17 1 2 10U_0402_6.3V6M LDO2_CAP 21 LDO1-CAP PDB RA17 1 2 0_0201_5%

    ci
    GNDA LDO2-CAP PLUG_IN# (22)
    close to CODEC:ALC3292 CA18 1 2 10U_0402_6.3V6M LDO3_CAP 19 48 PLUG_IN#_R RA16 1 @ 2 100K_0201_5% +DVDD
    LDO3-CAP HP/LINE2_JD 47 MUTE_LED_IN
    PC_BEEP I2S_IN/I2S_OUT_JD MUTE_LED_IN (29)
    34
    PCBEEP 38 VREF CA19 1 2 2.2U_0402_6.3V6M
    C (8) HDA_SYNC_R
    HDA_SYNC_R 15
    AUDIOLINK:SYNC
    VREF GNDA Codec Mixers/IO power C
    1 2 +5VS_AVDD LA2 +5VS
    CA20 0.1U_0201_6.3V6K 0_0603_5%

    l
    1 2
    GNDA
    CA23 1 2 2.2U_0402_6.3V6M ACPVEE 25
    CPVEE

    0.1U_0201_10V6K
    CA11

    10U_0402_10V6M
    CA12
    CBN 24 37
    CBN AVSS1

    1
    CA26 1 2 2.2U_0402_6.3V6M CBP 23 22

    ia
    CBP AVSS2 GNDA 1 2
    CODEC_DMIC_CLK 5 @
    (22) CODEC_DMIC_CLK CODEC_DMIC_DATA GPIO_1/DMIC_CLK EC_AMP_EAPD
    4 13 To EC DA1
    (22) CODEC_DMIC_DATA GPIO_0/DMIC_DATA12 DC_DET/EAPD EC_AMP_EAPD (29) 2 1
    1 AZ5125-01H.R7G_SOD523-2

    t
    I2S_EN/SPDIF_OUT/GPIO_2/DMIC_DATA34/DMIC_CLK_IN 49 SC400005Q00
    Thermal_Pad 100K_0201_5% 2 1 RA54 +3VS
    2

    2
    ALC3292-CG_MQFN48_6X6
    Place near Pin40

    n
    CA88
    0.1U_0201_10V6K GNDA
    1 +5VALW

    e
    @ LA13
    1 2
    FBMA-L11-201209601LMA20T_2P
    PC Beep Codec Stage power

    id
    +5VS_PVDD +5VS
    LA4
    1 2
    FBMA-L11-201209601LMA20T_2P

    0.1U_0201_6.3V6K
    CA21

    10U_0402_6.3V6M
    CA24

    0.1U_0201_6.3V6K
    CA22

    10U_0402_6.3V6M
    CA25
    EC Beep (29) EC_BEEP#
    1 2 PC_BEEP_R
    CA27 1 2 1 2

    0.1U_0201_6.3V6K
    CA91

    10U_0402_6.3V6M
    CA92
    0.1U_0201_6.3V6K RA19
    47K_0201_5% 1 2

    n
    1 2 1 2 1 2 PC_BEEP
    SB Beep (8) SPKR
    CA28 CA29 2 1 2 1
    1

    0.1U_0201_6.3V6K 0.1U_0201_6.3V6K
    2 1

    co
    B
    RA20
    10K_0201_5% Vinafix.com Place near Pin41 Place near Pin46
    B
    2

    Close to Codec pin34


    600ohms @100MHz 2A
    P/N: SM01000EE00

    L
    LA8 EMI@
    HP_OUTR 2 1 HP_OUT_R
    HP_OUT_R (22)
    1 2 BLM15AX601SN1D_2P
    CA30 @EMI@ SM01000KL00
    0.1U_0201_6.3V6K LA9 EMI@
    HP_OUTL HP_OUT_L

    A
    2 1
    +3VDS_AUDIO +3VDS_AUDIO HP_OUT_L (22)
    1 @ 2 BLM15AX601SN1D_2P
    RA22 0_0603_5% SM01000KL00
    LA10 EMI@
    1

    1 @ 2 INT_MIC_R 2 1 INT_MIC

    P
    INT_MIC (22)
    1

    RA24 0_0603_5% BLM15AX601SN1D_2P


    @ RA25 SM01000KL00
    1 @ 2 10K_0201_5% 100K_0201_5%
    1 1 1
    RA67 0_0603_5% RA26
    2 2

    CA97 @EMI@ CA96 @EMI@ CA95 @EMI@


    2
    B

    1 2 100P_0201_25V8J 10P_0201_25V8 10P_0201_25V8


    CA31 EMI@ @ 2 2 2

    M
    E

    0.1U_0201_6.3V6K HDA_RST#_R 3 1 PDB PDB


    <CPU> (8) HDA_RST#_R
    C

    SB000008E10 QA2 GNDA GNDA GNDA


    1 2 MMBT3904WH_SOT323-3
    DA3 2
    CA32 EMI@ @

    O
    0.1U_0201_6.3V6K 1 2 CA94
    <EC> (29) EC_MUTE#
    0.1U_0201_10V6K
    LRB521S-40T1G_SOD523-2-2 1
    1 2 SCS00008100
    A CA36 @EMI@ A

    C
    0.1U_0201_6.3V6K
    PIR15 SI: remove DA10,DA11
    1 2
    CA37 EMI@
    0.1U_0201_6.3V6K

    1 2
    CA38 @EMI@
    0.1U_0201_6.3V6K
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2017/03/20 Deciphered Date 2020/03/20 Title
    GNDA
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AUDIO ALC3292-CG
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 27 of 55
    5 4 3 2 1
    5 4 3 2 1

    FF:10.6 IC:10.2
    +3VALW +1.8VALW_AUDIO

    P
    +5VALW UA4
    UA3 1 5
    Imax=3A 2 VIN VOUT
    1 GND 1
    C3 B1 LA6 1 2 1UH +-20% DFE252010F-1R0M=P2 CA52 2 1 0.1U_0201_6.3V6K CA50 3 4 CA51
    D3 INP SW B2 SHI0000S500 CA49 2 1 1U_0201_6.3V6M 2.2U_0402_6.3V6M EN NC 1U_0201_6.3V6M
    D INM SW CA53 2 1 10U_0402_10VAK G9090-180TO1U_TSOT23-5 D

    H
    CA54 2 1 22U_0402_6.3V6M 2 2

    I2S_MCLK_R RA33 1 2 0_0201_5% I2S_MCLK_R_L D6 C1


    (27) I2S_MCLK_R I2S_BCLK_R I2S_BCLK_R_L MCLK_GPI2 VBOOST +VBOOST_L_8.5V
    RA34 1 2 0_0201_5% B6 C2
    (27) I2S_BCLK_R I2S_LRCK_R I2S_LRCK_R_L BCLK1_GPIO1 VBOOST
    RA35 1 2 0_0201_5% A5
    (27) I2S_LRCK_R I2S_OUT_R I2S_OUT_R_L WBLK1_GPIO2 +VBAT_L

    r
    RA36 1 2 0_0201_5% B5
    (27) I2S_OUT_R I2S_IN_R I2S_IN_R_L DIN1_GPI1
    RA37 1 2 0_0201_5% A6
    (27) I2S_IN_R DOUT1_GPIO3 A3 RA55 1 2 0_0402_5%
    VBAT
    +3VALW
    Imax=50mA

    fo
    F6 C6 +1.8VALW_AUDIO
    BCLK2_GPIO5 DVDD +1.8VALW_AUDIO
    E5
    C5 WCLK2_GPIO6
    E6 DIN2_GPI8 F4
    Imax=30mA
    SI: pop RA38,RA39 DOUT2_GPIO7 AVDD +1.8VALW_AUDIO

    CA55

    CA56

    CA57

    CA58

    CA59
    RA38 1 2 4.7K_0201_5%
    Imax=5mA 1 1 1 1 1
    (27,29) EC_SMB_CK3
    RA39 1 2 4.7K_0201_5% G6 RA56 1 2 0_0201_5%
    +3VALW RA61 1 2 0_0402_5%
    (27,29) EC_SMB_DA3 EC_SMB_CK3 IOVDD (27) SPK_OUT_L+
    F3 RA62 1 2 0_0402_5%

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    10U_0402_10VAK
    0.1U_0201_6.3V6K

    0.1U_0201_6.3V6K
    t
    EC_SMB_DA3 SCL_SS# (27) SPK_OUT_L- 2 2 2 2 2
    E4
    SDA_MOSI +IOVDD_L
    D2 VREG_L CA60 1 2 0.01U_0201_16V7

    i
    VREG +VBOOST_L_8.5V JSPK1
    ICC_RX_A B4 SM01000M700 SPK_OUT_L+_CONN 1
    ICC_CLK A4 ICC_GPI3 SPK_OUT_L-_CONN 2 1
    ICC_TX_A B3 ICC_GPIO9 F1 SPK_P_L+ RA40 1 2 SPK_L+_CONN 3 2 5

    u
    ICC_GPIO10 SPK_P BLM15PX471SN1D_2P EMI@ SPK_L-_CONN 4 3 G1 6
    D1 SPK_M_L- RA41 1 2 4 G2
    address SPK_M BLM15PX471SN1D_2P EMI@ close to UA4 pinC6 close to UA4 pinF4

    1 1000P_0201_16V7K

    1 1000P_0201_16V7K
    G3 ACES_50208-0040N-001
    ADR1_MISO

    c
    F5 CONN@
    ADR0_SCLK E2 +3VALW +VBOOST_L_8.5V
    VSENSE_P

    r
    +3VALW G4 F2
    SPI_SELECT VSENSE_M

    CA63

    CA64

    CA65

    CA67
    ci
    1 1 1 1
    PIR13 SI: remove CA98,CA99
    1

    @EMI@

    @EMI@
    close to Amp:TAS2557
    D5

    22U_0805_16V6M
    1U_0201_6.3V6M

    0.1U_0201_16V6K
    0.1U_0201_6.3V6K
    PAD T356 @ IRQ_GPIO4# 2 2 2 2
    RA42 E1

    2
    10K_0201_5% PGND A2
    PGND_B A1

    CA61

    CA62
    To EC
    2

    C EC_AMP_RST# PGND_B C
    RA43 1 2 0_0201_5% G5
    (29) EC_AMP_RST# RESET#
    @ 1

    l
    CA68 D4
    G1 IOGND E3
    0.1U_0201_6.3V6K
    2 G2 NC1 AGND C4
    NC2 DGND
    close to SPK CONN.
    close to UA4 pinG6 close to UA4 pinC1,C2

    ia
    SND032557_WCSP42 CA65 main:SE000016400
    2nd:SE00000XH80

    C3
    D3
    UA5

    INP SW
    B1
    B2
    LA7 1 2 1UH +-20% DFE252010F-1R0M=P2
    SHI0000S500

    n t
    +5VALW
    Imax=1.5A
    CA71 2
    CA72 2
    1 0.1U_0201_6.3V6K
    1 1U_0201_6.3V6M
    PIR16 SI: remove DA6,DA9

    e
    INM SW CA70 2 1 10U_0402_10VAK
    CA73 2 1 22U_0402_6.3V6M

    I2S_MCLK_R RA44 1 2 0_0201_5% I2S_MCLK_R_R D6 C1


    MCLK_GPI2 VBOOST +VBOOST_R_8.5V

    id
    I2S_BCLK_R RA45 1 2 0_0201_5% I2S_BCLK_R_R B6 C2
    I2S_LRCK_R RA46 1 2 0_0201_5% I2S_LRCK_R_R A5 BCLK1_GPIO1 VBOOST
    I2S_OUT_R RA47 1 2 0_0201_5% I2S_OUT_R_R B5 WBLK1_GPIO2 +VBAT_R
    I2S_IN_R RA48 1 2 0_0201_5% I2S_IN_R_R A6 DIN1_GPI1
    DOUT1_GPIO3 A3 RA57 1 2 0_0402_5%
    VBAT

    f
    PIR17 SI: pop RA48 Imax=50mA
    F6 C6 +1.8VALW_AUDIO
    E5 BCLK2_GPIO5 DVDD +1.8VALW_AUDIO
    C5 WCLK2_GPIO6
    E6 DIN2_GPI8 F4
    Imax=30mA

    n
    DOUT2_GPIO7 AVDD +1.8VALW_AUDIO
    Imax=5mA

    CA74

    CA75

    CA76

    CA77

    CA78
    1 1 1 1 1
    G6 RA58 1 2 0_0402_5% +3VALW
    EC_SMB_CK3 F3 IOVDD RA64 1 2 0_0402_5%
    (27) SPK_OUT_R+

    o
    EC_SMB_DA3 E4 SCL_SS# RA63 1 2 0_0402_5%

    10U_0402_10VAK
    1U_0201_6.3V6M

    1U_0201_6.3V6M
    0.1U_0201_6.3V6K

    0.1U_0201_6.3V6K
    SDA_MOSI +IOVDD_R (27) SPK_OUT_R- 2 2 2 2 2
    B B
    D2 VREG_R CA79 1 2 0.01U_0402_16V7K
    VREG +VBOOST_R_8.5V JSPK2

    c
    ICC_TX_A B4 SM01000M700 SPK_OUT_R+_CONN1
    ICC_CLK A4 ICC_GPI3 SPK_OUT_R-_CONN 2 1
    ICC_RX_A B3 ICC_GPIO9 F1 SPK_P_R+ RA49 1 2 SPK_R+_CONN 3 2 5
    ICC_GPIO10 SPK_P BLM15PX471SN1D_2P EMI@ SPK_R-_CONN 4 3 G1 6
    D1 SPK_M_R- RA50 1 2 4 G2
    address SPK_M BLM15PX471SN1D_2P EMI@

    1 1000P_0201_16V7K

    1 1000P_0201_16V7K
    G3 ACES_50208-0040N-001

    22P_0201_25V8

    22P_0201_25V8
    ADR1_MISO
    close to UA5 pinC6 close to UA5 pinF4
    1 2 F5 CONN@
    +3VALW

    L
    RA51 10K_0201_5% ADR0_SCLK E2
    VSENSE_P +3VALW +VBOOST_R_8.5V

    +3VALW G4 F2
    SPI_SELECT VSENSE_M

    CA82

    CA83

    CA84

    CA86
    close to Amp:TAS2557 1 1 1 1
    1

    1
    @EMI@

    @EMI@
    A
    D5
    PAD T357 @ IRQ_GPIO4#
    RA52 E1

    22U_0805_16V6M
    1U_0201_6.3V6M

    0.1U_0201_16V6K
    0.1U_0201_6.3V6K
    2

    2
    10K_0201_5% PGND A2 2 2 2 2
    PGND_B A1

    CA80

    CA81

    CA100

    CA101
    RF@

    RF@
    2

    EC_AMP_RST# RA53 1 2 0_0201_5% G5 PGND_B

    P
    @ RESET#
    1
    CA87 D4
    G1 IOGND E3
    0.1U_0201_6.3V6K
    2 G2 NC1 AGND C4
    NC2 DGND
    close to SPK CONN.
    close to UA5 pinG6 close to UA5 pinC1,C2
    SND032557_WCSP42

    M
    CA84 main:SE000016400
    SPK_R-_CONN
    2nd:SE00000XH80

    SPK_R+_CONN SPK_OUT_R-

    SPK_OUT_R+

    O 3

    2
    @ESD@
    DA5

    2
    L03ESDL5V0CG3-2 C/A SOT523 @ESD@
    ADR1_MISO ADR0_SLCK address SCA00002A00 DA8
    A L03ESDL5V0CG3-2 C/A SOT523 A
    SCA00002A00

    C 1
    0 0 0x98(8bit) Speaker Left
    0x4C(7bit)

    1
    0 1 0x9A(8bit) Speaker Right
    0x4D(7bit)

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2017/03/20 Deciphered Date 2020/03/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Audio Front Speaker Amp:TAS2555
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 28 of 55
    5 4 3 2 1
    5 4 3 2 1

    +3VL_EC (12,13,23,24,25,28,30,33,34,38,39,43,44,45,47,48,49,50) +3VALW +3VALW


    +3VL +3VL_EC (30) +3VALW_TP +3VALW_TP
    (13,22,31,33,35,36,41,42,43) +3VL +3VL
    LK1 +3VL_EC
    (40) +3VL_EC

    2
    FBMA-L11-160808-800LMT_0603 +3VS
    +3VL_EC (5,7,9,10,11,24,27,31,36,37,39,47,48) +3VS
    RK1 1 @ 2 1 2 +EC_VCCA RK2
    1 1 1 100K_0201_1% (27,30,39) +5VS +5VS
    0_0603_5%

    0.1U_0201_6.3V6K
    CK2

    0.1U_0201_6.3V6K
    CK3

    0.1U_0201_6.3V6K
    CK1
    Board ID control (31) +3V_SMBUS +3V_SMBUS

    1
    1
    +3V_LID

    ECAGND
    RK6 @2 1 330K_0201_5% EC_RST# 2 2 RK4 2 BOARD_ID
    +3VL_EC
    0_0402_5% Board ID control for 13"

    P
    CK4 @ 1 2 .1U_0201_6.3V7K

    1
    1

    2
    2014-09-25: Unpop RC for EC_RST# RK13 13"
    +3VL_EC DB SI PV MV

    0.1U_0201_6.3V6K
    CK9
    For KB9022, the ECRST# is internally pull-up to VCC via
    40Kohm resistor, so you can remove external pull-up 43K_0201_1%
    2 1 PLT_RST# +EC_VCCLPC
    D resistor and capacitor. 2 D

    H
    CK8 .1U_0201_6.3V7K KBL-Y 15K ohm 27K ohm 43K ohm 75 ohm

    2
    @ESD@
    PIR31 SI: change from 15K to 27K
    PV: Add 0.1u PV: change from 27K to 43K

    M12
    K12

    B11
    K7
    J4

    J7
    r
    UK1
    +3VALW_TP

    EC_VDD/VCC
    EC_VDD/VCC
    EC_VDD/VCC

    EC_VDD/VCC

    EC_VDD/AVCC
    EC_VCC0
    PIR9 SI: swaps pin for KB backlight PIR9 SI: swaps pin for KB backlight TP_CLK RK7 1 2 4.7K_0201_5%

    fo
    +3VL_EC MUTE_LED_OUT M2 M9 KBL_ON# TP_DATA RK8 1 2 4.7K_0201_5%
    (30) MUTE_LED_OUT EC_KBRST# L2 GATEA20/GPIO00 PWM0/GPIO0F M8 EC_BEEP# KBL_ON# (30)
    (7) EC_KBRST# LPC_SERIRQ KBRST#/GPIO01 PWM1/GPIO10 EC_BEEP# (27)
    M3 M10
    +3V_SMBUS EC_SMB_CK2 (7) LPC_SERIRQ LPC_FRAME# SERIRQ FANPWM0/GPIO12 WWAN_SAR (26)
    RK46 1 2 2.2K_0201_5% K4 N10
    RK43 1 2 2.2K_0201_5% EC_SMB_DA2 (7) LPC_FRAME# LPC_AD3_R N3 LPC_FRAME# FANPWM1/GPIO13 PV: remove LID_SW2# ACIN CK5 2 1 100P_0201_50V8J
    (7) LPC_AD3_R LPC_AD2_R LPC_AD3
    M4

    t
    EC_SMB_CK1 (7) LPC_AD2_R LPC_AD1_R LPC_AD2 PWM Output
    RK44 1 2 2.2K_0201_5% K5 B13 B/I#
    EC_SMB_DA1 (7) LPC_AD1_R LPC_AD0_R LPC_AD1 BATT_TEMP/AD0/GPIO38 HRESET_988 B/I# (41,42)
    RK45 1 2 2.2K_0201_5% N4 LPC & MISC A13

    i
    (7) LPC_AD0_R LPC_AD0 AD1/GPIO39 ADP_I HRESET_988 (35) PV: swap pin for right side LED
    B12
    CLK_LPC_EC_R ADP_I/AD2/GPIO3A BOARD_ID ADP_I (40,42)
    N5 AD Input A12
    (7) CLK_LPC_EC_R PLT_RST# CLK_PCI_EC AD3/GPIO3B PM_SLP_S0#
    (9,22,23,24,31,33) PLT_RST# M5 D8 RK63 1 @ 2 0_0201_5% H_PROCHOT# (5,49)
    EC_RST# PCIRST#/GPIO05 AD4/GPIO42 MUTE_LED_IN PM_SLP_S0# (9,11,12,47,49) (42) PROCHOT#
    K13 D7

    u
    EC_SCI# EC_RST# IMON/AD5/GPIO43 MUTE_LED_IN (27)
    N6
    +3VS (5) EC_SCI# LPC_CLKRUN# EC_SCI#/GPIO0E H_PROCHOT#_EC
    M6 RK25 1 @ 2 0_0201_5%
    (7) LPC_CLKRUN# CLKRUN#/GPIO1D

    c
    B10 TS_STOP#_EC
    SMB_CK2 BA0/GPIO3C TS_RST#_EC TS_STOP#_EC (22) +5VS
    RK47 1 2 2.2K_0201_5% DA Output A9
    SMB_DA2 (30) KSI[0..7] DA1/GPIO3D VR_PWRGD TS_RST#_EC (22)
    RK48 1 2 2.2K_0201_5% KSI0 E9 A10

    r
    KSI0/GPIO30 DA2/GPIO3E EC_MUTE# VR_PWRGD (49)
    KSI1 E12 B9
    KSI1/GPIO31 DA3/GPIO3F EC_MUTE# (27) MUTE_LED_OUT RK65
    KSI2 E13 1 2 100K_0201_1%

    ci
    KSI3 D12 KSI2/GPIO32 D6 EC_SMB_CK3
    <To PD,Thermal (SOC)> KSI3/GPIO33 PSCLK1/GPIO4A EC_SMB_CK3 (27,28)
    +3VS KSI4 D13 E7 EC_SMB_DA3 <To Codec / SPK AMP>
    SMB_CK2 (31) KSI4/GPIO34 PSDAT1/GPIO4B VR_ON EC_SMB_DA3 (27,28) MUTE_LED_IN
    KSI5 C12 E5 RK64 1 @ 2 10K_0201_5%
    KSI5/GPIO35 PSCLK2/GPIO4C VR_ON (49)
    1

    KSI6 C13 D5 AC_LED2#


    S1 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D TP_CLK AC_LED2# (31) PV: add right side LED
    2 KSI7 E10 A5 PIR11 SI: un-pop RK64
    C 6 EC_SMB_CK2 (30) KSO[0..15] KSI7/GPIO37 PSCLK3/GPIO4E TP_DATA TP_CLK (30) C
    G1
    D1 KSO0 J13 B5
    KSO0/GPIO20 PSDAT3/GPIO4F TP_DATA (30)
    4 KSO1 J12
    SMB_DA2 (31) KSO1/GPIO21

    l
    S2
    5 KSO2 H12
    G2
    D2 KSO3 H13 KSO2/GPIO22 B1 SOC_ENBKL
    KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 WLAN_PWR_EN SOC_ENBKL (5,22)
    DMN63D8LV-7_SOT563-6 KSO4 J10 A1
    WLAN_PWR_EN (23)
    3

    EC_SMB_DA2 KSO5 J9 KSO4/GPIO24 WOL_EN/GPXIOA01 C1 ME_EN


    KSO5/GPIO25 Int. K/B

    ia
    QK3 ME_EN/GPXIOA02 ME_EN (8)

    1
    KSO6 H9 C2 VCIN0_PH
    KSO7 H10 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH (40)
    EC_RTC_RST 2 S1

    KSO7/GPIO27 SPI Device Interface


    PV: change PU +3V_PRIM KSO8 G13 G1
    D1 6
    KSO8/GPIO28 EC_SPI_SO SOC_RTCRST# (9)
    KSO9 G12 K2 4

    t
    +3V_PRIM KSO9/GPIO29 SPIDI/GPIO5B EC_SPI_SI EC_SPI_SO (7) EC_RTC_RST S2
    KSO10 F13 J2 5 DMN63D8LV-7_SOT563-6
    SMB_BS_CLK (26,49) KSO10/GPIO2A SPIDO/GPIO5C EC_SPI_CLK EC_SPI_SI (7)
    KSO11 F12 SPI Flash ROM L1 G2
    D2 QK4
    KSO11/GPIO2B SPICLK/GPIO58
    1

    1
    EC_SPI_CS#0

    10K_0201_5%
    RK49
    KSO12 G10 N2
    EC_SPI_CS#0 (7)

    3
    KSO12/GPIO2C SPICS#/GPIO5A

    10K_0201_5%
    RK50
    S1
    2 KSO13 G9

    n
    G1
    D1 6 EC_SMB_CK2 KSO14 F10 KSO13/GPIO2D
    4 KSO15 F9 KSO14/GPIO2E B6 EC_AMP_EAPD
    S2 SMB_BS_DATA (26,49) KSO15/GPIO2F ENBKL/AD6/GPIO40 SYS_PWROK EC_AMP_EAPD (27) SOC_SRTCRST# (9)
    5 (35) TBTB_I2C_IRQ2Z
    D9 B7 SYS_PWROK (9)

    2
    KSO16/GPIO48 PECI_KB930/AD7/GPIO41

    e
    G2
    D2 D10 B4 EC_AMP_RST#
    (36) TBTC_I2C_IRQ2Z KSO17/GPIO49 FSTCHG/GPIO50 BAT_CHG_LED EC_AMP_RST# (28)
    DMN63D8LV-7_SOT563-6 A4
    BAT_CHG_LED (31)
    3

    EC_SMB_DA2 BATT_CHG_LED#/GPIO52 B3 CAP_LOCK#


    QK5 CAPS_LED#/GPIO53 CAP_LOCK# (30)
    EC_SMB_CK1 A8 A3 PWR_LED#
    (41,42) EC_SMB_CK1 EC_SMB_CK1/GPIO44 GPIO PWR_LED#/GPIO54 PWR_LED# (31)

    id
    <To BAT/Charger> EC_SMB_DA1 A7 A2 ACIN
    (41,42) EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 ACIN (9)
    B8 SM Bus B2 SYSON
    (35,36) EC_SMB_CK2 EC_SMB_DA2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 EC_RTC_RST SYSON (12,21,44)
    <To Thermal sensor/PD> A6 H5
    (35,36) EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 M1 DPWROK_EC SI:Rename from GPIO57 to EC_RTC_RST
    PM_SLP_S4#/GPIO59 DPWROK_EC (9)
    PIR9 SI: swaps pin for KB backlight

    f
    PV: change net name from TS_INT#_EC to SUB_EN
    PM_SLP_S3# J5 D4 EC_RSMRST#
    (9,12,33,39) PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# (9) EC_SPI_CLK
    N9 D1 RK54 1 EMI@ 2
    (26) SUB_EN PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 LID_SW1# (22) EC_SPI_CLK_R (7)
    SUSACK# L13 D2 VCIN1_PH 15_0201_1%

    n
    (9) SUSACK# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 VCIN1_PH (40)
    SLP_SUS# K6 E2 H_PROCHOT#_EC
    (9) SLP_SUS# GPIO0A H_PROCHOT#_EC/GPXIOA06 2
    PCH_SUSWARN# N7 E4 MAINPWON CK7
    (9) PCH_SUSWARN# GPIO0B VCOUT0_PH/GPXIOA07 MAINPWON (43)
    SI:swap from pin M9 to pin M7 EC_VCCST_PG_R M7 E1 EC_BKOFF#
    (9) EC_VCCST_PG_R GPIO0C GPO BKOFF#/GPXIOA08 BAT_CHG_LED2 EC_BKOFF# (22)
    SI:Add TBT_RST_EC# N8 GPIO F4 10P_0201_25V8

    co
    (33) TBT_RST_EC# GPIO0D PBTN_OUT#/GPXIOA09 BAT_CHG_LED2 (31) PV: add right side LED 1
    K8 F2 PCH_PWR_EN @EMI@
    (26) BATT_SHIP# EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 RESET_987 PCH_PWR_EN (12,39,45,46,48)
    B M11 F1 B
    (22) IR_GPIO N11 FANFB0/GPIO14 SA_PGOOD/GPXIOA11 RESET_987 (36) PV: swap pin for right side LED
    VCIN1_ACOK 1 2 VCIN1_AC_IN_R (23) EC_PCIE_WAKE# K10 FANFB1/GPIO15
    @
    (42) VCIN1_ACOK (31) E51TXD_P80DATA EC_TX/GPIO16 VCIN1_AC_IN_R
    RK29 0_0201_5% K9 F5
    (31) E51RXD_P80CLK PCH_PWROK EC_RX/GPIO17 AC_IN/GPXIOD01 EC_ON
    N12 G1
    (9) PCH_PWROK AC_LED# PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON (31,43)
    M13 G5 ON/OFF#
    (31) AC_LED# SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 LID_SW# ON/OFF# (31,36)
    L12 GPI H1 LID_SW# (31,36)
    (30) TP_EN NUM_LED#/GPIO1A LID_SW#/GPXIOD04 G4 SUSP#
    SUSP#/GPXIOD05 H4 NMI_DBG# SUSP# (12,39,44,47)
    HW Module OLB Define this function

    L
    GPXIOD06 H2 EC_PECI RK16 1 2 43_0402_1%
    PBTN_OUT# PECI_KB9012/GPXIOD07 H_PECI (5)
    (9) PBTN_OUT# J1
    (9,21) PM_SLP_S4#
    PM_SLP_S4# K1 XCLKI/GPIO5D N1 +V18R RK17 2 @ 1 +3VL_EC
    XCLKO/GPIO5E V18R 0_0402_5%
    1
    AGND
    GND0

    2014-09-30:
    GND

    PM_SLP_S4# Change to from pin:84 to pin:123. 2014-09-25: Add RK17

    A
    CK6
    PBTN_OUT# Change from pin:106 to 122. For 1.8V power plane: VCC_IO2 and VCC_LPC pull up +1.8VALW or
    due to it needs to support BayTrial M 1.8V 4.7U_0402_6.3V6M
    KB9022GD_VFBGA124 2 +1.8VL(P). (ex: for Bay Trial M platform)
    platform.
    For 3.3V power plane: VCC_IO2 and VCC_LPC pull up +3.3VALW or
    N13
    G2

    A11

    This pin can support V1.8 power plan. SA000074G10 BATT_SHIP# RK66 1 2 1M_0201_5%
    20mil +3.3VL(P).

    P
    LK2
    +3VALW ECAGND 2 1
    FBMA-L11-160808-800LMT_0603 SUSP# RK30 1 @ 2 100K_0201_5%
    1

    RK69
    10K_0201_5% @

    M
    ECAGND (40)
    RC581
    2

    PWR_LED# 2 @ 1 +3VL_EC
    PWR_LED#_PD (35,36)
    200_0201_1%
    1

    PIR12 SI: remove RK18 EC_ON RK58 1 2 100K_0201_5%


    1

    O
    PCH_PWR_EN RK59 1 2 100K_0201_5%
    RK70 RK22 PV: delete RK60
    @ 10K_0201_5% 10K_0201_5% E51TXD_P80DATA RK61 1 2 100K_0201_5%
    PIR2 SI: Add type-C additional features by PD
    2

    A A
    2

    C
    DK2
    @ NMI_DBG# 1 2
    NMI_DBG#_CPU (5)
    ON/OFF# DC7 2 1
    A K ON/OFF#_988 (35)
    BAT54LPS-7_X2-DFN1006-2-2 SCS0000AO00 LRB521S-40T1G_SOD523-2-2
    SCS00008100

    @
    DC8 2
    A K
    1
    ON/OFF#_987 (36)
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2017/03/20 Deciphered Date 2020/03/20 Title
    BAT54LPS-7_X2-DFN1006-2-2 SCS0000AO00
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    EC ENE-KB9022
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 29 of 55
    5 4 3 2 1
    5 4 3 2 1

    +3V_PRIM (12,13,23,24,25,28,29,33,34,38,39,43,44,45,47,48,49,50) +3VALW +3VALW


    +3VALW _TP (5,7,8,9,10,11,12,13,24,25,26,29,33) +3V_PRIM +3V_PRIM
    (27,29,39) +5VS +5VS
    (12,27,28,31,35,36,39,43,46) +5VALW +5VALW
    (5,7,9,10,11,24,27,29,31,36,37,39,47,48) +3VS +3VS

    2
    @ @

    2
    R28 R29
    R26 R27 2.2K_0201_5% 2.2K_0201_5%
    2.2K_0201_5% 2.2K_0201_5%
    Keyboard conn

    1
    +3V_PRIM +3V_PRIM
    PCH_SMBus(+3V_PRIM) PCH_I2C

    1
    SOC_SMBDATA (7) I2C_0_SCL (10)

    1
    D D

    H
    S1 S1 (29) KSI[0..7]
    2 2 KSI7
    G1
    D1 6 TP_SMBDAT G1
    D1 6 TP_SMBCLK KSI6
    4 4 KSI5
    S2 SOC_SMBCLK (7) S2 I2C_0_SDA (10)
    5 5 KSI4

    r
    G2 G2
    D2 D2 KSI3 CVILU_CF5532FD0R1-05-NH
    DMN63D8LV-7_SOT563-6 DMN63D8LV-7_SOT563-6 KSI2
    3

    3
    Q2 TP_SMBCLK Q3 @ TP_SMBDAT KSI1 KSI1 1

    fo
    KSI0 KSI7 2 1
    +3VALW _TP KSI6 3 2
    KSO9 4 3
    KSI4 5 4
    +3VALW KSI5 6 5
    1 2 6

    t
    +3VALW _TP

    0.1U_0201_6.3V6K
    KSO0 7
    7

    C49

    0.1U_0201_10V6K
    CC371 @RF@
    KSI2 8

    i
    (29) KSO[0..15] 8
    KSI3 9
    2 1 KSO15 KSO5 10 9
    R5803 1 2 0_0402_5% KSO14 KSO1 11 10

    u
    KSO13 KSI0 12 11
    KSO12 KSO2 13 12
    ESD request, change to SOT523 KSO11 KSO4 14 13

    c
    KSO10 KSO7 15 14
    +3VALW _TP CONN@ KSO9 KSO8 16 15

    r
    ESD@ D8 KSO8 KSO6 17 16
    ACES_51539-0080M-001
    Touch pad conn 2 TP_EN KSO7 KSO3 18 17

    ci
    10 1 KSO6 KSO12 19 18
    9 GND 3 TP_INT#_R KSO5 KSO13 20 19
    8 GND KSO4 KSO14 21 20
    TP_DATA 7 8 L03ESDL5V0CG3-2 C/A SOT523 KSO3 KSO11 22 21
    (29) TP_DATA TP_CLK 7 22
    C
    EC PS2 6 KSO2 KSO10 23 C
    (29) TP_CLK 6 23
    5 KSO1 KSO15 24

    l
    TP_SMBCLK 4 5 KSO0 25 24
    DC6
    TP_SMBDAT 4 25
    Check RC1. @ 3 ESD@ D9 PIR4 SI: From 1.3K to 1.8K 26
    2 1 SCS00008100 TP_INT#_R 2 3 2 TP_DATA 27 26

    ia
    (5) TP_INT# 2 +5VS 27
    LRB521S-40T1G_SOD523-2-2 TP_EN 1 1 R30 1 2 1.8K_0402_1% CAP_LOCK#_R 28
    (29) TP_EN 1 TP_CLK (29) CAP_LOCK# MUTE_LED_CTL R31 MUTE_LED_R 28
    3 1 2 3.3K_0201_5% 29
    30 29
    JTP1 30

    t
    L03ESDL5V0CG3-2 C/A SOT523 Delete pin30,31 connection 31
    TP_EN ACES_51539-0080M-001_8P-T 32 31
    +5VS 32
    1

    n
    100K_0201_5%

    PV: change symbol ESD@ D7


    R5798

    2 TP_SMBCLK
    1

    e
    3 TP_SMBDAT
    33
    2

    L03ESDL5V0CG3-2 C/A SOT523 34 G1


    G2

    id
    JKB1
    CONN@

    f
    TP_CLK TP_DATA TP_SMBCLK TP_SMBDAT

    1 1 1 1

    n
    RF@ RF@ RF@ RF@
    C5236 C5242 C5243 C5244
    10P_0201_25V8 10P_0201_25V8 10P_0201_25V8 10P_0201_25V8 100p_0201_25V 1 2 C158 @ESD@ CAP_LOCK#_R
    2 2 2 2

    co
    100p_0201_25V 1 2 C157 @ESD@ MUTE_LED_R
    B B

    ESD request, change 0.1u

    KB backlight Conn
    +5VS

    L (29) MUTE_LED_OUT
    1
    RA68
    2 MUTE_LED_CTL
    1

    A
    0_0201_5%
    R34
    100K_0201_5%

    P
    +5VS
    2

    KBL_ON_GND
    2

    Q1
    1

    AO3416L 1N SOT-23-3

    M
    R5806
    0_0603_5% KBL_ON
    High : Turn ON
    Low : Turn OFF
    +5VS_KB 1

    O
    2
    KBL_ON# (29)
    JKBL1
    1
    A 1 A

    C
    2
    3

    KBL_ON_GND 3 2
    4 3
    4
    5
    6 GND
    GND Security Classification Compal Secret Data Compal Electronics, Inc.
    JXT_FP272H-004G100M Issued Date 2017/03/20 Deciphered Date 2020/03/20 Title
    PV: for EC control KBL PWM
    CONN@
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    KB/TP/DB
    SP01002GE00 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 30 of 55
    5 4 3 2 1
    A B C D E

    (27,29,30,39) +5VS +5VS


    (5,7,9,10,11,24,27,29,36,37,39,47,48) +3VS +3VS
    +3VL

    Power Button Conn(TBD)


    (13,22,29,33,35,36,41,42,43) +3VL
    (13,29,41) +3V_LID +3V_LID

    Function Field:29.5
    1

    Debug Card Power +3V_LID

    H P 1

    +3VS +3V_LID

    +5VALW
    +3VL +3V_LID
    R5801
    1

    SA0000ARR00
    2
    200K_0201_5%

    APX8132HAI-TRG_SOT23-3

    fo r
    t
    2 3 LID_SW #

    GND
    D2 VDD VOUT LID_SW # (29,36)
    CONN@

    i
    JPW R 2 1 1 1
    1 2 C5229 UH2 C5228

    1
    3 1 2 4 LRB521S-40T1G_SOD523-2-2
    PW R_LED# (29)

    u
    5 3 4 6 SCS00008100 0.1U_0201_6.3V6K 10P_0201_25V8
    ON/OFF#_R 5 6 E51TXD_P80DATA (29) 2 2
    7 8
    7 8 E51RXD_P80CLK (29)
    9 10

    c
    9 10 PLT_RST# (9,22,23,24,29,33)
    1 2 11 12

    r
    RC522 @ 0_0603_5% 13 GND GND 14
    GND GND

    ci
    PANAS_AXT510124 PIR22 SI: Add CC405~CC410
    SP021307180

    +3VL +3V_LID
    2 2
    +3V_LID
    Charger LED
    l
    +3V_LID +3VL

    LID_SW#_OUT Side Light

    ia
    1 1 1 1 1 1
    1

    2 CC405 CC406 CC407 CC408 CC409 CC410 PIR3 SI: From 560 to 1.91K White: Vf=2.8~3.3V
    R5804 RF@ RF@ RF@ RF@ RF@ RF@ LED1
    +3V_SMBUS 100K_0402_5% 10 mil White Amber: Vf=1.8~2.0V

    t
    2 2 2 2 2 2

    68P_0201_50V8J

    0.1U_0201_6.3V6K

    68P_0201_50V8J

    0.1U_0201_6.3V6K

    68P_0201_50V8J

    0.1U_0201_6.3V6K
    1.91K_0402_1% 1 2 R38 2
    (29) AC_LED# left side
    2

    +8.4V ON/OFF# 1 3 ON/OFF#_R


    (29,36) ON/OFF#

    n
    1 +5VL
    (29) BAT_CHG_LED 825_0402_1% 2 1 R39 3
    +3VL
    QC5 10 mil

    e
    PV: change erom 220 ohm to 825 ohm
    PJE138K 1N SOT-523-3 Amber
    HT-210UD5-BP5_AMBER-W HITE

    id
    SC500007E00
    Unlock Storage mode by Lid open w/o AC.
    LED2
    White
    Storage mode circuit

    f
    1.91K_0402_1% 1 2 R5808 2
    (29) AC_LED2# right side

    n
    1 +5VL
    (29) BAT_CHG_LED2 825_0402_1% 2 1 R5807 3

    10 mil

    o
    PV: add right side LED Amber
    3 HT-210UD5-BP5_AMBER-W HITE 3

    c
    SC500007E00

    L +3VS
    Address : 1001_101xb
    UC14

    3300P_0201_16V7K
    1

    A CC133
    C 1
    QT1 2 1 10 +3VS
    B VCC SCL SMB_CK2 (29)
    MMBT3904W H_SOT323-3

    0.1U_0201_6.3V6K
    E THERM_DP1 2 9

    P
    SMB_DA2 (29)
    3

    2 DP1 SDA

    CC279
    SB000008E10 1
    THERM_DN1 3 8
    DN1 ALERT#
    THERM_DP2 4
    DP2 THERM#
    7
    2
    FF:27.1
    3300P_0201_16V7K
    1

    CC134

    THERM_DN2

    M
    C 1 5 6
    QT2 2 DN2 GND
    B
    D17
    MMBT3904W H_SOT323-3
    E 10mil
    3

    +3V_SMBUS SB000008E10 2 F75303M_MSOP10


    THERMAL SENSOR

    O
    (29,43) EC_ON 2 1

    LRB521S-40T1G_SOD523-2-2
    4
    SCS00008100 4

    C
    Thermal sensor SMBus address -->100-1_100xb : 0x48
    5.6P_0402_50V

    D4
    CC172

    1
    +3VL 2 1
    @RF@

    LRB521S-40T1G_SOD523-2-2
    SCS00008100 2 Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2017/03/20 Deciphered Date 2020/03/20 Title
    LID/LED
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 31 of 55
    A B C D E
    5 4 3 2 1

    Remove HP2DC Shielding Can Clip

    CONN@ CONN@ CONN@ CONN@ CONN@ CONN@ CONN@ CONN@ CONN@ CONN@
    CLIP1 CLIP2 CLIP3 CLIP4 CLIP5 CLIP6 CLIP7 CLIP8 CLIP9 CLIP10
    HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

    1
    D D

    CONN@ CONN@
    CLIP11 CLIP12
    HOLEA HOLEA
    CONN@ CONN@
    CLIP13 CLIP14
    HOLEA HOLEA
    CONN@ CONN@

    r
    CLIP15 CLIP16
    HOLEA HOLEA
    CONN@ CONN@
    CLIP17 CLIP18
    HOLEA HOLEA
    HCONN@ CONN@
    CLIP19 CLIP20
    HOLEA HOLEA

    fo

    1
    CONN@ CONN@
    CLIP21 CLIP22
    HOLEA HOLEA

    i t
    CONN@ CONN@
    CLIP23 CLIP24
    HOLEA HOLEA

    u
    CONN@ CONN@
    CLIP25 CLIP26
    HOLEA HOLEA
    CONN@ CONN@
    CLIP27 CLIP28
    HOLEA HOLEA
    CONN@ CONN@
    CLIP29 CLIP30
    HOLEA HOLEA

    ri c

    1
    CONN@ CONN@ CONN@ CONN@ CONN@ CONN@ CONN@ CONN@ CONN@ CONN@
    CLIP31 CLIP32 CLIP33 CLIP34 CLIP35 CLIP36 CLIP37 CLIP38 CLIP39 CLIP40

    c
    HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
    C C

    1
    t i a CONN@ CONN@
    CLIP41 CLIP42
    HOLEA HOLEA
    CONN@ CONN@
    CLIP43 CLIP44
    HOLEA HOLEA

    1
    id e
    Screw Hole
    n f
    B

    c o B

    L
    CPU
    Hinge FD1 FD2
    WLAN

    A
    H2 H1 H5 H4 H17 H6 H8 H9 H10 H11 @ @
    1

    1
    H_3P7 H_3P7 H_3P7 H_4P2 H_3P7 H_3P7 H_4P5 H_4P5 H_4P5 H_4P5
    FIDUCIAL_C40M80 FIDUCIAL_C40M80
    HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

    P
    FD3 FD4

    @ @ @ @ @ @ @ @ @ @
    1

    @ @
    1

    M
    FIDUCIAL_C40M80 FIDUCIAL_C40M80

    Type-C

    O
    SSD
    TBT
    H3 H13 H12 H7 H14 H15
    A
    H_3P7 H_3P2 H_3P2X4P0 H_3P2X4P0 H_3P2 H_3P2X4P0 A

    C
    HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

    @ @ @ @ @ @
    1

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2017/03/20 Deciphered Date 2020/03/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    TPM/G-SENSOR/13"Screw hole
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 32 of 55
    5 4 3 2 1
    5 4 3 2 1

    (34) +VCC3V3_S0_TBT +VCC3V3_S0_TBT


    TBT_XTAL_25_OUT TBT_XTAL_25_OUT_R (35) +3V_TBTB_PDLDO +3V_TBTB_PDLDO
    RT55 2 EMI@ 1
    33_0201_5%

    +3VALW_LC YT2 TBT_XTAL_25_IN TBT_XTAL_25_IN_R


    RT80 2 EMI@ 1
    JTAG 3
    Crystal
    4
    33_0201_5%
    OUT GND
    2 1
    GND IN

    2
    10K_0201_5%

    10K_0201_5%
    P
    10K_0201_5%

    10K_0201_5%
    IC:46.1 FF:46.2

    20P_0201_25V8

    20P_0201_25V8
    1 25MHZ_10PF_8Y25000010 1
    TBT_HDMI_DDC_DATA

    RT1

    RT2

    RT3

    RT4
    RT84 2 1 100K_0201_5%
    TBT_HDMI_DDC_CLK RT85 2 1 100K_0201_5% CT219 CT220

    1
    RTD3_USB_PWR_EN_R RT1103 2 1 10K_0201_5%
    D 2 2 D
    Change to SJ10000I800

    H
    TBT_TDI

    TBT_TMS
    +TBT_PU_RAIL
    TBT_TCK
    PCIE_CTX_C_TRX_P1 PCIE_CRX_C_TTX_P1

    r
    CT300 1 2 0.22U_0201_6.3V6M Y23 V23 CT9 1 2 0.22U_0201_6.3V6M
    TBT_TDO RTD3_CIO_PWR_EN_R (11) PCIE_CTX_TRX_P1 PCIE_CTX_C_TRX_N1 PCIE_RX0_P PCIE_TX0_P PCIE_CRX_C_TTX_N1 PCIE_CRX_TTX_P1 (11)
    RT1105 2 @ 1 10K_0201_5% CT301 1 2 0.22U_0201_6.3V6M Y22 V22 CT10 1 2 0.22U_0201_6.3V6M
    (11) PCIE_CTX_TRX_N1 PCIE_RX0_N PCIE_TX0_N PCIE_CRX_TTX_N1 (11)
    TBT_I2C_SDA RT21 2 1 2.2K_0201_1% CT302 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_TRX_P2 T23 P23 PCIE_CRX_C_TTX_P2 CT1 1 2 0.22U_0201_6.3V6M
    (11) PCIE_CTX_TRX_P2 PCIE_CRX_TTX_P2 (11)

    PCIe GEN3
    TBT_I2C_SCL RT22 2 1 2.2K_0201_1% CT303 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_TRX_N2 T22 PCIE_RX1_P PCIE_TX1_P P22 PCIE_CRX_C_TTX_N2 CT11 1 2 0.22U_0201_6.3V6M

    fo
    TBTA_I2C_INT (11) PCIE_CTX_TRX_N2 PCIE_RX1_N PCIE_TX1_N PCIE_CRX_TTX_N2 (11)
    RT23 2 1 10K_0201_5%
    TBT_I2C_INT RT24 2 @ 1 10K_0201_5% CT304 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_TRX_P3 M23 K23 PCIE_CRX_C_TTX_P3 CT12 1 2 0.22U_0201_6.3V6M
    (11) PCIE_CTX_TRX_P3 PCIE_CTX_C_TRX_N3 PCIE_RX2_P PCIE_TX2_P PCIE_CRX_C_TTX_N3 PCIE_CRX_TTX_P3 (11)
    CT305 1 2 0.22U_0201_6.3V6M M22 K22 CT13 1 2 0.22U_0201_6.3V6M
    +3VL +TBT_PU_RAIL +3VL (11) PCIE_CTX_TRX_N3 PCIE_RX2_N PCIE_TX2_N PCIE_CRX_TTX_N3 (11)
    CT306 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_TRX_P4 H23 F23 PCIE_CRX_C_TTX_P4 CT2 1 2 0.22U_0201_6.3V6M
    PM_SLP_S3# (11) PCIE_CTX_TRX_P4 PCIE_CTX_C_TRX_N4 PCIE_RX3_P PCIE_TX3_P PCIE_CRX_C_TTX_N4 PCIE_CRX_TTX_P4 (11)
    0_0402_5% 2 short@ 1 RT591 RT40 2 @ 1 10K_0201_5% CT307 1 2 0.22U_0201_6.3V6M H22 F22 CT14 1 2 0.22U_0201_6.3V6M
    TBT_WAKE# (11) PCIE_CTX_TRX_N4 PCIE_RX3_N PCIE_TX3_N PCIE_CRX_TTX_N4 (11)
    RT47 1 2 10K_0201_5% RT47 follow intel checklist
    +3VALW TBT_CIO_PLUG_EVENT# RT48 1 @ 2 10K_0201_5% V19 L4 TBT_RST#

    t
    (9) CLK_PCIE_P4 PCIE_REFCLK_100_IN_P PERST_N
    PIR4 PV: RT48 un-pop T19
    (9) CLK_PCIE_N4 CLKREQ_PCIE#4 PCIE_REFCLK_100_IN_N PCIe_RBIAS RT5
    0_0402_5% 2 @ 1 RT592 AC5 N16 1 2 3.01K_0201_1%
    (9) CLKREQ_PCIE#4 PCIE_CLKREQ_N PCIE_RBIAS

    i
    RF@ CT15 1 2 0.1U_0201_10V6K SOC_DP1_P0_C AB7 R2
    CLKREQ_PCIE#4 (5) SOC_DP1_P0 DPSNK0_ML0_P DPSRC_ML0_P TBT_DP_ML0_P_C (37)
    CT312 1 2 10P_0201_25V8 CT16 1 2 0.1U_0201_10V6K SOC_DP1_N0_C AC7 R1
    (5) SOC_DP1_N0 DPSNK0_ML0_N DPSRC_ML0_N TBT_DP_ML0_N_C (37)
    CT4 1 2 0.1U_0201_10V6K SOC_DP1_P1_C AB9 N2
    (5) SOC_DP1_P1 TBT_DP_ML1_P_C (37)

    u
    CT18 1 2 0.1U_0201_10V6K SOC_DP1_N1_C AC9 DPSNK0_ML1_P DPSRC_ML1_P N1

    SOURCE PORT 0
    (5) SOC_DP1_N1 DPSNK0_ML1_N DPSRC_ML1_N TBT_DP_ML1_N_C (37)

    SINK PORT 0
    CT6 1 2 0.1U_0201_10V6K SOC_DP1_P2_C AB11 L2 PV: remove AR side 0.1u Cap
    (5) SOC_DP1_P2 DPSNK0_ML2_P DPSRC_ML2_P TBT_DP_ML2_P_C (37)
    CT7 1 2 0.1U_0201_10V6K SOC_DP1_N2_C AC11 L1
    (5) SOC_DP1_N2 DPSNK0_ML2_N DPSRC_ML2_N TBT_DP_ML2_N_C (37) For TUSB546A

    ri c
    CT8 1 2 0.1U_0201_10V6K SOC_DP1_P3_C AB13 J2
    +3V_TBTB_PDLDO (5) SOC_DP1_P3 DPSNK0_ML3_P DPSRC_ML3_P TBT_DP_ML3_P_C (37)
    CT23 1 2 0.1U_0201_10V6K SOC_DP1_N3_C AC13 J1
    From TPS65988 (5) SOC_DP1_N3 DPSNK0_ML3_N DPSRC_ML3_N TBT_DP_ML3_N_C (37)
    SOC_DP1_AUXP CT25 1 2 0.1U_0201_10V6K SOC_DP1_AUXP_C Y11 W19 TBT_DP_AUX_P CT327 1 2 0.1U_0201_10V6K
    0.1U_0402_16V4Z

    (5) SOC_DP1_AUXP SOC_DP1_AUXN DPSNK0_AUX_P DPSRC_AUX_P TBT_DP_AUX_P_C (37)


    CT28 1 2 0.1U_0201_10V6K SOC_DP1_AUXN_C W11 Y19 TBT_DP_AUX_N CT321 1 2 0.1U_0201_10V6K
    (5) SOC_DP1_AUXN DPSNK0_AUX_N DPSRC_AUX_N TBT_DP_AUX_N_C (37)
    3.3K_0402_1%
    RT41

    3.3K_0402_1%
    RT42

    3.3K_0402_1%
    RT43

    1
    1

    AA2 G1 TBT_DPSRC_HPD
    (5) SOC_DP1_HPD DPSNK0_HPD DPSRC_HPD TBT_DPSRC_HPD (36,37)

    1
    3.3K_0402_1%
    RT44
    CT41

    TBT_SNK0_DDC_CLK Y5 N6 DPSRC_RBIAS RT7 1 2 14K_0201_1%

    c
    2 TBT_SNK0_DDC_DATA R4 DPSNK0_DDC_CLK DPSRC_RBIAS
    DPSNK0_DDC_DATA U1 TBT_I2C_SDA
    TBT_I2C_SDA (35)
    2

    C GPIO_0 C
    UT2 CT31 1 2 0.1U_0201_10V6K SOC_DP2_P0_C AB15 U2 TBT_I2C_SCL To TPS65988
    (5) SOC_DP2_P0 TBT_I2C_SCL (35)
    2
    TBT_EE_CS_N 1 8 CT32 1 2 0.1U_0201_10V6K SOC_DP2_N0_C AC15 DPSNK1_ML0_P GPIO_1 V1 TBT_EE_WP_N

    LC GPIO
    TBT_EE_DO CS# VCC 7 TBT_HOLD_N (5) SOC_DP2_N0 DPSNK1_ML0_N GPIO_2 TBT_TMU_CLK_OUT
    2 V2

    l
    TBT_EE_WP_N 3 DO(IO1) HOLD#(IO3) 6 TBT_EE_CLK CT33 1 2 0.1U_0201_10V6K SOC_DP2_P1_C AB17 GPIO_3 W1 RT582 2 @ 1 0_0201_5%
    WP#(IO2) CLK 5 TBT_EE_DI (5) SOC_DP2_P1 DPSNK1_ML1_P GPIO_4 TBT_WAKE# (7)
    4 CT34 1 2 0.1U_0201_10V6K SOC_DP2_N1_C AC17 W2 TBT_CIO_PLUG_EVENT# TBTA_I2C_INT
    GND DI(IO0) 9 (5) SOC_DP2_N1 DPSNK1_ML1_N GPIO_5 TBT_HDMI_DDC_DATA TBT_CIO_PLUG_EVENT# (10)
    Y1
    thermal pad GPIO_6

    1
    CT35 1 2 0.1U_0201_10V6K SOC_DP2_P2_C AB19 Y2 TBT_HDMI_DDC_CLK

    SINK PORT 1
    it a
    (5) SOC_DP2_P2 DPSNK1_ML2_P GPIO_7
    W25Q80DVZPIG_WSON8 CT36 1 2 0.1U_0201_10V6K SOC_DP2_N2_C AC19 AA1 TBT_SRC_CFG1
    (5) SOC_DP2_N2 DPSNK1_ML2_N GPIO_8 TBTA_I2C_INT
    SA00008DZ00 J4 @T358 PAD RT823
    CT37 1 2 0.1U_0201_10V6K SOC_DP2_P3_C AB21 POC_GPIO_0 E2 TBT_I2C_INT 0_0201_5%

    POC GPIO
    (5) SOC_DP2_P3 DPSNK1_ML3_P POC_GPIO_1 TBT_I2C_INT (35)
    CT38 1 2 0.1U_0201_10V6K SOC_DP2_N3_C AC21 D4 RTD3_USB_PWR_EN_R RT1102 1 2 0_0201_5%
    (5) SOC_DP2_N3 RTD3_USB_PWR_EN (8)

    2
    DPSNK1_ML3_N POC_GPIO_2 H4 TBT_FORCE_PWR TBT_I2C_INT
    SOC_DP2_AUXP CT39 POC_GPIO_3 TBT_FORCE_PWR (10)
    1 2 0.1U_0201_10V6K SOC_DP2_AUXP_C Y12 F2 RT584 2 @ 1 0_0201_5%
    (5) SOC_DP2_AUXP SOC_DP2_AUXN CT40 DPSNK1_AUX_P POC_GPIO_4 PM_BATLOW# (10)
    1 2 0.1U_0201_10V6K SOC_DP2_AUXN_C W12 D2 RT583 2 @ 1 0_0201_5%
    (5) SOC_DP2_AUXN DPSNK1_AUX_N POC_GPIO_5 RTD3_CIO_PWR_EN_R PM_SLP_S3# (9,12,29,39)
    F1 RT1104 1 2 0_0201_5%
    +TBT_PU_RAIL POC_GPIO_6 RTD3_CIO_PWR_EN (10)
    Y6
    (5) SOC_DP2_HPD DPSNK1_HPD TBT_TEST_EN
    E1 RT9 1 2 100_0201_1%

    n
    TBT_SNK1_DDC_CLK Y8 TEST_EN

    Misc
    TBT_SNK1_DDC_DATA N4 DPSNK1_DDC_CLK AB5 TBT_TEST_PWG RT10 1 2 100_0201_1%
    TBT_SRC_CFG1 RT755 1 @ 2 10K_0201_5% DPSNK1_DDC_DATA TEST_PWR_GOOD
    RT11 1 2 14K_0201_1% DPSNK_RBIAS Y18 F4 TBT_RESET#
    From TPS65988

    e
    DPSNK_RBIAS RESET_N
    TBT_TDI Y4 D22 TBT_XTAL_25_IN_R
    TBT_TMS V4 TDI XTAL_25_IN D23 TBT_XTAL_25_OUT_R TBT_EE_CLK
    PULL UP - HDMI MODE TBT_TCK T4 TMS XTAL_25_OUT
    TCK

    if d
    PIR25 SI: Change size TBT_TDO W4 MISC AB3 TBT_EE_DI
    DP/HDMI CONFIGURATION TDO EE_DI AC4 TBT_EE_DO TBT_EE_DI (35) 1
    EE_DO TBT_EE_DO (35)
    RT12 1 2 4.75K_0201_0.5% TBT_RBIAS H6 AC3 TBT_EE_CS_N CT48 @EMI@
    TBT_RSENSE RBIAS EE_CS_N TBT_EE_CLK_R TBT_EE_CLK TBT_EE_CS_N (35)
    J6 AB4 2 RT13 1 0_0402_5% 10P_0402_50V8J
    RSENSE EE_CLK TBT_EE_CLK (35) 2
    EMI@ EMI request
    A15 B7
    TBT_SRC_CFG1 (38) TBT_A_TRX_R_DTX_P2 PA_RX1_P PB_RX1_P TBT_B_TRX_R_DTX_P2 (38)
    RT35 1 2 1M_0201_5% PV: remove 0ohm B15 A7 PV: remove 0ohm
    TBT_DPSRC_HPD (38) TBT_A_TRX_R_DTX_N2 PA_RX1_N PB_RX1_N TBT_B_TRX_R_DTX_N2 (38)
    RT36 1 2 1M_0201_5%
    CT42 1 2 0.22U_0201_25V5K TBT_A_TTX_DRX_P2 A17 A9 TBT_B_TTX_DRX_P2 CT43 1 2 0.22U_0201_25V5K
    (38) TBT_A_TTX_C_DRX_P2 TBT_A_TTX_DRX_N2 B17 PA_TX1_P PB_TX1_P TBT_B_TTX_DRX_N2 TBT_B_TTX_C_DRX_P2 (38)
    RT756 1 @ 2 100K_0201_5% CT44 1 2 0.22U_0201_25V5K B9 CT45 1 2 0.22U_0201_25V5K
    (38) TBT_A_TTX_C_DRX_N2 PA_TX1_N PB_TX1_N TBT_B_TTX_C_DRX_N2 (38)

    n
    CT46 1 2 0.22U_0201_25V5K TBT_A_TTX_DRX_P1 A19 A11 TBT_B_TTX_DRX_P1 CT47 1 2 0.22U_0201_25V5K
    (38) TBT_A_TTX_C_DRX_P1 PA_TX0_P PB_TX0_P TBT_B_TTX_C_DRX_P1 (38)
    JTYPEC2 (38) TBT_A_TTX_C_DRX_N1
    CT49 1 2 0.22U_0201_25V5K TBT_A_TTX_DRX_N1 B19 B11 TBT_B_TTX_DRX_N1 CT50 1 2 0.22U_0201_25V5K
    TBT_B_TTX_C_DRX_N1 (38)
    JTYPEC1
    PA_TX0_N PB_TX0_N

    TBT PORTS
    NOTE: B21 A13
    90ohm (38) TBT_A_TRX_R_DTX_P1 TBT_B_TRX_R_DTX_P1 (38) 90ohm

    o
    ASSEMBLE RT35 & RT36 if DPSRC A21 PA_RX0_P PB_RX0_P B13
    PV: remove 0ohm PV: remove 0ohm

    Port A

    PORT B
    NOT IN USE (38) TBT_A_TRX_R_DTX_N1 PA_RX0_N PB_RX0_N TBT_B_TRX_R_DTX_N1 (38)
    B B
    CT51 1 2 0.1U_0201_10V6K TBT_A_SUB1 Y15 Y16 TBT_B_SUB1 CT52 1 2 0.1U_0201_10V6K
    (38) TBT_A_SUB1_C TBT_A_SUB2 PA_DPSRC_AUX_P PB_DPSRC_AUX_P TBT_B_SUB2 TBT_B_SUB1_C (38)
    CT53 1 2 0.1U_0201_10V6K W15 W16 CT54 1 2 0.1U_0201_10V6K
    (38) TBT_A_SUB2_C PA_DPSRC_AUX_N PB_DPSRC_AUX_N TBT_B_SUB2_C (38)

    c
    E20 E19
    D20 PA_USB2_D_P PB_USB2_D_P D19
    Delete
    PA_USB2_D_N PB_USB2_D_N
    A5 B4
    (38) TBT_A_LSTX PA_LSTX PB_LSTX TBT_B_LSTX (38)

    POC
    POC
    A4 B5
    (38) TBT_A_LSRX PA_LSRX PB_LSRX TBT_B_LSRX (38)
    M4 G2
    (35) TBT_A_HPD PA_DPSRC_HPD PB_DPSRC_HPD TBT_B_HPD (35)

    L
    RT16 1 2 499_0201_1% PA_USB2_RBIAS H19 F19 PB_USB2_RBIAS RT17 1 2 499_0201_1%
    PA_USB2_RBIAS PB_USB2_RBIAS
    AC23 D6
    AB23 THERMDA MONDC_SVR
    THERMDA A23
    V18 ATEST_P B23
    PCIE_ATEST ATEST_N TBT_SNK0_DDC_CLK RT1101 1 2 100K_0201_5%

    A
    AC1 DEBUG E18
    TEST_EDM USB2_ATEST TBT_SNK0_DDC_DATA RT1100 1 2 100K_0201_5%
    +3V_TBTB_PDLDO +3V_PRIM L15 W13
    N15 FUSE_VQPS_64 MONDC_DPSNK_0 TBT_SNK1_DDC_CLK RT19 1 2 100K_0201_5%
    FUSE_VQPS_128 W18

    P
    TC7SH08FU_SSOP5 C23 MONDC_DPSNK_1 TBT_SNK1_DDC_DATA RT20 1 2 100K_0201_5%
    MONDC_CIO_0
    5

    UH4 C22 AB2


    TBT_A_SUB2_C 100K_0201_5% 2 1 RT764 1 MONDC_CIO_1 MONDC_DPSRC TBT_FORCE_PWR RT49 1 2 10K_0201_5%
    P

    TBT_RST# B PLT_RST# (9,22,23,24,29,31)


    4 UT1A
    TBT_B_SUB2_C 100K_0201_5% 2 1 RT765 O 2 SA00009ZV30 TBT_TMU_CLK_OUT RT81 1 2 100K_0201_5%
    PCH_TBT_RST# (7)
    G

    A
    1
    3

    TBT_A_SUB1_C 100K_0201_5% 2 1 RT766 RH474 SOC_DP1_HPD RT27 1 2 100K_0201_5%

    M
    TBT_B_SUB1_C 100K_0201_5% 2 1 RT767 100K_0201_5% SOC_DP2_HPD RT28 1 2 100K_0201_5%
    2

    +3VALW TBT_A_LSTX RT29 1 2 1M_0201_5%

    PV: for RTD3 function TBT_A_HPD RT30 1 2 100K_0201_5%


    2

    O
    RT1110 TBT_A_LSRX RT31 1 2 1M_0201_5%
    10K_0201_5%
    TBT_B_LSTX RT32 1 2 1M_0201_5%
    DT19
    1

    A TBT_B_HPD RT33 1 2 100K_0201_5% A


    TBT_RESET# 2 1

    C
    TBT_RESET_N (35) TBT_B_LSRX RT34 1 2 1M_0201_5%
    LRB521S-40T1G_SOD523-2-2 2 RT825 1 0_0201_5%
    TBT_RST_EC# (29)
    SCS00008100 @

    Security Classification
    2017/03/20
    Compal Secret Data
    2020/03/20 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Thunderbolt Alpinerid (1/2)
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 33 of 55
    5 4 3 2 1
    5 4 3 2 1

    3.3V @ 40mA
    +V0P9_DP 0_0402_5% 2 @ 1 RT97 +3VALW
    0.9V @ 700mA
    3.3V @ 200mA
    0_0402_5% 2 @ 1 RT1108 +VCC3V3_S0_TBT

    1U_0201_6.3VM

    1U_0201_6.3VM

    1U_0201_6.3VM

    1U_0201_6.3VM

    1U_0201_6.3VM

    1U_0201_6.3VM

    1U_0201_6.3VM
    0_0402_5% 2 1 RT100 +3VALW
    +3VALW_LC 10P_0402_50V8J 2 1 CT297 +VCC3V3_S0_TBT
    1 1 1 1 1 1 1
    CT55

    CT56

    CT57

    CT58

    CT59

    CT60

    CT65
    @RF@ 3.3V @ 700mA

    1U_0201_6.3VM

    1U_0201_6.3VM

    10U_0402_6.3V6M

    10U_0603_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    47U_0603_6.3V6M

    47U_0603_6.3V6M

    82P_0402_50V8J
    2 2 2 2 2 2 2 +V0P9_CIO +V0P9_USB +V0P9_PCIE +V0P9_DP

    0.1U_0201_10V6K

    1U_0201_6.3VM
    1 1 @ 1 1 1 1 1 1 1

    CT68

    CT69

    CT298
    1 1

    CT66

    CT67

    CT150

    CT70

    CT71

    CT72

    CT73

    CT149

    RF@
    D 2 2 2 2 2 2 2 2 2 D

    H
    2 2

    R13
    R6

    H9
    F8
    L8 A2

    VCC3P3_SX

    VCC3P3A
    VCC3P3_LC

    VCC3P3_S0
    r
    L11 VCC0P9_DP VCC3P3_SVR A3
    +V0P9_PCIE L12 VCC0P9_DP VCC3P3_SVR B3
    M8 VCC0P9_DP VCC3P3_SVR +V0P9_SVR
    T11 VCC0P9_DP
    0.9V @ 580mA 0.9V @ 2000mA

    fo
    T12 VCC0P9_DP L9
    VCC0P9_DP VCC0P9_SVR

    1U_0201_6.3VM

    1U_0201_6.3VM

    1U_0201_6.3VM

    1U_0201_6.3VM

    1U_0201_6.3VM

    1U_0201_6.3VM

    1U_0201_6.3VM
    L6 M9
    VCC0P9_ANA_DPSRC VCC0P9_SVR
    1U_0201_6.3VM

    1U_0201_6.3VM

    1U_0201_6.3VM

    1U_0201_6.3VM

    M6 E12 1 1 1 1 1 1 1
    VCC0P9_ANA_DPSRC VCC0P9_SVR_ANA
    68P_0201_50V8J

    CT82

    CT83

    CT84

    CT85

    CT86

    CT140

    CT139
    1 1 1 1 1 V11 E13
    VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA
    CT91

    CT92

    CT93

    CT151

    V12 F11
    VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA
    CT299

    V13 F12
    VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA 2 2 2 2 2 2 2 Share same GND plane
    RF@

    F13

    t
    2 2 2 2 2 M13 VCC0P9_SVR_ANA F15
    M15 VCC0P9_PCIE VCC0P9_SVR_ANA J9 with SVR_VSS of AR

    i
    M16 VCC0P9_PCIE VCC0P9_SVR_SENSE +TBT_SVR_IND
    L19 VCC0P9_PCIE S COIL 0.6UH TMPC404012HB-R60MG-Z02 6.6A
    SI:RF request VCC0P9_ANA_PCIE_1
    N19 C1 LT1 1 2
    L18 VCC0P9_ANA_PCIE_1 SVR_IND C2 SH00001BK00

    u
    VCC0P9_ANA_PCIE_2 SVR_IND

    10P_0201_50V

    47U_0603_6.3V6M

    47U_0603_6.3V6M

    47U_0603_6.3V6M
    M18 D1 2 2 2 2
    +V0P9_USB N18 VCC0P9_ANA_PCIE_2 SVR_IND CT296 CT87 CT88 CT89

    VCC
    VCC0P9_ANA_PCIE_2 @RF@

    c
    0.9V @ 220mA R15 A1
    R16 VCC0P9_USB SVR_VSS B1 1 1 1 1
    VCC0P9_USB SVR_VSS B2

    r
    SVR_VSS
    1U_0201_6.3VM

    1U_0201_6.3VM

    R8 SI:RF request
    R9 VCC0P9_CIO +V0P9_LVR_OUT

    ci
    1 1 VCC0P9_CIO
    CT74

    CT75

    R11 0.9V @ 55mA


    R12 VCC0P9_CIO F18
    VCC0P9_CIO VCC0P9_LVR H18
    2 2 3.3V @ 100mA VCC0P9_LVR

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    1U_0201_6.3VM

    1U_0201_6.3VM
    L16 J11
    J16 VCC3P3_ANA_PCIE VCC0P9_LVR H11
    C VCC3P3_ANA_USB2 VCC0P9_LVR_SENSE 1 1 1 1 C

    1U_0201_6.3VM

    1U_0201_6.3VM

    CT101

    CT102
    3.3V @ 100mA

    CT99

    CT100
    1 1 A6 V5
    VSS_ANA VSS_ANA

    l
    CT103

    CT104
    A8 V6
    A10 VSS_ANA VSS_ANA V8 2 2 2 2
    A12 VSS_ANA VSS_ANA V9
    +V0P9_CIO 2 2 A14 VSS_ANA VSS_ANA V15

    ia
    A16 VSS_ANA VSS_ANA V16
    A18 VSS_ANA VSS_ANA V20
    0.9V @ 280mA A20 VSS_ANA VSS_ANA W5
    A22 VSS_ANA VSS_ANA W6

    t
    VSS_ANA VSS_ANA
    1U_0201_6.3VM

    1U_0201_6.3VM

    1U_0201_6.3VM

    B6 W8
    B8 VSS_ANA VSS_ANA W9
    1 1 1 VSS_ANA VSS_ANA
    CT105

    CT106

    CT107

    B10 W20
    B12 VSS_ANA VSS_ANA W22

    n
    B14 VSS_ANA VSS_ANA W23
    2 2 2 B16 VSS_ANA VSS_ANA Y9
    B18 VSS_ANA VSS_ANA Y13
    VSS_ANA VSS_ANA

    e
    B20 Y20
    B22 VSS_ANA VSS_ANA AA22
    D8 VSS_ANA VSS_ANA AA23
    D9 VSS_ANA VSS_ANA AB6
    VSS_ANA VSS_ANA

    id
    D11 AB8
    D12 VSS_ANA VSS_ANA AB10
    D13 VSS_ANA VSS_ANA AB12
    D15 VSS_ANA VSS_ANA AB14
    D16 VSS_ANA VSS_ANA AB16

    f
    GND
    D18 VSS_ANA VSS_ANA AB18
    E8 VSS_ANA VSS_ANA AB20
    E9 VSS_ANA VSS_ANA AB22
    E11 VSS_ANA VSS_ANA AC6

    n
    E15 VSS_ANA VSS_ANA AC8
    E16 VSS_ANA VSS_ANA AC10
    E22 VSS_ANA VSS_ANA AC12
    +3VALW +VCC3V3_S0_TBT E23 VSS_ANA VSS_ANA AC14

    o
    F9 VSS_ANA VSS_ANA AC16
    B F16 VSS_ANA VSS_ANA AC18 B
    F20 VSS_ANA VSS_ANA AC20
    VSS_ANA VSS_ANA

    c
    1 LT32 2 G22 AC22
    0_0603_5% G23 VSS_ANA VSS_ANA D5
    VSS_ANA VSS
    1U_0201_6.3VM

    H1 E4
    VSS_ANA VSS
    47U_0603_6.3V6M

    47U_0603_6.3V6M

    1 2 2 H2 E5
    VSS_ANA VSS
    CT152

    CT153

    CT154

    H12 E6
    H13 VSS_ANA VSS F5
    H15 VSS_ANA VSS F6

    L
    2 1 1 H16 VSS_ANA VSS H5
    H20 VSS_ANA VSS H8
    J5 VSS_ANA VSS J8
    J18 VSS_ANA VSS J12
    J19 VSS_ANA VSS J13
    VSS_ANA VSS

    A
    J20 J15
    J22 VSS_ANA VSS L13
    J23 VSS_ANA VSS M11
    K1 VSS_ANA VSS M12
    K2 VSS_ANA VSS N8

    P
    L5 VSS_ANA VSS N9
    L20 VSS_ANA VSS N11
    L22 VSS_ANA VSS N12
    L23 VSS_ANA VSS N13
    M1 VSS_ANA VSS T6
    M2 VSS_ANA VSS T8
    M5 VSS_ANA VSS T9

    M
    M19 VSS_ANA VSS T13
    M20 VSS_ANA VSS T15
    N5 VSS_ANA VSS T16
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA

    N20 VSS_ANA VSS T18


    N22 VSS_ANA VSS AB1
    VSS_ANA VSS

    O
    N23 AC2
    VSS_ANA VSS
    UT1B
    P1
    P2
    R5
    R18
    R19
    R20
    R22
    R23
    T1
    T2
    T5
    T20
    U22
    U23

    A A

    C
    S IC JHL6540 SLLSN C1 FC-CSP THUNDERBOLT
    SA00009ZV30

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2017/03/20 Deciphered Date 2020/03/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Thunderbolt AlpineRidge (2/2)
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 34 of 55
    5 4 3 2 1
    5 4 3 2 1

    +TBTA_VBUS_L +TBTA_VBUS

    FF:46.2
    +5VALW +5VALW @ JPHW3 +3V_TBTB_PDLDO
    3A 1 2
    1 2
    1 1 1

    1000P_0201_50V7K
    CT221
    3A CT223 JUMP_43X39

    1U_0402_25V6K
    CT222 TBTB_ADCIN1 10K_0201_1% 2 1 RT762
    CT224 0.1U_0201_25V6K

    P
    1 2 2 2 2 TBTB_ADCIN2 200K_0201_5% 1 2 RT763
    SI: Swap +TBTA_VBUS & +TBTB_VBUS
    2 2
    4.7U_0402_10V

    4.7U_0402_10V

    22U_0603_6.3V6M
    UT3
    CT225

    CT226

    +TBTB_VBUS_L +TBTB_VBUS
    D 1 1
    SI: CT223 CT230 D

    H
    3A 7 8 change from SE000012900 to SE000009R80 @ JPHW4
    PP_HV1 VBUS1 3A 1 2
    CT232 1 2

    1000P_0201_50V7K
    1 2 1 2 JUMP_43X39 TBTB_ADCIN1 100K_0201_1% 2 1 RT768
    1 1 1

    1U_0402_25V6K
    PP_HV2 VBUS2

    CT229
    CT230

    r
    22U_0603_6.3V6M CT228 1 2 10U_0402_6.3V6M CT233 TBTB_ADCIN2 100K_0201_1% 2 1 RT769
    place near 16,37 pin +3VL
    0.1U_0201_25V6K
    CT227 5 2 2 2 TBTA_PPEXT_EN 100K_0201_5% 2 1 RT842
    LDO_3V3 +3V_TBTB_PDLDO
    1 2 2 RT826 1+3VL_TBTAB 3 26

    fo
    VIN_3V3 LDO_1V8 +1.8V_TBTB_PDLDO TBTB_PPEXT_EN
    0_0402_5% 100K_0201_5% 2 1 RT843
    10U_0603_6.3V6M SI: Add RT826 CT234 1 2 10U_0603_6.3V6M
    15 TBT_RESET_N 100K_0201_1% 2 @ 1 RT1093
    C1_CC1 17 +TBTA_CC1 (38)
    EC_SMB_CK2 18 C1_CC2 +TBTA_CC2 (38) TBT_A_DP_MODE 100K_0201_1% 2 @ 1 RT1094
    (29,36) EC_SMB_CK2 EC_SMB_DA2 I2C1_SCL
    To EC (29,36) EC_SMB_DA2
    19 36 PIR39 SI: Change to SE00000XG80
    TBTB_I2C_IRQ2Z 20 I2C1_SDA C2_CC1 38 +TBTB_CC1 (38) TBT_A_POL 100K_0201_1% 2 1 RT1095

    t
    (29) TBTB_I2C_IRQ2Z @
    I2C1_IRQ C2_CC2 +TBTB_CC2 (38)

    220P_0201_50V7K

    220P_0201_50V7K

    10P_0402_50V8C

    10P_0402_50V8C

    10P_0402_50V8C

    10P_0402_50V8C
    TBT_I2C_SCL 23 TBT_A_TBT_MODE 100K_0201_1% 2 @ 1 RT1096

    i
    1 1 1 1 1 1

    220P_0201_50V7K

    220P_0201_50V7K
    (33) TBT_I2C_SCL I2C2_SCL
    To Alpine Ridge TBT_I2C_SDA 24 4 TBTB_ADCIN1

    CT235

    CT236

    @RF@ CT308

    @RF@ CT309

    @RF@ CT310

    @RF@ CT311
    (33) TBT_I2C_SDA I2C2_SDA ADCIN1 1 1
    TBTB_I2C_INT 25 6 TBTB_ADCIN2 TBT_B_DP_MODE 100K_0201_1% 2 1 RT1097

    CT237

    CT238
    (33) TBT_I2C_INT @
    I2C2_IRQ ADCIN2
    16 0.9A 2 2 2 2 2 2 TBT_B_POL 100K_0201_1% 2 @ 1 RT1098

    u
    PP1_CABLE 37 2 2
    TBT_EE_DO PP2_CABLE +5VALW TBT_B_TBT_MODE
    27 100K_0201_1% 2 @ 1 RT1099
    (33) TBT_EE_DO TBT_EE_DI 28 SPI_MISO(GPIO8) 41 USB20_P5
    USB20_P5 (11,38)

    c
    (33) TBT_EE_DI TBT_EE_CLK_PD 29 SPI_MOSI(GPIO9) C1_USB_P(GPIO18) 42 USB20_N5
    SPI_CLK(GPIO10) C1_USB_N(GPIO19) USB20_N5 (11,38)
    TBT_EE_CS_N 30
    (33) TBT_EE_CS_N SPI_SS(GPIO11) 43 USB20_P1

    r
    C2_USB_P(GPIO20) USB20_N1 USB20_P1 (11,38)
    44
    C2_USB_N(GPIO21) USB20_N1 (11,38) +3V_TBTB_PDLDO

    ci
    9 TBT_RESET_N PIR2 SI: Add type-C additional features by PD
    GPIO0 TBT_RESET_N (33)
    RT1109 2 1 HRESET 35 10 PWR_LED#_PD (29,36)
    (29) HRESET_988 HRESET GPIO1 TBTB_I2C_IRQ2Z RT759 2
    0_0201_5% 11 ON/OFF#_988 (29) 1 10K_0201_1%
    GPIO2 21 TBT_A_HPD
    TBT_A_HPD (33) To Alpine Ridge
    C HPD1(GPIO3) 22 TBT_B_HPD HRESET RT760 2 @ 1 100K_0201_5% C
    HPD2(GPIO4) TBT_B_HPD (33)
    45 12 TBT_A_DP_MODE
    NC GPIO5 TBT_A_DP_MODE (38)

    l
    EMI request 46 13 TBT_A_POL RT761 1 2 100K_0201_5%
    NC GPIO6 TBT_A_TBT_MODE TBT_A_POL (38)
    14
    GPIO7 TBT_A_TBT_MODE (38)
    RT819 2 1TBT_EE_CLK_PD 47 31 GPIO12 TP@ T353 @
    (33) TBT_EE_CLK 0_0201_5% G-Pad GPIO12 32 TBT_B_DP_MODE CT231 1 2 0.01U_0201_6.3V7K

    ia
    GPIO13 TBT_B_DP_MODE (38)
    33 TBT_B_POL
    10P_0201_25V8

    1 GPIO14(PWM) TBT_B_POL (38)


    A1 34 TBT_B_TBT_MODE
    CT291

    NC1 GPIO15(PWM) TBTA_PPEXT_EN TBT_B_TBT_MODE (38)


    A2 39
    NC2 GPIO16(PP_EXT1) TBTA_PPEXT_EN (40)
    A3 40 TBTB_PPEXT_EN
    TBTB_PPEXT_EN (40)

    t
    @EMI@ 2 A4 NC3 GPIO17(PP_EXT2)
    NC4

    n
    TPS65988CERJTR_QFN48_6X6
    SA0000ABQ60

    id e
    n f
    o
    B B

    L c
    Vinafix.com
    P A
    A
    TPS65988 I2C Address Setting

    O M A

    C Security Classification
    Issued Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    2017/03/20

    Size Document Number


    Custom
    Compal Secret Data
    Deciphered Date 2020/03/20 Title
    Compal Electronics, Inc.
    TPS65988 PORT1/2
    LA-F803P
    Rev
    0.1

    Date: Friday, June 08, 2018 Sheet 35 of 55


    5 4 3 2 1
    5 4 3 2 1

    +20V_VIN_TBTC +5VALW UT4 +TBTC_VBUS_L +3V_TBTC_PDLDO +1.8V_TBTC_PDLDO

    3A 7 8 +TBTC_VBUS_L +TBTC_VBUS +3V_TBTC_PDLDO


    PP_HV1 VBUS1 +5VALW
    @ JPHW8 TBTC_I2C_IRQ2Z RT770 2 1 10K_0201_5%
    3A 1 2 3A JUMP_43X118
    PP_HV2 VBUS2 place near pin7 1 2
    1 2

    1000P_0201_25V7K
    4.7U_0402_6.3V6M
    +3VL EMI@
    SI:Add 0ohm for debug 5.5mA 2 1

    22U_0603_6.3V6M

    0.1U_0201_25V6K
    5 1 1 1

    1U_0402_25V6K
    2 RT827 1 +3VL_TBTC 3 LDO_3V3 26

    CT239

    CT241

    CT242
    CT243 CT244
    0_0402_5% VIN_3V3 LDO_1V8
    1 2
    15 +TBTC_CC1_CONN 2 2 2 +3VS
    D C1_CC1 D
    +TBTC_CC2_CONN

    H
    17
    To Port A 0_0201_5% 2 1 RT828 EC_SMB_CK2_R 18 C1_CC2

    120P_0402_50V

    120P_0402_50V
    (29,35) EC_SMB_CK2 2 1 RT829 EC_SMB_DA2_R I2C1_SCL
    0_0201_5% 19 36 1 1
    (29,35) EC_SMB_DA2 I2C1_SDA C2_CC1 MUX_AMSEL
    20 38 2 1 10K_0201_5%

    CT246

    CT245
    RT771 @
    +3V_TBTC_PDLDO (29) TBTC_I2C_IRQ2Z I2C1_IRQ C2_CC2

    r
    10K_0201_5% 2 1 RT774 23 +5VALW MUX_EN RT772 2 @ 1 10K_0201_5%
    10K_0201_5% 2 1 RT775 24 I2C2_SCL 4 TBTC_ADCIN1 2 2
    10K_0201_5% 2 1 RT776 25 I2C2_SDA ADCIN1 6 TBTC_ADCIN2 MUX_POL RT773 2 @ 1 10K_0201_5%
    I2C2_IRQ ADCIN2 +3V_TBTC_PDLDO +3VL +1.8V_TBTC_PDLDO
    0.9A

    fo
    16
    PP1_CABLE 37
    TBTC_EE_DO 27 PP2_CABLE

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    4.7U_0402_6.3V6M
    TBTC_EE_DI 28 SPI_MISO(GPIO8) 41 USB20_P7
    SPI_MOSI(GPIO9) C1_USB_P(GPIO18) USB20_P7 (11) 1 1 1
    TBTC_EE_CLK 2 RT786 1 TBTC_EE_CLK_R 29 42 USB20_N7
    SPI_CLK(GPIO10) C1_USB_N(GPIO19) USB20_N7 (11) DT1
    0_0201_5% TBTC_EE_CS_N 30

    CT247

    CT248

    CT249
    10P_0201_25V8

    1 SPI_SS(GPIO11) 43 DP3_AUXN_SUB1 1 1 9 DP3_AUXN_SUB1

    t
    CT251

    EMI request 10
    C2_USB_P(GPIO20) TP@ T159 2 2 2
    44 TP@ T160
    C2_USB_N(GPIO21) +TBTC_CC1_CONN 2 2 8 +TBTC_CC1_CONN

    i
    9
    @EMI@ 2
    RT777 9 DP3_AUXP_SUB2 4 4 7 7 DP3_AUXP_SUB2
    2 1 GPIO0 MUX_AMSEL (37)
    35 10
    HRESET GPIO1 MUX_EN (37) +TBTC_CC2_CONN 5 5 +TBTC_CC2_CONN
    100K_0201_5% 11 6

    u
    6
    GPIO2 TBT_DPSRC_HPD MUX_POL (37) +3VL
    21
    HPD1(GPIO3) TBT_DPSRC_HPD (33,37)
    22 3 3
    45 HPD2(GPIO4) 12 PIR2 SI: Add type-C additional features by PD
    PWR_LED#_PD (29,35)

    c
    46 NC GPIO5 13 8
    NC GPIO6 ON/OFF#_987 (29)
    RT844 14

    82P_0402_50V8J

    82P_0402_50V8J

    68P_0201_50V8J
    10U_0402_6.3V6M

    10U_0402_6.3V6M
    0.1U_0201_25V6K

    0.1U_0201_25V6K
    GPIO7 TP@ T366
    2 1 47 31 RF@ 1 RF@ 1 RF@ RF@ 1 RF@ 1 RF@ 1 @RF@

    r
    (29) RESET_987 G-Pad GPIO12 TP@ T367 1 1
    32

    CT313

    CT314

    CT315

    CT316

    CT317

    CT318

    CT329
    0_0201_5% TP@ T154 L05ESDL5V0NA-4_SLP2510P8-10-9
    GPIO13 33

    ci
    GPIO14(PWM) TP@ T155 SC300001Y00
    A1 34 TP@ T156 TBT_C_PPEXT_EN
    A2 NC1 GPIO15(PWM) 39 2 2 2 2 2 2 2 ESD@
    A3 NC2 GPIO16(PP_EXT1) 40
    NC3 GPIO17(PP_EXT2) TP@ T158

    1
    A4
    NC4 RT822
    C C
    100K_0201_5%
    EMI@
    S IC PTPS65987DCERJTR VQFN 48P POWER SW LT33

    2
    SA0000BL010 USB20_P7 1 2 USB20_P7_R
    1 2

    ia
    USB20_N7 4 3 USB20_N7_R
    4 3

    SPI
    +3V_TBTC_PDLDO

    +3V_TBTC_PDLDO DLM0NSN900HY2D_4P

    t
    SM070005U00
    ESD@

    0.1U_0201_6.3V6K
    DT2

    10K_0201_1%

    10K_0201_1%
    1

    1
    USB20_P7_R USB20_P7_R

    3.3K_0201_1%
    RT780

    3.3K_0201_1%
    RT781

    3.3K_0201_1%
    RT782
    1 1 1 10 9

    1
    RT778

    RT779

    1
    USB20_N7_R USB20_N7_R

    3.3K_0201_1%
    RT783
    2 2 8

    CT250
    9

    e
    ON/OFF# 4 4 7 7 ON/OFF#
    (29,31) ON/OFF#

    2
    TBTC_ADCIN1 UT5 LID_SW# 5 5 6 6 LID_SW#
    (29,31) LID_SW#

    2
    TBTC_ADCIN2 TBTC_EE_CS_N 1 8
    CS# VCC

    id
    TBTC_EE_DO 2 7 TBTC_HOLD_N 3 3
    TBTC_EE_WP_N 3 DO(IO1) HOLD#(IO3) 6 TBTC_EE_CLK

    100K_0201_1%
    WP#(IO2) CLK

    1
    4 5 TBTC_EE_DI 8

    100K_0201_1%
    GND DI(IO0) 9
    thermal pad

    RT784

    RT785
    f
    W25X20CLZPIG_WSON8 AZ1045-04F_DFN2510P10E-10-9
    SA000063100 SC300001Y00

    n
    co
    B +TBTC_VBUS B

    W = 200 mils
    1000P_0201_50V7K

    0.1U_0201_25V6K
    0.022U_0402_25V7K

    1 1 1 ESD@
    DT4
    1
    CT253

    USB3_DP3_MRX_DTX_P2 1 1 9 USB3_DP3_MRX_DTX_P2
    CT295

    CT252

    DT3 10

    PESD24VS1UB_SOD523-2

    L
    2 2 2 ESD@ USB3_DP3_MRX_DTX_N2 2 2 9 8 USB3_DP3_MRX_DTX_N2
    EMI@ EMI@ JTYPEC3
    2

    A1 B1 USB3_DP3_MTX_C_DRX_P2 4 4 7 7 USB3_DP3_MTX_C_DRX_P2
    EMI@ GND GND
    USB3_DP3_MTX_C_DRX_P1 A2 B2 USB3_DP3_MTX_C_DRX_P2 USB3_DP3_MTX_C_DRX_N2 5 5 6 6 USB3_DP3_MTX_C_DRX_N2
    (37) USB3_DP3_MTX_C_DRX_P1 USB3_DP3_MTX_C_DRX_N1 SSTXP1 SSTXP2 USB3_DP3_MTX_C_DRX_N2 USB3_DP3_MTX_C_DRX_P2 (37)

    A
    A3 B3
    (37) USB3_DP3_MTX_C_DRX_N1 SSTXN1 SSTXN2 USB3_DP3_MTX_C_DRX_N2 (37) 3 3
    0.33U_0201_25V6K 1 2 CT254 A4 B4 CT256 1 2 0.33U_0201_25V6K
    VBUS VBUS 8
    +TBTC_CC1_CONN A5 B5 +TBTC_CC2_CONN

    P
    CC1 CC2
    USB20_P7_R A6 B6 USB20_P7_R AZ1045-04F_DFN2510P10E-10-9
    USB20_N7_R A7 DP1 DP2 B7 USB20_N7_R SC300001Y00
    DN1 DN2
    DP3_AUXN_SUB1 A8 B8 DP3_AUXP_SUB2 ESD@
    (37) DP3_AUXN_SUB1 SBU1 SBU2 DP3_AUXP_SUB2 (37) DT5
    0.33U_0201_25V6K 1 2 CT255 A9 B9 CT257 1 2 0.33U_0201_25V6K USB3_DP3_MTX_C_DRX_N1 1 1 9 USB3_DP3_MTX_C_DRX_N1

    M
    10
    VBUS VBUS
    PIR28 SI: Add Intel request USB3_DP3_MRX_R_DTX_N2 A10 B10 USB3_DP3_MRX_R_DTX_N1 USB3_DP3_MTX_C_DRX_P1 2 2 9 8 USB3_DP3_MTX_C_DRX_P1
    USB3_DP3_MRX_R_DTX_P2 A11 SSRXN2 SSRXN1 B11 USB3_DP3_MRX_R_DTX_P1
    SSRXP2 SSRXP1 USB3_DP3_MRX_DTX_N1 4 4 7 USB3_DP3_MRX_DTX_N1
    7
    A12 B12
    GND GND

    O
    USB3_DP3_MRX_DTX_P1 5 5 6 USB3_DP3_MRX_DTX_P1
    Crx Rb 6

    1 4 3 3
    RT1113 1 2 0.33U_0201_25V6K USB3_DP3_MRX_R_DTX_N2 2 GND GND 5
    (37) USB3_DP3_MRX_DTX_N2 USB3_DP3_MRX_R_DTX_P2 GND GND
    A RT1114 1 2 0.33U_0201_25V6K 3 6 8 A
    (37) USB3_DP3_MRX_DTX_P2 USB3_DP3_MRX_R_DTX_N1 GND GND
    1 2

    C
    RT1115 0.33U_0201_25V6K
    (37) USB3_DP3_MRX_DTX_N1 USB3_DP3_MRX_R_DTX_P1
    RT1116 1 2 0.33U_0201_25V6K
    (37) USB3_DP3_MRX_DTX_P1 AZ1045-04F_DFN2510P10E-10-9
    SINGA_2UB1734-C00111F
    CONN@ SC300001Y00
    USB3_DP3_MRX_R_DTX_N2 RT1120 1 2 200K_0201_5%
    USB3_DP3_MRX_R_DTX_P2 RT1119 1 2 200K_0201_5%
    USB3_DP3_MRX_R_DTX_N1 RT1118 1 2 200K_0201_5%
    USB3_DP3_MRX_R_DTX_P1 RT1117 1 2 200K_0201_5%
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2017/03/20 Deciphered Date 2020/03/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Type-C PORT3-TPS65987D
    Size Document Number Rev
    Intel request AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 36 of 55
    5 4 3 2 1
    5 4 3 2 1

    +3VS
    @
    +3VS_MUX
    +3VS_MUX

    1 1 1 1
    Function Field:4.14

    10U_0402_6.3V6M

    0.1U_0201_6.3V6K

    0.1U_0201_6.3V6K

    0.1U_0201_6.3V6K

    0.1U_0201_6.3V6K
    1 2 1

    CT270

    CT271

    CT272

    CT273

    CT274
    RT6 0_0603_5%

    2
    2 2 2 2

    GPIO/I2C mode
    D
    +3VS_MUX

    1
    6
    20
    28
    UT11

    VCC
    VCC
    VCC
    VCC
    TX1P
    TX1N
    RX1P
    RX1N
    33
    34
    30
    31
    USB3_DP3_MTX_DRX_P1
    USB3_DP3_MTX_DRX_N1
    CT279
    CT280
    1
    1
    2 0.22U_0201_25V5K
    2 0.22U_0201_25V5K
    USB3_DP3_MTX_C_DRX_P1 (36)
    USB3_DP3_MTX_C_DRX_N1 (36)
    USB3_DP3_MRX_DTX_P1 (36)
    USB3_DP3_MRX_DTX_N1 (36)

    H P D

    r
    CT3 1 2 0.22U_0201_6.3V6M SOC_DP3_P0_C 9 37 USB3_DP3_MTX_DRX_P2 CT281 1 2 0.22U_0201_25V5K
    (33) TBT_DP_ML0_P_C SOC_DP3_N0_C DP0P TX2P USB3_DP3_MTX_DRX_N2 USB3_DP3_MTX_C_DRX_P2 (36)
    CT17 1 2 0.22U_0201_6.3V6M 10 36 CT282 1 2 0.22U_0201_25V5K USB3_DP3_MTX_C_DRX_N2 (36)
    (33) TBT_DP_ML0_N_C 1 2 SOC_DP3_P1_C DP0N TX2N
    CT5 0.22U_0201_6.3V6M 12 40
    (33) TBT_DP_ML1_P_C 1 2 SOC_DP3_N1_C 13 DP1P RX2P 39 USB3_DP3_MRX_DTX_P2 (36)
    CT19 0.22U_0201_6.3V6M

    fo
    (33) TBT_DP_ML1_N_C SOC_DP3_P2_C DP1N RX2N USB3_DP3_MRX_DTX_N2 (36)
    CT20 1 2 0.22U_0201_6.3V6M 15
    (33) TBT_DP_ML2_P_C 1 2 SOC_DP3_N2_C 16 DP2P 27 DP3_AUXN_SUB1
    CT21 0.22U_0201_6.3V6M DP3_AUXN_SUB1 (36)
    (33) TBT_DP_ML2_N_C 1 2 SOC_DP3_P3_C 18 DP2N SBU1 26 DP3_AUXP_SUB2
    CT22 0.22U_0201_6.3V6M DP3_AUXP_SUB2 (36)
    (33) TBT_DP_ML3_P_C SOC_DP3_N3_C DP3P SBU2
    CT24 1 2 0.22U_0201_6.3V6M 19
    (33) TBT_DP_ML3_N_C DP3N MUX_USB3_EQ0
    24 38
    (33) TBT_DP_AUX_P_C AUXP EQ0 MUX_USB3_EQ1
    PV: remove MUX side 0.1u Cap 25 35
    (33) TBT_DP_AUX_N_C AUXN EQ1

    t
    CT287 1 2 0.22U_0201_6.3V6MUSB3_CTX_DRX_P3_C 8 17 MUX_I2C_EN
    (11) USB3_CTX_DRX_P3 SSTXP I2C_EN
    CT288 1 2 0.22U_0201_6.3V6MUSB3_CTX_DRX_N3_C 7 21 MUX_POL_R RT799 1 2 0_0201_5%

    i
    (11) USB3_CTX_DRX_N3 SSTXN FLIP/SCL MUX_POL (36)
    CT285 1 2 0.22U_0201_6.3V6MUSB3_CRX_DTX_P3_C 5 22 MUX_AMSEL_R RT800 1 2 0_0201_5%
    (11) USB3_CRX_DTX_P3 SSRXP CTL0/SDA MUX_AMSEL (36)
    CT286 1 2 0.22U_0201_6.3V6MUSB3_CRX_DTX_N3_C 4 23 MUX_EN_R RT801 1 2 0_0201_5%
    (11) USB3_CRX_DTX_N3 SSRXN CTL1/HPDIN MUX_CAD_SNK MUX_EN (36)
    29
    MUX_DP_EQ0 14 CAD_SNK/RSVD1 32 TBT_DPSRC_HPD

    u
    DPEQ0/A1 HPDIN/RSVD2 TBT_DPSRC_HPD (33,36)
    MUX_DP_EQ1 2
    MUX_SS_EQ0 11 DPEQ1 41
    MUX_SS_EQ1 3 SSEQ0/A0 GND RT1111 1 @ 2 22_0201_5% MUX_DCI_CLK (10)

    c
    SSEQ1 RT1112 1 @ 2 22_0201_5% +3VS_MUX
    MUX_DCI_DAT (10)
    TUSB546A-DCIRNQR_WQFN40_4X6

    1K_0201_5%
    1
    RT856
    I2C@
    ci

    2
    +3VS_MUX
    MUX_I2C_EN
    C C
    MUX_CAD_SNK RT859 1 2 100K_0201_5%

    1K_0201_5%
    20K_0201_5%
    1

    1
    RT860 1 @ 2 100K_0201_5%

    RT857

    RT858
    @

    ia

    2
    TBT_DP_AUX_N_C RT807 1 2 100K_0201_5%
    +3VS_MUX

    +3VS_MUX +3VS_MUX +3VS_MUX

    n t +3VS_MUX +3VS_MUX +3VS_MUX


    1K_0201_5%

    1K_0201_5%

    1K_0201_5%

    1K_0201_5%

    1K_0201_5%

    1K_0201_5%
    1

    1
    e
    RT813

    RT814

    RT841

    RT847

    RT850

    RT853
    TBT_DP_AUX_P_C RT812 1 2 100K_0201_5% @ @ @ @ @

    id
    DP3_AUXN_SUB1 RT815 1 2 2M_0201_5%
    2

    2
    DP3_AUXP_SUB2 RT816 1 2 2M_0201_5% MUX_DP_EQ0 MUX_DP_EQ1 MUX_SS_EQ0 MUX_SS_EQ1 MUX_USB3_EQ0 MUX_USB3_EQ1

    f
    1K_0201_5%

    1K_0201_5%

    1K_0201_5%

    1K_0201_5%

    1K_0201_5%

    1K_0201_5%
    20K_0201_5%

    20K_0201_5%

    20K_0201_5%

    20K_0201_5%

    20K_0201_5%

    20K_0201_5%
    1

    1
    RT817

    RT818

    RT840

    RT838

    RT845

    RT846

    RT848

    RT849

    RT851

    RT852

    RT854

    RT855
    @
    @ @ @ @ @ @

    n
    MUX_POL_R RT808 1 2 100K_0201_5%
    2

    2
    MUX_AMSEL_R RT809 1 2 100K_0201_5%

    o
    MUX_EN_R RT810 1 2 100K_0201_5%
    B B

    L c
    P A
    A

    O M A

    C Security Classification
    Issued Date 2017/03/20
    Compal Secret Data
    Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    2020/03/20 Title

    Size
    DP MUX
    Compal Electronics, Inc.

    Document Number

    LA-F803P
    Rev
    0.1

    Date: Friday, June 08, 2018 Sheet 37 of 53


    5 4 3 2 1
    A B C D E

    DT6
    TBTB_SBU1 1 1 10 9 TBTB_SBU1

    1000P_0201_50V7K
    0.022U_0402_25V7K
    +3VALW +TBTB_CC1 2 2 8 +TBTB_CC1

    0.1U_0201_25V6K
    1 1 1 9
    CT259
    TBTB_SBU2 4 4 7 TBTB_SBU2

    CT293

    CT258
    UT8 7
    13 20 TBT_B_SUB2_C
    2 2 2 VCC A1_OUTp TBT_B_SUB1_C TBT_B_SUB2_C (33) +TBTB_CC2 +TBTB_CC2
    19 5 5 6 6
    +TBTB_VBUS TBTB_SBU1 A1_OUTn TBT_B_SUB1_C (33)
    1
    TBTB_SBU2 2 A_INp 18 TBT_B_SUB1_C 3 3
    EMI@ EMI@ A_INn A0_OUTp 17 TBT_B_SUB2_C
    EMI@ RT792 1 2 0_0201_5%14 A0_OUTn 8
    W = 200 mils TBT_B_DP_MODE
    16 SAI
    EN_A SAO
    15 TBT_B_POL
    TBT_B_POL (35)

    1
    P
    L05ESDL5V0NA-4_SLP2510P8-10-9
    DT7 3 6 TBT_B_LSRX
    B_INp B1_OUTp TBT_B_LSRX (33) SC300001Y00
    EMI@ PESD24VS1UB_SOD523-2 4 7 TBT_B_LSTX
    LT35 B_INn B1_OUTn TBT_B_LSTX (33) ESD@
    ESD@
    USB20_N1 1 2 USB20_N1_R JTYPEC1 RT793 1 2 0_0201_5%12 8 TBT_B_LSTX

    2
    (11,35) USB20_N1 1 2 SBI B0_OUTp TBT_B_LSRX
    A1 B1 10 9
    1 GND GND TBT_B_TBT_MODE EN_B B0_OUTn 1

    H
    USB20_P1 4 3 USB20_P1_R TBT_B_TTX_C_DRX_P1 A2 B2 TBT_B_TTX_C_DRX_P2 5 11 TBT_B_TRX_R_DTX_P1 DT9 1 ESD@ 2
    (11,35) USB20_P1 4 3 TBT_B_TTX_C_DRX_N1 A3 SSTXP1 SSTXP2 B3 TBT_B_TTX_C_DRX_N2 21 GND SBO
    SSTXN1 SSTXN2 Thermal pad ESD8011MUT5G_X3DFN2-2
    DLM0NSN900HY2D_4P 0.33U_0201_25V6K 1 2 CT261 A4 B4 CT260 1 2 0.33U_0201_25V6K TS3DS10224RUKR_WQFN20_3X3
    VBUS VBUS TBT_B_TRX_R_DTX_N1 SC40000DM00
    SM070005U00 DT10 1 ESD@ 2
    +TBTB_CC1 +TBTB_CC2

    r
    A5 B5
    CC1 CC2 ESD8011MUT5G_X3DFN2-2
    USB20_P1_R A6 B6 USB20_P1_R
    USB20_N1_R DP1 DP2 USB20_N1_R TBT_B_TTX_C_DRX_P1 SC40000DM00
    A7 B7 DT11 1 ESD@ 2
    DN1 DN2

    fo
    TBTB_SBU1 A8 B8 TBTB_SBU2 ESD8011MUT5G_X3DFN2-2
    SBU1 SBU2
    TBT_B_TTX_C_DRX_N1 SC40000DM00
    0.33U_0201_25V6K 1 2 CT262 A9 B9 CT263 1 2 0.33U_0201_25V6K DT12 1 ESD@ 2
    VBUS VBUS
    TBT_B_TRX_N2 A10 B10 TBT_B_TRX_N1 ESD8011MUT5G_X3DFN2-2
    TBT_B_TRX_P2 A11 SSRXN2 SSRXN1 B11 TBT_B_TRX_P1
    SSRXP2 SSRXP1 TBT_B_TRX_R_DTX_P2 SC40000DM00
    DT13 1 ESD@ 2
    A12 B12
    Crx Rb

    t
    GND GND ESD8011MUT5G_X3DFN2-2
    ESD@ TBT_B_TRX_R_DTX_N2 RT1139 1 2 0.33U_0201_25V6K TBT_B_TRX_N2
    DT8 TBT_B_TRX_R_DTX_P2 TBT_B_TRX_P2 TBT_B_TRX_R_DTX_N2 SC40000DM00
    1 4 1 2 DT14 1 ESD@ 2

    i
    RT1140 0.33U_0201_25V6K
    USB20_N5_R 1 1 9 USB20_N5_R 2 GND GND 5 TBT_B_TRX_R_DTX_N1 RT1138 1 2 0.33U_0201_25V6K TBT_B_TRX_N1
    10
    3 GND GND 6 TBT_B_TRX_R_DTX_P1 RT1137 1 2 0.33U_0201_25V6K TBT_B_TRX_P1 ESD8011MUT5G_X3DFN2-2
    USB20_P5_R 2 2 8 USB20_P5_R GND GND
    9
    TBT_B_TTX_C_DRX_P2 SC40000DM00
    DT15 1 ESD@ 2

    u
    USB20_N1_R 4 4 7
    7 USB20_N1_R SINGA_2UB1734-C00111F TBT_B_TRX_N2 RT1128 1 2 200K_0201_5%
    TBT_B_TRX_P2 RT1127 1 2 200K_0201_5% ESD8011MUT5G_X3DFN2-2
    CONN@
    USB20_P1_R 5 5 6 6 USB20_P1_R TBT_B_TRX_N1 RT1126 1 2 200K_0201_5%
    TBT_B_TRX_P1 TBT_B_TTX_C_DRX_N2 SC40000DM00
    RT1125 1 2 200K_0201_5% DT17 1 ESD@ 2

    ri c
    3 3
    ESD8011MUT5G_X3DFN2-2
    8 TBT_A_TRX_R_DTX_N2 RT1142 1 2 0.33U_0201_25V6K TBT_A_TRX_N2
    TBT_A_TRX_R_DTX_P2 TBT_A_TRX_P2 SC40000DM00
    RT1144 1 2 0.33U_0201_25V6K
    TBT_A_TRX_R_DTX_N1 RT1143 1 2 0.33U_0201_25V6K TBT_A_TRX_N1
    AZ1045-04F_DFN2510P10E-10-9 TBT_A_TRX_R_DTX_P1 RT1141 1 2 0.33U_0201_25V6K TBT_A_TRX_P1
    SC300001Y00
    TBT_A_TRX_N2 RT1136 1 2 200K_0201_5%
    TBT_A_TRX_P2 RT1135 1 2 200K_0201_5%
    1000P_0201_50V7K

    0.1U_0201_25V6K
    0.022U_0402_25V7K

    TBT_A_TRX_N1 RT1134 1 2 200K_0201_5%


    1 1 1

    c
    CT265 TBT_A_TRX_P1 RT1133 1 2 200K_0201_5%
    CT294

    CT264

    2 2
    2 2 2 +TBTA_VBUS
    EMI@ EMI@ PIR27 SI: Add Intel request

    l
    EMI@
    W = 200 mils Intel request

    a
    DT16

    i
    PESD24VS1UB_SOD523-2
    ESD@
    JTYPEC2
    2

    t
    A1 B1
    EMI@ GND GND
    LT37 TBT_A_TTX_C_DRX_P1 TBT_A_TTX_C_DRX_P2
    A2 B2
    USB20_N5 1 2 USB20_N5_R TBT_A_TTX_C_DRX_N1 A3 SSTXP1 SSTXP2 B3 TBT_A_TTX_C_DRX_N2
    (11,35) USB20_N5 1 2 SSTXN1 SSTXN2

    n
    0.33U_0201_25V6K 1 2 CT266 A4 B4 CT267 1 2 0.33U_0201_25V6K
    USB20_P5 4 3 USB20_P5_R VBUS VBUS +3VALW
    (11,35) USB20_P5 4 3 +TBTA_CC1 +TBTA_CC2
    A5 B5
    CC1 CC2 UT10

    e
    DLM0NSN900HY2D_4P USB20_P5_R A6 B6 USB20_P5_R 13 20 TBT_A_SUB2_C
    SM070005U00 USB20_N5_R DP1 DP2 USB20_N5_R VCC A1_OUTp TBT_A_SUB1_C TBT_A_SUB2_C (33)
    A7 B7 19
    DN1 DN2 TBTA_SBU1 A1_OUTn TBT_A_SUB1_C (33)
    1
    TBTA_SBU1 A8 B8 TBTA_SBU2 TBTA_SBU2 2 A_INp 18 TBT_A_SUB1_C
    SBU1 SBU2 A_INn A0_OUTp

    id
    17 TBT_A_SUB2_C
    0.33U_0201_25V6K 1 2 CT268 A9 B9 CT269 1 2 0.33U_0201_25V6K RT796 1 2 0_0201_5%14 A0_OUTn
    VBUS VBUS 16 SAI 15 TBT_A_POL
    TBT_A_TRX_N2 TBT_A_TRX_N1 TBT_A_DP_MODE EN_A SAO TBT_A_POL (35)
    A10 B10
    TBT_A_TRX_P2 A11 SSRXN2 SSRXN1 B11 TBT_A_TRX_P1
    SSRXP2 SSRXP1 3 6 TBT_A_LSRX

    f
    B_INp B1_OUTp TBT_A_LSTX TBT_A_LSRX (33)
    A12 B12 4 7
    GND GND B_INn B1_OUTn TBT_A_LSTX (33)
    RT797 1 2 0_0201_5%12 8 TBT_A_LSTX
    1 4 10 SBI B0_OUTp 9 TBT_A_LSRX
    2 GND GND 5 TBT_A_TBT_MODE EN_B B0_OUTn

    n
    3 GND GND 6 5 11 DT18
    GND GND 21 GND SBO TBTA_SBU1 1 1 9 TBTA_SBU1
    10
    Thermal pad
    SINGA_2UB1734-C00111F TS3DS10224RUKR_WQFN20_3X3 +TBTA_CC1 2 2 9 8 +TBTA_CC1

    co
    CONN@
    3
    TBTA_SBU2 4 4 7 7 TBTA_SBU2 3

    +TBTA_CC2 5 5 6 6 +TBTA_CC2

    3 3

    TBT_A_DP_MODE
    (35) TBT_A_DP_MODE TBT_A_TBT_MODE L05ESDL5V0NA-4_SLP2510P8-10-9
    (35) TBT_A_TBT_MODE +TBTA_CC1
    (35) +TBTA_CC1 SC300001Y00

    L
    +TBTA_CC2
    (35) +TBTA_CC2 ESD@

    +TBTB_CC1
    (35) +TBTB_CC1 +TBTB_CC2
    (35) +TBTB_CC2
    TBT_B_DP_MODE

    A
    (35) TBT_B_DP_MODE TBT_B_TBT_MODE TBT_A_TRX_R_DTX_P1 DT20 1 ESD@ 2
    (35) TBT_B_TBT_MODE
    ESD8011MUT5G_X3DFN2-2
    TS3DS10224 Function Table NX3DV221GM Function Table SC40000DM00
    TBT_A_TRX_R_DTX_N1 DT21 1 ESD@ 2

    P
    ESD8011MUT5G_X3DFN2-2

    TBT_B_TRX_R_DTX_P1 TBT_A_TTX_C_DRX_P1 SC40000DM00


    DT22 1 ESD@ 2
    (33) TBT_B_TRX_R_DTX_P1 TBT_B_TRX_R_DTX_N1
    (33) TBT_B_TRX_R_DTX_N1
    ESD8011MUT5G_X3DFN2-2
    TBT_B_TTX_C_DRX_P1
    (33) TBT_B_TTX_C_DRX_P1 SC40000DM00
    TBT_B_TTX_C_DRX_N1 TBT_A_TTX_C_DRX_N1 DT23 1 ESD@ 2
    (33) TBT_B_TTX_C_DRX_N1

    M
    TBT_B_TRX_R_DTX_P2 ESD8011MUT5G_X3DFN2-2
    (33) TBT_B_TRX_R_DTX_P2 TBT_B_TRX_R_DTX_N2
    (33) TBT_B_TRX_R_DTX_N2 TBT_A_TRX_R_DTX_P2 SC40000DM00
    DT24 1 ESD@ 2
    TBT_B_TTX_C_DRX_P2
    (33) TBT_B_TTX_C_DRX_P2 TBT_B_TTX_C_DRX_N2 ESD8011MUT5G_X3DFN2-2
    (33) TBT_B_TTX_C_DRX_N2

    O
    TBT_A_TRX_R_DTX_N2 SC40000DM00
    DT25 1 ESD@ 2

    TBT_A_TRX_R_DTX_P1 ESD8011MUT5G_X3DFN2-2
    (33) TBT_A_TRX_R_DTX_P1 TBT_A_TRX_R_DTX_N1
    (33) TBT_A_TRX_R_DTX_N1 TBT_A_TTX_C_DRX_P2 SC40000DM00
    4 DT26 1 ESD@ 2 4
    TBT_A_TTX_C_DRX_P1
    (33) TBT_A_TTX_C_DRX_P1

    C
    TBT_A_TTX_C_DRX_N1 ESD8011MUT5G_X3DFN2-2
    (33) TBT_A_TTX_C_DRX_N1
    TBT_A_TRX_R_DTX_P2 TBT_A_TTX_C_DRX_N2 SC40000DM00
    DT27 1 ESD@ 2
    (33) TBT_A_TRX_R_DTX_P2 TBT_A_TRX_R_DTX_N2
    (33) TBT_A_TRX_R_DTX_N2
    ESD8011MUT5G_X3DFN2-2
    TBT_A_TTX_C_DRX_P2
    (33) TBT_A_TTX_C_DRX_P2 TBT_A_TTX_C_DRX_N2 SC40000DM00
    (33) TBT_A_TTX_C_DRX_N2

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2017/03/20 Deciphered Date 2020/03/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    TYPE-C Conn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 38 of 55
    A B C D E
    A B C D E

    1
    +5VALW +3VALW

    U6
    +3VS

    H P 1

    r
    1 14
    VIN1 VOUT1

    0.1U_0201_16V6K
    C70
    2 13 1 1 1
    VIN1 VOUT1

    10U_0402_6.3V6M

    68P_0201_50V8J
    C68 C69

    fo
    RC491 1 2 0_0201_5% EN_3.3VS 3 12 C66 1 2 100P_0201_50V8J @RF@
    (12,29,44,47) SUSP# ON1 CT1 RF@
    RC494 1 @ 2 0_0201_5% 4 11 2 2 2
    (9,12,29,33) PM_SLP_S3# VBIAS GND
    EN_5VS 5 10 C5237 1 2 100P_0201_50V8J +5VS
    1 ON2 CT2

    1
    t
    C5230 R5792 6 9

    i
    0.1U_0201_6.3V6K 100K_0201_5% 7 VIN2 VOUT2 8
    2 VIN2 VOUT2

    10U_0402_6.3V6M

    68P_0201_50V8J
    1 1
    1 1 15

    2
    u
    GPAD

    0.1U_0201_6.3V6K
    C5233
    C64 C65
    C67 RF@
    680P_0201_25V7K EM5209VF_DFN14_3X2 2 2

    c
    2 2
    SUSP# RC492 1 2 0_0201_5%

    2
    PM_SLP_S3# RC493 1 @ 2 0_0201_5%

    2
    EN_5VS
    0.1U_0201_6.3V6K
    C5232
    1
    100K_0201_5%
    R5793
    I (Max) : 6A
    RON(Max) : 5m ohm
    V drop : 0.03 V (=0.91%)

    +3VALW TO +3VS

    ci r 2

    l
    2

    I (Max) : 3.5A

    ia
    RON(Max) : 33m ohm
    V drop : 0.1155 V(=2.31%)

    +5VALW TO +5VS Vinafix.com


    +3VALW

    n t
    e
    PIR23 SI: Add CC411~CC425
    +1.8V_PRIM +1.8VS_AUDIO
    U7

    id
    1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
    1 14 CC411 CC412 CC413 CC414 CC415 CC416 CC417 CC418 CC419 CC420 CC421 CC422 CC423 CC424 CC425
    2 VIN1 VOUT1 13 RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@
    VIN1 VOUT1

    f
    +5VALW 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

    12P_0201_50V8J

    68P_0201_50V8J

    68P_0201_50V8J

    0.1U_0201_6.3V6K

    12P_0201_50V8J

    0.1U_0201_6.3V6K

    68P_0201_50V8J

    0.1U_0201_6.3V6K

    68P_0201_50V8J

    0.1U_0201_6.3V6K

    12P_0201_50V8J

    68P_0201_50V8J

    12P_0201_50V8J

    0.1U_0201_6.3V6K

    12P_0201_50V8J
    AUDIO_PW REN_R 3 12 C5238 1 2 470P_0201_50V7K
    ON1 CT1
    4 11
    VBIAS GND

    n
    +3VALW 5 10 C5239 1 2 470P_0201_50V7K +3VS_AUDIO
    ON2 CT2
    6 9

    co
    7 VIN2 VOUT2 8
    3 VIN2 VOUT2 3
    15 1 1
    GPAD
    0.1U_0201_6.3V6K
    C5240

    0.1U_0201_6.3V6K
    C5241

    EM5209VF_DFN14_3X2
    2 2

    For +1.8V_PRIM Discharge

    SUSP# RC495 1 2 0_0201_5%

    A L AUDIO_PW REN_R
    +5VALW +1.8V_PRIM

    1
    AUDIO_PW REN RC496 1 @ 2 0_0201_5% R52 R53
    (8) AUDIO_PW REN 22_0402_5%
    100K_0201_1%

    P
    1
    100K_0201_5%

    1 @
    0.1U_0201_6.3V6K
    C5234

    R5795

    2
    PCH_PW R_EN#
    2
    2

    1
    S1
    (12,29,45,46,48) PCH_PW R_EN 2
    G1
    D1 6

    O
    4
    S2
    5
    G2
    D2

    DMN63D8LV-7_SOT563-6

    3
    4 4

    C
    Q5

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2017/03/20 Deciphered Date 2020/03/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DC Interface
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F803P
    Date: Friday, June 08, 2018 Sheet 39 of 55
    A B C D E
    5 4 3 2 1

    +20V_VIN
    +20V_VIN PQ18 PQ19
    PQ16 PQ17 AON7409_DFN8-5 AON7409_DFN8-5
    AON7409_DFN8-5 AON7409_DFN8-5 1 1
    1 1 2 2
    2 2 3 5 5 3
    +TBTB_VBUS_L

    0.1U_0402_25V7K
    3 5 5 3
    +TBTA_VBUS_L

    0.1U_0402_25V7K

    3
    499K_0402_1%

    4
    ideal_1

    6
    499K_0402_1%
    D D

    PC2
    5

    4
    ideal_1

    PC1

    PR5
    2

    2
    PR4
    PQ7B

    2
    PQ7A BSS84AKS_SOT363-6

    4
    BSS84AKS_SOT363-6

    2
    r
    1

    1
    1
    fo
    PR8
    PR1809 49.9K_0402_1%

    4
    49.9K_0402_1%

    2
    2
    t
    2 5
    2 5

    PQ6A

    i
    PQ5A

    u
    METR3906KW-G_SOT363-6 PQ5B

    3
    METR3906KW-G_SOT363-6 PQ6B METR3906KW-G_SOT363-6

    3
    6
    METR3906KW-G_SOT363-6

    c
    6

    3
    5

    r
    2 (35) TBTB_PPEXT_EN L2N7002DW1T1G_SC88-6
    L2N7002DW1T1G_SC88-6

    1
    (35) TBTA_PPEXT_EN PQ3B

    ci
    C C

    1
    PQ3A PR9 PR11

    4
    PR6 PR23 47K_0402_1% PR10 47K_0402_1%
    1

    47K_0402_1% PR7 47K_0402_1% 470K_0402_1%


    470K_0402_1%

    2
    2

    2
    +20V_VIN

    ia l
    +20V_VIN_TBTC

    t
    PQ4
    AON7409_DFN8-5

    n
    1
    2
    5 3

    e
    1

    PD1

    id
    BZT52-B5V1S_SOD323-2
    4
    1

    D
    2

    2 ideal_1

    f
    B G B
    S PQ1
    3

    470K_0402_1%

    LBSS84LT1G_SOT23-3

    n
    PR26

    +20V_VIN ADP_I (29,42)


    +3VL_EC

    co
    2
    1

    1
    PR1
    2 5 16.2K_0402_1% PR2

    1000P_0402_50V7K

    1000P_0402_50V7K
    82P_0402_50V8J

    1U_0402_25V6K

    1U_0402_25V6K
    5.9K_0402_1%

    PC14

    2
    1

    1
    EMI@ PC5

    EMI@ PC6

    EMI@ PC7

    EMI@ PC8
    L
    PQ2A
    VCIN0_PH (29)

    2
    METR3906KW-G_SOT363-6 PQ2B
    VCIN1_PH (29)

    1
    METR3906KW-G_SOT363-6
    6

    1
    RF@
    PH1

    A
    100K_0402_1%_NCP15WF104F03RC PR3
    10K_0402_1%

    2
    1

    ECAGND(29)

    2
    PR12 PR14
    47K_0402_1% PR13 47K_0402_1%
    470K_0402_1%
    A A
    2

    O M Security Classification
    Issued Date 2018/2/2
    Compal Secret Data
    Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    2022/2/2 Title
    Compal Electronics, Inc.
    DC Conn
    Document Number
    LA-F801P
    Rev
    0.1

    C
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, June 08, 2018 Sheet 40 of 53
    5 4 3 2 1
    5 4 3 2 1

    +8.4V_BATT++ +8.4V_BATT+

    @ PJP1
    JUMP_43X79
    1 2
    1 2

    1
    EMI@ PC9 EMI@ PC10
    @ 1000P_0402_50V7K 1000P_0402_50V7K

    100P_0201_50V8J
    2.2U_0402_25V6M
    PJPB1

    2
    1

    1
    CVILU_CF4236DH0R2-05-NH

    PC15

    RF@ PC16
    D D

    H
    38
    GND 37

    2
    GND 36

    RF@
    36 35

    r
    35 34
    34 33
    33 32

    fo
    32 31
    31 30
    30 29
    29 28
    28 27
    27 26

    t
    26 25

    i
    25 24
    24 23 PR15 100_0402_5%
    23 22 1 2
    EC_SMB_CK1 (29,42)

    u
    22 21
    21 20 EC_SMB_CK1_R PR16 100_0402_5%
    20 19 EC_SMB_DA1_R 1 2

    c
    19 18 EC_SMB_DA1 (29,42)
    18 17

    r
    17 16 +3V_LID_R PR17
    16 15 0_0201_5% +3V_LID +3V_LID +8.4VB

    ci
    15 14 1 2
    14 13
    13 12 PR18 PR19
    12 11

    1
    100_0402_5% 100K_0201_5%

    3.9K_0603_5%

    3.9K_0603_5%
    C 11 10 B/I#_R 1 2 1 2 C
    10 9 +3VL PR20

    PR21

    PR22
    l
    9 8 200K_0201_5%
    8 7
    B/I# (29,42)

    2
    7 6

    ia
    6 5
    5 4

    6
    4 3
    3 2

    t
    2 1 2
    1 L2N7002DW 1T1G_SC88-6
    PQ10A

    1
    3
    id e +3VL
    5
    L2N7002DW 1T1G_SC88-6
    PQ10B

    4
    n f
    B

    c o B

    A L
    P
    A

    O M A

    C Security Classification
    Issued Date 2018/2/2
    Compal Secret Data
    Deciphered Date 2022/2/2
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Title

    Size
    Compal Electronics, Inc.

    Document Number
    BATT Conn

    LA-F801P
    Rev
    0.1
    Date: Friday, June 08, 2018 Sheet 41 of 53
    5 4 3 2 1
    A B C D

    ★ can not stuff 10V rated MLCC


    ★
    +8.4VB +8.4VB +8.4VB +8.4VB +8.4VB +20V_VIN +20V_VIN

    RF@ PCB40 @RF@ PCB44 @RF@ PCB48 @RF@ PCB52 @RF@ PCB56 @RF@ PCB60 @RF@ PCB64
    0.1U_0201_25V6K 0.22U_0201_10V6K 0.22U_0201_10V6K 0.22U_0201_10V6K 0.22U_0201_10V6K 0.22U_0201_10V6K 0.22U_0201_10V6K
    1 2 1 2 1 2 1 2 1 2 1 2 1 2

    P
    +20V_CHG RF@ PCB41 RF@ PCB45 RF@ PCB49 RF@ PCB53 RF@ PCB57 RF@ PCB61 RF@ PCB65
    68P_0201_25V8 68P_0201_25V8 68P_0201_25V8 68P_0201_25V8 68P_0201_25V8 68P_0201_25V8 68P_0201_25V8
    PRB1 1 2 1 2 1 2 1 2 1 2 1 2 1 2
    1 0.02_1206_1% 1

    RF@ PCB42 @RF@ PCB46 @RF@ PCB50 @RF@ PCB54 @RF@ PCB58 @RF@ PCB62 @RF@ PCB66

    H
    1 4

    1CSIN_CHG_R
    1CSIP_CHG_R
    2.2P_0201_25V8C 0.22U_0201_10V6K 0.22U_0201_10V6K 0.22U_0201_10V6K 0.22U_0201_10V6K 0.22U_0201_10V6K 0.22U_0201_10V6K
    +20V_VIN 1 2 1 2 1 2 1 2 1 2 1 2 1 2
    2 3
    @RF@ PCB43 RF@ PCB47 RF@ PCB51 RF@ PCB55 RF@ PCB59 RF@ PCB63 RF@ PCB67

    2200P_0402_25V7K

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M
    r
    2.2U_0201_10V6K 68P_0201_25V8 68P_0201_25V8 68P_0201_25V8 68P_0201_25V8 68P_0201_25V8 68P_0201_25V8

    100P_0402_50V8J
    2.2U_0402_25V6M
    0.1U_0402_25V6
    1 2 1 2 1 2 1 2 1 2 1 2 1 2

    0.1U_0402_25V6

    1
    EMI@ PCB2

    EMI@ PCB3

    PCB4

    PCB5

    PCB6

    PCB7

    RF@ PCB36

    RF@ PCB37
    1
    PRB2 PRB3 +8.4VB @RF@ PCB68

    PCB1
    fo
    2.2_0201_1% 2.2_0201_1% +8.4VB 0.22U_0201_10V6K

    2
    1 2

    2
    @ PCB8

    2
    4.7U_0603_25V6K RF@ PCB69
    1 2 1 2 68P_0201_25V8
    1 2 1 2
    @RF@ PCB70 @RF@ PCB75

    t
    1U_0402_25V6K
    82P_0201_50V8J 82P_0201_50V8J

    1U_0402_25V6K
    1
    1 2 1 2

    i
    PCB9

    PCB10
    @RF@ PCB71 @RF@ PCB74 +8.4VB

    2
    2200P_0201_50V7K 2200P_0201_50V7K

    2
    u
    1 2
    1

    PCB11
    PRB4 @RF@ PCB73 10U_0603_25V6M

    ri c
    1

    2_1206_5% BST1_CHG_R 82P_0201_50V8J 1 2


    PRB5
    432K_0402_1% 1 2 PCB13
    2

    10U_0603_25V6M
    @RF@ PCB72 1 2

    0.22U_0603_25V7K
    2

    2200P_0201_50V7K

    2.2_0603_5%
    1

    1
    ACIN_CHG

    PCB12
    PCB14

    PRB6
    10U_0603_25V6M
    1 2

    c
    2
    RF@PRB31 PCB15
    0.1U_0402_25V6

    2
    2 2
    0_0402_5% 10U_0603_25V6M
    1

    UG1_CHG 1 2 UG1_CHG_R 1 2

    l
    1
    PCB16

    PRB7 PCB17 RF@PRB33

    ADP_CHG

    CSIP_CHG

    CSIN_CHG

    BST1_CHG

    UG1_CHG

    LX1_CHG

    LG1_CHG
    120K_0201_1% 1U_0603_25V6K RF@PRB32 0_0402_5%
    2

    0_0402_5% UG2_CHG 1 2 UG2_CHG_R


    2

    it a
    PCB18 1U_0603_25V6K LG1_CHG 1 2 LG1_CHG_R
    2

    PRB8 RF@PRB34
    1 2 4.7_0402_5% 0_0402_5%
    PDB1 1 2 VDD_CHG LG2_CHG 1 2 LG2_CHG_R
    BAT54CW_SOT323-3

    16

    15

    14

    13

    12

    11

    10

    33
    9
    2 PRB9
    +20V_VIN 2_1206_5%

    BOOT1

    UGATE1

    PHASE1

    LGATE1
    CSIN

    PAD
    ADP

    CSIP

    ASGATE
    1 DCIN_CHG_R 1 2 PCB19 PQB1 PQB2
    5V PQB13

    9
    1U_0402_6.3V6K FDPC8013S FDPC8013S
    +8.4V_BATT

    n
    3 DCIN_CHG 17 8 VDDP_CHG 1 2 8 1 UG1_CHG_R PLB1 UG2_CHG_R
    1 8 PRB10 AON7401_DFN8-5

    V+

    V+
    +8.4VB DCIN VDDP V+ HSG 2.2UH_CMLE041B-2R2MS-70_3.3A_20% HSG V+ 0.005_1206_1% 1 +8.4V_BATT+
    VDD_CHG 18 7 LG2_CHG PRB13 LG1_CHG_R
    7 2 1 2 2 7LG2_CHG_R 2
    VDD LGATE2 LSG SW SW LSG

    e
    2.2_0603_5% 1 4 3 5
    PRB11 ACIN_CHG 19 PUB1 6 LX2_CHG 1 2 6 3 LX1_CHG PLB2 LX2_CHG 3 6
    100K_0201_5% ACIN ISL9538HRTZ-T_TQFN32_4X4 PHASE2 GND SW 2.2UH_CMLE041B-2R2MS-70_3.3A_20% SW GND 2 3

    BST2_CHG_R

    GND

    GND
    1

    1 2 CMIN_CHG 20 5 UG2_CHG 5 4 1 2 4 5
    +3VL

    4
    CMIN UGATE2 GND SW SW GND

    if d
    PCB20 PCB21
    1 2 SDA_CHG 21 4 BST2_CHG 1 2

    10U_0603_25V6M

    10U_0603_25V6M
    4.7_1206_5%

    4.7_1206_5%
    1U_0402_6.3V6K
    2

    10

    10
    (29,41) EC_SMB_DA1 SDA BOOT2

    RF@ PRB17
    PRB12 0_0201_5%

    CSON_CHG_R
    CSOP_CHG_R
    SCL_CHG VSYS_CHG

    PRB16
    1 2 22 3 0.22U_0603_25V7K
    (29,41) EC_SMB_CK1 SCL VSYS

    1
    PCB22

    PCB24
    PRB14 0_0201_5%

    100P_0402_50V8J
    2.2U_0402_25V6M
    1
    1 2 PROCHOT#_CHG 23 2 CSOP_CHG
    PROCHOT# CSOP

    1
    AMON/BMON

    (29) PROCHOT#

    RF@ PCB39

    RF@ PCB38
    PRB15 0_0201_5% PCB23

    1SNUB_CHG1 2

    1SNUB_CHG2 2

    2
    VDD_CHG 1 2 24 1 CSON_CHG
    BATGONE

    RF@
    4700P_0402_50V7K

    2
    PRB18 100K_0201_1% PRB19 ACOK CSON PRB20
    CMOUT

    BGATE_CHG
    BGATE

    2
    COMP

    +8.4VB
    PROG

    n
    PSYS

    VBAT
    200K_0201_5% 0_0201_5%
    1 2 1 2
    (29) VCIN1_ACOK

    680P_0402_50V7K

    680P_0402_50V7K
    @ PRB21
    25

    26

    27

    28

    29

    30

    31

    32

    o
    1 2

    PCB27

    PCB26
    PRB23 100K_0201_1% 1 2
    CMOUT_CHG

    100K_0201_1%
    BGATE_CHG
    VBAT1_CHG
    COMP_CHG

    AMON_CHG

    2
    PROG_CHG

    3
    (29,41) B/I# 1 2 BATGONE_CHG @ PCB25 0.1U_0402_25V6 3

    RF@

    RF@
    PCB28 10P_0402_50V8J
    1 2

    PRB24
    1 2
    +3VL PRB22

    L
    100K_0201_5% 71.5K_0201_1% 1 2
    1 2
    @ PCB29 1U_0402_25V6K

    PRB26

    A
    1 2
    499_0201_1%
    1

    1_0201_1%
    1
    PRB27

    560P_0402_50V7K

    PCB30

    P
    1U_0603_25V6K PRB28
    2
    1
    PCB31

    1_0201_1%
    2

    1 2
    0.01U_0402_25V7K

    2
    1

    1
    PCB32

    @
    PRB29 1 2
    1K_0201_1%
    2

    M
    PCB33 0.22U_0402_25V6K
    2

    0.1U_0402_25V6
    1
    PCB34

    O
    2

    PRB30
    1 2 +8.4V_BATT+

    C
    4 4

    (29,40) ADP_I 100_0201_1%


    1

    @ PCB35
    0.1U_0402_25V6
    2

    Close to EC ADP_I pin

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2018/2/2 Deciphered Date 2022/2/2 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    CHARGER
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F801P
    Date: Sheet 42 of 53
    A B C D
    A B C D E

    1 +8.4VB
    @ PJ301
    PU301
    SY8286BRAC_QFN20_3X3 PR313
    0_0402_5%
    PC302
    0.1U_0201_10V6K

    H P 1

    2200P_0402_50V7K
    1 2 +8.4VB_3V BST_3V 1 2 BST_3V_R 1 2
    1 2

    82P_0402_50V8J

    0.1U 25V K X5R 0402


    r

    10U_0603_25V6M
    PC301

    RF@ PC332

    EMI@ PC303
    JUMP_43X79

    1
    68P_0201_25V8

    PC304
    0.1U_0402_25V6
    PL301

    BS
    IN

    IN

    IN

    IN
    fo
    2.2UH_CMLE041B-2R2MS-70_3.3A_20%

    2
    1

    1
    LX_3V6 LX_3V

    @RF@ PC340

    RF@ PC341
    20 1 2
    LX LX +3VALWP

    RF@
    7 19

    2
    GND LX

    100P_0402_50V8J
    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    2.2U_0402_25V6M

    12P_0201_50V8J
    4.7_1206_5%
    1

    1
    PR302

    RF@ PC343
    RF@
    8 18
    +3VALW GND GND

    1
    t

    PC305

    PC306

    PC307

    PC308

    RF@ PC310

    RF@ PC311
    9 17
    +3VLP

    2
    PG LDO

    2
    1
    10 16 @

    3V_SN2
    NC NC

    1
    PC309

    OUT
    EN2

    EN1
    21

    NC
    u
    4.7U_0402_6.3V6M

    FF

    2
    GND

    680P_0603_50V7K
    PR301
    100K_0201_5%

    11

    12

    13

    14

    15

    1
    c
    2

    PC328
    RF@
    3.3V LDO 150mA~300mA

    2
    r
    (9) PWR_3V5V_PG
    ENLDO_3V5V PC329 PR303

    ci
    1000P_0402_25V8J 1K_0201_1%
    5V_3V_EN 3V_FB 1 2 3V_FB_1 1 2
    (26) 5V_3V_EN
    @ PJ302
    1 2
    2 +3VALWP 1 2 +3VALW 2
    JUMP_43X118

    ia l +3VLP
    @ PJ303
    JUMP_43X39
    1
    1 2
    2
    +3VL

    +8.4VB
    1
    @ PJ304
    1 2
    2 +8.4VB_5V BST_5V

    0_0402_5%
    1
    PR312
    2 BST_5V_R 1
    PC312
    0.1U_0201_10V6K
    2

    n t
    e
    JUMP_43X79
    68P_0201_25V8
    0.1U_0402_25V6

    13 PU302
    1

    SY8270CTMC_QFN13_4X3

    teknisi indonesia
    1

    1
    @RF@ PC338

    RF@ PC339

    PL302
    BS
    IN

    id
    1UH_PCMB041B-1R0MS_4.2A_20%
    2200P_0402_50V7K

    0.1U_0402_25V6

    1 2
    2

    10U_0603_25V6M

    10U_0603_25V6M

    LX_5V 2 12 LX_5V
    LX LX PL303 +5VALWP
    1

    f
    EMI@ PC315

    @EMI@ PC316

    1UH_PCMB041B-1R0MS_4.2A_20%

    2.2U_0402_25V6M

    100P_0402_50V8J

    12P_0201_50V8J
    PC313

    PC314

    3 11 1 2
    GND GND

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    RF@ PC330

    RF@ PC331

    RF@ PC342
    PC317
    2

    1
    n
    1 SPOK_5V

    VCC_5V

    PC318

    PC319

    PC320

    PC321

    PC322

    PC323

    PC336

    PC333

    PC334
    4 10 1 2
    PG VCC

    3.3_0603_1%

    2
    1
    PR314
    RF@
    OUT

    LDO
    EN2

    EN1

    2.2U_0402_6.3V6M

    co
    FF

    3 PR307 3
    5

    0_0201_5%

    5V_SN2
    PR304
    499K_0201_1%
    2

    1 2 ENLDO_3V5V PWR_3V5V_PG

    1000P_0201_50V7K
    +8.4VB +5VL
    1

    ENLDO_3V5V

    1
    4.7U_0402_6.3V6M

    RF@
    PR306

    L PC337
    1

    PC325

    499K_0201_1%

    2
    5V_3V_EN
    2

    @ PJ305
    1 2

    A
    +5VALWP 1 2 +5VALW
    JUMP_43X118
    PC326 PR310

    P
    1000P_0402_25V8J 1K_0201_1%
    5V_FB 1 2 5V_FB_1 1 2
    PR308
    2.2K_0201_5%
    1 2
    (29,31) EC_ON PR309
    @

    M
    1 2
    (29) MAINPWON
    0_0201_5%

    O
    5V_3V_EN
    1M_0201_1%

    4.7U_0402_6.3V6M
    1

    1
    PR311

    PC327

    4 4

    C
    2
    2

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2018/2/2 Deciphered Date 2022/2/2 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    3VALW/5VALW
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, June 08, 2018 Sheet 43 of 53
    A B C D E
    5 4 3 2 1

    P
    @ PRM1
    100K_0201_1%

    D
    +8.4VB @ PJPM1
    1 2
    +3VALW D

    H
    JUMP_43X79
    +8.4VB_DDR PUM1
    1 2
    1 2

    10U_0603_25V6M
    68P_0201_25V8

    RF@ PCM22
    0.1U_0402_25V6
    RF@ RF@

    0.1U_0402_25V6
    RF@PCM3

    2.2U_0402_25V6M
    RF@PCM4

    68P_0201_25V8
    10 19

    r
    IN OT
    1

    1
    PCM1
    @RF@ PCM24

    RF@ PCM25
    +3VALW PRM2 PCM5
    13 18 3.3_0603_1% 1000P_0201_50V7K
    BYP PG PRM3 PCM6 1 2 1 2

    fo
    2

    2
    14
    VCC BS
    12 0_0402_5% 0.1U_0603_50V7K
    2 1 1 2 PLM1
    +1.2V_VDDQP
    4 11 LX_DDR 0.56UH_CMLE041B-R56MS-70_6A_20%
    VTTGND LX

    1
    2.2U_0402_6.3V6M
    1 2

    PCM8
    PCM7 9 16 FB_DDR
    PGND FB

    330P_0402_50V7K

    RF@ 12P_0201_50V8J
    1U_0402_6.3V6K

    1
    71.5K_0201_1%

    EMI@

    EMI@
    15 8 +1.2V_VDDQP

    i
    SGND VDDQSNS

    PCM10

    PRM4
    PCM9
    +3VALW

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    2200P_0402_50V7K
    7 22U_0603_6.3V6M
    VLDOIN

    100P_0402_50V8J
    1 2

    2
    u

    1
    PCM11

    PCM12

    PCM13

    PCM14

    PCM16

    PCM17
    ILMT_DDR 17 6

    2
    ILMT VTT
    2

    @ PRM5 +0.6VSP

    PCM23
    1 5

    2
    S5 VTTSNS
    0_0201_5%
    2 3

    r
    S3 VTTREF

    1
    71.5K_0201_1%
    1

    22U_0603_6.3V6M

    PRM6
    ci

    1
    1U_0402_10V6K
    PCM18
    ILMT_DDR
    SY8210AQVC_QFN19_4X3

    PCM19
    2

    2
    2

    C PRM7 C
    0_0201_5%

    l
    1

    ia
    PRM8

    t
    0_0201_5%
    1 2
    (12,21,29) SYSON
    0.1U_0402_10V7K

    n
    1M_0201_5%
    1

    1
    PCM20
    PRM9

    e
    1

    @
    +1.2V_VDDQP +1.2V_VDDQ
    2
    @

    PRM12
    0_0201_5% @ PJM1
    2

    id
    JUMP_43X118
    1 2
    2

    PRM10 1 2
    0_0201_5%

    f
    (6) SM_PG_CTRL 1 2
    1

    n
    1M_0201_5%

    0.1U_0402_10V7K

    @ PRM13
    PRM11

    @ PCM21

    0_0201_5%
    2

    1 2

    o
    (12,29,39,47) SUSP#
    2

    B B

    L c
    P A
    A

    O M A

    C Security Classification
    Issued Date 2018/2/2
    Compal Secret Data
    Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    2022/2/2 Title

    Size
    Custom
    Document Number
    Compal Electronics, Inc.
    1.2V_VDDQ/0.6VS_VTT
    LA-F801P
    Rev
    0.1

    Date: Friday, June 08, 2018 Sheet 44 of 53


    5 4 3 2 1
    5 4 3 2 1

    H P D

    fo r
    +3VB_1.8V

    u i t
    c
    RF@ PC1809
    0.22U_0402_6.3V6K
    1 2

    r
    PC1801
    22U_0603_6.3V6M RF@ PC1810

    ci
    68P_0402_50V8J
    1 2 1 2

    RF@ PR1802 RF@ PC1806


    4.7_0603_5% 680P_0402_50V7K
    C 1 2 SNB_1.8V 1 2 C
    PU1801 +1.8V_PRIMP

    l
    @ PJ1801 4 5 PL1801
    JUMP_43X79 PGND NC 1UH_DFE201612R-H-1R0M-P2_2.6A_20%
    +3VALW 1 2 +3VB_1.8V 3 6 LX_1.8V 1 2

    ia
    1 2 IN LX

    68P_0402_50V8J

    12P_0201_50V8J
    2.2U_0402_25V6M
    1
    PG_1.8V 2 7 EN_1.8V

    RF@ PC1808

    RF@ PC1818
    100P_0402_50V8J
    PG EN

    1
    @ PR1801

    PC1802

    PC1803

    PC1804

    RF@ PC1807
    22U_0603_6.3V6M

    22U_0603_6.3V6M
    100K_0201_5% 1 8
    1 2 FB SGND 9 20K_0201_1%

    t
    +3VALW

    2
    PGND

    2
    PR1803
    FB_1.8V SY8003ADFC_DFN8_2X2

    1
    PR1806

    e
    PR1804 10K_0201_1%
    0_0201_5% @ PJ1802

    2
    1 2 JUMP_43X39
    (12,29,39,46,48) PCH_PWR_EN 1 2
    +1.8V_PRIM
    +1.8V_PRIMP 1 2

    1
    id
    1
    PR1805 @ PC1805
    0.1U_0201_6.3V6K
    1M_0201_1%

    2
    n f 2
    B

    c o B

    A L
    P
    O M
    C
    A A

    Security Classification Compal Secret Data


    Title
    Compal Electronics, Inc.
    Issued Date 2018/2/2 Deciphered Date 2022/2/2
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    1.8VALW
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, June 08, 2018 Sheet 45 of 53
    5 4 3 2 1
    5 4 3 2 1

    D D
    @ PJ1001
    1 2 VIN_+1.0V
    +8.4VB 1 2

    P
    68P_0201_25V8
    0.1U_0402_25V6
    JUMP_43X79

    0.1U_0402_25V6
    1

    1
    @RF@PC1013

    RF@ PC1014

    10U_0603_25V6M
    2200P_0402_50V7K
    1

    1
    EMI@ PC1001

    @EMI@ PC1003

    PC1004
    2

    2
    H
    2

    2
    PC1005 RF@ PR1002 RF@ PC1002

    r
    @ PR1001 PR1009
    0.1U_0603_25V7K 4.7_0805_5% 680P_0402_50V7K @ PJP10
    1 2 BST_+1.0V 1 2 BST_+1.0V_R 1 2 1 2 SNUB_1V 1 2 JUMP_43X118
    (12,29,39,45,48) PCH_PWR_EN
    1 2
    +1.0V_PRIMP 1 2 +1.0V_PRIM

    1
    0_0201_5% PR1005

    fo
    1M_0201_1% @ PC1012 0_0603_5%

    1
    0.1U_0201_6.3V6K
    C C
    PR1810

    7
    1 2 PU1001

    2
    (48) VCC_PRIM_PG

    BOOT
    VIN
    0_0201_5% 4
    EN PL1001 IOCP=5A(min), 6A(typ)

    t
    PR1003 10 LX_+1.0V 1 2
    5.1_0402_1% SW +1.0V_PRIMP

    i
    2 1 VBYP_+1.0V 2

    15K_0201_1%

    22P_0402_50V8J

    12P_0201_50V8J
    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    VBYP

    1
    9 0.47UH_MMD-04AB-R47M-V2_6A_20%

    PC1015
    +5VALW SW

    1
    high >1.35V

    PR1006

    PC1011

    PC1007

    PC1008

    PC1009
    1
    PC1006 RT6219CGQW_WDFN10_3X3

    u
    2.2U_0603_10V6K 8
    Rup

    2
    1 SW

    RF@
    2

    2
    PGOOD

    ri c
    5 FB_+1.0V
    FB

    PGND
    6
    VCC

    VFB=0.6V
    +1.0V_PRIMP_PG

    11
    Vout=0.6V*(1+Rup/Rdown)

    1
    B B
    1 2 =1.05V PR1007

    c
    PR1010 20K_0201_1%
    Rdown
    1

    10K_0201_1%
    1

    PR1004

    2
    10K_0201_1% PC1010

    l
    2.2U_0603_10V6K
    2
    2

    t i a
    n
    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.

    e
    Issued Date 2018/2/2 Deciphered Date 2022/2/2 Title
    PWR-+1VALW
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

    id
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. PWR-+1VALW
    Date: Friday, June 08, 2018 Sheet 46 of 53
    5 4 3 2 1

    n f
    c o
    A L
    P
    O M
    C
    5 4 3 2 1

    MODE=GND (VCCIO)
    MODE=Float (VCCPCH)
    +3VS MODE=100Kohm to GND (EDRAM/EOPIO)
    MODE=150Kohm to GND (Others)

    2
    @ PRI1
    100K_0201_1%

    1
    PRI4 PCI5
    D D
    2.2_0402_1% 0.1U_0402_25V6
    BST_+VCCIOP 1 2 BST_R_+VCCIOP 1 2
    (9,11,12,29,49) PM_SLP_S0#

    H
    PLI1
    IOCP=7A~8A(typ)

    9
    @ PJI1 PUI1
    JUMP_43X39 0.47UH_MMD-04AB-R47M-V2_6A_20%

    BST
    MODE
    LP#
    r
    +8.4VB 1
    1 2
    2 VIN_+VCCIOP 1
    VIN SW
    8 SW_VCCIOP 1 2
    +0.85VS_VCCIOP
    1 2 5 12 2 1

    68P_0201_25V8

    82P_0201_50V8J
    10U_0603_25V6M

    10U_0603_25V6M

    100P_0402_50V8J
    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    2.2U_0402_25V6M
    0.1U_0402_25V6
    EN VOUT

    @RF@ PCI12
    0.1U_0402_25V6
    fo
    SUSP# (12,29,39,44)
    PRI7

    1
    3 2 PRI10

    EMI@ PCI1

    PCI2

    PCI3

    PCI6

    PCI7

    PCI8
    @RF@ PCI13

    RF@ PCI14

    RF@ PCI10

    RF@ PCI11
    0.1U_0201_6.3V6K
    0_0201_5% C1 PGND 6.8_0402_5%

    1
    1M_0201_1%
    4 11

    PCI9
    2

    2
    C0 AGND

    3V3
    PG
    @

    PRI8

    2
    2
    @ NB681GD-Z_QFN13_2X3 PRI9

    20K_0201_1%
    2

    13

    10
    t
    0_0201_5%

    PRI2
    i

    1
    +3VALW

    1
    VCCIO_SENSE (12)

    1
    u
    PCI4 2 1
    VSSIO_SENSE (12)
    1U_0402_6.3V6K

    2
    PRI11

    ri c
    C 0_0201_5% C

    1
    @ PJP11
    PRI12 JUMP_43X39
    0_0201_5% 1 2
    +0.85VS_VCCIOP 1 2 +0.85VS_VCCIO

    2
    l c
    t i a
    B

    e n B

    n f id
    c o
    A

    A L A

    P Security Classification
    Issued Date 2018/2/2
    Compal Secret Data
    Deciphered Date 2022/2/2 Title
    PWR-+0.85VS_VCCIO
    Compal Electronics, Inc.

    M
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. PWR-+0.85VS_VCCIO
    Date: Friday, June 08, 2018 Sheet 47 of 53
    5 4 3 2 1

    C O
    5 4 3 2 1

    +3VS MODE=GND (VCCIO)

    P
    MODE=Float (VCCPCH)
    D D
    MODE=100Kohm to GND (EDRAM/EOPIO)
    MODE=150Kohm to GND (Others)

    2
    H
    PRH2
    100K_0201_1%

    2
    r

    1
    @ PRH14
    0_0201_5% PRH4 PCH7
    2.2_0402_1% 0.1U_0402_25V6
    BST_+VCCPRIMP 1 2 BST_R_+VCCPRIMP 1 2

    fo
    (11) PRIM_CORE_LPM

    1
    IOCP=7A~8A(typ)

    9
    PUH1 PLH1
    +8.4VB @ PJH1 0.47UH_MMD-04AB-R47M-V2_6A_20%

    BST
    MODE
    LP#
    1 2 VIN_+VCCPRIMP 1 8 SW_VCCPRIMP 1 2
    +VCCPRIMP_CORE

    t
    1 2 VIN SW
    5 12

    12P_0201_50V8J
    10U_0603_25V6M

    10U_0603_25V6M
    100P_0402_50V8J

    2200P_0402_50V7K

    100P_0402_50V8J
    2.2U_0402_25V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    2.2U_0402_25V6M
    0.1U_0201_25V6K
    JUMP_43X79 PCH8 0_0201_5% EN VOUT

    RF@ PCH17
    1

    1
    1 PRH8 2CORE_VID1_R 3 2
    RF@ PCH4

    RF@ PCH5

    @EMI@ PCH6

    PCH1

    PCH2

    PCH9

    PCH10

    PCH12

    RF@ PCH13

    RF@ PCH14
    (13) CORE_VID1 C1 PGND
    68P_0201_25V8
    0.1U_0402_25V6

    1 2CORE_VID0_R 4 11

    u
    (13) CORE_VID0
    2

    2
    C0 AGND
    1

    3V3
    EMI@

    PG
    @
    @RF@ PCH15

    RF@ PCH16

    PRH9
    0_0201_5% NB681GD-Z_QFN13_2X3

    c
    2

    13

    10
    C C
    PRH6

    r
    1 2
    +3VALW

    0.1U_0201_6.3V6K
    ci
    1
    (12,29,39,45,46) PCH_PWR_EN
    0_0201_5%

    1
    PRH7

    PCH23
    1M_0201_1% PCH3
    1U_0402_6.3V6K @ PJH2
    (46) VCC_PRIM_PG

    2
    @ JUMP_43X79
    2

    1 2
    +VCCPRIMP_CORE 1 2 +VCCPRIM_CORE

    2
    l
    PRH5
    100K_0201_1%

    ia
    1
    t
    +3VALW
    +3VALW
    100K_0201_1%

    n
    1

    e
    100K_0201_1%

    PRH11
    PRH10

    B B

    id
    @
    2

    @
    CORE_VID1_R

    CORE_VID0_R

    f
    100K_0201_1%
    PRH12

    100K_0201_1%
    1

    PRH13

    n
    @

    @
    2

    c o
    A

    A L A

    P Security Classification
    Issued Date 2018/2/2
    Compal Secret Data
    Deciphered Date 2022/2/2 Title
    PWR-+VCCPRIM
    Compal Electronics, Inc.

    M
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. PWR-+VCCPRIM
    Date: Friday, June 08, 2018 Sheet 48 of 53
    5 4 3 2 1

    C O
    5 4 3 2 1

    +3VALW
    VRA_VDD18
    +3VALW

    2
    0_0201_5%
    2

    2
    10K_0201_1%
    0_0201_5%

    PRZ2
    PRZ1

    PRZ3
    @

    1
    @

    1
    VRACPU_PE ADDRP VR_PWRGD

    0.1U_0402_10V6K
    D D

    2
    0_0201_5%

    0_0201_5%
    PCZ1

    PRZ4

    PRZ5
    H
    1

    +3VALW

    1
    Y@ PUZ1
    MP2949AGQKT-0024

    4.7_0201_5%
    2
    fo

    PRZ9
    VRA_VDD18
    (29) VR_ON
    PRZ6
    +8.4VB 0_0201_5%

    1
    PWM1 2 1

    1
    VRAGT_PWM1 (50)

    VRA_VDD33
    PRZ7

    2
    2M_0201_1%
    PRZ10
    0_0201_5%

    PRZ8
    0_0201_5%
    +3VALW PWM5 2 1

    t
    VRACPU_PWM1 (50)

    2
    PRZ54

    1
    i
    0_0201_5%

    0.01U_0402_50V7K

    1U_0402_6.3V6K
    2 1
    VRASA_PWM1 (50)
    +1.0V_VCCST

    1
    133K_0201_1%
    0.1U_0402_10V6K

    PCZ3
    PCZ4

    1
    PRZ11
    2.2U_0402_6.3V6K

    u
    2
    PCZ5

    PCZ2

    2
    VRACPU_STB (50) PRZ15

    2
    2

    2
    10K_0201_1%

    10K_0201_1%

    10K_0201_1%
    0_0201_5%

    1
    PRZ12

    PRZ13

    PRZ14
    CS1 2 1
    VRAGT_CS1 (50)

    c
    PRZ16
    1U_0402_6.3V6K

    @ @ @ 0_0201_5%

    1
    CS5 2 1

    r
    49

    47

    26

    44

    43

    42

    41

    40

    39

    38
    C C
    2

    2
    100_0201_1%

    47_0201_1%

    10K_0201_1%

    VRACPU_CS1 (50)
    1
    PCZ6

    PRZ17

    PRZ18

    PRZ19

    AGND

    VIN_SEN

    VDD18

    VDD33

    PWM1

    PWM2

    PWM3

    PWM4

    PWM5

    PWM6
    VRASA_CS1 (50)

    ci
    37
    EN 34
    @
    2

    PRZ20 35 STB
    1

    (9,11,12,29,47) PM_SLP_S0# 0_0201_5% SLP_S0# 5 PRZ21 1 2 1.5K_0201_1% CSUMA


    1 2 33 CS1
    (26,29) SMB_BS_CLK SCL_P 4
    1 2 32 CS2
    (26,29) SMB_BS_DATA @ PRZ22 SDA_P 3
    0_0201_5% 31 CS3
    (5,29) H_PROCHOT# VRHOT# 2

    l
    30 CS4
    (29) VR_PWRGD VRRDY 1 PRZ23 1 2 1.5K_0201_1% CSUMB
    PRZ24 2 1 49.9_0201_1% 27 CS5
    (14) SOC_SVID_CLK SCLK 48 PRZ25 1 2 1.5K_0201_1% VRASA_CSUMC

    ia
    29 CS6
    (14) SOC_SVID_ALERT#_R ALT# YR@ PUZ1 6 VRAGT_VDIFF 1 2
    PRZ26 2 1 10_0201_1% 28 VDIFFA 10K_0201_1% 0.1U_0201_6.3V6K
    (14) SOC_SVID_DAT SDIO MP2949AGQKT-0026-Z PRZ27 @ PRZ56 @ PCZ185 100_0201_1%
    ADDRP 25 7 VRAGT_VFB 3.65K_0402_1% 2 1 1 2 PRZ58
    CLOSE CPU SIDE
    ADDR_P VFBA

    t
    (Link SA0000AG630) PRZ28
    1 2
    2 1 46
    PSYS 8
    +VCC_GT VOSENA
    0_0201_5%
    2 1
    PRZ29 PRZ30 VRACPU_PE
    2 1 0_0201_5% 36 VOSENA VCCGT_SENSE (14)
    PE 9 VORTNA 2 1
    10K_0201_1%

    n
    PRZ32 1 2 61.9K_0201_1% VRACPU_IREF 24 VORTNA VSSGT_SENSE (14)

    1
    IREF 10 VRACPU_VDIFF 1 2 PRZ33
    CSUMA 18 VDIFFB 10K_0201_1% 0.1U_0201_6.3V6K PRZ59
    0_0201_5%
    CSSUMA @ PCZ186 100_0201_1%
    YR@ PRZ34 @ PRZ57

    e
    CSUMB 19 11 VRACPU_VFB 3.16K +-1% 0402 2 1 1 2 100_0201_1%
    CSSUMB VFBB

    2
    PRZ60
    VRASA_CSUMC 20 Y@ PRZ34 1 2 PRZ36
    CSSUMC 1/16W 3.65K +-1% 0402 +VCC_CORE 0_0201_5%
    PRZ35 1 2 154K_0201_1% VRAGT_IMON 21 12 VOSENB 2 1

    id
    IMONA VOSENB VCCSENSE (14)
    VRACPU_IMON 22 13 VORTNB 2 1

    VOSENC
    VORTNC
    B
    PCZ8 2 1 220P_0402_50V8J IMONB VORTNB VSSSENSE (14) B
    VDIFFC

    1
    VRASA_IMON
    TEMP

    VFBC
    23 PRZ37
    Y@ PRZ38 IMONC PRZ61 0_0201_5%
    1/20W 154K +-1% 0201 100_0201_1%

    f
    45

    14

    15

    17

    16
    YR@ PRZ38 1 2 133K +-1% 0201

    2
    100_0201_1%
    PRZ62
    1 2
    PCZ9 2 1 220P_0402_50V8J PRZ39 PRZ40 +VCC_SA

    n
    0_0201_5% 0_0201_5%
    1 2 VRASA_VOSEN 1 2
    (50) VRACPU_VTEMP VCCSA_SENSE (15)
    PRZ41 1 2 620K_0402_1% PRZ43
    49.9K_0201_1%
    1U_0402_6.3V6K

    0_0201_5%

    co
    1

    VRASA_VORTN 1 2
    PCZ10 2 1 47P_0402_50V8J VSSSA_SENSE (15)

    1
    1
    PCZ11

    PRZ42

    PRZ63
    100_0201_1%
    2

    2
    PRZ55
    1 2
    10K_0201_1%
    PRZ44
    1 1

    12.1K_0201_1%
    @ PCZ184

    L
    0.1U_0201_6.3V6K
    2

    P A A

    M
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2018/2/2 Deciphered Date 2022/2/2 Title
    PWR-CORE IC
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    PWR-CORE IC

    O
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, June 08, 2018 Sheet 49 of 53
    5 4 3 2 1

    C
    5 4 3 2 1

    +8.4VB_CPU
    @ PJZ01
    JUMP_43X79
    1 2
    1 2 +8.4VB

    @RF@ PCZ254

    68P_0201_25V8
    10U_0603_25V6M

    10U_0603_25V6M
    1U_0603_25V7K

    82P_0201_50V8J

    0.1U_0402_25V6
    1

    1
    Due to Z heihgt limitataion and Cost condition,

    PCZ13

    PCZ14

    PCZ15
    +3VALW

    @RF@PCZ265

    RF@ PCZ266
    use 47U_D3_16VM_R40M SGA0000AP00 x2 pcs.

    2
    1U_0402_6.3V6K
    D D

    H
    PUZ2

    1
    PCZ12
    14 1
    VCC VIN 8

    2
    VIN

    r
    RF@ PRZ46 RF@ PCZ16

    4.7_0603_5% 680P_0402_50V7K
    13 15 CORE_BST 1 2 1 2
    AGND BST

    fo
    1
    PCZ17 PLZ1
    2 1U_0402_16V6K 0.12UH TMPC0512HP-R12MG-Z03 12A

    2
    9 SW 3 CORE_LX 1 2
    (49) VRACPU_PWM1 PWM SW 4 +VCC_CORE
    PRZ47 11 SW
    (49) VRACPU_VTEMP VTEMP/FLT

    t
    0_0201_5%
    1 2 10 5 CPU_CORE
    (49) VRACPU_STB SYNC PGND 6 FSW = 800kHz

    i
    12 PGND 7
    (49) VRACPU_CS1 CS PGND

    MP86901-CGLT-Z_TQFN21_3X4

    +8.4VB_CPU

    r c u
    C

    ci C

    10U_0603_25V6M

    10U_0603_25V6M
    1U_0603_25V7K
    1

    1
    PCZ18

    PCZ19
    l
    PCZ20
    +3VALW

    2
    1U_0402_6.3V6K

    ia
    PUZ3
    1
    PCZ21

    14 1
    VCC VIN 8

    t
    2

    VIN RF@ PRZ49 RF@ PCZ22

    4.7_0603_5% 680P_0402_50V7K
    13 15 GT_BST 1 2 1 2

    n
    AGND BST
    1

    PCZ23 PLZ2

    e
    2 1U_0402_16V6K 0.12UH TMPC0412HP-R12MG-Z03 12A
    2

    9 SW 3 GT_LX 1 2
    (49) VRAGT_PWM1 PWM SW 4 +VCC_GT
    VRACPU_VTEMP PRZ50 11 SW
    VTEMP/FLT

    id
    0_0201_5%
    VRACPU_STB 1 2 10 5
    SYNC PGND 6
    12 PGND 7 GT_CORE
    (49) VRAGT_CS1 CS PGND
    FSW = 800kHz

    f
    MP86901-CGLT-Z_TQFN21_3X4

    o
    +8.4VB_CPU

    n B

    c
    1U_0603_25V7K

    10U_0603_25V6M
    1

    1
    PCZ24

    PCZ25

    +3VALW

    L
    2

    2
    1U_0402_6.3V6K

    PUZ4
    1

    A
    12 1
    PCZ26

    VCC VIN 6 RF@ PRZ52 RF@ PCZ27


    VIN
    2

    4.7_0603_5% 680P_0402_50V7K
    1 2 1 2

    P
    11 13 SA_BST
    AGND BST
    1

    PCZ28 PLZ3
    2 1U_0402_16V6K 0.47UH_MMD-04AB-R47M-V2_6A_20%
    2

    7 SW 3 SA_LX 1 2
    (49) VRASA_PWM1 PWM SW +VCC_SA

    M
    VRACPU_VTEMP PRZ53 9
    0_0201_5% VTEMP/FLT
    VRACPU_STB 1 2 8 4
    SYNC PGND
    10 5 SA_CORE
    (49) VRASA_CS1 CS PGND
    FSW = 800kHz

    O
    MP86901-AGQT-Z_TQFN13_3X3

    C
    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2018/2/2 Deciphered Date 2022/2/2 Title
    PWR-IA/GT/SA
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, June 08, 2018 Sheet 50 of 53
    5 4 3 2 1
    4
    3
    2
    1
    +VCC_CORE

    A
    A

    2 1 2 1

    2
    1
    2
    1

    PCZ217 PCZ95 YR@ PCZ69 PCZ29


    0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 47U 6.3V M X5R 0603 22U_0603_6.3V6M
    2 1 2 1

    2
    1
    2
    1

    PCZ218 PCZ96 PCZ72 PCZ30

    C
    0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 47U 6.3V M X5R 0603 22U_0603_6.3V6M
    2 1 2 1 2 1
    2
    1

    PCZ215 PCZ97 YR@ PCZ229 PCZ31


    0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 47U 6.3V M X5R 0603 47U 6.3V M X5R 0603
    2 1 2 1 2 1
    2
    1

    O
    PCZ221 PCZ98 YR@ PCZ231 PCZ32
    0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 47U 6.3V M X5R 0603 22U_0603_6.3V6M
    Near Package

    2 1 2 1
    2
    1

    PCZ219 PCZ99 YR@ PCZ34

    +VCC_SA
    0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 47U 6.3V M X5R 0603
    0.1U_0201*12 pcs

    Y@
    Y@
    Y@

    2 1 2 1
    2
    1

    2
    1
    PCZ216 PCZ100 YR@ PCZ35

    M
    PCZ258 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 47U 6.3V M X5R 0603
    PCZ34
    PCZ38
    PCZ35

    47U 6.3V M X5R 0603 2 1 2 1


    2
    1

    22U_0603_6.3V6M
    22U_0603_6.3V6M
    22U_0603_6.3V6M

    2
    1
    68p_0402*1+2200p_0402*1

    PCZ220 PCZ101 YR@ PCZ36


    PCZ259 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 47U 6.3V M X5R 0603
    22U_0603_6.3V6M 2 1 2 1

    P
    2
    1

    2
    1
    PCZ222 PCZ102 YR@ PCZ37
    Y@
    Y@
    Y@

    PCZ260 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 47U 6.3V M X5R 0603


    22U_0603_6.3V6M 2 1 2 1

    B
    B

    2
    1
    22U_0603 * 16 pcs+1U_0201*2 pcs

    2
    1
    1U_0201_6.3V6M PCZ103 YR@ PCZ38
    PCZ51
    PCZ37
    PCZ69

    PCZ261 YR@ PCZ242 0.1U_0201_6.3V6K 47U 6.3V M X5R 0603

    A
    22U_0603_6.3V6M
    22U_0603_6.3V6M
    22U_0603_6.3V6M

    22U_0603_6.3V6M 2 1 2 1
    2
    1

    68p_0402*1+2200p_0402*1

    2
    1
    1U_0201_6.3V6M PCZ104 PCZ50
    PCZ262 YR@ PCZ243 0.1U_0201_6.3V6K 22U_0603_6.3V6M
    22U_0603_6.3V6M 2 1 2 1
    2
    1

    L
    Y@
    Y@
    Y@

    2
    1
    1U_0201_6.3V6M PCZ105 YR@ PCZ51
    PCZ263 YR@ PCZ244 0.1U_0201_6.3V6K 47U 6.3V M X5R 0603
    22U_0603_6.3V6M 2 1 2 1
    2
    1

    2 1
    PCZ36

    1U_0201_6.3V6M PCZ106 PCZ52


    PCZ231
    PCZ229

    22U_0603_6.3V6M
    22U_0603_6.3V6M
    22U_0603_6.3V6M

    1U_0201_6.3V6M YR@ PCZ245 0.1U_0201_6.3V6K 47U 6.3V M X5R 0603

    22U_0603 * 7 pcs + 1U_0201 * 1 pcs


    PCZ156 2 1 2 1

    c
    Place on secondary side, underneath the package

    2 1
    1U_0201_6.3V6M @RF@ PCZ134
    RF@ PCZ157 YR@ PCZ246 68P_0201_50V8J
    68P_0201_50V8J 2 1 2 1
    2 1

    o
    1U_0201_6.3V6M @RF@ PCZ135
    RF@ PCZ158 YR@ PCZ247 2200P_0201_50V7K
    0.047U_0201_10V6K 2 1 2 1
    2 1
    1U_0201_6.3V6M
    RF@ PCZ207
    68P_0201_50V8J
    2

    RF@ PCZ208
    1

    0.047U_0201_10V6K
    n f YR@ PCZ248
    2 1

    1U_0201_6.3V6M
    YR@ PCZ249
    2 1
    @RF@ PCZ192
    68P_0201_50V8J
    2

    @RF@ PCZ191
    1

    2200P_0201_50V7K
    2 1

    Issued Date
    2 1 1U_0201_6.3V6M @RF@ PCZ194

    C
    C

    YR@ PCZ250 68P_0201_50V8J


    RF@ PCZ209 2 1

    Security Classification
    68P_0201_50V8J 2 1
    id
    2 1 1U_0201_6.3V6M @RF@ PCZ193
    YR@ PCZ251 2200P_0201_50V7K
    RF@ PCZ210 2 1
    0.047U_0201_10V6K 2 1
    e
    2 1 1U_0201_6.3V6M @RF@ PCZ196
    YR@ PCZ252 68P_0201_50V8J
    RF@ PCZ211 2 1 2 1
    68P_0201_50V8J
    2 1 1U_0201_6.3V6M @RF@ PCZ195
    n

    YR@ PCZ253 2200P_0201_50V7K


    RF@ PCZ212
    2 1

    2018/2/2
    0.047U_0201_10V6K
    t

    2 1 @RF@ PCZ198
    RF@ PCZ213 68P_0201_50V8J
    68P_0201_50V8J 2 1
    +VCC_GT

    2 1
    @RF@ PCZ197
    RF@ PCZ214 2200P_0201_50V7K
    ia

    0.047U_0201_10V6K
    2 1
    l

    RF@ PCZ264
    12P_0201_50V8J

    2 1

    Compal Secret Data


    near package

    2 1 2 1

    Deciphered Date
    @RF@ PCZ67
    2
    1

    68P_0201_50V8J
    1U_0201_6.3V6M PCZ82 2 1 PCZ39
    PCZ223 0.1U_0201_6.3V6K 47U 6.3V M X5R 0603
    2 1 2 1
    ci

    @RF@ PCZ68
    2
    1

    D
    D

    2200P_0201_50V7K
    22U_0603 * 16 pcss
    0.1U_0201 * 20 pcs

    PCZ83 2 1 PCZ40
    1U_0201_6.3V6M
    0.1U_0201_6.3V6K 47U 6.3V M X5R 0603
    PCZ224
    r

    2 1 @RF@PCZ199
    2
    1

    2
    1

    68P_0201_50V8J
    PCZ41
    68p_0402*1+2200p_0402*1

    PCZ232 PCZ86 2 1
    47U 6.3V M X5R 0603
    2022/2/2

    47U 6.3V M X5R 0603 0.1U_0201_6.3V6K


    c

    2 1 @RF@PCZ200
    2
    1
    2
    1

    2200P_0201_50V7K
    PCZ234 PCZ88 2 1 PCZ46
    47U 6.3V M X5R 0603 0.1U_0201_6.3V6K 47U 6.3V M X5R 0603
    2 1 @RF@PCZ201
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    u
    2
    1
    2
    1

    68P_0201_50V8J
    PCZ235 PCZ89 2 1 PCZ48
    47U 6.3V M X5R 0603 0.1U_0201_6.3V6K 47U 6.3V M X5R 0603
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    i

    2 1 2 1 @RF@PCZ202
    2
    1

    2200P_0201_50V7K
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

    @RF@ PCZ237 PCZ91 PCZ54


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    t

    Title

    Date:

    2 1
    82P_0201_50V8J 0.1U_0201_6.3V6K 47U 6.3V M X5R 0603
    2 1 2 1
    Custom

    @RF@PCZ203
    2
    1

    68P_0201_50V8J
    @

    @RF@PCZ236 PCZ108 PCZ255


    2 1
    2200P_0201_50V7K 0.1U_0201_6.3V6K 22U_0603_6.3V6M
    2 1 2 1 @RF@PCZ204
    2
    1

    2200P_0201_50V7K
    @

    @RF@ PCZ238 PCZ109 PCZ256


    2 1
    Size Document Number

    0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 22U_0603_6.3V6M


    2 1 2 1
    2
    1

    @RF@PCZ205
    Place on secondary side, underneath the package

    fo

    Friday, June 08, 2018

    68P_0201_50V8J
    @

    @RF@ PCZ239 PCZ110 PCZ257


    2 1
    PWR-CPU CAP

    82P_0201_50V8J 0.1U_0201_6.3V6K 22U_0603_6.3V6M


    2 1 2 1
    r

    @RF@PCZ206
    2200P_0201_50V7K
    PWR-CPU CAP

    @RF@PCZ240 PCZ111
    2200P_0201_50V7K 0.1U_0201_6.3V6K
    E
    E

    2 1 2 1

    @RF@ PCZ241 PCZ112


    Sheet

    0.1U_0201_6.3V6K 0.1U_0201_6.3V6K
    2 1
    H

    51

    PCZ114
    0.1U_0201_6.3V6K
    of
    Compal Electronics, Inc.
    P

    53
    Rev
    0.1
    4
    3
    2
    1
    5 4 3 2 1

    +8.4VB
    USB PD Power Switch

    P
    +3VALWP Jumper +3VALW
    SY8286B SY8032
    EC_ON
    EN +1.8VALWP Jumper +1.8V_PRIM
    Buck-Boost
    D Charger D

    H
    PCH_PWR_EN
    EN
    ISL9538

    r
    SY8288C +5VALWP Jumper +5VALW
    EC_ON
    EN

    Battery RBFET SYSON EN_VDDQ


    SY8210D +1.1V_VDDQP Jumper +1.1V_VDDQ

    i t fo
    u
    +0.6VSP Jumper +0.6VS_VTT
    SYSON EN_VTT

    r c
    C

    1.05V_PRIMCORE_PG
    SY8286
    +1.05V_PRIMPJumper +1.05V_PRIM

    l ci C

    ia
    EN

    NB681
    +1.5V_PRIM_COREP

    n t +1.5V_PRIM_CORE

    e
    Jumper

    +1.8V_PG

    id
    EN

    MP2940-0020

    n f +VCCIN
    B
    VR_ON

    c o EN
    B

    A L
    P
    A

    O M A

    C Security Classification
    Issued Date 2018/2/2
    Compal Secret Data
    Deciphered Date 2022/2/2
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Title

    Size
    Compal Electronics, Inc.
    Power Block Diagram
    Document Number
    LA-F801P
    Rev
    0.1
    Date: Friday, June 08, 2018 Sheet 52 of 53
    5 4 3 2 1
    5 4 3 2 1

    PV Version change list (P.I.R. List)


    Reson For
    Item Date Material Change Location Phase

    P
    S RES 1/16W 3.16K +-1% 0402 to PRZ34
    1 2018/05/30 S RES 1/16W 3.65K +-1% 0402 FAE recommend for KBL Y PV

    S RES 1/20W 133K +-1% 0201 to

    H
    D D
    2 2018/05/30 FAE recommend for KBL Y PRZ38 PV
    S RES 1/20W 154K +-1% 0201
    S RES 1/10W 4.7 +-5% 0603 to
    、 PV

    r
    3 2018/05/30 S RES 1/10W 3.3 +-1% 0603 RF MLCC shortage lead to change PRM2 PR314
    S CER CAP 680P 50V K X7R 0201 to

    fo
    4 2018/05/30 RF MLCC shortage lead to change PV
    S CER CAP 1000P 50V K X7R 0201 PC337,PCM5
    5 2018/05/30 S RES 1/20W 100K +-1% 0201to S PV
    RES 1/20W 71.5K +-1% 0201 shortage PRM4,PRM6

    t
    S CER CAP .1U 16V K X7R 0603 to
    6 2018/05/30 shortage

    i
    S CER CAP 0.1U 50V K X7R 0603 PCM6 PV
    7 S CER CAP 4700P 25V K X7R 0402 to
    2018/05/30 shortage PCB23 PV

    u
    S CER CAP 4700P 50V K X7R 0402
    8 2018/05/30 S CER CAP 12P 25V J NPO 0201 to PC342,PC343,PC1015,PC1818,PCH17,PCM23,PCZ264
    shortage PV

    c
    S CER CAP 12P 50V J NPO 0201
    S CER CAP 220P 25V K NPO 0402

    r
    9 2018/05/30 shortage PCZ8,PCZ9 PV
    to S CER CAP 220P 50V J NPO 0402

    ci
    10 2018/05/30 Delete S RES 1/20W 0 +-5% 0201 KBL_YRefresh PRI3 PV
    C C

    11 S CER CAP 2200P 50V K X7R 0201to S PCZ158,PCZ208,PCZ210,PCZ212,PCZ214 PV

    l
    2018/05/30 CER CAP 0.047U 10V K X5R 0201 shortage

    ia
    12 S CER CAP 82P 50V J NPO 0201 to PC339,PC341,PC1014,PCB41,PCB45,PCB47,PCB49,PCB51, PV
    2018/05/30 S CER CAP 68P 25V J NPO 0201 shortage PCB53,PCB55,PCB57,PCB59,PCB61,PCB63,PCB65,PCB67,
    PCB69,PCH16,PCI14,PCM22,PCM25,PCZ266
    13 2018/05/31
    S RES 1/20W 0 +-5% 0201 to
    S RES 1/20W 20K +-1% 0201 KBL_YRefresh

    n t PRI2 PV

    14

    15
    2018/05/31

    2018/06/04
    add S RES 1/16W 6.8 +-5%
    0402,S RES 1/20W 0 +-5% 0201
    S CER CAP 100P 50V J NPO 0402 to S
    CER CAP 100P 50V J NPO 0201

    id e
    local sense to remote sense

    connetor bigger
    PRI9,PRI10,PRI11,PRI12

    PC16
    PV

    PV

    16
    17
    2018/06/07 1U 6.3V K X5R 0402 to 1U 6.3V M X5R 0201

    n f shortage PCZ156,PCZ223,PCZ224 PV

    B 21

    22
    23
    c o B

    24
    25

    A L
    P
    26
    27
    28
    29

    30

    31
    O M
    C
    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2018/2/2 Deciphered Date 2022/2/2 Title

    FAE recomment for IMON


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PIR
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F801P
    Date: Friday, June 08, 2018 Sheet 53 of 53
    5 4 3 2 1
    5 4 3 2 1

    Version Change List ( P. I. R. List ) Page 1


    Request
    Item Page# Title Date Owner Issue Description Solution Description Rev.

    D
    1

    2
    10

    29,35,36
    PM_BATLOW# Add 10K PU

    PM_BATLOW# Add 10K PU


    18/3/16

    18/3/16
    HW

    HW
    Add RC580 10Kohm PU to +3VALW_DSW

    Add type-C additional features

    H P 0.2

    0.2
    D

    r
    3 31 change R38 From 560 to 1.91K 18/3/22 HW change R30 From SD034130180 to SD00000R580 0.2

    fo
    4 30 change R30 From 1.3K to 1.8K 18/3/22 HW change R38 From SD028560080 to SD000009O80 0.2

    5 25 WWAN Pcie change EQ setting 18/3/22 HW un-pop RW6,RW18 & pop RW7,RW19 0.2

    t
    6 21 change CD122,CD248,CD249 18/3/22 HW change from SE000006E00 to SE00000TH00 0.2

    i
    from 6.3V to 10V

    7 13 change LC3 & L24 PN 18/3/22 HW change from SM01000HC00 to SM01000NY00 0.2

    10
    12,18

    29

    11
    change CC117 & C5245 PN

    EC swaps pin for KB backlight

    For Port 3 USB2.0 function


    18/3/23

    18/3/28

    18/4/3
    HW

    HW

    HW
    change from SE000000K80 to SE00000QL10

    KBL_ON# change to M9
    MUTE_LED_OUT change to M2
    TS_INT#_EC change to N9

    pop RH125

    ri c u 0.2

    0.2

    0.2

    C 11

    12
    29

    29
    For KB mute LED function

    HW Design change
    18/4/3

    18/4/3
    HW

    HW
    un-pop RK64

    remove RK18

    l c 0.2

    0.2
    C

    13

    14
    28

    26
    RF

    ESD
    request

    request
    18/4/10

    18/4/10
    RF

    ESD
    remove CA98,CA99

    remove D6

    t i a 0.2

    n
    15 27 ESD request 18/4/10 ESD remove DA10,DA11

    e
    16 28 ESD request 18/4/10 ESD remove DA6,DA9

    id
    17 28 HW Design change 18/4/11 HW pop RA48

    f
    18 18 RF request 18/4/16 RF Add CC400~CC404

    n
    19 18 RF request 18/4/16 RF pop more Cap

    20 13 RF request 18/4/16 RF remove CA98,CA99

    B
    21

    22
    14

    31
    HW Design change

    RF request
    18/4/16

    18/4/16
    HW

    RF

    c o
    un-pop RC147,RC148

    Add CC405~CC410
    B

    L
    23 39 RF request 18/4/18 RF Add CC411~CC425

    24 7 Change UC2 to 16M 18/4/18 HW Change from SA00005I950 to SA00007XA10

    25

    26

    27
    33

    11

    38
    Change RT12 size

    HW Design change

    Intel request

    P A
    18/4/19

    18/4/19

    18/4/19
    HW

    HW

    HW
    Change from (0402) SD000011980 to (0201) SD000024G00

    pop UH3 , un-pop RC579

    By USB3.1 Type-C USB-IF ECN

    A
    28

    29

    30
    36

    39

    39
    Intel request

    RF

    RF
    request

    request

    O M 18/4/19

    18/4/19

    18/4/19
    HW

    RF

    RF
    By USB3.1 Type-C USB-IF ECN

    pop CH47

    pop CC387,CC388
    A

    31 29

    C
    Change board ID 18/4/20 HW change from15K to 27K

    Security Classification
    Issued Date 2017/3/20
    Compal Secret Data
    Deciphered Date 2020/3/20

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Title

    Size
    Compal Electronics, Inc.

    Document Number
    Custom
    LA-F803P
    HW PIR
    Rev
    0.1

    Date: Friday, June 08, 2018 Sheet 54 of 55


    5 4 3 2 1
    5 4 3 2 1

    Version Change List ( P. I. R. List ) Page 1


    Request
    Item Page# Title Date Owner Issue Description Solution Description Rev.

    D
    1 NA NA 17'_1019 HW

    H P 0.
    D

    fo r
    u i t
    r c
    C

    l ci C

    n t ia
    id e
    n f
    B

    c o B

    A L
    P
    A

    O M A

    C Security Classification
    Issued Date 2017/3/20
    Compal Secret Data
    Deciphered Date 2020/3/20

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Title

    Size
    Compal Electronics, Inc.

    Document Number
    Custom
    LA-F803P
    HW PIR
    Rev
    0.1

    Date: Friday, June 08, 2018 Sheet 55 of 55


    5 4 3 2 1

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