Compal La-J801p Fh5li PDF

A B C D E
1 1
Compal Confidential
FH5LI MB Schematic Document
2 2
3
LA-J801P 3
Rev:1.0
2019.10.30
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/11/23 Deciphered Date 2018/09/01 Title
Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom FH5LI M/B LA-H801P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, October 30, 2019 Sheet 1 of 102
A B C D E
A B C D E
HDMI Conn. eDP Interleaved Memory
DDR4-ON BOARD 4G 8Gbx16
page 24
page 40 page 38 Memory BUS
1
DDI2 Dual Channel 1
HDMI x 4 lanes
260pin DDR4-SO-DIMM X1
eDP 1.2V DDR4 2666/3200
DDI page 23
Intel Ice Lake U USB 3.0 USB 2.0 CMOS

conn x1 conn x2
USB2 port3 (MB) Camera
USB3 port 1
USB2 port 1 USB2 port4(SUB) USB2 port 7
Processor
Card Reader
page 68
RTS5140
SATA Gen 3 PCIE 3.0 x4 Reserved
2 6.0 Gb/s 8GT/s Flexible IO 2
(SATA2) Port 13-16

page 72 page 71 page 38 USB2 port 8(SUB)
SATA Gen 3 SATA Gen 1
Ice Lake PCH-LP USBx8 48MHz
NGFF PCIe 1.0 PCIe 1.0 6.0 Gb/s 1.5. Gb/s Finger
WLAN 2.5GT/s 2.5GT/s port 0 port 1 Printer
support CNVi port 10 port 9 (SATA0) (SATA1A) HD Audio 3.3V 24MHz USB2 port 5
USB2 port 10 page 52 50x25 mm Touch
LAN(GbE) SATA HDD SATA ODD 15W Screen
Realtek 8111H Conn. Conn. 1526pin BGA HDA Codec
ICL-U 4+2 USB2 port 6
page 51
page 06~19 SPI ALC255page 56 page 38
RJ45 conn. eSPI BUS

3
SPI ROM 3
page 67 CLK=24MHz 128Mb page 9
ENE
KB9052 Int. Speaker Int. DMIC UAJ
page 58
on Camera
page 56 page 38 page 56
RTC CKT. Fan Control
page 77 Touch Pad
page 11
PS2 (from EC) / I2C (from SOC)
Int.KBD USB2 port 8 (FP)
Power On/Off CKT. Sub Board

page 63
LS-H781P
page 63 page 63
IO/B
page 73
4 DC/DC Interface CKT. 4
page 78
LS-H783P
LID/B Security Classification Compal Secret Data Compal Electronics, Inc.
Power Circuit DC/DC
Vinafix.com page 63
Block Diagrams
page 81~100 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH5LI M/B LA-H801P
Date: Tuesday, October 15, 2019 Sheet 2 of 102
A B C D E
A B C D E
Board ID Table for AD channel

Vcc 3.3V +/- 5%
Ra 100K +/- 1% Power State
Board ID Rb V BID min V BID typ V BID max EC AD3 PCB Revision SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
0 0 0 V 0 V 0.300 V 0x00 - 0x13 0.1(EVT)
1 12K +/- 1% 0.347 V 0.345 V 0.360 V 0x14 - 0x1E 1.0(PVT) S0 (Full ON) HIGH HIGH HIGH ON ON ON ON
2 15K +/- 1% 0.423 V 0.430 V 0.438 V 0x1F - 0x25 1.0(MP) S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
1
3 20K +/- 1% 0.541 V 0.550 V 0.559 V 0x26 - 0x30 1
4 27K +/- 1% 0.691 V 0.702 V 0.713 V 0x31 - 0x3A S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
5 33K +/- 1% 0.807 V 0.819 V 0.831 V 0x3B - 0x45 S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
6 43K +/- 1% 0.978 V 0.992 V 1.006 V 0x46 - 0x54
7 56K +/- 1% 1.169 V 1.185 V 1.200 V 0x55 - 0x64
Voltage Rails
Power Plane Description S0 S3 S4/S5
+19V_VIN Adapter power supply N/A N/A N/A
+12.6V_BATT Battery power supply N/A N/A N/A
BOM Structure Table
+19VB AC or battery power rail for power circuit. N/A N/A N/A
+VCCIN Core voltage for CPU ON OFF OFF
BOM Option Table
+VCCIN_AUX CPU and PCH merged auxiliary power rail ON OFF OFF
Item BOM Structure
+0.6VS_VTT DDR +0.6VS power rail for DDR terminator . ON OFF OFF
Unpop @ +1.05VO_OUT_FET FIVR output of PCH to platform 1.05V Power Gates ON ON OFF
Connector CONN@ +1.05V_VCCST Sustain voltage for CPU standby modes ON ON OFF
G Sensor GSEN@ +1.05VS_VCCSTG Gated sustain voltage for CPU standby modes ON OFF/ON OFF
CODEC 255@/256@ +1.2V_VDDQ DDR4 +1.2V Power Rail ON ON OFF
2 For over 3 cell battery 3S@ +1.2V_VCCPLL_OC 1.2V power rail for CPU digital PLL ON ON OFF
2
For Intel CMC CMC@ +1.8VALW_PRIM +1.8V Always power rail ON ON ON*1
CNVi CNVI@ +1.8VS System +1.8V power rail ON OFF OFF
EMI/ESD requirement EMC@ / XEMC@ +3VLP +19VB to +3VLP power rail for suspend power ON ON ON
BOM select 15@ +3VALW System +3VALW always on power rail ON ON ON*1
RF requirement @RF@ +3VALW_PRIM +3VALW power for PCH suspend rails ON ON ON*1
TPM TPM@ +3VS System +3V power rail ON OFF OFF
Finger Print FP@/FPEMC@
+5VALW +5V Always power rail ON ON ON
Finger print power FP3V@/FP5V@ +5VS System +5V power rail ON OFF OFF
SATA/ODD select RD@/NRD@/ODD@ +RTCVCC RTC Battery Power ON ON ON
NOX76@/X76DSAM@/
MD BOM Select
X76DMIC@/X76DHYN@/
Memory related SPD@/DDP@/MEM@
MB Stage EVT@/DVT@/PVT@/MP@
Premium/Volume PREM@/VOL@
CPU i3@/i5@
3 3
DAZ PCB@
Note : ON*1 means power plane is ON only when WOL enable and RTC wake at BIOS setting, otherwise it is OFF.
ON*2 power plane is ON when DGPU turn on
43 level BOM table

43 Level Description BOM Structure
431ALBBOL01 SMT MB AJ801 FH5LI I31005D1 HDMI 255@/3S@/MEM@/15@/VOL@/CNVI@/CMC@/SDP@/MP@/FP@/FP3V@/i3@/NRD@/PCB@
431ALBBOL02 SMT MB AJ801 FH5LI I51035D1 HDMI 255@/3S@/MEM@/15@/VOL@/CNVI@/CMC@/SDP@/MP@/FP@/FP3V@/i5@/NRD@/PCB@
4 4

Vinafix.com Issued Date 2018/12/27 Deciphered Date 2019/12/27 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
A B C D E
A B C D E
JUMP VR_ON RT3612EBGQW

(PJZ1) (PUZ1) +VCCIN
JUMP 1.8VALW_PG RT6543AGQW

(PJG1) (PUG1) +VCCIN_AUX
VOL@
R-Short R-Short
(RC3970) (RX8) +TS_PWR
ADAPTER PREM@ AP2330W

1 SYSON (UY1) +HDMI_5V_OUT 1
JUMP EM5201V JUMP
+1.2VP (PJM3) +1.2V_VDDQ (UC11) +1.2V_VCCPLL_OC_P (JPC6) +1.2V_VCCPLL_OC
RT8207PGQW 0 ohm
SM_PG_CTRL (PUM1) (RO3) +5VS_HDD
JUMP
+0.6VSP (PJM4) +0.6VS_VTT
+19VB 0 ohm
BATTERY (RO26) +5VS_ODD
SY8288CRAC JUMP SUSP# AOZ1331DI JUMP JUMP

EC_ON +5VALWP +5VALW +5VS_OUT +5VS +VDDA
(PU501) (PJ501) (UQ1) (JPQ2) (JPA1)
USB_EN SY6288C20AAC JUMP R-Short
(US21) +USB3_VCCB (JPC10) +USB3_VCCA (RF1) +VCC_FAN1
CHARGER
(PU301) KBL_EN SY6288C20AAC
JLID1 (U1) +5VS_BL
(LID/B)
LDO JIO1
+3VLP (IO/B)
3V_EN SY8286BRAC SOC_ENVDD

(PU301) JUMP R-Short SY6288C20AAC
+3VALWP (PJ301) +3VALW (RC173) +3VALW_DSW (UX1) +LCDVDD
JUMP R-Short 0 ohm

(JPC7) +3VALW_PRIM (LC2) +3VALW_HDA (RK3)@ +3V_PTP
2 SYSON G9661MF11U R-Short 0 ohm 2
(PUM2) +2.5VP (RC154) +3VALW_SPI (RM9) +3VS_SSD_NGFF

LAN_PWR_EN SY6288C20AAC
(UL1) +3V_LAN
TP_PWR_EN SY6288C20AAC R-Short
(UK1) +3V_PTP (RW2)@ +3VS_TPM
WLAN_ON SY6288C20AAC R-Short
(UM1) +3VS_WLAN (RA2) +3VS_DVDDIO
R-Short
(RA5) +3VS_DVDD
FP_PWR_EN SY6288C20AAC JEDP1
(UK6)FP@ +FP_VCC (CAMERA)
R-Short JMIC1
(RW1) +3VALW_TPM (4DMIC)
SUSP# AOZ1331DI JUMP VOL@
(UQ2) +3VS_OUT (JPQ1) +3VS
R-Short
(RC407)
PREM@
EN_1.8VALW SY8032ABC JUMP EM5201V JUMP
(PU1801) +1.8VALWP (PJ1802) +1.8VALW_PRIM (UC12) +1.8V_PRIM_SOC_P (JPC5) +1.8V_PRIM_SOC
SUSP# G2898KD1U R-Short

(UC14) +1.8VS (RA6) +1.8VS_VDDA
3 3
PREM@
ICL-U FIVR VCCST_EN_LS
(UC1) +1.05VO_OUT_FET EM5201V 0Ohm
(BY2,CB2,CC1) (UC9) +1.05V_VCCST_SINGLE (RC3989) +1.05V_VCCST
0Ohm
(RC414)
VOL@ JUMP
(JPC16) +1.05V_VCCST_P
0Ohm
(RC413)
PREM@
VCCSTG_EN_LS G2898KD1U 0Ohm
(UC14) +1.05V_VCCST_DUAL (RC3981) +1.05VS_VCCSTG
4 4
HCB2012KF
(LX1) 3S@ +INVPWR_B+
Vinafix.com Security Classification

Issued Date 2018/12/27
Compal Secret Data
Deciphered Date 2019/12/27 Title
Compal Electronics, Inc.
Power Rail
A B C D E
5 4 3 2 1
D D
FH5LI_EVT Power Sequence AC mode

BIOS ver: V0.01T015
EC: ver: V0.01T08B
Plug in Power On S3 S3 Resume Power Off

+19VB
+19VB
+3VLP
+3VLP
EC_ON
EC_ON
→ 209.9us
+5VALW
+5VALW
→ 2.144ms
ON/OFFBTN#
★
ON/OFFBTN#
3V_EN
→ 98.52ms → 19.97us
3V_EN
+3VALW →567.3us → 683us +3VALW
SPOK_3V → 702.5us → 38.59us SPOK_3V
+1.8VALW_PRIM → 644.6us → 1.118ms
+1.8VALW_PRIM
1.8VALW_PG → 279.6us → 43.75us 1.8VALW_PG
C +VCCIN_AUX → 779.9us → 13.7ms +VCCIN_AUX C
VCC_AUX_PWRGD → 314.7us → 43.89us
VCCIN_AUX_CORE_VID → 2.383ms 814.3us → 811us
VCCST_OVERRIDE_LS
→ → 3.976us
VCCST_OVERRIDE_LS
EC_VCCST_EN → 4.565ms → 4.906ms EC_VCCST_EN
+1.05V_VCCST → 4.261ms → 4.223ms +1.05V_VCCST
★
EC_RSMRST# 31.4ms → → 9.59s EC_RSMRST#
(DSW_PWROK)
(DSW_PWROK)
→ 10.09ms → 10.99us AC_PRESENT
AC_PRESENT
PBTN_OUT# 11.52ms → 121.1ms → ←→ → 9.301us

20ms
PBTN_OUT#
→ 23.76ms
SLP_S4# SLP_S4#
→ 121.1us
SLP_S3#
SLP_S3#
SYSON → 6.44ms → 3.463us

SYSON
+1.2V_VDDQ
→ 515.9us → 1.006ms
+1.2V_VDDQ
+2.5V_VPP → 1.25ms → 922.5us

+2.5V_VPP
→ 28.04ms → 7.833us → 25.83ms → 9.894us

SUSP# SUSP#
+5VS → 1.56ms → 2.588ms → 1.563ms → 2.163ms
+5VS
→ 1.18ms → 8.698ms → 1.170ms → 402.6us
+3VS
+3VS
→ 741us → 600.9us → 763.3us → 923us
+1.8VS +1.8VS
B
SM_PG_CTRL → 20.21ms → 4.599us → 20.19ms → 4.841us B
SM_PG_CTRL
+0.6VS_VTT
→ 4.897us → 693.9us → 5.291us → 392.9us
+0.6VS_VTT
EC_VCCST_PG_R → 20.26ms → 4.772us → 20.16ms → 6.098us

EC_VCCST_PG_R
VR_ON
→ 20.28ms → 1.742us → 20.18ms → 2.198us VR_ON
→ 1.964ms → 32.3us → 1.966ms → 105.7us +VCCIN
+VCCIN
→ 9.98ms → 174.3us → 9.940ms → 147.6us
PCH_PWROK PCH_PWROK
SYSPWROK
→ 120.5ms → 182.2us → 120.9ms → 155.5us
SYSPWROK
→ 122ms → 319.3us → 124.7ms → 348.8us
PLT_RST# PLT_RST#
A A
Vinafix.com Security Classification

Issued Date 2019/07/12
Compal Secret Data
Deciphered Date 2019/12/31 Title
Power Sequence
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5 4 3 2 1
A B C D E
1 1
UC1A
Y5 BB5
<38> EDP_TXN0 DDIA_TXN_0 TCP0_TX_N0
Y3 BB6
<38> EDP_TXP0 DDIA_TXP_0 TCP0_TX_P0
Y1 AV6
<38> EDP_TXN1 DDIA_TXN_1 TCP0_TX_N1
Y2 AV5
<38> EDP_TXP1 DDIA_TXP_1 TCP0_TX_P1
V2 BH2
<38> EDP_TXN2 DDIA_TXN_2 TCP0_TXRX_N0
<eDP> <38> EDP_TXP2
V1
V3 DDIA_TXP_2 TCP0_TXRX_P0
BH1
BF1
PCB DAZ
<38> EDP_TXN3 DDIA_TXN_3 TCP0_TXRX_N1
V5 BF2 ZZZ
<38> EDP_TXP3 DDIA_TXP_3 TCP0_TXRX_P1
<38> EDP_AUXN W4 AY5

W3 DDIA_AUX_N TCP0_AUX_N AY6
<38> EDP_AUXP DDIA_AUX_P TCP0_AUX_P
AE3 DDI
<40> SOC_DP2_N0 DDIB_TXN_0
AE5 AR5
<40> SOC_DP2_P0 DDIB_TXP_0 TCP1_TX_N0 PCB@ DAZ2W V00100
AE2 AR6
<40> SOC_DP2_N1 DDIB_TXN_1 TCP1_TX_P0
AE1 AL5 PCB FH5LI LA-J801P LS-H781P/H783P
<40> SOC_DP2_P1 DDIB_TXP_1 TCP1_TX_N1
<HDMI> <40> SOC_DP2_N2
AC5
DDIB_TXN_2 TCP1_TX_P1
AL3
AC3 BD2
<40> SOC_DP2_P2 DDIB_TXP_2 TCP1_TXRX_N0
AC1 BD1
<40> SOC_DP2_N3 DDIB_TXN_3 TCP1_TXRX_P0
AC2 BB1
<40> SOC_DP2_P3 DDIB_TXP_3 TCP1_TXRX_N1 BB2
AD3 TCP1_TXRX_P1
AD4 DDIB_AUX_N AN3
DDIB_AUX_P TCP1_AUX_N
TCP1_AUX_P
AN5 Ice Lake-U CPU SKU
DP15
2 DJ17 GPP_E22/DDPA_CTRLCLK/PCIE_LNK_DOWN
GPP_E23/DDPA_CTRLDATA/BK4/SBK4
TBT / USB / DP i3-1005G1 i5-1035G1 2
BF6
DL40 TCP2_TX_N0 BF5
<40> SOC_DP2_CTRL_CLK GPP_H16/DDPB_CTRLCLK TCP2_TX_P0
HDMI DDC (Port 2) <40> SOC_DP2_CTRL_DATA
DP42
GPP_H17/DDPB_CTRLDATA TCP2_TX_N1
BJ5 UC1 UC1
BJ6
DL17 TCP2_TX_P1 BL1
1SOC_GPP_E19 DK17 GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD TCP2_TXRX_N0 BL2
T302 TP@ GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD TCP2_TXRX_P0 BM2
DN17 TCP2_TXRX_N1 BM1
1SOC_GPP_E21 DP17 GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD TCP2_TXRX_P1
GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD ICL-U_BGA1526 ICL-U_BGA1526
T509 TP@ BG6
TCP2_AUX_N S IC FJ8068904310007 SRGKF D1 1.2G FCBGA S IC FJ8068904368700 SRGKG D1 1G FCBGA
DK34 BG5
GPP_D9/ISH_SPI_CS_N/DDP3_CTRLCLK/GSPI2_CS0_N/TBT_LSX2_TXD TCP2_AUX_P SA0000CVQ30 SA0000CUQ20
1SOC_GPP_D10 DL34
GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/GSPI2_CLK/TBT_LSX2_RXD i3@ i5@
T510 TP@
DN33 BP6
1SOC_GPP_D12 DL33 GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/GSPI2_MISO/TBT_LSX3_TXD TCP3_TX_N0 BP5
T511 TP@ GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/GSPI2_MOSI/TBT_LSX3_RXD TCP3_TX_P0 BV5
DW11 TCP3_TX_N1 BV6
<38> CPU_EDP_HPD GPP_E14/DPPE_HPDA/DISP_MISCA TCP3_TX_P1
<40> SOC_DP2_HPD CV42 BR1
1SOC_GPP_A19 CV39 GPP_A18/DDSP_HPDB/DISP_MISCB TCP3_TXRX_N0 BR2
T512 TP@ 1SOC_GPP_A20 CY43 GPP_A19/DDSP_HPD1/DISP_MISC1 TCP3_TXRX_P0 BT2
T303 TP@ USB_OC1# CR41 GPP_A20/DDSP_HPD2/DISP_MISC2 TCP3_TXRX_N1 BT1
USB_OC2# CT41 GPP_A14/USB_OC1_N/DDSP_HPD3/DISP_MISC3 TCP3_TXRX_P1
1SOC_GPP_E17 DV14 GPP_A15/USB_OC2_N/DDSP_HPD4/DISP_MISC4 BT6
T306 TP@ GPP_E17 TCP3_AUX_N BT5
EDP_VDDEN: DN21 TCP3_AUX_P
100K PD on load swith side <38> SOC_ENVDD EDP_VDDEN TC_RCOMP_N
ENBKL DL19 AY1 RC351 1 2 150_0402_1%
<58> ENBKL EDP_BKLTEN TC_RCOMP_N TC_RCOMP_P
DU19 AY2
<38> SOC_BKL_PW M RSVD_1 EDP_BKLTCTL TC_RCOMP_P
J3
3 RSVD_1 CT38 3
+3VALW _PRIM 1DISP_UTILS D2 GPP_A17/DISP_MISCC CV43 TPM_PIRQ#
DISP_UTILS GPP_A21 TPM_PIRQ# <66>
T301 TP@ DISP_RCOMP R2 CV41 TS_EN
DISP_RCOMP GPP_A22 TS_EN <38,58>
1
RC164 1 2 10K_0402_5% USB_OC1# 1 0f 19

RC165 1 2 10K_0402_5% USB_OC2# RC350 ICL-U_BGA1526
150_0402_1% @
2
Reserve Test Point
GPP_E19
TBT LSX #0 PINS VCCIO CONFIGURATION RSVD_1:
NO INTERNAL PU/PD
Follow 573129_ICL_U_DDR4_SODIMM_HW_SCH_RN
HIGH: 3.3V
LOW: 1.8V RC348 1 2 100K_0402_5% RSVD_1
RC422 1 2 100K_0402_5% ENBKL

GPP_E21
TBT LSX #1 PINS VCCIO CONFIGURATION
INTERNAL PD 20K
HIGH: 3.3V
LOW: 1.8V
GPP_D10
4 TBT LSX #2 PINS VCCIO CONFIGURATION 4
NO INTERNAL PU/PD
HIGH: 3.3V
LOW: 1.8V
GPP_D12
TBT LSX #3 PINS VCCIO CONFIGURATION
NO INTERNAL PU/PD Issued Date 2019/04/12 Deciphered Date 2020/04/12 Title
HIGH: 3.3V Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICL-U(1/14)DDI,EDP
LOW: 1.8V AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
A B C D E
A B C D E
+3VS
1 @ 2 EC_SCI#_R
RC3984
10K_0402_5%
+1.05VS_VCCSTG_OUT_LGC check XDP /DCI
Reserve
1
RC6
< PU/PD for CMC Debug > +1.05VS_VCCSTG_OUT_LGC
1 1
1K_0402_5% UC1D
CATERR# J4 P3 SOC_XDP_TCK0 SOC_XDP_TMS RC13 1 CMC@ 2 51_0402_5%
2
H_PECI CD5 CATERR# PROC_TCK K5 SOC_XDP_TDI
<58> H_PECI PECI PROC_TDI
H_PROCHOT# 1 2 H_PROCHOT#_R C3 K3 SOC_XDP_TDO SOC_XDP_TDI RC14 1 CMC@ 2 51_0402_5%
<58,84> H_PROCHOT# PROCHOT# PROC_TDO
RC7 1 H_THERMTRIP# E3 P4 SOC_XDP_TMS
499_0402_1% CC1 THRMTRIP# PROC_TMS N1 SOC_XDP_TRST# SOC_XDP_TDO RC15 1 CMC@ 2 51_0402_5%
EMC@ PROC_POPIRCOMP CJ41 PROC_TRST#
100P_0201_50V8J PCH_OPIRCOMP DU3 PROC_POPIRCOMP N5 SOC_XDP_TRST# XDP_PREQ# RC17 1 @ 2 51_0402_5%
+3VALW _PRIM 2 A14 PCH_OPIRCOMP JTAG PCH_TRST# R5 PCH_JTAG_TCK1
B14 RSVD_25 PCH_TCK K1 SOC_XDP_TDI
RSVD_26 PCH_TDI K2 SOC_XDP_TDO CMC@
PCH_TDO
1
XDP_ITP_PMODE DL15 N3 SOC_XDP_TMS SOC_XDP_TCK0 RC20 1 2 51_0402_5%

RC371 DBG_PMODE PCH_TMS N2 SOC_XDP_TCK0
100K_0402_5% EC_SLP_S0IX# DV11 PCH_JTAGX
<58> EC_SLP_S0IX# GPP_E3/CPU_GP0
0_0402_5% 2 @ 1 RC3991 EC_SCI#_R DT11 P6 XDP_PRDY#
TP@ T497
<58> EC_SCI# GPP_E7/CPU_GP1 PROC_PRDY#
DC10 0_0402_5% 2 1 RC3963 TP_INT# CR38 M6 XDP_PREQ#
TP@ T2
<58,63> EC_TP_INT#
2
CR39 GPP_B3/CPU_GP2 PROC_PREQ#

1 2 H_PROCHOT# GPP_B4/CPU_GP3
<17> VCCIN_AUX_CORE_ALERT#_R
SOC_GPP_E6 DT12
RB751V-40_SOD323-2 SOC_GPP_H2 DJ38 GPP_E6 PCH_JTAG_TCK1 RC22 1 @ 2 51_0402_5%
SCS00000Z00 DL38 GPP_H2/CNV_BT_I2S_SDO
GPP_H19/TIME_SYNC0 4 of 19
+3VALW _PRIM ICL-U_BGA1526
@ SOC_XDP_TRST# RC21 1 @ 2 51_0402_5%
1 2 EC_SLP_S0IX#
2 RC3990 100K_0402_5% 2
+1.05V_VCCST
RC11 1 2 49.9_0402_1% CATERR#
RC12 1 2 1K_0402_5% H_THERMTRIP#
CC4 2 1 0.1U_0201_10V6K
EMC@
CC130 2 1 0.1U_0201_10V6K H_PECI
XEMC@
RC366 1 2 49.9_0402_1% PROC_POPIRCOMP

RC365 1 2 49.9_0402_1% PCH_OPIRCOMP
XDP_ITP_PMODE SOC_GPP_E6 GPP_H2

DFX TEST MODE JTAG ODT DISABLE MAF/SAF STRAP
INTERNAL PD 20K NO INTERNAL PU/PD +3VALW _PRIM INTERNAL PD 20K
HIGH: DFX TEST MODE DISABLED(DEFAULT) +3VALW _PRIM HIGH: JTAG ODT ENABLED HIGH: Slave Attached Flash Sharing (SAFS) is enabled.
LOW: DFX TES TMODE ENABLED LOW: JTAG ODT DISABLED LOW: Master Attached Flash Sharing (MAFS) is enabled.
3
(Default) 3
+1.05VO_OUT_FET
RC370 1 2 100K_0402_5% SOC_GPP_E6 RC389 1 @ 2 2.2K_0402_5% SOC_GPP_H2
RC18 1 CMC@ 2 1K_0402_5% XDP_ITP_PMODE RC3965 1 @ 2 100K_0402_5% RC3966 1 @ 2 2.2K_0402_5%
RC19 1 @ 2 1K_0402_5%
4 4

ICL-U(1/14)DDI,MSIC,XDP
A B C D E
5 4 3 2 1
Follow Intel DDR4 NIL
DDR4: Refer to 575034_ICL_U42_DDR4_T3_6L_Core_Schematics_Rev0p7
D D
UC1B
UC1C
<23> DDR_A_D[0..15] DDR_A_D0 LP4(NIL) / DDR4(NIL) LP4(NIL) / DDR4(NIL)
CA48 BL48 DDR_A_CLK#0 <23>
DDR_A_D1 DDRA_DQ0_0/DDR0_DQ0_0 DDRA_CLK_N/DDR0_CLK_N_0 <24> DDR_B_D[0..15] DDR_B_D0 LP4(NIL) / DDR4(NIL) LP4(NIL) / DDR4(NIL)
CA47 BL47 AK48 Y48
DDR_A_D2 DDRA_DQ0_1/DDR0_DQ0_1 DDRA_CLK_P/DDR0_CLK_P_0 DDR_A_CLK0 <23> DDR_B_D1 DDRC_DQ0_0/DDR1_DQ0_0 DDRC_CLK_N/DDR1_CLK_N_0 DDR_B_CLK#0 <24>
CA49 BF42 AK45 Y47
DDR_A_D3 DDRA_DQ0_2/DDR0_DQ0_2 DDRB_CLK_N/DDR0_CLK_N_1 DDR_A_CLK#1 <23> DDR_B_D2 DDRC_DQ0_1/DDR1_DQ0_1 DDRC_CLK_P/DDR1_CLK_P_0 DDR_B_CLK#1 DDR_B_CLK0 <24>
BV49 BF43 AK49 M43
DDR_A_D4 DDRA_DQ0_3/DDR0_DQ0_3 DDRB_CLK_P/DDR0_CLK_P_1 DDR_A_CLK1 <23> DDR_B_D3 DDRC_DQ0_2/DDR1_DQ0_2 DDRD_CLK_N/DDR1_CLK_N_1 DDR_B_CLK1 TP@ T3
CA45 AG47 M42
DDR_A_D5 DDRA_DQ0_4/DDR0_DQ0_4 DDR_B_D4 DDRC_DQ0_3/DDR1_DQ0_3 DDRD_CLK_P/DDR1_CLK_P_1 TP@ T4
BV47 BG49 DDR_A_CKE0 <23> AK47
DDR_A_D6 BV45 DDRA_DQ0_5/DDR0_DQ0_5 DDRA_CKE0/DDR0_CKE0 BJ47 DDR_B_D5 AG45 DDRC_DQ0_4/DDR1_DQ0_4 U45
DDR_A_D7 DDRA_DQ0_6/DDR0_DQ0_6 DDRA_CKE1/NC DDR_B_D6 DDRC_DQ0_5/DDR1_DQ0_5 DDRC_CKE0/DDR1_CKE0 DDR_B_CKE0 <24>
BV48 BF38 AG48 V46
DDR_A_D8 CC42 DDRA_DQ0_7/DDR0_DQ0_7 DDRB_CKE0/NC BF41 DDR_B_D7 AG49 DDRC_DQ0_6/DDR1_DQ0_6 DDRC_CKE1/NC M41
DDR_A_D9 DDRA_DQ1_0/DDR0_DQ1_0 DDRB_CKE1/DDR0_CKE1 DDR_A_CKE1 <23> DDR_B_D8 DDRC_DQ0_7/DDR1_DQ0_7 DDRD_CKE0/NC DDR_B_CKE1
CC39 AJ38 P43
DDR_A_D10 DDRA_DQ1_1/DDR0_DQ1_1 DDR_B_D9 DDRC_DQ1_0/DDR1_DQ1_0 DDRD_CKE1/DDR1_CKE1 TP@ T504
CC43 BM38 DDR_A_CS#0 <23> AL39
DDR_A_D11 CE38 DDRA_DQ1_2/DDR0_DQ1_2 DDRA_CS_0/DDR0_CS#0 BM42 DDR_B_D10 AJ39 DDRC_DQ1_1/DDR1_DQ1_1 V42
DDR_A_D12 DDRA_DQ1_3/DDR0_DQ1_3 DDRA_CS_1/NC DDR_B_D11 DDRC_DQ1_2/DDR1_DQ1_2 DDRC_CS_0/DDR1_CS#0 DDR_B_CS#0 <24>
CC38 BP42 AL43 V39
DDR_A_D13 CE39 DDRA_DQ1_4/DDR0_DQ1_4 DDRB_CS_0/NC BG42 DDR_B_D12 AL38 DDRC_DQ1_3/DDR1_DQ1_3 DDRC_CS_1/NC Y39
DDR_A_D14 DDRA_DQ1_5/DDR0_DQ1_5 DDRB_CS_1/DDR0_CS#1 DDR_A_CS#1 <23> DDR_B_D13 DDRC_DQ1_4/DDR1_DQ1_4 DDRD_CS_0/NC DDR_B_CS#1
CE42 AJ42 T39
DDR_A_D15 DDRA_DQ1_6/DDR0_DQ1_6 DDR_B_D14 DDRC_DQ1_5/DDR1_DQ1_5 DDRD_CS_1/DDR1_CS#1 TP@ T498
CE43 BM43 DDR_A_BA0 <23> AL42
<23> DDR_A_D[16..31] DDR_A_D16 DDRA_DQ1_7/DDR0_DQ1_7 DDRB_CA4/DDR0_BA0 DDR_B_D15 DDRC_DQ1_6/DDR1_DQ1_6
BT48 BG39 AJ43 T38
DDR_A_D17 DDRA_DQ2_0/DDR0_DQ2_0 NC/DDR0_BA1 DDR_A_BA1 <23> <24> DDR_B_D[16..31] DDR_B_D16 DDRC_DQ1_7/DDR1_DQ1_7 DDRD_CA4/DDR1_BA0 DDR_B_BA0 <24>
BT47 AB49 T42
DDR_A_D18 DDRA_DQ2_1/DDR0_DQ2_1 DDR_B_D17 DDRC_DQ2_0/DDR1_DQ2_0 NC/DDR1_BA1 DDR_B_BA1 <24>
BT49 BB49 DDR_A_BG0 <23>
AB48
DDR_A_D19 BN49 DDRA_DQ2_2/DDR0_DQ2_2 DDRA_CA5/DDR0_BG0 BD47 DDR_B_D18 AE49 DDRC_DQ2_1/DDR1_DQ2_1 R45
DDR_A_D20 DDRA_DQ2_3/DDR0_DQ2_3 NC/DDR0_BG1 DDR_A_BG1 <23> DDR_B_D19 DDRC_DQ2_2/DDR1_DQ2_2 DDRC_CA5/DDR1_BG0 DDR_B_BG0 <24>
BT45 AE47 N47 DDR_B_BG1 <24>
DDR_A_D21 BN47 DDRA_DQ2_4/DDR0_DQ2_4 BB48 DDR_B_D20 AE48 DDRC_DQ2_3/DDR1_DQ2_3 NC/DDR1_BG1
DDR_A_D22 DDRA_DQ2_5/DDR0_DQ2_5 NC/DDR0_MA0 DDR_A_MA0 <23> DDR_B_D21 DDRC_DQ2_4/DDR1_DQ2_4
BN45 BL49 DDR_A_MA1 <23>
AB47 P42 DDR_B_MA0 <24>
DDR_A_D23 BN48 DDRA_DQ2_6/DDR0_DQ2_6 NC/DDR0_MA1 BG38 DDR_B_D22 AB45 DDRC_DQ2_5/DDR1_DQ2_5 NC/DDR1_MA0 Y49
DDR_A_D24 DDRA_DQ2_7/DDR0_DQ2_7 DDRB_CA5/DDR0_MA2 DDR_A_MA2 <23> DDR_B_D23 DDRC_DQ2_6/DDR1_DQ2_6 NC/DDR1_MA1 DDR_B_MA1 <24>
BV42 BL45 AE45 U48
DDR_A_D25 DDRA_DQ3_0/DDR0_DQ3_0 NC/DDR0_MA3 DDR_A_MA3 <23> DDR_B_D24 DDRC_DQ2_7/DDR1_DQ2_7 DDRD_CA5/DDR1_MA2 DDR_B_MA2 <24>
BV39 BJ46 DDR_A_MA4 <23> AD38 Y45 DDR_B_MA3 <24>
DDR_A_D26 BV43 DDRA_DQ3_1/DDR0_DQ3_1 NC/DDR0_MA4 BG48 DDR_B_D25 AD39 DDRC_DQ3_0/DDR1_DQ3_0 NC/DDR1_MA3 U47
DDR_A_D27 DDRA_DQ3_2/DDR0_DQ3_2 DDRA_CA0/DDR0_MA5 DDR_A_MA5 <23> DDR_B_D26 DDRC_DQ3_1/DDR1_DQ3_1 NC/DDR1_MA4 DDR_B_MA4 <24>
BW38 BE45 AE39 R49
DDR_A_D28 DDRA_DQ3_3/DDR0_DQ3_3 DDRA_CA2/DDR0_MA6 DDR_A_MA6 <23> DDR_B_D27 DDRC_DQ3_2/DDR1_DQ3_2 DDRC_CA0/DDR1_MA5 DDR_B_MA5 <24>
BV38 BG45 AE43 U49
BW39 BG47 AE38 M47
BW42 BE47 DDR_A_MA9 <23> AD43 M45 DDR_B_MA8 <24>
DDR_A_D31 BW43 DDRA_DQ3_6/DDR0_DQ3_6 DDRA_CA1/DDR0_MA9 BJ38 DDR_B_D30 AD42 DDRC_DQ3_5/DDR1_DQ3_5 DDRC_CA3/DDR1_MA8 R47
<23> DDR_A_D[32..47] DDR_A_D32 DDRA_DQ3_7/DDR0_DQ3_7 NC/DDR0_MA10 DDR_A_MA10 <23> DDR_B_D31 DDRC_DQ3_6/DDR1_DQ3_6 DDRC_CA1/DDR1_MA9 DDR_B_MA9 <24>
AY48 BB47 AE42 P39
DDR_A_D33 DDRB_DQ0_0/DDR0_DQ4_0 NC/DDR0_MA11 DDR_A_MA11 <23> <24> DDR_B_D[32..47] DDR_B_D32 DDRC_DQ3_7/DDR1_DQ3_7 NC/DDR1_MA10 DDR_B_MA10 <24>
AY47 BE48 J48 N46
DDR_A_D34 DDRB_DQ0_1/DDR0_DQ4_1 NC/DDR0_MA12 DDR_A_MA12 <23> DDR_B_D33 DDRD_DQ0_0/DDR1_DQ4_0 NC/DDR1_MA11 DDR_B_MA11 <24>
AY49 BM39 J45 R48
DDR_A_D35 DDRB_DQ0_2/DDR0_DQ4_2 DDRB_CA0/DDR0_MA13 DDR_A_MA13 <23> DDR_B_D34 DDRD_DQ0_1/DDR1_DQ4_1 NC/DDR1_MA12 DDR_B_MA12 <24>
AU45 BG43 DDR_A_MA14 <23> J49 Y41 DDR_B_MA13 <24>
DDR_A_D36 AY45 DDRB_DQ0_3/DDR0_DQ4_3 DDRB_CA2/DDR0_MA14WE# BJ42 DDR_B_D35 G47 DDRD_DQ0_2/DDR1_DQ4_2 DDRD_CA0/DDR1_MA13 V41
C DDR_A_D37 DDRB_DQ0_4/DDR0_DQ4_4 DDRB_CA1/DDR0_MA15CAS# DDR_A_MA15 <23> DDR_B_D36 DDRD_DQ0_3/DDR1_DQ4_3 DDRD_CA2/DDR1_MA14WE# DDR_B_MA14 <24> C
AU47 BM41 J47 Y42
DDR_A_D38 DDRB_DQ0_5/DDR0_DQ4_5 DDRB_CA3/DDR0_MA16RAS# DDR_A_MA16 <23> DDR_B_D37 DDRD_DQ0_4/DDR1_DQ4_4 DDRD_CA1/DDR1_MA15CAS# DDR_B_MA15 <24>
AU48 G45 V47
DDR_A_D39 DDRB_DQ0_6/DDR0_DQ4_6 DDR_B_D38 DDRD_DQ0_5/DDR1_DQ4_5 DDRD_CA3/DDR1_MA16RAS# DDR_B_MA16 <24>
AU49 BJ39 G48
DDR_A_D40 DDRB_DQ0_7/DDR0_DQ4_7 NC/DDR0_ODT_0 DDR_A_ODT0 <23> DDR_B_D39 DDRD_DQ0_6/DDR1_DQ4_6
AY42 BB45 DDR_A_ODT1 <23> E48 V43 DDR_B_ODT0 <24>
DDR_A_D41 AY38 DDRB_DQ1_0/DDR0_DQ5_0 NC/DDR0_ODT_1 DDR_B_D40 J38 DDRD_DQ0_7/DDR1_DQ4_7 NC/DDR1_ODT_0 V38 DDR_B_ODT1
DDR_A_D42 DDRB_DQ1_1/DDR0_DQ5_1 DDR_B_D41 DDRD_DQ1_0/DDR1_DQ5_0 NC/DDR1_ODT_1 TP@ T500
AY43 BY47 G39
DDR_A_D43 DDRB_DQ1_2/DDR0_DQ5_2 DDRA_DQSN_0/DDR0_DQSN_0 DDR_A_DQS#0 <23> DDR_B_D42 DDRD_DQ1_1/DDR1_DQ5_1
BB39 BY46 DDR_A_DQS0 <23>
G38 AH46 DDR_B_DQS#0 <24>
DDR_A_D44 AY39 DDRB_DQ1_3/DDR0_DQ5_3 DDRA_DQSP_0/DDR0_DQSP_0 CC41 DDR_B_D43 G42 DDRD_DQ1_2/DDR1_DQ5_2 DDRC_DQSN_0/DDR1_DQSN_0 AH47
DDR_A_D45 DDRB_DQ1_4/DDR0_DQ5_4 DDRA_DQSN_1/DDR0_DQSN_1 DDR_A_DQS#1 <23> DDR_B_D44 DDRD_DQ1_3/DDR1_DQ5_3 DDRC_DQSP_0/DDR1_DQSP_0 DDR_B_DQS0 <24>
BB38 CE41 DDR_A_DQS1 <23> J39 AJ41 DDR_B_DQS#1 <24>
DDR_A_D46 BB42 DDRB_DQ1_5/DDR0_DQ5_5 DDRA_DQSP_1/DDR0_DQSP_1 BR47 DDR_B_D45 J42 DDRD_DQ1_4/DDR1_DQ5_4 DDRC_DQSN_1/DDR1_DQSN_1 AL41
DDR_A_D47 DDRB_DQ1_6/DDR0_DQ5_6 DDRA_DQSN_2/DDR0_DQSN_2 DDR_A_DQS#2 <23> DDR_B_D46 DDRD_DQ1_5/DDR1_DQ5_5 DDRC_DQSP_1/DDR1_DQSP_1 DDR_B_DQS1 <24>
BB43 BR46 DDR_A_DQS2 <23>
G43 AC47 DDR_B_DQS#2 <24>
<23> DDR_A_D[48..63] DDR_A_D48 DDRB_DQ1_7/DDR0_DQ5_7 DDRA_DQSP_2/DDR0_DQSP_2 DDR_B_D47 DDRD_DQ1_6/DDR1_DQ5_6 DDRC_DQSN_2/DDR1_DQSN_2
AR48 BV41 J43 AC46
DDR_A_D49 DDRB_DQ2_0/DDR0_DQ6_0 DDRA_DQSN_3/DDR0_DQSN_3 DDR_A_DQS#3 <23> <24> DDR_B_D[48..63] DDR_B_D48 DDRD_DQ1_7/DDR1_DQ5_7 DDRC_DQSP_2/DDR1_DQSP_2 DDR_B_DQS2 <24>
AR47 BW41 B43 AE41
DDR_A_D50 DDRB_DQ2_1/DDR0_DQ6_1 DDRA_DQSP_3/DDR0_DQSP_3 DDR_A_DQS3 <23> DDR_B_D49 DDRD_DQ2_0/DDR1_DQ6_0 DDRC_DQSN_3/DDR1_DQSN_3 DDR_B_DQS#3 <24>
AR49 AV46 DDR_A_DQS#4 <23> D43 AD41 DDR_B_DQS3 <24>
DDR_A_D51 AM45 DDRB_DQ2_2/DDR0_DQ6_2 DDRB_DQSN_0/DDR0_DQSN_4 AV47 DDR_B_D50 A43 DDRD_DQ2_1/DDR1_DQ6_1 DDRC_DQSP_3/DDR1_DQSP_3 H47
DDR_A_D52 DDRB_DQ2_3/DDR0_DQ6_3 DDRB_DQSP_0/DDR0_DQSP_4 DDR_A_DQS4 <23> DDR_B_D51 DDRD_DQ2_2/DDR1_DQ6_2 DDRD_DQSN_0/DDR1_DQSN_4 DDR_B_DQS#4 <24>
AR45 AY41 C40 H46
DDR_A_D53 DDRB_DQ2_4/DDR0_DQ6_4 DDRB_DQSN_1/DDR0_DQSN_5 DDR_A_DQS#5 <23> DDR_B_D52 DDRD_DQ2_3/DDR1_DQ6_3 DDRD_DQSP_0/DDR1_DQSP_4 DDR_B_DQS4 <24>
AM47 BB41 C43 G41
DDR_A_D54 DDRB_DQ2_5/DDR0_DQ6_5 DDRB_DQSP_1/DDR0_DQSP_5 DDR_A_DQS5 <23> DDR_B_D53 DDRD_DQ2_4/DDR1_DQ6_4 DDRD_DQSN_1/DDR1_DQSN_5 DDR_B_DQS#5 <24>
AM48 AN46 D40 J41
AM49 AN47 DDR_A_DQS6 <23> B40 C42 DDR_B_DQS#6 <24>
DDR_A_D56 AT42 DDRB_DQ2_7/DDR0_DQ6_7 DDRB_DQSP_2/DDR0_DQSP_6 AR41 DDR_B_D55 A40 DDRD_DQ2_6/DDR1_DQ6_6 DDRD_DQSN_2/DDR1_DQSN_6 D42
AT39 AT41 DDR_A_DQS7 <23>
B35 D36 DDR_B_DQS#7 <24>
DDR_A_D58 AR43 DDRB_DQ3_1/DDR0_DQ7_1 DDRB_DQSP_3/DDR0_DQSP_7 DDR_B_D57 D35 DDRD_DQ3_0/DDR1_DQ7_0 DDRD_DQSN_3/DDR1_DQSN_7 C36
DDR_A_D59 DDRB_DQ3_2/DDR0_DQ7_2 DDR_B_D58 DDRD_DQ3_1/DDR1_DQ7_1 DDRD_DQSP_3/DDR1_DQSP_7 DDR_B_DQS7 <24>
AT38 BF39 DDR_A_PAR <23>
A35
DDR_A_D60 AR38 DDRB_DQ3_3/DDR0_DQ7_3 NC/DDR0_PAR BE49 DDR_B_D59 D38 DDRD_DQ3_2/DDR1_DQ7_2 P38
DDR_A_D61 DDRB_DQ3_4/DDR0_DQ7_4 NC/DDR0_ACT# DDR_A_ACT# <23> DDR_B_D60 DDRD_DQ3_3/DDR1_DQ7_3 NC/DDR1_PAR DDR_B_PAR <24>
AR39 BD46 C35 M48 DDR_B_ACT# <24>
DDR_A_D62 DDRB_DQ3_5/DDR0_DQ7_5 NC/DDR0_ALERT# DDR_A_ALERT# <23> DDR_B_D61 DDRD_DQ3_4/DDR1_DQ7_4 NC/DDR1_ACT#
AR42 C38 M49
DDR_A_D63 DDRB_DQ3_6/DDR0_DQ7_6 DDR_B_D62 DDRD_DQ3_5/DDR1_DQ7_5 NC/DDR1_ALERT# DDR_B_ALERT# <24>
AT43 M38 1 TP@ T244
B38
DDRB_DQ3_7/DDR0_DQ7_7 RSVD_73 C44 DDR_B_D63 A38 DDRD_DQ3_6/DDR1_DQ7_6
SM_RCOMP0 DDR0_VREF_CA +0.6V_A_VREFCA DDRD_DQ3_7/DDR1_DQ7_7
100_0402_1% 2 1 RC25 D47 B45 +0.6V_B_VREFCA
Trace width/Spacing >= 20mils 3 of 19
100_0402_1% 2 1 RC26 SM_RCOMP1 E46 DDR_RCOMP_0 DDR1_VREF_CA M39 DDR_PG_CTRL ICL-U_BGA1526
100_0402_1% 2 1 RC27 SM_RCOMP2 C47 DDR_RCOMP_1 DDR_VTT_CTL DK47 DDR_DRAMRST#
DDR_RCOMP_2 DRAM_RESET# DDR_DRAMRST# <23,24> @
2 of 19
ICL-U_BGA1526
@
+1.2V_VDDQ
B B
1
RC30
470_0402_5%
Buffer with Open Drain Output
2
For VTT power control DDR_DRAMRST#
+1.2V_VDDQ
+3VS
1
CC6 2 1 0.1U_0201_10V6K CC9
1
100P_0402_50V8J
UC3 RC28 EMC@
1 5 100K_0402_5% 2
NC VCC
DDR_PG_CTRL 2
2
A 4
Y SM_PG_CTRL <86>
3
GND ESD
2
74AUP1G07GW_TSSOP5 SM_PG_CTRL to DDR

SA00005U600 RC16
@ 1M_0402_5% VTT supplied ramped
<35uS
(tCPU18) PDG & CKL no stuff
1
A A

2019/04/12 2020/04/12 Title
Vinafix.com
Issued Date Deciphered Date
ICL-U(3/14)DDR4
1.0
5 4 3 2 1
5 4 3 2 1
+3VALW _PRIM
+3VALW _PRIM
SOC_GPP_C2 RC86 1 2 4.7K_0402_5% SOC_SML0ALERT# RC3944 1 @ 2 4.7K_0402_5%

RC3969 1 @ 2 4.7K_0402_5% RC3945 1 @ 2 4.7K_0402_5%
GPP_C2 SOC_SML0ALERT#
TLS CONFIDENTIALITY ESPI OR EC LESS
INTERNAL PD 20K INTERNAL PD 20K
HIGH: TLS CONFIDENTIALITY ENABLE HIGH: ESPI DISABLE
LOW: TLS CONFIDENTIALITY DISABLE LOW: ESPI ENABLE (Default)
UC1E
D D
<66> SOC_SPI_0_CLK SOC_SPI_0_CLK DB42
SOC_SPI_0_SI DD43 SPI0_CLK DK27 SOC_SMBCLK
<66> SOC_SPI_0_SI
SOC_SPI_0_SO DF43 SPI0_MOSI GPP_C0/SMBCLK DP24 SOC_SMBDATA
SMB
<66> SOC_SPI_0_SO SPI0_MISO GPP_C1/SMBDATA
SOC_SPI_0_IO2 DF42 SMBUS DL24 SOC_GPP_C2 (Link to DDR& G sensor)
SPI ROM SOC_SPI_0_IO3 DD41 SPI0_IO2 SPI 0 GPP_C2/SMBALERT#
SOC_SPI_0_CS#0 DB43 SPI0_IO3
DF41 SPI0_CS0# DK24 SOC_SML0CLK
SOC_SPI_0_CS#2 DB41 SPI0_CS1# GPP_C3/SML0CLK DJ24 SOC_SML0DATA
TPM<- <66> SOC_SPI_0_CS#2 SPI0_CS2# SML 0 GPP_C4/SML0DATA DP22 SOC_SML0ALERT#
GPP_C5/SML0ALERT#
DV16
DT16 GPP_E11/SPI1_CLK/BK1/SBK1 DN22 EC_SMB_CK2
DU18 GPP_E13/SPI1_MOSI/BK3/SBK3 GPP_C6/SML1CLK/SUSWARN_N/SUSPWRDNACK DL22 EC_SMB_DA2
EC_SMB_CK2 <58> SML1
GPP_E12/SPI1_MISO/BK2/SBK2 SML1 GPP_C7/SML1DATA/SUSACK# EC_SMB_DA2 <58>
DT18 SPI 1 (Link to EC)
DW18 GPP_E1/SPI1_IO2
DW16 GPP_E2/SPI1_IO3 CR47 ESPI_CLK RC34 1 EMC@ 2 49.9_0402_1%
GPP_E10/SPI1_CS_N/BK0/SBK0 GPP_A5/ESPI_CLK ESPI_IO0 ESPI_CLK_R <58>
DU16 CN45 RC32 1 2 10_0402_1%
GPP_E8/SATALED#/SPI1_CS1# GPP_A0/ESPI_IO0 ESPI_IO1 ESPI_IO0_R <58>
CN48 RC33 1 2 10_0402_1%
GPP_A1/ESPI_IO1 ESPI_IO2 ESPI_IO1_R <58>
CN49 RC35 1 2 10_0402_1% To EC
GPP_A2/ESPI_IO2 ESPI_IO3 ESPI_IO2_R <58>
DV19 eSPI CN47 RC36 1 2 10_0402_1%
CL_CLK GPP_A3/ESPI_IO3 ESPI_CS# ESPI_IO3_R <58>
DW19 MLINK CT45
CL_DATA GPP_A4/ESPI_CS# ESPI_RST# ESPI_CS# <58>
DT19 CR46
+3VALW _PRIM CL_RST# GPP_A6/ESPI_RESET# ESPI_RST# <58>
ESPI
Follow
5 of 19
572907_ICL_UY_PDG
RC37 1 2 100K_0402_5% SOC_SPI_0_SI ICL-U_BGA1526
@
SOC_SPI_0_SI
C RC3968 1 @ 2 100K_0402_5% BOOT HALT C
NO INTERNAL PU/PD
HIGH: DISABLE
LOW: ENABLE
+3VALW _PRIM
RC38 1 2 100K_0402_5% SOC_SPI_0_IO2 +3VALW _PRIM

Follow CRB
RC3967 1 @ 2 100K_0402_5% SOC_SPI_0_IO2
CONSENT STRAP SOC_SMBCLK RC383 1 2 1K_0402_5%
NO INTERNAL PU/PD SOC_SMBDATA RC384 1 2 1K_0402_5%
HIGH: DISABLE SOC_SML0CLK
LOW: ENABLE RC316 1 2 499_0402_1%
SOC_SML0DATA RC315 1 2 499_0402_1%
EC_SMB_CK2 RC381 1 2 1K_0402_5%

EC_SMB_DA2 RC382 1 2 1K_0402_5%
+3VALW _PRIM
RC39 1 2 100K_0402_5% SOC_SPI_0_IO3
RC3943 1 @ 2 100K_0402_5%
SOC_SPI_0_IO3 +3VS
A0 PERSONALITY STRAP
NO INTERNAL PU/PD SOC_SMBCLK_1 RC3961 1 2 2.2K_0402_5%
B HIGH: DISABLE SOC_SMBDATA_1 B
LOW: ENABLE RC3962 1 2 2.2K_0402_5%
+3VS
75K_0402_5% 1 @ 2 RC443 ESPI_RST#
75K_0402_5% 1 @ 2 RC444 ESPI_CS#
100K_0402_5% 1 2 RC441 SOC_SPI_0_CLK
5
G
close to SPI ROM QC4B
2N7002KDW _SOT363-6
SOC_SPI_0_SO RC2 1 2 49.9_0402_1% SOC_SPI_0_SO_R SOC_SMBCLK 3 4 SOC_SMBCLK_1
S
SOC_SPI_0_CLK SOC_SMBCLK_1 <23,66>
RC3 1 EMC@ 2 49.9_0402_1% SOC_SPI_0_CLK_R Follow 572907_ICL_UY_PDG for Glitch
2
SOC_SPI_0_SI RC4 1 2 49.9_0402_1% SOC_SPI_0_SI_R
G
SOC_SPI_0_IO3 RC5 1 2 49.9_0402_1% SOC_SPI_0_IO3_R QC4A
From SOC 2N7002KDW _SOT363-6
SOC_SMBDATA 6 1 SOC_SMBDATA_1 SOC_SMBDATA_1 <23,66>
S
D
SOC_SPI_0_IO2 RC1 1 2 49.9_0402_1% SOC_SPI_0_IO2_R
MAF - Master Attached Flash

Single SPI Flash attached to SPI Bus
EC FW access through eSPI Bus
< SPI ROM - 16M >

+3VALW _PRIM
A
@ A
UC2 CC3 1 2 0.1U_0201_10V6K
SOC_SPI_0_CS#0 1 8
SOC_SPI_0_SO_R 2 CS# VCC 7 SOC_SPI_0_IO3_R
SOC_SPI_0_IO2_R 3 DO(IO1) IO 6 SOC_SPI_0_CLK_R
4 IO2 CLK 5 SOC_SPI_0_SI_R
GND DI(IO0)
XM25QH128AHIG SOP 8P Security Classification Compal Secret Data Compal Electronics, Inc.
SA0000B8400 2019/04/12 2020/04/12 Title
ICL-U(3/12)SPI,ESPI,SMB,LPC
5 4 3 2 1
5 4 3 2 1
UC1G
CE46
HDA_BIT_CLK CY46 GPP_G6/SD_CLK CC48
HDA_SYNC CV49 GPP_R0/HDA_BCLK/I2S0_SCLK GPP_G1/SD_DATA0 CC49
HDA_SDOUT CY47 GPP_R1/HDA_SYNC/I2S0_SFRM GPP_G2/SD_DATA1 CC47
D D
CV45 GPP_R2/HDA_SDO/I2S0_TXD GPP_G3/SD_DATA2 CF45
<56> HDA_SDIN0 GPP_R3/HDA_SDI0/I2S0_RXD GPP_G4/SD_DATA3
HDA_RST# DA47 CC45
GPP_R4/HDA_RST# GPP_G0/SD_CMD CF49
SD3.0 GPP_G7/SD_WP
DP33 CE47
GPP_D19/I2S_MCLK GPP_G5/SD_CD#
DC45 DK38
HDA_SDIN1 DA49 GPP_A23/I2S1_SCLK GPP_H0/CNV_BT_I2S_SDO DG38
DA45 GPP_R5/HDA_SDI1/I2S1_SFRM GPP_H1/SD_PWR_EN_N/CNV_BT_I2S_SDO
DA48 GPP_R6/I2S1_TXD CJ43 SD3_RCOMP RC358 1 2 200_0402_1%
CT49 GPP_R7/I2S1_RXD SD3_RCOMP
CNV_RF_RESET# CT48 GPP_A7/I2S2_SCLK
<52> CNV_RF_RESET# GPP_A8/I2S2_SFRM/CNV_RF_RESET#
CV47 DG36
CT47 GPP_A10/I2S2_RXD GPP_S6/SNDW4_CLK/DMIC_CLK0 DG34
<52> CLKREQ_CNV# GPP_A9/I2S2_TXD/MODEM_CLKREQ GPP_S7/SNDW4_DATA/DMIC_DATA0
CY39 CV38 SNDW _RCOMP RC359 1 2 200_0402_1%
CY38 GPP_S0/SNDW1_CLK SNDW_RCOMP
GPP_S1/SNDW1_DATA
AUDIO
DB39
DD38 GPP_S2/SNDW2_CLK
GPP_S3/SNDW2_DATA
DF38
DD39 GPP_S4/SNDW3_CLK/DMIC_CLK1
GPP_S5/SNDW3_DATA/DMIC_DATA1
7 of 19
ICL-U_BGA1526
@
C C
< HD AUDIO > RC448 1 2 100K_0402_5% HDA_BIT_CLK

RC449 1 2 33K_0402_5% HDA_RST#
1
RC3947 2 33_0402_5% HDA_RST# RC3946 1 @ 2 33K_0402_5% HDA_SDIN1
<56> HDA_RST#_R
RC46 1 EMC@ 2 33_0402_5% HDA_BIT_CLK
<56> HDA_BIT_CLK_R
RC48 1 2 33_0402_5% HDA_SYNC Follow
<56> HDA_SYNC_R
RC47 1 2 33_0402_5% HDA_SDOUT 572907_ICL_UY_PDG for Glitch
<56> HDA_SDOUT_R
1
RC49
@ 499_0402_1%
2
< To Enable ME Override >

B B
RC51 1 2 0_0402_5% HDA_SDOUT
<58> ME_EN
A A

ICL-U(4/12)HDA,SD
5 4 3 2 1
5 4 3 2 1
+3VS
+3VALW_PRIM
RC352 1 2 10K_0402_5% CLKREQ_PCIE#0 PMCALERT# RC533 2 1 10K_0402_5%

RC353 1 2 10K_0402_5% CLKREQ_PCIE#1 PM_BATLOW# RC69 2 1 8.2K_0402_5%
RC64 1 2 10K_0402_5% CLKREQ_PCIE#2 UC1J
Follow Check list NC for un-used WAKE# RC451 2 1 1K_0402_5%
LAN_WAKE# RC452 1 2 10K_0402_5%
need to check PBTN_OUT#_R RC3955 2 @ 1 100K_0402_5%
CJ3 CF5 AC_PRESENT_R RC3964 1 @ 2 10K_0402_5%
<68> CLK_PCIE_N0 CJ5 CLKOUT_PCIE_N0 CLKOUT_PCIE_N5 CF3
CLKREQ_PCIE#4
M.2/SSD <68> CLK_PCIE_P0 CLKREQ_PCIE#0 CLKOUT_PCIE_P0 CLKOUT_PCIE_P5
RC68 1 @ 2 10K_0402_5% DK33 DP40 573129 RVP reserve both side, INPUT3VSEL INPUT3VSEL RC456 2 @ 1 4.7K_0402_5%
<68> CLKREQ_PCIE#0 GPP_D5/SRCCLKREQ0# GPP_H11/SRCCLKREQ5# but ORB only reserve on RTCX2 3V SELECT STRAP
CL2 HIGH: 3.0V +/-5% RC457 2 1 100K_0402_5%
<51> CLK_PCIE_N1 CL1 CLKOUT_PCIE_N1 DL48 SOC_RTCX1 LOW: 3.3V +/-5%
reserve GLAN <51> CLK_PCIE_P1 CLKREQ_PCIE#1 CLKOUT_PCIE_P1 RTCX1 SOC_RTCX2 SOC_RTCX2_R Follow 573129_ICL_U_DDR4_SODIMM_HW_SCH_RN
DN34 RTC DL49 RC61 1 2 0_0402_5%
<51> CLKREQ_PCIE#1 GPP_D6/SRCCLKREQ1# RTCX2
CL3 DT47 SOC_RTCRST# SUSCLK RC375 1 @ 2 100K_0402_5%
D <52> CLK_PCIE_N2 CLKOUT_PCIE_N2 RTCRST# SOC_SRTCRST# D
WLAN CL5 DK46
<52> CLK_PCIE_P2 CLKREQ_PCIE#2 DP34 CLKOUT_PCIE_P2 SRTCRST#
<52> CLKREQ_PCIE#2 GPP_D7/SRCCLKREQ2#
Follow DF49 SUSCLK Follow
CK3 GPD8/SUSCLK SUSCLK <52>
573129_ICL_U_DDR4_SODIMM_HW_SCH_RN CK4 CLKOUT_PCIE_N3 573129_ICL_U_DDR4_SODIMM_HW_SCH_RN
& 572907_ICL_UY_PDG for Glitch DP36 CLKOUT_PCIE_P3 DW8 SOC_XTAL38.4_IN
+3VALW_PRIM GPP_D8/SRCCLKREQ3# XTAL XTAL_IN DU8 SOC_XTAL38.4_OUT +3VS
CJ2 XTAL_OUT
CJ1 CLKOUT_PCIE_N4
RC3959 1 2 100K_0402_5% PM_SLP_S0# CLKREQ_PCIE#4 DN40 CLKOUT_PCIE_P4 DU6 XCLK_BIASREF RC59 1 2 60.4_0402_1% CPU_C10_GATE# RC3972 2 PREM@ 1 100K_0402_5%
GPP_H10/SRCCLKREQ4# XCLK_BIASREF
RC394 1 2 100K_0402_5% SLP_SUS#
RC395 1 @ 2 100K_0402_5% PM_SLP_S5# 10 of 19
RC396 1 2 100K_0402_5% PM_SLP_S4# ICL-U_BGA1526
RC397 1 2 100K_0402_5% PM_SLP_S3#
@
SOC_RTCX2_R
UC1K
RC398 1 2 100K_0402_5% PM_SLP_A#
RC399 1 2 100K_0402_5% PM_SLP_LAN# SOC_RTCX1
RC400 1 2 100K_0402_5% PM_SLP_WLAN# SLP_SUS# DM49 CY42 PBTN_OUT#_R RC3954 1 2 0_0402_5% PBTN_OUT# <58>
PM_SLP_S5# DF45 SLP_SUS# GPD3/PWRBTN# DE46 AC_PRESENT_R RC66 1 2 0_0402_5% 1 2
GPD10/SLP_S5# GPD1/ACPRESENT AC_PRESENT <58>
PM_SLP_S4# DC48 DH48 PM_BATLOW# RC62 10M_0402_5%
<78> PM_SLP_S4# PM_SLP_S3# GPD5/SLP_S4# GPD0/BATLOW#
DF47
<15,78> PM_SLP_S3# PM_SLP_A# GPD4/SLP_S3#
DH47 CL39 PMCALERT# MP modify
PM_SLP_S0# CL45 GPD6/SLP_A# GPP_B11/PMCALERT# DU40 CPU_C10_GATE#
+3VALW_PRIM <15,58,66> PM_SLP_S0# GPP_B12/SLP_S0# GPP_H18/CPU_C10_GATE# CPU_C10_GATE# <15>
DG40 YC2
PM_SLP_WLAN# DE49 GPP_H3/SX_EXIT_HOLDOFF_N/CNV_BT_I2S_SDO 1 2
RC428 2 1 10K_0402_5% SYS_RESET# PM_SLP_LAN# DN48 GPD9/SPL_WLAN# DL45 WAKE#
SLP_LAN# WAKE# 32.768KHZ_9PF_X1A000141000200
EC_RSMRST# DG49 DE47 LAN_WAKE# SJ10000PW00
+RTCVCC <58> EC_RSMRST# SYS_RESET# RSMRST# GPD2/LAN_WAKE#
8.2P_0201_50V8B
8.2P_0201_50V8B
DK19 DF48 Close SOC ASAP 1 1
PLT_RST# CM49 SYS_RESET# GPD11/LANPHYPC/DSWLDO_MON
<66> PLT_RST# GPP_B13/PLTRST# VCCST_OVERRIDE VCCST_OVERRIDE_R
CC17
CC18
CE4 RC388 1 2 0_0402_5%
RC56 1 2 20K_0402_5% SOC_SRTCRST# VCCST_OVERRIDE CF2 EC_VCCST_PG
C PCH_DPWROK DR48 VCCST_PWRGD CE3 VCCSTPWRGOOD_TCSS RC453 1 2 0_0402_5% 2 2 C
CC13 1 2 1U_0201_6.3V6M PCH_PWROK DN47 DSW_PWROK VCCSTPWRGOOD_TCSS CF1 H_PROCPWRGD
<58,78> PCH_PWROK PCH_PWROK PROCPWRGD TP@ T503
SYS_PWROK DP19 Only For Power Sequence Debug
<58,78> SYS_PWROK SYS_PWROK DC47 GPD7
GPD7 TP@ T501
INPUT3VSEL DN49 PVT modify
SM_INTRUDER# DR47 INPUT3VSEL EC_RSMRST# RC3948 1 2 0_0402_5% PCH_DPWROK
RC58 1 2 20K_0402_5% SOC_RTCRST# INTRUDER#
SOC_RTCRST# <58>
SYS_PWROK RC3950 1 @ 2 0_0402_5% PCH_PWROK
CC14 1 2 1U_0201_6.3V6M 11 of 19
ICL-U_BGA1526
JCMOS1 1 @ 2 0_0603_5% CLR CMOS @
EC_VCCST_PG_R Follow C38
RC377 1 @ 2 1M_0402_5% SM_INTRUDER# SM_INTRUDER# +3VALW_PRIM
NO INTERNAL PU/PD tCPU22/ tPCH28b RC3973
3
@ CC319 1 2 0.1U_0201_10V6K HIGH: SPI VOLTAGE IS 1.8V 100K_0402_5% D
LOW: SPI VOLTAGE IS 3.3V From EC (Open-Drain) +1.05V_VCCST D15 @ 2 1 PM_SLP_S3#_N 5
RC427 2 1 10K_0402_5% EC_VCCST_PG_R 2 G
6
1 PM_SLP_S3# D QC5B
1
RC386 1 2 100K_0402_5% EC_RSMRST# PCH_PWROK RC537 1 @ 2 0_0402_5% PCH_PWROK_R 3 PM_SLP_S3# 2 S 2N7002KDW_SOT363-6
4
RC78 2 1 8.2K_0402_5% PCH_PWROK RC76 G
1K_0402_5% LRB715FT1G_SOT323-3
SCS00008E00 S QC5A
1
2 2N7002KDW_SOT363-6
tPLT17
EC_VCCST_PG_R RC77 1 2 60.4_0402_1% EC_VCCST_PG D32 @
2 1 100P_0402_50V8J SYS_RESET# <58,78> EC_VCCST_PG_R
EMC@ CC20
VR_ON 2 1 PM_SLP_S3# D16 @
1 <58,78,88> VR_ON
EMC@ CC21 2 1 100P_0402_50V8J EC_RSMRST# CC15
100P_0402_50V8J RB751V-40_SOD323-2 EC_VCCST_PG_R 2 1 PM_SLP_S3#
@EMC@ CC376 2 1 100P_0402_50V8J SYS_PWROK EMC@ SCS00000Z00
2 RB751V-40_SOD323-2
EMC@ CC23 2 1 100P_0402_50V8J PLT_RST# SCS00000Z00
@EMC@ CC377 2 1 100P_0402_50V8J PCH_PWROK

B ESD SOC_XTAL38.4_IN RC54 1 EMC@ 2 0_0402_5% SOC_XTAL38.4_IN_R B
SOC_XTAL38.4_OUT RC55 1 EMC@ 2 0_0402_5% SOC_XTAL38.4_OUT_R
ESD
cost down plan EMI RC57 1 2 200K_0402_1%
VCCST_EN R345 1 @ 2 0_0402_5% EMI want to change 33 ohm, but ORB &CRB is 0ohm
D14 YC3
2 MP modify 1 3 MP modify
<17,91> VCCIN_AUX_CORE_VID0_R
1 2 4
2
3 VCCIN_AUX_CORE_VID <58> To EC CC162 CC163
<17,58,91> VCCIN_AUX_CORE_VID1_R
Singal Name Input 12P_0402_50V8J 38.4MHZ_10PF_8Y38420005 12P_0402_50V8J
LRB715FT1G_SOT323-3 SJ10000VM00
1
SCS00008E00
PVT modify VCCIN_AUX_CORE_VID H D D L
R344 1 2 0_0402_5% From EC to VCCST
<58> EC_VCCST_EN VCCST_EN_LS <16> VR Power SW Enable
Premium
PM_SLP_S3# R342 1 @ 2 0_0402_5% VCCST_OVERRIDE_LS D H D L

PCH PLTRST Buffer
PM_SLP_S4# R343 1 @ 2 0_0402_5% RC63 1 2 0_0402_5%
PM_SLP_S3# (SUSP#) D D H L
+3VS
EC_VCCST_EN Output H H H L CC19 @
1 2
+3VALW
5
VCCIN_AUX_CORE_VID H D D L 0.1U_0201_10V6K
100K_0402_5% 1 2 RC417 VCCST_OVERRIDE_LS To EC PLT_RST# 1
P
100K_0402_5% 1 2 RC418 VCCST_OVERRIDE_N B 4 PLT_RST_BUF#
VCCST_OVERRIDE_R VCCST_OVERRIDE_LS <58> Y PLT_RST_BUF# <51,52,68>
100K_0402_5% 1 2 RC419 VCCST_OVERRIDE_LS D H D L 2
Volume
G
UC4 @
1
100K_0402_5%
74AHC1G08GW_SOT353-5
3
1
RC312
A PM_SLP_S4# (SYSON) D D H L SA741080400 A
VCCST_OVERRIDE_N 2 QC3
G BSS138W-7-F_SOT323-3
VGS(Max) : 1.5S V SB00001GC00 EC_VCCST_EN Output H H H L
3
2
For Glitch
1
D stuff for CNVI check list

VCCST_OVERRIDE_R 2 QC2
G BSS138W-7-F_SOT323-3
VGS(Max) : 1.5 V S SB00001GC00
3
Size
ICL-U(5/12)CLK,GPIO
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
Date: Wednesday, October 30, 2019 Sheet 11 of 102
5 4 3 2 1
5 4 3 2 1
D D
UC1F
CH48 DV33 PROJECT_ID0

SOC_GPP_B18 CF48 GPP_B16/GSPI0_CLK GPP_D13/ISH_UART0_RXD DW33 PROJECT_ID1
CF47 GPP_B18/GSPI0_MOSI GPP_D14/ISH_UART0_TXD DT33 +3VALW_PRIM
CH49 GPP_B17/GSPI0_MISO GPP_D15/ISH_UART0_RTS_N/GSPI2_CS1_N/IMGCLKOUT5 DU33 SOC_GPP_D16
PCH_SPKR CH47 GPP_B15/GSPI0_CS0# GPP_D16/ISH_UART0_CTS_N/CNV_WCEN
<56> PCH_SPKR GPP_B14/SPKR/TIME_SYNC1/GSPI0_CS1# PROJECT_ID0
UART DK22 RC207 2 @ 1 10K_0402_5%
G_INT# CL47 GSPI GPP_C12/UART1_RXD/ISH_UART1_RXD DW24 RC3958 1 2 10K_0402_5%
<66> G_INT# GPP_B20/GSPI1_CLK GPP_C13/UART1_TXD/ISH_UART1_TXD
CK47 DV24
CK46 GPP_B22/GSPI1_MOSI GPP_C14/UART1_RTS#/ISH_UART1_RTS# DU24
CH45 GPP_B21/GSPI1_MISO GPP_C15/UART1_CTS#/ISH_UART1_CTS# PROJECT_ID1 RC211 2 @ 1 10K_0402_5%
SOC_GPP_B23 CL48 GPP_B19/GSPI1_CS0# CN43 RC213 1 2 10K_0402_5%
+3VALW_PRIM GPP_B23/SML1ALERT#/PCHHOT#/GSPI1_CS1# GPP_B5/ISH_I2C0_SDA CN42
DP21 GPP_B6/ISH_I2C0_SCL
DK21 GPP_C8/UART0_RXD CN41
DL21 GPP_C9/UART0_TXD I2C / ISH GPP_B7/ISH_I2C1_SDA CL43
DJ22 GPP_C10/UART0_RTS# GPP_B8/ISH_I2C1_SCL
GPP_C11/UART0_CTS# CL41
UART_2_CRXD_DTXD DT22 UART GPP_B9/I2C5_SDA/ISH_I2C2_SDA CJ39
<52> UART_2_CRXD_DTXD UART_2_CTXD_DRXD DW22 GPP_C20/UART2_RXD GPP_B10/I2C5_SCL/ISH_I2C2_SCL DU36 RAM_ID0 Project_ID1 Project_ID0
RC166 1 2 2.2K_0402_5% I2C_1_SDA <52> UART_2_CTXD_DRXD UART_2_CRTS_DCTS DV22 GPP_C21/UART2_TXD GPP_D0/ISH_GP0 DV36 RAM_ID1 Project ID
RC167 1 2 2.2K_0402_5% I2C_1_SCL UART_2_CCTS_DRTS DU22 GPP_C22/UART2_RTS# GPP_D1/ISH_GP1 DW36 RAM_ID2 GPP_D14 GPP_D13
GPP_C23/UART2_CTS# GPP_D2/ISH_GP2 DT36 RAM_ID3
DT24 ISH GPP_D3/ISH_GP3 DU34
* FH5LI 0 0
DT23 GPP_C16/I2C0_SDA GPP_D17/ISH_GP4 DW34
GPP_C17/I2C0_SCL GPP_D18/ISH_GP5 DT14 NA 0 1
I2C_1_SDA DW23 GPP_E15/ISH_GP6 DU14
+3VS
Touch Pad
<63> I2C_1_SDA I2C_1_SCL DU23 GPP_C18/I2C1_SDA GPP_E16/ISH_GP7 NA 1 0
<63> I2C_1_SCL GPP_C19/I2C1_SCL
DU41 I2C NA 1 1
DV41 GPP_H4/I2C2_SDA
RC459 1 2 49.9K_0402_1% UART_2_CRXD_DTXD GPP_H5/I2C2_SCL
RC460 1 2 49.9K_0402_1% UART_2_CTXD_DRXD DW41
DT41 GPP_H6/I2C3_SDA
C
RC3956 1 @ 2 49.9K_0402_1% UART_2_CRTS_DCTS GPP_H7/I2C3_SCL C
RC3957 1 @ 2 49.9K_0402_1% UART_2_CCTS_DRTS DT40
DW40 GPP_H8/I2C4_SDA/CNV_MFUART2_RXD
GPP_H9/I2C4_SCL/CNV_MFUART2_TXD 6 of 19
ICL-U_BGA1526
@
Memory Down Strap

+3VALW_PRIM
B B
1
RC151 RC150 RC153 RC224

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
NODX76@ NODX76@ NODX76@ NODX76@ Strap Pin
2
RAM_ID0
RAM_ID1
RAM_ID2 +3VALW_PRIM +3VALW_PRIM
RAM_ID3
1
4.7K_0402_5%
RC278
4.7K_0402_5%
RC277
4.7K_0402_5%
RC279
10K_0402_5%
RC283
RC155 RC225 RC226 RC227
1
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
@ @ @ @
GPP_B23
2
@
CPUNSSC CLOCK FREQ
INTERNAL PD 20K
2
HIGH: 19.2 MHz (form internal divider)
LOW: 38.4 MHz (direct form crystal) (Default)
SOC_GPP_B18 SOC_GPP_B23
GPP_B18
No Reboot
PCH_SPKR SOC_GPP_D16 INTERNAL PD 20K
HIGH: No Reboot
LOW: Reboot Enable (Default)
1
20K_0402_5%
RC281
20K_0402_5%
RC282
20K_0402_5%
RC285
100K_0402_5%
RC280
RAM_ID3 RAM_ID2 *RAM_ID1 *RAM_ID0 PartNumber - Description GPP_D16 Strap refer RVP
ZZZ1 Hynix4GB SPKR
X76DHYN@ X76829BOL04 Hynix 4GB SA0000BMN30 (S IC D4 512M16 H5AN8G6NCJR-VKC FBGA ABO!) TOP SWAP OVERRIDE
0 0 0 0 INTERNAL PD 20K
HIGH: Top swap enable
@
ZZZ2 Micron4GB Micron 4GB SA0000ARD60 (S IC D4 8G/2666 MT40A512M16LY-075:E ABO!)
0 0 0 1 LOW: Disable (Default)
2
2
X76DMIC@ X76829BOL05
Samsung 4GB 0 0 1 0 SA0000B6F30 (S IC D4 512M16 K4A8G165WC-BCTD FBGA 96P)
ZZZ3 Samsung4GB GPP_D16
A X76DSAM@ X76829BOL06 MFR_MODE_DET_STRAP A
0 0 1 1 Follow 573129_ICL_U_DDR4_SODIMM_HW_SCH_RN_1P0
No OnBoard No On Board Memory
Memory 1 1 1 1

Size
ICL-U(6/12)GPIO
Document Number Rev
1.0
5 4 3 2 1
5 4 3 2 1
UC1H
CV7 DJ8 USB3_CRX_DTX_N1 <72>

CV6 PCIE7_RXN PCIE1_RXN/USB31_1_RXN DJ6
PCIE7_RXP PCIE1_RXP/USB31_1_RXP USB3_CRX_DTX_P1 <72>
DD3 DJ2 USB3 MB (Front&Charging)
PCIE7_TXN PCIE1_TXN/USB31_1_TXN USB3_CTX_DRX_N1 <72>
DD5 DJ1
PCIE7_TXP PCIE1_TXP/USB31_1_TXP USB3_CTX_DRX_P1 <72>
CT6 DG9
CT7 PCIE8_RXN PCIE2_RXN/USB31_2_RXN DG7
DA3 PCIE8_RXP PCIE2_RXP/USB31_2_RXP DJ3
DA5 PCIE8_TXN PCIE2_TXN/USB31_2_TXN DJ5
PCIE8_TXP PCIE2_TXP/USB31_2_TXP
D D
PCIE_CRX_DTX_N9 CP7 PCIe DE7
<51> PCIE_CRX_DTX_N9 PCIE9_RXN PCIE3_RXN/USB31_3_RXN USB3_CRX_DTX_N3 <71>
PCIE_CRX_DTX_P9 CP6 DE9
<51> PCIE_CRX_DTX_P9 PCIE9_RXP PCIE3_RXP/USB31_3_RXP USB3_CRX_DTX_P3 <71>
LAN CC25 2 1 .1U_0402_16V7K PCIE_CTX_DRX_N9 DA2 DF3
<51> PCIE_CTX_C_DRX_N9
CC26 2 1 .1U_0402_16V7K PCIE_CTX_DRX_P9 DA1 PCIE9_TXN PCIE3_TXN/USB31_3_TXN DF5
USB3_CTX_DRX_N3 <71> USB3 MB
<51> PCIE_CTX_C_DRX_P9 PCIE9_TXP PCIE3_TXP/USB31_3_TXP USB3_CTX_DRX_P3 <71>
PCIE_CRX_DTX_N10 CM7 PCIe / USB3.1 DC7
<52> PCIE_CRX_DTX_N10 PCIE_CRX_DTX_P10 CM6 PCIE10_RXN PCIE4_RXN/USB31_4_RXN DC9
<52> PCIE_CRX_DTX_P10 1 2 .1U_0402_16V7K PCIE_CTX_DRX_N10 CY3 PCIE10_RXP PCIE4_RXP/USB31_4_RXP DF2
WLAN <52> PCIE_CTX_C_DRX_N10
CC60
PCIE10_TXN PCIE4_TXN/USB31_4_TXN
CC62 1 2 .1U_0402_16V7K PCIE_CTX_DRX_P10 CY4 DF1
<52> PCIE_CTX_C_DRX_P10 PCIE10_TXP PCIE4_TXP/USB31_4_TXP
CK7 DA6
<67> SATA_CRX_DTX_N0 CK6 PCIE11_RXN/SATA0_RXN PCIE5_RXN/USB31_5_RXN DA7
<67> SATA_CRX_DTX_P0 CW2 PCIE11_RXP/SATA0_RXP PCIE5_RXP/USB31_5_RXP DE4
HDD <67> SATA_CTX_DRX_N0 PCIE11_TXN/SATA0_TXN PCIE5_TXN/USB31_5_TXN
CW1 DE3
<67> SATA_CTX_DRX_P0 CJ6 PCIE11_TXP/SATA0_TXP PCIE5_TXP/USB31_5_TXP
<67> SATA_CRX_DTX_N1 PCIE12_RXN/SATA1A_RXN PCIe / SATA CY7
CJ7 PCIE6_RXN/USB31_6_RXN CY6
<67> SATA_CRX_DTX_P1 CW5 PCIE12_RXP/SATA1A_RXP PCIE6_RXP/USB31_6_RXP DD1
ODD <67> SATA_CTX_DRX_N1 PCIE12_TXN/SATA1A_TXN PCIE6_TXN/USB31_6_TXN DD2
CW3 PCIE6_TXP/USB31_6_TXP
<67> SATA_CTX_DRX_P1 CG7 PCIE12_TXP/SATA1A_TXP DN8
<68> PCIE_CRX_DTX_N13 PCIE13_RXN USB2N_1 USB20_N1 <72>
<68> PCIE_CRX_DTX_P13 CG6 DP8 USB3 MB (Front&Charging)
PCIE13_RXP USB2P_1 USB20_P1 <72>
CT3
<68> PCIE_CTX_DRX_N13 PCIE13_TXN
CT5 DK11
<68> PCIE_CTX_DRX_P13 PCIE13_TXP USB2N_2 DJ11
CE6 PCIe USB2P_2
<68> PCIE_CRX_DTX_N14 PCIE14_RXN
<68> PCIE_CRX_DTX_P14 CE7 DP13
PCIE14_RXP USB2N_3 USB20_N3 <71>
CT2 DN13 USB3 MB
<68> PCIE_CTX_DRX_N14 PCIE14_TXN USB2P_3 USB20_P3 <71>
C CT1 C
<68> PCIE_CTX_DRX_P14 PCIE14_TXP
SSD DK10
USB2N_4 USB20_N4 <73>
<68> PCIE_CRX_DTX_N15 CC5 DJ10 TO D/B USB2
PCIE15_RXN/SATA1B_RXN USB2P_4 USB20_P4 <73>
<68> PCIE_CRX_DTX_P15 CC6
CR3 PCIE15_RXP/SATA1B_RXP DL5
<68> PCIE_CTX_DRX_N15 PCIE15_TXN/SATA1B_TXN USB2N_5 USB20_N5 <66>
CR4 DL3 FP
<68> PCIE_CTX_DRX_P15 PCIE15_TXP/SATA1B_TXP PCIe / SATA USB2P_5 USB20_P5 <66>
<68> PCIE_CRX_DTX_N16 CA6 DP11

PCIE16_RXN/SATA2_RXN USB2N_6 USB20_N6 <38>
<68> PCIE_CRX_DTX_P16 CA5 DN11 TS
SATA SSD PCIE16_RXP/SATA2_RXP USB2P_6 USB20_P6 <38>
CP1 USB2.0
<68> PCIE_CTX_DRX_N16 PCIE16_TXN/SATA2_TXN
CP2 DK13
<68> PCIE_CTX_DRX_P16 PCIE16_TXP/SATA2_TXP USB2N_7 USB20_N7 <38>
RC402 @ DJ13 Camera
USB2P_7 USB20_P7 <38>
10K_0402_5% DW 12
1 2 CR42 GPP_E0/SATAXPCIE0/SATAGP0 DN6
+3VS GPP_A12/SATAXPCIE1/SATAGP1 USB2N_8 USB20_N8 <73>
SATAXPCIE2 CR43 DP6
<68> SATAXPCIE2 GPP_A13/SATAXPCIE2/SATAGP2 USB2P_8 USB20_P8 <73> Card reader(Reserved)
USB_OC0# DW 14 DL2
USB_OC3# CT43 GPP_E9/USB_OC0# USB2N_9 DL1
GPP_A16/USB_OC3# USB2P_9
DU12 DP10
GPP_E4/DEVSLP0 USB2N_10 USB20_N10 <52>
DU11 DN10 BT
GPP_E5/DEVSLP1 USB2P_10 USB20_P10 <52>
CV48
+3VALW _PRIM <68> SSD_DEVSLP2 GPP_A11 / DEVSLP2 DL6 USB2_ID RC355 1 2 10K_0402_5%
USB_OC0# Strap refer RVP USB_ID
DT38
RC401 1 2 10K_0402_5% USB_OC0# DW 38 GPP_H12/M2_SKT2_CFG0 DL11 USB2_VBUSSENSE RC354 1 2 10K_0402_5%
RC403 1 2 10K_0402_5% USB_OC3# DV38 GPP_H13/M2_SKT2_CFG1 USB_VBUSSENSE
DU38 GPP_H14/M2_SKT2_CFG2 DN5 USB2_COMP RC356 1 2 113_0402_1%
GPP_H15/M2_SKT2_CFG3 USB2_COMP
check list needs stuff even un-use PCIE_RCOMPN UFS_RESET#
RC100 1 2 100_0402_1% DN1 CD3 1 T328
B PCIE_RCOMPP DN3 PCIE_RCOMPN RSVD_81 TP@ B
PCIE_RCOMPP
8 of 19 From ACER HSIO
Note : ICL-U_BGA1526
Please reference PCH EDS Tabel 1-2 @
A A

ICL-U(7/12)PCIE,USB,SATA
5 4 3 2 1
5 4 3 2 1
UC1I
D12 DP27
C12 CSI_E_CLK_N GPP_F8/EMMC_DATA0 DU30
B12 CSI_E_CLK_P GPP_F9/EMMC_DATA1 DT30
D D
A12 CSI_E_DN_0 GPP_F10/EMMC_DATA2 DT29
G13 CSI_E_DP_0 GPP_F11/EMMC_DATA3 DV30
F13 CSI_E_DN_1 GPP_F12/EMMC_DATA4 DU29
CSI_E_DP_1 GPP_F13/EMMC_DATA5 DW30
K10 eMMC GPP_F14/EMMC_DATA6 DW29
L10 CSI_F_CLK_N GPP_F15/EMMC_DATA7 DV28
L8 CSI_F_CLK_P GPP_F7/EMMC_CMD DW28
M8 CSI_F_DN_0 GPP_F16/EMMC_RCLK DN27
M11 CSI_F_DP_0 GPP_F17/EMMC_CLK DT28
L11 CSI_F_DN_1
CSI_F_DP_1
1.8V GPP_F18/EMMC_RESET#
EMMC_RCOMP
DU28 EMMC_RCOMP
D9
C9 CSI_D_CLK_N DV45
CSI_D_CLK_P CNV_WT_D0N CNV_CTX_DRX_N0 <52>
A7 DU45 CNV_CTX_DRX_P0 <52>
B7 CSI_D_DN_0 CNV_WT_D0P DU44
CSI_D_DP_0 CNV_WT_D1N CNV_CTX_DRX_N1 <52>
B9 DT44 CNV_CTX_DRX_P1 <52>
A9 CSI_D_DN_1 CNV_WT_D1P DL42
CSI_D_DP_1 CNV_WT_CLKN CLK_CNV_CTX_DRX_N <52>
D7 DK42 CLK_CNV_CTX_DRX_P <52>
C7 CSI_D_DN_2/CSI_C_DN_0 CNV_WT_CLKP EMMC_RCOMP RC104 2 1 200_0402_1%
D8 CSI_D_DP_2/CSI_C_DP_0 DP44
CSI_D_DN_3/CSI_C_CLK_N CNV_WR_D0N CNV_CRX_DTX_N0 <52>
C8 CSI2 DN44
CSI_D_DP_3/CSI_C_CLK_P CNV_WR_D0P CNV_CRX_DTX_P0 <52>
DG42
CNV_WR_D1N CNV_CRX_DTX_N1 <52> SOC_GPP_F19 RC432
G11 DG44 1 2 75K_0402_5%
CSI_H_CLK_N CNV_WR_D1P CNV_CRX_DTX_P1 <52>
J11 DK44 CLK_CNV_CRX_DTX_N <52>
F6 CSI_H_CLK_P CNVi CNV_WR_CLKN DJ44
CSI_H_DN_0 CNV_WR_CLKP CLK_CNV_CRX_DTX_P <52>
G6 Follow 574200 MoW WW03
G10 CSI_H_DP_0 DT45 CNV_W T_RCOMP RC109 1 2 150_0402_1%
F10 CSI_H_DN_1 CNV_WT_RCOMP
C G8 CSI_H_DP_1 DL29 CNV_BRI_CRX_DTX C
CSI_H_DN_2/CSI_G_DN_0 GPP_F1/CNV_BRI_RSP/UART0_RXD CNV_RGI_CTX_DRX CNV_BRI_CRX_DTX <52>
J8 DP31 CNV_RGI_CTX_DRX <52>
K6 CSI_H_DP_2/CSI_G_DP_0 GPP_F2/CNV_RGI_DT/UART0_TXD DL31 CNV_BRI_CTX_DRX
CSI_H_DN_3/CSI_G_CLK_N GPP_F0/CNV_BRI_DT/UART0_RTS# CNV_BRI_CTX_DRX <52>
L6 DN29 CNV_RGI_CRX_DTX
CSI_H_DP_3/CSI_G_CLK_P GPP_F3/CNV_RGI_RSP/UART0_CTS# CNV_RGI_CRX_DTX <52>
RC357 1 2 CSI_RCOMP B4 DJ29 SOC_GPP_F4
100_0402_1% CSI_RCOMP GPP_F4/CNV_RF_RESET# DP29
DT34 GPP_F6/CNV_PA_BLANKING DL27 SOC_GPP_F19
DP38 GPP_D4/IMGCLKOUT0 GPP_F19/A4WP_PRESENT DK29 SOC_GPP_F5 1
DK36 GPP_H20/IMGCLKOUT1 GPP_F5/MODEM_CLKREQ TP@ T340
DL36 GPP_H21/IMGCLKOUT2
DN38 GPP_H22/IMGCLKOUT3
GPP_H23/IMGCLKOUT4
1.8V
9 of 19
ICL-U_BGA1526 SOC_GPP_F4
@
1
RC440
75K_0402_5%
@
CNV_RGI_CTX_DRX CNV_BRI_CTX_DRX
2
M.2 CNVI MODES XTAL SEL
Follow 572907_ICL_UY_PDG
Follow check list reserve
+1.8VALW _PRIM 0 = Integrated CNVi enable. 0 = 38.4/19.2MHZ (DEFAULT) PC glitch free,it is recommended that a
B pull-down resistor of 75K B
1 = Integrated CNVi disable. 1 = 24MHZ (25 MHZ WHEN XTAL FREQ DIVIDER NON ZERO) ohm on GPP_F4(CNV_RF_RESET#)
RC181 1 @ 2 20K_0402_5% CNV_BRI_CRX_DTX
RC182 1 @ 2 20K_0402_5% CNV_RGI_CRX_DTX NO INTERNAL PU/PD WEAK INTERNAL PD 20K

+1.8VALW _PRIM +1.8VALW _PRIM
CNV_RGI_CTX_DRX RC373 1 2 100K_0402_5% CNV_BRI_CTX_DRX RC374 1 @ 2 4.7K_0402_5%
RC112 1 @ 2 4.7K_0402_5% RC111 1 @ 2 20K_0402_5%
A A

ICL-U(8/13)CSI,CNV
5 4 3 2 1
5 4 3 2 1
+1.2V_VDDQ Primuem/Volume
+1.2V_VDDQ TO +1.2V_VCCPLL_OC +1.2V_VDDQ
+VCCIN +VCCIN
2
For NON-S0IX UC1L
1U_0201_6.3V6M
Imax : 0.152 A 1 VOL@
CC306
RC3970 A19 CPU POWER 1 OF 3 CJ35
For Power consumption UC11 AC12 VCCIN_1 VCCIN_52 CK10
0_0603_5% VCCIN_2 VCCIN_53
Measurement PREM@ 1 V13 J32
1
2 2 VIN1 +1.2V_VCCPLL_OC W12 VCCIN_3 VCCIN_54 CL34
PREM@ +5VALW VIN2 JUMP@ JPC6 Y13 VCCIN_4 VCCIN_55 CL35
CC307 7 6 +1.2V_VCCPLL_OC_P 1 2 K29 VCCIN_5 VCCIN_56 CN34
D D
0.1U_0201_10V6K VIN thermal VOUT 1 2 K31 VCCIN_6 VCCIN_57 CN35
2 1 3 JUMP_43X79 B19 VCCIN_7 VCCIN_58 CP33
VBIAS 1 Imax : 0.152 A VCCIN_8 VCCIN_59
CC308 B23 CR34
VCCSTG_EN_LS 1 PREM@ 2VCCPLL_OC_EN_LS_R 4 5 B27 VCCIN_9 VCCIN_60 A29
ON GND 0.1U_0201_10V6K VCCIN_10 VCCIN_61
RC408 B29 CR35
2 VCCIN_11 VCCIN_62
1U_0201_6.3V6M
0_0402_5% 1 BN10 CT33
VCCIN_12 VCCIN_63
CC309
EM5201V_DFN8_3X3 BP11 CT34
PREM@ PREM@ BP9 VCCIN_13 VCCIN_64 CT35
BR10 VCCIN_14 VCCIN_65 CU33
2 BT11 VCCIN_15 VCCIN_66 D19
I (Max) : 0.152 A(+1.2V_VCCPLL_OC) VCCIN_16 VCCIN_67
RDS(Typ) : 3.5 mohm A21 D21
BT9 VCCIN_17 VCCIN_68 D23
V drop : 0.0005V BU10 VCCIN_18 VCCIN_69 D24
+1.8VALW _PRIM BV36 VCCIN_19 VCCIN_70 D27
BV9 VCCIN_20 VCCIN_71 AA12
+1.8VALW _PRIM BW10 VCCIN_21 VCCIN_72 D29
+1.8V_PRIM_SOC BW36
BW9
VCCIN_22
VCCIN_23
VCCIN_73
VCCIN_74
F19
F21
VCCIN_24 VCCIN_75
1
1U_0201_6.3V6M
Imax : 0.7 A 1 For NON-S0IX BY10 F23
VCCIN_25 VCCIN_76
CC117
VOL@ C19 F24

For Power consumption UC12 RC407 C23 VCCIN_26 VCCIN_77 F27
Measurement PREM@ 1 A23 VCCIN_27 VCCIN_78 F29
VIN1 0_0603_5% VCCIN_28 VCCIN_79
2 2 +1.8V_PRIM_SOC C27 G1
2
PREM@ +5VALW VIN2 JUMP@ JPC5 C29 VCCIN_29 VCCIN_80 G19
CC107 7 6 +1.8V_PRIM_SOC_P 1 2 CA36 VCCIN_30 VCCIN_81 G23
0.1U_0201_10V6K VIN thermal VOUT 1 2 CA9 VCCIN_31 VCCIN_82 AB1
2 1 3 JUMP_43X79 CB10 VCCIN_32 VCCIN_83 G27
VBIAS 1 Imax : 0.7 A VCCIN_33 VCCIN_84
CC127 CC11 G29
C CPU_C10_GATE# 1 PREM@ 2 CPU_C10_GATE#_R 4 5 CC36 VCCIN_34 VCCIN_85 H19 C
ON GND 0.1U_0201_10V6K VCCIN_35 VCCIN_86
RC186 CC9 H23
2 VCCIN_36 VCCIN_87
1U_0201_6.3V6M
0_0402_5% 1 CD10 H27

VCCIN_37 VCCIN_88
CC305
EM5201V_DFN8_3X3 CE11 H29

PREM@ PREM@ A24 VCCIN_38 VCCIN_89 J18
CE34 VCCIN_39 VCCIN_90 J20
2 CE35 VCCIN_40 VCCIN_91 J22
CF10 VCCIN_41 VCCIN_92 J23
I (Max) : 0.7 A(+1.8V_PRIM_SOC) VCCIN_42 VCCIN_93
+3VALW _PRIM CF33 AB13
RDS(Typ) : 3.5 mohm VCCIN_43 VCCIN_94
CG11 J26
V drop : 0.0024V CG34 VCCIN_44 VCCIN_95 J28
CG35 VCCIN_45 VCCIN_96 K17
1 VCCIN_46 VCCIN_97
CC49 CH10 K19
J30 VCCIN_47 VCCIN_98 K21
0.1U_0201_10V6K VCCIN_48 VCCIN_99
SUSP# RC132 1 PREM@ 2 0_0402_5% PREM@ CJ11 K23
<16,58,78,84,86> SUSP# 2 VCCIN_49 VCCIN_100
A27 K24
VCCIN_50 VCCIN_101
5
PM_SLP_S3# RC133 1 @ 2 0_0402_5% UC7 CJ34 K27
<11,78> PM_SLP_S3# VCCIN_51 VCCIN_102
1 M1
P
B 4 VCCSTG_EN_LS 12 of 19 VCCIN_103 U1
@ Y VCCSTG_EN_LS <16> VCCIN_104
PM_SLP_S0# RC134 1 2 0_0402_5% 2 CPU_SVID_ALERT# H1
<11,58,66> PM_SLP_S0# A VIDALERT#
G
CPU_SVID_CLK H2 F17
CPU_SVID_DAT VIDSCK VCCIN_SENSE VCC_SENSE_VCCIN <88>
74AHC1G08GW _SOT353-5 H3 G17
VSS_SENSE_VCCIN <88>
3
CPU_C10_GATE# 1 2 0_0402_5% PREM@ VIDSOUT VSSIN_SENSE
<11> CPU_C10_GATE#
RC3971 PREM@ ICL-U_BGA1526
@
B +1.05V_VCCST B
SVID DATA
1
RC148
100_0402_1%
2
0_0402_5% 2 1 RC362 CPU_SVID_DAT

<88> CPU_SVID_DAT_R
+1.05V_VCCST
SVID ALERT
2
RC146
56_0402_5%
1
0_0402_5% 2 1 RC363 CPU_SVID_ALERT#

<88> CPU_SVID_ALERT#_R
A
SVID CLOCK A
0_0402_5% 2 1 RC364 CPU_SVID_CLK

<88> CPU_SVID_CLK_R
ICL-U(9/13)Power, SVID
5 4 3 2 1
5 4 3 2 1
+1.2V_VDDQ +1.2V_VDDQ
UC1M
AA37 CPU POWER 2 OF 3 BP39

AG36 VDDQ_1 VDDQ_31 BR37 +1.05VS_VCCSTG_OUT_FUSE +1.05V_VCCST +1.8V_PRIM_SOC +1.05VO_VCCPLL
EMC CAPS-PLACE AJ36 VDDQ_2
VDDQ_3
VDDQ_32
VDDQ_33
BT38 reserve more
AL36 AC35
< 4mm from SOC VDDQ AL49 VDDQ_4 VDDQ_34 BU37
VDDQ_5 VDDQ_35
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6K
1U_0201_6.3V6M
1U_0201_6.3V6M
with each pair < 12mm Apart AN36
VDDQ_6 VDDQ_36
BU49 1 1 1 1 1 1 1
1U_0201_6.3V6M
CC271
CC274 @
CC34 @
CC270
CC273
AP37 CA39
VDDQ_7 VDDQ_37
12pF* 3 (EMI@)
CC267 @
CC207
CC208
AR36 CB49 1
AR37 VDDQ_8 VDDQ_38 L38
VDDQ_9 VDDQ_39
2.2pF* 3 (EMI@) AT36
VDDQ_10 VDDQ_40
L49 2 2 2 2 2 2 2
@
AT49 N36
VDDQ_11 VDDQ_41 2
@
AA49 T49
AV36 VDDQ_12 VDDQ_42 AC37
D VDDQ_13 VDDQ_43 D
+1.2V_VDDQ +1.2V_VDDQ +1.2V_VDDQ AW37 AD35
AY36 VDDQ_14 VDDQ_44 AD36
BA37 VDDQ_15 VDDQ_45 AE36 Follow 573129 RVP reserve close to BGA
BA49 VDDQ_16 VDDQ_46 AF49
BB36 VDDQ_17 VDDQ_47
BD36 VDDQ_18 C33 1
1 1 1 1 1 1 VDDQ_19 RSVD_78 TP@ T446
2.2P_0201_50V8C
CC218
12P_0201_50V8J
CC219
2.2P_0201_50V8C
CC220
12P_0201_50V8J
CC221
2.2P_0201_50V8C
CC222
12P_0201_50V8J
CC223
BE37
BF36 VDDQ_20 A33 1 +1.8V_PRIM_SOC
VDDQ_21 RSVD_2 TP@ T447 +1.05VS_VCCSTG +1.2V_VCCPLL_OC
BF37 B33 1
2 2 2 2 2 2 VDDQ_22 RSVD_3 TP@ T448
AB36 reserve more
VDDQ_23
EMC@
EMC@
EMC@
EMC@
EMC@
EMC@
BF49 BG9
BG36 VDDQ_24 VCC1P8A_1 BJ9
VDDQ_25 VCC1P8A_2
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
BJ36 BM9 1 1 1
VDDQ_26 VCC1P8A_3
CC272
CC275
CC35
1U_0201_6.3V6M
1U_0201_6.3V6M
BL37 BW1
VDDQ_27 VCC1P8A_4
CC278
CC276
BM49 BW2 1 1
BN37 VDDQ_28 VCC1P8A_5 +1.05VS_VCCSTG_OUT_FUSE
+1.05V_VCCST BP38 VDDQ_29 R35 2 2 2
VDDQ_30 VCCSTG_OUT_3
@
V34
+1.05VS_VCCSTG VCCSTG_OUT_4 2 2
@
CB1 T34
VCCST VCCSTG_OUT_5 U35
BY1 VCCSTG_OUT_6 AB34
VCCSTG VCCSTG_OUT_7 W35
+1.05VS_VCCSTG_OUT_FUSE RSVD_74 AA35 +1.05VO_VCCPLL
RSVD_75 Y34
F33 RSVD_76
+1.05VS_VCCSTG_OUT_LGC G33 VCCSTG_OUT_1
VCCSTG_OUT_2 CD2
E5 VCCPLL +1.2V_VCCPLL_OC
VCCSTG_OUT_LGC CG38
VCCPLL_OC_1 CG41
VCCPLL_OC_2 CG42 +1.05V_VCCIO_OUT
VCCPLL_OC_3 CG49
VCCPLL_OC_4
AD7
13 of 19 VCCIO_OUT
C C
ICL-U_BGA1526
@
+1.05VO_OUT_FET
VCCST
1U_0201_6.3V6M
Imax : 0.445 A 1
CC314
PREM@
For Power consumption UC9
Measurement 1 PREM@
+5VALW
2 2 VIN1
VIN2
RC3989 +1.05V_VCCST +1.8VALW _PRIM TO +1.8V_PRIM_SOC
PREM@ 0_0805_5%
CC315 7 6 +1.05V_VCCST_SINGLE 1 2
0.1U_0201_10V6K VIN thermal VOUT +1.8V_PRIM_SOC Imax : 0.7 A
2 1 3 1
VBIAS CC316
1 2 VCCST_EN_LS_R 4 5 0.1U_0201_10V6K
<11> VCCST_EN_LS ON GND
RC412 1
2
1U_0201_6.3V6M
0_0402_5% 1 CC355
CC317
PREM@
EM5201V_DFN8_3X3 4.7U_0402_6.3V6M
SA00008R600 2
2
I (Max) : 0.455 A(+1.05V_VCCST)
RDS(Typ) : 3.5 mohm
V drop : 0.0016V +1.05V_VCCST_P +1.05V_VCCST
Imax : 0.445 A
RC414 1 VOL@ 2 0_0805_5%

+1.2V_VDDQ TO +1.2V_VCCPLL_OC
B B
+1.05VS_VCCSTG Imax : 0.152 A
RC413 1 VOL@ 2 0_0603_5%

Imax : 0.119 A
+1.05V_VCCST_DUAL RC3981 1 PREM@ 2 0_0603_5%
+1.05V_VCCST (PCH to CPU)

+5VALW
For VOL@ +1.05V_VCCST_P

Place on opposite of CPU Side
Place on CPU Side
1U_0201_6.3V6M
1 JPC16
+1.05V_VCCST_DUAL 1
JUMP@
2 1uF* 6 + 1uF*3 reserve
+1.05VO_OUT_FET 1 2 22uF* 2 + 22uF* 1 (Reserved)
CC24
10uF* 2
0.1U_0201_10V6K
CC375 @
JUMP_43X39 1
2 UC14
1 14 +1.2V_VDDQ +1.2V_VDDQ +1.2V_VDDQ
2 VIN1 VOUT1 13
VCCSTG_EN_LS RC3983 1 PREM@ 2 0_0402_5% VIN1 VOUT1 2
<15> VCCSTG_EN_LS VCCST_EN_LS_R RC3980 1 VOL@ 2 0_0402_5% 3 12 1 2
ON1 CT1
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
RC3979 1 @ 2 0_0402_5% CC374
22U_0603_6.3V6K
22U_0603_6.3V6K
22U_0603_6.3V6K
10U_0402_6.3V6M
10U_0402_6.3V6M
CC289
CC290
CC291
CC292
CC293
CC294
CC295
CC296
CC297
4 11 8200P_0402_25V7K 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VBIAS GND
CC189
CC190
CC191
CC235
CC236
RC135 1 2 0_0402_5% EN_1.8VS 5 10 1 2 @
<15,58,78,84,86> SUSP# ON2 CT2 CC27
2 2 2 2 2 2 2 2 2 2 2 2 2 2
@
A 1 6 9 1000P_0402_50V7K A
7 VIN2 VOUT2 8
+1.8VALW_PRIM VIN2 VOUT2
CC378
0.1U_0201_10V6K 15 +1.8VS
@ 2 GPAD
JW7110DFNC_DFN14_2X3
+1.8VS_R RC136 1 2 0_0402_5%
SA0000BEL00
+1.8VALW TO +1.8VS
0.1U_0201_10V6K
CC28 @
1
2 Issued Date 2019/04/12 Deciphered Date 2020/04/12 Title
Size
ICL-U(10/13)Power
Document Number Rev
1.0
5 4 3 2 1
5 4 3 2 1
+3VALW +3VALW_PRIM
JPC7 +1.8VALW_PRIM LC15 @ +1.8V_VCCA_CLKLDO
1 2
1 2 1 2
JUMP_43X39
@ 0.6UH_TMPC0412HP-R60MG-Z02_6A_20%
SH000019M00
+3VALW +3VALW_DSW RC248 needs stuff 100 ohm when stuff LC15
2
RC246 1 2
CC365 near DE31 0_0402_5% RC248 1
2 1 1 2 0_0402_5% CC298
RC173 0_0402_5% 1U_0201_6.3V6M
1U_0201_6.3V6M @
1
@ 2
D D
1 1
CC36 CC246
22U_0603_6.3V6K 22U_0603_6.3V6K
2 2
use 22u x2 to replace 47ux1
26000 mA 202 mA (Include UC1.DC33)

+VCCIN_AUX UC1N +3VALW_PRIM LC2
SD028000080
+3VALW AH1
AW10 VCCIN_AUX_1
CPU POWER 3 OF 3
VCCPRIM_3P3_2
DF23
DG26 RF
0_0402_5%
AY11 VCCIN_AUX_2 VCCPRIM_3P3_3 DG28

AY9 VCCIN_AUX_3 VCCPRIM_3P3_4 +3VALW_HDA
1354mA VCCIN_AUX_4 1300 mA (Include UC1.DD35) +3VALW_PRIM
BA10 +1.8VALW_PRIM
+3VALW_PRIM BB9 VCCIN_AUX_5
CH1 VCCIN_AUX_6 DF15 LC2 @RF@
CK11 VCCIN_AUX_7 VCCPRIM_1P8_2 DF17 1 2
CL10 VCCIN_AUX_8 VCCPRIM_1P8_3 DF18 BLM15BB221SN1D_2P_0402
1 VCCIN_AUX_9 VCCPRIM_1P8_4
CC106 CM11 DF20 SM01000BV00 1
4.7U_0402_6.3V6M CN1 VCCIN_AUX_10 VCCPRIM_1P8_5 DG17 CC76
AJ1 VCCIN_AUX_11 VCCPRIM_1P8_6 DG18 0.1U_0201_10V6K
2 CN10 VCCIN_AUX_12 VCCPRIM_1P8_7 DG20 @RF@
CP11 VCCIN_AUX_13 VCCPRIM_1P8_8 DF34 2
CR10 VCCIN_AUX_14 VCCPRIM_1P8_9
CT11 VCCIN_AUX_15
C CU10 VCCIN_AUX_16 C
CV1 VCCIN_AUX_17 +0.85VO_VCCLDOSTD
CV11 VCCIN_AUX_18 RF request
VCCIN_AUX_19 165 mA
CW10 DW37 +1.8V_VCCA_CLKLDO
CY11 VCCIN_AUX_20 VCCLDOSTD_0P85 +1.24VO_VCCDPHY
DC1 VCCIN_AUX_21 DW15
AL1 VCCIN_AUX_22 VCCA_CLKLDO_1P8 +1.05VO_VCCDSW
P13 VCCIN_AUX_23 DW32
R12 VCCIN_AUX_24 VCCDPHY_1P24 +1.05VO_OUT_FET
T13 VCCIN_AUX_25 DD34
U12 VCCIN_AUX_26 VCCDSW_1P05
DC11 VCCIN_AUX_27 BY2 +1.05VO_VCCPLL
DE12 VCCIN_AUX_28 VCC1P05_1 CB2
DF12 VCCIN_AUX_29 VCC1P05_2 CC1 +1.05VO_OUT_PCH
500 mA 500 mA VCCIN_AUX_30 VCC1P05_3
AM1
+3VALW_PRIM AN1 VCCIN_AUX_31 CD1
100K_0402_5%
100K_0402_5%
AT11 VCCIN_AUX_32 VCCPLL

VCCIN_AUX_33
1
AT9 DG31
+1.8VALW_PRIM AU10 VCCIN_AUX_34 VCCPRIM_1P05_1
@ @ AV9 VCCIN_AUX_35 DG29
R3054
R3053
VCCIN_AUX_36 VCCPRIM_1P05_2 2 mA
+RTCVCC
BF9 DF29
<91> VCC_SENSE_VCCIN_AUX
2
BD9 VCCIN_AUX_VCCSENSE VCCPRIM_1P05_3

<91> VSS_SENSE_VCCIN_AUX VCCIN_AUX_VSSSENSE
3 mA DF31 4 mA
+3VALW_PRIM VCCPRIM_1P05_4 +3VALW_DSW
DG33 5 mA
+1.05VO_EXTBYPASS DJ15 VCCRTC +3VALW_HDA
VCC_V1P05EXT_1P05 DE31
+1.05VO_VNNBYPASS CY34 VCCDSW_3P3
VCC_VNNEXT_1P05 DF26
DC33 VCCPGPPR
VCCPRIM_3P3_1 CL38 VCCIN_AUX_CORE_VID0 RC216 1 2 0_0402_5%
GPP_B0/CORE_VID0 VCCIN_AUX_CORE_VID1 VCCIN_AUX_CORE_VID0_R <11,91>
DD35 CJ38 RC217 1 2 0_0402_5%
VCCPRIM_1P8_1 GPP_B1/CORE_VID1 VCCIN_AUX_CORE_ALERT# VCCIN_AUX_CORE_VID1_R <11,58,91>
CN38 RC218 1 2 0_0402_5%
GPP_B2/VRALERT# VCCIN_AUX_CORE_ALERT#_R <7>
DB34
B VCCSPI B
NOTE: 14 of 19
Need to follow SPI ROM Voltage ICL-U_BGA1526 stuff PU on PWR side
@ NOTE: +3VALW_PRIM
572631_ICL_PCH_LP_EDS_Vol_1_Rev_1p0
VCCPGPPR: Audio Power 3.3V, 1.8V, or 1.5V
Need to sync with codec VDDIO. VCCIN_AUX_CORE_VID0_R RC512 1 @ 2 100K_0402_5%
VCCIN_AUX_CORE_VID1_R RC513 1 @ 2 100K_0402_5%
572907_ICL_UY_PDG_Rev1p1
When configured as 3.3V or 1.8V, VCCPGPPR can be merged directly with
either VCCPRIM_1P8 or VCCPRIM_3P3 depending on their operating voltage.
+1.24VO_VCCDPHY
+3VALW_PRIM
+1.05VO_VCCDSW +0.85VO_VCCLDOSTD
+1.8VALW_PRIM RTC Battery
4.7U_0402_6.3V6M
+RTCBATT
1
+RTCBATT
1U_0201_6.3V6M
1U_0201_6.3V6M
CC252
2 1 1 1 1 RH163
+RTCVCC
CC301
CC304 @
CC299 CC249 1K_0402_5% DC1

0.1U_0201_10V6K
CC254
1U_0201_6.3V6M 2.2U_0402_6.3V6M 1 2 3 JRTC1

2 1
1 2 2 2 2 1 2 1
2
@
1 1
@
2 3
+CHGRTC CC143 GND
near DG26 CC84 4
0.1U_0201_10V6K 1U_0201_6.3V6M GND
CHN202UPT_SC70-3 2 2
A near DF23 near DG20 ACES_50271-0020N-001 A
CONN@
#575412_WHL_U_PDG_R0.7 table11-11
Close to BR23 SP02000RO00

Size
ICL-U(11/13)Power
Document Number Rev
1.0
5 4 3 2 1
5 4 3 2 1
UC1O UC1P UC1Q

GND 1 OF 3 GND 2 OF 3 DJ33 GND 3 OF 3 F11
A11 AF45 BT3 CR37 DJ36 VSS_297 VSS_362 F31
A46 VSS_1 VSS_75 AF47 BT39 VSS_149 VSS_223 CR45 DJ42 VSS_298 VSS_363 F45
BA45 VSS_2 VSS_76 AG1 BT41 VSS_150 VSS_224 CR49 DK3 VSS_299 VSS_364 F47
BA47 VSS_3 VSS_77 AG11 BT42 VSS_151 VSS_225 CT37 DK4 VSS_300 VSS_365 F8
BB11 VSS_4 VSS_78 AG3 BT43 VSS_152 VSS_226 CT39 DK49 VSS_301 VSS_366 G21
BB3 VSS_5 VSS_79 AG38 BT7 VSS_153 VSS_227 CT42 DK6 VSS_302 VSS_367 G24
BB7 VSS_6 VSS_80 AG39 BU45 VSS_154 VSS_228 CT9 DK8 VSS_303 VSS_368 G3
BC37 VSS_7 VSS_81 AG41 BU47 VSS_155 VSS_229 CU45 DL10 VSS_304 VSS_369 G31
D D
BD3 VSS_8 VSS_82 A31 BV1 VSS_156 VSS_230 CU47 DL13 VSS_305 VSS_370 G36
BD38 VSS_9 VSS_83 AG42 BV11 VSS_157 VSS_231 CU49 DL44 VSS_306 VSS_371 G49
BD39 VSS_10 VSS_84 AG43 BV2 VSS_158 VSS_232 CV3 DL47 VSS_307 VSS_372 G5
BD41 VSS_11 VSS_85 AG5 BV3 VSS_159 VSS_233 CV34 DM47 VSS_308 VSS_373 H17
A48 VSS_12 VSS_86 AG9 BV7 VSS_160 VSS_234 CV35 DN15 VSS_309 VSS_374 H21
BD42 VSS_13 VSS_87 AH2 BW3 VSS_161 VSS_235 CV5 DN19 VSS_310 VSS_375 H24
BD43 VSS_14 VSS_88 AH37 BW37 VSS_162 VSS_236 CV9 DN24 VSS_311 VSS_376 H31
BD45 VSS_15 VSS_89 AH45 BW5 VSS_163 VSS_237 CY41 DN31 VSS_312 VSS_377 H33
BD49 VSS_16 VSS_90 AH49 BW6 VSS_164 VSS_238 CY45 DN36 VSS_313 VSS_378 H36
BD5 VSS_17 VSS_91 AJ2 BW7 VSS_165 VSS_239 CY49 DN42 VSS_314 VSS_379 H45
BD6 VSS_18 VSS_92 AJ3 BY37 VSS_166 VSS_240 CY9 DP45 VSS_315 VSS_380 H49
BD7 VSS_19 VSS_93 A34 BY45 VSS_167 VSS_241 D13 DR49 VSS_316 VSS_381 J10
BE1 VSS_20 VSS_94 AK37 BY49 VSS_168 VSS_242 D17 DT1 VSS_317 VSS_382 J13
BE2 VSS_21 VSS_95 AL2 C11 VSS_169 VSS_243 D31 DT10 VSS_318 VSS_383 J16
BF3 VSS_22 VSS_96 AL45 C13 VSS_170 VSS_244 D44 DT15 VSS_319 VSS_384 J36
A49 VSS_23 VSS_97 AL47 C14 VSS_171 VSS_245 D49 DT20 VSS_320 VSS_385 J6
BF45 VSS_24 VSS_98 AL6 C17 VSS_172 VSS_246 DA10 DT27 VSS_321 VSS_386 K11
BF47 VSS_25 VSS_99 AM2 C21 VSS_173 VSS_247 DA33 DT3 VSS_322 VSS_387 K33
BF7 VSS_26 VSS_100 AM37 C24 VSS_174 VSS_248 DA9 DT32 VSS_323 VSS_388 K8
BG3 VSS_27 VSS_101 AN2 C31 VSS_175 VSS_249 DB32 DT37 VSS_324 VSS_389 L36
BH37 VSS_30 VSS_104 A36 C48 VSS_178 VSS_252 DB45 DT6 VSS_327 VSS_392 L42
BJ1 VSS_31 VSS_105 AN41 C49 VSS_179 VSS_253 DB47 DT7 VSS_328 VSS_393 L43
BJ2 VSS_32 VSS_106 AN42 C6 VSS_180 VSS_254 DB49 DT8 VSS_329 VSS_394 L45
BJ3 VSS_33 VSS_107 AN43 CA3 VSS_181 VSS_255 DC3 DU1 VSS_330 VSS_395 L47
AA45 VSS_34 VSS_108 AN45 CA38 VSS_182 VSS_256 DC49 DU10 VSS_331 VSS_396 M10
BJ41 VSS_35 VSS_109 AN49 CA41 VSS_183 VSS_257 DC5 DU15 VSS_332 VSS_397 M3
C BJ43 VSS_36 VSS_110 AN6 CA42 VSS_184 VSS_258 DC6 DU2 VSS_333 VSS_398 M36 C
BJ45 VSS_37 VSS_111 AR1 CA43 VSS_185 VSS_259 DD37 DU20 VSS_334 VSS_399 M5
BJ49 VSS_38 VSS_112 AR11 CA7 VSS_186 VSS_260 DD42 DU27 VSS_335 VSS_400 N45
BJ7 VSS_39 VSS_113 AR2 CB37 VSS_187 VSS_261 DE10 DU32 VSS_336 VSS_401 N49
BM11 VSS_40 VSS_114 AR3 CB45 VSS_188 VSS_262 DE13 DU37 VSS_337 VSS_402 P11
BM3 VSS_41 VSS_115 A39 CB47 VSS_189 VSS_263 DE17 DU48 VSS_338 VSS_403 P41
BM45 VSS_42 VSS_116 AR7 CC3 VSS_190 VSS_264 DE18 DU49 VSS_339 VSS_404 P8
BM47 VSS_43 VSS_117 AR9 CC7 VSS_191 VSS_265 DE20 DU7 VSS_340 VSS_405 R3
BM5 VSS_44 VSS_118 AT3 CE37 VSS_192 VSS_266 DE22 DV2 VSS_341 VSS_406 R37
AA47 VSS_45 VSS_119 AT45 CE45 VSS_193 VSS_267 DE23 DV44 VSS_342 VSS_407 T11
BM6 VSS_46 VSS_120 AT47 CE49 VSS_194 VSS_268 DE26 DV48 VSS_343 VSS_408 T36
BM7 VSS_47 VSS_121 AT5 CE9 VSS_195 VSS_269 DE28 DV8 VSS_344 VSS_409 T41
BP1 VSS_48 VSS_122 AT6 CG37 VSS_196 VSS_270 DE29 DW1 VSS_345 VSS_410 T43
BP2 VSS_49 VSS_123 AT7 CG39 VSS_197 VSS_271 DE33 DW10 VSS_346 VSS_411 T45
BP3 VSS_50 VSS_124 AU37 CG43 VSS_198 VSS_272 DE45 DW2 VSS_347 VSS_412 T47
BP43 VSS_51 VSS_125 AV11 CG45 VSS_199 VSS_273 DE6 DW20 VSS_348 VSS_413 U3
BP7 VSS_52 VSS_126 A42 CG47 VSS_200 VSS_274 DF13 DW27 VSS_349 VSS_414 U37
BR45 VSS_53 VSS_127 AV3 CG9 VSS_201 VSS_275 DF22 DW44 VSS_350 VSS_415 U5
BR49 VSS_54 VSS_128 AV38 CH3 VSS_202 VSS_276 DF28 DW46 VSS_351 VSS_416 V11
AB11 VSS_55 VSS_129 AV39 CH5 VSS_203 VSS_277 DF33 DW48 VSS_352 VSS_417 V36
AB3 VSS_56 VSS_130 AV41 CJ37 VSS_204 VSS_278 DF35 DW49 VSS_353 VSS_418 V45
AB38 VSS_57 VSS_131 AV42 CJ42 VSS_205 VSS_279 DF39 DW7 VSS_354 VSS_419 V49
AB39 VSS_58 VSS_132 AV43 CJ9 VSS_206 VSS_280 DG10 E11 VSS_355 VSS_420 V9
AB41 VSS_59 VSS_133 AV45 CK45 VSS_207 VSS_281 DG12 E34 VSS_356 VSS_421 W37
A17 VSS_60 VSS_134 AV49 CK49 VSS_208 VSS_282 DG13 E36 VSS_357 VSS_422 Y36
AB42 VSS_61 VSS_135 AV7 CK9 VSS_209 VSS_283 DG15 E39 VSS_358 VSS_423 Y38
AB43 VSS_62 VSS_136 AY3 CL37 VSS_210 VSS_284 DG22 E42 VSS_359 VSS_424 Y43
AB5 VSS_63 VSS_137 A44 CL42 VSS_211 VSS_285 DG23 E6 VSS_360 VSS_425 Y9
AB6 VSS_64 VSS_138 AY7 CL49 VSS_212 VSS_286 DG47 VSS_361 VSS_426 DE15
B AC45 VSS_65 VSS_139 B17 CM45 VSS_213 VSS_287 DG6 VSS_427 B
AC49 VSS_66 VSS_140 B2 CM47 VSS_214 VSS_288 DH1 17 of 19
AD10 VSS_67 VSS_141 B21 CM9 VSS_215 VSS_289 DH3 ICL-U_BGA1526
AD11 VSS_68 VSS_142 B24 CN3 VSS_216 VSS_290 DH45
VSS_69 VSS_143 VSS_217 VSS_291 @
AD34 B3 CN37 DH5
AD37 VSS_70 VSS_144 B31 CN39 VSS_218 VSS_292 DJ19
A3 VSS_71 VSS_145 B48 CN5 VSS_219 VSS_293 DJ21
AE6 VSS_72 VSS_146 BA1 CP9 VSS_220 VSS_294 DJ27
AF37 VSS_73 VSS_147 BA2 CR32 VSS_221 VSS_295 DJ31
VSS_74 VSS_148 VSS_222 VSS_296
15 of 19 16 of 19
ICL-U_BGA1526 ICL-U_BGA1526
@ @
A A

ICL-U(12/13)GND
5 4 3 2 1
5 4 3 2 1
+1.05V_VCCIO_OUT UC1S
RC3992 1 2 1K_0402_5% CFG0 AG6 RESERVED SIGNALS A47

RC3993 1 2 1K_0402_5% CFG1 AE7 CFG_0 RSVD_TP_1 B47
AG7 CFG_1 RSVD_TP_2
RC3994 1 @ 2 1K_0402_5% CFG3 AD9 CFG_2 C1
CFG4 AE9 CFG_3 RSVD_57 E1
PDG NC this pin AB9 CFG_4 RSVD_58
AJ6 CFG_5 CT32
AB7 CFG_6 RSVD_TP_10 CV32
RC3995 1 2 1K_0402_5% CFG8 V10 CFG_7 RSVD_TP_11
RC3996 1 2 1K_0402_5% CFG9 AJ5 CFG_8 G15
RC3997 1 2 1K_0402_5% CFG10 Y10 CFG_9 RSVD_79 F15
AJ7 CFG_10 RSVD_80
D D
RC3998 1 2 1K_0402_5% CFG12 AB10 CFG_11 BW11
RC3999 1 2 1K_0402_5% CFG13 AL7 CFG_12 RSVD_TP_5 CA11
AL9 CFG_13 RSVD_TP_6
AJ9 CFG_14 C16
CFG_15 VSS_428 A16
CFG16 V6 VSS_429
V7 CFG_16 C2
CFG_17 RSVD_55 A4
CFG18 Y6 RSVD_56
Y7 CFG_18 DP5
CFG_19 RSVD_65 DR5
CFG_RCOMP AD6 RSVD_66
CFG_RCOMP D14
RSVD_59
1
T494 TP@ 1 BPM#0 T9 E16
RC210 1 BPM#1 T7 BPM#0 RSVD_60
T495 TP@ BPM#1
49.9_0402_1% T291 TP@ 1 BPM#2 T10 DV6
1 BPM#3 T6 BPM#2 RSVD_TP_13 DW6
T290 TP@ BPM#3 RSVD_TP_14
2
BJ11 DP2
BL10 RSVD_62 RSVD_TP_24 DP1
RVP To MIPI60 RSVD_63 RSVD_TP_25
RC344 1 2 1K_0402_5% CFG4
AV1 DW4
RC341 1 2 51_0402_5% CFG16 RSVD_TP_17 RSVD_TP_15 DV4
AT2 RSVD_TP_16
RC342 1 2 51_0402_5% CFG18 AT1 RSVD_TP_18 CM33
AU1 RSVD_TP_20 TP_3 DB10
AU2 RSVD_TP_19 TP_4
RSVD_TP_21 R1
AV2 RSVD_TP_12
C CFG4 RSVD_TP_22
C
Display port presence strap DW3
DP3 RSVD_TP_7 DV3
0 : Enable RSVD_67 RSVD_TP_8
An external display port device is connected to DT2
RSVD_68 DH49
the embedded displayport AR10 RSVD_TP_9
1 : Disable AP10 RSVD_69 DL8
No physical display port attached to embedded display port BP36 RSVD_71 RSVD_TP_23
BM36 RSVD_70 DW47
RSVD_72 TP_1 DV47
J15 TP_2 DU47
K15 VSS_430 VSS_432
VSS_431 P10
1SKTOCC# C5 RSVD_TP_26
T288 TP@ SKTOCC#
T289 TP@ 1PROC_SELECT# D4
A5 RSVD_77
RSVD_64 19 of 19
ICL-U_BGA1526
@
UC1R
N34 DA11
AK10 RSVD_TP_28 RESERVED SIGNALS RSVD_TP_35 CL32
BT36 RSVD_TP_29 RSVD_TP_36 CN32
AH10 RSVD_7 RSVD_TP_37 CY35
BC10 RSVD_TP_30 RSVD_32 DB37
CH33 RSVD_TP_31 RSVD_33 DF37
RSVD_TP_32 RSVD_34
CJ32 BF11
AM10 RSVD_12 IST_TP_0 BD11
B BH10 RSVD_TP_33 IST_TP_1 BE10 B
J34 RSVD_TP_34 IST_TRIG_0 BF10
RSVD_TP_27 IST_TRIG_1
Y11 CW33
L34 RSVD_9 PCH_IST_TP_0 CY32
RSVD_10 PCH_IST_TP_1
AJ11 CY37
CG32 RSVD_17 RSVD_27 CV37
RSVD_21 RSVD_28
CK33
BP41 RSVD_22 G34
AL11 RSVD_20 RSVD_35 H34
BG11 RSVD_23 RSVD_46 DJ34
AN11 RSVD_24 RSVD_48 DK31
M13 RSVD_16 RSVD_49 DK15
M34 RSVD_18 RSVD_50 CP3
RSVD_19 RSVD_51 CP5
RSVD_52 AN9
RSVD_53 AN7
RSVD_54 AF10
DU42 RSVD_36 AE11
DW42 RSVD_42 RSVD_37 H5
D33 RSVD_43 RSVD_38 D1
L13 RSVD_44 RSVD_39 DJ40
K13 RSVD_45 RSVD_40 DK40
RSVD_47 RSVD_41
A A
ICL-U_BGA1526
@

ICL-U(13/13)RSVD,CFG
5 4 3 2 1
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
<8> DDR_A_DQS#[0..7]
JDIMM2A
<8> DDR_A_D[0..63]
DDR_A_CLK0
DDR_A_CLK#0
137
139 CK0(T)
CK0#(C)
STD
DQ0
DQ1
8
7
DDR_A_D61
DDR_A_D62 Standard Type
DDR_A_CLK1 138 20 DDR_A_D56
<8> DDR_A_DQS[0..7] DDR_A_CLK#1 140 CK1(T) DQ2 21 DDR_A_D57
CK1#(C) DQ3 4 DDR_A_D60 2-3A to 1 DIMMs/channel
DDR_A_CKE0 109 DQ4 3 DDR_A_D58
<8> DDR_A_MA[0..16] DDR_A_CKE1 110 CKE0 DQ5 16 DDR_A_D63
DDR_A_BA0 +3VS CKE1 DQ6 17 DDR_A_D59
<8> DDR_A_BA0 DDR_A_BA1 DDR_A_CS#0 149 DQ7 13 DDR_A_DQS7
<8> DDR_A_BA1 DDR_A_BG0 DDR_A_CS#1 157 S0# DQS0(T) 11 DDR_A_DQS#7
<8> DDR_A_BG0 DDR_A_BG1 162 S1# DQS0#(C) +1.2V_VDDQ +1.2V_VDDQ
1 <8> DDR_A_BG1 DDR_A_ACT# 165 S2#/C0 28 DDR_A_D44 1
JDIMM2B
<8> DDR_A_ACT# S3#/C1 DQ8
1
DDR_A_ALERT# @ @ 29 DDR_A_D40 STD
<8> DDR_A_ALERT# DDR_A_PAR DDR_A_ODT0 155 DQ9 41 DDR_A_D47 111 141
RD243 RD52 RD242
<8> DDR_A_PAR DDR_A_ODT1 161 ODT0 DQ10 42 DDR_A_D45 112 VDD1 VDD11 142
0_0402_5% 0_0402_5% 0_0402_5%
ODT1 DQ11 24 DDR_A_D41 117 VDD2 VDD12 147
DDR_A_BG0 115 DQ12 25 DDR_A_D42 118 VDD3 VDD13 148
2
DDR_A_CLK0 DDR_A_BG1 113 BG0 DQ13 38 DDR_A_D43 +1.2V_VDDQ 123 VDD4 VDD14 153
<8> DDR_A_CLK0 DDR_A_CLK#0 DDR_A_SA2 DDR_A_BA0 150 BG1 DQ14 37 DDR_A_D46 124 VDD5 VDD15 154
<8> DDR_A_CLK#0 DDR_A_CLK1 DDR_A_SA1 DDR_A_BA1 145 BA0 DQ15 34 DDR_A_DQS5 +0.6V_A_VREFCA 129 VDD6 VDD16 159
<8> DDR_A_CLK1 BA1 DQS1(T) VDD7 VDD17
1
DDR_A_CLK#1 DDR_A_SA0 32 DDR_A_DQS#5 130 160
<8> DDR_A_CLK#1 DDR_A_MA0 144 DQS1#(C) RD46 135 VDD8 VDD18 163
A0 VDD9 VDD19
1
@ DDR_A_MA1 133 50 DDR_A_D54 1K_0402_1% 136
DDR_A_CKE0 RD54 RD241 RD56 DDR_A_MA2 132 A1 DQ16 49 DDR_A_D53 +0.6V_DDRA_VREFCA VDD10
<8> DDR_A_CKE0 DDR_A_CKE1 0_0402_5% 0_0402_5% 0_0402_5% DDR_A_MA3 131 A2 DQ17 62 DDR_A_D50 Data swap 12/12 255 258
RD49 +3VS +0.6VS_VTT
<8> DDR_A_CKE1
2
DDR_A_CS#0 DDR_A_MA4 128 A3 DQ18 63 DDR_A_D48 VDDSPD VTT
<8> DDR_A_CS#0 DDR_A_CS#1 DDR_A_MA5 A4 DQ19 DDR_A_D55
2_0402_1% 20mils
126 46 2 1 164 257
<8> DDR_A_CS#1 +2.5V
2
DDR_A_MA6 127 A5 DQ20 45 DDR_A_D51 VREFCA VPP1 259
A6 DQ21 1 VPP2
DDR_A_MA7 122 58 DDR_A_D52
SOC_SMBDATA_1 DDR_A_MA8 125 A7 DQ22 59 DDR_A_D49 CD66 1 99
<9,66> SOC_SMBDATA_1 A8 DQ23 1 VSS VSS
1
SOC_SMBCLK_1 DDR_A_MA9 121 55 DDR_A_DQS6 0.022U_0402_16V7K 2 102
<9,66> SOC_SMBCLK_1 DDR_A_MA10 146 A9 DQS2(T) 53 DDR_A_DQS#6 2 5 VSS VSS 103
RD47 CD65
DDR_A_MA11 120 A10_AP DQS2#(C) 1K_0402_1% 0.1U_0201_10V6K 6 VSS VSS 106
A11 VSS VSS
1
DDR_A_ODT0 DDR_A_MA12 119 70 DDR_A_D33 2 9 107
<8> DDR_A_ODT0 DDR_A_ODT1 DDR_A_MA13 158 A12 DQ24 71 DDR_A_D38 10 VSS VSS 167
RD50
<8> DDR_A_ODT1
2
DDR_A_MA14 151 A13 DQ25 83 DDR_A_D35 14 VSS VSS 168
A14_WE# DQ26 24.9_0402_1% VSS VSS
DDR_A_MA15 156 84 DDR_A_D32 15 171
DDR_A_MA16 152 A15_CAS# DQ27 66 DDR_A_D39 18 VSS VSS 172
2
A16_RAS# DQ28 67 DDR_A_D37 19 VSS VSS 175
DDR_A_ACT# 114 DQ29 79 DDR_A_D34 22 VSS VSS 176
ACT# DQ30 80 DDR_A_D36 23 VSS VSS 180
DDR_A_PAR 143 DQ31 76 DDR_A_DQS4 26 VSS VSS 181
DDR_A_ALERT# 116 PARITY DQS3(T) 74 DDR_A_DQS#4 27 VSS VSS 184
Layout Note:
2
Place near JDIMM2 +1.2V_VDDQ RD63 2 1 240_0402_1% DDR_A_EVENT# 134
DDR_DRAMRST# 108
ALERT#
EVENT#
DQS3#(C)
DDR_A_D19
Place near to SO-DIMM connector. 30 VSS
VSS
VSS
VSS
185 2
174 31 188
<8,24> DDR_DRAMRST# RESET# DQ32 173 DDR_A_D23 35 VSS VSS 189
RD1 1 @ 2 470_0402_5% DQ33 187 DDR_A_D18 36 VSS VSS 192
+1.2V_VDDQ SOC_SMBDATA_1 254 DQ34 DDR_A_D17 VSS VSS
186 39 193
CD30 2 1 .1U_0402_16V7K SOC_SMBCLK_1 253 SDA DQ35 170 DDR_A_D21 40 VSS VSS 196
@EMC@ SCL DQ36 169 DDR_A_D22 43 VSS VSS 197
+1.2V_VDDQ DDR_A_SA2 166 DQ37 183 DDR_A_D16 44 VSS VSS 201
DDR_A_SA1 260 SA2 DQ38 182 DDR_A_D20 47 VSS VSS 202
DDR_A_SA0 256 SA1 DQ39 179 DDR_A_DQS2 48 VSS VSS 205
SA0 DQS4(T) DDR_A_DQS#2 VSS VSS
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
177 51 206
DQS4#(C) 52 VSS VSS 209
1 1 1 1 1 1 1 1 VSS VSS
DDR_A_D5
CD32
CD33
CD34
CD35
CD36
CD37
CD69
CD70
92 195 56 210
91 CB0_NC DQ40 194 DDR_A_D6 57 VSS VSS 213
2 2 2 2 2 2 2 2 105 CB2_NC DQ42 208 DDR_A_D0 61 VSS VSS 217
RD61 2 1 240_0402_1% DDR_A_DQS8 97 CB7_NC DQ47 200 DDR_A_DQS0 72 VSS VSS 227
+1.2V_VDDQ DDR_A_DQS#8 DQS8(T) DQS5(T) DDR_A_DQS#0 VSS VSS
RD62 2 1 240_0402_1% 95 198 73 230
DQS8#(C) DQS5#(C) 77 VSS VSS 231
+1.2V_VDDQ 216 DDR_A_D26 78 VSS VSS 234
12 DQ48 215 DDR_A_D28 81 VSS VSS 235
+1.2V_VDDQ DM0#/DBI0# DQ49 DDR_A_D29 VSS VSS
33 228 82 238
54 DM1#/DBI1# DQ50 229 DDR_A_D31 85 VSS VSS 239
DM3#/DBI3# DQ52 DDR_A_D24 VSS VSS
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
178 212 89 244

DM5#/DBI5# DQ54 VSS VSS
1
DDR_A_D30
CD38
CD39
CD40
CD41
CD42
CD43
CD44
CD45
220 225 93 248

241 DM6#/DBI6# DQ55 221 DDR_A_DQS3 94 VSS VSS 251
3 96 DM7#/DBI7# DQS6(T) 219 DDR_A_DQS#3 98 VSS VSS 252 3
2
DM8#/DBI8# DQS6#(C) VSS VSS

VDDQ
262 261
1uF*8 GND GND
10uF*8 237 DDR_A_D12
DQ56 DDR_A_D10
330uF*1 DQ57
236 FOX_AS0A821-H4SB-7H
249 DDR_A_D14 CONN@
DQ58 250 DDR_A_D13
DQ59 SP07001GA00
232 DDR_A_D8
DQ60 233 DDR_A_D9
+1.2V_VDDQ DQ61 245 DDR_A_D15
DQ62 246 DDR_A_D11
DQ63 DDR_A_DQS1
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
242
DQS7(T) 240 DDR_A_DQS#1
1@
1@
1 1 DQS7#(C)
CD258
CD259
CD260
CD261
Layout Note:
Place near JDIMM1.258
2
2 2 FOX_AS0A821-H4SB-7H
CONN@
SP07001GA00
VTT
Compatible with SP07001HW00 1uF*2
Reserved for cap downsize +0.6VS_VTT
Layout Note: 10uF*1
Place near JDIMM2.255
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
Layout Note:
Place near JDIMM1.257,259 1 1
1
CD257
CD64
CD62
CD63
2
2
+3VS 2 2
4
+2.5V VPP VDDSPD 4
1uF*1 0.1uF*1
10uF*1 2.2uF*1
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
0.1U_0201_10V6K
2.2U_0402_6.3V6M
add 1 cap for MLCC downsize
1 1
1
1
CD240
CD68
CD67
CD55
CD239

2
2 2
DDR4_DIMMA
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
add 1 cap for MLCC downsize Date: Tuesday, October 15, 2019 Sheet 23 of 102
A B C D E
5 4 3 2 1
+DDR_VREF_CA +DDR_VREF_CA
+DDR_VREF_CA +DDR_VREF_CA
U2 U3
U4 U5
M1 G2 DDR_B_D29 M1 G2 DDR_B_D22
VREFCA DQL0 VREFCA DQL0
0.047U_0402_25V7K
0.047U_0402_25V7K
F7 DDR_B_D28 F7 DDR_B_D23 M1 G2 DDR_B_D37 M1 G2 DDR_B_D50
DQL1 DQL1 VREFCA DQL0 VREFCA DQL0
0.047U_0402_25V7K
0.047U_0402_25V7K
H3 DDR_B_D25 H3 DDR_B_D17 F7 DDR_B_D33 F7 DDR_B_D51
DDR_B_MA0 P3 DQL2 H7 DDR_B_D27 DDR_B_MA0 P3 DQL2 H7 DDR_B_D20 DQL1 H3 DDR_B_D35 DQL1 H3 DDR_B_D48
A0 DQL3 A0 DQL3 DQL2 DQL2
1
DDR_B_MA1 P7 H2 DDR_B_D30 DDR_B_MA1 P7 H2 DDR_B_D16 DDR_B_MA0 P3 H7 DDR_B_D34 DDR_B_MA0 P3 H7 DDR_B_D55
CD124
CD125
A1 DQL4 A1 DQL4 A0 DQL3 A0 DQL3
1
DDR_B_MA2 R3 H8 DDR_B_D26 DDR_B_MA2 R3 H8 DDR_B_D18 DDR_B_MA1 P7 H2 DDR_B_D39 DDR_B_MA1 P7 H2 DDR_B_D52
CD126
CD127
DDR_B_MA3 N7 A2 DQL5 J3 DDR_B_D24 DDR_B_MA3 N7 A2 DQL5 J3 DDR_B_D21 DDR_B_MA2 R3 A1 DQL4 H8 DDR_B_D32 DDR_B_MA2 R3 A1 DQL4 H8 DDR_B_D54
2
MEM@ DDR_B_MA4 N3 A3 DQL6 J7 DDR_B_D31 MEM@ DDR_B_MA4 N3 A3 DQL6 J7 DDR_B_D19 DDR_B_MA3 N7 A2 DQL5 J3 DDR_B_D38 DDR_B_MA3 N7 A2 DQL5 J3 DDR_B_D53
2
DDR_B_MA5 P8 A4 DQL7 DDR_B_MA5 P8 A4 DQL7 MEM@ DDR_B_MA4 N3 A3 DQL6 J7 DDR_B_D36 MEM@ DDR_B_MA4 N3 A3 DQL6 J7 DDR_B_D49
DDR_B_MA6 P2 A5 DDR_B_MA6 P2 A5 DDR_B_MA5 P8 A4 DQL7 DDR_B_MA5 P8 A4 DQL7
DDR_B_MA7 R8 A6 A3 DDR_B_D13 DDR_B_MA7 R8 A6 A3 DDR_B_D3 DDR_B_MA6 P2 A5 DDR_B_MA6 P2 A5
DDR_B_MA8 R2 A7 DQU0 B8 DDR_B_D9 DDR_B_MA8 R2 A7 DQU0 B8 DDR_B_D2 DDR_B_MA7 R8 A6 A3 DDR_B_D41 DDR_B_MA7 R8 A6 A3 DDR_B_D57
D A8 DQU1 A8 DQU1 A7 DQU0 A7 DQU0 D
DDR_B_MA9 R7 C3 DDR_B_D10 DDR_B_MA9 R7 C3 DDR_B_D6 DDR_B_MA8 R2 B8 DDR_B_D44 DDR_B_MA8 R2 B8 DDR_B_D60
DDR_B_MA10 M3 A9 DQU2 C7 DDR_B_D11 DDR_B_MA10 M3 A9 DQU2 C7 DDR_B_D4 DDR_B_MA9 R7 A8 DQU1 C3 DDR_B_D43 DDR_B_MA9 R7 A8 DQU1 C3 DDR_B_D62
DDR_B_MA11 T2 A10/AP DQU3 C2 DDR_B_D8 DDR_B_MA11 T2 A10/AP DQU3 C2 DDR_B_D5 DDR_B_MA10 M3 A9 DQU2 C7 DDR_B_D47 DDR_B_MA10 M3 A9 DQU2 C7 DDR_B_D56
DDR_B_MA12 M7 A11 DQU4 C8 DDR_B_D12 DDR_B_MA12 M7 A11 DQU4 C8 DDR_B_D0 DDR_B_MA11 T2 A10/AP DQU3 C2 DDR_B_D42 DDR_B_MA11 T2 A10/AP DQU3 C2 DDR_B_D61
DDR_B_MA13 T8 A12/BC DQU5 D3 DDR_B_D15 DDR_B_MA13 T8 A12/BC DQU5 D3 DDR_B_D7 DDR_B_MA12 M7 A11 DQU4 C8 DDR_B_D40 DDR_B_MA12 M7 A11 DQU4 C8 DDR_B_D59
DDR_B_MA14 L2 A13 DQU6 D7 DDR_B_D14 DDR_B_MA14 L2 A13 DQU6 D7 DDR_B_D1 DDR_B_MA13 T8 A12/BC DQU5 D3 DDR_B_D46 DDR_B_MA13 T8 A12/BC DQU5 D3 DDR_B_D63
A14/WE DQU7 A14/WE DQU7 DDR_B_MA14 L2 A13 DQU6 D7 DDR_B_D45 DDR_B_MA14 L2 A13 DQU6 D7 DDR_B_D58
DDR_B_BA0 N2 DDR_B_BA0 N2 A14/WE DQU7 A14/WE DQU7
<8> DDR_B_BA0 DDR_B_BA1 BA0 DDR_B_BA1 BA0 DDR_B_BA0 DDR_B_BA0
<8> DDR_B_BA1 N8 B3 +1.2V_VDDQ N8 B3 +1.2V_VDDQ N2 N2 +1.2V_VDDQ
BA1 VDD B9 BA1 VDD B9 DDR_B_BA1 N8 BA0 B3 DDR_B_BA1 N8 BA0 B3
VDD VDD BA1 VDD +1.2V_VDDQ BA1 VDD
+1.2V_VDDQ E2 D1 +1.2V_VDDQ E2 D1 B9 B9
E7 DMU/DBIU VDD G7 E7 DMU/DBIU VDD G7 E2 VDD D1 E2 VDD D1
DML/DBIL VDD DML/DBIL VDD +1.2V_VDDQ DMU/DBIU VDD +1.2V_VDDQ DMU/DBIU VDD
J1 J1 E7 G7 E7 G7
VDD J9 VDD J9 DML/DBIL VDD J1 DML/DBIL VDD J1
VDD L1 VDD L1 VDD J9 VDD J9
DDR_B_CLK0 K7 VDD L9 DDR_B_CLK0 K7 VDD L9 VDD L1 VDD L1
<8> DDR_B_CLK0 DDR_B_CLK#0 CK_t VDD DDR_B_CLK#0 CK_t VDD DDR_B_CLK0 VDD DDR_B_CLK0 VDD
<8> DDR_B_CLK#0 K8 R1 K8 R1 K7 L9 K7 L9
DDR_B_CKE0 K2 CK_c VDD T9 DDR_B_CKE0 K2 CK_c VDD T9 DDR_B_CLK#0 K8 CK_t VDD R1 DDR_B_CLK#0 K8 CK_t VDD R1
<8> DDR_B_CKE0 CKE VDD CKE VDD DDR_B_CKE0 CK_c VDD DDR_B_CKE0 CK_c VDD
K2 T9 K2 T9
CKE VDD CKE VDD
A1 A1
VDDQ A9 VDDQ A9 A1 A1
VDDQ C1 VDDQ C1 VDDQ A9 VDDQ A9
VDDQ D9 VDDQ D9 VDDQ C1 VDDQ C1
VDDQ F2 VDDQ F2 VDDQ D9 VDDQ D9
VDDQ F8 VDDQ F8 VDDQ F2 VDDQ F2
DDR_B_ODT0 K3 VDDQ G1 DDR_B_ODT0 K3 VDDQ G1 VDDQ F8 VDDQ F8
<8> DDR_B_ODT0 DDR_B_CS#0 ODT VDDQ DDR_B_CS#0 ODT VDDQ DDR_B_ODT0 VDDQ DDR_B_ODT0 VDDQ
<8> DDR_B_CS#0 L7 G9 L7 G9 K3 G1 K3 G1
DDR_B_MA16 L8 CS VDDQ J2 DDR_B_MA16 L8 CS VDDQ J2 DDR_B_CS#0 L7 ODT VDDQ G9 DDR_B_CS#0 L7 ODT VDDQ G9
DDR_B_MA15 M8 RAS VDDQ J8 DDR_B_MA15 M8 RAS VDDQ J8 DDR_B_MA16 L8 CS VDDQ J2 DDR_B_MA16 L8 CS VDDQ J2
CAS VDDQ CAS VDDQ DDR_B_MA15 M8 RAS VDDQ J8 DDR_B_MA15 M8 RAS VDDQ J8
B2 RD206 B2 RD207 CAS VDDQ CAS VDDQ
VSS 10mils VSS 10mils
E1 240_0402_1% E1 240_0402_1% B2 10mils RD208 B2 10mils
VSS E9 VSS_E9_U2 1 DDP@ 2 VSS E9 VSS_E9_U3 1 DDP@ 2 VSS E1 240_0402_1% VSS E1
VSS G8 VSS G8 VSS E9 VSS_E9_U4 1 DDP@ 2 VSS E9 VSS_E9_U5
DDR_B_DQS#1 A7 VSS K1 RD79 DDR_B_DQS#0 A7 VSS K1 VSS G8 VSS G8
DDR_B_DQS1 DQSU_c VSS 10mils DDR_B_DQS0 DQSU_c VSS 10mils DDR_B_DQS#5 VSS DDR_B_DQS#7 VSS
B7 K9 0_0402_5% B7 K9 A7 K1 10mils A7 K1 DDP@
DDR_B_DQS#3 F3 DQSU_t VSS M9 DDR_B_BG1_R 1 SDP@ 2 DDR_B_DQS#2 F3 DQSU_t VSS M9 DDR_B_BG1_R DDR_B_DQS5 B7 DQSU_c VSS K9 DDR_B_DQS7 B7 DQSU_c VSS K9
DQSL_c VSS DQSL_c VSS DQSU_t VSS DQSU_t VSS
1
DDR_B_DQS3 DDR_B_DQS2 DDR_B_DQS#4 DDR_B_BG1_R DDR_B_DQS#6
240_0402_1%
RD209
G3 N1 G3 N1 F3 M9 F3 M9
DQSL_t VSS T1 RD78 DQSL_t VSS T1 DDR_B_DQS4 G3 DQSL_c VSS N1 DDR_B_DQS6 G3 DQSL_c VSS N1
DDR_B_BG1_R
MEMRST# P1 VSS 0_0201_1% MEMRST# P1 VSS DQSL_t VSS T1 DQSL_t VSS T1
RESET 1 DDP@ 2 DDR_B_BG1 RESET MEMRST# P1 VSS MEMRST# P1 VSS
1 MEM@ 2 RD210 F9 1 MEM@ 2 RD211 F9 RESET RESET
2
240_0402_1% ZQ 240_0402_1% ZQ 1 MEM@ 2 RD212 F9 1 MEM@ 2 RD213 F9
DDR_A_BG1(RD78, Intel:549352) ZQ ZQ
C 1. Near SOC side 240_0402_1% 240_0402_1% C
DDR_B_ACT# L3 A2 2. BO1+BO2+M small then other DDR_B_ACT# L3 A2 10mils
<8> DDR_B_ACT# DDR_B_BG0 ACT VSSQ DDR_B_BG0 ACT VSSQ DDR_B_ACT# DDR_B_ACT#
<8> DDR_B_BG0 M2 A8 CMD 25mils M2 A8 L3 A2 L3 A2
N9 BG0 VSSQ C9 N9 BG0 VSSQ C9 DDR_B_BG0 M2 ACT VSSQ A8 DDR_B_BG0 M2 ACT VSSQ A8
DDR_B_ALERT# TEN VSSQ 3. BO1+BO2 small then 800mils DDR_B_ALERT# TEN VSSQ BG0 VSSQ BG0 VSSQ
<8> DDR_B_ALERT# P9 D2 P9 D2 N9 C9 N9 C9
DDR_B_PAR T3 ALERT VSSQ D8 DDR_B_PAR T3 ALERT VSSQ D8 DDR_B_ALERT# P9 TEN VSSQ D2 DDR_B_ALERT# P9 TEN VSSQ D2
<8> DDR_B_PAR PAR VSSQ PAR VSSQ DDR_B_PAR ALERT VSSQ DDR_B_PAR ALERT VSSQ
E3 E3 T3 D8 T3 D8
T7 VSSQ E8 T7 VSSQ E8 PAR VSSQ E3 PAR VSSQ E3
B1 NC VSSQ F1 B1 NC VSSQ F1 T7 VSSQ E8 T7 VSSQ E8
+2.5V VPP VSSQ +2.5V VPP VSSQ NC VSSQ NC VSSQ
R9 H1 R9 H1 +2.5V B1 F1 +2.5V B1 F1
VPP VSSQ H9 VPP VSSQ H9 R9 VPP VSSQ H1 R9 VPP VSSQ H1
<8> DDR_B_MA[0..16] VSSQ VSSQ VPP VSSQ VPP VSSQ
96-BALL 96-BALL H9 H9
SDRAM DDR4 SDRAM DDR4 96-BALL VSSQ 96-BALL VSSQ
<8> DDR_B_DQS#[0..7]
K4A8G165WB-BCPB_FBGA96 K4A8G165WB-BCPB_FBGA96 SDRAM DDR4 SDRAM DDR4
X76@ X76@ K4A8G165WB-BCPB_FBGA96 K4A8G165WB-BCPB_FBGA96
<8> DDR_B_DQS[0..7]
X76@ X76@
<8> DDR_B_D[0..63]
<8> DDR_B_BG1
TERMINATION
+1.2V_VDDQ
+0.6VS_VTT
DDR_B_CLK0 RD214 1 MEM@ 2 39_0201_1% 1 2
DDR4 mapping SDP DDP +1.2V_VDDQ DDR_B_CLK#0 RD215 1 MEM@ 2 39_0201_1%
CD50 MEM@ DDR_B_MA14 RD218 1 MEM@ 2 39_0201_1%
E9 VSS UZQ +0.6V_B_VREFCA 0.01U_0402_16V7K DDR_B_CS#0 RD217 1 MEM@ 2 39_0201_1%
DDR_B_CLK0 DDR_B_MA15 RD220 1 MEM@ 2 39_0201_1%
M9 VSS BG1 1
2
DDR_B_MA12 RD219 1 MEM@ 2 39_0201_1%
T7 NC VSS RD195 CD51
1.8K_0402_1% DDR_B_CLK#0 3.3P_0402_50V8W
RD11 +DDR_VREF_CA 2@
VDDQ RCOMP[0] MEM@
2.7_0402_1%
1uF*16 (SOC side) 200_1% 121_1%
1
2 MEM@ 1 DDR_B_MA13 RD222 1 MEM@ 2 39_0201_1%
10uF*5 CD51 close to CPU DDR_B_MA8 RD221 1 MEM@ 2 39_0201_1%
DDR_B_PAR RD223 1 MEM@ 2 39_0201_1%
+0.6VS_VTT DDR_B_MA11 RD224 1 MEM@ 2 39_0201_1%
4 as near each on board RAM device as possible Follow MA51 1
+1.2V_VDDQ SDP@ SDP@
RD206 RD208 CD24
DDR_B_BG1_R
CD230
CD231
CD232
CD233
CD234
CD235
CD236
CD218
CD210
CD211
CD212
CD213
CD214
CD215
CD216
CD217
CD225
CD226
CD227
CD228
CD229
0_0402_5% 0_0402_5% 0.022U_0402_16V7K RD86 1 DDP@ 2 39_0201_1%

SD028000080 SD028000080 MEM@ 2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DDR_B_MA1 RD225 1 MEM@ 2 39_0201_1%
B B
2
+ CD237 SDP@ SDP@ +1.2V_VDDQ DDR_B_MA5 RD226 1 MEM@ 2 39_0201_1%
DDR_B_MA7
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
330U_D2_2V_Y RD207 RD209 RD13 RD200 RD228 1 MEM@ 2 39_0201_1%

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 @ 0_0402_5% 0_0402_5% DDR_B_MA9 RD227 1 MEM@ 2 39_0201_1%
2 SGA00009S00 SD028000080 SD028000080
24.9_0402_1%
MEM@
1.8K_0402_1%
DDR_B_ALERT# RD41 2 1 49.9_0402_1%
330U 2V H1.9 MEM@
1
9mohm POLY MEM@ INTEL suggest 50ohm 1%
DDR_B_BG0 RD229 1 MEM@ 2 39_0201_1%

DDR_B_MA10 RD230 1 MEM@ 2 39_0201_1%
DDR_B_MA3 RD232 1 MEM@ 2 39_0201_1%
DDR_B_BA1 RD231 1 MEM@ 2 39_0201_1%
+1.2V_VDDQ
DDR_B_CKE0 RD234 1 MEM@ 2 39_0201_1%

DDR_DRAMRST# 1 MEM@ 2 MEMRST# DDR_B_MA16 RD233 1 MEM@ 2 39_0201_1%
<8,23> DDR_DRAMRST# DDR_B_ODT0
CD264
CD263
CD266
CD267
RD202 0_0402_5% RD235 1 MEM@ 2 39_0201_1%

DDR_B_ACT# RD236 1 MEM@ 2 39_0201_1%
1 1 1 1
1
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
@ CD219
2 2 2 2
.1U_0402_16V7K
2
DDR_B_MA2 RD216 1 MEM@ 2 39_0201_1%
Add for cap downsize DDR_B_MA4 RD238 1 MEM@ 2 39_0201_1%

DDR_B_BA0 RD237 1 MEM@ 2 39_0201_1%
DDR_B_MA0 RD239 1 MEM@ 2 39_0201_1%
DDR_B_MA6 RD240 1 MEM@ 2 39_0201_1%
VPP
1uF*8 VTT
10uF*3 1uF*8
A A
10uF*2
+2.5V +0.6VS_VTT
CD238
CD254
CD255
CD241
CD256
CD243
CD244
CD245
CD220
CD221
CD222
CD269
CD270
CD271
CD246
CD247
CD248
CD249
CD250
CD251
CD252
CD253
CD224
CD223
CD274
CD272
CD273
1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
2 2 2 2 2 2 2 2 2 2 2 2 2 2
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
2 2 2 2 2 2 2 2 2 2 2 2 2
Vinafix.com Compal Electronics, Inc.

Security Classification Compal Secret Data
DDR4 ON BOARD CHIPS
2 as near each on board RAM device as possible AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Add for cap downsize
2 as near each on board RAM device as possible Add for cap downsize DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
5 4 3 2 1
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
LCD POWER CIRCUIT

+3VS +LCDVDD +19VB +INVPW R_B+ Place closed to JEDP1
UX1
5 1 W=80mils +LCDVDD
W=60mils W=60mils
1U_0201_6.3V6M
IN OUT LX1 +3VS

1
CX1 2 1 1 HCB2012KF-221T30_0805
GND CX4 1 2
1 1
4 3 0.1U_0201_10V6K 3S@ 1 1
2 EN OC
1000P_0402_50V7K
CX5
@ SM01000EJ00 3000ma 1 1
SY6288C20AAC_SOT23-5 CX3 2 2 CX2 CX6 CX7
220ohm@100mhz
4.7U_0402_6.3V6M 68P_0402_50V8J 0.1U_0201_10V6K .1U_0402_16V7K
DCR 0.04 2 2
XEMC@
XEMC@ @
<6> SOC_ENVDD 2 2
1
RX9
100K_0402_5%
2
For ICL Gitch Note: Unmount LX1 when panel boost

circuit was use. (2S battery cell)
EDP_TXP0_C
LED PANEL Conn.
CX8 1 2 .1U_0402_16V7K
<6> EDP_TXP0 EDP_TXN0_C
CX9 1 2 .1U_0402_16V7K
<6> EDP_TXN0 EDP_TXP1_C
CX10 1 2 .1U_0402_16V7K
<6> EDP_TXP1 EDP_TXN1_C CONN@
CX11 1 2 .1U_0402_16V7K
<6> EDP_TXN1 EDP_TXP2_C +INVPW R_B+
CX17 1 2 .1U_0402_16V7K W=60mils
<6> EDP_TXP2 EDP_TXN2_C
CX16 1 2 .1U_0402_16V7K 1
<6> EDP_TXN2 EDP_TXP3_C 1
CX19 1 2 .1U_0402_16V7K 2 41
<6> EDP_TXP3 EDP_TXN3_C 2 G1
CX18 1 2 .1U_0402_16V7K 3 42
<6> EDP_TXN3 3 G2
4 43
CX14 1 2 .1U_0402_16V7K EDP_AUXP_C 5 4 G3 44
<6> EDP_AUXP 5 G4
CX15 1 2 .1U_0402_16V7K EDP_AUXN_C SOC_BKL_PW M 6 45
<6> EDP_AUXN 6 G5
2 SOC_BKL_PW M RX1 1 @ 2 100K_0402_5% BKOFF# 7 46 2
<6> SOC_BKL_PW M +LCDVDD EDP_HPD 7 G6
8
+3VS XEMC@ 9 8
CX12 1 2 220P_0402_50V7K 10 9
100K_0402_5% 1 @ 2 RX3 EDP_AUXN_C XEMC@
W=60mils 11 10
100K_0402_5% 1 @ 2 RX4 EDP_AUXP_C BKOFF# CX13 1 2 220P_0402_50V7K 12 11
<58> BKOFF# 12
13
RX2 1 @ 2 10K_0402_5% EDP_AUXN_C 14 13
EDP_AUXP_C 15 14
16 15
EDP_TXP0_C 17 16
EDP_TXN0_C 18 17
RX5 19 18
0_0402_5% EDP_TXP1_C 20 19
1 2 EDP_HPD EDP_TXN1_C 21 20
Touch Screen <6> CPU_EDP_HPD
EDP_TXP2_C
22 21
22
RX6 23
+5VS +3VS +TS_PW R 100K_0402_5% EDP_TXN2_C 24 23
2 1 25 24
RX7 1 @ 2 0_0603_5% EDP_TXP3_C 26 25
RX8 1 @ 2 0_0603_5% EDP_TXN3_C 27 26
28 27
USB20_P6 29 28
<13> USB20_P6 USB20_N6 29
30
<13> USB20_N6 30
31
32 31
Touch +TS_PW R 32
Screen 33
TS_EN 34 33
<6,58> TS_EN 34
35
3 Camera +3VS
USB20_N7_CAMERA
USB20_P7_CAMERA
36 35
36
3
For 37
38 37
USB20_N7 USB20_N7_CAMERA
Camera DMIC_CLK_R 38
RX10 1 2 0_0402_5% 39
<13> USB20_N7 <56> DMIC_CLK_R DMIC_DATA_R 39
40
<56> DMIC_DATA_R 40
USB20_P7 RX11 1 2 0_0402_5% USB20_P7_CAMERA
<13> USB20_P7 JEDP1
DMIC_DATA_R
STARC_107K40-000001-G2
DMIC_CLK_R
SP010014B10
2
DX1
@EMC@
YSLC05CH_SOT23-3
1
4 4

eDP Connector
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
+5VS W=40mils +HDMI_5V_OUT

HDMI_C_CLKN 2 1 HDMI_R_CLKN
RY28 1 2 2.2K_0402_5% SOC_DP2_CTRL_CLK RY40 5.6_0402_5%
UY1 +3VS
2
EMC@
RY29 1 2 2.2K_0402_5% SOC_DP2_CTRL_DATA RY48
3 XEMC@ 360_0402_5%
OUT
1
1 RY27 1 2 2.2K_0402_5% HDMI_CTRL_DAT
+HDMI_5V_OUT
1
IN CY9 HDMI_C_CLKP 2 1 HDMI_R_CLKP
2 0.1U_0201_10V6K RY30 1 2 2.2K_0402_5% HDMI_CTRL_CLK RY41 5.6_0402_5%
GND 2
EMC@
1 1
AP2330W -7_SC59-3 HDMI_C_TX_N0 2 1 HDMI_R_TX_N0
RY42 5.6_0402_5%
2
EMC@
RY49
XEMC@ 360_0402_5%
port 0, 2 swap for INTEL HDMI
<6> SOC_DP2_P2 CY14 2 1 0.1U_0201_10V6K HDMI_C_TX_P0 RY31 1 2 470_0402_5%
1
<6> SOC_DP2_N2 CY15 2 1 0.1U_0201_10V6K HDMI_C_TX_N0 RY32 1 2 470_0402_5%
HDMI_C_TX_P0 2 1 HDMI_R_TX_P0
<6> SOC_DP2_P1 CY12 2 1 0.1U_0201_10V6K HDMI_C_TX_P1 RY33 1 2 470_0402_5% RY43 5.6_0402_5%
<6> SOC_DP2_N1 CY13 2 1 0.1U_0201_10V6K HDMI_C_TX_N1 RY34 1 2 470_0402_5% EMC@
<6> SOC_DP2_P0 CY10 2 1 0.1U_0201_10V6K HDMI_C_TX_P2 RY35 1 2 470_0402_5%

<6> SOC_DP2_N0 CY11 2 1 0.1U_0201_10V6K HDMI_C_TX_N2 RY36 1 2 470_0402_5%
HDMI_C_TX_N1 2 1 HDMI_R_TX_N1
<6> SOC_DP2_P3 CY16 2 1 0.1U_0201_10V6K HDMI_C_CLKP RY37 1 2 470_0402_5% RY44 5.6_0402_5%
<6> SOC_DP2_N3 CY17 2 1 0.1U_0201_10V6K HDMI_C_CLKN RY38 1 2 470_0402_5% EMC@
2
RY50
XEMC@ 360_0402_5%
1
+3VS RY45 5.6_0402_5%
6
D EMC@
2
G 2N7002KDW _SOT363-6
2 QY5A HDMI_C_TX_N2 2 1 HDMI_R_TX_N2 2
S RY46 5.6_0402_5%
1
EMC@
2
+3VS
RY51
XEMC@ 360_0402_5%
1
2
RY47 5.6_0402_5%
G
SOC_DP2_CTRL_DATA 1 6 HDMI_CTRL_DAT EMC@

<6> SOC_DP2_CTRL_DATA
S
PJT138KA 2N SOT363-6
QY7B
5
+3VS
HDMI connector
G
SOC_DP2_CTRL_CLK 4 3 HDMI_CTRL_CLK
<6> SOC_DP2_CTRL_CLK
S
JHDMI1
PJT138KA 2N SOT363-6 HDMI_HPD 19
18 HP_DET
QY7A +HDMI_5V_OUT +5V
17
DDC/CEC_GND
2
HDMI_CTRL_DAT 16
RY39 HDMI_CTRL_CLK 15 SDA
1M_0402_5% 14 SCL
13 Utility
CEC
5
HDMI_R_CLKN 12
G
1
QY5B 11 CK-
3 2N7002KDW _SOT363-6 HDMI_R_CLKP 10 CK_shield 3
HDMI_R_TX_N0 9 CK+
SOC_DP2_HPD 4 3 HDMI_HPD 8 D0-
S
<6> SOC_DP2_HPD D0_shield
D
HDMI_R_TX_P0 7
HDMI_R_TX_N1 6 D0+
D1-
2
5
RY11 HDMI_R_TX_P1 4 D1_shield 23
HDMI_R_TX_N2 3 D1+ GND1 22
100K_0402_5% D2- GND2
2 21
HDMI_R_TX_P2 1 D2_shield GND3 20
1
D2+ GND4
ACON_HMRBL-AK120D
DC232007600
CONN@
SYMBOL:DC232004700
DY1
HDMI_HPD 6 3 HDMI_CTRL_DAT
I/O4 I/O2
DY3 @EMC@ DY2 @EMC@
HDMI_R_TX_N11 1 10 9 HDMI_R_TX_N1 HDMI_R_TX_P0 1 1 10 9 HDMI_R_TX_P0
5 2
HDMI_R_TX_P12 2 HDMI_R_TX_P1 HDMI_R_TX_N0 HDMI_R_TX_N0 VDD GND
9 8 2 2 9 8
HDMI_R_TX_P24 4 7 7 HDMI_R_TX_P2 HDMI_R_CLKN 4 4 7 7 HDMI_R_CLKN
HDMI_CTRL_CLK 4 1
I/O3 I/O1 +HDMI_5V_OUT
HDMI_R_TX_N25 5 6 6 HDMI_R_TX_N2 HDMI_R_CLKP 5 5 6 6 HDMI_R_CLKP
AZC099-04S.R7G_SOT23-6
3 3 3 3 @EMC@
4 4
8 8
P/N: SC300001G00,S DIO(BR) AZC099-04S.R7G SOT23 ESD
TVW DF1004AD0 TVW DF1004AD0

HDMI CONN.
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
LAN-RTL8111H
PVT modify
+3VALW +3V_LAN
RL1
60mil 0_0805_5%
1 2 W=60mil W=60mil
UL1 IDC=1200mA +LAN_VDD +3V_LAN
5 1
60mil W=60mil
IN OUT 300mA 1.4A
1 2 +REGOUT RL10 1 @ 2 0_0603_5% 1
GND
4 3
EN OC
1 1 1 1 1 1 1 1 1 1 1 1 1
0.1U_0201_10V6K
CL7
0.1U_0201_10V6K
CL1
0.1U_0201_10V6K
CL2
0.1U_0201_10V6K
CL3
0.1U_0201_10V6K
CL8
0.1U_0201_10V6K
CL9
1U_0201_6.3V6M
CL4
1U_0201_6.3V6M
CL23
4.7U_0402_6.3V6M
CL10
4.7U_0402_6.3V6M
C11
1U_0201_6.3V6M
CL12
0.1U_0201_10V6K
CL13
0.1U_0201_10V6K
CL14
2 2 SY6288C20AAC_SOT23-5
@
CL22 CL5
1U_0201_6.3V6M 1U_0201_6.3V6M LAN_PWR_EN 2 2 2 2 2 2 2 2 2 2 2 2 2
Using LDO mode
@
1 1 LAN_PWR_EN <58>
@
Place near Pin 3,8,22,30 Place near Pin 22 For surge improvement Place near Pin 11,32
From EC Place near Pin 11,32 For downsize CL12 change to 1uF
Add 1 cap for downsize reserved
High active.
EN threshold voltage min:1.2V typ:1.6V max:2.0V
Current limit threshold 1.5~2.8A
+3V_LAN Rising time must >0.5ms and <100ms
+3V_LAN
UL2 +3VS
1
RL4 RL8
reserve EC_PME# pull high 100K to +3VALW_EC 10K_0402_5% 1K_0402_5%
@
2
2 LAN_MIDI0+ 1 17 PCIE_CRX_C_DTX_P9 .1U_0402_16V7K 2 1 CL16 GPO ISOLATEB 2
LAN_MIDI0- 2 MDIP0 HSOP 18 PCIE_CRX_C_DTX_N9 .1U_0402_16V7K 2 1 PCIE_CRX_DTX_P9 <13>
CL15
MDIN0 HSON PCIE_CRX_DTX_N9 <13>
2
+LAN_VDD 3 19 PLT_RST_BUF#
LAN_MIDI1+ 4 AVDD10 PERSTB 20 ISOLATEB PLT_RST_BUF# <11,52,68>
RL9
LAN_MIDI1- 5 MDIP1 ISOLATEB 21 LAN_PME# 0_0402_5% 2 @ 1 RL2
MDIN1 LANWAKEB EC_PME# <58> 15K_0402_1%
LAN_MIDI2+ 6 22 +LAN_VDD
LAN_MIDI2- 7 MDIP2 DVDD10 23 +3V_LAN 10K_0402_5% 2 1 RL3 +3V_LAN
1
+LAN_VDD 8 MDIN2 VDDREG 24 +REGOUT
LAN_MIDI3+ 9 AVDD10 REGOUT 25
LAN_MIDI3- 10 MDIP3 LED2 26 GPO 2 @ 1
+3V_LAN 11 MDIN3 LED1/GPIO 27 LAN_GPO <58> YL1
0_0402_5% RL7
CLKREQ_PCIE#1 12 AVDD33 LED0 28 XTLI PVT modify 25MHZ_20PF_7R25000001
PU at PCH side <11> CLKREQ_PCIE#1 13 CLKREQB CKXTAL1 29 XTLO_R 2 1 XTLO 3/13 update Pin 28 to XTALIN
<13> PCIE_CTX_C_DRX_P9 HSIP CKXTAL2 +LAN_VDD RL5
14 30 0_0402_5% XTLI 1 3 XTLO MP modify
<13> PCIE_CTX_C_DRX_N9 HSIN AVDD10 LAN_RST 1 3
15 31 1 2
<11> CLK_PCIE_P1 REFCLK_P RSET +3V_LAN 2.49K_0402_1% NC NC
16 32 RL6 MP modify
<11> CLK_PCIE_N1 REFCLK_N AVDD33
1
33
GND CL20 2 4 CL21
27P_0402_50V8J 27P_0402_50V8J
2
SJ10000TO00
RTL8111H-CG_QFN32_4X4
SA000080P00 LAN Connector 12/21 change YL1 size to 20x16
JRJ45
12
RJ45_MIDI3- 8 GND
PR4- 11
3 RJ45_MIDI3+ 7 GND 3
RJ45_MIDI1-
PR4+ ESD
6
PR2- PLT_RST_BUF#
TR1 RJ45_MIDI2- 5
PR3-
1
LAN_TERMAL 1 24 MCT1 RJ45_MIDI2+ 4 @EMC@
LAN_MIDI0+ 2 TCT1 MCT1 23 RJ45_MIDI0+ PR3+ CL25
LAN_MIDI0- 3 TD1+ MX1+ 22 RJ45_MIDI0- RJ45_MIDI1+ 3
TD1- MX1- PR2+ 100P_0402_50V8J
2
4 21 MCT2 RJ45_MIDI0- 2
LAN_MIDI1+ 5 TCT2 MCT2 20 RJ45_MIDI1+ PR1- 10
LAN_MIDI1- 6 TD2+ MX2+ 19 RJ45_MIDI1- RJ45_MIDI0+ 1 GND
TD2- MX2- PR1+ 9
7 18 MCT3 GND
LAN_MIDI2+ 8 TCT3 MCT3 17 RJ45_MIDI2+
LAN_MIDI2- 9 TD3+ MX3+ 16 RJ45_MIDI2- SINGA_2RJ1660-000111F
TD3- MX3- CONN@
10 15 MCT4 LTCX008KA00
LAN_MIDI3+ 11 TCT4 MCT4 14 RJ45_MIDI3+
LAN_MIDI3- 12 TD4+ MX4+ 13 RJ45_MIDI3-
TD4- MX4- 40mil
RJ45_GND
RL35
RL34
RL33
RL32
1 2 LANGND
C1
1 GST5009-E 40mil 10P_0402_50V8J
2
2
2
2
SP050006B10
C2 LANGND
2
.1U_0402_16V7K
2 @
Place close to TCT pin J1 JP2
1
1
1
1
75_0402_1%~D
75_0402_1%~D
75_0402_1%~D
75_0402_1%~D
JUMP_43X118 XEMC@
B88069X9231T203_4P5X3P2-2
4 4
2
D1
EMC@
MESC5V02BD03_SOT23-3
1
RJ45_GND

LAN RTL8111H-CG
A B C D E
A B C D E
+3VS_WLAN
Wireless LAN
+3VS_WLAN CNVi use ALW power rail / PCIE WLAN use VS rail
autodetct and change EN pin power domain by BIOS +3VS_WLAN PVT modify
RM6 +3VALW
2 1 10K_0402_5% WLAN_PME# UM1 W=60mils CM2/CM4/CM31 close to pin64,66
5 1 1 1 1
IN OUT CM4 CM2 CM31
NGFF WL+BT (KEY E) CM19
1 GND
2
4.7U_0402_6.3V6M
@ @
2 2 2
@
WLAN_ON 4 3
<58> WLAN_ON EN OC 1 1
UART_2_CRXD_R_DTXD RM45 1 UART@ 2 0_0402_5% 1U_0201_6.3V6M CM1 CM3 0.1U_0201_10V6K 4.7U_0402_6.3V6M
UART_2_CTXD_R_DRXD RM46 1 UART@ 2 0_0402_5% UART_2_CRXD_DTXD <12> 2 SY6288C20AAC_SOT23-5
UART_2_CTXD_DRXD <12>
4.7U_0402_6.3V6M 0.1U_0201_10V6K
2 2
Co-layout with CNVi for UART Debug and BT signal
1 +3VS_WLAN PVT modify 1
KEY E +3VS_WLAN
reserve 1000p for cnvi
CM32/CM33/CM34 close to pin2,4
JNGFF1 1 2 1000P_0402_50V7K
#571906 change to USB port10 for CNVi 1 2 CM18 @
1
CM34
1
CM32
1
CM33
USB20_P10 GND_1 3.3VAUX_2 @ T52
3 4 Follow C38&ORB CNVI@ @ @ @
<13> USB20_P10 USB20_N10 5 USB_D+ 3.3VAUX_4 6 1 RM41 2
For BT <13> USB20_N10 7 USB_D- LED1# 8 RM42 75K_0402_5% 2 4.7U_0402_6.3V6M 2 2
9 GND_7 PCM_CLK 10 CNV_RF_RESET#_R 1 2 0.1U_0201_10V6K 4.7U_0402_6.3V6M
<14> CNV_CRX_DTX_N1 SDIO_CLK PCM_SYNC CNV_RF_RESET# <10>
11 12 RM37 33_0402_5%
<14> CNV_CRX_DTX_P1 SDIO_CMD PCM_OUT CLKREQ_CNV#_R
13 14 1 2
SDIO_DAT0 PCM_IN CLKREQ_CNV# <10>
15 16 33_0402_5%
<14> CNV_CRX_DTX_N0 SDIO_DAT1 LED2# @ T267
17 18
<14> CNV_CRX_DTX_P0 SDIO_DAT2 GND_18
19 20
21 SDIO_DAT3 UART_WAKE 22 UART_2_CRXD_R_DTXD RM47 2 CNVI@ 1 22_0402_5%
<14> CLK_CNV_CRX_DTX_N 23 SDIO_WAKE UART_TX CNV_BRI_CRX_DTX <14>
<14> CLK_CNV_CRX_DTX_P SDIO_RST
24 UART_2_CTXD_R_DRXD RM48 2 CNVI@ 1 22_0402_5%
PH +3VS at SOC side, for win7 USB3 debug INTEL RF Linda suggest reserve for CNVi
25 UART_RX 26 CNV_RGI_CRX_R_DTX RM38 2 CNVI@ 1 22_0402_5% CNV_RGI_CTX_DRX <14>
PCIE_CTX_C_DRX_P10 27 GND_33 UART_RTS 28 CNV_BRI_CTX_R_DRX RM39 2 CNVI@ 1 22_0402_5% CNV_RGI_CRX_DTX <14> +1.8VALW_PRIM
<13> PCIE_CTX_C_DRX_P10 PCIE_CTX_C_DRX_N10 PET_RX_P0 UART_CTS E51TXD_P80DATA_R CNV_BRI_CTX_DRX <14>
29 30 RM2 2 1 0_0402_5%
<13> PCIE_CTX_C_DRX_N10 31 PET_RX_N0 CLink_RST 32 E51RXD_P80CLK_R 2 1 0_0402_5% E51TXD_P80DATA <58> CNV_BRI_CTX_R_DRX 1 RM57 2
RM7
PCIE_CRX_DTX_P10 33 GND_39 CLink_DATA 34 E51RXD_P80CLK <58>
<13> PCIE_CRX_DTX_P10 @ 10K_0402_5%
PCIE_CRX_DTX_N10 35 PER_TX_P0 CLink_CLK 36
<13> PCIE_CRX_DTX_N10 PER_TX_N0 COEX3 +3VS_WLAN
37 38
CLK_PCIE_P2 39 GND_45 COEX2 40
<11> CLK_PCIE_P2 CLK_PCIE_N2 41 REFCLK_P0 COEX1 42 SUSCLK_R WL_OFF#
RM14 1 @ 2 0_0402_5% 1 RM58 2
<11> CLK_PCIE_N2 43 REFCLK_N0 SUSCLK(32KHz) 44 WL_RST#_R 2 0_0402_5% PLT_RST_BUF# SUSCLK <11>
RM4 1 @ 10K_0402_5%
CLKREQ_PCIE#2 45 GND_51 PERST0# 46 BT_ON PLT_RST_BUF# <11,51,68>
<11> CLKREQ_PCIE#2 WLAN_PME# CLKREQ0# W_DISABLE2# WL_OFF# BT_ON <58>
47 48 RM56
<58> WLAN_PME# 49 PEWAKE0# W_DISABLE1# 50 WL_OFF# <58> 2 1CLKREQ_CNV#_R
51 GND_57 I2C_DAT 52 10K_0402_5%
2 <14> CNV_CTX_DRX_N1 53 RSVD/PCIE_RX_P1 I2C_CLK 54 P80CLK and BT_ON enable seperate. 2
<14> CNV_CTX_DRX_P1 55 RSVD/PCIE_RX_N1 I2C_IRQ 56 REFCLK_CNV_R
GND_63 RSVD_64 @ T508
57 58
<14> CNV_CTX_DRX_N0 59 RSVD/PCIE_TX_P1 RSVD_66 60
<14> CNV_CTX_DRX_P0 61 RSVD/PCIE_TX_N1 RSVD_68 62
63 GND_69 RSVD_70 64
<14> CLK_CNV_CTX_DRX_N 65 RSVD_71 3.3VAUX_72 66
<14> CLK_CNV_CTX_DRX_P 67 RSVD_73 3.3VAUX_74 E51TXD_P80DATA_R
GND_75 68
69 GND1
reserve for BT_ON OD pull high (1.0) GND2
1
BELLW_80152-3221 RM19
BT_ON 1 @ 2 CONN@ 100K_0402_5%
+3VS_WLAN
8.2K_0402_5% RM49
SP070013E00
2
3 3
4 4

M.2 Key E (WLAN)/Key M(SSD)
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
HD Audio Codec add 1 cap for MLCC downsize

+PVDD_HDA
Int. Speaker Conn.
SPK_R bead on sub/B 40mil
SM01000EJ00 3000mA 220ohm@100mhz DCR 0.04 +5VS (output = 300 mA) +VDDA SPKR+ LA2 1 2 0_0603_5% SPK_R+
40mil 40mil JPA1 40mil SPKR- LA3 1 2 0_0603_5% SPK_R- SPK_R+
SPK_R-
<73>
<73>
LA1 2 1 1 2
+VDDA 1 2
HCB2012KF-221T30_0805 1 1 1
0.1U_0201_10V6K
CA2
0.1U_0201_10V6K
CA3
.1U_0402_16V7K
CA4
JUMP_43X79 4.75V JSPK1
10U_0402_6.3V6M
10U_0402_6.3V6M
10_0805_5%2SPKL+_R LA4 EMC@1 2 PBY160808T-121Y-N_2P SPK_L+ 1
CA1
SPKL+ RA3
CA34
@
SPKL- RA4 10_0805_5%2SPKL-_R LA5 EMC@1 2 PBY160808T-121Y-N_2P SPK_L- 2 1
2
2 2 @ +AVDD1_HDA 2 2 3
XEMC@ G1 4
GND & GNDA moat EMI request for solve EMI noise, SM01000OW00. G2
GND GND
3
GND CVILU_CI4202M2HR0-NH
Add resistor for R/L channel balance GND
1 Place near Pin41 Place near Pin46 XEMC@ XEMC@ SP02000RR00 1
DA1 DA2 CONN@
add 1 cap for MLCC downsize CA35 1 2 10U_0402_6.3V6M add 1 cap for MLCC downsize TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
GND 20mil
1
CA5 1 2 10U_0402_6.3V6M RA1 1 2 0_0603_5%
+VDDA
1 GND
1
0.1U_0201_10V6K
CA8
Pin9 need to matching with SOC HDA CA6 1 2 0.1U_0201_10V6K CA9 CA36 GND
interface.
10U_0402_6.3V6M
10U_0402_6.3V6M
2 1 Place near Pin9 +3VS_DVDDIO
+3VS
2
RA2 0_0402_5% 2 @
+3VS_DVDD GND & GNDA moat
20mil GNDA place close codec
2 1 Place near Pin26
+3VS +3VS
RA5 0_0402_5%
1
1
+1.8VS_VDDA
0.1U_0201_10V6K
CA11
CA37 CA10 2 1 +1.8VS
1 RA6 0_0402_5%
1
0.1U_0201_10V6K
CA12
CA13 JDMIC1
10U_0402_6.3V6M
10U_0402_6.3V6M
2
2
2 1
#575412 WHL DG p292_ DMIC_DATA34 RA50 2 4MIC@ 10_0402_5% DMIC_DATA34_1 2 1
10U_0402_6.3V6M
2
2 @ add 2pF cap on HDA_SDO and HDA_RST# close to CPU DMIC_CLK 2 1 DMIC_CLK34_1 3 2
1 2 DMIC_CLK add 2pF cap on HDA_SDI close to codec
LA9 4MIC@ BLM15PX221SN1D_2P 4 3
Place near Pin1 GND GNDA 11/26 4
CA32 @EMC@ 5
10P_0402_50V8J HDA_SDIN0_AUDIO SM01000Q500 6 G1
41
46
26
40
G2
9
UA1 Place near Pin40
Reserved for EMI ACES_50278-00401-001
DVDD
DVDD-IO
PVDD1
PVDD2
AVDD1
AVDD2
add 1 cap for MLCC downsize CONN@
GND 1
CA31 GND
SP02000RR00
LINE1-L 22 2P_0201_25V8B
LINE1-R 21 LINE1-L(PORT-C-L) 43 SPKL- 2
UA1 LINE1-R(PORT-C-R) SPK-OUT-L- 42 SPKL+
24 SPK-OUT-L+
23 LINE2-L(PORT-E-L) 45 SPKR+
LINE2-R(PORT-E-R) SPK-OUT-R+ GND
44 SPKR-
2 RING2 17 SPK-OUT-R- 2
40mil SLEEVE 18 MIC2-L(PORT-F-L) /RING2
ALC256-CG MQFN 48P CODEC MIC2-R(PORT-F-R) /SLEEVE 32 HP_LEFT
Combo MIC
256@ +MICBIAS
+MICBIAS 31
LINE1-VREFO-L
HPOUT-L(PORT-I-L)
HPOUT-R(PORT-I-R)
33 HP_RIGHT Digital MIC
SA000080Q00 30
LINE1-VREFO-R 10 HDA_SYNC_R
SYNC HDA_SYNC_R <10>
DMIC_DATA 2 6 HDA_BIT_CLK_R
DMIC_CLK GPIO0/DMIC-DATA BCLK HDA_BIT_CLK_R <10>
3
GPIO1/DMIC-CLK 1 XEMC@ 2 1 2 CA15 XEMC@ GND
RA10 0_0402_5% 22P_0402_50V8J
EC_MUTE# 47 5 HDA_SDOUT_R
<58> EC_MUTE#
HDA_RST#_R 2 255@ 1 11 PDB SDATA-OUT 8 HDA_SDIN0_AUDIO 1 RA33 2
HDA_SDOUT_R <10>
PVT modify
TO eDP Conn
Pin11,12 <10> HDA_RST#_R
0_0402_5% RA41 RESETB SDATA-IN 33_0402_5%
HDA_SDIN0 <10>
ALC255: RESETB, PCBEEP 48 DMIC_DATA34 DMIC_DATA 1 2 RA35 DMIC_DATA_R
ALC256 : Floating ( I2C ) MONO_IN 12 SPDIF-OUT/GPIO2 0_0402_5% DMIC_DATA_R <38>
10mil Close codec1
PCBEEP 16 PC_BEEP DMIC_CLK 2 1 DMIC_CLK_R
HP_PLUG# RA13 2 200K_0402_1% SENSE_A 13 MONO-OUT LA6 EMC@ BLM15PX221SN1D_2P DMIC_CLK_R <38>
2 1 100K_0402_1% SENSE A +MIC2_VREFO
RA14 14
+3VS SENSE B 29 10U_0402_6.3V6M 1 2 CA18
SM01000Q500
MIC2-VREFO GND
1
37
CA19 35 CBP 7 10U_0402_6.3V6M 1 2 CA20
CBN LDO3-CAP GNDA
+1.8VS_VDDA
2 256@ 1 2.2U_0402_6.3V6M 39
2
0_0402_5% RA43 LDO2-CAP 27 10U_0402_6.3V6M 1 2 CA21 GNDA

+3VS_DVDD
2 255@ 1 CPVDD 36
CPVDD
LDO1-CAP Headphone Out +MIC2_VREFO
Pin20 0_0402_5% RA42 1 RA15 2
28 CODEC_VREF 100K_0402_5% 10mil
ALC255 : 3.3V VREF
2.2U_0402_6.3V6M
+3VALW
2 1 20
ALC256 : 3.3V or 5V CPVREF
0.1U_0201_10V6K
CA23
RA16 0_0402_5% 15 1
JDREF
CA24
Power for combo jack depop 10U_0402_6.3V6M 1 2 CA22 19 34 CPVEE
GNDA MIC-CAP CPVEE
1
circuit at system shutdown mode RA19 RA20
2
1
4 @ 2 2.2K_0402_5%
DVSS 2.2K_0402_5%
49 25 CA26
Pin4 Thermal PAD AVSS1 38 2.2U_0402_6.3V6M
ALC283 : DVSS
2
AVSS2 LA7 EMC@
3 ALC255/256/233 : DC DET (For Japen customer only) Place near pin28 GNDA BLM15PX330SN1D 0402 3
ALC255-CG_MQFN48_6X6 SLEEVE 2 1 SLEEVE_L
Pin36 SA000082700 GND
255@ RING2 2 1 RING2_L
ALC255 : 3.3V GND
GNDA LA8 EMC@
2
ALC256 : 1.8V
AZ5123-02S.R7G 3P C/A SOT23

BLM15PX330SN1D 0402
2 2
CA40 CA41 D3
RA21 CA27 EMC@
DOS mode 22K_0402_5% .1U_0402_16V7K Pin15 680P_0402_50V7K 680P_0402_50V7K
2 1 BEEP#_R 1 2 MONO_IN EMC@ 1 1
<58> BEEP# ALC283 : Ref. Resistor for Jack Detect EMC@
255@
Pin16 ALC255/256/233 : Jack Detect for SPDIF-OUT and SPK-OUT port
RA22 CA33 ALC255: MONO-OUT GND
1
2
ALC256 : BEEP
4.7K_0402_5%
OS mode 22K_0402_5% 1 .1U_0402_16V7K

PC_BEEP
100P_0402_50V8J
CA28 @EMC@
2 1 1 2
<12> PCH_SPKR
RA23
GND
256@
2 LINE1-L 1 2 JHP1
1
CA29 4.7U_0402_6.3V6M
RING2_L 4
HP_LEFT RA24 1 2 0_0603_5% HPOUT_L_1 RA48 1 2 HPOUT_L_2 2
62_0603_1%
GND 5
HP_PLUG# 6
GND & GNDA moat HP_RIGHT RA27 1 2 0_0603_5% HPOUT_R_1 RA49 1 2 HPOUT_R_2
SLEEVE_L
3 G 7
62_0603_1% 1
RA47 2 1 0_0402_5% DEREN_570704-001H

LINE1-R 1 2 2 2
ESD reserved CA30 4.7U_0402_6.3V6M CA38 CA39 SP02000RR00
4 +MICBIAS DA5 XEMC@ XEMC@ 4
CONN@
RA44 2 1 0_0402_5% 2 2 RA29 1 330P_0402_50V7K 330P_0402_50V7K GNDA GNDA
HPOUT_R_2 4.7K_0402_5% 1 1
HPOUT_L_2 1
TVNST52302AB0_SOT523-3
2
RA45 2 1 0_0402_5% 3 2 RA32 1

4.7K_0402_5%
D4
BAT54A-7-F_SOT23-3 GNDA
SCSBAT54100
RA46 2 1 0_0402_5% SYMBOL:SCSBAT540A0
XEMC@ Security Classification Compal Secret Data Compal Electronics, Inc.
1
Vinafix.com GND THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec ALC255/ALC256 Colay
Rev
GND GNDA AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Vendor suggest: Custom 1.0
At least one Ground short close to codec.
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
5 4 3 2 1
+1.8VALW_PRIM
near SOC SOC_RTCRST# <11>
1
EC_RST# D
1U_0201_6.3V6M
C3853 1 2 0.1U_0201_10V6K 1
C3886
EC_CLR_CMOS 2 QB6
G L2N7002WT1G_SC-70-3
1
S
3
2 RB26
10K_0402_5%
Vendor suggest
2
+3VLP_EC +3VLP +3VLP_EC +3VLP_ECA +VTT_EC +1.05V_VCCST
R3985
0_0603_5% L17
1 @ 2 EC_PME# 1 @ 2 1 2 R3983 2 1 0_0402_5%
D D
RB5 47K_0402_5% BLM15AX601SN1D _2P
4.7U_0402_6.3V6M
EC_PME# PU +3V_LAN at LAN side SM01000KL00 1
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1 1 1
+3VLP_EC
C3881
C3880
C3849
+3VLP_EC +1.8VALW_PRIM +1.8VALW_ESPI +VTT_EC
C3887
C3884 0.1U_0201_10V6K
0.1U_0201_10V6K 2
R3970 1 2 2.2K_0402_5% EC_SMB_CK1 2 2 2 R3984 2 Vendor suggest LID_SW# RB15 1 2 100K_0402_5%
R3971 1 2 2.2K_0402_5% EC_SMB_DA1 0_0402_5%
1 2
ECAGND
ECAGND <83>
111
117
124
22
33
96
67
U11
9
ESPI Bus Pin : 1~14
PECI_VTT
VCC_ESPI
VCC
VCC
VCC
AVCC
VCC0
VCC_IO2
Power rail 1.8V
C3885
XEMC@
2 1 2
XEMC@
R3972
1 ESPI_CLK_R EMI TP_PWR_EN 1
eSPI & MISC
21
<63> TP_PWR_EN GA20/GPIO00 PWM0/GPIO0F EC_VCCST_PG_R <11,78>
22P_0402_50V8J 33_0402_5% 1ESPI_ALERT# 2 23
T135 TP@ FP_PWR_EN ESPI_ALERT#/GPIO01 PWM1/GPIO10 BEEP# <56>
3 PWM Output 26
<66> FP_PWR_EN GPIO02 FANPWM0/GPIO12 FAN_PWM1 <77> SYS_PWROK_R
4 27 2 1 SYS_PWROK <11,78>
1 2 SYS_PWROK <9> ESPI_CS# ESPI_CS# FANPWM1/GPIO13
@ 5
<9> ESPI_IO3_R ESPI_IO3
R3874 10K_0402_5% 7 RB11 0_0402_5%
<9> ESPI_IO2_R ESPI_IO2 BATT_TEMP
8 63
<9> ESPI_IO1_R ESPI_IO1 AD0/GPIO38 VCIN1_BATT_DROP BATT_TEMP <83,84>
10 64
<9> ESPI_IO0_R ESPI_IO0 AD1/GPIO39 VCIN1_BATT_DROP <83>
65
ESPI_CLK_R AD2/GPIO3A AD_BID ADP_I <83,84>
Reserved R3874,as Schematic checklist requirement, 12 AD Input 66
<9> ESPI_CLK_R KBL_EN 13 ESPICLK AD3/GPIO3B 75
<63> KBL_EN EC_RST# 37 GPIO05 AD4/GPIO42 76 IDCHG DB1
For Thermal Portect Shutdown
<77> EC_RST# EC_SCI# ECRST# AD5/GPIO43 IDCHG <84>
20 RB751V-40_SOD323-2
<7> EC_SCI# GPIO0E 3V_EN
38 MAINPWON 1 2
GPIO1D 3V_EN <85>
14
<9> ESPI_RST# ESPI_RST#/GPIO07 EC_VCCST_EN
68
DA0/GPIO3C EC_VCCST_EN <11> 3V_EN_R
R3973 1 @ 2 4.7K_0402_5% OPMODE DA Output 70 OPMODE 1 2 RB17 1 2
KSI0 55 DA1/GPIO3D 71 WLAN_ON RB16 1M_0402_5%
C KSI0/GPIO30 DA2/GPIO3E WL_OFF# WLAN_ON <52> C
KSI1 56 72 1K_0402_5%
KSI1/GPIO31 DA3/GPIO3F WL_OFF# <52>
KSI2 57
KSI3 58 KSI2/GPIO32 83 EC_MUTE#
KSI3/GPIO33 SCL2/GPIO4A USB_EN EC_MUTE# <56>
KSI4 59 84
KSI4/GPIO34 SDA2/GPIO4B WLAN_PME# USB_EN <71,73>
OPMODE (Internal Pull High) : KSI5 60 85
KSI5/GPIO35 SCL3/GPIO4C SPOK_5V WLAN_PME# <52> +3VS
KSI6 61 86
KSO[0..17] KSI6/GPIO36 SDA3/GPIO4D TP_CLK SPOK_5V <85>
KSI7 62 87
Pull Up : Intel eSPI Master Attached Flash Sharing Topology <63> KSO[0..17] KSO0 39 KSI7/GPIO37
PS2 Interface
PSCLK3/GPIO4E 88 TP_DATA TP_CLK <63>
KSO0/GPIO20 PSDAT3/GPIO4F TP_DATA <63>
--> For KB9042 / KB9052 KSI[0..7] KSO1 40
<63> KSI[0..7] KSO2 41 KSO1/GPIO21 EC_MUTE# R3961 1 @ 2 10K_0402_5%
KSO3 42 KSO2/GPIO22 97 ENBKL
Pull Down : Intel Legacy Wire-OR share ROM. KSO4 43 KSO3/GPIO23 SHICS#/GPIO60 98 VCC_AUX_PWRGD ENBKL <6>
--> For KB9022/9042 Use KSO5 44 KSO4/GPIO24 SHICLK/GPIO61 99 VCC_AUX_PWRGD <91>
KSO5/GPIO25 Int. K/B GPIO SHIDO/GPIO62 VCIN0_PH AC_IN
KSO6 45 109 C3879 1 2 100P_0402_50V8J
KSO7 46 KSO6/GPIO26 Matrix VCIN0/GPIO78 VCIN0_PH <83>
KSO8 47 KSO7/GPIO27 R3964 1 @ 2 4.7K_0402_5%
KSO9 48 KSO8/GPIO28 119
KSO9/GPIO29 MISO_SHR_ROM/GPIO5B BT_ON VCCIN_AUX_CORE_VID <11>
KSO10 49 120
KSO10/GPIO2A MOSI_SHR_ROM/GPIO5C EC_CLR_CMOS BT_ON <52>
KSO11 50 SPI ROM 126
KSO12 51 KSO11/GPIO2B SPICLK_SHR_ROM/GPIO58 128 SW_PROCHOT#
KSO13 52 KSO12/GPIO2C SPICS#_SHR_ROM/GPIO5A
PM_SLP_S0# 1 @ 2 KSO14 53 KSO13/GPIO2D
<11,15,66> PM_SLP_S0# KSO14/GPIO2E EC_TP_INT# VCCIN_AUX_CORE_VID1_R_EC 1
RB35 0_0402_5% KSO15 54 73 @ 2
KSO15/GPIO2F AD6/GPIO40 SYS_PWROK_R EC_TP_INT# <7,63> VCCIN_AUX_CORE_VID1_R <11,17,91>
KSO16 81 74 RB36 0_0402_5%
EC_SLP_S0IX# 1 2 EC_SLP_S0IX#_R KSO17 82 KSO16/GPIO48 AD7/GPIO41 89 BATT_4S
<7> EC_SLP_S0IX# KSO17/GPIO49 LOCK#/GPIO50 90 BATT_BLUE_LED# BATT_4S <84>
RB34 0_0402_5%
GPIO52 BATT_BLUE_LED# <63>
91
PVT modify EC_SMB_CK1 77 CAPSLED#/GPIO53 92 PWR_LED#
<83,84> EC_SMB_CK1 EC_SMB_DA1 SCL0/GPIO44 GPIO WDT_LED/GPIO54 BATT_AMB_LED# PWR_LED# <63>
78 93
<83,84> EC_SMB_DA1 EC_SMB_CK2 SDA0/GPIO45 SCROLED#/GPIO55 BATT_AMB_LED# <63>
79 95 SYSON
<9> EC_SMB_CK2 EC_SMB_DA2 SCL1_BT/GPIO46 GPIO56 VR_ON SYSON <78,86>
80 121
<9> EC_SMB_DA2 SPOK_3V 15 SDA1_BT/GPIO47 GPIO57 127 VR_ON <11,78,88>
<85,87> SPOK_3V AC_PRESENT SCL4/GPIO08 SMBUS GPIO59
19
<11> AC_PRESENT TS_EN SDA4/GPIO0D
17
<6,38> TS_EN VCCIN_AUX_CORE_VID1_R_EC SCL5/GPIO0B EC_RSMRST#
RB28 0_0402_5% 18 100
SPOK_3V SDA5/GPIO0C FANFB2/GPIO63 EC_SLP_S0IX#_R EC_RSMRST# <11>
B 2 1 101 B
FANFB3/GPIO64 102 VCIN1_ADP_PROCHOT
SPOK_5V 1 RB27 2 0_0402_5% SPOK_3V_5V C38 only GPIO
VCIN1/GPIO65 103 VCOUT1_PROCHOT# VCIN1_ADP_PROCHOT <83>
@ VCOUT1/GPIO66 104 MAINPWON
LAN_PWR_EN VCOUT0/GPIO67 MAINPWON <77,85>
6 105 BKOFF#
<51> LAN_PWR_EN TP_EN GPIO04 GPIO68 BKOFF# <38>
16 106
<63> TP_EN ME_EN OWM/GPIO0A GPIO69 3V_EN_R VCCST_OVERRIDE_LS <11>
25 107
<10> ME_EN FAN_SPEED1 PWM2/GPIO11 GPIO6A
28 108
<77> FAN_SPEED1 29 FANFB0/GPIO14 GWG/GPIO6B EC_PME# <51>
E51TXD_P80DATA 30 FANFB1/GPIO15
<52> E51TXD_P80DATA E51RXD_P80CLK TXD/GPIO16 GPIO AC_IN
For abnormal shutdown 31 110
<52> E51RXD_P80CLK PCH_PWROK RXD/GPIO17 AC_IN/GPIO79 EC_ON AC_IN <84>
32 112
<11,78> PCH_PWROK PWR_SUSP_LED# POWER_FAIL1/GPIO18 GPXIOD02/GPIO7A EC_ON <85>
DB2 34 114 ON/OFFBTN#
<63> PWR_SUSP_LED# VR_PWRGD PWM3/GPIO19 GPIO7B LID_SW# ON/OFFBTN# <63>
RB751V-40_SOD323-2 36 GPIO 115
SPOK_3V_5V EC_RSMRST# <88> VR_PWRGD NUMLED#/GPIO1A GPXIOD04/GPIO7C LID_SW# <63>
1 2 116 SUSP#
GPIO7D SUSP# <15,16,78,84,86>
RB25
DB3 118 H_PECI_R R3966 1 2 43_0402_1% 2 1 VCOUT1_PROCHOT#
RB751V-40_SOD323-2 C38 reserve <11> PBTN_OUT#
122 PECI/GPIO7F H_PECI <7>
0_0402_5%
1 2 PCH_PWROK 123 XCLKI/GPIO5D SW_PROCHOT#
GPIO5E
for Debug, place near KB connector 125 LAN_GPO QB7A @
GPIO7E LAN_GPO <51>
3
AGND
DB4 2N7002KDW_SOT363-6 D D
GND
GND
GND
GND
GND
RB751V-40_SOD323-2 1 KSI4 2 5 VCOUT1_PROCHOT#

EC_VCCST_PG_R TI4 TP@
1 2 1 KSI5 G G
TI5 TP@
TI6 TP@
1 KSI6 KB9052Q-D_LQFP128_14X14 VCOUT1_PROCHOT# is QB7B
11
24
35
94
113
69
TI7 TP@
1 KSI7 SA0000BCG30 high active when QB1 S S 2N7002KDW_SOT363-6
4
20mil mount @
ECAGND
Board ID RB4 PVT@ TO5 TP@

1 KSO5 1 2 BATT_TEMP 2015/1/9 acer require:
+3VLP_EC 12K_0402_5% 1 KSO6 C3882 100P_0201_50V8J
SD028120280
TO6 TP@
1 KSO7 1 2 reserved protact circuit when
TO7 TP@
TO8 TP@
1 KSO8 L16 BLM15AX601SN1D _2P adaptor 107% happen
2
RB4 MP@ 1 KSO11 SM01000KL00

TO11 TP@
RB1 15K_0402_1% 1 KSO12
TO12 TP@
Ra 100K_0402_1% SD034150280 TO13 TP@
1 KSO13
A TO14 TP@ 1 KSO14 ECAGND A
1
AD_BID 2 1 VR_HOT#
ESD RB20 0_0402_5%

VR_HOT# <88>
1
1
RB4 CB4 H_PROCHOT# 2 1 SW_PROCHOT#
SYS_PWROK PCH_PWROK VCOUT1_PROCHOT# <7,84> H_PROCHOT#
Rb 0_0402_5% 0.1U_0201_10V6K RB21 0_0402_5%
EVT@ @
2
2 1
2
CC22 2
100P_0201_50V8J
EMC@
C3883
100P_0201_50V8J
C3878
100P_0402_50V8J
Security Classification
2019/04/12
Compal Secret Data
2020/04/12 Title
1 2 EMC@ Issued Date Deciphered Date
Vinafix.com
Analog Board ID definition, EMC@
Please see page 3.
1
EC_ENE KB9052Q
1.0
5 4 3 2 1
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1K 2.2K
1K
+3VALW_PRIM 2.2K
+3VS
DK27 SOC_SMBCLK
SOC_SMBDATA 2N7002DW
1 SO-DIMM 1
DP24
Ice lake
SOC
SOC_SML0CLK 499
DK24 G-Sensor
499
+3VALW_PRIM
DJ24 SOC_SML0DATA
1K
1K
+3VALW_PRIM
DN22 EC_SMB_CK2
DL22 EC_SMB_DA2
2 2
2.2K
2.2K
+3VLP_EC
77 EC_SMB_CK1 100 ohm EC_SMB_CK1-1 4

SCL1 BATTERY
78 EC_SMB_DA1 100 ohm EC_SMB_DA1-1 3
SDA1 CONN
12
Charger
11
KBC SCL2 79 EC_SMB_CK2
SDA2 80 EC_SMB_DA2
3
KB9052 3
I2C Address Table
BUS Device Address (8 bit)
TM-P3393-003 (TP) 0x2C

I2C_1 (+3VALW_PRIM)
FA577E-1206 (TP-ELAN) 0x15
SA577C-12A0 (TP-ELAN) 0x15
SOC_SMBCLK (+3VS) SO-DIMM1 TBD
G-Sensor 0x30
EC_SMB_CK2 SOC 0x90
(+3VALW_PRIM)
BQ24781 (Charger IC) 0x12
EC_SMB_CK1 (+3VLP)
4 BATTERY PACK 0x16 4

Vinafix.com SMBUS_Routing_Table
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
KB Conn. TP/B Conn.
ON/OFF BTN 30
GND2
JKB1
+3V_PTP
RK1 29 +3VS RK3
100K_0402_5% KSO16 28 GND1 +3VALW 0_0402_5%
2 1 KSO17 27 28 2 @ 1
+3VLP 27
KSO0 26
KSO1 25 26
ON/OFFBTN# KSO2 24 25 UK1 +3V_PTP
<58> ON/OFFBTN# 24 +3V_PTP
KSO3 23 5 1
KSO4 22 23 IN OUT @ CK2
22 1
KSO5 21 2 0.1U_0201_10V6K
2
KSO6 20 21 GND CK1 2 1 JTP1
KSO7 19 20 4 3 1
4.7U_0402_6.3V6M
KSO8 18 19 EN OC 2 RK4 TP_CLK 2 1
18 1 2
DVT: remove SWK1 switch button KSO9 17 CK3 SY6288C20AAC_SOT23-5 10K_0402_5% TP_DATA 3
KSO10 16 17 EC PS2 4 3
1
KSO11 15 16 1U_0201_6.3V6M EC_TP_INT# I2C_1_SDA_R 5 4
KSO12 14 15 2 I2C_1_SCL_R 6 5
KSO13 13 14 TP_PWR_EN <58> PCH I2C EC_TP_INT# 7 6
13 <7,58> EC_TP_INT# TP_EN 7
KSO14 12 8
12 <58> TP_EN 8
KSO15 11 9
KSI0 10 11 TP_PWR_EN follow SYSON behavior 10 GND
KSI1 9 10 GND
KSI2 8 9 ACES_51524-00801-001
KSI3 7 8 CONN@
KSI[0..7] KSI4 6 7
KSI[0..7] <58>
KSI5 5 6 SP01001A900
KSO[0..17] KSI6 4 5 +3V_PTP +3V_PTP
KSO[0..17] <58> 4
KSI7 3
2 3
ON/OFFBTN# 1 2
1
1 RK7 RK10
5
2.2K_0402_5% 2.2K_0402_5%
G
KB BackLight
ACES_85201-2805 QK1B
CONN@ 2N7002KDW _SOT363-6 +3V_PTP
SP01000GO00
2
3 4 I2C_1_SCL_R
S
+5VS <12> I2C_1_SCL
JBL1
1
U1 1
5 1 +5VS_BL 2 1 1 2 RK5 RK6
IN OUT 3 2 RK8 @ 0_0402_5% 4.7K_0402_5% 4.7K_0402_5%
2
2 4 3
G
GND 4
2
4 3 5 QK1A
<58> KBL_EN EN OC GND
6 2N7002KDW _SOT363-6
SY6288C20AAC_SOT23-5 GND 6 1 I2C_1_SDA_R TP_CLK
S
<12> I2C_1_SDA <58> TP_CLK TP_DATA
ACES_51524-0040N-001
D
<58> TP_DATA
1 CONN@
1 @ 2
C3 SP010022M00 RK9 0_0402_5%
0.1U_0201_10V6K
2
LID/B with LED for 17" UMA &DIS

CONN@
+5VALW
SP010025K00
ACES_51530-01001-P01
10 12
9 10 G12 11
8 9 G11
<58> BATT_AMB_LED# 8
<58> BATT_BLUE_LED# 7
6 7
<58> PW R_SUSP_LED# 6
5
<58> PW R_LED# 5
4
3 4
2 3
<58> LID_SW # 2
1
+3VLP 1
JLID2
LED for 15" UMA
LID for 15" DIS
Battery LED
LED1
RG4
680_0402_5% LID/B for 15" UMA 4pin
BATT_AMB_LED# 1 2 3 A 4
+5VALW
15@ MB LID SW remove on UMA SKU
BATT_BLUE_LED# 1 2 1 B 2
RG7 +3VLP
560_0402_5%
LTST-C295TBKF-CA_AMBER-BLUE JLID1
15@
15@ 1
LID_SW # 2 1
3 2 5
Power LED 4 3
4
G1
G2
6
LED2
RG11 ACES_51575-00401-001
680_0402_5% CONN@
PWR_SUSP_LED# 1 2 3 A 4
15@
SP01002BY00
PWR_LED# 1 2 1 B 2
+5VALW
RG10
560_0402_5%
LTST-C295TBKF-CA_AMBER-BLUE
15@
15@

Vinafix.com
Security Classification Compal Secret Data
KB/TP
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
G-Sensor reserved for BA serial

+3VS
1
RZ1 +3VS
10K_0402_5%
GSEN@ UZ1 GSEN@
1 CZ1 1 2 10U_0402_6.3V6M
2
1 8 Vdd_IO 1
4 CS 14 CZ2 1 2 GSEN@
<9,23> SOC_SMBCLK_1 6 SCLSPC Vdd 0.1U_0201_10V6K
<9,23> SOC_SMBDATA_1 SDA/SDI/SDO
+3VS RZ2 1 @ 2 10K_0402_5% 7
RO25 1 GSEN@ 2 10K_0402_5% SDO/SA0 11 G_INT#
16 INT1 9 G_INT2 G_INT# <12>
15 ADC1 INT2 G_INT2 <67>
13 ADC2 10 INT1/2 all High Active
ADC3 RES
2
3 NC 5
NC GND 12
GND
LIS3DHTR_LGA16_3X3
GSEN@
LIS3DH
SA0 ->0, Address is 0011 000 (0x30h)
SA0 ->1, Address is 0011 001 (0x32h)
2 2
TPM 2.0 Finger Print +FP_VCC
SP010020S00
Power Souce Check DVT:update JFP1 define CONN@
JXT_FP201H-008G10M
EGIS ETU801 +FP_VCC=5V 1
USB20_P5_L 1
+3VALW +3VALW_TPM +3VS +3VS_TPM ELAN SA464K-2200 +FP_VCC=3.3V USB20_N5_L
2
3 2
add 1 cap for MLCC downsize 4 3
1 TPM@ 2 1 TPM@ 2 5 4
5
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
RW1 0_0603_5% RW2 0_0603_5% 6

6
0.1U_0201_10V6K
CW2 TPM@
0.1U_0201_10V6K
CW4 TPM@
0.1U_0201_10V6K
CW5 TPM@
0.1U_0201_10V6K
CW6 TPM@
TPM@ CW7
TPM@ CW1
TPM@ CW8
TPM@ CW3
1 1 1 1 7
7
1
8
8
9
near pin1
2
2 2 2 2 10 GND
3 GND 3
JFP1
add 1 cap for MLCC downsize
+3VALW_TPM near pin8,22

+FP_VCC
RW16 1 TPM@ 2 10K_0402_5% TPM_PIRQ# +3VALW RK16 1 FP3V@ 2 0_0603_5% UK6

+5VALW RK17 1 FP5V@ 2 0_0603_5% 5 1
IN OUT
1
UW1 2 FP@
1 GND CK12 LK2 FPEMC@
VSB +3VALW_TPM USB20_P5 USB20_P5_L
2 TPM@ 1 29 4 3 4.7U_0402_6.3V6M 3 4
<11,15,58> PM_SLP_S0# SDA/GPIO0 EN OC 2 <13> USB20_P5 3 4
RW10 0_0402_5% 30 8 1
SCL/GPIO1 VHIO +3VS_TPM
22 CK11 SY6288C20AAC_SOT23-5
6 VHIO FP@ FP@ USB20_N5 2 1 USB20_N5_L
GPIO3 <13> USB20_N5 2 1
2 1U_0201_6.3V6M
SOC_SPI_0_SO RW5 2 TPM@ 1 51_0402_5% TPM_SPI_SO 24 NC 3 2 DLM0NSN900HY2D_4P
SOC_SPI_0_SI TPM_SPI_SI MISO NC FP_PWR_EN <58>
RW13 2 TPM@ 1 51_0402_5% 21 5 SM070005U00
TPM_PIRQ# 2 TPM@ 1 TPM_PIRQ#_R 18 MOSI/GPIO7 NC 7
RW11 0_0402_5% PIRQ/GPIO2 NC 9 DK2 FPEMC@
NC 10 6 3 USB20_N5_L
SOC_SPI_0_CLK RW14 2 TPM@ 1 51_0402_5% TPM_SPI_CLK 19 NC 11 I/O4 I/O2
SOC_SPI_0_CS#2 RW15 2 TPM@ 1 0_0402_5% TPM_SPI_CS#2 20 SCLK NC 12
PLT_RST# RW12 2 TPM@ 1 0_0402_5% TPM_RST# 17 SCS/GPIO5 NC 14
27 PLTRST NC 15 5 2
NC NC +FP_VCC VDD GND
13 26
GPIO4 NC 25
NC 28
4 NC 31 4 1 USB20_P5_L
@ T283 PP/GPIO6 NC I/O3 I/O1
32
4 NC AZC099-04S.R7G_SOT23-6 4
16
GND 23
GND 33
PGND
SOC_SPI_0_SO NPCT750AAAYX_QFN32_5X5
<9> SOC_SPI_0_SO SOC_SPI_0_SI
<9> SOC_SPI_0_SI TPM@
TPM_PIRQ#
<6> TPM_PIRQ#
<9> SOC_SPI_0_CLK
SOC_SPI_0_CLK Security Classification Compal Secret Data Compal Electronics, Inc.
SOC_SPI_0_CS#2 2018/12/27 2019/12/27 Title
<9> SOC_SPI_0_CS#2 PLT_RST# Issued Date Deciphered Date
<11> PLT_RST# Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB & TP & TPM & FP
SA0000AQ230, S IC NPCT750AAAYX QFN 32P TPM (SPI interface) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
A B C D E
A B C D E
+5VS +5VS_HDD
1 2
100mils
RO3 0_0805_5%
10U_0402_6.3V6M
10U_0402_6.3V6M
1 1
1
1
CO16
CO12
CO13
0.1U_0201_10V6K
G_INT2_R @
2
2
2
RO29
0_0402_5% add 1 cap for MLCC downsize
GSEN@
1
HDD JHDD1
FFC Type
14
+5VS_HDD 13 GND
GND
+5VS_HDD 12
11 12
0_0402_5% 10 11
G_INT2 RO4 1 2
GSEN@ G_INT2_R 9 10
<66> G_INT2 9
8
+3VS 7 8
2 RDSATA_CRX_DTX_P0 CO4 1 RD@
2 0.01U_0402_16V7K RDSATA_CRX_C_DTX_P0 6 7 2
RDSATA_CRX_DTX_N0 CO3 1 RD@
2 0.01U_0402_16V7K RDSATA_CRX_C_DTX_N0 5 6
5
B_EQ1
A_EQ2
A_EQ1
4
CO14 4
DEW
RDSATA_CTX_DRX_N0 CO2 1 RD@
2 0.01U_0402_16V7K RDSATA_CTX_C_DRX_N0 3
2 1 RDSATA_CTX_DRX_P0 CO1 1 RD@
2 0.01U_0402_16V7K RDSATA_CTX_C_DRX_P0 2 3
1 2
UO2 1
0.01U_0402_16V7K close to CONN.
20
19
18
17
16
RD@ PS8527CTQFN20GTR2A_TQFN20_4X4 ACES_51625-01201-001
SA00007JU10 CONN@
VDD2
B_EQ1
A_EQ2
A_EQ1
DEW
RD@ SP010028W00
RD@ CO24 2 1 SATA_CTX_C_DRX_P0 0.01U_0402_16V7K 1 15 RDSATA_CTX_DRX_P0
<13> SATA_CTX_DRX_P0 A_INP A_OUTP
RD@ CO25 2 1 SATA_CTX_C_DRX_N0 0.01U_0402_16V7K 2 14 RDSATA_CTX_DRX_N0
<13> SATA_CTX_DRX_N0 A_INN A_OUTN
3 13 B_EQ2
RD@ CO26 2 1 SATA_CRX_C_DTX_N0 0.01U_0402_16V7K 4 GND1 B_EQ2 12 RDSATA_CRX_DTX_N0
<13> SATA_CRX_DTX_N0 SATA_CRX_C_DTX_P0 B_OUTN B_INN RDSATA_CRX_DTX_P0
RD@ CO27 2 1 0.01U_0402_16V7K 5 11
<13> SATA_CRX_DTX_P0 B_OUTP B_INP
21
GND2
REXT
VDD1
SATA_CTX_DRX_P0 1 NRD@ 2 0_0402_5% SATA_CTX_DRX_P0_R RDSATA_CTX_C_DRX_P0

B_DE
A_DE
RO30 CO31 1NRD@2 0.01U_0402_16V7K

SATA_CTX_DRX_N0 RO31 1 NRD@ 2 0_0402_5% SATA_CTX_DRX_N0_R CO29 1NRD@2 0.01U_0402_16V7K RDSATA_CTX_C_DRX_N0
EN
+3VS DVT 02/07 SATA_CRX_DTX_N0 RO32 1 NRD@ 2 0_0402_5% SATA_CRX_DTX_N0_R CO30 1NRD@2 0.01U_0402_16V7K RDSATA_CRX_C_DTX_N0
6
7
8
9
10
+3VS SATA_CRX_DTX_P0 RO33 1 NRD@ 2 0_0402_5% SATA_CRX_DTX_P0_R CO28 1NRD@2 0.01U_0402_16V7K RDSATA_CRX_C_DTX_P0
@@
RO10 1 2 4.7K_0402_5% A_DE RO27 +3VS

RO15 1 2 4.7K_0402_5% 4.99K_0402_1% 1 Co-lay non redriver
@
2 1 CO15
B_DE
A_DE
@
RO13 1 2 4.7K_0402_5% A_EQ1 RD@ 0.1U_0201_10V6K

RO18 1 RD@ 2 4.7K_0402_5% RO6 2 1 RD@
+3VS 4.99K_0402_1% 2
@
RO14 1 2 4.7K_0402_5% A_EQ2

3 3
@
RO19 1 RD@ 2 4.7K_0402_5% RO5 1 2 change ODD pin define

4.7K_0402_5%
ODD FFC Type
@@
RO11 1 2 4.7K_0402_5% B_DE

RO16 1 2 4.7K_0402_5% +5VS_ODD
@
RO12 1 2 4.7K_0402_5% B_EQ1 +5VS_ODD 1

RO17 1 RD@ 2 4.7K_0402_5% 2 1
3 2
3
@
RO20 1 2 4.7K_0402_5% B_EQ2 4

RO21 1 RD@ 2 4.7K_0402_5% 5 4
6 5
6
@@
RO22 1 2 4.7K_0402_5% DEW 7

RO28 1 2 4.7K_0402_5% 8 7
9 8
10 9
PVT 03/13 10
11
SATA_CRX_DTX_P1 ODD@ CO20 1 2 0.01U_0402_16V7K SATA_CRX_C_DTX_P1 12 11
<13> SATA_CRX_DTX_P1 SATA_CRX_DTX_N1 SATA_CRX_C_DTX_N1 12
ODD@ CO18 1 2 0.01U_0402_16V7K 13
<13> SATA_CRX_DTX_N1 13
14
SATA_CTX_DRX_N1 ODD@ CO19 1 2 0.01U_0402_16V7K SATA_CTX_C_DRX_N1 15 14
<13> SATA_CTX_DRX_N1 15
SATA_CTX_DRX_P1 ODD@ CO17 1 2 0.01U_0402_16V7K SATA_CTX_C_DRX_P1 16
<13> SATA_CTX_DRX_P1 16
+5VS +5VS_ODD close to CONN. 17
18 GND17
GND18
1 2
100mils JODD1
RO26 0_0805_5% ACES_51625-01601-001
10U_0402_6.3V6M
10U_0402_6.3V6M
SP01002OK00
ODD@
1@
1
1
CO23
CO22
4
CO21 CONN@ 4
0.1U_0201_10V6K
@
2
add 1 cap for MLCC downsize Security Classification Compal Secret Data Compal Electronics, Inc.
HDD/ODD
A B C D E
5 4 3 2 1
D D
mSATA/SSD JSSD1
KEY M
+3VS +3VS_SSD_NGFF
1 2
GND 3P3VAUX +3VS_SSD_NGFF
3 4
PCIE_CRX_DTX_N13 5 GND 3P3VAUX 6 RM9 1 2
<13> PCIE_CRX_DTX_N13 PCIE_CRX_DTX_P13 7 PERn3 NC 8
<13> PCIE_CRX_DTX_P13 9 PERp3 NC 10 SSD_LED# 0_0805_5%
10U_0402_6.3V6M
10U_0402_6.3V6M
GND DAS/DSS# @ T245 2 1
1
CM30
CM14
CM5 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_N13 11 12
<13> PCIE_CTX_DRX_N13 CM6 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_P13 13 PETn3 3P3VAUX 14 + CM29
<13> PCIE_CTX_DRX_P13 15 PETp3 3P3VAUX 16 150U_B2_6.3VM_R35M
2
PCIE_CRX_DTX_N14 17 GND 3P3VAUX 18 1 CM13 SGA00009M00
<13> PCIE_CRX_DTX_N14 PCIE_CRX_DTX_P14 19 PERn2 3P3VAUX 20 2
<13> PCIE_CRX_DTX_P14 21 PERp2 NC 22 0.1U_0201_10V6K
CM7 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_N14 23 GND NC 24
<13> PCIE_CTX_DRX_N14 CM8 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_P14 25 PETn2 NC 26
<13> PCIE_CTX_DRX_P14 27 PETp2 NC 28 add 1 cap for MLCC downsize
PCIE_CRX_DTX_N15 29 GND NC 30
<13> PCIE_CRX_DTX_N15 PCIE_CRX_DTX_P15 31 PERn1 NC 32
<13> PCIE_CRX_DTX_P15 33 PERp1 NC 34
CM9 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_N15 35 GND NC 36
<13> PCIE_CTX_DRX_N15 CM10 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_P15 37 PETn1 NC 38 RM21 1 2 0_0402_5%
<13> PCIE_CTX_DRX_P15 39 PETp1 DEVSLP 40 SSD_DEVSLP2 <13>
RM16 1 2 0_0201_5% PCIE_CRX_R_DTX_P16 41 GND NC 42 RM20 1 @ 2 0_0402_5%
<13> PCIE_CRX_DTX_P16 RM17 1 2 0_0201_5% PCIE_CRX_R_DTX_N16 43 PERn0/SATA-B+ NC 44
<13> PCIE_CRX_DTX_N16 45 PERp0/SATA-B- NC 46 CM15 1 2 EMC@
CM11 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_N16 47 GND NC 48 100P_0402_50V8J DVR change from 1000p to 100p
<13> PCIE_CTX_DRX_N16 CM12 1 2 0.22U_0201_6.3V6K PCIE_CTX_C_DRX_P16 49 PETn0/SATA-A- NC 50 NGFF_SSD_RST#_R 2 1 PLT_RST_BUF#
<13> PCIE_CTX_DRX_P16 51 PETp0/SATA-A+ PERST# 52 NGFF_CLKREQ#_R RM18 2 1 0_0402_5% PLT_RST_BUF# <11,51,52>
C GND CLKREQ# CLKREQ_PCIE#0 <11> C
53 54 RM5 0_0402_5%
<11> CLK_PCIE_N0 REFCLKN PEWake#
Port P and N follow SATA 55 56
<11> CLK_PCIE_P0 REFCLKP NC
57 58
GND NC
+3VS_SSD_NGFF 59 60 SUSCLK_SSD
NC SUSCLK(32kHz) @ T246
RM22 61 62
10K_0402_5% 63 PEDET(NC-PCIE/GND-SATA) 3P3VAUX 64
1 @ 2 65 GND 3P3VAUX 66
GND 3P3VAUX +3VS_SSD_NGFF
67
GND 68
2 1 SSD_DET# GND1 69
<13> SATAXPCIE2 GND2
RM23 0_0402_5%
BELLW_80159-3221
CONN@
1
D
QM1 2
SP070018L00
BSS138W-7-F_SOT323-3 G
SB00001GC00 S
3
@
SSD_DET# (SATA_GP0)
SATA Device 0
PCIE Device 1
B B
A A

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
M.2 SSD_PCIe/SATA
Document Number Rev
5 4 3 2 1
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
5 4 3 2 1
MP modify
USB3 port reserved
USB3.0 (Port 3) MP modify
DS1~4 change to SC300001Y00 For ESD request
@EMC@
CS3 1 2 USB3_CTX_C_DRX_N3 RS5 1 @ 2 0_0402_5% USB3_CTX_L_DRX_N3 DS23 @EMC@
<13> USB3_CTX_DRX_N3 USB3_CTX_L_DRX_P3 USB3_CTX_L_DRX_P3
.1U_0402_16V7K 1 1 10 9
@EMC@
CS4 1 2 USB3_CTX_C_DRX_P3 RS6 1 @ 2 0_0402_5% USB3_CTX_L_DRX_P3 USB3_CTX_L_DRX_N3 2 2 9 8 USB3_CTX_L_DRX_N3
<13> USB3_CTX_DRX_P3
.1U_0402_16V7K
USB3_CRX_L_DTX_P3 4 4 7 7 USB3_CRX_L_DTX_P3
USB3_CRX_L_DTX_N3 5 5 6 6 USB3_CRX_L_DTX_N3
D D
USB3_CRX_DTX_N3 RS7 1 @ 2 0_0402_5% USB3_CRX_L_DTX_N3 3 3

<13> USB3_CRX_DTX_N3
8
USB3_CRX_DTX_P3 RS8 1 @ 2 0_0402_5% USB3_CRX_L_DTX_P3
<13> USB3_CRX_DTX_P3
AZ1045-04F_DFN2510P10E-10-9
USB2.0 (Port 3)
DS24 EMC@
+5VALW 6 3 USB20_N3_L
LS5 EMC@ +USB3_VCCB I/O4 I/O2
USB20_P3 2 1 USB20_P3_L CS93 +USB3_VCCB
<13> USB20_P3 2 1 1U_0201_6.3V6M US21
1 2 5 1 W=100mils 5 2
C USB20_N3 3 4 USB20_N3_L IN OUT VDD GND C
<13> USB20_N3 3 4 2
DLM0NSN900HY2D_4P GND
SM070005U00 4 3 4 1 USB20_P3_L
<58,73> USB_EN EN OC I/O3 I/O1
SY6288C20AAC_SOT23-5 AZC099-04S.R7G_SOT23-6
+USB3_VCCB
W=100mils
10U_0402_6.3V6M
470P_0402_50V7K
1
1 1
+
CS91
CS94
CS90
150U_B2_6.3VM_R35M
SGA00009M00 2 2 2 @
@
@
B JUSB3 B
1
USB20_N3_L 2 VBUS
USB20_P3_L 3 D-
4 D+
USB3_CRX_L_DTX_N3 5 GND
USB3_CRX_L_DTX_P3 6 StdA-SSRX- 10
7 StdA-SSRX+ GND 11
USB3_CTX_L_DRX_N3 8 GND-DRAIN GND 12
USB3_CTX_L_DRX_P3 9 StdA-SSTX- GND 13
StdA-SSTX+ GND
C-K_26227-8B19-06
DC23300J920
A A

USB3_P2_MB
5 4 3 2 1
Vinafix.com
A B C D E
USB3.0 (Port 1)
DS21 change to SC300001Y00 For ESD request +USB3_VCCB +USB3_VCCA
JPC10
DS21 EMC@ 1 2
USB3_CTX_L_DRX_P1 1 1 USB3_CTX_L_DRX_P1 1 2
@RF@ 10 9
CS21 1 2 USB3_CTX_C_DRX_N1 RS21 1 2 0_0402_5% USB3_CTX_L_DRX_N1 JUMP_43X79 Non charger need short this JP
<13> USB3_CTX_DRX_N1 USB3_CTX_L_DRX_N1 2 2 USB3_CTX_L_DRX_N1
.1U_0402_16V7K 9 8 @
@RF@
CS22 1 2 USB3_CTX_C_DRX_P1 RS22 1 2 0_0402_5% USB3_CTX_L_DRX_P1 USB3_CRX_L_DTX_P1 4 4 7 7 USB3_CRX_L_DTX_P1 modify 11/12
1 <13> USB3_CTX_DRX_P1 1
.1U_0402_16V7K
USB3_CRX_L_DTX_N1 5 5 6 6 USB3_CRX_L_DTX_N1
3 3
@RF@
USB3_CRX_DTX_N1 RS24 1 2 0_0402_5% USB3_CRX_L_DTX_N1 8
<13> USB3_CRX_DTX_N1
@RF@ AZ1045-04F_DFN2510P10E-10-9
USB3_CRX_DTX_P1 RS25 1 2 0_0402_5% USB3_CRX_L_DTX_P1
<13> USB3_CRX_DTX_P1
DS22 EMC@
6 3 USB20_N1_L +USB3_VCCA
LS2 EMC@ I/O4 I/O2
USB20_N1 2 1 USB20_N1_L +USB3_VCCA W=100mils
<13> USB20_N1 2 1
5 2 1
USB20_P1 3 4 USB20_P1_L VDD GND
<13> USB20_P1 3 4 1 1
10U_0402_6.3V6M
CS26
470P_0402_50V7K
CS95
CS25 +
DLM0NSN900HY2D_4P 220U_6.3V_ESR18M_6.3X4.5
SM070005U00 4 1 USB20_P1_L SF000006R00
I/O3 I/O1 2 2 2 @
@
AZC099-04S.R7G_SOT23-6
USB3.0 Conn.
JUSB1
USB3_CTX_L_DRX_P1 9
1 SSTX+
USB3_CTX_L_DRX_N1 8 VBUS
USB20_P1_L 3 SSTX-
2 7 D+ 2
USB20_N1_L 2 GND 10
USB3_CRX_L_DTX_P1 6 D- GND 11
4 SSRX+ GND 12
USB3_CRX_L_DTX_N1 5 GND GND 13
SSRX- GND
ACON_TARBA-9U1393
CONN@
LTCX008KB00
Symbol:DC23300N800
compatible: DC23300TT00
3 3
4 4

USB3_P1_MB
A B C D E
A B C D E
I/O Borad (USB2 /Card reader/ Speaker-RCH)

USB2 I/O PVT:change to SP01001KD00 footprint 22
GND
21
RS157 1 @ 2 0_0402_5% USB20_L_P4 +5VALW GND
<13> USB20_P4
20
RS158 1 @ 2 0_0402_5% USB20_L_N4 19 20
<13> USB20_N4 18 19
17 18
16 17
1 15 16 1
14 15
13 14
<56> SPK_R+ 13
12
11 12
<56> SPK_R- 11
10
9 10
Card reader Reserved CMC on SUB/B side 9
8
<58,71> USB_EN 8
7
USB20_L_N8 6 7
USB20_L_P8 5 6
4 5
USB20_L_N4 3 4
USB20_L_P4 2 3
1 2
RS159 1 @ 2 0_0402_5% USB20_L_N8 1
<13> USB20_N8
JIO1
USB20_L_P8 CONN@
RS160 1 @ 2 0_0402_5%
<13> USB20_P8
SP01001KD00
ACES_51522-02001-P02
2 2
3 3
4 4

IO/LiD/LED
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Issued Date 2017/11/23 2018/09/01 Title
Vinafix.com
Deciphered Date
eDP MUX
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
A B C D E
A B C D E
FAN1 Conn Screw Hole

+5VS
40mil
RF1 1 2 0_0603_5% +VCC_FAN1 H1 H2 H3 H5 H6 H7 H8
1 2 H_3P0-G H_3P0-G H_3P3 H_3P3 H_3P3 H_3P0-G H_4P5X4P0
1 FD1 FD2 1
XEMC@ CF2 CF1
1000P_0402_50V7K 4.7U_0402_6.3V6M
1
2 1 @ @
1
FIDUCIAL_C40M80 FIDUCIAL_C40M80
@ @ @ @ @ @ @
FD3 FD4
@ @
1
+3VS H20 H22 FIDUCIAL_C40M80 FIDUCIAL_C40M80
H_2P0N H_2P7X2P0N
1
RF2 @ @
1
10K_0402_5%
40mil
JFAN1
2
+VCC_FAN1 1
FAN_SPEED1 2 1
<58> FAN_SPEED1 FAN_PWM1 3 2
<58> FAN_PWM1 4 3
1 4
5
6 G1
CF3 G2
2 1000P_0402_50V7K ACES_50278-00401-001
XEMC@ CONN@
SP02000RR00
2 2
Reset Circuit
+3VLP
RG1 1 @ 2 0_0402_5%
MAINPWON <58,85>
2
RG3 RG2 1 2 0_0402_5%
EC_RST# <58>
10K_0402_5%
6
D
BI_GATE# 2
G 2N7002KDW_SOT363-6
BI_GATE PH to +RTCVCC at PWR side QG1A
3
D 1 S
1
BI_GATE 5
3 <83> BI_GATE G C70 3
QG1B 0.1U_0201_10V6K
2N7002KDW_SOT363-6 S 2
4
Reset Button
MP modify
SWG2
BI_GATE 1 2 BI_GATE
3 4
TS-A45U-2-S085_4P
4 4

FAN & Screw Hole & Reset
A B C D E
A B C D E
DC Interface JW7110DFNC_DFN14_2X3
15
CQ5
.1U_0402_16V7K
1 2
RQ2
+5VALW
1U_0201_6.3V6M
CQ8 1 2
7
6 VIN2
VIN2
GPAD
VOUT2
VOUT2
8
9 +5VS_OUT 1
@ JPQ2
1 2
2
+5VS
For Power ON/Off Sequence
0_0402_5% PM_SLP_S3
SUSP# 2 1 5VS_ON 5 10 1 2 JUMP_43X118 +3VALW
ON2 CT2
2
CQ1 1000P_0402_50V7K
G
1
1 2 4 11 Q1A
+5VALW VBIAS GND
CQ4 .1U_0402_16V7K R24 2N7002KDW_SOT363-6
@ 3 12 100K_0402_5%
1 ON1 CT1 1 6 1
2 CQ10
S
EC_VCCST_PG_R <11,58>
.1U_0402_16V7K
D
2 13
2
1 VIN1 VOUT1 14
VIN1 VOUT1
MOW14, For tCPU28 200us(max)
@ SLP_S3# to VCCST_PWRGD deassertion
5
1 UQ1
G
Q1B
Q2A 2N7002KDW_SOT363-6
2N7002KDW_SOT363-6 4 3
S
VR_ON <11,58,88>
D
1 2 D
2 MOW14, For tPLT17 200us(max)
JW7110DFNC_DFN14_2X3 <11,15> PM_SLP_S3# G
CQ7 SLP_S3# to IMVP VR_ON deassertion
5
15 .1U_0402_16V7K
G
+3VALW GPAD S
1
1U_0201_6.3V6M 7 8 @ JPQ3 Q2B
CQ9 1 2 6 VIN2 VOUT2 9 +3VS_OUT 1 2 2N7002KDW_SOT363-6
VIN2 VOUT2 1 2 +3VS
4 3 SUSP#
S
3VS_ON 5
D
SUSP# 2 1 10 1 2 JUMP_43X118
ON2 CT2
RQ1 0_0402_5% CQ3 1000P_0402_50V7K MOW14, For tPLT18 200us(max)
4 11 SLP_S3# to VCCIO VR disable
+5VALW VBIAS GND
2
1 2
G
CQ2 .1U_0402_16V7K 2 CQ11 3 12 Q3A @
ON1 CT1
.1U_0402_16V7K
@ 2N7002KDW_SOT363-6
2 13
@ 1 VIN1 VOUT1 14 1 6
S
1 VIN1 VOUT1 SYS_PWROK <11,58>
D
UQ2
5
G
+3VALW Q3B @
2N7002KDW_SOT363-6
1
2 4 3 2
S
PCH_PWROK <11,58>
D
R29
100K_0402_5%
+5VALW +0.6VS_VTT
+2.5V +1.2V_VDDQ +5VALW
2
Q6A PM_SLP_S4
2
2N7002KDW_SOT363-6
2
5
R25 R26 D
G
2
100K_0402_5% @ @ 100K_0402_5% R31 R27 R28 2 Q6B
<11> PM_SLP_S4# G
100K_0402_5% 100K_0402_5% 100K_0402_5% 2N7002KDW_SOT363-6
@ @ @
1
SUSP +0.6VS_VTT_R S 4 3 SYSON
S
1
D
MOW14, For tPLT15 200us(max)
1
Q4A @ Q4B @ SLP_S4# to VDDQ ramp down
2N7002KDW_SOT363-6 2N7002KDW_SOT363-6 +1.2V_VDDQ_R SYSON#
6
D D D
2 5 SUSP 2 SYSON# Q5A @ Q5B @
<15,16,58,84,86> SUSP# G G G 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
3
Q7 S D D
3
1
S S L2N7002WT1G_SC-70-3 SYSON# 2 5 SYSON

@ SYSON <58,86>
1
R30 G G
10K_0402_5%
@ S S
4
2
3 3
4 4

DC Interface
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve Page
A B C D E
5 4 3 2 1
D D
PWR-Reserve Page C
B B
A A
Title
<Title>
Size Document Number Rev

Vinafix.com A <Doc> <RevCode>

5 4 3 2 1
A B C D E
1 1
+19V_ADPIN 5A_Z120_25M_0805_2P
EMI@ PL101
+19V_VIN
@ PJP101 1 2
ACES_50278-00401-001
6
G2 5
G1
1
4
4
1
3 EMI@ PC104
3 2 EMI@ PC105 PC102 EMI@ 1000P_0402_50V7K
2
2 1 1000P_0402_50V7K 100P_0402_50V8J
2
1
2 2
@
PR101
1 2
+3VLP +CHGRTC
0_0402_5%
3 3
4 4
2018/12/27
Compal Secret Data
2019/12/27 Title
PWR DCIN / Pre-charge
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH7LW M/B LA-H791P
A B C D E
A B C D E
1 1
PR207 100_0402_1%
MB:Battery Con Put TOP Side 1 2
EC_SMB_DA1 <58,84>
PR205 100_0402_1%
1 2
EC_SMB_CK1 <58,84>
Battery Bot Side PR202

200K_0402_1%
1 2
PIN1 GND @ PJP201 +3VLP
1
PIN2 GND 1 2 1 2
2 3 BATT_TEMP <58,84>
PIN3 SMD 3 4
EC_SMB_DA1-1
EC_SMB_CK1-1 PR203 1K_0402_1%
PIN4 SMC 4 5
5 6
BATT_TS
BATT_B/I
PIN5 TEMP 6 7
7 8
PIN6 BI 8 9 +RTCVCC
PIN7 Batt+ GND 10
GND
PIN8 Batt+ CVILU_CI9908M2HR0-NH
2016/11/16 update
1
PR212
100K_0402_5% For KB9022
PQ201 Change to SB00000QO00,
sense 20mΩ Active Recovery
SB501380010(BSS138LT1G Del)
2
2 2
1
D
<77> BI_GATE 2 PQ201
G LBSS139LT1G 1N SOT-23-3 45W PR206 58.5W,1V Active=recovery
+12.6V_BATT+ S 2.32K ohm
3
EMI@ PL201
2
5A_Z120_25M_0805_2P @
1 2 PR217
change PL201, PL202 +12.6V_BATT 0_0402_5%
65W PR206 84.5W,1V
PL202
SM01000C000 to comm 7.87K ohm Active=recovery
1 2
part SM01000P200
1
5A_Z120_25M_0805_2P
EMI@ 90W PR20K __W,__V
ohm Active=recovery
1
EMI@ PC201 EMI@ PC202

1000P_0402_50V7K 0.01U_0402_25V7K PH1 under CPU botten side :
2
PH1 2V 1V CPU thermal protection at 89 +-3 degree C

Recovery at 56 +-3 degree C
2013/06/07
Add for ENE9022 Battery Voltage drop detection.
Connect to ENE9022 pin64 AD1.
3 +3VLP_ECA 3
ADP_I <58,84>
+19VB_5V
VAL50/ZAL20 Battery is 3-cell NVDC design.
1
B+=9V PR204
Change PR12=50k if Battery is 2-cell NVDC design 16.9K_0402_1%
45W@ PR206
B+=6V
1
2.32K_0402_1%
2
PR209 65W@
VCIN0_PH <58>
750K_0402_1%
@ PR206
7.87K_0402_1%
PR210
2
1
1
1 2
VCIN1_BATT_DROP <58> PC203 must close to EC pin
2
PH201
VCIN1_ADP_PROCHOT <58>
@ PC203
0_0402_5% 100K_0402_1%_NCP15WF104F03RC 0.1U_0402_25V6
1
1
1
2
2
PC204 PR211 PR208

0.1U_0402_25V6 150K_0402_1%
T202 T201 must close to PH201
T202@ 10K_0402_1%
1
2
T201@
ECAGND <58>
4 4
2018/12/27
Compal Secret Data
2019/12/27 Title
PWR-BATTERY CONN/OTP
A B C D E
A B C D E
PRB1 PQB2
1
D AON7506_DFN33-8-5
1M_0402_1%
2 1 2
PQB1 +19VB 1
G L2N7002SW T1G_SOT323-3 2 +12.6V_BATT_CHG
PRB2 S 5 3
3
2 1
+19V_P1 +19V_P2
PQB3 3M_0402_5% PQB4
4
EMB04N03H_EDFN5X6-8-5 AON7506_DFN33-8-5
1 1
PRB3
0.01_1206_1% EMI@ PLB1
+19V_CHG
2 2 HCB2012KF-121T50_0805
5 3 3 5 1 4 1 2
+19V_VIN
2 3
10U_0603_25V6M
PCB8 @ 10U_0603_25V6M
0.047U_0603_25V7M
4
4
1 1
PCB2
10U_0603_25V6M
1000P_0402_50V7K
2200P_0402_50V7K
1 2
1
1
PCB1
PCB3
PCB4
ACP ACN
68P_0402_50V8J
0.1U_0402_25V6
0.1U_0402_25V6
1
1
@EMI@ PCB5
EMI@ PCB6
PCB9
EMI@ PCB10
0.022U_0603_25V7K
2
4.7_0603_1%
4.02K_0402_1%
2
10_0402_1%
PRB4
PCB12
PCB11
2
0.1U_0402_25V6 PCB13
PRB5
PRB6
EMI@
2 1 1 2 1 2
PCB7
1 0.01U_0402_25V7K~N
2
ACDRV_CHGR_R 0.1U_0402_25V7K
PRB7
4.02K_0402_1% BATDRV_CHGR
ACFET MDU1512 SB00000SY00 1 2 ACDRV_CHGR
1
@ PRB8 @ PRB9
Rds(on):4.2~5m Ohm 0_0402_5% 0_0402_5%
Vgs=20V
Vds=30V 2 1CMSRC_CHGR BATSRC_CHGR
ID= 24.2A (Ta=70C) PRB10
2
4.02K_0402_1%
ACN_CHGR
ACP_CHGR
+19V_VIN
PDB1 PRB12 @ PCB15
S SCH DIO BAS40CW SOT-323 10_1206_5% 1000P_0402_50V7K 2016/03/13 SE158225K80 X1
+19V_VIN
3 1 2 down size SE00000WP00 S
1
1 2 1
PRB11 +19VB 2 ACDRV_CHGR CER CAP 2.2U 25V K X5R 0603 PQB5
422K_0402_1% PCB16 1U_0603_25V6K +6V_CHG_REGN
2 1 PCB18
2.2U_0603_25V7M
2
5
2 ACDET PUB1 2
AON7506_DFN33-8-5
1 2 Choke 4.7uH SH00000YC00 (Common Part)
ACDRV
ACP
ACN
28
VCC PRB14
(Size:6.6 x 7.3 x 3 mm)
66.5K_0402_1%
(DCR:28m~33m)
1
CMSRC_CHGR 3 24 0_0603_5%
CMSRC REGN
1
2DH_CHGR_R 4
PRB13
@ PCB19 1
6 PRB16
PCB17 0.047U_0603_25V7M
2200P_0402_25V7K ACDET 25 BST_CHGR1 2BST_CHGR_R 1 2
2
11 BTST
<58,83> EC_SMB_DA1 +12.6V_BATT
2
SDA
3
2
1
12 26 UG_CHGR 0_0603_5% PRB19
<58,83> EC_SMB_CK1 SCL HIDRV PLB2 0.01_1206_1%
ACPRN_CHGR 5 4.7UH_PCMB063T-4R7MS_8A_20%
<58,83> ADP_I PCB20 ACOK 27 LX_CHGR 1 2 1 4
1 2 PRB18 1 2 0_0402_5% 7 PHASE
IADP 2 3
1
100P_0402_50V8J IDCHG 8 23 LG_CHGR PQB6
4.7_1206_5%
IDCHG LODRV
EMI@ PRB20
1 2 9
10U_0603_25V6M
10U_0603_25V6M
PMON
AON7506_DFN33-8-5
@ PCB21 10 22 PRB22 316K_0402_1% SRP SRN
1SNUB_CHGR 2
/PROCHOT GND
1
1 2
PCB22
PCB23
100P_0402_50V8J
@ +3VLP 4
<58> IDCHG PRB24 78.7K_0402_1%
PRB23
2
13 21 ILIM_CHGR 1 2
1 2 GND ILIM PRB25
680P_0402_50V7K
<7,58> H_PROCHOT# 14 10_0402_1%
3
2
1
NC 20 SRP_CHGR 1 2
EMI@ PCB24
@
0_0402_5% PRB26 SRP
1 2 15 19 SRN_CHGR 1 2
20160601 colay BQ24781
2
/BATPRES SRN
3 PRB27 3
0_0402_5% 16 18 BATDRV_CHGR 10_0402_1% PCB25
/TB_STAT BATDRV 0.1U_0402_25V6
29 17 BATSRC_CHGR 1 2
PWPD BATSRC
For 4S per cell 4.35V battery <58,83> BATT_TEMP
CHG_TB_STAT BQ24781RUYR_W QFN28_4X4
+6V_CHG_REGN
ACDET 3.3*100/(316+100)=0.79 H/L Side AON7506 SB000010A00
0.1U_0402_25V6
0.1U_0402_25V6
@ PRB36
ICHG= 0.79 /(20*0.01)=3.95A Rds(on):13~15.8mohm
1
PCB26
PCB27
10K_0402_1%
1 2 Vgs=20V
1
4S_BATT@ 3.3*78.7/(316+78.7)=0.66 Vds=30V
2
PRB28 ICHG= 0.66 /(20*0.01)=3.28A ID= 10.5A (Ta=70C)
2M_0402_1%
+6V_CHG_REGN
1 2
4S_BATT@
PRB31
0_0402_5%
1
PRB32
2
10K_0402_1%
PRB34
1
4S_BATT@ 10K_0402_1%
2
PQB7 1 2 ACPRN_CHGR
4S_BATT@ PRB33 LTC015EUBFS8TL_UMT3F <58> AC_IN 1
100K_0402_1%
1 2 2 PRB35
<58> BATT_4S
4 12K_0402_1% 4
2
4S_BATT@
3
1
PQB9 D
2
<15,16,58,78,86> SUSP# G
L2N7002SW T1G_SOT323-3S
3
2018/12/27 2019/12/27
Vinafix.com Issued Date Title
Deciphered Date
charger
A B C D E
A B C D E
PR302
499K_0402_1%
ENLDO_3V 1 2
EN1 and EN2 dont't floating +19VB
1
150K_0402_1%
+19VB
PR303
EMI@ PL301 @ PC302
PR304
FBMA-L11-201209-800LMA50T 0.1U_0402_25V7K
1 +19VB_3V BST_3V 1
1 2 1 2 1 2
2200P_0402_50V7K
10U_0603_25V6M
10U_0603_25V6M
2
EMI@ PC301
@EMI@ PC303
EMI@ PC304
0.1U_0402_25V6
0.1U_0402_25V6
1
1
0_0603_5%
@ PC305
PC306
1
PU301
2
PL302
BS
IN
IN
IN
IN
1.5UH_6A_20%_5X5X3_M
LX_3V 6 20 LX_3V 1 2
LX LX +3VALWP
7 19
GND LX
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
8 18
+3VALWP GND GND
@ PC307
PC308
PC309
@ PC310
PC311
PC312
SY8286BRAC_QFN20_3X3 @EMI@
SPOK_3V 9 17 PR305
+3VLP
2
PG LDO 4.7_1206_5%
1 3V_SN
10 16
2
NC NC
1
PC313
OUT
EN2
EN1
21 4.7U_0402_6.3V6M
NC
FF
2
PR301 GND @EMI@
100K_0402_5% PC314
11
12
13
14
15
680P_0402_50V7K
2
Vout is 3.234V~3.366V
<58,87> SPOK_3V
3.3V LDO 150mA~300mA
ENLDO_3V PC315 PR306

1000P_0402_50V7K 1K_0402_5%
3V_FB 1 2 1 2
<58> 3V_EN
@ PJ301
+3VALWP 1 2 +3VALW
1 2
keep short pad, JUMP_43X118
2 snubber is for EMI only. 2
+19VB_5V
+19VB EMI@ PL501 @ PC502
PR502
FBMA-L11-201209-800LMA50T 0.1U_0402_25V7K
1 2 +19VB_5V 1BST_5V 2 BST_5V_R 1 2
Choke 1.5uH SH00000II00, SH000008800, SH000019B00
2200P_0402_50V7K
0.1U_0402_25V6
0.1U_0402_25V6
0_0402_5% (Size:6.8 x 6.47 x 3 mm)

10U_0603_25V6M
10U_0603_25V6M
PU501
(DCR:14m~15m Ohm)
5
1
SY8288CRAC_QFN20_3X3
1
1
@EMI@ PC501
PC503
PC504
EMI@ PC505
@EMI@ PC506
BS
IN
IN
IN
IN
PL502
LX_5V 6 20 1.5UH_MMD-06CZ-1R5M-V1_9A_20%
2
LX LX
7 19 LX_5V 1 2
GND LX +5VALWP
8 18
GND GND
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
+3VLP
1
9 17 VCC_5V 1 2
PG VCC
1
PR503
PC508
PC509
PC510
PC511
PC512
PC513
4.7_1206_5%
@EMI@
10 16 PC507
2
NC NC
1
2.2U_0402_6.3V6M
OUT
LDO
EN2
EN1
21 @
FF
PR501 GND
2
100K_0402_5%
11
12
13
14
15
2
15V_SN
680P_0402_50V7K
<58> SPOK_5V +5VLP
@EMI@
ENLDO_5V
PC514
5V LDO 150mA~300mA
4.7U_0402_6.3V6M
2
1
PC515
PR504
2.2K_0402_5% 5V_3V_EN
2
1 2 Iocp=12A
<58> EC_ON PR505
@
1 2 EN1 and EN2 dont't be floating.
3
<58,77> MAINPWON EN :H>0.8V ; L<0.4V PC516 PR506 @ PJ501
3
1000P_0402_50V7K 1K_0402_1% +5VALWP 1 2 +5VALW
0_0402_5% 5V_FB 1 2 5V_FB_1 1 2 1 2
Fsw : 600K Hz
JUMP_43X118
5V_3V_EN
1M_0402_1%
1
1
PR507
PC517
4.7U_0402_6.3V6M
2
2
PR509
499K_0402_1%
ENLDO_5V 1 2
+19VB
1
150K_0402_1%
PR508
4 4

+3VALW/+5VALW
Custom 0.2
A B C D E
A B C D E
Pin19 need pull separate from +1.35VP.

+19VB_1.2VP If you have +1.35V and +0.675V sequence question, 0.6Volt +/- 5%
@ PJM1 you can change from +1.35VP to +1.35VS. TDC 0.7A
JUMP_43X79
1
1 2 +19VB_1.2VP PRM1 Peak Current 1A 1
+19VB 1 2 2.2_0603_5%
BST_1.2VP_R 1 2 BST_1.2VP
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
0.1U_0402_25V6
+1.2VP
1
@EMI@ PCM1
EMI@ PCM2
PCM3
PCM4
UG_1.2VP +0.6VSP
2
PQM1
AON7408L_DFN8-5
LX_1.2VP
10U_0402_6.3V6M
10U_0402_6.3V6M
5
1
PCM5
1
PCM6
PCM7
0.1U_0402_25V7K
16
17
18
19
20
2
2
VLDOIN
PHASE
UGATE
BOOT
VTT
4 21
PAD
LG_1.2VP 15 1
LGATE VTTGND
PLM1
1
2
3
14 2
1UH_11A_20%_7X7X3_M PRM2 PGND VTTSNS
30.9K_0402_1% PUM1
1 2LX_1.2VP 1 2 CS_1.2VP 13 3
+1.2VP PCM8 CS RT8207PGQW _W QFN20_3X3 GND
1
1U_0402_10V6K
5
1 2 12 4 VTTREF_1.2VP
@EMI@ PRM3 PRM4 VDDP VTTREF
2 4.7_1206_5% 5.1_0603_5% 2
1 2 VDD_1.2VP 11 5
+5VALW +1.2VP
1 2
VDD VDDQ
1
PGOOD
PCM12
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
TON
1
PCM9
PCM13
PCM14
PCM10
PCM15
PCM16
@EMI@ PCM11 PCM17 0.033U_0402_16V7K
FB
S5
S3
2
1
680P_0402_50V7K
2
2 PQM2 1U_0402_10V6K
10
6
AON7506_DFN3X3-8-5 PRM5
1
2
3
2.2_0402_1%
FB_1.2VP
2
TON_1.2VP
EN_1.2VP
PRM6
+5VALW
EN_0.6VSP
6.19K_0402_1%
PRM7 1 2 +1.2VP
470K_0402_1%
+19VB_1.2VP 1 2
1
PRM8 Vout=0.75V* (1+Rup/Rdown)
<58,78> SYSON
SYSON 1 2 PRM9 =0.75*(1+(6.19/10))
10K_0402_1%
0_0402_5% =1.21V
2
1
@ PCM18
+5VALW 0.1U_0402_10V7K
2
+3VALW @ PRM10
0_0402_5%
1 2
<15,16,58,78,84> SUSP#
@ PJM2
3 JUMP_43X39 @ @ PJM3 3
PRM11
1
1 2 VIN_2.5V PCM19 JUMP_43X118

1 2 1U_0402_6.3V6K 1 2 1 2
+1.2VP +1.2V_VDDQ
<8> SM_PG_CTRL 1 2
2
0_0402_5%
1
1
@ PCM21 @ PJM4
PCM20 JUMP_43X39
4.7U_0402_6.3V6M 0.1U_0402_10V7K 1 2
+0.6VSP +0.6VS_VTT
2
2
PUM2 1 2
G9661MF11U_SO8
@ 4 5
PRM12 VPP NC
3 6 MOSFET: 3x3 DFN
SYSON 1 2 EN_2.5V 2 VIN VO 7 +2.5VP
H/S Rds(on): 27mohm(Typ), 32mohm(Max)
GND
1 VEN ADJ 8
22U_0603_6.3V6M
0.01U_0402_25V7K
POK GND Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C

1
0.1U_0402_16V7K
PCM23
0_0402_5% PRM14
9
1
1
PCM22
PCM24
PRM13
21.5K_0402_1%
Rup L/S Rds(on): 13mohm(Typ), 15.8mohm(Max)
Vout=0.8V* (1+(21.5/10)) = 2.52V 0.8% Idsm: 12A@Ta=25C, 10.5A@Ta=70C
2
1M_0402_5%
2
2
2
@ FB_2.5V Choke: 7x7x3

Rdc=14mohm(Typ), 15mohm(Max)
1
Mode Level +0.6VSP VTTREF_1.2V

PRM15
S5 L off off Switching Frequency: 538kHz
10K_0402_1%
Rdown S3 L off on Ipeak=7.5A
S0 H on on Iocp=Ipeak*1.2A
2
4
OVP: 110%~120% 4
@ PJM5
Note: S3 - sleep ; S5 - power off VFB=0.75V, Vout=1.365V
JUMP_43X39
1 2 MOSFET footprint: SIS412DN
+2.5VP 1 2 +2.5V

RT8207P
A B C D E
A B C D E
@ PJ1802
JUMP_43X39
1 2
+1.8VALWP 1 2 +1.8VALW_PRIM
1 1
Imax= 2A, Ipeak= 3A

FB=0.6V
PC1801
22U_0603_6.3V6M
1 2 PU1801 PL1801
@ PJ1801 SY8032ABC_SOT23-6
1UH_MHCD252012A-1R0M-A8S_3A_20%
+3VALW 1
JUMP_43X79
2 IN_1.8V 4 3 LX_1.8V 1 2
1 2 IN LX +1.8VALWP
1 2 5 2
+3VALW
68P_0402_50V8J
PR1801 100K_0402_5% PG GND
1
6 1
PC1802
22U_0603_6.3V6M
22U_0603_6.3V6M
FB EN
1
1
PC1803
PC1804
<91> 1.8VALW_PG
2
@EMI@ PR1802 PR1803
2
PR1804 0_0402_5% 4.7_0603_5% 20K_0402_1%
1 2 +1.8V_EN
<58,85> SPOK_3V
2
Rup
2
0.1U_0402_16V7K
1
PC1805
1
PR1805 FB_1.8V
1M_0402_1%
1
@
2
@EMI@ PC1806
680P_0402_50V7K PR1806
2
10K_0402_1%
Rdown
2
2
Note: 2
When design Vin=5V, please stuff snubber
to prevent Vin damage
Vout=0.6V* (1+Rup/Rdown)
1.8 = 0.6*(1 + 20k/10k)
3 3
4 4

SY8032
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
A B C D E
1 2 3 4 5
Module model information

RT3612EB_2Phase_V1A.mdd for IC portion
RT3612EB_2Phase_V1B.mdd for SW portion
A A
RT3612EBGQW-02 is not MP part

+5VALW PUZ1
PRZ2 +19VB_VCCIN
6.8_0603_1% PRZ3 2.2_0805_5%
1 2 VCC_RT3612 10 22 VIN_RT3612 1 2
VCC VIN PCZ2 0.47U_0402_25V6K
2
1 2
PCZ1
4.7U_0402_6.3V6M
1
PRZ1 PRZ4 0_0402_5%
2.2_0603_1%
VRON
23 VRON_RT3612 1 2
VR_ON
High: > 0.7V
<11,58,78>
1 2 PVCC_RT3612 29
PVCC
@ PCZ3 0.1U_0402_25V6
1 2 Low: < 0.3V
2
PCZ4
Pull High in HW site. 4.7U_0402_6.3V6M 25
BST1_VCCIN <89>
1
BOOT1
<58> VR_HOT# PRZ5
75_0402_5% 26
VRHOT_RT3612 UGATE1 UG1_VCCIN <89>
1 2 2
VR_HOT
VREF06_RT3612 0.6V 27
VREF06_RT3612
PRZ6 PHASE1 LX1_VCCIN <89>
3.9_0402_1%
1 2 12 28
VREF06 LGATE1 LG1_VCCIN <89>
1
750_0402_1%
68.1K_0402_1%
16.9K_0402_1%
PCZ5
1
8.2K_0402_1%
1
0.47U_0402_6.3V6K
PRZ7
PRZ8
PRZ9
PRZ10
2
B B
VR_HOT# 110 degreeC 1

2
BST2_VCCIN <89>
2
BOOT2
ALERT# 107 degreeC
1.74K_0402_1%
1
PRZ15 41.2K_0402_1% 32
62K_0402_1%
560_0402_1%
3.4K_0402_1%
UGATE2 UG2_VCCIN <89>

1
1 2
PRZ14
PRZ11
PRZ12
PRZ13
Close to Phase1 MOS 31 LX2_VCCIN <89>

PHZ1 TSEN_RT3612 21 PHASE2
2
TSEN_RT3612_R 1 2 TSEN
2
30
LGATE2 LG2_VCCIN <89>
220K_0402_5%_B25/50 4700K
SET1_RT3612 8 PRZ16 2.61K_0603_1% PRZ17 2.1K_0603_1%
SET1 20 ISENSE1P_VCCIN_RR 1 2 ISENSE1P_VCCIN_R
1 2
SET2_RT3612 ISEN1P ISENSE1P_VCCIN <89>
7
SET2
1
7.68K_0402_1%
1
15.8K_0402_1%
PRZ19
1
SET3_RT3612 6 PCZ6
4.53K_0402_1%
PRZ18
SET3
680_0402_1% 510_0402_1%
+1.05V_VCCST 0.1U_0402_25V6
1
PRZ20
24K_0402_1%
2
1
PRZ21
19 ISENSE1N_VCCIN_R1 2
PRZ22
ISENSE1N_VCCIN <89>
2
ISEN1N PCZ7 0.1U_0402_25V6
2
PRZ23 681_0402_1%
2
1 2
1 2
15K_0402_1%
1
1 2
PRZ27 2.61K_0603_1% PRZ29 2.1K_0603_1%

1.5K_0402_1%
17 ISENSE2P_VCCIN_RR 1 2 ISENSE2P_VCCIN_R 1 2
PRZ24
PRZ25
ISEN2P ISENSE2P_VCCIN <89>

PRZ26
15K_0402_1%
100_0402_1%
45.3_0402_1%
1
1
PRZ30
PRZ28
PCZ8
0_0402_5%
2
0.1U_0402_25V6 PCZ9
PRZ31
PRZ32
PRZ33
2
0.1U_0402_25V6
2
4.53K_0402_1%
2
2
@ 18 ISENSE2N_VCCIN_R1 2
ISENSE2N_VCCIN <89>
2
2
ISEN2N PCZ10 0.1U_0402_25V6
1
PRZ34 681_0402_1%
PRZ35 0_0402_5% 1 2 +VCCIN
1 2 SVID_CLK_PWR_VCCIN 5
<15> CPU_SVID_CLK_R VCLK
2
C C
PRZ37 0_0402_5% PRZ36

1 2 SVID_DAT_PWR_VCCIN 4 100_0402_1%
<15> CPU_SVID_DAT_R VDIO
1
PRZ38 0_0402_5% 0_0402_5%
1 2 SVID_ALERT#_PWR_VCCIN 3 14 VSEN_VCCIN PRZ39 1 2
<15> CPU_SVID_ALERT#_R ALERT VSEN VCC_SENSE_VCCIN <15>
PCZ11 82P_0402_50V8J PCZ12 330P_0402_50V7K @ PCZ13
+3VS 15 COMP_VCCIN 1 2 1 2 1 2
0.082U_0402_16V7K
PRZ40 10K_0402_1% COMP
1 2 24 PRZ41 23.7K_0402_1% PRZ42 8.45K_0402_1% 330P_0402_50V7K
@ PCZ14
VR_READY
1
1 2 1 2
@ PCZ15
<58> VR_PWRGD LL=2m
2
0.47U_0402_6.3V6K 16 FB_VCCIN
1 2 FB
@PCZ16
1 2
PRZ43
16.2K_0402_1% 0.01UF_0402_25V7K
I_SYS PRZ44 0_0402_5%
Close to Phase1 Inductor 1 2 9
PSYS 13 RGND_VCCIN 1 2
RGND VSS_SENSE_VCCIN <15>
VREF06_RT3612 LL/IMON Compesation
1
PRZ45 PHZ2 PRZ46
3.4K_0402_1% 100K_0402_1%_B25/50 4250K 22.6K_0402_1% PRZ47
1 2 VCCIN_NTC1P 1 2 VCCIN_NTC1N 1 2 IMON_VCCIN 11 33 100_0402_1%
IMON GND
2
RT3612EBGQW-02_WQFN32_4X4
PRZ48
17.4K_0402_1%
1 2
D D

+VCORE(RT3612EB)
1 2 3 4 5
5 4 3 2 1
ICCMAX=54A
+VCCIN
TDC=25A
OCP=160% of Iccmax=86.4A
OVP=VID+0.35V=2.24V
330U_D2_2.5VY_R9M
330U_D2_2.5VY_R9M
1 1
Frequency 600KHz + +
PCZ17
PCZ18
@ 2 2
D D
+19VB_VCCIN
@
PJZ1
+19VB
<88> UG1_VCCIN
1 2
1 2
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
JUMP_43X118
@EMI@ PCZ19
PCZ33
PCZ20
PCZ34
0.1U_0402_25V6
1 1
33U_25V_NC_6.3X4.5
33U_25V_NC_6.3X4.5
1
1
+ +
PCZ22
PCZ21
PRZ49
EMI@
2
2
2.2_0603_5% 2 2
1 2 BST1_VCCIN_R
<88> BST1_VCCIN
1
PCZ36 PQZ1
1
0.1U_0402_25V6
Rdc=0.98 mohm
D1
G1
2
+VCCIN
PLZ3
LX1_VCCIN 7 LX1_VCCIN 1 4
<88> LX1_VCCIN D2/S1
2 3
@EMI@ PRZ50
4.7_1206_5%
G2
S2
S2
S2
1
AONY36352 2N DFN5X6D
0.22UH_24A_20%_ 7X7X4_M
1 SNUB1_VCCIN 2
<88> LG1_VCCIN
ISENSE1N_VCCIN <88>
@EMI@ PCZ47
C C
680P_0402_50V7K
2
ISENSE1P_VCCIN <88>
+19VB_VCCIN
<88> UG2_VCCIN
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
@EMI@ PCZ54
EMI@ PCZ55
PCZ56
0.1U_0402_25V6
PCZ57
1
PRZ51
2
2.2_0603_5%
1 2 BST2_VCCIN_R
<88> BST2_VCCIN
B B
1
PCZ58 PQZ2
2
0.1U_0402_25V6
Rdc=0.98 mohm
D1
G1
2
+VCCIN
PLZ4
LX2_VCCIN 7 LX2_VCCIN 1 4
<88> LX2_VCCIN D2/S1
2 3
@EMI@ PRZ52
4.7_1206_5%
G2
S2
S2
S2
AONY36352 2N DFN5X6D
0.22UH_24A_20%_ 7X7X4_M
3
1SNUB2_VCCIN 2
<88> LG2_VCCIN
@EMI@ PCZ59
ISENSE2N_VCCIN <88>
680P_0402_50V7K
2
ISENSE2P_VCCIN <88>
A A

Size
Power stage-VCCIN
Document Number Rev
5 4 3 2 1
A
D
5
5
+VCCIN
2 1 2 1
@
PCZ37 PCZ24
22U_0603_6.3V6M 22U_0603_6.3V6M
4
4
+VCCIN
2 1 2 1
PCZ38 PCZ25
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2 1
PCZ39 PCZ26
PCZ48 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
2 1
PCZ40 PCZ27
PCZ49 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
2 1
PCZ41 PCZ28
PCZ50 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
2 1
@
PCZ42 PCZ29
3
3
PCZ51 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
2 1
PCZ43 PCZ30
PCZ52 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
2 1
PCZ44 PCZ31
PCZ53 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
+VCCIN
Date:
Size
Title
PCZ45 PCZ32
A
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2 1
Document Number
<Doc>
<Title>
@RF@ PCZ46 PCZ35

PCZ60
Tuesday, October 15, 2019
22U_0603_6.3V6M 22U_0603_6.3V6M
12P_0402_50V8J
2
2
2 1
@RF@
PCZ61
12P_0402_50V8J
1U_0201 *6
22U_0603 *18
330U_R9
2 1
@RF@
PCZ62
12P_0402_50V8J
2 1
@RF@
Sheet
PCZ63
12P_0402_50V8J
*1
2 1
@RF@
90
PCZ64
12P_0402_50V8J
1
1
of
2 1
@RF@
PCZ65
102
12P_0402_50V8J
Rev
<RevCode>
Vinafix.com
A B C D E
Module model information

RT6543A_V1A.mdd for IC portion
RT6543A_V1B.mdd for SW portion
1 1
BST_AUX_R +19VB
1
PRG1
2.2_0603_5% PCG1 PRG2 AUX input cap need place 5pcs +19VB_AUX
0.1U_0402_25V6 0_0805_5%
2
+19VB
2
@ PJG1
OCP is Lowside MOSFET Rdson sense
2
1 2 ICCMAX=31A
BST_AUX
1 2
TDC=14A
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
226K x1.2 JUMP_43X118
PCG5
PCG6
0.1U_0402_25V6
0.1U_0402_25V6
DC LL=TBD
1
255K x1.4
1
PUG1
PCG2
10
RT6543AGQW _W QFN20_3X3 AC LL=4.5
EMI@
@EMI@
PCG36
PCG35
PCG3
PCG4
PRG3
2
BOOT
232K_0402_1%
1 2 CS_DSI_RT6543 1 20 VSYS_RT6543
CS_DIS VSYS UG_AUX
+5VALW
PRG5 0_0603_5% +VCCIN_AUX
1 2 PVCC_RT6543 15 11 UG_AUX
PVCC UGATE
PQG3
1
2 1
PCG7 1U_0402_6.3V6K
Rdc=0.98 mohm
D1
G1
PRG4 5.1_0603_5%
VCC_RT6543 LX_AUX PLG1
1 2 16 12
VCC PH 7 LX_AUX 1 4
2 1 D2/S1
PCG8 1U_0402_6.3V6K ISENSEP_AUX 2 3 ISENSEN_AUX
High > 1V
G2
PRG6 100K_0402_1%
S2
S2
S2
1
1 2 VCC_AUX_PW RGD 4 13 LG_AUX AONY36352 2N DFN5X6D
@EMI@ PRG7
+3VALW
4.7_1206_5%
8.87K_0603_1%
PGOOD LGATE 0.22UH_24A_20%_ 7X7X4_M
Low <0.4V
PRG8
3
6
<58> VCC_AUX_PWRGD
PRG9
1 AUX_SNUB
2
2
2<87> 1 2 EN_RT6543 19 14 2
1.8VALW_PG EN PGND
1ISENSEP_AUX_R
LG_AUX
1
0_0402_5% PCG9
0_0402_5%
0.1U_0402_25V6 PRG10 0_0402_5%
@EMI@ PCG10
680P_0402_50V7K
2
VCCIN_AUX_CORE_VID1_R 17 2 ISENSEP_RT6543 1 2 ISENSEP_RT6543_R
PRG11
<11,17,58>
@ VCCIN_AUX_CORE_VID1_R VID1 ISENSEP
8.87K_0603_1%
2
PRG12 0_0402_5%
+3VALW VCCIN_AUX_CORE_VID0_R 18 3 ISENSEN_RT6543 1 2 ISENSEN_RT6543_R
PRG13
<11,17> VCCIN_AUX_CORE_VID0_R VID0 ISENSEN
PCG11 +VCCIN_AUX
1 2 PRG15 PRG18
@ PRG14
PRG16 PRG17
2
100K_0402_1% 0.1U_0402_25V6 1 2 1 2
1 2 FSW SEL_RT6543 9 8 VOUT_RT6543 1 2 0_0402_5% 2 1
ISENSEN_RT6543_R
+5VALW FSWSEL VOUT 1.24K_0402_1% 1.5K_0402_1%
1
PRG21 PCG13 PRG22 100_0402_1% PHG1

@ PRG19
100K_0402_1% PCG12 820P_0402_25V7 10K_0402_1% 390P_0402_50V7K 1.6K_0402_1% ISENSEN_AUX_NTC 1 2
1
5 COMP_RT6543 1 2 1 2 1 2 1 2
COMP
10K_0402_1%_B25/50 3370K
2
PRG20 PRG23
ISENSEP_RT6543_R
10K_0402_1% 10K_0402_1%
B=3435(B25/85)
PCG14 15P_0402_50V8J PRG24 20K_0402_1%
2
VCCIN_AUX_CORE_VID0_R FB_RT6543
6 1 2 1 2
VCCIN_AUX_CORE_VID1_R
5V: 800KHz FB 1 2
1
Float: 600KHz PRG25 PCG15
GND: 400KHz 0_0402_5% 0.1U_0402_25V6
1
7
VSS_SENSE_VCCIN_AUX <17>
AGND
RGND
@ PRG26
2
@ PRG27
1
10K_0402_1% 10K_0402_1%
VCC_SENSE_VCCIN_AUX <17>
PRG29
2
21
1
100_0402_1%
PCG16
@ PCG17 0.1U_0402_25V6
2
2
1 2
0.082U_0402_16V7K
@ PCG18
330P_0402_50V7K
1
3 3
2
VCCIN_AUX VID Follow Intel PDG Rev0.71 @PCG19
1 2
330U_R9 *1
VID1 VID0 +VCCIN_AUX 0.01UF_0402_25V7K 22U_0603 *13
Voltage +VCCIN_AUX
0 0 0
0 1 1.1 +VCCIN_AUX
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1 0 1.65
1
PCG20
PCG21
PCG22
PCG23
PCG24
PCG25
PCG26
PCG27
PCG28
PCG29
1 1 1.8
2
330U 2.5V Y D2 LESR9M
330U 2.5V Y D2 LESR9M

1 1
+ +
PCG30
PCG31
2 2
@
+VCCIN_AUX
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PCG32
PCG33
PCG34
2
2
@RF@ @RF@ @RF@ @RF@
@RF@ @RF@
12P_0402_50V8J
12P_0402_50V8J
12P_0402_50V8J
12P_0402_50V8J
12P_0402_50V8J
12P_0402_50V8J
1
1
1
1
PCG42
PCG41
PCG40
PCG37
PCG39
PCG38
2
2
2
4 4

+VCCIN_AUX
Rev
A B C D E
5 4 3 2 1
D D
C
PWR-Reserve Page C
B B
A A
Title
<Title>


5 4 3 2 1
5 4 3 2 1
D D
C
PWR-Reserve Page C
B B
A A
Title
<Title>


5 4 3 2 1
5 4 3 2 1
D D
C
PWR-Reserve Page C
B B
A A
Title
<Title>


5 4 3 2 1
5 4 3 2 1
D D
C
PWR-Reserve Page C
B B
A A
Title
<Title>


5 4 3 2 1
5 4 3 2 1
D D
C
PWR-Reserve Page C
B B
A A
Title
<Title>


5 4 3 2 1
5 4 3 2 1
D D
C
PWR-Reserve Page C
B B
A A
Title
<Title>


5 4 3 2 1
5 4 3 2 1
D D
PWR-Reserve Page C
B B
A A
Title
<Title>


5 4 3 2 1
5 4 3 2 1
D D
C
PWR-Reserve Page C
B B
A A
Title
<Title>


5 4 3 2 1
5 4 3 2 1
D D
C
PWR-Reserve Page C
B B
A A
Title
<Title>


5 4 3 2 1
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 1 for

PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
Change PCZ21,PCZ22 PN Avoid material shortage P.89 Change PCZ21,PCZ22 to SF000007700 19/09/16 EVT
01
D 02 Add PRZ36,PRZ47 Add PRZ36,PRZ47 for CPU transient test P.88 Add PRZ36,PRZ47 (SD034100080) 19/09/16 EVT D
for CPU transient test

03 optmization cpu transient test change PRZ16,PRZ27 to 2.61K(SD014261180)
CPU transient test P.88 19/10/09 EVT
change PRZ19,PRZ33 to 4.53K(SD034453180)
04 P.84,88,91
PRB18,PRG2,PRG5,PRG10,PRG11,PRG12,PRG16,PRG25,PRG28,PRZ39,PRZ44 19/10/14 EVT
Reduce part count Reduce part count change to R-short
05
06
07
08
C C
09
10
11
B B
12
13
14
15
16
17
18
A A
19
2018/12/27
Compal Secret Data
2019/12/27 Title
PIR
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title
<Title>


5 4 3 2 1

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A B C D E

Security Classification Compal Secret Data Compal Electronics, Inc.

HDMI Conn. eDP Interleaved Memory

DDR4-ON BOARD 4G 8Gbx16

Intel Ice Lake U USB 3.0 USB 2.0 CMOS

(SATA2) Port 13-16

RJ45 conn. eSPI BUS

page 67 CLK=24MHz 128Mb page 9

Power On/Off CKT. Sub Board

Board ID Table for AD channel

43 level BOM table

Security Classification Compal Secret Data Compal Electronics, Inc.

JUMP VR_ON RT3612EBGQW

JUMP 1.8VALW_PG RT6543AGQW

ADAPTER PREM@ AP2330W

SY8288CRAC JUMP SUSP# AOZ1331DI JUMP JUMP

3V_EN SY8286BRAC SOC_ENVDD

JUMP R-Short 0 ohm

(PUM2) +2.5VP (RC154) +3VALW_SPI (RM9) +3VS_SSD_NGFF

SUSP# G2898KD1U R-Short

Vinafix.com Security Classification

FH5LI_EVT Power Sequence AC mode

Plug in Power On S3 S3 Resume Power Off

VCC_AUX_PWRGD → 314.7us → 43.89us

VCCIN_AUX_CORE_VID → 2.383ms 814.3us → 811us

PBTN_OUT# 11.52ms → 121.1ms → ←→ → 9.301us

SYSON → 6.44ms → 3.463us

+2.5V_VPP → 1.25ms → 922.5us

→ 28.04ms → 7.833us → 25.83ms → 9.894us

EC_VCCST_PG_R → 20.26ms → 4.772us → 20.16ms → 6.098us

Vinafix.com Security Classification

<38> EDP_AUXN W4 AY5

RC164 1 2 10K_0402_5% USB_OC1# 1 0f 19

Reserve Test Point

RC422 1 2 100K_0402_5% ENBKL

CATERR# J4 P3 SOC_XDP_TCK0 SOC_XDP_TMS RC13 1 CMC@ 2 51_0402_5%

XDP_ITP_PMODE DL15 N3 SOC_XDP_TMS SOC_XDP_TCK0 RC20 1 2 51_0402_5%

CR39 GPP_B3/CPU_GP2 PROC_PREQ#

RC11 1 2 49.9_0402_1% CATERR#

RC12 1 2 1K_0402_5% H_THERMTRIP#

RC366 1 2 49.9_0402_1% PROC_POPIRCOMP

XDP_ITP_PMODE SOC_GPP_E6 GPP_H2

RC18 1 CMC@ 2 1K_0402_5% XDP_ITP_PMODE RC3965 1 @ 2 100K_0402_5% RC3966 1 @ 2 2.2K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Follow Intel DDR4 NIL

DDR4: Refer to 575034_ICL_U42_DDR4_T3_6L_Core_Schematics_Rev0p7

Buffer with Open Drain Output

74AUP1G07GW_TSSOP5 SM_PG_CTRL to DDR

Security Classification Compal Secret Data Compal Electronics, Inc.

SOC_GPP_C2 RC86 1 2 4.7K_0402_5% SOC_SML0ALERT# RC3944 1 @ 2 4.7K_0402_5%

RC38 1 2 100K_0402_5% SOC_SPI_0_IO2 +3VALW _PRIM

EC_SMB_CK2 RC381 1 2 1K_0402_5%

RC39 1 2 100K_0402_5% SOC_SPI_0_IO3

SOC_SPI_0_SO RC2 1 2 49.9_0402_1% SOC_SPI_0_SO_R SOC_SMBCLK 3 4 SOC_SMBCLK_1

SOC_SMBDATA 6 1 SOC_SMBDATA_1 SOC_SMBDATA_1 <23,66>

MAF - Master Attached Flash

< SPI ROM - 16M >

< HD AUDIO > RC448 1 2 100K_0402_5% HDA_BIT_CLK

< To Enable ME Override >

Security Classification Compal Secret Data Compal Electronics, Inc.

RC352 1 2 10K_0402_5% CLKREQ_PCIE#0 PMCALERT# RC533 2 1 10K_0402_5%

@EMC@ CC377 2 1 100P_0402_50V8J PCH_PWROK