Compal LA-M211P HH5A4 R1a

A B C D E
1 1
2
Compal Confidential 2
HH5A4 MB Schematic Document

LA-M211P
3 3
Rev : 1A
2022.04.18
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2021/08/05 Deciphered Date 2022/08/05 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH5A4 MB LA-M211P
Date: Monday, April 18, 2022 Sheet 1 of 122
A B C D E
A B C D E
Nvidia M.2 SSD PCIe 4.0

VBIOS ROM GN18-S5 - GDDR6 2G
GN20-S7 - GDDR6 4G Memory BUS Interleaved (DDR4)
- SOP8
- Size : 2M - DDR4 So-DIMM 260 pin
- PCIE4 Port B P.27-37 - Channel A
P.29 - PCIE4 Port A
P.69 P.23
1 1
PCIe
- DDR4 So-DIMM 260 pin
- Channel B
P.24
eDP - JEDP1 DDI
- CPU eDP
(OLED)
P.38 SPI
HDMI - JHDMI1
SPI ROM 32M TPM
- VGA Port C HDMI Re-driver - NPCT750
- PS8409 - WSON P.66
- Size : 32M
P.40 Intel
SUB/B ADL-P U28 P.16
USB3.1 - JUSB 1 USB3.1 - JUSB 1 USB3.1 - JUSB 1

Thunderbolt 4
JUSBC1
Processor EC KB9052
2
eSPI BUS Int.Keyboard 2
- GEN1 - GEN1 - GEN1

- USB3.1 Port 3 - USB3.1 Port 2 - USB3.1 Port 1 USB-C TCP0 P.63
- USB2.0 Port 6 - USB2.0 Port 5 - USB2.0 Port 1 USB2 Port 2 P.42-49 P.58
TCP
USB3.0 Fan Control*2
page 77
USB2.0
I2C
Touch Pad
CAMERA Touch Screen FingerPrint WLAN BT
3 - EC PS2 3
- USB2 Port 8 - USB2 Port 9 - USB2 Port 10 - PCH I2C1 P.63

USB2.0 Port 7 - PCH I2C5
LAN(GbE) JRJ45 WLAN M.2 SSD PCIe 3.0 HD Audio HDA Codec
ALC256
P.56
Sub Board - PCIE4 Port12 - PCIE Port9 - PCIE Port5~8

P.51 P.52 P.69
IO/B (LS-M211P) PCIe Int. DMIC Audio Jack

Int. Speaker
- On CCD Module
SUB/B
P.06-22
RTC CKT. (JRTC1) CNVi
4 Power On/Off CKT. HDD 4
SATA
HW Circuit DC/DC
Power Circuit DC/DC P.63

SATA Port 0 2021/08/05 2022/08/05 Title
Issued Date Deciphered Date Block Diagrams
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A B C D E
A B C D E
3.3V +/- 5% *PCB Version SIGNAL SLP_S0# CPU_C10_GATE# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Vcc STATE
Ra 100K +/- 1% EC Board ID Table for AD channel *Key board type
S0 (Full ON) HIGH HIGH HIGH HIGH HIGH ON ON ON ON
Board ID Vmin Vtyp Vmax EC AD Board ID PCB Revision
Rb S3 (Suspend to RAM) HIGH HIGH LOW HIGH HIGH ON ON OFF OFF
0 0 0.000 V 0.300 V 0x00 - 0x13 0 Rev0.1 S4 (Suspend to Disk) HIGH HIGH LOW LOW HIGH ON OFF OFF OFF
1 12K +/- 1% 0.347 V 0.345 V 0.360 V 0x14 - 0x1E SD034120280 1 Rev0.2 S5 (Soft OFF) HIGH HIGH LOW LOW LOW ON OFF OFF OFF
2 15K +/- 1% 0.423 V 0.430 V 0.438 V 0x1F - 0x25 SD034150280 2 Rev0.3 S0IX LOW LOW HIGH HIGH HIGH ON ON ON ON
3 20K +/- 1% 0.541 V 0.550 V 0.559 V 0x26 - 0x30 SD034200280 3 Rev1.0
Power Plane Description S0 S0ix S3 S4/S5
4 27K +/- 1% 0.691 V 0.702 V 0.713 V 0x31 - 0x3A SD034270280 4 Rev1A
Aspire5 +19V_ADPIN_P1 Adapter power supply N/A N/A N/A N/A 1
1 5 33K +/- 1% 0.807 V 0.819 V 0.831 V 0x3B - 0x45 SD034330280 5
+20V_PDVIN PD USB-C power supply N/A N/A N/A N/A
6 43K +/- 1% 0.978 V 0.992 V 1.006 V 0x46 - 0x54 SD034430280 6
+12.6V_BATT Bat tery power supply N/A N/A N/A N/A
7 56K +/- 1% 1.169 V 1.185 V 1.200 V 0x55 - 0x64 SD034560280 7
+19VB AC or bat tery power rail for power circuit N/A N/A N/A N/A
8 75K +/- 1% 1.398 V 1.414 V 1.430 V 0x65 - 0x76 SD034750280 8
100K +/- 1% 1.634 V 1.650 V 1.667 V 0x77 - 0x87 +VCCIN Core voltage for CPU ON OFF OFF OFF
9 SD034100380 9
130K +/- 1% 1.849 V 1.865 V 1.881 V 0x88 - 0x96 SD034130380 10 +VCCIN_AUX CPU and PCH merged auxiliary power rail ON OFF OFF OFF
10
+0.6V_VDDQ LPDDR4x +0.6V power rail(VDDQ) ON OFF OFF OFF
11 160K +/- 1% 2.015 V 2.031 V 2.046 V 0x97 - 0xA4 SD034160380 11 Rev0.3
200K +/- 1% 2.185 V 2.200 V 2.215 V 0xA5 - 0xAF SD034200380 12 Rev1.0 +1.05V_VCCST Sustain voltage for CPU standby modes ON ON ON OFF
12
+1.05VS_VCCSTG Gated sustain voltage for CPU standby modes ON OFF OFF OFF
13 240K +/- 1% 2.316 V 2.329 V 2.343 V 0xB0 - 0xB7 SD000001B80 13 Rev1A
+1.2V_VCCPLL_OC +1.2V power rail for CPU digital PLL ON OFF ON OFF
14 270K +/- 1% 2.395 V 2.408 V 2.421 V 0xB8 - 0xBF SD00000G280 14
330K +/- 1% 2.521 V 2.533 V 2.544 V 0xC0 - 0xC9 SD034330380 Aspire3 15 +1.35VS_VRAM +1.35VS power rail for GPU ON OFF OFF OFF
15
430K +/- 1% 2.667 V 2.677 V 2.687 V 0xCA - 0xD4 SD00000WM80 16 +1.1V_VDDQ LPDDR4x +1.1V power rail (VDD2) ON ON ON OFF
16
560K +/- 1% 2.791 V 2.800 V 2.808 V 0xD5 - 0xDD SD034560380 17 +1.8V LPDDR4x +1.8V power rail(VDD1) ON ON ON OFF
17
+1.8V_PRIM_SOC TCSS/AGSH TypeC sub system / CPU analog power supply ON OFF OFF OFF
18 750K +/- 1% 2.905 V 2.912 V 2.919 V 0xDE - 0xF0 SD00000AL80 18
NC 3.000 V 3.000 V 0xF1 - 0xFF +1.8VALW System +1.8V power rail ON ON ON ON*
19 19
+1.8VS System +1.8VS power rail ON ON OFF OFF
Address(8bit) +3VALW System +3VALW always on power rail ON ON ON ON*
BUS Device Address(7 bit) Write Read +3VLP +19VB to +3VLP power rail for suspend power ON ON ON ON
2 SOC_CK/DA (Port0) +3VALW_DSW +3VALW power for PCH DSW rails ON ON ON ON* 2
SOC_CK/DA (Port1) TM-P3393-003 (Touch Pad) 0x15 +3V_PRIM +3VALW power for PCH suspend rails ON ON ON ON*
SOC_CK/DA (Port5) Touch screen TBD +3VS System +3VS power rail ON ON OFF OFF
SOC_SMBCLK DIMM1 0xA0 0xA1 0xA0 +1.8VS_DGPU_AON +1.8VS power rail for GPU(AON rails) ON OFF OFF OFF
DIMM2 0xA3 0xA4 0xA3 +1.8VS_DGPU +1.8VS power rail for GPU ON OFF OFF OFF
EC_CK/DA (Port0) BQ24780 (Charger IC) 0x12 +VGA_CORE Power rail for GPU ON OFF OFF OFF
(+3VLP) BATTERY PACK 0x16 +5VALW System +5VALW power rail ON ON ON ON*
EC_CK/DA (Port1) +5VS System +5VS power rail ON ON OFF OFF
(+3VS) GN18-S5/GN20-S5 (VGA) 0x9E 0x9F +3VL_RTC RTC power ON ON ON ON
SOC_SML1CK/DA
(+3VALW) Thermal Sensor (NCT7718W) 0x98 1001_1001b 1001_1000b Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF
Thermal Sensor (G753T11U) 0x90
EC_CK/DA (Port2)
EC_CK/DA (Port3) Realtek RTS5452E PD
EC_CK/DA (Port4) N/A (Set GPIO)
V : Must V : Options
3 3
Item (X43 / X76) BOM Structure Item (X43 / X76) BOM Structure 43 Level Description BOM Structure
Unpop @ FOR UART debug UART@ HH5A4 QXZS UMA PCB@/15@/EVT@/QXZS@/1LD@/2012@/ASPIRE5@/CMC@/CNVi@/LAN@/GLITCH@/TMS@/FP@/HDD@/I2CTS@/Typec@/PD@/DB@/OVP@/256@/CHG@/SLGC55544@/X4EUMA@/UMA@
431AUWBOL01
Connector CONN@ FOR EVT EC debug DEBUG@ PCB@/15@/EVT@/QY4Y@/1LD@/2012@/ASPIRE5@/CMC@/CNVi@/LAN@/GLITCH@/TMS@/FP@/HDD@/I2CTS@/Typec@/PD@/DB@/OVP@/256@/
431AUWBOL02 HH5A4 QY4Y GN18-S5 CHG@/SLGC55544@/X4EDIS@/VGA@/GN18S@/OVRM@/GEN1@/GN18X76H2G@/X76GEN1ON@
PCB PCB@ Finger Print FP@
FJ8071504698605 QXZS QXZS@ USB Charger CHG@/ NCHG@ 431AUWBOL03 PCB@/15@/EVT@/QY4W@/1LD@/2012@/ASPIRE5@/CMC@/CNVi@/LAN@/GLITCH@/TMS@/FP@/HDD@/I2CTS@/Typec@/PD@/DB@/OVP@/256@/
HH5A4 QY4W GN18-S5 CHG@/SLGC55544@/X4EDIS@/VGA@/GN18S@/OVRM@/GEN1@/GN18X76H2G@/X76GEN1ON@
FJ8071504661121 QY4T QY4T@ USB Charger IC SLGC55544@/CW3046@ PCB@/15@/EVT@/QY4U@/1LD@/2012@/ASPIRE5@/CMC@/CNVi@/LAN@/GLITCH@/TMS@/FP@/HDD@/I2CTS@/Typec@/PD@/DB@/OVP@/256@/
431AUWBOL04 HH5A4 QY4U GN18-S5 CHG@/SLGC55544@/X4EDIS@/VGA@/GN18S@/OVRM@/GEN1@/GN18X76H2G@/X76GEN1ON@
FJ8071504698606 QXZT OXZT@ Thermal sensor TMS@
FJ8071504661122 QY4U QY4U@ GLITCH GLITCH@ 431AUWBOL05 PCB@/15@/EVT@/QY4T@/1LD@/2012@/ASPIRE5@/CMC@/CNVi@/LAN@/GLITCH@/TMS@/FP@/HDD@/I2CTS@/Typec@/PD@/DB@/OVP@/256@/
HH5A4 QY4T GN18-S5 CHG@/SLGC55544@/X4EDIS@/VGA@/GN18S@/OVRM@/GEN1@/GN18X76H2G@/X76GEN1ON@
FJ8071504661124 QY4W QY4W@ CMC CMC@ HH5A4 NO-CHIP PCB@/15@/EVT@/1LD@/2012@/ASPIRE5@/CMC@/CNVi@/LAN@/GLITCH@/TMS@/FP@/HDD@/I2CTS@/Typec@/PD@/DB@/OVP@/256@/
431AUWBOL06 CHG@/SLGC55544@/X4EDIS@/VGA@/GN18S@/OVRM@/GEN1@/X76GEN1ON@
FJ8071504661126 QY4Y QY4Y@ HDD HDD@ PCB@/15@/EVT@/QXZT@/1LD@/2012@/ASPIRE5@/CMC@/CNVi@/LAN@/GLITCH@/TMS@/FP@/HDD@/I2CTS@/Typec@/PD@/DB@/OVP@/256@/
431AUWBOL07 HH5A4 QXZT GN18-S5 CHG@/SLGC55544@/X4EDIS@/VGA@/GN18S@/OVRM@/GEN1@/GN18X76H2G@/X76GEN1ON@
GN20-S5 GPU GN20S@ Crystal package 2012@/3215@
GN18-S5 GPU GN18S@ EVT Phase EVT@ 431AUWBOL08 PCB@/15@/EVT@/QXZS@/2LD@/TPM@/2012@/ASPIRE5@/CMC@/CNVi@/LAN@/GLITCH@/TMS@/FP@/HDD@/I2CTS@/Typec@/PD@/DB@/OVP@/256@
HH5A4 QXZS GN18-S5 /CHG@/SLGC55544@/X4EDIS@/VGA@/GN18S@/OVRM@/GEN1@/GN18X76H2G@/X76GEN1ON@
dGPU circuit VGA@ Project ID ASPIRE5@/ASPIRE3@ PCB@/15@/EVT@/QXZT@/1LD@/2012@/ASPIRE5@/CMC@/CNVi@/LAN@/GLITCH@/TMS@/FP@/HDD@/I2CTS@/Typec@/PD@/DB@/OVP@/256@
431AUWBOL09 HH5A4 QXZT GN20-S5 /CHG@/SLGC55544@/X4EDIS@/VGA@/GN20S@/OVRM@/GEN1@/GN20X76H2G@/X76GEN1ON@
GPU OVRM OVRM@ JUMPER JUMP@
OVRM GEN1 GEN1@ R-SHORT RS@ 431AUWBOL10 PCB@/15@/EVT@/QXZS@/1LD@/2012@/ASPIRE5@/CMC@/CNVi@/LAN@/GLITCH@/TMS@/FP@/HDD@/I2CTS@/Typec@/PD@/DB@/OVP@/256@/
CHG@/SLGC55544@/X4EDIS@/VGA@/GN20S@/OVRM@/GEN1@/GN20X76H2G@/X76GEN1ON@
TypeC Port TypeC@ KC3810 KC3810@
Item (X76) BOM Structure
PD Controller PD@ Item (X4E) pop BOM Structure Item(X4E)un-pop BOM Structure
OVRM-uPI Gen1 X76UPIGEN1@
Dead battery DB@ EMI requirement EMI@ EMI require reserve XEMI@
4
OVRM-ON Gen1 X76ONGEN1@ 4
HV protect OVP@ / NOVP@ EMC requirement EMC@ EMC require reserve XEMC@
VRAM-SAMSUNG GN18X76S2G@ GN20X76S2G@
SPI 1 Load 1LD@ ESD requirement ESD@ ESD require reserve XESD@
VRAM-Hynix GN18X76H2G@ GN20X76H2G@
SPI 2 Load 2LD@ RF require reserve RF@ RF require reserve @RF@
VRAM-Hynix C-die X76H2GC@
TPM TPM@ FP EMC requirement FPEMC@
Vpro function VPRO@ FP ESD requirement FPESD@ Security Classification Compal Secret Data Compal Electronics, Inc.
eDP-TS USB USBTS@ TBT ESD requirement BL_ESD@ Issued Date 2021/08/05 Deciphered Date 2022/08/05 Title
eDP-TS I2C I2CTS@ TBT EMC requirement BL_EMC@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Custom 1A
Intel CNVi CNVI@ X4E X4EDIS@/X4EUMA@ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A B C D E
5 4 3 2 1
DC_IN +20V_VIN_TYPEC
UT14
PL101,2,3 PQ251
PJP101
+19V_VIN
AC CONN. +1.0VSDGPUP +PEX_VDD
PU1002 PJ1003
GPU +3V_CAM
+12.6V_BATT
+12.6V_BATT+ JEDP1 CAMERA
PL201,PL1803 BATTERY
PJP201 U8 JPQ2 +3VS
IMVP8
D D
+19VB_CPU
PUZ2,3,4,5 +VCC_CORE CPU UV11 +3VSDGPU GPU
PUB1 +19VB PLZ1,2,3,4 +3VS_RETIMER
EN:VR_ON UT1 UT2 TBT
RVE7 +DMIC_VCC JEDP1 DMIC
UM1 +3VS_WLAN JNGFF1 WLAN CARD Conn.
RV691
+19VB_CPU
JIO1 +3VALW JIO1 IO Conn.
CHARGER +19VB PUG1,2 PLG02,PLG04 +VCC_GT CPU UV117 +LCDVDD JEDP1 PANEL
EN:VR_ON UK2 +3V_PTP JTP1 TP Conn. +3V_AUDIO
RA82 CODEC
UM2 RS21 +3VS_SSD1 JSSD1 SSD Conn.
+19VB_CPU JIO1 +3VS JIO1 IO Conn.
PUA01 UM2 RS25 +3VS_SSD2 JSSD2 SSD Conn.
PLA01 +VCCIN_AUX CPU
+19VB
EN:EN_AUX JPC2 +3VALW_PRIM CPU
RC197 +3VALW_DSW CPU

+3VALWP
EN:3V_EN PJ302 +3VALW
UK1 +FP_VCC JFP1 FP Conn.
+19VB
PU301
EC,LID +3VLP
+1.2VP
C
EN:SYSON PJM4 +1.2V_VDDQ CPU,Memory C
+19VB EN:SM_PG_CTRL
+0.6VSP
PUM1 +0.6VS_VTT
PJM5 Memory
+2.5VP EN:1V8_AON_EN
PJM3 +2.5V Memory +1.8VSDGPU_AON +FP_FUSE_GPU GPU
UV14
UV11
UV12 +1.8VSDGPU_MAIN GPU
RS27 +1.8VS RA83 +1.8V_AUDIO CODEC

UM5
+1.8VALWP
PU1801 +1.8VALW_PRIM RC256 +1.8V_PRIM_MCP
CPU
+19VB
PJ1801
EN:EC_1.8V_EN
+5VALWP
PU501 PJ502 +5VALW

+19VB UT14 USB PD
EN:5V_EN
U4 +5VS_BL JKBL1,2 KB Backlight
JIO1 +5VALW JIO1 IO Conn. +VCC_FAN1

RF4 JFAN1 FAN1 Conn.
B B
UT4 +5VALW_USBA JUSB2 USB3.0 Conn. RF7 +VCC_FAN2 JFAN1 FAN2 Conn.
US1 +5VALW_USBB JUSB1 USB3.0 Conn. +5V_AUDIO
JPA1 UA1 CODEC
UK1 +FP_VCC JFP1 FP Conn. +5VS_HDD
RO4 JHDD1 HDD Conn.
U8 JPQ1 +5VS +HDMI_5V_OUT
UV63 JHDMI1 HDMI Conn.
PLV11, GPU_B+ GPU

PLV11,PLV12 PUV2,3,4 PLV2,3,4 +NVVDD1
+19VB PLV12
FBVDD_B+ GPU
PRV75 PQW1 PLW1 +FBVDDQ
LVE1 +INVPWR_B+
+19VB
PANEL
A A

Power MAP
5 4 3 2 1
5 4 3 2 1
[ HH5A4 -PWR Sequence_ADL-U ]
G3->S0 S0-> S0iX S0iX ->S0 S0->S5

AC_IN AC_IN
+3VLP +3VLP
2.839ms
EC_ON EC_ON
D 220us D
+5VALW +5VALW
1.976ms
ON/OFFBTN# ON/OFFBTN#
EC_RSMRST#
3V_EN
91.4ms 9.864ms
3V_EN
+3VALW 545.5us
701us +3VALW
EC_RSMRST#
PCH_DPWROK 122.4ms tPCH03 159.5us PCH_DPWROK
SLP_SUS# 95.92ms 952.4us SLP_SUS#
EC_1V8EN 2.49ms 9.9ms

EC_1V8EN
+1.8VALW(+1.8VALW_PRIM) 243.6us tPCH31 tPCH06 10.77ms
+1.8VALW
C10_GATE PLTRST# 9.908ms
1.8VALW_PG 316.4us
1.8VALW_PG(EN_AUX)
0.83ms
+VCCINAUX 760.2us C10_GATE
+VCCINAUX
+1.8VALW_PRIM
10.98ms
+1.05VO_OUT_FET 6us +1.05VO_OUT_FET
2us 10.90ms +1.05VO_EXTBYPASS
+1.05VO_EXTBYPASS
+1.05VO_VNNBYPASS 4us 10.90ms +1.05VO_VNNBYPASS

EC_RSMRST#
VCCST_OVERRIDE_LS
VCCST_OVERRIDE_LS
C
EC_RSMRST# EC_1V8EN 19.64ms 9.02s EC_RSMRST# C
tPCH07 SLP_S3#
AC_PRESENT_R 29.44ms 10.ms AC_PRESENT_R

ON_OFFBTN#
PBTN_OUT# 11.04ms PBTN_OUT#
9.9ms
267.2ms 20.01ms SOC_PLTRST#
EC_RSMRST#
PM_SLP_S4# 2.328s 598.8us
PM_SLP_S4#
PM_SLP_S3# 1.08ms 500.0us
+3VALW
PM_SLP_S3#
C10_GATE C10_GATE
PM_SLP_S0# Not used
PM_SLP_S0# Not used
SLP_S4# EC_RSMRST#
SYSON SLP_S4# 22.13ms 320.1us
SYSON
+1.2V_VDDQ 4.73ms 6.48ms
+1.2V_VDDQ
+2.5V 716us 50.98ms

SLP_S3# +2.5V
+VCC_AUX
CPU_C10_GATE# SLP_S3# 1.0ms 10us

CPU_C10_GATE#
C10_GATE
+1.05V_VCCSTG Not used +1.05V_VCCSTG
Not used
C10_GATE#
+1.05V_VCCST Not used

SLP_S3#
+1.05V_VCCST Not used
SLP_S3#
SUSP# SLP_S3# 27.07ms 148us
B
SUSP# B
+5VS
971.5us 190.2us +5VS
+3VS 2.17ms
631.5us +3VS
+1.8VS 850.2us
343.3us +1.8VS
SLP_S3#
EC_VCCST_PG
tCPU00 SLP_S3# 46.49ms 116.0us
EC_VCCST_PG
C10_GATE
SM_PG_CTRL SLP_S3# 46.50ms 140.6us
SM_PG_CTRL
SM_PG_CTRL
+0.6VS_VTT 5.4us 51.31us
SM_PG_CTRL SM_PG_CTRL
+0.6VS_VTT
SLP_S3#
VR_ON SLP_S3# 48.30ms 80.24us

VR_ON
C10_GATE
+VCC_CORE 78.93us
227.5ms +VCC_CORE
C10_GATE
VR_PWRGD 0s
1.799ms
VR_PWRGD
SOC_PLTRST#
PCH_PWROK tPCH08
SLP_S3# tCPU16 58.12ms 0.518ms
PCH_PWROK
+1.05V_VCCIO_OUT Not used
+VCCIO_OUT +1.05V_VCCIO_OUT Not used
A
SYS_PWROK A
98.24ms 0.558ms
SYS_PWROK
SOC_PLTRST#
tPCH33 214.5ms SOC_PLTRST#

Power Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Document Number Rev
1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH5A4
5 4 3 2 1
A B C D E
UC1A
REV 0.6
CPU_EDP_TXP3 W3 BE8 TBT_0_TRX_DTX_P1
PDG 1.5 update to add Pull-down <38> CPU_EDP_TXP3 CPU_EDP_TXN3 DDIA_TXP_3 TCP0_TXRX_P1 TBT_0_TRX_DTX_N1 TBT_0_TRX_DTX_P1 <42>
AA3 BE6
11/16 <38> CPU_EDP_TXN3 CPU_EDP_TXP2 DDIA_TXN_3 TCP0_TXRX_N1 TBT_0_TRX_DTX_P0 TBT_0_TRX_DTX_N1 <42>
AA1 BG8
<38> CPU_EDP_TXP2 CPU_EDP_TXN2 DDIA_TXP_2 TCP0_TXRX_P0 TBT_0_TRX_DTX_N0 TBT_0_TRX_DTX_P0 <42>
AB1 BG6
SOC_GPP_E22 <38> CPU_EDP_TXN2 CPU_EDP_TXP1 DDIA_TXN_2 TCP0_TXRX_N0 TBT_0_TTX_DRX_P1 TBT_0_TRX_DTX_N0 <42>
RC496 1 2 AB3 AY3 TBT_0_TTX_DRX_P1 <42>
<38> CPU_EDP_TXP1 CPU_EDP_TXN1 DDIA_TXP_1 TCP0_TX_P1 TBT_0_TTX_DRX_N1
10K_0201_5% AD3 BB3 TBT_0_TTX_DRX_N1 <42>
<38> CPU_EDP_TXN1 CPU_EDP_TXP0 DDIA_TXN_1 TCP0_TX_N1 TBT_0_TTX_DRX_P0
1 AF1 BD3 TBT_0_TTX_DRX_P0 <42> 1
<38> CPU_EDP_TXP0 CPU_EDP_TXN0 DDIA_TXP_0 TCP0_TX_P0 TBT_0_TTX_DRX_N0
AD1 BE3 TBT_0_TTX_DRX_N0 <42>
<38> CPU_EDP_TXN0 DDIA_TXN_0 TCP0_TX_N0 TBT_0_DP_AUXP RC1
BB1 1 RS@ 2 0_0201_5%
CPU_EDP_AUXP TCP0_AUX_P TBT_0_DP_AUXN RC2 TBT_0_DP_AUXP_R <42>
<38> CPU_EDP_AUXP AF3 BD1 1 RS@ 2 0_0201_5%
+3VS CPU_EDP_AUXN DDIA_AUXP TCP0_AUX_N TBT_0_DP_AUXN_R <42>
<38> CPU_EDP_AUXN AG3
DDIA_AUXN AV8
TCP1_TXRX_P1 DVT
RC493 1 2 2.2K_0402_5% SOC_DP2_CTRL_CLK SOC_GPP_E22 ER23 AV6
RC494 1 2 2.2K_0402_5% SOC_DP2_CTRL_DATA 1 SOC_GPP_E23 ET23 GPP_E22/DDPA_CTRLCLK/DNX_FORCE_RELOAD TCP1_TXRX_N1 AY8
T226 @ GPP_E23/DDPA_CTRLDATA TCP1_TXRX_P0 AY6
CPU_EDP_HPD EV25 TCP1_TXRX_N0 AP3
<38> CPU_EDP_HPD GPP_E14/DDSP_HPDA/DISP_MISC_A TCP1_TX_P1 AR3
RC3 1 2 100K_0201_5% SOC_DP2_HPD SOC_DP2_P3 AP6 TCP1_TX_N1 AU3
<40> SOC_DP2_P3 DDIB_TXP_3 TCP1_TX_P0
RC4 1 2 100K_0201_5% CPU_EDP_HPD SOC_DP2_N3 AP8 AW3
<40> SOC_DP2_N3 SOC_DP2_P2 DDIB_TXN_3 TCP1_TX_N0
AM6 AR1
<40> SOC_DP2_P2 SOC_DP2_N2 DDIB_TXP_2 TCP1_AUX_P
AM8 AU1
<40> SOC_DP2_N2 SOC_DP2_P1 DDIB_TXN_2 TCP1_AUX_N
AK6
<40> SOC_DP2_P1 DDIB_TXP_1
RC5 1 GLITCH@2 100K_0201_5% SOC_ENVDD SOC_DP2_N1 AK8 BN8
<40> SOC_DP2_N1 DDIB_TXN_1 TCP2_TXRX_P1
RC6 1 GLITCH@2 100K_0201_5% SOC_ENBKL SOC_DP2_P0 AH6 BN6
<40> SOC_DP2_P0 SOC_DP2_N0 DDIB_TXP_0 TCP2_TXRX_N1
AH8 BL8
<40> SOC_DP2_N0 DDIB_TXN_0 TCP2_TXRX_P0 BL6
AE6 TCP2_TXRX_N0 BK3
AE8 DDIB_AUXP TCP2_TX_P1 BM3
follow RVP DDIB_AUXN TCP2_TX_N1 BG3
SOC_DP2_CTRL_CLK EK46 TCP2_TX_P0 BH3
<40> SOC_DP2_CTRL_CLK SOC_DP2_CTRL_DATA GPP_H15/DDPB_CTRLCLK/PCIE_LINK_DOWN TCP2_TX_N0
EL46 BH1
<40> SOC_DP2_CTRL_DATA GPP_H17/DDPB_CTRLDATA TCP2_AUX_P BK1
SOC_DP2_HPD EB47 TCP2_AUX_N
+3VALW _PRIM <40> SOC_DP2_HPD GPP_A18/DDSP_HPDB/DISP_MISCB BW8
TPM_PIRQ# DV54 TCP3_TXRX_P1 BW6
2 <66> TPM_PIRQ# DV52 GPP_A21/DDPC_CTRLCLK TCP3_TXRX_N1 BU8 2
GPP_A22/DDPC_CTRLDATA TCP3_TXRX_P0
1
BU6
RC482 TBT_0_LSX_TX ER26 TCP3_TXRX_N0 BU3
<42> TBT_0_LSX_TX TBT_0_LSX_RX GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD/BSSB_LS0_RX TCP3_TX_P1
4.7K_0201_5% ET26 BV3
<42> TBT_0_LSX_RX GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD/BSSB_LS0_TX TCP3_TX_N1
@ BN3
EL26 TCP3_TX_P0 BR3
2
TBT_0_LSX_RX EN26 GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD/BSSB_LS1_RX TCP3_TX_N0 BR1

GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD/BSSB_LS1_TX TCP3_AUX_P BU1
TCP3_AUX_N
2
FC37
RC483 EV37 GPP_D9/ISH_SPI_CS#/DDP3_CTRLCLK/TBT_LSX2_TXD/BSSB_LS2_RX/GSPI2_CS0# AL3
GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/TBT_LSX2_RXD/BSSB_LS2_TX/GSPI2_CLK VSS AM1 TCRCOMP_DN RC7 1 2 2.2K_0201_1%
20K_0201_5% TCP_RCOMP
EY37
FA37 GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/TBT_LSX3_TXD/BSSB_LS3_RX/GSPI2_MISO AF32 DSI_DE_TE_2 RC8 1 2 100K_0201_5%
1
GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/TBT_LSX3_RXD/BSSB_LS3_TX/GSPI2_MOSI DISP_UTILS_2
DY54 AJ1 DDIA_RCOMP RC10 1 2 150_0201_1%
EB49 GPP_A17/DISP_MISCC DDIA_RCOMP AL1 DDIB_RCOMP RC12 1 2 150_0201_1%
EB51 GPP_A19/DDSP_HPD1/DISP_MISC1 DDIB_RCOMP
TBT LSX #0 PINS VCCIO CONFIGURATION GPP_A20/DDSP_HPD2/DISP_MISC2 DJ1 DISP_UTILS RC495 1 @ 2 100K_0201_5%
Weak Internal Pull down 20k USB_OC1# DY47 DISP_UTILS_1
SAMPLING - RSMRSTB <71> USB_OC1# USB_OC2# GPP_A14/USB_OC1#/DDSP_HPD3/DISP_MISC3
DY49
<71> USB_OC2# GPP_A15/USB_OC2#/DDSP_HPD4/DISP_MISC4
HIGH 3.3V SOC_ENVDD DISP_UTILS Reserve pull-down (PDG) 20210827
ET21
<38> SOC_ENVDD SOC_ENBKL VDDEN
LOW 1.8V EN21
<58> SOC_ENBKL SOC_BKL_PW M eDP_BKLTEN
EL21
<38> SOC_BKL_PW M eDP_BKLTCTL
ADL-P_BGA1744
+3VALW _PRIM @
3 3
RC9 1 2 10K_0201_5% USB_OC2#
RC11 1 2 10K_0201_5% USB_OC1#
4 4

ADL-P(1/14)DDI,EDP
A B C D E
A B C D E
+1.05V_PROC
1 2 CATERR#
RC13 1K_0201_5% CHECK power net name, 05/17
2 1 H_THERMTRIP#
RC15 1K_0201_5% +1.05V_PROC
CC1 2 1 0.1U_0201_10V6K
1
XEMC@ RC16 UC1V
1 1K_0201_5% REV0.6 1
CATERR# AF15 R6 SOC_XDP_TRST#
0.1U_0201_10V6K 1 2 CC2 H_PECI H_PECI DG3 CATERR# PROC_JTAG_TRST# U8 SOC_XDP_TMS
<58> H_PECI
2
1 2 H_PROCHOT#_R AK32 PECI PROC_JTAG_TMS AA6 SOC_XDP_TDO
<58,85> H_PROCHOT# PROCHOT# PROC_JTAG_TDO
XEMC@ RC18 499_0201_1% H_THERMTRIP# AH32 W8 SOC_XDP_TDI
THERMTRIP# PROC_JTAG_TDI N6 SOC_XDP_TCK0
RC19 2 1 PROC_POPIRCOMP ESD@ 2 1 PROC_POPIRCOMP DV60 PROC_JTAG_TCK
49.9_0201_1% CC3 100P_0201_50V8J PCH_OPIRCOMP DG1 PROC_POPIRCOMP N8 SOC_XDP_TCK0
RC20 2 1 PCH_OPIRCOMP 1 SOC_TP_1 DV11 DMI_RCOMP PCH_JTAGX U6 SOC_XDP_TMS
49.9_0201_1% T228 @ 1 SOC_TP_2 DV10 TP_3 PCH_JTAG_TMS AA8 SOC_XDP_TDO
T229 @ TP_2 PCH_JTAG_TDO W6 SOC_XDP_TDI
XDP_ITP_PMODE ET14 PCH_JTAG_TDI FB6 PCH_JTAG_TCK1
DBG_PMODE PCH_JTAG_TCK R8 SOC_XDP_TRST#
1 T230@
EB56 PCH_PROC_TRST#
EC_TP_INT# EB57 GPP_B4/PROC_GP3/ISH_GP5B L6 XDP_PREQ#
+3VS <58,63> EC_TP_INT# GPP_B3/PROC_GP2/ISH_GP4B PROC_PREQ#
SOC_GPP_E7 FB23 L8 XDP_PRDY# 1 T233@
EY23 GPP_E7/PROC_GP1 PROC_PRDY#
check SW setting for leakage, 1225 GPP_E3/PROC_GP0
1 @ 2 SOC_GPP_E7 AF25 SOC_EAR
RC21 10K_0201_5% SOC_GPP_H2 ET46 EAR#
SOC_GPP_H1 EL48 GPP_H2 EN28
SOC_GPP_H0 EK48 GPP_H1 GPP_F7 ET28
GPP_H0 GPP_F9/BOOTMPC EF28
DY61 GPP_F10
+3VALW _PRIM PCH_SPKR DW56 GPP_B15/TIME_SYNC0/ISH_GP7
<56> PCH_SPKR GPP_B14/SPKR/TIME_SYNC1/SATA_LED#/ISH_GP6
ADL-P_BGA1744
1
@
2 RC26 RC27 RC28 +1.05V_PROC 2
4.7K_0201_5% 4.7K_0201_5% 4.7K_0201_5% +3VALW _PRIM
@ @ @ SOC_XDP_TMS 51_0201_5% 2 CMC@ 1 RC22
2
1
SOC_XDP_TDI 51_0201_5% 2 CMC@ 1 RC24
SOC_GPP_H2 RC31
100K_0201_5% SOC_XDP_TDO 51_0201_5% 2 CMC@ 1 RC25
SOC_GPP_H1
check SW setting, 1225 @ 05/13 RC93 change 100 follow ADL DDR4 RVP rev07
2
SOC_GPP_H0 1 2 H_PROCHOT#
<17,43> VCCIN_AUX_CORE_ALERT#_R
DC1
RB751S40T1G_SOD523-2
2
RC460 RC461 RC462 SOC_XDP_TCK0 51_0201_5% 2 CMC@ 1 RC29

20K_0201_5% 20K_0201_5% 20K_0201_5%
PCH_JTAG_TCK1 51_0201_5% 2 @ 1 RC30
1
+1.05VO_OUT_FET
@ @ @
RC23 1 CMC@ 2 1K_0201_5% XDP_ITP_PMODE
EDS 12.12 internal PH/PD
XDP_ITP_PMODE
DFX TEST MODE
INTERNAL PU 20K
This strap should sample high. There should NOT be
SOC_GPP_H0 GH4FT For RTD3 SSD any on-board device driving it to opposite direction +1.05V_PROC
GH52T Remove 20200817 during strap sampling.
SOC_GPP_H2
BOOT STRAP3 - BIT3 XDP_PREQ# RC255 1 @ 2 3.3K_0201_5%
3 This is bit 1 of a total of 4-bit encoded pin straps for 3
boot configuration.
Refer to Boot Strap 0 (on GPP_C5) for the encoding.
Strap Pin 05/17 Follow ADL_P SchChk_rev1.2
INTERNAL PD 20K +3VS
SOC_GPP_H1
BOOT STRAP1 - BIT2
This is bit 1 of a total of 4-bit encoded pin straps for +1.05V_PROC
boot configuration.
4.7K_0201_5%

1
INTERNAL PD 20K
1
RC458
SOC_GPP_H0 @ RC14
BOOT STRAP1 - BIT1 1K_0201_5%
This is bit 1 of a total of 4-bit encoded pin straps for
2
boot configuration.
2
INTERNAL PD 20K
SOC_EAR
PCH_SPKR
1
SPKR Stall reset sequence after PCU PLL
TOP SWAP OVERRIDE RC17
INTERNAL PD 20K lock until de-asserted:
SOC_WWAN_RST# (No used) 1K_0201_5%
20K_0201_5%
HIGH: Top swap enable 1 = (Default) Normal

1
This strap should sample LOW. There should NOT be @

any on-board device driving it to opposite direction LOW: Disable (Default) Operation; No stall.
RC459
2
during strap sampling. 0 = Stall.
INTERNAL PD 20K @
2
4 4

ADL-P(2/14)MISC,XDP
A B C D E
5 4 3 2 1
Follow Intel DDR4 NIL

DDR4: Refer to ADL_P_DDR4_SODIMM_1DPC_RVP_Rev0p7
D D
UC1B UC1C
REV0.6 REV0.6
<23> DDR_A_D[0..7] DDR_A_D7 DH58 DDR4 / LP4x / LP5_ascend / LP5_descend / DDR5 DDR_A_CLK1 <24> DDR_B_D[0..7] DDR_B_D7 BB58
DDR4(IL) / DDR4(NIL) / DDR5(NIL) / LP4x-LP5(NIL) CD49 DDR4(IL) / DDR4(NIL) / DDR5(NIL) / LP4x-LP5(NIL) DDR4 / LP4x / LP5_ascend / LP5_descend / DDR5 V48 DDR_B_CLK1
DDR_A_D6 DG57 DDR0_DQ_0_7/DDR0_DQ_0_7/DDR0_DQ_0_7/DDR0_DQ_0_7 DDR0_CLK_P_1/DDR3_CLK_P/DDR3_CLK_P/DDR3_CLK_P/DDR1_CLK_P_1 DDR_A_CLK#1 DDR_A_CLK1 <23> DDR_B_D6 BA57 DDR0_DQ_4_7/DDR1_DQ_0_7/DDR2_DQ_0_7/DDR4_DQ_0_7 DDR1_CLK_P_1/DDR7_CLK_P/DDR7_CLK_P/DDR7_CLK_P/DDR3_CLK_P_1 DDR_B_CLK1 <24>
CD48 V49 DDR_B_CLK#1
DDR_A_D5 DH56 DDR0_DQ_0_6/DDR0_DQ_0_6/DDR0_DQ_0_6/DDR0_DQ_0_6 DDR0_CLK_N_1/DDR3_CLK_N/DDR3_CLK_N/DDR3_CLK_N/DDR1_CLK_N_1 CH61 DDR_A_CLK#1 <23> DDR_B_D5 BB56 DDR0_DQ_4_6/DDR1_DQ_0_6/DDR2_DQ_0_6/DDR4_DQ_0_6 DDR1_CLK_N_1/DDR7_CLK_N/DDR7_CLK_N/DDR7_CLK_N/DDR3_CLK_N_1 DDR_B_CLK#1 <24>
AB61
DDR_A_D4 DG60 DDR0_DQ_0_5/DDR0_DQ_0_5/DDR0_DQ_0_5/DDR0_DQ_0_5 NC/DDR2_CLK_P/DDR2_CLK_P/DDR2_CLK_P/DDR1_CLK_P_0 CF61 DDR_B_D4 BA60 DDR0_DQ_4_5/DDR1_DQ_0_5/DDR2_DQ_0_5/DDR4_DQ_0_5 NC/DDR6_CLK_P/DDR6_CLK_P/DDR6_CLK_P/DDR3_CLK_P_0 Y61
DDR_A_D3 DL60 DDR0_DQ_0_4/DDR0_DQ_0_4/DDR0_DQ_0_4/DDR0_DQ_0_4 NC/DDR2_CLK_N/DDR2_CLK_N/DDR2_CLK_N/DDR1_CLK_N_0 CN49 DDR_B_D3 BE60 DDR0_DQ_4_4/DDR1_DQ_0_4/DDR2_DQ_0_4/DDR4_DQ_0_4 NC/DDR6_CLK_N/DDR6_CLK_N/DDR6_CLK_N/DDR3_CLK_N_0 AG49
DDR_A_D2 DK56 DDR0_DQ_0_3/DDR0_DQ_0_3/DDR0_DQ_0_3/DDR0_DQ_0_3 NC/DDR1_CLK_P/DDR1_CLK_P/DDR1_CLK_P/DDR0_CLK_P_1 CN48 DDR_B_D2 BD56 DDR0_DQ_4_3/DDR1_DQ_0_3/DDR2_DQ_0_3/DDR4_DQ_0_3 NC/DDR5_CLK_P/DDR5_CLK_P/DDR5_CLK_P/DDR2_CLK_P_1 AG48
DDR_A_D1 DL57 DDR0_DQ_0_2/DDR0_DQ_0_2/DDR0_DQ_0_2/DDR0_DQ_0_2 NC/DDR1_CLK_N/DDR1_CLK_N/DDR1_CLK_N/DDR0_CLK_N_1 CU61 DDR_A_CLK0 DDR_B_D1 BE57 DDR0_DQ_4_2/DDR1_DQ_0_2/DDR2_DQ_0_2/DDR4_DQ_0_2 NC/DDR5_CLK_N/DDR5_CLK_N/DDR5_CLK_N/DDR2_CLK_N_1 AL61 DDR_B_CLK0
DDR_A_D0 DK58 DDR0_DQ_0_1/DDR0_DQ_0_1/DDR0_DQ_0_1/DDR0_DQ_0_1 DDR0_CLK_P_0/DDR0_CLK_P/DDR0_CLK_P/DDR0_CLK_P/DDR0_CLK_P_0 CR61 DDR_A_CLK#0 DDR_A_CLK0 <23> DDR_B_D0 BD58 DDR0_DQ_4_1/DDR1_DQ_0_1/DDR2_DQ_0_1/DDR4_DQ_0_1 DDR1_CLK_P_0/DDR4_CLK_P/DDR4_CLK_P/DDR4_CLK_P/DDR2_CLK_P_0 DDR_B_CLK0 <24>
DDR_A_CLK#0 <23>
AJ61 DDR_B_CLK#0 DDR_B_CLK#0 <24>
<23> DDR_A_D[8..15] DDR_A_D15DA58 DDR0_DQ_0_0/DDR0_DQ_0_0/DDR0_DQ_0_0/DDR0_DQ_0_0 DDR0_CLK_N_0/DDR0_CLK_N/DDR0_CLK_N/DDR0_CLK_N/DDR0_CLK_N_0 <24> DDR_B_D[8..15] DDR_B_D15AR58 DDR0_DQ_4_0/DDR1_DQ_0_0/DDR2_DQ_0_0/DDR4_DQ_0_0 DDR1_CLK_N_0/DDR4_CLK_N/DDR4_CLK_N/DDR4_CLK_N/DDR2_CLK_N_0
DDR_A_D14CY57 DDR0_DQ_1_7/DDR0_DQ_1_7/DDR0_DQ_1_7/DDR0_DQ_1_7 DDR4 / LP4x / LP5_ascend / LP5_descend / DDR5 CF51 DDR_B_D14AP57 DDR0_DQ_5_7/DDR1_DQ_1_7/DDR2_DQ_1_7/DDR4_DQ_1_7 DDR4 / LP4x / LP5_ascend / LP5_descend / DDR5 AB51
DDR_A_D13DB56 DDR0_DQ_1_6/DDR0_DQ_1_6/DDR0_DQ_1_6/DDR0_DQ_1_6 NC/DDR3_CKE_0/DDR3_WCK_P/DDR3_WCK_P/NC CH51 DDR_B_D13AR56 DDR0_DQ_5_6/DDR1_DQ_1_6/DDR2_DQ_1_6/DDR4_DQ_1_6 NC/DDR7_CKE_0/DDR7_WCK_P/DDR7_WCK_P/NC Y51
DDR_A_D12CY60 DDR0_DQ_1_5/DDR0_DQ_1_5/DDR0_DQ_1_5/DDR0_DQ_1_5 NC/DDR3_CKE_1/DDR3_WCK_N/DDR3_WCK_N/NC CE57 DDR_B_D12AP60 DDR0_DQ_5_5/DDR1_DQ_1_5/DDR2_DQ_1_5/DDR4_DQ_1_5 NC/DDR7_CKE_1/DDR7_WCK_N/DDR7_WCK_N/NC W57
DDR_A_D11DE60 DDR0_DQ_1_4/DDR0_DQ_1_4/DDR0_DQ_1_4/DDR0_DQ_1_4 NC/DDR2_CKE_0/DDR2_WCK_P/DDR2_WCK_P/NC CF58 DDR_B_D11AV60 DDR0_DQ_5_4/DDR1_DQ_1_4/DDR2_DQ_1_4/DDR4_DQ_1_4 NC/DDR6_CKE_0/DDR6_WCK_P/DDR6_WCK_P/NC Y58
DDR_A_D10DD56 DDR0_DQ_1_3/DDR0_DQ_1_3/DDR0_DQ_1_3/DDR0_DQ_1_3 NC/DDR2_CKE_1/DDR2_WCK_N/DDR2_WCK_N/NC CR51 DDR_B_D10AU56 DDR0_DQ_5_3/DDR1_DQ_1_3/DDR2_DQ_1_3/DDR4_DQ_1_3 NC/DDR6_CKE_1/DDR6_WCK_N/DDR6_WCK_N/NC AL51
DDR_A_D9 DE57
DDR_A_D8 DD58
DDR0_DQ_1_2/DDR0_DQ_1_2/DDR0_DQ_1_2/DDR0_DQ_1_2
NC/DDR1_CKE_0/DDR1_WCK_P/DDR1_WCK_P/NC CU51
NC/DDR1_CKE_1/DDR1_WCK_N/DDR1_WCK_N/NC CR58
Check symbol DDR_B_D9 AV57
DDR_B_D8 AU58
NC/DDR5_CKE_0/DDR5_WCK_P/DDR5_WCK_P/NC AJ51
NC/DDR5_CKE_1/DDR5_WCK_N/DDR5_WCK_N/NC AJ58
Check symbol
<23> DDR_A_D[16..23] DDR_A_D23DG50 DDR0_DQ_1_0/DDR0_DQ_1_0/DDR0_DQ_1_0/DDR0_DQ_1_0 NC/DDR0_CKE_0/DDR0_WCK_P/DDR0_WCK_P/NC CP57 <24> DDR_B_D[16..23] DDR_B_D23BA50 DDR0_DQ_5_0/DDR1_DQ_1_0/DDR2_DQ_1_0/DDR4_DQ_1_0 NC/DDR4_CKE_0/DDR4_WCK_P/DDR4_WCK_P/NC AH57
DDR_A_D22DG47 DDR1_DQ_0_7/DDR0_DQ_2_7/DDR0_DQ_2_7/DDR1_DQ_0_7 NC/DDR0_CKE_1/DDR0_WCK_N/DDR0_WCK_N/NC DDR_B_D22AY47 DDR1_DQ_4_7/DDR1_DQ_2_7/DDR2_DQ_2_7/DDR5_DQ_0_7 NC/DDR4_CKE_1/DDR4_WCK_N/DDR4_WCK_N/NC
DDR_A_D21DH48 DDR1_DQ_0_6/DDR0_DQ_2_6/DDR0_DQ_2_6/DDR1_DQ_0_6 DDR4(IL) / DDR4(NIL) / DDR5(NIL) / LP4x-LP5(NIL) BN51 DDR_A_DQS7 DDR_B_D21BB48 DDR1_DQ_4_6/DDR1_DQ_2_6/DDR2_DQ_2_6/DDR5_DQ_0_6 DDR4(IL) / DDR4(NIL) / DDR5(NIL) / LP4x-LP5(NIL) N51 DDR_B_DQS7
DDR_A_D20DG53 DDR1_DQ_0_5/DDR0_DQ_2_5/DDR0_DQ_2_5/DDR1_DQ_0_5 DDR1_DQSP_3/DDR0_DQSP_7/DDR1_DQSP_3/DDR3_DQSP_1 BL51 DDR_A_DQS#7 DDR_A_DQS7 <23> DDR_B_D20BA53 DDR1_DQ_4_5/DDR1_DQ_2_5/DDR2_DQ_2_5/DDR5_DQ_0_5 DDR1_DQSP_7/DDR1_DQSP_7/DDR3_DQSP_3/DDR7_DQSP_1 L51 DDR_B_DQS#7 DDR_B_DQS7 <24>
DDR_A_D19DL53 DDR1_DQ_0_4/DDR0_DQ_2_4/DDR0_DQ_2_4/DDR1_DQ_0_4 DDR1_DQSN_3/DDR0_DQSN_7/DDR1_DQSN_3/DDR3_DQSN_1 BW51DDR_A_DQS6 DDR_A_DQS#7 <23> DDR_B_D19BE53 DDR1_DQ_4_4/DDR1_DQ_2_4/DDR2_DQ_2_4/DDR5_DQ_0_4 DDR1_DQSN_7/DDR1_DQSN_7/DDR3_DQSN_3/DDR7_DQSN_1 N61 DDR_B_DQS6 DDR_B_DQS#7 <24>
DDR_A_D18DK48 DDR1_DQ_0_3/DDR0_DQ_2_3/DDR0_DQ_2_3/DDR1_DQ_0_3 DDR1_DQSP_2/DDR0_DQSP_6/DDR1_DQSP_2/DDR3_DQSP_0 BU51 DDR_A_DQS#6 DDR_A_DQS6 <23> DDR_B_D18BD48 DDR1_DQ_4_3/DDR1_DQ_2_3/DDR2_DQ_2_3/DDR5_DQ_0_3 DDR1_DQSP_6/DDR1_DQSP_6/DDR3_DQSP_2/DDR7_DQSP_0 L61 DDR_B_DQS#6 DDR_B_DQS6 <24>
DDR_A_D17 DDR1_DQ_0_2/DDR0_DQ_2_2/DDR0_DQ_2_2/DDR1_DQ_0_2 DDR1_DQSN_2/DDR0_DQSN_6/DDR1_DQSN_2/DDR3_DQSN_0 BL61 DDR_A_DQS5 DDR_A_DQS#6 <23> DDR_B_D17BE47 DDR1_DQ_4_2/DDR1_DQ_2_2/DDR2_DQ_2_2/DDR5_DQ_0_2 DDR1_DQSN_6/DDR1_DQSN_6/DDR3_DQSN_2/DDR7_DQSN_0 A43 DDR_B_DQS5 DDR_B_DQS#6 <24>
DM47
DDR_A_D16DL50 DDR1_DQ_0_1/DDR0_DQ_2_1/DDR0_DQ_2_1/DDR1_DQ_0_1 DDR0_DQSP_3/DDR0_DQSP_5/DDR1_DQSP_1/DDR2_DQSP_1 BN61 DDR_A_DQS#5 DDR_A_DQS5 <23> DDR_B_D16BE50 DDR1_DQ_4_1/DDR1_DQ_2_1/DDR2_DQ_2_1/DDR5_DQ_0_1 DDR0_DQSP_7/DDR1_DQSP_5/DDR3_DQSP_1/DDR6_DQSP_1 A44 DDR_B_DQS#5 DDR_B_DQS5 <24>
<23> DDR_A_D[24..31] DDR_A_D31CY50 DDR1_DQ_0_0/DDR0_DQ_2_0/DDR0_DQ_2_0/DDR1_DQ_0_0 DDR0_DQSN_3/DDR0_DQSN_5/DDR1_DQSN_1/DDR2_DQSN_1 BU61 DDR_A_DQS4 DDR_A_DQS#5 <23> <24> DDR_B_D[24..31] DDR_B_D31AP50 DDR1_DQ_4_0/DDR1_DQ_2_0/DDR2_DQ_2_0/DDR5_DQ_0_0 DDR0_DQSN_7/DDR1_DQSN_5/DDR3_DQSN_1/DDR6_DQSN_1 A49 DDR_B_DQS4 DDR_B_DQS#5 <24>
DDR_A_D30CY47 DDR1_DQ_1_7/DDR0_DQ_3_7/DDR0_DQ_3_7/DDR1_DQ_1_7 DDR0_DQSP_2/DDR0_DQSP_4/DDR1_DQSP_0/DDR2_DQSP_0 BW61DDR_A_DQS#4 DDR_A_DQS4 <23> DDR_B_D30AP47 DDR1_DQ_5_7/DDR1_DQ_3_7/DDR2_DQ_3_7/DDR5_DQ_1_7 DDR0_DQSP_6/DDR1_DQSP_4/DDR3_DQSP_0/DDR6_DQSP_0 A51 DDR_B_DQS#4 DDR_B_DQS4 <24>
DDR_A_D29DB48 DDR1_DQ_1_6/DDR0_DQ_3_6/DDR0_DQ_3_6/DDR1_DQ_1_6 DDR0_DQSN_2/DDR0_DQSN_4/DDR1_DQSN_0/DDR2_DQSN_0 DC51 DDR_A_DQS3 DDR_A_DQS#4 <23> DDR_B_D29AR48 DDR1_DQ_5_6/DDR1_DQ_3_6/DDR2_DQ_3_6/DDR5_DQ_1_6 DDR0_DQSN_6/DDR1_DQSN_4/DDR3_DQSN_0/DDR6_DQSN_0 AU51 DDR_B_DQS3 DDR_B_DQS#4 <24>
DDR_A_D28DA53 DDR1_DQ_1_5/DDR0_DQ_3_5/DDR0_DQ_3_5/DDR1_DQ_1_5 DDR1_DQSP_1/DDR0_DQSP_3/DDR0_DQSP_3/DDR1_DQSP_1 DB51 DDR_A_DQS#3 DDR_A_DQS3 <23> DDR_B_D28AP53 DDR1_DQ_5_5/DDR1_DQ_3_5/DDR2_DQ_3_5/DDR5_DQ_1_5 DDR1_DQSP_5/DDR1_DQSP_3/DDR2_DQSP_3/DDR5_DQSP_1 AR51 DDR_B_DQS#3 DDR_B_DQS3 <24>
DDR_A_D27DE53 DDR1_DQ_1_4/DDR0_DQ_3_4/DDR0_DQ_3_4/DDR1_DQ_1_4 DDR1_DQSN_1/DDR0_DQSN_3/DDR0_DQSN_3/DDR1_DQSN_1 DK51 DDR_A_DQS2 DDR_A_DQS#3 <23> DDR_B_D27AV53 DDR1_DQ_5_4/DDR1_DQ_3_4/DDR2_DQ_3_4/DDR5_DQ_1_4 DDR1_DQSN_5/DDR1_DQSN_3/DDR2_DQSN_3/DDR5_DQSN_1 BD51 DDR_B_DQS2 DDR_B_DQS#3 <24>
DDR_A_D26DC48 DDR1_DQ_1_3/DDR0_DQ_3_3/DDR0_DQ_3_3/DDR1_DQ_1_3 DDR1_DQSP_0/DDR0_DQSP_2/DDR0_DQSP_2/DDR1_DQSP_0 DH51 DDR_A_DQS#2 DDR_A_DQS2 <23> DDR_B_D26AU48 DDR1_DQ_5_3/DDR1_DQ_3_3/DDR2_DQ_3_3/DDR5_DQ_1_3 DDR1_DQSP_4/DDR1_DQSP_2/DDR2_DQSP_2/DDR5_DQSP_0 BB51 DDR_B_DQS#2 DDR_B_DQS2 <24>
DDR_A_D25DE47 DDR1_DQ_1_2/DDR0_DQ_3_2/DDR0_DQ_3_2/DDR1_DQ_1_2 DDR1_DQSN_0/DDR0_DQSN_2/DDR0_DQSN_2/DDR1_DQSN_0 DB61 DDR_A_DQS1 DDR_A_DQS#2 <23> DDR_B_D25 DDR1_DQ_5_2/DDR1_DQ_3_2/DDR2_DQ_3_2/DDR5_DQ_1_2 DDR1_DQSN_4/DDR1_DQSN_2/DDR2_DQSN_2/DDR5_DQSN_0 AR61 DDR_B_DQS1 DDR_B_DQS#2 <24>
AW47
DDR_A_D24DE50 DDR1_DQ_1_1/DDR0_DQ_3_1/DDR0_DQ_3_1/DDR1_DQ_1_1 DDR0_DQSP_1/DDR0_DQSP_1/DDR0_DQSP_1/DDR0_DQSP_1 DC61 DDR_A_DQS#1 DDR_A_DQS1 <23> DDR_B_D24AV50 DDR1_DQ_5_1/DDR1_DQ_3_1/DDR2_DQ_3_1/DDR5_DQ_1_1 DDR0_DQSP_5/DDR1_DQSP_1/DDR2_DQSP_1/DDR4_DQSP_1 AU61 DDR_B_DQS#1 DDR_B_DQS1 <24>
<23> DDR_A_D[32..39] DDR_A_D39BU58 DDR1_DQ_1_0/DDR0_DQ_3_0/DDR0_DQ_3_0/DDR1_DQ_1_0 DDR0_DQSN_1/DDR0_DQSN_1/DDR0_DQSN_1/DDR0_DQSN_1 DH61 DDR_A_DQS0 DDR_A_DQS#1 <23> <24> DDR_B_D[32..39] DDR_B_D39 C49 DDR1_DQ_5_0/DDR1_DQ_3_0/DDR2_DQ_3_0/DDR5_DQ_1_0 DDR0_DQSN_5/DDR1_DQSN_1/DDR2_DQSN_1/DDR4_DQSN_1 BB61 DDR_B_DQS0 DDR_B_DQS#1 <24>
DDR_A_D38BT57 DDR0_DQ_2_7/DDR0_DQ_4_7/DDR1_DQ_0_7/DDR2_DQ_0_7 DDR0_DQSP_0/DDR0_DQSP_0/DDR0_DQSP_0/DDR0_DQSP_0 DK61 DDR_A_DQS#0 DDR_A_DQS0 <23> DDR_B_D38 E48 DDR0_DQ_6_7/DDR1_DQ_4_7/DDR3_DQ_0_7/DDR6_DQ_0_7 DDR0_DQSP_4/DDR1_DQSP_0/DDR2_DQSP_0/DDR4_DQSP_0 BD61 DDR_B_DQS#0 DDR_B_DQS0 <24>
DDR_A_D37BU56 DDR0_DQ_2_6/DDR0_DQ_4_6/DDR1_DQ_0_6/DDR2_DQ_0_6 DDR0_DQSN_0/DDR0_DQSN_0/DDR0_DQSN_0/DDR0_DQSN_0 DDR_A_DQS#0 <23> DDR_B_D37 F49 DDR0_DQ_6_6/DDR1_DQ_4_6/DDR3_DQ_0_6/DDR6_DQ_0_6 DDR0_DQSN_4/DDR1_DQSN_0/DDR2_DQSN_0/DDR4_DQSN_0 DDR_B_DQS#0 <24>
DDR_A_D36BT60 DDR0_DQ_2_5/DDR0_DQ_4_5/DDR1_DQ_0_5/DDR2_DQ_0_5 DDR4 / LP4x / LP5_ascend / LP5_descend / DDR5 CM60DDR_A_MA5 DDR_B_D36 B48 DDR0_DQ_6_5/DDR1_DQ_4_5/DDR3_DQ_0_5/DDR6_DQ_0_5 DDR4 / LP4x / LP5_ascend / LP5_descend / DDR5 AE60 DDR_B_MA5
C DDR_A_D35BY60 DDR0_DQ_2_4/DDR0_DQ_4_4/DDR1_DQ_0_4/DDR2_DQ_0_4 DDR0_MA_5/DDR0_CA_5/DDR0_CA_6/DDR0_CA_0/NC CL55 DDR_A_MA7 DDR_A_MA5 <23> DDR_B_D35 B52 DDR0_DQ_6_4/DDR1_DQ_4_4/DDR3_DQ_0_4/DDR6_DQ_0_4 DDR1_MA_5/DDR4_CA_5/DDR4_CA_6/DDR4_CA_0/NC AE55 DDR_B_MA7 DDR_B_MA5 <24> C
DDR_A_D34 DDR0_DQ_2_3/DDR0_DQ_4_3/DDR1_DQ_0_3/DDR2_DQ_0_3 DDR0_MA_7/DDR0_CA_4/DDR0_CA_5/DDR0_CA_1/NC CM57DDR_A_MA6 DDR_A_MA7 <23> DDR_B_D34 F51 DDR0_DQ_6_3/DDR1_DQ_4_3/DDR3_DQ_0_3/DDR6_DQ_0_3 DDR1_MA_7/DDR4_CA_4/DDR4_CA_5/DDR4_CA_1/NC AF57 DDR_B_MA6 DDR_B_MA7 <24>
BW56
DDR_A_D33BY57 DDR0_DQ_2_2/DDR0_DQ_4_2/DDR1_DQ_0_2/DDR2_DQ_0_2 DDR0_MA_6/DDR0_CA_3/DDR0_CA_4/DDR0_CS_1/NC CP60 DDR_A_MA8 DDR_A_MA6 <23> DDR_B_D33 E52 DDR0_DQ_6_2/DDR1_DQ_4_2/DDR3_DQ_0_2/DDR6_DQ_0_2 DDR1_MA_6/DDR4_CA_3/DDR4_CA_4/DDR4_CS_1/NC AH60 DDR_B_MA8 DDR_B_MA6 <24>
DDR_A_D32 DDR0_DQ_2_1/DDR0_DQ_4_1/DDR1_DQ_0_1/DDR2_DQ_0_1 DDR0_MA_8/DDR0_CA_2/DDR0_CA_3/DDR0_CS_0/DDR0_CA_9 CU58 DDR_A_MA8 <23> DDR_B_D32 C51 DDR0_DQ_6_1/DDR1_DQ_4_1/DDR3_DQ_0_1/DDR6_DQ_0_1 DDR1_MA_8/DDR4_CA_2/DDR4_CA_3/DDR4_CS_0/DDR2_CA_9 AL56 DDR_B_MA8 <24>
BW58
<23> DDR_A_D[40..47] DDR_A_D47BL58 DDR0_DQ_2_0/DDR0_DQ_4_0/DDR1_DQ_0_0/DDR2_DQ_0_0 NC/DDR0_CA_1/DDR0_CA_1/DDR0_CA_5/DDR0_CA_0 CU56 <24> DDR_B_D[40..47] DDR_B_D47 E41 DDR0_DQ_6_0/DDR1_DQ_4_0/DDR3_DQ_0_0/DDR6_DQ_0_0 NC/DDR4_CA_1/DDR4_CA_1/DDR4_CA_5/DDR2_CA_1 AL58
DDR_A_D46BK57 DDR0_DQ_3_7/DDR0_DQ_5_7/DDR1_DQ_1_7/DDR2_DQ_1_7 NC/DDR0_CA_0/DDR0_CA_0/DDR0_CA_6/DDR0_CA_1 CM47DDR_A_BA1 DDR_B_D46 C42 DDR0_DQ_7_7/DDR1_DQ_5_7/DDR3_DQ_1_7/DDR6_DQ_1_7 NC/DDR4_CA_0/DDR4_CA_0/DDR4_CA_6/DDR2_CA_0 AE47 DDR_B_BA1
DDR_A_D45BL56 DDR0_DQ_3_6/DDR0_DQ_5_6/DDR1_DQ_1_6/DDR2_DQ_1_6 DDR0_BA_1/DDR1_CA_5/DDR1_CA_6/DDR1_CA_0/DDR0_CA_10 CM53DDR_A_MA16 DDR_A_BA1 <23> DDR_B_D45 F43 DDR0_DQ_7_6/DDR1_DQ_5_6/DDR3_DQ_1_6/DDR6_DQ_1_6 DDR1_BA_1/DDR5_CA_5/DDR5_CA_6/DDR5_CA_0/DDR2_CA_10 AE53 DDR_B_MA16 DDR_B_BA1 <24>
DDR_A_D44BK60 DDR0_DQ_3_5/DDR0_DQ_5_5/DDR1_DQ_1_5/DDR2_DQ_1_5 DDR0_MA_16/DDR1_CA_4/DDR1_CA_5/DDR1_CA_1/DDR0_CA_8 CT46 DDR_A_MA15 DDR_A_MA16 <23> DDR_B_D44 B41 DDR0_DQ_7_5/DDR1_DQ_5_5/DDR3_DQ_1_5/DDR6_DQ_1_5 DDR1_MA_16/DDR5_CA_4/DDR5_CA_5/DDR5_CA_1/DDR2_CA_8 AK46 DDR_B_MA15 DDR_B_MA16 <24>
DDR_A_D43BP60 DDR0_DQ_3_4/DDR0_DQ_5_4/DDR1_DQ_1_4/DDR2_DQ_1_4 DDR0_MA_15/DDR1_CA_3/DDR1_CA_4/DDR1_CS_1/DDR0_CA_7 CP53 DDR_A_MA14 DDR_A_MA15 <23> DDR_B_D43 B46 DDR0_DQ_7_4/DDR1_DQ_5_4/DDR3_DQ_1_4/DDR6_DQ_1_4 DDR1_MA_15/DDR5_CA_3/DDR5_CA_4/DDR5_CS_1/DDR2_CA_7 AH53 DDR_B_MA14 DDR_B_MA15 <24>
DDR_A_D42BN56 DDR0_DQ_3_3/DDR0_DQ_5_3/DDR1_DQ_1_3/DDR2_DQ_1_3 DDR0_MA_14/DDR1_CA_2/DDR1_CA_3/DDR1_CS_0/DDR0_CA_11 CW47DDR_A_CS#1 DDR_A_MA14 <23> DDR_B_D42 F44 DDR0_DQ_7_3/DDR1_DQ_5_3/DDR3_DQ_1_3/DDR6_DQ_1_3 DDR1_MA_14/DDR5_CA_2/DDR5_CA_3/DDR5_CS_0/DDR2_CA_11 AM47 DDR_B_CS#1 DDR_B_MA14 <24>
DDR_A_D41BP57 DDR0_DQ_3_2/DDR0_DQ_5_2/DDR1_DQ_1_2/DDR2_DQ_1_2 DDR0_CS_1/DDR1_CA_1/DDR1_CA_1/DDR1_CA_5/DDR0_CA_2 CV53 DDR_A_ODT1 DDR_A_CS#1 <23> DDR_B_D41 E46 DDR0_DQ_7_2/DDR1_DQ_5_2/DDR3_DQ_1_2/DDR6_DQ_1_2 DDR1_CS_1/DDR5_CA_1/DDR5_CA_1/DDR5_CA_5/DDR2_CA_2 AM53 DDR_B_ODT1 DDR_B_CS#1 <24>
DDR_A_D40BN58 DDR0_DQ_3_1/DDR0_DQ_5_1/DDR1_DQ_1_1/DDR2_DQ_1_1 DDR0_ODT_1/DDR1_CA_0/DDR1_CA_0/DDR1_CA_6/DDR0_CA_3 CC60 DDR_A_CKE0 DDR_A_ODT1 <23> DDR_B_D40 C45 DDR0_DQ_7_1/DDR1_DQ_5_1/DDR3_DQ_1_1/DDR6_DQ_1_1 DDR1_ODT_1/DDR5_CA_0/DDR5_CA_0/DDR5_CA_6/DDR2_CA_3 T55 DDR_B_CKE0 DDR_B_ODT1 <24>
<23> DDR_A_D[48..55] DDR_A_D55BT50 DDR0_DQ_3_0/DDR0_DQ_5_0/DDR1_DQ_1_0/DDR2_DQ_1_0 DDR0_CKE_0/DDR2_CA_5/DDR2_CA_6/DDR2_CA_0/NC CB55 DDR_A_CKE1 DDR_A_CKE0 <23> <24> DDR_B_D[48..55] DDR_B_D55 L58 DDR0_DQ_7_0/DDR1_DQ_5_0/DDR3_DQ_1_0/DDR6_DQ_1_0 DDR1_CKE_0/DDR6_CA_5/DDR6_CA_6/DDR6_CA_0/NC T60 DDR_B_CKE1 DDR_B_CKE0 <24>
DDR_A_D54BT47 DDR1_DQ_2_7/DDR0_DQ_6_7/DDR1_DQ_2_7/DDR3_DQ_0_7 DDR0_CKE_1/DDR2_CA_4/DDR2_CA_5/DDR2_CA_1/NC CC57 DDR_A_BG0 DDR_A_CKE1 <23> DDR_B_D54 K57 DDR1_DQ_6_7/DDR1_DQ_6_7/DDR3_DQ_2_7/DDR7_DQ_0_7 DDR1_CKE_1/DDR6_CA_4/DDR6_CA_5/DDR6_CA_1/NC W60 DDR_B_BG0 DDR_B_CKE1 <24>
DDR_A_D53BU48 DDR1_DQ_2_6/DDR0_DQ_6_6/DDR1_DQ_2_6/DDR3_DQ_0_6 DDR0_BG_0/DDR2_CA_3/DDR2_CA_4/DDR2_CS_1/NC CE60 DDR_A_BG1 DDR_A_BG0 <23> DDR_B_D53 L56 DDR1_DQ_6_6/DDR1_DQ_6_6/DDR3_DQ_2_6/DDR7_DQ_0_6 DDR1_BG_0/DDR6_CA_3/DDR6_CA_4/DDR6_CS_1/DDR3_CA_4 U57 DDR_B_BG1 DDR_B_BG0 <24>
DDR_A_D52BT53 DDR1_DQ_2_5/DDR0_DQ_6_5/DDR1_DQ_2_5/DDR3_DQ_0_5 DDR0_BG_1/DDR2_CA_2/DDR2_CA_3/DDR2_CS_0/DDR1_CA_4 CH56 DDR_A_MA12 DDR_A_BG1 <23> DDR_B_D52 K60 DDR1_DQ_6_5/DDR1_DQ_6_5/DDR3_DQ_2_5/DDR7_DQ_0_5 DDR1_BG_1/DDR6_CA_2/DDR6_CA_3/DDR6_CS_0/NC AB58 DDR_B_MA12 DDR_B_BG1 <24>
DDR_A_D51BY53 DDR1_DQ_2_4/DDR0_DQ_6_4/DDR1_DQ_2_4/DDR3_DQ_0_4 DDR0_MA_12/DDR2_CA_1/DDR2_CA_1/DDR2_CA_5/DDR1_CA_12 CH58 DDR_A_MA9 DDR_A_MA12 <23> DDR_B_D51 P60 DDR1_DQ_6_4/DDR1_DQ_6_4/DDR3_DQ_2_4/DDR7_DQ_0_4 DDR1_MA_12/DDR6_CA_1/DDR6_CA_1/DDR6_CA_5/DDR3_CA_7 AC60 DDR_B_MA9 DDR_B_MA12 <24>
DDR_A_D50 DDR1_DQ_2_3/DDR0_DQ_6_3/DDR1_DQ_2_3/DDR3_DQ_0_3 DDR0_MA_9/DDR2_CA_0/DDR2_CA_0/DDR2_CA_6/DDR1_CA_7 CC53 DDR_A_MA9 <23> DDR_B_D50 N56 DDR1_DQ_6_3/DDR1_DQ_6_3/DDR3_DQ_2_3/DDR7_DQ_0_3 DDR1_MA_9/DDR6_CA_0/DDR6_CA_0/DDR6_CA_6/DDR3_CA_11 T53 DDR_B_MA9 <24>
BW48
DDR_A_D49CA47 DDR1_DQ_2_2/DDR0_DQ_6_2/DDR1_DQ_2_2/DDR3_DQ_0_2 NC/DDR3_CA_5/DDR3_CA_6/DDR3_CA_0/DDR1_CS_1 CC47 DDR_B_D49 P57 DDR1_DQ_6_2/DDR1_DQ_6_2/DDR3_DQ_2_2/DDR7_DQ_0_2 NC/DDR7_CA_5/DDR7_CA_6/DDR7_CA_0/DDR3_CS_1 T47
DDR_A_D48BY50 DDR1_DQ_2_1/DDR0_DQ_6_1/DDR1_DQ_2_1/DDR3_DQ_0_1 NC/DDR3_CA_4/DDR3_CA_5/DDR3_CA_1/DDR1_CS_0 CE53 DDR_B_D48 N58 DDR1_DQ_6_1/DDR1_DQ_6_1/DDR3_DQ_2_1/DDR7_DQ_0_1 NC/DDR7_CA_4/DDR7_CA_5/DDR7_CA_1/DDR3_CS_0 W53
<23> DDR_A_D[56..63] DDR_A_D63BJ50 DDR1_DQ_2_0/DDR0_DQ_6_0/DDR1_DQ_2_0/DDR3_DQ_0_0 NC/DDR3_CA_3/DDR3_CA_4/DDR3_CS_1/DDR1_CA_0 CH46 <24> DDR_B_D[56..63] DDR_B_D63 K50 DDR1_DQ_6_0/DDR1_DQ_6_0/DDR3_DQ_2_0/DDR7_DQ_0_0 NC/DDR7_CA_3/DDR7_CA_4/DDR7_CS_1/DDR3_CA_0 AA46
DDR_A_D62BJ47 DDR1_DQ_3_7/DDR0_DQ_7_7/DDR1_DQ_3_7/DDR3_DQ_1_7 NC/DDR3_CA_2/DDR3_CA_3/DDR3_CS_0/DDR1_CA_6 CK47 DDR_A_MA10 DDR_B_D62 F58 DDR1_DQ_7_7/DDR1_DQ_7_7/DDR3_DQ_3_7/DDR7_DQ_1_7 NC/DDR7_CA_2/DDR7_CA_3/DDR7_CS_0/DDR3_CA_6 AC47 DDR_B_MA10
DDR_A_D61BL48 DDR1_DQ_3_6/DDR0_DQ_7_6/DDR1_DQ_3_6/DDR3_DQ_1_6 DDR0_MA_10/DDR3_CA_1/DDR3_CA_1/DDR3_CA_5/DDR1_CA_8 CJ53 DDR_A_BA0 DDR_A_MA10 <23> DDR_B_D61 F54 DDR1_DQ_7_6/DDR1_DQ_7_6/DDR3_DQ_3_6/DDR7_DQ_1_6 DDR1_MA_10/DDR7_CA_1/DDR7_CA_1/DDR7_CA_5/DDR3_CA_8 AC53 DDR_B_BA0 DDR_B_MA10 <24>
DDR_A_D60BK53 DDR1_DQ_3_5/DDR0_DQ_7_5/DDR1_DQ_3_5/DDR3_DQ_1_5 DDR0_BA_0/DDR3_CA_0/DDR3_CA_0/DDR3_CA_6/DDR1_CA_10 DDR_A_BA0 <23> DDR_B_D60 L48 DDR1_DQ_7_5/DDR1_DQ_7_5/DDR3_DQ_3_5/DDR7_DQ_1_5 DDR1_BA_0/DDR7_CA_0/DDR7_CA_0/DDR7_CA_6/DDR3_CA_10 DDR_B_BA0 <24>
DDR_A_D59BP53 DDR1_DQ_3_4/DDR0_DQ_7_4/DDR1_DQ_3_4/DDR3_DQ_1_4 DDR4 / LP4x / LP5_ascend / LP5_descend / DDR5 CV60 DDR_A_MA3 DDR_B_D59 H56 DDR1_DQ_7_4/DDR1_DQ_7_4/DDR3_DQ_3_4/DDR7_DQ_1_4 DDR4 / LP4x / LP5_ascend / LP5_descend / DDR5 AM57 DDR_B_MA3
DDR_A_D58BN48 DDR1_DQ_3_3/DDR0_DQ_7_3/DDR1_DQ_3_3/DDR3_DQ_1_3 DDR0_MA_3/DDR0_CS_1/DDR0_CS_0/DDR0_CA_3/DDR0_CS_1 CR56 DDR_A_MA4 DDR_A_MA3 <23> DDR_B_D58 K53 DDR1_DQ_7_3/DDR1_DQ_7_3/DDR3_DQ_3_3/DDR7_DQ_1_3 DDR1_MA_3/DDR4_CS_1/DDR4_CS_0/DDR4_CA_3/DDR2_CS_1 AJ56 DDR_B_MA4 DDR_B_MA3 <24>
DDR_A_D57BP47 DDR1_DQ_3_2/DDR0_DQ_7_2/DDR1_DQ_3_2/DDR3_DQ_1_2 DDR0_MA_4/DDR0_CS_0/DDR0_CA_2/DDR0_CA_2/DDR0_CA_12 CU48 DDR_A_MA13 DDR_A_MA4 <23> DDR_B_D57 P50 DDR1_DQ_7_2/DDR1_DQ_7_2/DDR3_DQ_3_2/DDR7_DQ_1_2 DDR1_MA_4/DDR4_CS_0/DDR4_CA_2/DDR4_CA_2/DDR2_CA_12 AK48 DDR_B_MA13 DDR_B_MA4 <24>
DDR_A_D56BP50 DDR1_DQ_3_1/DDR0_DQ_7_1/DDR1_DQ_3_1/DDR3_DQ_1_1 DDR0_MA_13/DDR1_CS_1/DDR1_CS_0/DDR1_CA_3/DDR0_CA_5 CM50DDR_A_ODT0 DDR_A_MA13 <23> DDR_B_D56 P53 DDR1_DQ_7_1/DDR1_DQ_7_1/DDR3_DQ_3_1/DDR7_DQ_1_1 DDR1_MA_13/DDR5_CS_1/DDR5_CS_0/DDR5_CA_3/DDR2_CA_5 AE50 DDR_B_ODT0 DDR_B_MA13 <24>
DDR1_DQ_3_0/DDR0_DQ_7_0/DDR1_DQ_3_0/DDR3_DQ_1_0 DDR0_ODT_0/DDR1_CS_0/DDR1_CA_2/DDR1_CA_2/DDR0_CA_6 CJ57 DDR_A_ACT# DDR_A_ODT0 <23> DDR1_DQ_7_0/DDR1_DQ_7_0/DDR3_DQ_3_0/DDR7_DQ_1_0 DDR1_ODT_0/DDR5_CS_0/DDR5_CA_2/DDR5_CA_2/DDR2_CA_6 AC57 DDR_B_ACT# DDR_B_ODT0 <24>
DDR0_ACT_N/DDR2_CS_1/DDR2_CS_0/DDR2_CA_3/DDR1_CA_9 CF56 DDR_A_ACT# <23> DDR1_ACT_N/DDR6_CS_1/DDR6_CS_0/DDR6_CA_3/DDR3_CA_9 Y56 DDR_B_ACT# <24>
NC/DDR2_CS_0/DDR2_CA_2/DDR2_CA_2/DDR1_CA_2 CH48 DDR_A_PAR NC/DDR6_CS_0/DDR6_CA_2/DDR6_CA_2/DDR3_CA_2 AA48 DDR_B_PAR
DDR0_PAR/DDR3_CS_1/DDR3_CS_0/DDR3_CA_3/DDR1_CA_3 CC50 DDR_A_MA2 DDR_A_PAR <23> DDR1_PAR/DDR7_CS_1/DDR7_CS_0/DDR7_CA_3/DDR3_CA_3 T50 DDR_B_MA2 DDR_B_PAR <24>
DDR0_MA_2/DDR3_CS_0/DDR3_CA_2/DDR3_CA_2/DDR1_CA_1 DDR_A_MA2 <23> DDR1_MA_2/DDR7_CS_0/DDR7_CA_2/DDR7_CA_2/DDR3_CA_1 DDR_B_MA2 <24>
DDR4 / LP4x / LP5_ascend / LP5_descend / DDR5 CV50 DDR_A_CS#0 DDR_A_CS#0 <23>
DDR4 / LP4x / LP5_ascend / LP5_descend / DDR5 AM50 DDR_B_CS#0 DDR_B_CS#0 <24>
DDR0_CS_0/NC/DDR1_CS_1/DDR1_CA_4/DDR0_CA_4 CJ50 DDR_A_MA0 DDR1_CS_0/NC/DDR5_CS_1/DDR5_CA_4/DDR2_CA_4 AC50 DDR_B_MA0
DDR0_MA_0/NC/DDR3_CS_1/DDR3_CA_4/DDR1_CA_5 CV57 DDR_A_MA1 DDR_A_MA0 <23> DDR1_MA_0/NC/DDR7_CS_1/DDR7_CA_4/DDR3_CA_5 AM60 DDR_B_MA1 DDR_B_MA0 <24>
DDR0_MA_1/NC/DDR0_CS_1/DDR0_CA_4/DDR0_CS_0 CJ60 DDR_A_MA11 DDR_A_MA1 <23> DDR1_MA_1/NC/DDR4_CS_1/DDR4_CA_4/DDR2_CS_0 AB56 DDR_B_MA11 DDR_B_MA1 <24>
DDR0_MA_11/NC/DDR2_CS_1/DDR2_CA_4/DDR1_CA_11 DDR_A_MA11 <23> DDR1_MA_11/NC/DDR6_CS_1/DDR6_CA_4/DDR3_CA_12 DDR_B_MA11 <24>
BF61 DDR_A_ALERT# DDR_A_ALERT# <23> BG57 DDR_B_ALERT# DDR_B_ALERT# <24>
DDR0_ALERT_N BG60 +0.6V_A_VREFCA DDR1_ALERT_N BG55 +0.6V_B_VREFCA
DDR0_VREF_CA0 +0.6V_A_VREFCA DDR1_VREF_CA0 +0.6V_B_VREFCA
B BG50 DDR_PG_CTRL Trace width/Spacing >= 20mils Trace width/Spacing >= 20mils B
DDR_VTT_CTL EE53 DDR_DRAMRST#
DRAM_RESET#
ADL-P_BGA1744
A56
DDR_COMP_1 B56 DDR_RCOMP RC32 1 2 100_0201_1% @
DDR_COMP_2
ADL-P_BGA1744
Follow 633909_ADL_P_DDR4_SODIMM_1DPC_RVP_Rev0p7
@
UC1D
REV0.6
AF27
AH20 RSVD_1
Buffer with Open Drain Output AK22 RSVD_2
+1.2V_VDDQ AK40 RSVD_4
For VTT power control AL30 RSVD_6
+1.2V_VDDQ +3VS AL40 RSVD_7
BG47 RSVD_8
RSVD_9
1
0.1U_0201_10V6K 2 1 CC4 BG53

1
RC33 DT42 RSVD_10

UC2 RC35 470_0402_5% EE46 RSVD_13
1 5 EF33 RSVD_15
100K_0201_5%
NC VCC PVT EH41 RSVD_16
2
DDR_PG_CTRL 2 RSVD_20
2
A 4 DDR_DRAMRST# RC34 1 RS@ 2 DDR_DRAMRST#_R

Y SM_PG_CTRL <89> DDR_DRAMRST#_R <23,24>
3 0_0201_5%
GND ADL-P_BGA1744
2
74AUP1G07GW_TSSOP5 ESD@ @
CC5
RVP 0511 33P_0201_50V8J
1
DDR_PG_CTRL 1 2 ESD change to pop 10/07

A CC6 2200P_0201_25V7K A
XEMC@
2200P for power sequence tCPU19

100P for ESD reserve

ADL-P(3/14)DDR4
1A
5 4 3 2 1
5 4 3 2 1
+3VALW_PRIM
check power level & TLS en or not? 1213 +3VALW_PRIM
SOC_GPP_B23 RC36 2 @ 1 4.7K_0201_5%
+3V_SPI SOC_GPP_C2
SOC_GPP_B23 RC465 1 @ 2 20K_0201_5% TLS CONFIDENTIALITY SOC_GPP_C2 4.7K_0201_5% 1 2 RC37
CPUNSSC CLOCK FREQ INTERNAL PD 20K
INTERNAL PD 20K HIGH: TLS CONFIDENTIALITY ENABLE 1 2 RC463
LOW: TLS CONFIDENTIALITY DISABLE(Default) 20K_0201_5% @
HIGH: 19.2 MHz (form internal divider)
LOW: 38.4 MHz (direct form crystal) (Default)
1
1
Internal PD 20K
RC38 RC39 RC40
4.7K_0201_5% 100K_0201_5% 100K_0201_5%
SOC_SPI_0_D0
BOOT HALT +3VALW_PRIM
2
2
INTERNAL PU RVP is different from EDS description
SOC_SPI_0_D0 HIGH: ENABLED
LOW: DISABLED SOC_SML0ALERT# 4.7K_0201_5% 1 @ 2 RC41
SOC_SPI_0_D2 SOC_SPI_0_D2
External pull-up is required. 20K_0201_5% 1 @ 2 RC464
SOC_SPI_0_D3 Recommend 100K if pulled up to 3.3V
75K if pulled up to 1.8V. 20200727
- Remove D0/D1/CLK intersheet UC1E SOC_SML0ALERT#
D INTERNAL PU INTERNAL PD 20K D
REV0.6
1
1
SOC_SPI_0_D3 SOC_SPI_0_CLK EG56 EL38 SOC_SMBCLK This is bit 0 (LSB) of a total of 4-bit encoded pin straps for boot configuration
External pull-up is required. SOC_SPI_0_D3 SPI0_CLK GPP_C0/SMBCLK SOC_SMBDATA SOC_SMBCLK <23,24> Boot Strap 1,2,3, (on GPP_H0, GPP_H1, GPP_H2 respectively).
RC313 RC312 RC311 EC59 EK38 SOC_SMBDATA <23,24> (Link to DDR)
Recommend 100K if pulled up to 3.3V SOC_SPI_0_D2 EC61 SPI0_IO3 GPP_C1/SMBDATA EN38 SOC_GPP_C2
4.7K_0201_5% 4.7K_0201_5% 100K_0201_5%
@ @ @ 75K if pulled up to 1.8V. SOC_SPI_0_D1 EF59 SPI0_IO2 GPP_C2/SMBALERT#
INTERNAL PU SOC_SPI_0_D0 SPI0_MISO SOC_SML0CLK
EF57 EE38
SOC_SML0CLK <42>
2
1 SOC_SPI_0_CS#1 EG58 SPI0_MOSI GPP_C3/SML0CLK EF38 SOC_SML0DATA

T234 @ SPI0_CS1# GPP_C4/SML0DATA SOC_SML0DATA <42> (To TBT)
SOC_SPI_0_CS#0 EF61 EH38 SOC_SML0ALERT#
SOC_SPI_0_CS#2 EF56 SPI0_CS0# GPP_C5/SML0ALERT#
<66> SOC_SPI_0_CS#2 SPI0_CS2# SOC_SML1CLK
ET38
PCB_ID1 GPP_C6/SML1CLK SOC_SML1DATA SOC_SML1CLK <43> +3VS
FC28 ER38 (To PD controller)
GPP_E11/THC0_SPI1_CLK/GSPI0_CLK GPP_C7/SML1DATA SOC_GPP_B23 SOC_SML1DATA <43>
EF23 EF41
EE23 GPP_E2/THC0_SPI1_IO3 GPP_B23/SML1ALERT#/PCHHOT# SOC_SMBDATA RC42 1 2 2.2K_0402_5%
SOC_GPP_E12 EL23 GPP_E1/THC0_SPI1_IO2 DT49 ESPI_CLK RC50 1 EMI@ 2 33_0201_5% ESPI_CLK_R SOC_SMBCLK RC44 1 2 2.2K_0402_5%
+1.8VALW_PRIM GPP_E12/THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO GPP_A9/ESPI_CLK ESPI_IO3 ESPI_IO3_R ESPI_CLK_R <58>
EN23 DP52 RC51 1 2 33_0201_5%
PCB_ID0 GPP_E13/THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI GPP_A3/ESPI_IO3/SUSACK# ESPI_IO2 ESPI_IO2_R ESPI_IO3_R <58>
FA28 DT54 RC52 1 2 33_0201_5% 10P_0201_50V8J1 2 CC7
SOC_TS_PWR_EN GPP_E10/THC0_SPI1_CS#/GSPI0_CS0# GPP_A2/ESPI_IO2/SUSWARN#/SUSPWRDNACK ESPI_IO1 ESPI_IO1_R ESPI_IO2_R <58>
EY25 DT44 RC53 1 2 33_0201_5%
<38> SOC_TS_PWR_EN GPP_E17/THC0_SPI1_INT# GPP_A1/ESPI_IO1 ESPI_IO1_R <58>
1
SOC_GPP_E6 EH23 DP51 ESPI_IO0 RC54 1 2 33_0201_5% ESPI_IO0_R @RF@

GPP_E6/THC0_SPI1_RST# GPP_A0/ESPI_IO0 ESPI_CS# ESPI_IO0_R <58>
RC43 DP44 RF Suggestion
GPP_A4/ESPI_CS0# ESPI_CS# <58>
20K_0201_5% EN33 DT46
SOC_GPP_F15 EN36 GPP_F11/THC1_SPI2_CLK/GSPI1_CLK GPP_A23/ESPI_CS1# DT51 ESPI_RST#
05/13 Follow ADL_DDR4_RVP_rev07 GPP_F15/GSXSRESET#/THC1_SPI2_IO3 GPP_A10/ESPI_RESET# ESPI_RST# <58>
SOC_GPP_F14 EL36 DP47 +3VALW_PRIM
2
SOC_GPP_E6 SOC_GPP_F13 ET33 GPP_F14/GSXDIN/THC1_SPI2_IO2 GPP_A5/ESPI_ALERT0# DP54

EL31 GPP_F13/GSXSLOAD/THC1_SPI2_IO1/GSPI1_MISIO/I2C1A_SDA GPP_A6/ESPI_ALERT1# SOC_SML0CLK 499_0201_1% 1 2 RC45
GPP_F12/GSXDOUT/THC1_SPI2_IO0/GSPI1_MOSI/I2C1A_SCL
1
SOC_GPP_F16 EL33 SOC_SML0DATA 499_0201_1% 1 2 RC46

RC48 Signal: SOC_GPP_E6 ET36 GPP_F16/GSXCLK/THC1_SPI2_CS#/GSP1_CS0# SOC_SML1CLK 1K_0201_5% 1 2 RC47
Usage: JTAG ODT Disable ER33 GPP_F18/THC1_SPI2_INT# SOC_SML1DATA 1K_0201_5% 1 2 RC49
4.7K_0201_5%
@ NO INTERNAL PU/PD GPP_F17/THC1_SPI2_RST#
0=> JTAG ODT is disabled 1 CL_CLK EE26
1=> JTAG ODT is enabled T324 @
2
1 CL_DATA EF26 CL_CLK CC9

T325 @ CL_RST# CL_DATA ESPI_CLK_R +1.8VALW_PRIM
T326 @ 1 EH26 1 2
CL_RST#
10P_0201_50V8J
XEMC@ ESPI_CS# RC55 2 @ 1 10K_0201_5%
SOC_SPI_0_CLK ADL-P_BGA1744
CC8 2 1 10P_0201_50V8J EMC Suggestion
@
XEMC@ EMC Suggestion
SOC_SPI_0_CLK RC56 2 GLITCH@1 100K_0201_5%
ESPI_RST# RC57 2 GLITCH@1 75K_0201_5%
C C
A3/A5 Strap(GPIO) Audio IC Strap(GPIO) VGA Strap(GPIO) Strap(GPIO) (Reserve) Strap(GPIO) (Reserve)
+3VALW_PRIM +3VALW_PRIM +3VALW_PRIM +3VALW_PRIM +3VALW_PRIM
Follow ADL_DDR4_RVP_rev07 for Glitch
From EC MAF - Master Attached Flash

UMA Single SPI Flash attached to SPI Bus
1
(For share ROM)

1
RC58 RC59 EC FW access through eSPI Bus

ASPIRE3@ 10K_0402_5% 256@ 10K_0402_5% RC60 RC480 RC491
UMA@ 10K_0402_5% @ 10K_0402_5% @ 10K_0402_5%
2
SOC_GPP_E12 SOC_GPP_F16 SOC_GPP_F15 SOC_GPP_F14 SOC_GPP_F13

1 2
1 2
1 2
1
RC61 RC62 RC63 RC481 RC492

ASPIRE5@ 10K_0402_5% 256M@ 10K_0402_5% VGA@ 10K_0402_5% 10K_0402_5% 10K_0402_5%
DIS
2
Default pull-down 12/6
PCB ID +3VALW_PRIM
1
15@
RC64 10K_0402_5%
SD028100280 RC64 RC65
10K_0402_5% 10K_0402_5%
15@ @ @
2
RC67 10K_0402_5% PCB_ID0

SD028100280 PCB_ID1
* SPI0 1 load topology: *** SPI0 3 load topology:

R1 is required 33 ohm±5% for 1.8V, 62 ohm±5% for 3.3V. R1 is required 15 ohm±10% for 1.8V, 33 ohm±5% for 3.3V.
1
RC66 RC67 R2 is required 10 ohm for 1.8V and 3.3V.

10K_0402_5% 10K_0402_5% ** SPI0 2 load topology: It is an optional to have R2 on the channel. It can be removed to reduce BOM cost.
B
@ @
SPI ROM R1 is required 33 ohm±5% for 1.8V, 56 ohm±5% for 3.3V.
B
2
R2 is required 5 ohm for 1.8V and 3.3V. **** CS# does not need series resistor
It is an optional to have R2 on the channel. It can be removed to reduce BOM cost.
+3VALW_PRIM 3mA +3V_SPI
Project Project_ID1 Project_ID0 PartNumber - Description RC68 1 RS@ 2 0_0402_5%
14" 0 0
15"/17" 20210511 - 32M SPI ROM (WSON8)
0 1
To SPI ROM R2 R1
17"(Reserve) 1 0 Reserve for 17"
CONN@
SOC_SPI_0_CLK RC69 1 1LD@ 2 0_0402_5% SOC_SPI_0_CLK_R SOC_SPI_0_CLK_R RC70 1 1LD@ 2 62_0201_1% SOC_SPI_0_CLK_R1 JC1
1 1 SOC_SPI_0_D0 RC466 1 1LD@ 2 0_0402_5% SOC_SPI_0_D0_R SOC_SPI_0_CLK_R <66> SOC_SPI_0_D0_R RC72 1 1LD@ 2 62_0201_1% SOC_SPI_0_D0_R1 SOC_SPI_0_D0_R1 5 2 SOC_SPI_0_D1_R1
SOC_SPI_0_D1 SOC_SPI_0_D1_R SOC_SPI_0_D0_R <66> SOC_SPI_0_D1_R SOC_SPI_0_D1_R1 D Q
RC467 1 1LD@ 2 0_0402_5% RC74 1 1LD@ 2 62_0201_1%
SOC_SPI_0_D2 SOC_SPI_0_D2_R SOC_SPI_0_D1_R <66> SOC_SPI_0_D2_R SOC_SPI_0_D2_R1 SOC_SPI_0_CLK_R1
RC76 1 1LD@ 2 0_0402_5% RC75 1 1LD@ 2 62_0201_1% 6
SOC_SPI_0_D3 RC77 1 1LD@ 2 0_0402_5% SOC_SPI_0_D3_R SOC_SPI_0_D3_R RC78 1 1LD@ 2 62_0201_1% SOC_SPI_0_D3_R1 C
SOC_SPI_0_CS#0 1
S
RC69 2LD@ RC466 2LD@ RC467 2LD@ RC76 2LD@ RC77 2LD@ RC70 2LD@ RC72 2LD@ RC74 2LD@ RC75 2LD@ RC78 2LD@ SOC_SPI_0_D3_R1 7
HOLD
+3V_SPI SOC_SPI_0_D2_R1 3
W
4.99_0402_1% 4.99_0402_1% 4.99_0402_1% 4.99_0402_1% 4.99_0402_1% 56_0201_1% 56_0201_1% 56_0201_1% 56_0201_1% 56_0201_1%
+3V_SPI 8 4
SD034499B80 SD034499B80 SD034499B80 SD034499B80 SD034499B80 SD000010J80 SD000010J80 SD000010J80 SD000010J80 SD000010J80 VCC VSS
ACES_50950-0084N-001_ROM
ACES_50950-0084N-001_8P-NPM
JC1 cover solder mask 11/23 PVT
20200813 remove Memory Down Strap Topology BOM Config

+3V_SPI
UC4 CC10
32M 1LD@ SOC_SPI_0_CS#0 1 8 +3V_SPI 1 2 0.1U_0201_10V6K
/CS VCC
32M+TPM 2LD@+2LDTPM@ SOC_SPI_0_D1_R1 2 7 SOC_SPI_0_D3_R1
IO1 IO3
SOC_SPI_0_D2_R1 3 6 SOC_SPI_0_CLK_R1 1 2
A IO2 CLK A
4 5 SOC_SPI_0_D0_R1 @EMC@ CC11
GND IO0 10P_0201_50V8J
9
PAD
GD25R256DYIGR_WSON8_8X6
SA0000D4D00
S IC FL 256M GD25LB256EYIGR WSON 8P SPI ROM

ADL-P(4/14)SPI,ESPI,SMB
1A
5 4 3 2 1
5 4 3 2 1
UC1G
REV0.6
EY34 ER56 HDA_BIT_CLK
GPP_D19/I2S_MCLK1_OUT GPP_R0/HDA_BCLK/I2S0_SCLK/DMIC_CLK_B0/HDAPROC_BCLK EP60 HDA_SYNC
EV53 GPP_R1/HDA_SYNC/I2S0_SFRM/DMIC_CLK_B1 ER57 HDA_SDOUT
EY53 GPP_S0/SNDW0_CLK/I2S1_SCLK GPP_R2/HDA_SDO/I2S0_TXD/HDAPROC_SDO ER59 HDA_SDIN0
GPP_S1/SNDW0_DATA/I2S1_SFRM GPP_R3/HDA_SDI0/I2S0_RXD/HDAPROC_SDI
D D
PCH_DMIC_CLK FA50 ER53 HDA_RST#
<38> PCH_DMIC_CLK PCH_DMIC_DATA GPP_S2/SNDW1_CLK/DMIC_CKL_A0/I2S1_TXD GPP_R4/HDA_RST#/I2S2_SCLK/DMIC_CLK_A0
DMIC FC50 ET53
<38> PCH_DMIC_DATA GPP_S3/SNDW1_DATA/DMIC_DATA0/I2S1_RXD GPP_R5/HDA_SDI1/I2S2_SFRM/DMIC_DATA0 EB44
EV50 GPP_R6/I2S2_TXD/DMIC_CLK_A1 EB46
Change to GPP_S2/GPP_S3 EY50 GPP_S4/SNDW2_CLK/DMIC_CLK_B0 GPP_R7/I2S2_RXD/DMIC_DATA1
GPP_S5/SNDW2_DATA/DMIC_CLK_B1 DVT
due to Intel spec define 2021/9/13 DV51
EW48 GPP_A11/PMC_I2C_SDA DV47 SOC_BT_ON R71 1 RS@ 2 0_0402_5%
GPP_S6/SNDW3_CLK/DMIC_CLK_A1 GPP_A13/PMC_I2C_SCL BT_ON <52>
EY48
GPP_S7/SNDW3_DATA/DMIC_DATA1 FA53 SNDW _RCOMP RC90 1 2 200_0201_1%
SNDW_RCOMP_1 FC53
SNDW_RCOMP_2
ADL-P_BGA1744
@
20200819
HDA_SDOUT HDA_SYNC CC12 @RF@1 2 22P_0201_25V8
HDA for AUDIO - Remove RC180 BOM config , must pop of PDG . FLASH DESCRIPTOR SECURITY OVERRIDE
HDA_SDOUT_R RC91 1 2 33_0201_5% HDA_SDOUT INTERNAL PD 20K HDA_BIT_CLK CC13 @RF@1 2 22P_0201_25V8
<56> HDA_SDOUT_R HDA_BIT_CLK_R RC92 1 2 33_0201_5% HDA_BIT_CLK
To Enable ME Override HIGH: OVERRIDEN
<56> HDA_BIT_CLK_R LOW: SECURITY MEASURES NOT OVERRIDEN (DEFAULT)
HDA_SYNC_R RC93 1 2 33_0201_5% HDA_SYNC HDA_SDOUT CC14 @RF@1 2 22P_0201_25V8
<56> HDA_SYNC_R HDA_RST#_R HDA_RST#
C RC94 1 2 33_0201_5% C
<56> HDA_RST#_R HDA_SDIN0 HDA_SDIN0 CC15 @RF@1 2 22P_0201_25V8
<56> HDA_SDIN0
DVT
HDA_RST# CC16 @RF@1 2 22P_0201_25V8
R72 1 RS@ 2 0_0201_5% HDA_SDOUT
<58> ME_EN
PCH_DMIC_CLK CC17 @RF@1 2 22P_0201_25V8
100K_0201_5% 1 GLITCH@2 RC95 HDA_BIT_CLK PCH_DMIC_DATA CC18 @RF@1 2 22P_0201_25V8

100K_0201_5% 1 GLITCH@2 RC96 HDA_RST# RC97 1 @ 2 100K_0201_5%
Close SOC
572631_ICL_PCH_LP_EDS_Vol_1_Rev_0p7
VCCPGPPR: Audio Power 3.3V, 1.8V, or 1.5V
Follow Need to sync with codec VDDIO
627205_ADL P_PDG for Glitch
CC19 2 1 10P_0201_50V8J HDA_BIT_CLK_R
XEMC@ EMC Suggestion
B B
A A

ADL-P(5/14)HDA,SNDW
5 4 3 2 1
5 4 3 2 1
+3VS
Follow
627205_ADL P_PDG_Rev0p7 for Glitch CLKREQ_GPU# 1 2
10K_0201_5% RC99
UC1K CLKREQ_WLAN# 10K_0201_5% 1 2 RC100
+3VALW REV0.6 CLKREQ_LAN# 10K_0201_5% 1 2 RC101
DP1 DY46 SATA_GP1 1 CLKREQ_SSD1# 10K_0201_5% 1 2 RC102
CLKOUT_PCIE_P6 GPP_A12/SATAXPCIE1/SATAGP1/SRCCLKREQ9B# SATA_GP0 @ T318
DP3 EV22 1 5/28 remove SSD port3 CLKREQ_SSD2# 10K_0201_5% 1 2 RC240
CLKOUT_PCIE_N6 GPP_E0/SATAXPCIE0/SATAGP0/SRCCLKREQ9# @ T319
RC106 1 2 100K_0201_5% PM_SLP_S0# EY22 GPP_E16 1 @ T331
DU5 GPP_E16/RSVD_TP/SRCCLKREQ8# EB54 Intel debug port use
RC450 1 2
GLITCH@ 100K_0201_5% SLP_SUS# 5/28 remove SSD port3 DU6 CLKOUT_PCIE_P5 GPP_A8/SRCCLKREQ7# EF31
RC451 1 2
GLITCH@ 100K_0201_5% PM_SLP_S5# CLKOUT_PCIE_N5 GPP_F19/SRCCLKREQ6# ET43 5/28 remove SSD port3
RC108 1 2
GLITCH@ 100K_0201_5% PM_SLP_S4# CLK_PCIE_SSD2 DP5 GPP_H23/SRCCLKREQ5# ER48 CLKREQ_SSD2#
PM_SLP_S3# <69> CLK_PCIE_SSD2 CLK_PCIE_SSD2# CLKOUT_PCIE_P4 GPP_H19/SRCCLKREQ4# CLKREQ_SSD1# CLKREQ_SSD2# <69> SSD2
RC110 1 2
GLITCH@ 100K_0201_5% SSD2 DP6 FC34
PM_SLP_A# <69> CLK_PCIE_SSD2# CLKOUT_PCIE_N4/UFS_REF_CLK GPP_D8/SRCCLKREQ3# CLKREQ_LAN# CLKREQ_SSD1# <69> SSD1
RC452 1 2
GLITCH@ 100K_0201_5% FC31
1 2 PM_SLP_LAN# CLK_PCIE_SSD1 DN10 GPP_D7/SRCCLKREQ2# FB36 CLKREQ_WLAN# CLKREQ_LAN# <51> GLAN
RC453 GLITCH@ 100K_0201_5%
1 2 PM_SLP_WLAN# <69> CLK_PCIE_SSD1 CLK_PCIE_SSD1# DN11 CLKOUT_PCIE_P3 GPP_D6/SRCCLKREQ1# FB29 CLKREQ_GPU# CLKREQ_WLAN# <52>WLAN
RC454 GLITCH@ 100K_0201_5% SSD1 <69> CLK_PCIE_SSD1# CLKOUT_PCIE_N3 GPP_D5/SRCCLKREQ0# CLKREQ_GPU# <33> dGPU
CLK_PCIE_LAN DR4 EV6 SOC_XTAL38.4_OUT +3VALW
<51> CLK_PCIE_LAN CLK_PCIE_LAN# CLKOUT_PCIE_P2 XTAL_OUT SOC_XTAL38.4_IN
GLAN <51> CLK_PCIE_LAN# DR6 EV8
CLKOUT_PCIE_N2 XTAL_IN PM_BATLOW# 10K_0201_5% 2 1 RC107
D 05/18 update CLK_PCIE_WLAN DU1 EJ61 SUSCLK WAKE# 1K_0201_5% 1 2 RC109 D
<52> CLK_PCIE_WLAN CLK_PCIE_WLAN# CLKOUT_PCIE_P1 GPD8/SUSCLK LAN_WAKE#
WLAN DU3 10K_0201_5% 2 1 RC111
<52> CLK_PCIE_WLAN# CLKOUT_PCIE_N1 SOC_RTCX2
EV58 SPIVCCIOSEL SPIVCCIOSEL 1K_0201_5% 1 @ 2 RC112
+3VALW CLK_PEG_VGA DT10 RTCX2 EV56 SOC_RTCX1 3.3V / 1.8V SELECT FOR SPI
<27> CLK_PEG_VGA CLK_PEG_VGA# CLKOUT_PCIE_P0 RTCX1 HIGH: 1.8V
dGPU DT11 4.7K_0201_5% 2 1 RC113
AC_PRESENT_R <27> CLK_PEG_VGA# CLKOUT_PCIE_N0 SOC_RTCRST# LOW: 3.3V
RC487 1 2 10K_0201_5% FA55
XCLK_BIASREF RTCRST# SOC_SRTCRST# Follow 633909_ADL_P_DDR4_RVP_Rev_0p7
2 1 DJ3 FB56
RC488 1 2 10K_0201_5% PCH_DPWROK RC114 60.4_0402_1% XCLK_BIASREF SRTCRST# Intel debug port use
EB52 SUSCLK 1K_0201_5% 1 @ 2 RC115
RC489 1 2 10K_0201_5% SYS_PWROK GPP_A7/SRCCLK_OE7# EW23 GPP_E15 1
GPP_E15/RSVD_TP/SRCCLK_OE8# @ T332
RC490 1 2 10K_0201_5% PCH_PWROK Follow
ADL-P_BGA1744 633909_ADL_P_DDR4_SODIMM_1DPC_RVP
@
+3VALW
+3VALW
RC116 1 2 10K_0201_5% SOC_PD_INT# RT1126 2 1 10K_0201_5%
CC20 2 1 SYS_RESET#
XESD@ 0.1U_0201_10V6K CPU_C10_GATE# 1 2
RC118 100K_0201_5%
CC21 2 1 SYS_PWROK UC1L
XESD@ 0.1U_0201_10V6K REV0.6
SLP_SUS# EN53 EM61 PBTN_OUT#_R Follow
PCH_PWROK <58> SLP_SUS# SLP_SUS# GPD3/PWRBTN# PM_BATLOW# SLP_DRAM#
CC121 2 1 EM56 1 2
@ESD@ PM_SLP_S5# EG60 GPD0/BATLOW# EJ59 AC_PRESENT_R LA-L111P R01(DDR4)
0.1U_0201_10V6K RC120 100K_0201_5%
PM_SLP_S4# EP56 GPD10/SLP_S5# GPD1/ACPRESENT
SOC_PLTRST# <16> PM_SLP_S4# PM_SLP_S3# GPD5/SLP_S4# SOC_PD_INT#
CC22 1 2 EM59 EA56
<16> PM_SLP_S3# PM_SLP_A# GPD4/SLP_S3# GPP_B11/PMCALERT# CPU_C10_GATE# SOC_PD_INT# <43> EC_VCCST_PG
ESD@ 100P_0201_50V8J EM57 ER46 1 2
PM_SLP_WLAN# EJ57 GPD6/SLP_A# GPP_H18/PROC_C10_GATE# ET48 SX_EXIT_HOLDOFF# 1 CC23 XESD@
GPD9/SLP_WLAN# GPP_H3/SX_EXIT_HOLDOFF# @ T238
05/27 update 0.1U_0201_10V6K
ESD Suggestion PM_SLP_S0# DW59 ET51 WAKE# 5/25
<59,66> PM_SLP_S0# PM_SLP_LAN# GPP_B12/SLP_S0# WAKE#
EK53 ESD Suggestion
SLP_LAN# EP58 LAN_WAKE# SOC_RTCX1
EC_RSMRST# EH53 GPD2/LAN_WAKE# EJ56 GPD11 1
+RTCVCC <58> EC_RSMRST# SYS_RESET# RSMRST# GPD11/LANPHYPC @ T240
EK26
SOC_PLTRST# DW57 SYS_RESET# EK60 TBT_RETIMER_RESET# 1 SOC_RTCX2
GPP_B13/PLTRST# GPD7 @ T241
SOC_SRTCRST# PCH_DPWROK SLP_DRAM# RC129
RC1241 2 20K_0201_5% EE48 FA22
<11,58> PCH_DPWROK SYS_PWROK DSW_PWROK GPP_E8/SLP_DRAM#
EK23 2 1
<58> SYS_PWROK PCH_PWROK SYS_PWROK EC_VCCST_PG
CC24 1 2 1U_0201_6.3V6M CLR ME EH51 DJ8
<58> PCH_PWROK PCH_PWROK VCCST_PWRGD VCCST_OVERRIDE VCCST_OVERRIDE_R
DK4 RC126 1 RS@ 2 0_0201_5%
SM_INTRUDER# DY44 VCCST_OVERRIDE 10M_0201_1%
INTRUDER#
2
SPIVCCIOSEL EL53 EH28 GPP_F20 1
SPIVCCIOSEL GPP_F20/EXT_PWR_GATE# @ T320
EH31 RC127 RC133
C RC1251 2 20K_0201_5% SOC_RTCRST# T242 @ 1 H_PROCPWRGD BG11 GPP_F21/EXT_PWR_GATE2# C
SOC_RTCRST# <58> PROCPWRGD 0_0201_5% 0_0201_5%
CC25 1 2 1U_0201_6.3V6M
1
ADL-P_BGA1744
JCMOS1 1 @ 2 0_0603_5% CLR CMOS
@
SOC_RTCX2_R
SOC_RTCX1_R
VCCSTPWRGOOD_TGSS 1 RS@ 2 VCCST_OVERRIDE_R
SM_INTRUDER# <15> VCCSTPWRGOOD_TGSS YC1
RC1281 2 1M_0201_5% RC131 0_0201_5%
PDG 6.2.5 2 1
INTRUDER# should have a weak external pull-up to VccRTC 32.768KHZ_12.5_X1A000171000118
2012@
YC3
RC130 1 @ 2 0_0201_5% <58> AC_PRESENT RC134 1 RS@ 2 0_0201_5% AC_PRESENT_R SJ100015U00
RC132 1 2 100K_0201_5% EC_RSMRST# RC135 1 RS@ 2 0_0201_5% PBTN_OUT#_R 2 1

<58> PBTN_OUT#
32.768KHZ_9PF_X1A00014100030
CC173 1 2 0.1U_0201_10V6K 3215@
@ESD@ 2 SJ10000PW00 2
CC26 CC27
DC2 18P_0201_50V8J 18P_0201_50V8J
+1.05V_PROC PM_SLP_S4# 2 1 1 1
From EC(open-drain) RB751S-40_SOD523-2 tCPU22/ tPCH28b

1
RC137 DC3
1K_0201_5% EC_VCCST_PG_R 2
DC4 1 PM_SLP_S3# SOC_XTAL38.4_IN
PM_SLP_S3# 2 PCH_PWROK 3
2
RC1381 2 60.4_0201_1% EC_VCCST_PG 1 PCH_DPWROK SOC_XTAL38.4_OUT

<58> EC_VCCST_PG_R SLP_SUS# PCH_DPWROK <11,58>
3 LRB715FT1G_SOT323-3 RC136 1 2 200K _0201_1%
@
LRB715FT1G_SOT323-3
1
tPLT17
DC14 RC139 RC140
2 1 SLP_SUS# DC5 33_0201_5% 33_0201_5%
VR_ON 2 1 PM_SLP_S3# EMI@ EMI@
+1.8V_PROC_EN No support PCIE5 port (U15/P28) RB751S-40_SOD523-2
<58,97> VR_ON
2
+1.8V_PROC can be NC RB751S-40_SOD523-2
SOC_XTAL38.4_OUT_R
SOC_XTAL38.4_IN_R
DC13 @
SUSP# RC141 1 @ 2 0_0201_5% +3VALW EC_RSMRST# 2
<16,38,58,69,78,85,89> SUSP# SPOK_3V
UC5 @ 1
PM_SLP_S3# PCH_DPWROK SPOK_3V <58,87,90>
RC143 1 @ 2 0_0201_5% 1 5 3
A VCC
VCCIN_AUX_CORE_VID 2 LRB715FT1G_SOT323-3
B
3 4 05/18 follow TD team YC2
GND Y +1.8V_PROC_EN <90> 1 3
B
RC143/UC5 Chnage to unpop 12/2 B
U74LVC1G08G-AL5-R_SOT353-5 DC15 2 2 4 2
Due to no support PCIE5 EC_RSMRST# 2
SA0000BJI00
RC144 1 @ 2 0_0201_5% 1 SPOK_5V CC28 38.4MHZ_10PF_8Y38420005 CC29
PCH_DPWROK SPOK_5V <43,58,87>
3 12P_0201_50V8J 12P_0201_50V8J
1 1
LRB715FT1G_SOT323-3 Add for sequence modify 2021/08/25
For Prevent EC Autoload issue 11/10

+3VALW
VCCST_EN
PCH PLTRST Buffer
1
DC6 VR_ON PVT
2 RC283 RC150 1 RS@ 2 0_0201_5%
<17,95> VCCIN_AUX_CORE_VID0 1 EC_VCCST_PG_R
10K_0201_5%
3 VCCIN_AUX_CORE_VID <16>
<17,95> VCCIN_AUX_CORE_VID1 +3VS
3
LRB715FT1G_SOT323-3 CC174 @
EC_VCCST_PG_R# 5 G
D
QC2A 1 2
1
D S
PJT138KA 2N SOT363-6
5
+3VALW_PRIM EC_VCCST_PG_R# 2 QC3 UC8 0.1U_0201_10V6K
4
6
G L2N7002WT1G_SC-70-3 SOC_PLTRST# 1
P
100K_0201_5% 1 2 RC147 VCCST_OVERRIDE_LS VCCST_OVERRIDE_LS <16> PM_SLP_S3# 2
D
B 4 PLT_RST_R#
S G
PLT_RST_R# <33,42,51,52,66,69>
3
100K_0201_5% 1 2 RC148 VCCST_OVERRIDE_N S QC2B 2 Y

@ A
G
PJT138KA 2N SOT363-6
1
1
6 74AHC1G08GW_SOT353-5
3
100K_0201_5% 1 2 RC149 VCCST_OVERRIDE_R D RC455 @
100K_0201_5%
GLITCH@
VCCST_OVERRIDE_N 2
2
G tCPU00/tCPU22
3 QC1A
D S PJT7838_SOT363-6
1
VCCST_OVERRIDE_R 5
G
QC1B
S PJT7838_SOT363-6
4
A
TGL use single MOS for sequnce A

ADL-P(6/14)CLK,GPIO
5 4 3 2 1
5 4 3 2 1
+3VS
UC1F
REV0.6
RC456 1 @ 2 10K_0201_5% SOC_DGPU_HOLD_RST# UART_2_CTXD_DRXD EN48 EY28 I2C_TS_INT#
<52> UART_2_CTXD_DRXD UART_2_CRXD_DTXD EN46 GPP_H11/UART0_TXD/M2_SKT2_CFG1 GPP_D14/ISH_UART0_TXD/I2C4B_SCL EV28 SOC_SLP_DS0# I2C_TS_INT# <38>
<52> UART_2_CRXD_DTXD GPP_H10/UART0_RXD/M2_SKT2_CFG0 GPP_D13/ISH_UART0_RXD/I2C4B_SDA SOC_GPP_D16 SOC_SLP_DS0# <42>
EL41 EY36 1 @ T243
RC484 1 VGA@ 2 10K_0201_5% SOC_DGPU_PWR_EN SOC_GC6_FB_EN EK41 GPP_H13/I2C7_SCL/UART0_CTS#/M2_SKT2_CFG3/ISH_GP7B/DEVSLP1B GPP_D16/ISH_UART0_CTS#/I2C7B_SCL EW36 SOC_TS_RST#
GPP_H12/I2C7_SDA/UART0_RTS#/M2_SKT2_CFG2/ISH_GP6B/DEVSLP0B GPP_D15/ISH_UART0_RTS#/I2C7B_SDA SOC_TS_RST# <38>
D SOC_DGPU_PWR_EN PANEL_OD_EN D
For Power up sequence 10/12 DVT EW30 FA34
<33> SOC_DGPU_PWR_EN SOC_DGPU_HOLD_RST# EV34 GPP_D18/UART1_TXD/ISH_UART1_TXD GPP_D3/ISH_GP3/BK3/SBK3 EY30 PANEL_OD_EN <38>
<33> SOC_DGPU_HOLD_RST# GPP_D17/UART1_RXD/ISH_UART1_RXD GPP_D2/ISH_GP2/BK2/SBK2
RC485 1 VGA@ 2 10K_0201_5% SOC_DGPU_HOLD_RST# 20200722 - Add for TBT4 EY31 New add for QHD Panel OD pin 10/19
RC89 1 2 SOC_DG_BB_FORCE_PWR EH46 GPP_D1/ISH_GP1/BK1/SBK1 EV31
<42,43> SOC_DG_BB_FORCE_PWR_R GPP_H5/I2C0_SCL GPP_D0/ISH_GP0/BK0/SBK0
RC486 1 @ 2 10K_0201_5% SOC_DGPU_PWR_EN 33_0201_5% EF46
GPP_H4/I2C0_SDA DR61 GPP_RCOMP RC151 1 2
+3VS I2C_1_SCL EH43 GPPC_RCOMP
Track Pad <63> I2C_1_SCL GPP_H7/I2C1_SCL
200_0201_1%
0528 rename <63> I2C_1_SDA EF43
I2C_1_SDA GPP_H6/I2C1_SDA
(For R-BOM) T244 @ 1SOC_GPP_B6 DT57
1SOC_GPP_B5 DT56 GPP_B6/ISH_I2C0_SCL/I2C2_SCL
For EC Debug UART / MIPI60 T245 @ GPP_B5/ISH_I2C0_SDA/I2C2_SDA
RC153 1 2 49.9K_0201_1% UART_2_CRXD_DTXD 1SOC_GPP_B8 DR56
T246 @ GPP_B8/ISH_I2C1_SCL/I2C3_SCL
1SOC_GPP_B7 DR58
UART_2_CTXD_DRXD T247 @ GPP_B7/ISH_I2C1_SDA/I2C3_SDA
RC154 1 2 49.9K_0201_1%
EN43
EL43 GPP_H9/I2C4_SCL/CNV_MFUART2_TXD
+3VS GPP_H8/I2C4_SDA/CNV_MFUART2_RXD
DN60
I2C_5_SCL <38> I2C_5_SCL GPP_B17/I2C5_SCL/ISH_I2C2_SCL
RC478 1 2 1K_0201_5% Touch screen DN57
I2C_5_SDA <38> I2C_5_SDA GPP_B16/I2C5_SDA/ISH_I2C2_SDA
RC479 1 2 1K_0201_5%
ADL-P_BGA1744
@
+3VALW_PRIM Track Pad

RC156 1 2 1K_0201_5% I2C_1_SCL
RC157 1 2 1K_0201_5% I2C_1_SDA
20200824
C
To dGPU Connect to SOC GPIO - Remove GPU_EVENT# , GN20 not used .
C
SOC_GC6_FB_EN RC160 1 RS@ 2 0_0201_5% GC6_FB_EN3V3 GC6_FB_EN3V3 <33>
B B
A A

ADL-P(7/14)GPIO
5 4 3 2 1
5 4 3 2 1
UC1H
REV0.6
PCIE4_A_CTX_DRX_P3 A20 C33
<69> PCIE4_A_CTX_DRX_P3 PCIE4_A_CTX_DRX_N3 C20 PCIEX4_A_TX_P_3 PCIEX8_TX_P_7 D33
<69> PCIE4_A_CTX_DRX_N3 PCIE4_A_CRX_DTX_P3 M22 PCIEX4_A_TX_N_3 PCIEX8_TX_N_7 J33
<69> PCIE4_A_CRX_DTX_P3 PCIE4_A_CRX_DTX_N3 M24 PCIEX4_A_RX_P_3 PCIEX8_TX_P_6 G33
<69> PCIE4_A_CRX_DTX_N3 PCIEX4_A_RX_N_3 PCIEX8_TX_N_6 C30
PCIE4_A_CTX_DRX_P2 G20 PCIEX8_TX_P_5 D30
<69> PCIE4_A_CTX_DRX_P2 PCIE4_A_CTX_DRX_N2 F20 PCIEX4_A_TX_P_2 PCIEX8_TX_N_5 J30
<69> PCIE4_A_CTX_DRX_N2 PCIE4_A_CRX_DTX_P2 V22 PCIEX4_A_TX_N_2 PCIEX8_TX_P_4 G30
<69> PCIE4_A_CRX_DTX_P2 PCIE4_A_CRX_DTX_N2 U22 PCIEX4_A_RX_P_2 PCIEX8_TX_N_4 C26
D <69> PCIE4_A_CRX_DTX_N2 PCIEX4_A_RX_N_2 PCIEX8_TX_P_3 D
D26
PCIE4_A_CTX_DRX_P1 A17 PCIEX8_TX_N_3 J26
<69> PCIE4_A_CTX_DRX_P1 PCIE4_A_CTX_DRX_N1 C17 PCIEX4_A_TX_P_1 PCIEX8_TX_P_2 G26
<69> PCIE4_A_CTX_DRX_N1 PCIE4_A_CRX_DTX_P1 AC22 PCIEX4_A_TX_N_1 PCIEX8_TX_N_2 C23
<69> PCIE4_A_CRX_DTX_P1 PCIE4_A_CRX_DTX_N1 AA22 PCIEX4_A_RX_P_1 PCIEX8_TX_P_1 D23
<69> PCIE4_A_CRX_DTX_N1 PCIEX4_A_RX_N_1 PCIEX8_TX_N_1 J23
PCIE4_A_CTX_DRX_P0 G17 PCIEX8_TX_P_0 G23
<69> PCIE4_A_CTX_DRX_P0 PCIE4_A_CTX_DRX_N0 F17 PCIEX4_A_TX_P_0 PCIEX8_TX_N_0
<69> PCIE4_A_CTX_DRX_N0 PCIE4_A_CRX_DTX_P0 M18 PCIEX4_A_TX_N_0 M39
<69> PCIE4_A_CRX_DTX_P0 PCIE4_A_CRX_DTX_N0 M19 PCIEX4_A_RX_P_0 PCIEX8_RX_P_7 M37
<69> PCIE4_A_CRX_DTX_N0 PCIEX4_A_RX_N_0 PCIEX8_RX_N_7 U37
PCIE4_RCONP_N F6 PCIEX8_RX_P_6 V37
A6 PCIEX4_RCOMP_N PCIEX8_RX_N_6 AA37
2.2K_0201_1%1 RC165 2 PCIE4_A_RCOMP_P C6 PCIEX4_A_RCOMP_P_1 PCIEX8_RX_P_5 AC37
A5 PCIEX4_A_RCOMP_P_2 PCIEX8_RX_N_5 U32
2.2K_0201_1%1 RC166 2 PCIE4_B_RCOMP_P D6 PCIEX4_B_RCOMP_P_1 PCIEX8_RX_P_4 V32
PCIEX4_B_RCOMP_P_2 PCIEX8_RX_N_4 AA32
PCIE4_B_CTX_C_DRX_P3 0.22U_0201_6.3V6K 2 1 VGA@ CC30 PCIE4_B_CTX_DRX_P3 A14 PCIEX8_RX_P_3 AC32
<27> PCIE4_B_CTX_C_DRX_P3 PCIE4_B_CTX_C_DRX_N3 0.22U_0201_6.3V6K 2 1 VGA@ CC31 PCIE4_B_CTX_DRX_N3 C14 PCIEX4_B_TXP_3 PCIEX8_RX_N_3 M29
<27> PCIE4_B_CTX_C_DRX_N3 PCIE4_B_CRX_C_DTX_P3 PCIE4_B_CRX_DTX_P3 PCIEX4_B_TXN_3 PCIEX8_RX_P_2
0.22U_0201_6.3V6K 2 1 VGA@ CC32 V17 M27
<27> PCIE4_B_CRX_C_DTX_P3 PCIE4_B_CRX_C_DTX_N3 0.22U_0201_6.3V6K 2 1 VGA@ CC33 PCIE4_B_CRX_DTX_N3 U17 PCIEX4_B_RXP_3 PCIEX8_RX_N_2 U27
<27> PCIE4_B_CRX_C_DTX_N3 PCIEX4_B_RXN_3 PCIEX8_RX_P_1 V27
PCIE4_B_CTX_C_DRX_P2 0.22U_0201_6.3V6K 2 1 VGA@ CC34 PCIE4_B_CTX_DRX_P2 G14 PCIEX8_RX_N_1 AA27
<27> PCIE4_B_CTX_C_DRX_P2 PCIE4_B_CTX_C_DRX_N2 0.22U_0201_6.3V6K 2 1 VGA@ CC35 PCIE4_B_CTX_DRX_N2 F14 PCIEX4_B_TXP_2 PCIEX8_RX_P_0 AC27
<27> PCIE4_B_CTX_C_DRX_N2 PCIE4_B_CRX_C_DTX_P2 PCIE4_B_CRX_DTX_P2 PCIEX4_B_TXN_2 PCIEX8_RX_N_0
0.22U_0201_6.3V6K 2 1 VGA@ CC36 AC17 Change to unpop due to no PCIE5
<27> PCIE4_B_CRX_C_DTX_P2 PCIE4_B_CRX_C_DTX_N2 0.22U_0201_6.3V6K 2 1 VGA@ CC37 PCIE4_B_CRX_DTX_N2 AA17 PCIEX4_B_RXP_2 A8
<27> PCIE4_B_CRX_C_DTX_N2 PCIEX4_B_RXN_2 PCIEX8_RCOMP_P_1 C8 PCIE5_RCOMPP RC167 1 @ 2 150_0201_1%
PCIE4_B_CTX_C_DRX_P1 0.22U_0201_6.3V6K 2 1 VGA@ CC38 PCIE4_B_CTX_DRX_P1 A11 PCIEX8_RCOMP_P_2 D8 PCIE5_RCOMPN
<27> PCIE4_B_CTX_C_DRX_P1 PCIE4_B_CTX_C_DRX_N1 0.22U_0201_6.3V6K 2 1 VGA@ CC39 PCIE4_B_CTX_DRX_N1 C11 PCIEX4_B_TXP_1 PCIEX8_RCOMP_N
dGPU <27> PCIE4_B_CTX_C_DRX_N1 PCIE4_B_CRX_C_DTX_P1 PCIE4_B_CRX_DTX_P1 PCIEX4_B_TXN_1
0.22U_0201_6.3V6K 2 1 VGA@ CC40 M13
<27> PCIE4_B_CRX_C_DTX_P1 PCIE4_B_CRX_C_DTX_N1 0.22U_0201_6.3V6K 2 1 VGA@ CC41 PCIE4_B_CRX_DTX_N1 M14 PCIEX4_B_RXP_1
<27> PCIE4_B_CRX_C_DTX_N1 PCIEX4_B_RXN_1
PCIE4_B_CTX_C_DRX_P0 0.22U_0201_6.3V6K 2 1 VGA@ CC42 PCIE4_B_CTX_DRX_P0 G11
<27> PCIE4_B_CTX_C_DRX_P0 PCIE4_B_CTX_C_DRX_N0 0.22U_0201_6.3V6K 2 1 VGA@ CC43 PCIE4_B_CTX_DRX_N0 F11 PCIEX4_B_TXP_0
<27> PCIE4_B_CTX_C_DRX_N0 PCIE4_B_CRX_C_DTX_P0 PCIE4_B_CRX_DTX_P0 PCIEX4_B_TXN_0
0.22U_0201_6.3V6K 2 1 VGA@ CC44 V12
C <27> PCIE4_B_CRX_C_DTX_P0 PCIE4_B_CRX_C_DTX_N0 0.22U_0201_6.3V6K 2 1 VGA@ CC45 PCIE4_B_CRX_DTX_N0 U12 PCIEX4_B_RXP_0 C
<27> PCIE4_B_CRX_C_DTX_N0 PCIEX4_B_RXN_0
ADL-P_BGA1744
@
UC1I
REV0.6
PCIE_CTX_DRX_P12 DY10 EM5 USB20_P10
<51> PCIE_CTX_DRX_P12 PCIE_CTX_DRX_N12 PCIE12_TXP/SATA1_TXP USB2P_10 USB20_N10 USB20_P10 <52>
DY11 EM6 NGFF WLAN (BT)
<51> PCIE_CTX_DRX_N12 PCIE_CRX_DTX_P12 EA4 PCIE12_TXN/SATA1_TXN USB2N_10 USB20_N10 <52>
GLAN (Gen1) <51> PCIE_CRX_DTX_P12 PCIE_CRX_DTX_N12 PCIE12_RXP/SATA1_RXP USB20_P9
EA6 EL18
<51> PCIE_CRX_DTX_N12 PCIE12_RXN/SATA1RXN USB2P_9 USB20_N9 USB20_P9 <66>
EN18 Finger Print
SATA_CTX_DRX_P0 USB2N_9 USB20_N9 <66>
EB10
<67> SATA_CTX_DRX_P0 SATA_CTX_DRX_N0 EB11 PCIE11_TXP/SATA0_TXP EN1 USB20_P8
SATA (Gen3) <67> SATA_CTX_DRX_N0 SATA_CRX_DTX_P0 PCIE11_TXN/SATA0_TXN USB2P_8 USB20_N8 USB20_P8 <38>
EC5 EN3 Touchscreen
(SATA Port 0) <67> SATA_CRX_DTX_P0 SATA_CRX_DTX_N0 EC6 PCIE11_RXP/SATA0_RXP USB2N_8 USB20_N8 <38>
<67> SATA_CRX_DTX_N0 PCIE11_RXN/SATA0_RXN ER16 USB20_P7
USB2P_7 USB20_N7 USB20_P7 <38>
ED10 ET16 Camera
ED11 PCIE10_TXP/UFS11_TXP USB2N_7 USB20_N7 <38>
EC1 PCIE10_TXN/UFS11_TXN EP4 USB20_P6
PCIE10_RXP/UFS11_RXP USB2P_6 USB20_N6 USB20_P6 <73>
EC3 EP6 USB3.1 Type-A Port (SUB)
PCIE10_RXN/UFS11_RXN USB2N_6 USB20_N6 <73>
PCIE_CTX_DRX_P9 EF10 FA15 USB20_P5
<52> PCIE_CTX_DRX_P9 PCIE_CTX_DRX_N9 EF11 PCIE9_TXP/UFS10_TXP USB2P_5 FC15 USB20_N5 USB20_P5 <71>
<52> PCIE_CTX_DRX_N9 PCIE_CRX_DTX_P9 EF5 PCIE9_TXN/UFS10_TXN USB2N_5 USB20_N5 <71> USB3.1 Type-A Port2 (MB)
WLAN <52> PCIE_CRX_DTX_P9 PCIE_CRX_DTX_N9 PCIE9_RXP/UFS10_RXP
EF6 ER5
<52> PCIE_CRX_DTX_N9 PCIE9_RXN/UFS10_RXN USB2P_4 ER6
PCIE3_CTX_DRX_P8 EH10 USB2N_4
<69> PCIE3_CTX_DRX_P8 PCIE3_CTX_DRX_N8 EH11 PCIE8_TXP ER18
<69> PCIE3_CTX_DRX_N8 PCIE3_CRX_DTX_P8 PCIE8_TXN USB2P_3
EF1 ET18
<69> PCIE3_CRX_DTX_P8 PCIE3_CRX_DTX_N8 EF3 PCIE8_RXP USB2N_3
<69> PCIE3_CRX_DTX_N8 PCIE8_RXN EH16 USB20_P2
B PCIE3_CTX_DRX_P7 EL10 USB2P_2 EK16 USB20_N2 USB20_P2 <43> TBT port0 B
<69> PCIE3_CTX_DRX_P7 PCIE3_CTX_DRX_N7 EL11 PCIE7_TXP USB2N_2 USB20_N2 <43> USB3.1 TBT Port (MB)
<69> PCIE3_CTX_DRX_N7 PCIE3_CRX_DTX_P7 PCIE7_TXN USB20_P1
EG4 EL16
<69> PCIE3_CRX_DTX_P7 PCIE3_CRX_DTX_N7 PCIE7_RXP USB2P_1 USB20_N1 USB20_P1 <71>
EG6 EN16 USB3.1 Type-A Port1 (MB)
<69> PCIE3_CRX_DTX_N7 PCIE7_RXN USB2N_1 USB20_N1 <71>
PCIE3_CTX_DRX_P6 EN10 FC25 SOC_GPP_E9 1 T248
SSD2 <69> PCIE3_CTX_DRX_P6 PCIE3_CTX_DRX_N6 PCIE6_TXP GPP_E9/USB_OC0#/ISH_GP4 @
EN11 DY51
<69> PCIE3_CTX_DRX_N6 PCIE3_CRX_DTX_P6 PCIE6_TXN GPP_A16/USB_OC3#/ISH_GP5
EJ5
<69> PCIE3_CRX_DTX_P6 PCIE3_CRX_DTX_N6 EJ6 PCIE6_RXP FA25 DEVSLP1 1 T249
<69> PCIE3_CRX_DTX_N6 PCIE6_RXN GPP_E5/DEVSLP1/SRCCLK_OE6# FC22 DEVSLP0 1 @ T250
PCIE3_CTX_DRX_P5 ER10 GPP_E4/DEVSLP0/SRCCLK_OE9# @
<69> PCIE3_CTX_DRX_P5 PCIE3_CTX_DRX_N5 ER11 PCIE5_TXP DY1 PCIE_RCOMPP RC168 1 2 100_0201_1%
<69> PCIE3_CTX_DRX_N5 PCIE3_CRX_DTX_P5 PCIE5_TXN MPHY_RCOMPP PCIE_RCOMPN
EJ1 DY3
<69> PCIE3_CRX_DTX_P5 PCIE3_CRX_DTX_N5 EJ3 PCIE5_RXP MPHY_RCOMPN
<69> PCIE3_CRX_DTX_N5 PCIE5_RXN EF18 USB2_VBUSSENSE RC169 1 2 10K_0201_1%
FB10 USB_VBUSSENSE EF16 USB2_ID RC170 1 2 10K_0201_1%
FA9 PCIE4_TXP/USB32_4_TXP USB_ID FB20 USB2_COMP RC171 1 2 113_0201_1%
EV16 PCIE4_TXN/USB32_4_TXN USB2_COMP
EY16 PCIE4_RXP/USB32_4_RXP DL8 1 T251
PCIE4_RXN/USB32_4_RXN UFS_RESET# @
USB3_CTX_DRX_P3 EW11
<73> USB3_CTX_DRX_P3 USB3_CTX_DRX_N3 EY11 PCIE3_TXP/USB32_3_TXP
USB3.1 Type-A <73> USB3_CTX_DRX_N3 USB3_CRX_DTX_P3 PCIE3_TXN/USB32_3_TXN
EW17
(SUB) <73> USB3_CRX_DTX_P3 USB3_CRX_DTX_N3 EY17 PCIE3_RXP/USB32_3_RXP
<73> USB3_CRX_DTX_N3 PCIE3_RXN/USB32_3_RXN
USB3_CTX_DRX_P2 FA12
<71> USB3_CTX_DRX_P2 USB3_CTX_DRX_N2 FC12 PCIE2_TXP/USB32_2_TXP
FA18
(MB JUSB2) <71> USB3_CRX_DTX_P2 USB3_CRX_DTX_N2 FC18 PCIE2_RXP/USB32_2_RXP
USB3_CTX_DRX_P1 EV12
<71> USB3_CTX_DRX_P1 USB3_CTX_DRX_N1 EY12 PCIE1_TXP/USB32_1_TXP
EV19
(MB JUSB1) <71> USB3_CRX_DTX_P1 USB3_CRX_DTX_N1 EY19 PCIE1_RXP/USB32_1_RXP
A A
ADL-P_BGA1744
@

ADL-P(8/14)PCIE,USB,SATA
1A
5 4 3 2 1
5 4 3 2 1
D D
UC1J
REV0.6
AD41 FC46 CNV_CTX_DRX_P1
CSI_D_DP_1/CSI_C_DP_2 CNV_WT_D1P CNV_CTX_DRX_P1 <52>
AB41 FA46 CNV_CTX_DRX_N1
CSI_D_DN_1/CSI_C_DN_2 CNV_WT_D1N CNV_CTX_DRX_N1 <52>
AG41 EV43 CNV_CTX_DRX_P0
CSI_D_DP_0/CSI_C_DP_3 CNV_WT_D0P CNV_CTX_DRX_P0 <52>
AF41 EY43 CNV_CTX_DRX_N0
CSI_D_DN_0/CSI_C_DN_3 CNV_WT_D0N CNV_CTX_DRX_N0 <52>
J41 EV47 CLK_CNV_CTX_DRX_P
CSI_D_CLK_P CNV_WT_CLKP CLK_CNV_CTX_DRX_P <52>
L41 EY47 CLK_CNV_CTX_DRX_N
CSI_D_CLK_N CNV_WT_CLKN CLK_CNV_CTX_DRX_N <52>
P44 EV40 CNV_CRX_DTX_P1
CSI_C_DP_1 CNV_WR_D1P CNV_CRX_DTX_N1 CNV_CRX_DTX_P1 <52>
M44 EY40
CSI_C_DN_1 CNV_WR_D1N CNV_CRX_DTX_P0 CNV_CRX_DTX_N1 <52>
T41 EW42
CSI_C_DP_0 CNV_WR_D0P CNV_CRX_DTX_N0 CNV_CRX_DTX_P0 <52>
P41 EY42
CSI_C_DN_0 CNV_WR_D0N CLK_CNV_CRX_DTX_P CNV_CRX_DTX_N0 <52> +1.8VALW _PRIM
J44 FA43 CLK_CNV_CRX_DTX_P <52>
K44 CSI_C_CLK_P CNV_WR_CLKP FC43 CLK_CNV_CRX_DTX_N
CSI_C_CLK_N CNV_WR_CLKN CLK_CNV_CRX_DTX_N <52>
W41 FC40 CNV_W T_RCOMP RC172 1 2 150_0201_1% CNV_BRI_CRX_DTX 20K_0201_5% 1 @ 2 RC173
AA41 CSI_B_DP_1 CNV_WT_RCOMP
C38 CSI_B_DN_1 EK33 CNV_BRI_CRX_DTX CNV_RGI_CRX_DTX 20K_0201_5% 1 @ 2 RC174
CSI_B_DP_0 GPP_F1/CNV_BRI_RSP/UART2_RXD CNV_BRI_CTX_DRX CNV_BRI_CRX_DTX <52>
A38 EH33 CNV_BRI_CTX_DRX <52>
G39 CSI_B_DN_0 GPP_F0/CNV_BRI_DT/UART2_RTS# ER31 CNV_RGI_CRX_DTX
CSI_B_CLK_P GPP_F3/CNV_RGI_RSP/UART2_CTS# CNV_RGI_CTX_DRX CNV_RGI_CRX_DTX <52>
C F39 EN31 CNV_RGI_CTX_DRX <52>
C
CSI_B_CLK_N GPP_F2/CNV_RGI_DT/UART2_TXD
C36 EF36 CLKREQ_CNV# +1.8VALW _PRIM
CSI_A_DP_1/CSI_B_DP_2 GPP_F5/MODEM_CLKREQ/CRF_XTAL_CLKREQ CLKREQ_CNV# <52> CNV_BRI_CTX_DRX
A36 EH36
G37 CSI_A_DN_1/CSI_B_DN_2 GPP_F6/CNV_PA_BLANKING ET31 CNV_RF_RESET# XTAL SEL
CSI_A_DP_0/CSI_B_DP_3 GPP_F4/CNV_RF_RESET# CNV_RF_RESET# <52> INTERNAL PD 20K
E37
F36 CSI_A_DN_0/CSI_B_DN_3 LOW = 38.4 MHZ (DEFAULT)
CSI_A_CLK_P HIGH = 24MHZ (25 MHZ WHEN XTAL FREQ DIVIDER NON ZERO)
1
G36
CSI_A_CLK_N RC175
RC176 1 2 CSI_RCOMP A55 100K_0201_5%
150_0201_1% B54 CSI_RCOMP_1
CSI_RCOMP_2
2
ET41 CNV_RGI_CTX_DRX
ER41 GPP_H22/IMGCLKOUT3
EN41 GPP_H21/IMGCLKOUT2 CNV_RGI_CTX_DRX
FA31 GPP_H20/IMGCLKOUT1 M.2 CNVI MODES
GPP_D4/IMGCLKOUT0/BK4/SBK4 LOW = Integrated CNVi enable.
HIGH = Integrated CNVi disable.
1
NO INTERNAL PU/PD
RC177
ADL-P_BGA1744
4.7K_0201_5%
@ @
2
B B
A A

ADL-P(9/14)CSI,CNVi
5 4 3 2 1
5 4 3 2 1
+VCC_CORE +VCC_CORE EMC CAPS-PLACE Stitching Cap.

0604 rename
UC1M < 5mm from SOC VCCIN
BA44
REV0.6
CF8
0.1uF *1
VCCCORE_1 VCCCORE_51
D
BB43
BB45 VCCCORE_2 VCCCORE_52
CF9
CG14 +VCC_CORE
100pF *1 D
BC44
BD43 VCCCORE_4 VCCCORE_54
CG4
CH1
15pF *1
BD45
BE44
VCCCORE_5
VCCCORE_6
VCCCORE_55
VCCCORE_56
CH3
CK11
3pF *1
3P_0201_25V8B
15P_0201_25V8J
100P_0201_50V8J
1 1 1 1
0.1U_0201_10V6K
BH43 VCCCORE_7 VCCCORE_57 CK12
EMI@ CC62
EMI@ CC63
EMI@ CC64
EMI@ CC65
BK43 VCCCORE_8 VCCCORE_58 CK4
BK44 VCCCORE_9 VCCCORE_59 CK6
BL45 VCCCORE_10 VCCCORE_60 CK8 2 2 2 2
BM44 VCCCORE_11 VCCCORE_61 CK9
BN11 VCCCORE_12 VCCCORE_62 CL1
BP14 VCCCORE_15 VCCCORE_65 CM11
BR11 VCCCORE_16 VCCCORE_66 CM12
BR12 VCCCORE_17 VCCCORE_67 CM4
BT14 VCCCORE_18 VCCCORE_68 CM6
VCCCORE_19 VCCCORE_69 626549_ADL_P_BEP_plus_TDK_Rev0p71
BT44 CM8
BU11 VCCCORE_20 VCCCORE_70 CM9
BU12 VCCCORE_21 VCCCORE_71 CN1
BV14 VCCCORE_24 VCCCORE_74 CP1 +1.05V_PROC
BV44 VCCCORE_25 VCCCORE_75 CP11
BW12 VCCCORE_26 VCCCORE_76 CP12
1
BY1 CP6
BY44 VCCCORE_30
VCCCORE_31
VCCCORE_80
VCCCORE_81
CP8 SVID DATA RC179
C CA1 CP9 100_0201_1% C
CA3 VCCCORE_32 VCCCORE_82 CR4
CB12 VCCCORE_33 VCCCORE_83
2
CC14 VCCCORE_34 CT3
VCCCORE_35 VCC_SENSE VCC_SENSE_VCCIN <97> SOC_SVID_DAT
CC3 CT1 SOC_SVID_DAT <97>
VCCCORE_36 VSS_SENSE VSS_SENSE_VCCIN <97>
CD11
CD12 VCCCORE_37 R9 SOC_SVID_DAT
CD6 VCCCORE_38 VIDSOUT U9 SOC_SVID_CLK +1.05VO_PROC_OUT
CD8 VCCCORE_39 VIDSCK W9 SOC_SVID_ALERT# +1.05V_PROC
CD9 VCCCORE_40 VIDALERT#
CE1 VCCCORE_41 AU14
VCCCORE_42 VCC1P05_PROC_OUT_3
1
CE14
CE3 VCCCORE_43
VCCCORE_44 VCCST_PWRGD_SX
DJ6 VCCSTPW RGOOD_TGSS
VCCSTPW RGOOD_TGSS <11>
SVID ALERT RC181
CE4 56_0201_1%
CF1 VCCCORE_45
CF11 VCCCORE_46
2
CF12 VCCCORE_47
CF3 VCCCORE_48 SOC_SVID_ALERT#
VCCCORE_49 SOC_SVID_ALERT# <97>
CF6
VCCCORE_50
+1.05V_PROC
ADL-P_BGA1744
@
SVID CLOCK
1
RC183
100_0201_1%
@
B B
2
SOC_SVID_CLK
SOC_SVID_CLK <97>
A A

ADL-P(10/14)Power, SVID
5 4 3 2 1
5 4 3 2 1
+1.2V_VDDQ UC1O +VCC_GT

REV0.6 0604 rename
AD61 CP44
AG61 VDD2_1 VCCGT_1 CR45
AN61 VDD2_2 VCCGT_2 CT44
AP41 VDD2_3 VCCGT_3 CU43
EMC CAPS-PLACE AP44 VDD2_4 VCCGT_4 CU45
VDD2_5 VCCGT_5
< 4mm from SOC VDDQ AR43
AR45 VDD2_6 VCCGT_6
CV4
CV44
VDD2_7 VCCGT_7
with each pair < 12mm Apart +1.2V_VDDQ +1.2V_VDDQ +1.2V_VDDQ AT44
AU43 VDD2_8 VCCGT_8
CW1
CW11
VDD2_9 VCCGT_9
15pF* 3 (EMI@) AU45
AV44 VDD2_10 VCCGT_10
CW12
CW3
3pF* 3 (EMI@) AY61 VDD2_11 VCCGT_11 CW6
3P_0201_25V8B
3P_0201_25V8B
3P_0201_25V8B
15P_0201_25V8J
15P_0201_25V8J
15P_0201_25V8J
BH61 VDD2_12 VCCGT_12 CW8
1 1 1 1 1 1 VDD2_13 VCCGT_13
BR61 CW9
EMI@ CC66
EMI@ CC67
EMI@ CC68
EMI@ CC69
EMI@ CC70
EMI@ CC71
CA61 VDD2_14 VCCGT_14 CY14
D CC44 VDD2_15 VCCGT_15 CY4 D
2 2 2 2 2 2 CD43 VDD2_16 VCCGT_16 CY44
CD61 VDD2_17 VCCGT_17 DA1
CE44 VDD2_18 VCCGT_18 DA3
CF43 VDD2_19 VCCGT_19 DA43
CF45 VDD2_20 VCCGT_20 DB45
CG44 VDD2_21 VCCGT_21 DC1
CH45 VDD2_22 VCCGT_22 DC11
627333_ADL_P_DDR4_RVP_TDK_Rev0p7 VDD2_23 VCCGT_23
CK61 DC12
CN61 VDD2_24 VCCGT_24 DC3
CW61 VDD2_25 VCCGT_25 DC4
DF61 VDD2_26 VCCGT_26 DC44
J61 VDD2_27 VCCGT_27 DC6
R61 VDD2_28 VCCGT_28 DC8
+1.05VO_PROC_OUT V61 VDD2_29 VCCGT_29 DC9
VDD2_30 VCCGT_30 DD1
AR14 VCCGT_31 DD14
AT12 VCC1P05_PROC_OUT_1
VCCGT_32 DD3
VCC1P05_PROC_OUT_2
VCCGT_33 DD43
T253 TP@ 1 CM44 VCCGT_34 DD45
+1.8V_PROC T254 TP@ 1 EA14 RSVD_TP_33 VCCGT_35 DE11
RSVD_TP_49 VCCGT_36 DE12
E61 VCCGT_37 DE4
G61 VCC1P8_PROC_8 VCCGT_38 DE6
H59 VCC1P8_PROC_9 VCCGT_39 DE8
AH44 VCC1P8_PROC_10 VCCGT_40 DE9
+1.8V_PROC for PCIE5x8 Use only , AJ45 VCC1P8_PROC_1 VCCGT_41 DF1
can connect PWR or GND(Intel spec) AK44 VCC1P8_PROC_2 VCCGT_42 DF14
AL45 VCC1P8_PROC_3 VCCGT_43 DF3
AM41 VCC1P8_PROC_4 VCCGT_44 DG4
AM44 VCC1P8_PROC_5 VCCGT_45
AN43 VCC1P8_PROC_6
VCC1P8_PROC_7
CV1
<97> VCC_SENSE_VCCIN_GT VCCGT_SENSE
CV3
<97> VSS_SENSE_VCCIN_GT VSSGT_SENSE
ADL-P_BGA1744
@
C C
627205_ADL_P_PDG_Rev1.2
+1.05VO_OUT_FET +1.05VO_OUT_FET +1.05V_PROC
+1.05VO_OUT_FET_JP1
JPC1
1
1 2
2 +1.05V_PROC RC185 1 @ 2 0_0402_5%
1U_0201_6.3V6M
Imax : 0.500 A JUMP_43X79 1

CC72
JUMP@
For Power consumption UC6
Measurement 1 +1.05V_PROC_R
2 2 VIN1 +1.05V_PROC
+5VALW VIN2 Imax : 0.500 A
CC73 7 6 +1.05V_PROC_R RC186 1 RS@ 2 0_0603_5%
0.1U_0201_16V6K VIN thermal VOUT
2 @ 1 3 CC74 1
VBIAS 0.1U_0201_10V6K
+1.05V_PROC_EN_LS 1 RS@ 2+1.05V_PROC_EN_LS_R 4 5
RC187 ON GND DAZ10@
2
1U_0201_6.3V6M
0_0201_5% 1
CC75
B EM5201V_DFN8_3X3 RC186 0_0402_5% B

SD028000080
@
2
I (Max) : 0.500 A(+1.05V_PROC)
RDS(Typ) : 3.5 mohm
V drop : 0.00175V
+1.05V_PROC Enable 1uF* 6

<58,66,89> SYSON
SYSON RC188 1 @ 2 0_0201_5% 10uF * 3
PM_SLP_S4# RC189 1 @ 2 0_0201_5%
uF * 2
<11> PM_SLP_S4#
SUSP# RC190 1 @ 2 0_0201_5%
Layout Follow 627205_ADL_P_PDG_Rev0p7
<11,38,58,69,78,85,89> SUSP#
PM_SLP_S3# RC191 1 RS@ 2 0_0201_5%
<11> PM_SLP_S3#
PVT
+1.2V_VDDQ +1.2V_VDDQ
+3VALW
+1.8V_PROC
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1
CC82
CC83
CC84
CC85
CC86
DC7
CC76
CC77
CC78
CC79
CC80
CC81
1 2
CC87 1 +1.05V_PROC_EN_LS @ @
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
47U_0603_6.3V6M
47U_0603_6.3V6M
3 2 2 2 2 2 2 2 2 2 2 2
1U_0201_10V6M
0.1U_0201_10V6K 1 1 1 1
1
@
CC88
CC89
CC90
CC91
CC92
CC93
5
UC7 2 LRB715FT1G_SOT323-3 @ @ @ @
VCCST_OVERRIDE_LS 2 @ @
G Vcc
<11> VCCST_OVERRIDE_LS
2
2
A 4 VCCST_STG_COM_EN 2 2 2 2
VCCIN_AUX_CORE_VID 1 Y
<11> VCCIN_AUX_CORE_VID B TOP side BOT side
A 74AUP1G32GW_TSSOP5 TOP side A
3
CC90 2_0402_1%
SD000005V00
1 @ 2
RC192 0_0201_5% +1.8V_PROC for PCIE5x8 Use only ,
can connect PWR or GND(Intel spec) 10/8

ADL-P(11/14)Power
1A
5 4 3 2 1
5 4 3 2 1
+1.8V_PRIM_MCP +1.8V_VCCA_CLKLDO
+3VALW TO +3V_PRIM @
L7 1 2
1354mA +1.8VALW_PRIM +1.8V_PRIM_MCP 4.7UH_UHP252012BF-4R7M_20%
+3VALW +3VALW_PRIM DVT
2
JPC2 I Max = 0.17A
1 2 RC256 1 RS@ 2 0_0805_5% RC195
1 2 RC196 1 2 0_0402_5%
JUMP_43X39 0_0402_5%
JUMP@ 1
1
CC95 +3VALW +3VALW_DSW
4.7U_0402_6.3V6M DVT 1
D 2 D
RC197 1 RS@ 2 0_0402_5% I Max = 0.202A CC94
47U_0603_6.3V6M
2
+VCCIN_AUX UC1N +1.8V_PRIM_MCP

REV0.6
EMC CAPS-PLACE AL20
VCCIN_AUX_1 VCCPRIM_1P8_1
DW20
AL32 DW22
< 5mm from SOC VCCIN_AUX AN20 VCCIN_AUX_2 VCCPRIM_1P8_2 DW27
AN22 VCCIN_AUX_3 VCCPRIM_1P8_3 DW30
+VCCIN_AUX AN30 VCCIN_AUX_4 VCCPRIM_1P8_4 DY21
AN32 VCCIN_AUX_5 VCCPRIM_1P8_5 DY23
AN37 VCCIN_AUX_6 VCCPRIM_1P8_6 DY26
VCCIN_AUX_7 VCCPRIM_1P8_7 Note: VCCPGPPR follow HDA interface
AP17 DY28
AP27 VCCIN_AUX_8 VCCPRIM_1P8_8 DY31
CC96
CC97
CC98
CC99
EMI@ CC100
EMI@ CC101
10P_0201_25V8
10P_0201_25V8
10P_0201_25V8
10P_0201_25V8
10P_0201_25V8
10P_0201_25V8
1
AP30 EB18
AP32 VCCIN_AUX_10 VCCPRIM_1P8_12 EB21
AP37 VCCIN_AUX_11 VCCPRIM_1P8_13 EB23
2
EMI@
EMI@
EMI@
EMI@
B3 EB28
D3 VCCIN_AUX_13 VCCPRIM_1P8_15 EC14
E1 VCCIN_AUX_14 VCCPRIM_1P8_16 EC16
F1 VCCIN_AUX_33 VCCPRIM_1P8_17 EC23
F3 VCCIN_AUX_36 VCCPRIM_1P8_18 EC26
G3 VCCIN_AUX_37 VCCPRIM_1P8_19 EE14
H4 VCCIN_AUX_38 VCCPRIM_1P8_20 EE28
J1 VCCIN_AUX_39 VCCPRIM_1P8_21 EG14
C J3 VCCIN_AUX_40 VCCPRIM_1P8_22 FB33 +3VALW_PRIM C
L1 VCCIN_AUX_41 VCCPRIM_1P8_23
L3 VCCIN_AUX_42 DV41
N3 VCCIN_AUX_43 VCCPRIM_3P3_1 DW40
VCCIN_AUX_44 VCCPRIM_3P3_2 EB33
DH45 VCCPRIM_3P3_3 EC31
DJ41 VCCIN_AUX_15 VCCPRIM_3P3_5 EC33
DJ44 VCCIN_AUX_16 VCCPRIM_3P3_6 EE31
DK40 VCCIN_AUX_17 VCCPRIM_3P3_7 +0.85VO_VCCLDOSTD
DK43 VCCIN_AUX_18 FB45
DK45 VCCIN_AUX_19 RSVD_24
+VCCIN_AUX_FIL DL44 VCCIN_AUX_20 FB52 +1.8V_VCCA_CLKLDO
DM1 VCCIN_AUX_21 VCCLDOSTD_0P85
+1.05VO_VNNBYPASS DM14 VCCIN_AUX_22 EJ14 +1.24VO_VCCDPHY
DM43 VCCIN_AUX_23 VCCA_CLKLDO_1P8_1 EM14
DP41 VCCIN_AUX_24 VCCA_CLKLDO_1P8_2
DP42 VCCIN_AUX_25 FB39
1 VCCIN_AUX_26 VCCDPHY_1P24
1
DR14
CC171
CC479
47U_0603_6.3V6M
10U_0402_6.3V6M
+1.05VO_EXTBYPASS DR40 VCCIN_AUX_27 BN43 1 TP@T255

VCCIN_AUX_28 RSVD_TP_28
1
DT41 AY11 1 TP@T256

100K_0201_5%
2 DU14 VCCIN_AUX_29 RSVD_TP_18 BP44 1 TP@T257

RC73
DU40 VCCIN_AUX_30 RSVD_TP_29 BL12 1 TP@T258

DV2 VCCIN_AUX_31 RSVD_TP_27 CN43 1 TP@T259
@ ED2 VCCIN_AUX_32 RSVD_TP_34 BJ11 1 TP@T260 +1.05VO_OUT_PCH
100K_0201_5%
VCCIN_AUX_34 RSVD_TP_24
1
EL2
VCCIN_AUX_35
TOP side 5/17 Follow TD team P1 EB36 +1.05VO_VCCDSW
RC71
VCCIN_AUX_FLTR VCCPRIM1P05_OUT_PCH_1 EC36

@ AH30 VCCPRIM1P05_OUT_PCH_3 EE41 +1.05VO_OUT_PCH
<95> VSS_SENSE_VCCIN_AUX VSSINAUX_SENSE VCCDSW_1P05 +1.24V_MIPI
AF30 V1 1 TP@T261
<95> VCC_SENSE_VCCIN_AUX
2
VCCINAUX_SENSE VCC_MIPILP EB38

EF21 VCCPRIM1P05_OUT_PCH_2 EE36 +RTCVCC
EH21 VCC_VNNEXT_1P05_1 VCCPRIM1P05_OUT_PCH_4 +3VALW_DSW
VCC_VNNEXT_1P05_2 EC38 +3VALW_PRIM
EE18 VCCRTC EB42
EE21 VCC_V1P05EXT_1P05_1 VCCPDSW_3P3 EE33
B VCC_V1P05EXT_1P05_2 VCCPGPPR +1.8V_PRIM_MCP B
DVT
<7,43> VCCIN_AUX_CORE_ALERT#_R RC200 1 RS@ 2 0_0201_5% VCCIN_AUX_CORE_ALERT# DT59 EB41
1 VNN_CTRL EK31 GPP_B2/VRALERT# VCCPRIM_3P3_4 DY41
T262 @ 1 V1.05P_CTRL EL28 GPP_F22/VNN_CTRL VCCPRIM_1P8_10 DY42 +1.05V_PROC
T263 @ GPP_F23/V1P05_CTRL VCCPRIM_1P8_11
VCCIN_AUX_CORE_VID0 EA60 EU1
<11,95> VCCIN_AUX_CORE_VID0 GPP_B0/CORE_VID0 VCC1P05_PROC_1
VCCIN_AUX_CORE_VID1 EA58 EU4 +1.05VO_OUT_FET
<11,95> VCCIN_AUX_CORE_VID1 GPP_B1/CORE_VID1 VCC1P05_PROC_2
EV3
VCC1P05_OUT_FET_1 EW1
VCC1P05_OUT_FET_2 EY1 +1.05VO_PROC_OUT
VCC1P05_OUT_FET_3
AM15
VCC_DISPIO
BJ12 1 TP@T264
RSVD_TP_25 BK14 1 TP@T265
RSVD_TP_26 BF14 1 TP@T266
RSVD_TP_21
ADL-P_BGA1744
@
RTC Battery +RTCBATT
MAX. 8000mil JRTC1

1
+RTCBATT 2 1
W=20mil 2
+1.8V_PRIM_MCP +3VALW_PRIM
+3VALW_DSW +1.05VO_VCCDSW +0.85VO_VCCLDOSTD +1.24VO_VCCDPHY +1.05V_PROC 1 2 3
+RTCVCC 4 GND
RC203 1K_0402_5% DC8 W=40mil
+CHGRTC 2 GND
2mA
0.1U_0201_10V6K
1 ACES_50271-0020N-001
1U_0201_10V6M
1 1 1 1 1 1
4.7U_0402_6.3V6M
CC103 CC104 CC107 1 1 1 3

1U_0201_6.3V6M
1U_0201_6.3V6M
CONN@
1U_0201_6.3V6M
@ CC102 1U_0201_6.3V6M 2.2U_0201_6.3V6M @ 1U_0201_6.3V6M
CC105
CC106
CC108
CC109
CC110
0.1U_0201_10V6K
1U_0201_10V6M
A
2 2 2 2
@
2 2 W=20mil
LRB715FT1G_SOT323-3 2 1 SP02000RO00 A
2 2 2
CC111
CC112
1 2
PLACE CAP CLOSEST POSSIBLE TO THE BGA

ADL-P(12/14)Power
1A
5 4 3 2 1
5 4 3 2 1
UC1R UC1S
UC1P UC1Q REV0.6 REV0.6
REV0.6 REV0.6 DC47 ED58 F56 M36
A3 AL15 BF58 CD58 DC54 VSS_295 VSS_369 ED6 F59 VSS_443 VSS_517 M47
D D
A10 VSS_7 VSS_74 AL17 BG1 VSS_149 VSS_222 CE51 DC57 VSS_296 VSS_370 ED60 F9 VSS_444 VSS_518 M57
A21 VSS_1 VSS_75 AL22 BG12 VSS_150 VSS_223 CE55 DC59 VSS_297 VSS_371 ED8 FA40 VSS_445 VSS_519 M59
A23 VSS_2 VSS_76 AL4 BG44 VSS_151 VSS_224 CF47 DE44 VSS_298 VSS_372 EE16 FA7 VSS_446 VSS_520 N1
A25 VSS_3 VSS_77 AL41 BG52 VSS_152 VSS_225 CF49 DE51 VSS_299 VSS_373 EE43 FB1 VSS_447 VSS_521 N4
A26 VSS_4 VSS_78 AL54 BG9 VSS_153 VSS_226 CF54 DE55 VSS_300 VSS_374 EE51 FB14 VSS_448 VSS_522 N40
A28 VSS_5 VSS_79 AM11 BH4 VSS_154 VSS_227 CG57 DF43 VSS_301 VSS_375 EF13 FB26 VSS_449 VSS_523 N41
A30 VSS_6 VSS_80 AM3 BH46 VSS_155 VSS_228 CG59 DF46 VSS_302 VSS_376 EF8 FB42 VSS_450 VSS_524 N48
A31 VSS_8 VSS_81 AM51 BH48 VSS_156 VSS_229 CH11 DF48 VSS_303 VSS_377 EH13 FB48 VSS_451 VSS_525 N54
A33 VSS_9 VSS_82 AM55 BH58 VSS_157 VSS_230 CH12 DF58 VSS_304 VSS_378 EH8 FB59 VSS_452 VSS_526 N9
A40 VSS_10 VSS_83 AM9 BJ51 VSS_158 VSS_231 CH54 DG11 VSS_305 VSS_379 EK21 FB61 VSS_453 VSS_527 P11
A47 VSS_11 VSS_84 AN17 BJ55 VSS_159 VSS_232 CH6 DG12 VSS_306 VSS_380 EK28 FC2 VSS_454 VSS_528 P16
AA11 VSS_14 VSS_87 AN48 BJ9 VSS_162 VSS_235 CJ14 DG6 VSS_309 VSS_383 EK51 FC58 VSS_457 VSS_531 P3
AA21 VSS_15 VSS_88 AN58 BL11 VSS_163 VSS_236 CJ4 DG8 VSS_310 VSS_384 EK56 FC60 VSS_458 VSS_532 P31
AA26 VSS_16 VSS_89 AP1 BL4 VSS_164 VSS_237 CJ44 DG9 VSS_311 VSS_385 EK58 G21 VSS_459 VSS_533 P35
AA31 VSS_17 VSS_90 AP15 BL54 VSS_165 VSS_238 CK1 DH4 VSS_312 VSS_386 EL13 G25 VSS_460 VSS_534 P47
AA35 VSS_18 VSS_91 AP20 BL9 VSS_166 VSS_239 CK3 DH54 VSS_313 VSS_387 EL4 G28 VSS_461 VSS_535 P51
AA40 VSS_19 VSS_92 AP22 BM1 VSS_167 VSS_240 CK43 DJ47 VSS_314 VSS_388 EL6 G31 VSS_462 VSS_536 P55
AA44 VSS_20 VSS_93 AP25 BM14 VSS_168 VSS_241 CK46 DJ57 VSS_315 VSS_389 EL8 G34 VSS_463 VSS_537 R12
AA57 VSS_21 VSS_94 AP35 BM47 VSS_169 VSS_242 CK48 DJ59 VSS_316 VSS_390 EN13 G42 VSS_464 VSS_538 R17
AA59 VSS_22 VSS_95 AP51 BM57 VSS_170 VSS_243 CK51 DK14 VSS_317 VSS_391 EN8 G43 VSS_465 VSS_539 R22
AB16 VSS_23 VSS_96 AP55 BM59 VSS_171 VSS_244 CK55 DK54 VSS_318 VSS_392 EP14 G50 VSS_466 VSS_540 R27
AB21 VSS_24 VSS_97 AP9 BN1 VSS_172 VSS_245 CK58 DL10 VSS_319 VSS_393 ER1 H1 VSS_467 VSS_541 R32
AB26 VSS_25 VSS_98 AR4 BN54 VSS_173 VSS_246 CM52 DL11 VSS_320 VSS_394 ER13 H13 VSS_468 VSS_542 R37
AB31 VSS_26 VSS_99 AR54 BN9 VSS_174 VSS_247 CN46 DL13 VSS_321 VSS_395 ER21 H16 VSS_469 VSS_543 R44
AB35 VSS_27 VSS_100 AT47 BP4 VSS_175 VSS_248 CN58 DM4 VSS_322 VSS_396 ER28 H18 VSS_470 VSS_544 R48
AB54 VSS_28 VSS_101 AT57 BP51 VSS_176 VSS_249 CP51 DM41 VSS_323 VSS_397 ER3 H34 VSS_471 VSS_545 R58
C AC4 VSS_29 VSS_102 AT59 BP55 VSS_177 VSS_250 CP55 DM46 VSS_324 VSS_398 ER36 H37 VSS_472 VSS_546 T1 C
AC40 VSS_30 VSS_103 AT6 BR43 VSS_178 VSS_251 CR43 DM48 VSS_325 VSS_399 ER43 H52 VSS_473 VSS_547 T11
AC44 VSS_31 VSS_104 AT8 BR46 VSS_179 VSS_252 CR47 DM51 VSS_326 VSS_400 ER51 H58 VSS_474 VSS_548 T16
AC51 VSS_32 VSS_105 AU54 BR48 VSS_180 VSS_253 CR49 DM55 VSS_327 VSS_401 ER61 H6 VSS_475 VSS_549 T21
AC55 VSS_33 VSS_106 AV11 BR58 VSS_181 VSS_254 CR54 DM58 VSS_328 VSS_402 ER8 H8 VSS_476 VSS_550 T26
AC6 VSS_34 VSS_107 AV4 BR6 VSS_182 VSS_255 CT11 DM6 VSS_329 VSS_403 EU11 H9 VSS_477 VSS_551 T3
AC8 VSS_35 VSS_108 AV9 BR8 VSS_183 VSS_256 CT57 DM61 VSS_330 VSS_404 EU56 J11 VSS_478 VSS_552 T31
AD21 VSS_36 VSS_109 AW1 BR9 VSS_184 VSS_257 CT59 DN13 VSS_331 VSS_405 EU58 J14 VSS_479 VSS_553 T35
AD26 VSS_37 VSS_110 AW14 BT4 VSS_185 VSS_258 CT6 DN40 VSS_332 VSS_406 EU8 J17 VSS_480 VSS_554 T40
AD31 VSS_38 VSS_111 AW51 BT51 VSS_186 VSS_259 CT8 DN8 VSS_333 VSS_407 EV14 J20 VSS_481 VSS_555 T52
AD35 VSS_39 VSS_112 AW55 BT55 VSS_187 VSS_260 CT9 DP46 VSS_334 VSS_408 EV20 J21 VSS_482 VSS_556 U16
AD46 VSS_40 VSS_113 AY1 BU54 VSS_188 VSS_261 CU4 DP49 VSS_335 VSS_409 EV26 J25 VSS_483 VSS_557 U21
AD48 VSS_41 VSS_114 AY43 BU9 VSS_189 VSS_262 CU54 DT13 VSS_336 VSS_410 EV33 J28 VSS_484 VSS_558 U26
AD58 VSS_42 VSS_115 AY46 BV1 VSS_190 VSS_263 CV14 DT52 VSS_337 VSS_411 EV39 J31 VSS_485 VSS_559 U31
AE12 VSS_43 VSS_116 AY48 BV47 VSS_191 VSS_264 CW43 DT8 VSS_338 VSS_412 EV4 J36 VSS_486 VSS_560 U35
AE17 VSS_44 VSS_117 AY51 BV57 VSS_192 VSS_265 CW46 DV13 VSS_339 VSS_413 EV45 J39 VSS_487 VSS_561 U44
AE22 VSS_45 VSS_118 AY55 BV59 VSS_193 VSS_266 CW48 DV4 VSS_340 VSS_414 EV52 J47 VSS_488 VSS_562 U46
AE27 VSS_46 VSS_119 AY58 BW4 VSS_194 VSS_267 CW51 DV44 VSS_341 VSS_415 EV59 J48 VSS_489 VSS_563 V3
AE32 VSS_47 VSS_120 AY9 BW54 VSS_195 VSS_268 CW55 DV49 VSS_342 VSS_416 EW61 J51 VSS_490 VSS_564 V40
AE37 VSS_48 VSS_121 B34 BW9 VSS_196 VSS_269 CW58 DV56 VSS_344 VSS_417 EY14 J55 VSS_491 VSS_565 V41
AE40 VSS_49 VSS_122 B4 BY3 VSS_197 VSS_270 CY51 DV58 VSS_345 VSS_418 EY20 K4 VSS_492 VSS_566 V51
AE44 VSS_50 VSS_123 B43 C1 VSS_198 VSS_271 CY55 DV6 VSS_346 VSS_419 EY26 L12 VSS_493 VSS_567 V55
AE52 VSS_51 VSS_124 B50 C21 VSS_199 VSS_272 D11 DV8 VSS_347 VSS_420 EY3 L13 VSS_494 VSS_568 V58
AE9 VSS_52 VSS_125 B58 C25 VSS_200 VSS_273 D14 DW14 VSS_348 VSS_421 EY33 L15 VSS_495 VSS_569 W1
AF4 VSS_53 VSS_126 B61 C28 VSS_201 VSS_274 D17 DW25 VSS_349 VSS_422 EY39 L17 VSS_496 VSS_570 W11
AF46 VSS_54 VSS_127 BA4 C31 VSS_202 VSS_275 D20 DW35 VSS_350 VSS_423 EY4 L18 VSS_497 VSS_571 W16
AG1 VSS_55 VSS_128 BB12 C34 VSS_203 VSS_276 D21 DY13 VSS_351 VSS_424 EY45 L20 VSS_498 VSS_572 W21
B AG58 VSS_58 VSS_132 BB8 C9 VSS_206 VSS_279 D31 DY38 VSS_354 VSS_427 EY58 L27 VSS_501 VSS_575 W35 B
AH9 VSS_59 VSS_133 BB9 CA14 VSS_207 VSS_280 D4 DY52 VSS_355 VSS_428 EY59 L30 VSS_502 VSS_576 W44
AJ3 VSS_60 VSS_134 BC14 CA43 VSS_208 VSS_281 D53 DY8 VSS_356 VSS_429 EY6 L33 VSS_503 VSS_577 Y12
AJ41 VSS_61 VSS_135 BC47 CA46 VSS_209 VSS_282 D56 E43 VSS_357 VSS_430 EY9 L35 VSS_504 VSS_578 Y17
AJ47 VSS_62 VSS_136 BC57 CA48 VSS_210 VSS_283 D58 E50 VSS_358 VSS_431 F21 L36 VSS_505 VSS_579 Y22
AJ49 VSS_63 VSS_137 BC59 CA51 VSS_211 VSS_284 D59 EB13 VSS_359 VSS_432 F23 L38 VSS_506 VSS_580 Y27
AJ54 VSS_64 VSS_138 BD4 CA55 VSS_212 VSS_285 D9 EB26 VSS_360 VSS_433 F26 L40 VSS_507 VSS_581 Y32
AK20 VSS_65 VSS_139 BD54 CA58 VSS_213 VSS_286 DA11 EB31 VSS_361 VSS_434 F28 L54 VSS_508 VSS_582 Y37
AK25 VSS_66 VSS_140 BE1 CB4 VSS_214 VSS_287 DA12 EB8 VSS_362 VSS_435 F30 L9 VSS_509 VSS_583 Y4
AK30 VSS_67 VSS_141 BE12 CB6 VSS_215 VSS_288 DA6 EC21 VSS_363 VSS_436 F33 M16 VSS_510 VSS_584 Y45
AK37 VSS_68 VSS_143 BE51 CB8 VSS_216 VSS_289 DA8 EC28 VSS_364 VSS_437 F4 M21 VSS_511 VSS_585 Y47
AK4 VSS_69 VSS_144 BE55 CB9 VSS_217 VSS_290 DA9 ED13 VSS_365 VSS_438 F40 M26 VSS_512 VSS_586 Y49
AK57 VSS_70 VSS_145 BE9 CC1 VSS_218 VSS_291 DB14 ED4 VSS_366 VSS_439 F46 M31 VSS_513 VSS_587 Y54
AK59 VSS_71 VSS_146 BF46 CC52 VSS_219 VSS_292 DB4 ED56 VSS_367 VSS_440 F47 M32 VSS_514 VSS_588
AK9 VSS_72 VSS_147 BF48 CD46 VSS_220 VSS_293 DB54 VSS_368 VSS_441 F52 1 M34 VSS_515
VSS_73 VSS_148 VSS_221 VSS_294 VSS_442 T267 TP@ VSS_516
ADL-P_BGA1744 ADL-P_BGA1744 ADL-P_BGA1744 ADL-P_BGA1744

@ @ @ @
follow RVP
A A

ADL-P(13/14)GND
5 4 3 2 1
5 4 3 2 1
+VCC_CFG_PU_OUT UC1U
REV0.6
RC210 1 @ 2 10K_0201_5% CFG0 CFG15 AF37 A58 1
CFG_15 RSVD_TP_1 TP@ T270
RC204 1 @ 2 1K_0201_5% CFG1 CFG14 AH35 B59 1
RC205 1 2 1K_0201_5% CFG2 CFG13 AF35 D61 1 TP@ T269
RC206 1 @ 2 1K_0201_5% CFG3 CFG12 AH37 CFG_13 RSVD_TP_37
CFG11 AH25 CFG_12 AF40 1
CFG10 AF20 AH40 1
CFG9 AH22
CFG8 AK17 CFG_9 DG44 1
RC207 1 @ 2 10K_0201_5% CFG4 CFG7 AJ15 DH43 1 TP@ T274
RC208 1 @ 2 10K_0201_5% CFG5 CFG6 AH17 CFG_7 RSVD_TP_40
RC209 1 @ 2 10K_0201_5% CFG6 CFG5 AG15 CFG_6 BB11
RC211 1 @ 2 10K_0201_5% CFG7 CFG4 AD11 CFG_5 VSS_129 BE11
CFG3 AC12 CFG_4 VSS_142
D CFG_3 D
CFG2 AA12 FB3
CFG1 AD16 CFG_2 RSVD_23 FC6
CFG0 AA16 CFG_1 RSVD_25
CFG_0 DY5 1
CFG_RCOMP RSVD_TP_47 TP@ T275
RC212 1 @ 2 10K_0201_5% CFG8 F8 DY6 1 TP@ T276
RC213 1 2 1K_0201_5% CFG9 CFG_RCOMP RSVD_TP_48
RC214 1 2 1K_0201_5% CFG10 T277 TP@ 1 AF22 FC9
CFG_17 RSVD_27
1
RC215 1 @ 2 1K_0201_5% CFG11 1 AF17 FC7
T323 TP@ CFG_16 RSVD_26
RC216
BPM#3 AF12 FB4 1 TP@ T278
BPM#2 AH12 BPM#_3 RSVD_TP_54 FC4 1
49.9_0201_1%
BPM#_2 RSVD_TP_56 TP@ T279
BPM#1 AK12
2
BPM#0 AL12 BPM#_1 DT61 ADR_COMPLETE
RC217 1 @ 2 10K_0201_5% CFG12 BPM#_0 GPP_B18/ADR_COMPLETE
RC218 1 @ 2 10K_0201_5% CFG13 AK27 R4
RC219 1 2 10K_0201_5% CFG14 AH27 RSVD_5 RSVD_28 AC9 1
RSVD_3 RSVD_TP_3 TP@ T280 ADR_COMPLETE
RC220 1 2 10K_0201_5% CFG15
AY12 DL1
1 AT9 VSS RSVD_11 DL3
T281 TP@ RSVD_TP_16 RSVD_12
T282 TP@
1 AT11
1 AP11 RSVD_TP_15 EU61
20K_0201_5%
T283 TP@ RSVD_TP_13 RSVD_22
1
T284 TP@
1 AP12 EC18
1 BA14 RSVD_TP_14 RSVD_14
RC221
+VCC_CFG_PU_OUT T285 TP@ RSVD_TP_20 DV46 @
1 CT12 VSS_343 DV42 1
T286 TP@ RSVD_TP_36 TP_4 TP@ T287
T288 TP@
1 CR14 DT47 1 TP@ T289
2
1 EK18 RSVD_TP_35 TP_1 CB11 1
T290 TP@ RSVD_TP_52 RSVD_TP_31 TP@ T291
RC222 1 2 10K_0201_5% BPM#0 1 EH18 BW11 1
T292 TP@ RSVD_TP_51 RSVD_TP_30 TP@ T293
RC223 1 2 10K_0201_5% BPM#1
RC224 1 2 10K_0201_5% BPM#2 T294 TP@
1 AL25 AK35 1 TP@ T295
RC225 1 2 10K_0201_5% BPM#3 1 AN25 RSVD_TP_6 SKTOCC#
T296 TP@ RSVD_TP_10 AN27 1 TP@ T297
RSVD_TP_11 AL27 1
RSVD_TP_7 TP@ T298
AL35 1 TP@ T299
C RSVD_TP_8 AN35 1 C
RSVD_TP_12 TP@ T300
EL51 1
GPP_T3 TP@ T301
EN51 1
GPP_T2 TP@ T302
RC226 1 @ 2 1K_0201_5% CFG15

1 2 ADL-P_BGA1744
RC227 @ 1K_0201_5% CFG14
RC228 1 @ 2 1K_0201_5% CFG13 Signal: CFG12, 13 PD 1K follow RVP @
RC229 1 @ 2 1K_0201_5% CFG12 633909_ADL_P_DDR4_SODIMM_1DPC_RVP_TDK_Rev0p7
RC230 1 @ 2 1K_0201_5% CFG11
RC231 1 @ 2 1K_0201_5% CFG10
RC232 1 @ 2 1K_0201_5% CFG8
RC233 1 @ 2 1K_0201_5% CFG7 UC1T

RC234 1 @ 2 1K_0201_5% CFG6 REV0.6
RC235 1 @ 2 1K_0201_5% CFG5 EF48 BF43 1
RSVD_17 RSVD_TP_22 TP@ T303
RC236 1 2 1K_0201_5% CFG4 AA9 1
RSVD_TP_2 TP@ T304
RC237 1 @ 2 1K_0201_5% CFG3 EF51 DJ9 1 TP@ T305 +VCC_CFG_PU_OUT
RC238 1 @ 2 1K_0201_5% CFG1 RSVD_18 RSVD_TP_43
RC239 1 @ 2 1K_0201_5% CFG0 T306 TP@
1 FB58 DJ12 1 TP@ T307
1 EY61 RSVD_TP_55 RSVD_TP_42 AV12
T308 TP@ RSVD_TP_53 VCC_CFG_PU_OUT CH43 1
RSVD_TP_32 TP@ T309
EH48 DH14 1 TP@ T310
EF53 RSVD_21 RSVD_TP_39 DW32 1
Signal: CFG4 (Ref : MoW WW37) RSVD_19 RSVD_TP_44 TP@ T311
The CFG [4] pin is made Reserved. Pull -Down termination BH14 1 TP@ T312
1 DJ11 RSVD_TP_23 DW37 1
recommendation is added wherever applicable. T313 TP@ RSVD_TP_41 RSVD_TP_45 TP@ T314
AL37 1
RSVD_TP_9 TP@ T315
T316 TP@
1 EB16
1 DY18 RSVD_TP_50
T317 TP@ RSVD_TP_46
ADL-P_BGA1744
B @ B
A A

ADL-P(14/14)RSVD,CFG
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

Reserve for SOC/PCH/FCH
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

5 4 3 2 1
5 4 3 2 1
CHANNEL-A ( Interleaved Memory ) <8> DDR_A_D[0..15] DDR_A_CLK0 137

JDIMM1A
REVERSE 8 DDR_A_D62
> BOT : Reverse type (4mm) <8>
<8>
DDR_A_D[16..31]
DDR_A_D[32..47]
<8>
<8>
<8>
<8>
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1
139
138
140
CK0(T)
CK0#(C)
CK1(T)
CK1#(C)
DQ0
DQ1
DQ2
DQ3
7
20
21
4
DDR_A_D60
DDR_A_D58
DDR_A_D57
DDR_A_D61
> Non-ECC SO-DIMM DDR_A_CKE0 109 DQ4 3 DDR_A_D63

<8> DDR_A_D[48..63] <8> DDR_A_CKE0 DDR_A_CKE1 CKE0 DQ5 DDR_A_D59
110 16
<8> DDR_A_CKE1 CKE1 DQ6 17 DDR_A_D56
DDR_A_CS#0 149 DQ7 13 DDR_A_DQS7
<8> DDR_A_CS#0 DDR_A_CS#1 157 S0# DQS0(T) 11 DDR_A_DQS#7 DDR_A_DQS7 <8>
<8> DDR_A_CS#1 S1# DQS0#(C) DDR_A_DQS#7 <8>
D
162 D
165 S2#/C0 28 DDR_A_D52
S3#/C1 DQ8 29 DDR_A_D55
DDR_A_ODT0 155 DQ9 41 DDR_A_D51
<8> DDR_A_ODT0 DDR_A_ODT1 161 ODT0 DQ10 42 DDR_A_D48
<8> DDR_A_ODT1 ODT1 DQ11 DDR_A_D53
24
JDIMM1B DDR_A_BG0 115 DQ12 25 DDR_A_D54
REVERSE <8> DDR_A_BG0 DDR_A_BG1 113 BG0 DQ13 38 DDR_A_D50
111 141 <8> DDR_A_BG1 DDR_A_BA0 150 BG1 DQ14 37 DDR_A_D49
+1.2V_VDDQ 112 VDD1 VDD11 142 +1.2V_VDDQ <8> DDR_A_BA0 DDR_A_BA1 145 BA0 DQ15 34 DDR_A_DQS6
VDD2 VDD12 <8> DDR_A_BA1 BA1 DQS1(T) DDR_A_DQS#6 DDR_A_DQS6 <8>
117 147 32
118 VDD3 VDD13 148 DDR_A_MA0 144 DQS1#(C) DDR_A_DQS#6 <8>
123 VDD4 VDD14 153 <8> DDR_A_MA0 DDR_A_MA1 133 A0 50 DDR_A_D44
VDD5 VDD15 <8> DDR_A_MA1 DDR_A_MA2 A1 DQ16 DDR_A_D45
124 154 132 49
129 159 131 62
130 160 128 63
135 VDD8 VDD18 163 <8> DDR_A_MA4 DDR_A_MA5 126 A4 DQ19 46 DDR_A_D46
+3VS 136 VDD9 VDD19 <8> DDR_A_MA5 DDR_A_MA6 127 A5 DQ20 45 DDR_A_D47
VDD10 <8> DDR_A_MA6 DDR_A_MA7 A6 DQ21 DDR_A_D42
122 58
<8> DDR_A_MA7 DDR_A_MA8 A7 DQ22 DDR_A_D41
255 258 125 59
VDDSPD VTT +0.6VS_VTT <8> DDR_A_MA8 DDR_A_MA9 121 A8 DQ23 55 DDR_A_DQS5
<8> DDR_A_MA9 DDR_A_MA10 A9 DQS2(T) DDR_A_DQS#5 DDR_A_DQS5 <8>
0.1U_0201_10V6K
164 257 146 53
2.2U_0402_6.3V6M
+0.6V_DDRA_VREFCA VREFCA VPP1 259 +2.5V <8> DDR_A_MA10 DDR_A_MA11 120 A10_AP DQS2#(C) DDR_A_DQS#5 <8>
2 2 VPP2 <8> DDR_A_MA11 A11
DDR_A_MA12 DDR_A_D39
CD1
119 70
<8> DDR_A_MA12 DDR_A_MA13 A12 DQ24 DDR_A_D36
CD2
1 99 158 71
VSS VSS <8> DDR_A_MA13 DDR_A_MA14 A13 DQ25 DDR_A_D35
2 102 151 83
1 1 VSS VSS <8> DDR_A_MA14 DDR_A_MA15 A14_WE# DQ26 DDR_A_D34
5 103 156 84
SPD ADDRESS FOR CHANNEL A : 6 VSS
VSS
VSS
VSS
106 <8>
<8>
DDR_A_MA15
DDR_A_MA16
DDR_A_MA16 152 A15_CAS#
A16_RAS#
DQ27
DQ28
66 DDR_A_D37
DDR_A_D38
9 107 67
WRITE ADDRESS: 0XA0 PLACE NEAR TO PIN
10
14
VSS
VSS
VSS
VSS
167
168
<8> DDR_A_ACT#
DDR_A_ACT# 114
ACT#
DQ29
DQ30
79
80
DDR_A_D33
DDR_A_D32
READ ADDRESS: 0XA1 15
18
VSS
VSS
VSS
VSS
171
172 <8> DDR_A_PAR
DDR_A_PAR
DDR_A_ALERT#
143
116 PARITY
DQ31
DQS3(T)
76
74
DDR_A_DQS4
DDR_A_DQS#4 DDR_A_DQS4 <8>
SA0 = 0; SA1 = 0; SA2 = 0. 19
22
VSS
VSS
VSS
VSS
175
176 +1.2V_VDDQ RD7 2 <8>1 DDR_A_ALERT#
240_0402_1% DDR_A_EVENT#
DDR_DRAMRST#_R
134
108
ALERT#
EVENT#
DQS3#(C)
174 DDR_A_D12
DDR_A_DQS#4 <8>
C
DDR4 POR OPERATING SPEED: 1867 MT/S 23
26
VSS
VSS
VSS
VSS
180
181
<8,24> DDR_DRAMRST#_R RESET# DQ32
DQ33
173
187
DDR_A_D15
DDR_A_D11 C
STRETCH GOAL IS 2133 MT/S 27

30
VSS
VSS
VSS
VSS
184
185 <9,24> SOC_SMBDATA
254
253 SDA
DQ34
DQ35
186
170
DDR_A_D9
DDR_A_D14
VSS VSS <9,24> SOC_SMBCLK SCL DQ36 DDR_A_D13
31 188 169
35 VSS VSS 189 166 DQ37 183 DDR_A_D10
36 VSS VSS 192 260 SA2 DQ38 182 DDR_A_D8
39 VSS VSS 193 256 SA1 DQ39 179 DDR_A_DQS1
Decopling Cap._Channel A 40
43
VSS
VSS
VSS
VSS
VSS
VSS
196
197
SA0 DQS4(T)
DQS4#(C)
177 DDR_A_DQS#1 DDR_A_DQS1
DDR_A_DQS#1
<8>
<8>
44 201 92 195 DDR_A_D6
47 VSS VSS 202 91 CB0_NC DQ40 194 DDR_A_D5
Layout Note: Layout Note: VSS VSS CB2_NC DQ42 DDR_A_D2
51 206 105 208
Place near JDIMM1B.257,259 Place near JDIMM1B.258 52 VSS VSS 209 88 CB3_NC DQ43 191 DDR_A_D4
56 VSS VSS 210
For ECC DIMM 87 CB4_NC DQ44 190 DDR_A_D7
57 VSS VSS 213 +1.2V_VDDQ 100 CB5_NC DQ45 203 DDR_A_D3
61 VSS VSS 217 RD30 2 1 240_0402_1% 97 CB7_NC DQ47 200 DDR_A_DQS0
+2.5V +0.6VS_VTT VSS VSS DQS8(T) DQS5(T) DDR_A_DQS#0 DDR_A_DQS0 <8>
10uF *1 10uF *1+1uF *2 64 218 RD31 2 1 240_0402_1% 95 198
VSS VSS DQS8#(C) DQS5#(C) DDR_A_DQS#0 <8>
65 222
1uF *1 68 VSS VSS 223 Follow ORB 216 DDR_A_D31
69 VSS VSS 226 12 DQ48 215 DDR_A_D28
VSS VSS +1.2V_VDDQ DM0#/DBI0# DQ49 DDR_A_D27
10U_0402_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 72 227 33 228
73 VSS VSS 230 54 DM1#/DBI1# DQ50 229 DDR_A_D26
VSS VSS DM2#/DBI2# DQ51
CD9
CD11
CD12
CD14
CD15
77 231 75 211 DDR_A_D30

2 2 @ 2 2 2 81 VSS VSS 235 199 DM4#/DBI4# DQ53 224 DDR_A_D25
85 VSS VSS 239 DDR_DRAMRST#_R 241 DM6#/DBI6# DQ55 221 DDR_A_DQS3
VSS VSS DM7#/DBI7# DQS6(T) DDR_A_DQS#3 DDR_A_DQS3 <8>
86 243 96 219
VSS VSS DM8#/DBI8# DQS6#(C) DDR_A_DQS#3 <8>
89 244
90 VSS VSS 247
VSS VSS 2
93 248 XESD@
94 VSS VSS 251 CD10 237 DDR_A_D20
98 VSS VSS 252 DQ56 236 DDR_A_D21
VSS VSS 33P_0201_50V8J DQ57
B 1 249 DDR_A_D19 B
262 261 DQ58 250 DDR_A_D17
GND GND DQ59 232 DDR_A_D23
20200302 DQ60 233 DDR_A_D22
LOTES_ADDR0206-P001A - CD10 change to unpop for ESD DQ61 245 DDR_A_D16
Layout Note: DQ62 DDR_A_D18
246
PLACE THE CAP near JDIMM1B. 164 CONN@
PLACE NEAR TO SODIMM DQ63 242 DDR_A_DQS2
DQS7(T) DDR_A_DQS#2 DDR_A_DQS2 <8>
240
Part Number: SP07001HW00 DQS7#(C) DDR_A_DQS#2 <8>
Part Value: S SOCKET LOTES ADDR0205-P001A DDR4 STD +1.2V_VDDQ
+0.6V_DDRA_VREFCA
2.2uF *1
LOTES_ADDR0206-P001A
0.1uF *1
CONN@
+1.2V_VDDQ I Max = 3.44A
2 2 2 channel --> 3.44 / 2 = 1.72A
CD70 @ CD13
0.1U_0201_10V6K 2.2U_0201_6.3V6M
1 1
DIMM Side CPU Side
@EMI@
@EMI@
@EMI@
@EMI@
ESD@
ESD@
ESD@
ESD@
ESD@
ESD@
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
2 2 2 2 2 2 2 2 2 2
2
RD10 +0.6V_DDRA_VREFCA +0.6V_A_VREFCA
1K_0402_1%
1 1 1 1 1 1 1 1 1 1
CD5
CD6
CD7
CD8
CD73
CD74
CD75
CD76
CD77
CD78
Layout Note: VREF traces should be at least 20 mils

1 RD11 2
Place near JDIMM2 2_0402_1% wide with 20 mils spacing to other
5/25
Follow Intel RVP ESD suggest 1 signals
2
CD3
follow RVP 1p0 RD12 0.022U_0402_16V7K
2
10uF*8 1K_0402_1%
1uF*8
2
A +1.2V_VDDQ +1.2V_VDDQ A
1
RD13
24.9_0402_1%
1
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD26
CD27
CD28
CD29
CD30
CD31
CD32
CD71
CD72
CD35
CD36
CD37
CD38
CD39
CD40
CD41
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DDRIV_CHA: DIMM0
1A
5 4 3 2 1
5 4 3 2 1
CHANNEL-B ( Interleaved Memory ) <8>
<8>
DDR_B_D[0..15]
DDR_B_D[16..31]
> BOT : STD type (4mm) <8>
<8>
DDR_B_D[32..47]
DDR_B_D[48..63] DDR_B_CLK0 137

JDIMM2A
STD 8 DDR_B_D47
> Non-ECC SO-DIMM

<8> DDR_B_CLK0 DDR_B_CLK#0 CK0(T) DQ0 DDR_B_D44
JDIMM2B 139 7
STD <8> DDR_B_CLK#0 DDR_B_CLK1 138 CK0#(C) DQ1 20 DDR_B_D41
<8> DDR_B_CLK1 DDR_B_CLK#1 CK1(T) DQ2 DDR_B_D40
111 141 140 21
+1.2V_VDDQ 112 VDD1 VDD11 142 +1.2V_VDDQ <8> DDR_B_CLK#1 CK1#(C) DQ3 4 DDR_B_D46
117 VDD2 VDD12 147 DDR_B_CKE0 109 DQ4 3 DDR_B_D45
VDD3 VDD13 <8> DDR_B_CKE0 DDR_B_CKE1 CKE0 DQ5 DDR_B_D43
118 148 110 16
123 VDD4 VDD14 153 <8> DDR_B_CKE1 CKE1 DQ6 17 DDR_B_D42
124 VDD5 VDD15 154 DDR_B_CS#0 149 DQ7 13 DDR_B_DQS5
D VDD6 VDD16 <8> DDR_B_CS#0 S0# DQS0(T) DDR_B_DQS5 <8> D
129 159 DDR_B_CS#1 157 11 DDR_B_DQS#5
130 VDD7 VDD17 160 <8> DDR_B_CS#1 162 S1# DQS0#(C) DDR_B_DQS#5 <8>
135 VDD8 VDD18 163 165 S2#/C0 28 DDR_B_D36
+3VS 136 VDD9 VDD19 S3#/C1 DQ8 29 DDR_B_D39
VDD10 DDR_B_ODT0 155 DQ9 41 DDR_B_D32
255 258 <8> DDR_B_ODT0 DDR_B_ODT1 161 ODT0 DQ10 42 DDR_B_D35
VDDSPD VTT +0.6VS_VTT <8> DDR_B_ODT1 ODT1 DQ11 24 DDR_B_D38
DDR_B_BG0 DQ12 DDR_B_D37
0.1U_0201_10V6K
164 257 115 25
2.2U_0402_6.3V6M
+0.6V_DDRB_VREFCA VREFCA VPP1 259 +2.5V <8> DDR_B_BG0 DDR_B_BG1 113 BG0 DQ13 38 DDR_B_D34
2 2 VPP2 <8> DDR_B_BG1 BG1 DQ14
CD33
DDR_B_BA0 150 37 DDR_B_D33
<8> DDR_B_BA0 DDR_B_BA1 BA0 DQ15 DDR_B_DQS4
CD34
1 99 145 34
2 VSS VSS 102 <8> DDR_B_BA1 BA1 DQS1(T) 32 DDR_B_DQS#4 DDR_B_DQS4 <8>
1 1 VSS VSS DDR_B_MA0 DQS1#(C) DDR_B_DQS#4 <8>
5 103 144
VSS VSS <8> DDR_B_MA0 DDR_B_MA1 A0 DDR_B_D63
6 106 133 50
VSS VSS <8> DDR_B_MA1 DDR_B_MA2 A1 DQ16 DDR_B_D56
9 107 132 49
10 VSS VSS 167 <8> DDR_B_MA2 DDR_B_MA3 131 A2 DQ17 62 DDR_B_D61
<8> DDR_B_MA3
PLACE NEAR TO PIN 14 VSS
VSS
VSS
VSS
168
<8> DDR_B_MA4
DDR_B_MA4 128 A3
A4
DQ18
DQ19
63 DDR_B_D58
15 171 DDR_B_MA5 126 46 DDR_B_D60
18 172 127 45
19 175 122 58
22 VSS VSS 176 <8> DDR_B_MA7 DDR_B_MA8 125 A7 DQ22 59 DDR_B_D59
SPD ADDRESS FOR CHANNEL B : 23 VSS
VSS
VSS
VSS
180 <8>
<8>
DDR_B_MA8
DDR_B_MA9
DDR_B_MA9
DDR_B_MA10
121 A8
A9
DQ23
DQS2(T)
55 DDR_B_DQS7
DDR_B_DQS#7 DDR_B_DQS7 <8>
26 181 146 53
WRITE ADDRESS: 0XA4 27
30
VSS
VSS
VSS
VSS
184
185
<8>
<8>
DDR_B_MA10
DDR_B_MA11
DDR_B_MA11
DDR_B_MA12
120
119
A10_AP
A11
DQS2#(C)
70 DDR_B_D53
DDR_B_DQS#7 <8>
READ ADDRESS: 0XA3 31

35
VSS
VSS
VSS
VSS
188
189
<8>
<8>
DDR_B_MA12
DDR_B_MA13
DDR_B_MA13
DDR_B_MA14
158
151
A12
A13
DQ24
DQ25
71
83
DDR_B_D54
DDR_B_D49
SA0 = 0; SA1 = 1; SA2 = 0. 36
39
VSS
VSS
VSS
VSS
192
193
<8>
<8>
DDR_B_MA14
DDR_B_MA15
DDR_B_MA15
DDR_B_MA16
156
152
A14_WE#
A15_CAS#
DQ26
DQ27
84
66
DDR_B_D50
DDR_B_D55
DDR4 POR OPERATING SPEED: 3200 MT/S 40
43
VSS
VSS
VSS
VSS
196
197
<8> DDR_B_MA16
DDR_B_ACT# 114
A16_RAS# DQ28
DQ29
67
79
DDR_B_D52
DDR_B_D51
VSS VSS <8> DDR_B_ACT# ACT# DQ30 DDR_B_D48
44 201 80
47 VSS VSS 202 DDR_B_PAR 143 DQ31 76 DDR_B_DQS6
VSS VSS <8> DDR_B_PAR DDR_B_ALERT# PARITY DQS3(T) DDR_B_DQS#6 DDR_B_DQS6 <8>
48 205 116 74
VSS VSS <8> DDR_B_ALERT# DDR_B_EVENT# ALERT# DQS3#(C) DDR_B_DQS#6 <8>
51 206 2 RD18 1 134
C
Decopling Cap._Channel B 52
56
VSS
VSS
VSS
VSS
VSS
VSS
209
210
+1.2V_VDDQ 240_0402_1%
<8,23> DDR_DRAMRST#_R
DDR_DRAMRST#_R 108 EVENT#
RESET# DQ32
DQ33
174
173
DDR_B_D13
DDR_B_D14
C
57 213 187 DDR_B_D10

60 VSS VSS 214 254 DQ34 186 DDR_B_D9
VSS VSS <9,23> SOC_SMBDATA SDA DQ35 DDR_B_D15
61 217 253 170
64 VSS VSS 218 <9,23> SOC_SMBCLK SCL DQ36 169 DDR_B_D12
65 VSS VSS 222 +3VS 166 DQ37 183 DDR_B_D8
Layout Note: VSS VSS SA2 DQ38 DDR_B_D11
Layout Note: 68 223 260 182
Place near JDIMM2B.258 69 VSS VSS 226 256 SA1 DQ39 179 DDR_B_DQS1
PLACE THE CAP WITHIN 200 MILS 72 VSS VSS 227 SA0 DQS4(T) 177 DDR_B_DQS#1 DDR_B_DQS1 <8>
FROM THE JDIMM1 VSS VSS DQS4#(C) DDR_B_DQS#1 <8>
73 230
77 VSS VSS 231 92 195 DDR_B_D6
78 VSS VSS 234 91 CB0_NC DQ40 194 DDR_B_D7
+0.6V_DDRB_VREFCA +0.6VS_VTT 85 VSS VSS 239 88 CB3_NC DQ43 191 DDR_B_D4
2.2uF *1 10uF *1+1uF *2 VSS VSS For ECC DIMM CB4_NC DQ44 DDR_B_D5
86 243 87 190
0.1uF *1 89 VSS VSS 244 +1.2V_VDDQ 100 CB5_NC DQ45 203 DDR_B_D2
2 2 VSS VSS CB7_NC DQ47
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
93 248 RD32 2 1 240_0402_1% 97 200 DDR_B_DQS0

1 1 1 VSS VSS DQS8(T) DQS5(T) DDR_B_DQS0 <8>
CD51 @ CD52 94 251 RD33 2 1 240_0402_1% 95 198 DDR_B_DQS#0
VSS VSS DQS8#(C) DQS5#(C) DDR_B_DQS#0 <8>
CD48
CD49
CD50
0.1U_0201_10V6K 2.2U_0201_6.3V6M 98 252

1 1 VSS VSS 216 DDR_B_D28
2 2 2 262 261 12 DQ48 215 DDR_B_D31
GND GND +1.2V_VDDQ 33 DM0#/DBI0# DQ49 228 DDR_B_D24
54 DM1#/DBI1# DQ50 229 DDR_B_D25
LOTES_ADDR0205-P001A 75 DM2#/DBI2# DQ51 211 DDR_B_D29
178 DM3#/DBI3# DQ52 212 DDR_B_D30
CONN@ DM4#/DBI4# DQ53
199 224 DDR_B_D26
220 DM5#/DBI5# DQ54 225 DDR_B_D27
241 DM6#/DBI6# DQ55 221 DDR_B_DQS3
Part Number: SP07001HW00 96 DM7#/DBI7# DQS6(T) 219 DDR_B_DQS#3 DDR_B_DQS3 <8>
DM8#/DBI8# DQS6#(C) DDR_B_DQS#3 <8>
Layout Note: Part Value: S SOCKET LOTES ADDR0205-P001A DDR4 STD
Place near JDIMM2B.257,259
B 237 DDR_B_D23 B
EMC CAPS-PLACE DQ56
DQ57
236 DDR_B_D20
249 DDR_B_D17
< 4mm from SO-DIMM VDDQ DQ58
DQ59
250 DDR_B_D16
+2.5V DDR_B_D22
10uF *1 with each pair < 12mm Apart DQ60
232
233 DDR_B_D19
1uF *1 DQ61
12pF* 5 (EMI@) 261
262 GND1 DQ62
245
246
DDR_B_D18
DDR_B_D21
GND2 DQ63
2.2pF* 5 (EMI@) +1.2V_VDDQ DDR_B_DQS2
1U_0201_6.3V6M
1 1 242
DQS7(T) DDR_B_DQS2 <8>
10U_0402_6.3V6M
240 DDR_B_DQS#2
DQS7#(C) DDR_B_DQS#2 <8>
CD46
CD47
+1.2V_VDDQ +1.2V_VDDQ +1.2V_VDDQ +1.2V_VDDQ +1.2V_VDDQ

2 2
LOTES_ADDR0205-P001A
CONN@
1 1 1 1 1 1 1 1 1 1
DIMM Side
CD16
CD17
CD18
CD19
CD20
CD21
CD22
CD23
CD24
CD25
CPU Side
12P_0201_50V8J
12P_0201_50V8J
12P_0201_50V8J
12P_0201_50V8J
12P_0201_50V8J
2.2P_0201_50V8C
2.2P_0201_50V8C
2.2P_0201_50V8C
2.2P_0201_50V8C
2.2P_0201_50V8C
2 RD21
2 2 2 2 2 2 2 2 2 2
1K_0402_1%
+0.6V_DDRB_VREFCA +0.6V_B_VREFCA
EMI@
EMI@
EMI@
EMI@
EMI@
EMI@
EMI@
EMI@
EMI@
EMI@
1 RD27 2
Layout Note: 2_0402_1%
VREF traces should be at least 20 mils
Place near JDIMM2 wide with 20 mils spacing to other
2
RD28
1 signals
1K_0402_1% CD44
follow RVP 1p0 0.022U_0402_16V7K
2
10uF*8
1
1uF*8
2
A +1.2V_VDDQ +1.2V_VDDQ A
@330uF*1 +1.2V_VDDQ RD29
24.9_0402_1%
placeholder
1
1
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 @
+ CD69
CD53
CD54
CD55
CD56
CD57
CD58
CD59
CD60
CD61
CD62
CD63
CD64
CD65
CD66
CD67
CD68
330U_D2_2V_Y
SGA20331E10
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DDRIV_CHB: DIMM0
1A
5 4 3 2 1
1 2 3 4 5
A A
B B
C C
D D

eDP / DMIC / IR Camera / Touch
1A
1 2 3 4 5
1 2 3 4 5
A A
B B
C C
D D

1A
1 2 3 4 5
5 4 3 2 1
Main Func = Nv - GPU Pex
+1.8VSDGPU_AON
UV1A
2
1/14 PCI_EXPRESS
RV1
10K_0201_5% VGA@
AG30
<33> PLTRST_VGA#_1V8 PEX_WAKE#
1
D D
AG29
PEX_RST#
AG31 PEX_CLKREQ#
VGA_CLKREQ#_R
<33> VGA_CLKREQ#_R +PEX_VDD GN20-S5(GB3-64) : 0.95V
Intel/ AMD naming GN18-S5(GB3B-64) : 1.0V
CLK_PEG_VGA AE30
<11> CLK_PEG_VGA CLK_PEG_VGA# PEX_REFCLK
AE31 PEX_REFCLK#
<11> CLK_PEG_VGA#
PCIE4_B_CRX_C_DTX_P0 AC27
<13> PCIE4_B_CRX_C_DTX_P0 PCIE4_B_CRX_C_DTX_N0 PEX_TX0
AC28 AA25
<13> PCIE4_B_CRX_C_DTX_N0 PEX_TX0# PEX_DVDD
1U_0201_6.3V6M
CV1
1U_0201_6.3V6M
CV2
1U_0201_6.3V6M
CV3
1U_0201_6.3V6M
CV4
4.7U_0402_6.3V6M
CV8
10U_0402_6.3V6M
CV10
10U_0402_6.3V6M
CV15
22U_0603_6.3V6M
CV14
PEX_DVDD
U25 1 1 1 1 1 1 1 1
PCIE4_B_CTX_C_DRX_P0 AC30 V25
<13> PCIE4_B_CTX_C_DRX_P0 PCIE4_B_CTX_C_DRX_N0 PEX_RX0 PEX_DVDD
AC31 V26
<13> PCIE4_B_CTX_C_DRX_N0 PEX_RX0# PEX_DVDD
PEX_DVDD
W25
PCIE4_B_CRX_C_DTX_P1 2 2 2 2 2 2 2 2
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
AA27 PEX_TX1 PEX_DVDD
Y25
<13> PCIE4_B_CRX_C_DTX_P1 PCIE4_B_CRX_C_DTX_N1 AA28 Y26
<13> PCIE4_B_CRX_C_DTX_N1 PEX_TX1# PEX_DVDD
PCIE4_B_CTX_C_DRX_P1 AA31
<13> PCIE4_B_CTX_C_DRX_P1 PCIE4_B_CTX_C_DRX_N1 PEX_RX1
AA30 PEX_RX1#
<13> PCIE4_B_CTX_C_DRX_N1
PCIE4_B_CRX_C_DTX_P2 W27
W28 PEX_TX2#
<13> PCIE4_B_CRX_C_DTX_N2
PCIE4_B_CTX_C_DRX_P2 W31 1 X 4.7uF(0402), 1 X 22uF(0603),
<13> PCIE4_B_CTX_C_DRX_P2 PCIE4_B_CTX_C_DRX_N2 PEX_RX2 4 X 1uF(0201) 2 X 10uF(0402)
W30
<13> PCIE4_B_CTX_C_DRX_N2 PEX_RX2# Place Under GPU(Ball) Place near GPU
PCIE4_B_CRX_C_DTX_P3 U28
U27
<13> PCIE4_B_CRX_C_DTX_N3 PEX_TX3#
PCIE4_B_CTX_C_DRX_P3 U30 AB25
<13> PCIE4_B_CTX_C_DRX_P3 PCIE4_B_CTX_C_DRX_N3 PEX_RX3 PEX_CVDD
U31 AB26
<13> PCIE4_B_CTX_C_DRX_N3 PEX_RX3# PEX_CVDD
+1.8VSDGPU_MAIN
PEX_HVDD
AC25
C PEX_HVDD
AD25 C
1U_0201_6.3V6M
CV16
1U_0201_6.3V6M
CV17
1U_0201_6.3V6M
CV18
4.7U_0402_6.3V6M
CV20
10U_0402_6.3V6M
CV21
10U_0402_6.3V6M
CV22
22U_0603_6.3V6M
CV23
PEX_HVDD
AE26 1 1 1 1 1 1 1
PEX_HVDD
AE27
PEX_HVDD
AE28
2 2 2 2 2 2 2
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
PEX_PLL_HVDD
AD26
1 X 4.7uF(0402), 1 X 22uF(0603),
3 X 1uF(0201) 2 X 10uF(0402)
Place Under GPU(Ball) Place near GPU
+PEX_PLL_HVDD +1.8VSDGPU_MAIN
RV2 2 RS@ 1 0_0402_5%

DVT
1
CV24
VGA@ 1U_0201_6.3V6M
2
B
QS PN MP PN B
UV1 UV1
S IC GN18-S5-A1 BGA 771P GPU PS S S IC GN18-S5-A1 BGA 771P GPU ABO !

@ GN18S@
SA0000EG510 SA0000EG560
UV1 UV1
S IC GN20-S5-A1 BGA 771P GPU PS S S IC GN20-S7-A1 BGA 771P GPU ABO !

GN20S5@ GN20S7@
SA0000EJE30 SA0000F8A30
R30 PEX_CVDD_SENSE TV1 @

PEX_CVDD_SENSE
R31 PEX_TREMP 1 2
PEX_TERMP
RV4 VGA@
2.49K_0402_1%
Place near GPU
GN20-S5-ES-A1_BGA771~D
@
A A

NV(1/10)-PCIE
5 4 3 2 1
5 4 3 2 1
Main Func = Nv - MEMORY: GPU Partition A/B
+FB_PLLVDD +1.8VSDGPU_MAIN
VGA@
0.328A 20mil LV2 1 2 50 mils
TAI-TECH HCB1608KF-330T30
1U_0201_6.3V6M
CV25
1U_0201_6.3V6M
CV26
1U_0201_6.3V6M
CV27
4.7U_0402_6.3V6M
CV28
4.7U_0402_6.3V6M
CV29
22U_0603_6.3V6M
CV30
1 1 1 1 1 1 SM01000JX00
D 2 2 2 2 2 2 D
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
UV1B
2/14 FBA
G24
FB_PLLVDD
FB_PLLVDD
H7 Under GPU Near GPU
<29> FBA_D[0..63] FBA_D0
H6 FBA_D0
FBA_D1 FBA_CMD0 FBA_CMD[0..24] <29>
F6 FBA_D1 FBA_CMD0
F11
FBA_D2 F5 A12 FBA_CMD1
FBA_D3 FBA_D2 FBA_CMD1
F4 D11 FBA_CMD2
E3 B12 FBA_CMD3
E8 D12 FBA_CMD4
D6 C12 FBA_CMD5
E4 F12 FBA_CMD6
H4 D14 FBA_CMD7
J6 B14 FBA_CMD8
J4 A14 FBA_CMD9
L5 A15 FBA_CMD10
L4 C14 FBA_CMD11
H5 B15 FBA_CMD12
R6 A9 FBA_CMD13
J3 E11 FBA_CMD14
B5 C9 FBA_CMD15
F2 C11 FBA_CMD16
B3 E12 FBA_CMD17
C3 C15 FBA_CMD18
A3 A11 FBA_CMD19
C2 C8 FBA_CMD20
B2 B8 FBA_CMD21
C1 A8 FBA_CMD22
M4 B11 FBA_CMD23
M1 B9 FBA_CMD24
M2 FBA_D26 FBA_CMD25_NC
F14
FBA_D27 M3 F15
FBA_D28 FBA_D27 FBA_CMD26_NC
C P1 E14 FBA_CMD27 C
FBA_D29 FBA_D28 FBA_CMD27 FBA_CMD[28..52] <29>
P3 D20 FBA_CMD28
R4 C24 FBA_CMD29
J2 F20 FBA_CMD30
H26 B24 FBA_CMD31
F27 F21 FBA_CMD32
E29 A24 FBA_CMD33
F28 D21 FBA_CMD34
E26 B18 FBA_CMD35
E28 C17 FBA_CMD36
F26 A18 FBA_CMD37
D26 A17 FBA_CMD38
J28 B17 FBA_CMD39
R27 D17 FBA_CMD40
J26 B23 FBA_CMD41
R26 C23 FBA_CMD42
L28 C21 FBA_CMD43
H27 B21 FBA_CMD44
H28 A21 FBA_CMD45
J29 A20 FBA_CMD46
B27 E21 FBA_CMD47
F30 C20 FBA_CMD48
E30 B20 FBA_CMD49
F31 C18 FBA_CMD50
B29 E20 FBA_CMD51
C31 A23 FBA_CMD52
C29 FBA_D54 FBA_CMD53_NC
D15
FBA_D55 Follow ORB NC
B30 FBA_D55 FBA_CMD54_NC
E15
FBA_D56 M29 E18 FBA_CMD55
D18
FBA_D58 M28 E17
FBA_D59 FBA_D58 FBA_CMD57_NC
F18 Follow ORB NC
FBA_D60
J30 FBA_D60 FBA_CMD59_NC
F17
FBA_D61 P30
FBA_D62 FBA_D61
P29 FBA_D62
FBA_D63
R28 FBA_D63
E9
B FBA_CLK0 FBA_CLK0 <29> B
F9
FBA_CLK0#
F23 FBA_CLK0# <29>
FBA_CLK1 FBA_CLK1 <29> +FBVDDQ +FBVDDQ
E23
FBA_CLK1# FBA_CLK1# <29>
<29> FBA_DBI[0..7] 0 FBA_DBI0 E6 FBA_DQM0
1
FBA_DBI1
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
1 P6 FBA_DQM1
FBA_DBI2
RV5
VGA@
RV6
VGA@
RV7
VGA@
RV8
VGA@
2 E2 FBA_DQM2
FBA_DBI3
3 R2 FBA_DQM3
4 FBA_DBI4 E24 D5
FBA_DBI5 FBA_DQM4 FBA_WCK01 FBA_WCK01 <29>
5 P26 FBA_DQM5 FBA_WCK01#
C5
FBA_WCK01# <29>
2
FBA_DBI6 FBA_CMD14 FBA_CMD17
6 A29 FBA_DQM6 FBA_WCK23
B6
FBA_WCK23 <29>
7 FBA_DBI7 P28 FBA_DQM7 FBA_WCK23#
FBA_WCK45
A6
D27
C27
FBA_WCK23#
FBA_WCK45
<29>
<29>
CKE_A FBA_CMD44 CKE_B FBA_CMD41
FBA_WCK45# FBA_WCK45# <29>
FBA_WCK67
A26
<29> FBA_EDC[0..7] FBA_EDC0 FBA_WCK67 <29>
0 F8 FBA_DQS_WP0 FBA_WCK67#
B26
1 FBA_EDC1 R5 FBA_WCK67# <29>
FBA_EDC2 FBA_DQS_WP1
2 F1 FBA_DQS_WP2
3 FBA_EDC3 P4 FBA_CMD3 FBA_CMD27
FBA_EDC4 FBA_DQS_WP3
4 F24 FBA_DQS_WP4
5
FBA_EDC5 L27 FBA_CMD31 FBA_CMD55
FBA_DQS_WP5
FBA_EDC6
Reset
49.9K_0402_1%
49.9K_0402_1%
6 C30 FBA_DQS_WP6
1
FBA_EDC7
10K_0201_5%
10K_0201_5%
7 P31 FBA_DQS_WP7
Debug
RV9
VGA@
RV10
VGA@
RV267
RV266
@
@
L6
FBA_WCKB01 FBA_WCKB01 <29>
M6
FB_VREF FBA_WCKB01#
L1 FBA_WCKB01# <29> Follow ORB
RV14
FBA_WCKB23 <29>
2
FBA_WCKB23
L2
FBA_WCKB23# FBA_WCKB23# <29>
L26
49.9_0402_1%
RV14 GN18S@
3.9P_0402_50V8C
M26
1
1 L31
CV316
GN18S@
L30
2.49K_0402_1%
GN20S@
SD034249180 2
2
A J31 FB_VREF A
@

NV(2/10)-GPU_VRAM
5 4 3 2 1
5 4 3 2 1
Main Func = Nv - GPU MEMORY: GDDR6 Vram
MEMORY: FBA Partition 63..32

MEMORY: FBA Partition 31..0
@ @
UV4 UV5
C2 B4 C2 B4
<28> FBA_EDC1 EDC0_A DQ0_A FBA_D8 <28> <28> FBA_EDC7 EDC0_A DQ0_A FBA_D56 <28>
C13 A3 C13 A3
<28> FBA_EDC3 EDC1_A DQ1_A FBA_D9 <28> <28> FBA_EDC5 EDC1_A DQ1_A FBA_D57 <28>
T2 B3 T2 B3
<28> FBA_EDC0 EDC0_B DQ2_A FBA_D10 <28> <28> FBA_EDC6 EDC0_B DQ2_A FBA_D58 <28>
T13 B2 T13 B2
<28> FBA_EDC2 EDC1_B DQ3_A FBA_D11 <28> <28> FBA_EDC4 EDC1_B DQ3_A FBA_D59 <28>
E3 E3
DQ4_A FBA_D12 <28> DQ4_A FBA_D60 <28>
E2 E2
DQ5_A FBA_D13 <28> DQ5_A FBA_D61 <28>
D2 F2 D2 F2 UV4 SAM2G@ UV5 SAM2G@
<28> FBA_DBI1 DBI0#_A DQ6_A FBA_D14 <28> <28> FBA_DBI7 DBI0#_A DQ6_A FBA_D62 <28>
D13 G2 D13 G2
<28> FBA_DBI3 DBI1#_A DQ7_A FBA_D15 <28> <28> FBA_DBI5 DBI1#_A DQ7_A FBA_D63 <28>
R2 B11 R2 B11
<28> FBA_DBI0 DBI0#_B DQ8_A FBA_D24 <28> <28> FBA_DBI6 DBI0#_B DQ8_A FBA_D40 <28>
R13 A12 R13 A12 IC D6 256M32 K4Z80325BC-HC14 1.2V ABO! IC D6 256M32 K4Z80325BC-HC14 1.2V ABO!
<28> FBA_DBI2 DBI1#_B DQ9_A FBA_D25 <28> <28> FBA_DBI4 DBI1#_B DQ9_A FBA_D41 <28>
D B12 B12 SA0000C6280 SA0000C6280 D
DQ10_A FBA_D26 <28> DQ10_A FBA_D42 <28>
B13 B13
DQ11_A FBA_D27 <28> DQ11_A FBA_D43 <28>
J10 E12 J10 E12
<28> FBA_CLK0 CK_T DQ12_A FBA_D28 <28> <28> FBA_CLK1 CK_T DQ12_A FBA_D44 <28>
K10 E13 K10 E13 UV4 HYN2G@ UV5 HYN2G@
<28> FBA_CLK0# CK_C DQ13_A FBA_D29 <28> <28> FBA_CLK1# CK_C DQ13_A FBA_D45 <28>
G10 F13 G10 F13
<28> FBA_CMD14 CKE#_A DQ14_A FBA_D30 <28> <28> FBA_CMD44 CKE#_A DQ14_A FBA_D46 <28>
M10 G13 M10 G13
<28> FBA_CMD17 CKE#_B DQ15_A FBA_D31 <28> <28> FBA_CMD41 CKE#_B DQ15_A FBA_D47 <28>
S IC D6 256M32 H56C8H24AIR-S2C FBGA ABO! S IC D6 256M32 H56C8H24AIR-S2C FBGA ABO!
U4 U4 SA0000DUW20 SA0000DUW20
DQ0_B FBA_D6 <28> DQ0_B FBA_D48 <28>
V3 V3
DQ1_B FBA_D0 <28> DQ1_B FBA_D49 <28>
U3 U3
DQ2_B FBA_D1 <28> DQ2_B FBA_D50 <28>
J5 U2 J5 U2 UV4 HYN2GC@ UV5 HYN2GC@
<28> FBA_CMD10 CABI#_A DQ3_B FBA_D3 <28> <28> FBA_CMD37 CABI#_A DQ3_B FBA_D51 <28>
K5 P3 K5 P3
<28> FBA_CMD9 CABI#_B DQ4_B FBA_D4 <28> <28> FBA_CMD38 CABI#_B DQ4_B FBA_D52 <28>
P2 P2
DQ5_B FBA_D2 <28> DQ5_B FBA_D53 <28>
N2 N2 S IC D6 256M32 H56G32CS4DX005 FBGA ABO ! S IC D6 256M32 H56G32CS4DX005 FBGA ABO !
DQ6_B FBA_D5 <28> DQ6_B FBA_D54 <28>
VGA@ M2 VGA@ M2 SA0000ENP40 SA0000ENP40
DQ7_B FBA_D7 <28> DQ7_B FBA_D55 <28>
RV17 121_0402_1% U11 RV15 U11
DQ8_B FBA_D16 <28> DQ8_B FBA_D34 <28>
2 1 FBA_ZQ_1_A V12 2 1 121_0402_1% FBA_ZQ_2_A V12
DQ9_B FBA_D17 <28> DQ9_B FBA_D32 <28>
J14 U12 J14 U12
ZQ_A DQ10_B FBA_D18 <28> ZQ_A DQ10_B FBA_D39 <28>
K14 U13 K14 U13
ZQ_B DQ11_B FBA_D19 <28> ZQ_B DQ11_B FBA_D35 <28>
2 1 FBA_ZQ_1_B P12 2 1 121_0402_1% FBA_ZQ_2_B P12
DQ12_B FBA_D20 <28> DQ12_B FBA_D36 <28>
P13 P13 UV4 SAM4G@ UV5 SAM4G@
DQ13_B FBA_D21 <28> DQ13_B FBA_D38 <28>
RV16 121_0402_1% N13 RV18 N13
DQ14_B FBA_D22 <28> DQ14_B FBA_D37 <28>
VGA@ M13 VGA@ M13
DQ15_B FBA_D23 <28> DQ15_B FBA_D33 <28>
S IC D6 512M32 K4ZAF325BM-HC14 NR3C ABO! S IC D6 512M32 K4ZAF325BM-HC14 NR3C ABO!
SA0000CBG60 SA0000CBG60
N5 H3 N5 H3
TCK CA0_A FBA_CMD1 <28> TCK CA0_A FBA_CMD33 <28>
F10 G11 F10 G11
TDI CA1_A FBA_CMD13 <28> TDI CA1_A FBA_CMD45 <28>
N10 G4 N10 G4 UV4 MIC4G@ UV5 MIC4G@
TDO CA2_A FBA_CMD12 <28> TDO CA2_A FBA_CMD35 <28>
F5 H12 F5 H12
TMS CA3_A FBA_CMD24 <28> TMS CA3_A FBA_CMD46 <28>
H5 H5
CA4_A FBA_CMD11 <28> CA4_A FBA_CMD36 <28>
H10 H10 S IC D6 512M32 MT61K512M32KPA-14:C FBGA 180P ABO ! S IC D6 512M32 MT61K512M32KPA-14:C FBGA 180P ABO !
J12 J12 SA0000ERM30 SA0000ERM30
D4 J11 D4 J11
<28> FBA_WCKB01 WCK0_T_A CA7_A FBA_CMD23 <28> <28> FBA_WCKB67 WCK0_T_A CA7_A FBA_CMD47 <28>
D5 J4 D5 J4
<28> FBA_WCKB01# WCK0_C_A CA8_A FBA_CMD0 <28> <28> FBA_WCKB67# WCK0_C_A CA8_A FBA_CMD34 <28>
D11 J3 D11 J3
<28> FBA_WCKB23 WCK1_T_A CA9_A FBA_CMD2 <28> <28> FBA_WCKB45 WCK1_T_A CA9_A FBA_CMD32 <28>
D10 D10
<28> FBA_WCKB23# WCK1_C_A <28> FBA_WCKB45# WCK1_C_A
L3 L3
CA0_B FBA_CMD5 <28> CA0_B FBA_CMD29 <28>
M11 M11
R4 M4 R4 M4
<28> FBA_WCK01 WCK0_T_B CA2_B FBA_CMD7 <28> <28> FBA_WCK67 WCK0_T_B CA2_B FBA_CMD40 <28>
R5 L12 R5 L12
<28> FBA_WCK01# WCK0_C_B CA3_B FBA_CMD20 <28> <28> FBA_WCK67# WCK0_C_B CA3_B FBA_CMD50 <28>
R11 L5 R11 L5
<28> FBA_WCK23 WCK1_T_B CA4_B FBA_CMD8 <28> <28> FBA_WCK45 WCK1_T_B CA4_B FBA_CMD39 <28>
R10 L10 R10 L10
<28> FBA_WCK23# WCK1_C_B CA5_B FBA_CMD16 <28> <28> FBA_WCK45# WCK1_C_B CA5_B FBA_CMD42 <28>
K12 K12
K11 K11
K4 K4
K3 K3
CA9_B +FBVDDQ FBA_CMD4 <28> CA9_B +FBVDDQ FBA_CMD30 <28>
1 VGA@ 2 K1 1 VGA@ 2 K1
RV19 1K_0402_1% VREFC RV20 1K_0402_1% VREFC
C1 C1
J1 VDDQ1 E1 J1 VDDQ1 E1
<28> FBA_CMD3 RESET# VDDQ2 <28> FBA_CMD31 RESET# VDDQ2
C H1 H1 C
VDDQ3 L1 VDDQ3 L1
B1 VDDQ4 P1 B1 VDDQ4 P1
D1 VSS1 VDDQ5 T1 D1 VSS1 VDDQ5 T1
F1 VSS2 VDDQ6 J2 F1 VSS2 VDDQ6 J2
G1 VSS3 VDDQ7 K2 G1 VSS3 VDDQ7 K2
M1 VSS4 VDDQ8 C4 M1 VSS4 VDDQ8 C4
N1 VSS5 VDDQ9 F4 N1 VSS5 VDDQ9 F4
R1 VSS6 VDDQ10 N4 R1 VSS6 VDDQ10 N4
U1 VSS7 VDDQ11 T4 U1 VSS7 VDDQ11 T4
A2 VSS8 VDDQ12 B5 A2 VSS8 VDDQ12 B5
V2 VSS9 VDDQ13 U5 V2 VSS9 VDDQ13 U5
C3 VSS10 VDDQ14 B10 C3 VSS10 VDDQ14 B10
D3 VSS11 VDDQ15 U10 D3 VSS11 VDDQ15 U10
F3 VSS12 VDDQ16 C11 F3 VSS12 VDDQ16 C11
G3 VSS13 VDDQ17 F11 G3 VSS13 VDDQ17 F11
M3 VSS14 VDDQ18 N11 M3 VSS14 VDDQ18 N11
N3 VSS15 VDDQ19 T11 N3 VSS15 VDDQ19 T11
R3 VSS16 VDDQ20 J13 R3 VSS16 VDDQ20 J13
T3 VSS17 VDDQ21 K13 T3 VSS17 VDDQ21 K13
A4 VSS18 VDDQ22 C14 A4 VSS18 VDDQ22 C14
E4 VSS19 VDDQ23 E14 E4 VSS19 VDDQ23 E14
H4 VSS20 VDDQ24 H14 H4 VSS20 VDDQ24 H14
L4 VSS21 VDDQ25 L14 L4 VSS21 VDDQ25 L14
P4 VSS22 VDDQ26 P14 P4 VSS22 VDDQ26 P14
V4 VSS23 VDDQ27 T14 V4 VSS23 VDDQ27 T14
C5 VSS24 VDDQ28 +FBVDDQ C5 VSS24 VDDQ28 +FBVDDQ
T5 VSS25 T5 VSS25
C10 VSS26 A1 C10 VSS26 A1
T10 VSS27 VDD1 V1 T10 VSS27 VDD1 V1
A11 VSS28 VDD2 H2 A11 VSS28 VDD2 H2
E11 VSS29 VDD3 L2 E11 VSS29 VDD3 L2
H11 VSS30 VDD4 E5 H11 VSS30 VDD4 E5
L11 VSS31 VDD5 P5 L11 VSS31 VDD5 P5
P11 VSS32 VDD6 E10 P11 VSS32 VDD6 E10
V11 VSS33 VDD7 P10 V11 VSS33 VDD7 P10
C12 VSS34 VDD8 H13 C12 VSS34 VDD8 H13
D12 VSS35 VDD9 L13 D12 VSS35 VDD9 L13
F12 VSS36 VDD10 A14 +1.8VSDGPU_AON F12 VSS36 VDD10 A14
G12 VSS37 VDD11 V14 G12 VSS37 VDD11 V14 +1.8VSDGPU_AON
M12 VSS38 VDD12 +1.8VSDGPU_AON M12 VSS38 VDD12 +1.8VSDGPU_AON
N12 VSS39 N12 VSS39
VSS40 VSS40
1U_0201_6.3V6M
CV39
1U_0201_6.3V6M
CV40
1U_0201_6.3V6M
CV41
1U_0201_6.3V6M
CV42
R12 A5 1 1 1 1 R12 A5
VSS41 VPP1 VSS41 VPP1
1U_0201_6.3V6M
CV43
1U_0201_6.3V6M
CV44
1U_0201_6.3V6M
CV45
1U_0201_6.3V6M
CV46
T12 V5 T12 V5 1 1 1 1
A13 VSS42 VPP2 A10 A13 VSS42 VPP2 A10
V13 VSS43 VPP3 V10 V13 VSS43 VPP3 V10
VSS44 VPP4 2 2 2 2 VSS44 VPP4
VGA@
VGA@
VGA@
VGA@
B14 B14
VSS45 VSS45 2 2 2 2
VGA@
VGA@
VGA@
VGA@
D14 D14
F14 VSS46 G5 F14 VSS46 G5
G14 VSS47 NC1 M5 G14 VSS47 NC1 M5
B M14 VSS48 NC2 M14 VSS48 NC2 B
N14 VSS49 Place near VPP N14 VSS49
R14 VSS50 R14 VSS50 Place near VPP
U14 VSS51 U14 VSS51
180-BALL 180-BALL
VSS52 SGRAM GDDR6 VSS52 SGRAM GDDR6
MT61K256M32JE-13-A_FBGA180~D MT61K256M32JE-13-A_FBGA180~D
6x 0603W 22uF + 2x 0603 10uF
6x 0603W 22uF + 2x 0603 10uF

+FBVDDQ
Around VRAM
+FBVDDQ
Around VRAM 10U_0402_6.3V6M
CV47
10U_0402_6.3V6M
CV48
22U_0603_6.3V6M
CV49
22U_0603_6.3V6M
CV50
22U_0603_6.3V6M
CV51
22U_0603_6.3V6M
CV52
22U_0603_6.3V6M
CV53
22U_0603_6.3V6M
CV54
22U_0603_6.3V6M
CV322 VGA_EMI@
22U_0603_6.3V6M
CV323 VGA_EMI@
1 1 1 1 1 1 1 1 1 1
10U_0402_6.3V6M
CV31
10U_0402_6.3V6M
CV32
22U_0603_6.3V6M
CV33
22U_0603_6.3V6M
CV34
22U_0603_6.3V6M
CV35
22U_0603_6.3V6M
CV36
22U_0603_6.3V6M
CV37
22U_0603_6.3V6M
CV38
1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
2 2 2 2 2 2 2 2
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
EMI Request DVT
+FBVDDQ 0402 1UF X18 + 0603 10UF X4

0402 1UF X18 + 0603 10UF X4
+FBVDDQ
1U_0201_6.3V6M
CV76
1U_0201_6.3V6M
CV77
1U_0201_6.3V6M
CV78
1U_0201_6.3V6M
CV79
1U_0201_6.3V6M
CV80
1U_0201_6.3V6M
CV81
1U_0201_6.3V6M
CV82
1U_0201_6.3V6M
CV83
1U_0201_6.3V6M
CV84
1U_0201_6.3V6M
CV85
1U_0201_6.3V6M
CV86
1U_0201_6.3V6M
CV87
1U_0201_6.3V6M
CV88
1U_0201_6.3V6M
CV89
1U_0201_6.3V6M
CV90
1U_0201_6.3V6M
CV91
1U_0201_6.3V6M
CV92
1U_0201_6.3V6M
CV321
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1U_0201_6.3V6M
CV55
1U_0201_6.3V6M
CV56
1U_0201_6.3V6M
CV57
1U_0201_6.3V6M
CV58
1U_0201_6.3V6M
CV59
1U_0201_6.3V6M
CV60
1U_0201_6.3V6M
CV61
1U_0201_6.3V6M
CV62
1U_0201_6.3V6M
CV63
1U_0201_6.3V6M
CV64
1U_0201_6.3V6M
CV65
1U_0201_6.3V6M
CV66
1U_0201_6.3V6M
CV67
1U_0201_6.3V6M
CV68
1U_0201_6.3V6M
CV69
1U_0201_6.3V6M
CV70
1U_0201_6.3V6M
CV71
1U_0201_6.3V6M
CV320
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
+FBVDDQ
+FBVDDQ
10U_0402_6.3V6M
CV93
10U_0402_6.3V6M
CV94
10U_0402_6.3V6M
CV95
10U_0402_6.3V6M
CV96
1 1 1 1
CLOSE OR UNDER DRAM

10U_0402_6.3V6M
CV72
10U_0402_6.3V6M
CV73
10U_0402_6.3V6M
CV74
10U_0402_6.3V6M
CV75
1 1 1 1
A A
CLOSE OR UNDER DRAM 2 2 2 2

VGA@
VGA@
VGA@
VGA@
2 2 2 2
VGA@
VGA@
VGA@
VGA@

2021/08/05 2022/08/05 Title
Issued Date Deciphered Date
Nv(3/10) GDDR6_VRAM
1A
5 4 3 2 1
1 2 3 4 5
Main Func = NV - GPU GND, RFU & RSVD
12/14 GND_1/2 UV1M

A2 GND GND
D8
13/14 GND_2/2
A27 GND GND
D9
A30 GND GND
E1
A5 GND GND
E27
AA10 GND GND
E31
AA12 GND GND
E5
AA14 GND GND
F10
AA16 GND GND
F13
AA18 GND GND
F16 AF15
GND
AA20 GND GND
F19 U29
A GND A
AA22 GND GND
F22 V11
GND
AA26 GND GND
F25 V13
GND
AA29 GND GND
F29 V15
GND
AB11 GND GND
F3 V17
GND
AB13 GND GND
F7 V19
GND
AB15 GND GND
G2 V21
GND
AB17 GND GND
G26 V23
GND
AB19 GND GND
G28 V27
GND
AB2 GND GND
G30 V29
GND
AB21 GND GND
G4 V30
GND
AB23 GND GND
G6 V9
GND
AB27 GND GND
J1 W10
GND
AB29 GND GND
J10 W12
GND
AB30 GND GND
J12 W14
GND
AB4 GND GND
J14 W16
GND
AB6 GND GND
J16 W18
GND
AB9 GND GND
J18 W2
GND
AC10 GND GND
J20 W20
GND
AC12 GND GND
J22 W22
GND
AC14 GND GND
J27 W26
GND
AC16 GND GND
J5 W29
GND
AC18 GND GND
K11 W4
GND
AC20 GND GND
K13 W6
GND
AC22 GND GND
K15 Y11
GND
AC26 GND GND
K17 Y13
GND
AC29 GND GND
K19 Y15
GND
AD27 GND GND
K2 Y17
GND
AD29 GND GND
K21 Y19
GND
AD30 GND GND
K23 Y21
GND
AE14 GND GND
K26 Y23
GND
AE2 GND GND
K28 Y27
GND
AE29 GND GND
K30 Y29
GND
AE4 GND GND
K4 Y30
GND
AE6 GND GND
K6 Y9
GND
AF10 GND GND
K9
AF13 GND GND
L10
AF16 GND GND
L12
B AF19 GND GND
L14 B
AF22 GND GND
L16
AF26 GND GND
L18
AF27 GND GND
L20
AF28 GND GND
L22
AF29 GND GND
L29
AF30 GND GND
L3
AF7 GND GND
M11
AG28 GND GND
M13 GN20-S5-ES-A1_BGA771~D
AH10 GND GND
M15 @
AH11 GND GND
M17
AH12 GND GND
M19
AH13 GND GND
M21
AH14 GND GND
M23
AH15 GND GND
M27
AH16 GND GND
M5
AH17 GND GND
M9
AH18 GND GND
N10
AH19 GND GND
N12
AH2 GND GND
N14
AH20 GND GND
N16
AH21 GND GND
N18
AH22 GND GND
U26
AH23 GND GND
N2
AH24 GND GND
N20
AH25 GND GND
N22
AH26 GND GND
N26
AH27 GND GND
N28
AH28 GND GND
N30
AH30 GND GND
N4
AH4 GND GND
N6
AH7 GND GND
P11
AJ8 GND GND
P13
AJ9 GND GND
P15
AK1 GND GND
P17
AK10 GND GND
P19
AK13 GND GND
P2
AK16 GND GND
P21
C C
AK19 GND GND
P23
AK22 GND GND
P27
AK25 GND GND
P5
AK28 GND GND
P9
AK31 GND GND
R10
AK4 GND GND
R12
AK7 GND GND
R14
AL2 GND GND
R16
AL30 GND GND
R18
B1 GND GND
R20
B10 GND GND
R22
B13 GND GND
R29
B16 GND GND
R3
B19 GND GND
T11
B22 GND GND
T13
B25 GND GND
T15
B28 GND GND
T17
B31 GND GND
T19
B4 GND GND
T2
B7 GND GND
T21
C26 GND GND
T23
C6 GND GND
T26
D10 GND GND
T28
D13 GND GND
T30
D16 GND GND
T4
D19 GND GND
T6
D2 GND GND
T9
D22 GND GND
U10
D23 GND GND
U12
D24 GND GND
U14
D25 GND GND
U16
D28 GND GND
U18
D30 GND GND
U20
D4 GND GND
U22
D7 GND
D D
@

Nv(4/10) GND
1 2 3 4 5
1 2 3 4 5
Main Func = NV - GPU Strap, Rom, Xtal

ZZZ GN18X76H2G@ ZZZ GN18X76S4G@
8Gb VRAM Strap 0 Strap 1 Strap 2
GN18 X76 VRAM HYN 2G GN18 X76 VRAM SAM 4G
X76954BOL03 X76954BOL08 SAMSUNG L L L SAM2G@ SAM2G@ SAM2G@
(0x0) RV180 100K_0201_5% RV182 100K_0201_5% RV191 100K_0201_5%
ZZZ GN18X76S2G@ SD043100380 SD043100380 SD043100380
HYNIX HYN2G@ HYN2G@ HYN2G@

GN20 X76 VRAM SAM 2G
L H L RV180 100K_0201_5% RV181 100K_0201_5% RV191 100K_0201_5%
(0x2)
X76954BOL04 SD043100380 SD043100380 SD043100380
HYNIX C-Die H L H HYN2GC@ HYN2GC@ HYN2GC@

ZZZ X76H2GC@ (0x5) RV179 100K_0201_5% RV182 100K_0201_5% RV190 100K_0201_5%
SD043100380 SD043100380 SD043100380
GN18 X76 VRAM HYN 2G C-Die

X76954BOL07
+1.8VSDGPU_AON 16Gb VRAM Strap 0 Strap 1 Strap 2
A A
RAMCFG UV1I
9/14 MISC2
ZZZ GN20X76H2G@ ZZZ GN20S7X76S4G@ SAMSUNG
(0x9)
L M L SAM4G@
RV180 100K_0201_5%
SD043100380
SAM4G@ SAM4G@ SAM4G@
RV181 100K_0201_5% RV182 100K_0201_5% RV191 100K_0201_5%
SD043100380 SD043100380 SD043100380
GN20 X76 VRAM HYN 2G GN20-S7 X76 VRAM SAM 4G
+1.8VSDGPU_AON Micron MIC4G@ MIC4G@ MIC4G@
X76954BOL05 X76954BOL51 H H H
1
1
100K_0201_5%
RV179
100K_0201_5%
RV181
100K_0201_5%
RV190
100K_0201_5%
RV176
100K_0201_5%
RV189
100K_0201_5%
RV177
@
(0x7) RV179 100K_0201_5% RV181 100K_0201_5% RV190 100K_0201_5%
ZZZ GN20X76S2G@ ZZZ GN20S7X76H4G@ SD043100380 SD043100380 SD043100380
@ @ @ @ @ V7 ROM_CS#
ROM_CS#
1
100K_0201_5%
RV183
10K_0201_5%
RV184
100K_0201_5%
RV185
GN20 X76 VRAM SAM 2G GN20-S7 X76 VRAM MIC 4G
2
2
X76954BOL06 X76954BOL52
GN20S@
STRAP0 AG4
STRAP0
STRAP1 AG3
2
STRAP1 ROM_SI
STRAP2 AG6 U7
STRAP2 ROM_SI ROM_SO
STRAP3 AH5 V6
STRAP3 ROM_SO ROM_SCLK
STRAP4 AH6 U6
STRAP4 ROM_SCLK
STRAP5 AG5
STRAP5
100K_0201_5%
RV274
10K_0201_5%
RV197
100K_0201_5%
RV275
1
1
100K_0201_5%
RV180
100K_0201_5%
RV182
100K_0201_5%
RV191
100K_0201_5%
RV272
100K_0201_5%
RV273
100K_0201_5%
RV195
VGA@
VGA@
VGA@
VGA@
VGA@
GN18S@
@ @ @
2
2
Strap Res. Place on BOT
@
DGPU VBIOS ROM 8Mb +1.8VSDGPU_AON +1.8VSDGPU_AON

B B
VGA@ GN18S@
10K_0402_1%
1
1
RV37 2 CV297 VGA@

10K_0402_5%
0.1U_0201_10V6K
RV36
2
33_0402_5% VGA@ UV2 GN18S@ VGA@
2
ROM_CS# RV39 1 2 ROM_CS_R# 1 8 RV41

ROM_SO RV276 1 2 ROM_SO_R 2 CS# VCC 7 33_0402_5%
0_0402_5% RS@ 3 DO(IO1) HOLD#(IO3) 6 ROM_SCLK_R 1 2 ROM_SCLK
PVT WP#(IO2) CLK
4 5 ROM_SI_R 1 2 ROM_SI
GND DI(IO0)
10K_0402_1%
<33> ROM_WP#_R
RV42 2
W25Q80EWSSIG_SO8 VGA@
GN20S@ SA00009QP00 RV40
33_0402_5%
1
UV2
GN20S@
S IC FL 16M W25Q16JWSSIQ SOIC 8P SPI ROM

SA0000DHJ00
+1.8VSDGPU_MAIN +GPU_PLLVDD
C C
VGA@
LV3 1 2
TAI-TECH HCB1608KF-330T30
4.7U_0402_6.3V6M
CV302
22U_0603_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
SM01000JX00 1 1 1 1 1 1 UV1H
CV303
CV298 VGA@
CV299 VGA@
CV300 VGA@
CV301 VGA@
8/14 XTAL_PLL
SM01000JX00
3000ma 33ohm@100mhz DCR 0.04 2 2 2 2 2 2
AE15
CORE_PLL_AVDD XTALOUTBUFF : 100K ohm pull down only.
VGA@
AE12
GPCADC_AVDD
VGA@
AF8
SP_PLLVDD +1.8VSDGPU_AON
AE8
VID_PLLVDD
Place Near GPU Place under GPU AJ1 XTAL_OUTBUFF 1 @ 2

XTAL_OUTBUFF RV204 100K_0402_1%
XTALSSIN_GPU AG2
EXT_REFCLK_FL
1
AJ2 XTALOUT
10K_0402_1%
10K_0402_1%
XTAL_OUT
VGA@ VGA@ XTALIN AK2 RV46
RV277 RV45 XTAL_IN VGA@ 100K_0402_1%
2
@
1
CV319 VGA@
18P_0402_50V8J
2
RV43 VGA@ YV1 VGA@

470_0402_1%
XTALOUT 2 1 XTALOUT_R 1 3 XTALIN
1 3
NC NC
1 1
CV304 VGA@ 2 4 CV305 VGA@
18P_0402_50V8J 18P_0402_50V8J
2 SJ10000UI00 2
27MHZ_10PF_XRCGB27M000F2P18R0
D D

Nv(5/10) Strap,Rom,Xtal
1 2 3 4 5
1 2 3 4 5
Main Func = Nv - GPU Power

1x 0603 10uF , 3x 0603 22uF FBVDDQ_GPU 2x 0603 10 uF , 8x 1uF
Close to GPU Decoupling Under GPU
+FBVDDQ
+NVVDD1 +NVVDD1
+FBVDDQ
1U_0201_6.3V6M
CV97
1U_0201_6.3V6M
CV98
1U_0201_6.3V6M
CV99
1U_0201_6.3V6M
CV100
UV1J 1 1 1 1
10/14 VDD
A A
10U_0402_6.3V6M
CV107
22U_0603_6.3V6M
CV108
22U_0603_6.3V6M
CV109
22U_0603_6.3V6M
CV110
AA11 VDD
R15 1 1 1 1
VDD 2 2 2 2
VGA@
VGA@
VGA@
VGA@
AA13 VDD
R17
AA15 VDD R19
VDD VDD
AA17 VDD
R21
VDD 2 2 2 2
VGA@
VGA@
VGA@
VGA@
AA19 VDD
R23
AA21 VDD R9
VDD VDD
AA23 VDD
T10
AA9 VDD T12
VDD VDD
AB10 VDD
T14
AB12 VDD T16
VDD VDD
AB14 VDD
T18
AB16 VDD T20
VDD VDD
1U_0201_6.3V6M
CV101
1U_0201_6.3V6M
CV102
1U_0201_6.3V6M
CV103
1U_0201_6.3V6M
CV104
AB18 VDD
T22 1 1 1 1
VDD
AB20 VDD
U11
AB22 VDD U13
VDD VDD
AC11 U15 +FBVDDQ
VDD VDD 2 2 2 2
VGA@
VGA@
VGA@
VGA@
AC13 VDD
U17 UV1K
AC15 VDD U19
VDD VDD 11/14 FBVDDQ
AC17 VDD
U21
AC19 VDD U23
VDD VDD
AC21 VDD
U9
AC23 VDD V10 G11
VDD VDD FBVDDQ
AC9 VDD
V12 G12 FBVDDQ
VDD
J11 VDD
V14 G14 FBVDDQ
VDD
10U_0402_6.3V6M
CV105
10U_0402_6.3V6M
CV106
J13 VDD
V16 G15 FBVDDQ 1 1
J15 VDD V18 G17
VDD VDD FBVDDQ
J17 VDD
V20 G18 FBVDDQ
J19 VDD V22 G20
VDD VDD FBVDDQ
2 2
VGA@
VGA@
J21 VDD
W11 G21 FBVDDQ
J23 VDD W13 G23
VDD VDD FBVDDQ
J9 VDD
W15 G8 FBVDDQ
K10 VDD W17 G9
VDD VDD FBVDDQ
K12 VDD
W19 H25 FBVDDQ
VDD
K14 VDD
W21 J25 FBVDDQ
K16 VDD W23 J7
VDD VDD FBVDDQ
K18 VDD
W9 L25 FBVDDQ
K20 VDD Y10 L7
B VDD FBVDDQ B
K22 VDD Y12 M25
VDD VDD FBVDDQ
L11 VDD
Y14 M7 FBVDDQ
L13 VDD Y16 P25
VDD VDD FBVDDQ
L15 VDD
Y18 P7 FBVDDQ RS@
L17 VDD Y20 R25 1 RV29 2
VDD VDD FBVDDQ FBVDDQ_GND_SENSE <108>
L19 VDD
N17 R7 FBVDDQ PVT 0_0402_5%
VDD
L21 VDD
N19
L23 VDD N21
VDD VDD
L9 VDD
N23
M10 VDD N9 H1 FBVDDQ_SENSE 1 FB_VDDQ_SENSE
VDD PVT RS@ 2
VDD FBVDDQ_SENSE FB_VDDQ_SENSE <108>
M12 VDD
P10 RV21 0_0201_1%
VDD
M14 VDD
P12
M16 VDD P14 +FBVDDQ
VDD VDD
M18 VDD
P16
M20 VDD P18 H31 FB_CAL_PD_VDDQ 1 2 40.2_0402_1%
VDD FB_CAL_PD_VDDQ
VGA@ RV22
M22 VDD P20 H30 FB_CAL_PU_GND 1 2 40.2_0402_1%
VDD FB_CAL_PU_GND VGA@ RV23
VDD FB_CALTERM_GND
N11 VDD
P22 FB_CALTERM_GND
H29 VGA@ RV24 1 2 40.2_0402_1%
N13 VDD R11
VDD VDD
N15 VDD
R13
VDD Y22
VDD
@
+1.8VSDGPU_AON
H2 VDD_SENSE RV30 1 VGA@ 2 0_0201_5% VCC_SENSE_NVVDD1

VDD_SENSE GND_SENSE VSS_SENSE_NVVDD1 VCC_SENSE_NVVDD1 <103>
H3 RV31 1 VGA@ 2 0_0201_5% 0.558A
GND_SENSE VSS_SENSE_NVVDD1 <103>
1U_0201_6.3V6M
CV113
1U_0201_6.3V6M
CV114
1U_0201_6.3V6M
CV115
4.7U_0402_6.3V6M
CV116
4.7U_0402_6.3V6M
CV117
4.7U_0402_6.3V6M
CV118
1 1 1 1 1 1
C 2 2 2 2 2 2 C
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
3 X 4.7UF(0603),
@ 3 X 1UF(0402/0201)
UV1N
Near GPU
14/14 1V8 / NC
1U_0201_6.3V6M
CV119
1U_0201_6.3V6M
CV120
1U_0201_6.3V6M
CV121
1U_0201_6.3V6M
CV122
1 1 1 1
AC6
1V8
AA5 AC7
NC 1V8
AE23 AD6
NC 1V8 2 2 2 2
VGA@
VGA@
VGA@
VGA@
AE24 AD7
NC 1V8
AF23 4 X 1UF (0402/0201)
NC
AF24
AF25
AG23
AG24
NC
NC
NC
Under GPU
NC
AG27
NC +FUSE_SRC
AJ3
NC
Y5
NC
FUSE_SRC
AF14
@
D D

Nv(6/10) PWR
1 2 3 4 5
5 4 3 2 1
Main Func = Nv - MISC

+1.8VSDGPU_MAIN
+1.8VSDGPU_AON
VGA_OVERT# RV214 1 VGA@ 2 10K_0201_5%
UV1G FRM_LCK# RV216 1 VGA@ 2 10K_0201_5%

Intel /AMD naming
5
7/14 MISC1
NVVDD_PSI RV217 1 VGA@ 2 10K_0201_5%
G
AL6 VGA_I2CS_SCL VGA_I2CS_SCL 4 3
I2CS_SCL VGA_I2CS_SDA EC_SMB_CK1 <58,66> VGA_ALERT#
D
AL5 RV220 1 VGA@ 2 10K_0201_5%
I2CS_SDA
PJT138KA_SOT363-6
AJ5 VGA_I2CC_SCL +1.8VSDGPU_AON QV14A VGA@ ACIN_BUF RV221 1 VGA@ 2 10K_0201_5%
I2CC_SCL
2
AK5 VGA_I2CC_SDA PJT138KA_SOT363-6
I2CC_SDA GPIO22_ADC_MUX_SEL
unused pin PH 4.7K to 1V8 (Checklist) QV14B VGA@ RV222 1 VGA@ 2 2.2K_0402_5%
G
VGA_OVERT# AF2 AJ6 RV80 1 VGA@ 2 4.7K_0201_5% VGA_I2CS_SDA 1 6
D OVERT I2CB_SCL EC_SMB_DA1 <58,66> D
AK6 RV81 1 VGA@ 2 4.7K_0201_5% FBVDDQ_PSI 1 VGA@ 2 10K_0201_5%
D
RV223
I2CB_SDA
R1
TS_VREF AF5 NVVDD_VID
AF1
GPIO0
V5 GC6_FB_EN1V8 NVVDD_VID <103>
THERMDN GPIO1 VGA_I2CS_SDA
AC3 RV78 1 VGA@ 2 1.8K_0402_1%
GPIO2 VGA_I2CS_SCL
AG1 Y6 RV79 1 VGA@ 2 1.8K_0402_1%
THERMDP GPIO3 GPIO4_EN
Y2 Level FBVDD
GPIO4 FRM_LCK# VGA_I2CC_SDA
AD4 RV82 1 VGA@ 2 4.7K_0201_5%
GPIO5 NVVDD_PSI VGA_I2CC_SCL
Y3 MEM_VDD_CTL H 1.35V/1.25V RV83 1 VGA@ 2 4.7K_0201_5%
GPIO6 NVVDD_PSI <103>
V1
GPU_JTAG_TCK GPIO7 VRAM_VDD_CTL
TV2 @ AJ31 U5 L 1.2V
GPU_JTAG_TMS AL29
JTAG_TCK GPIO8
U1 VGA_ALERT# VRAM_VDD_CTL <108> GPIO4_EN 1 VGA@ 2 10K_0201_5%
TV3 @ RV289
GPU_JTAG_TDI JTAG_TMS GPIO9 VRAM_VREF_CTL
TV4 @ AK30 AC4
GPU_JTAG_TDO JTAG_TDI GPIO10
TV5 @ AJ30 AA2
GPU_JTAG_TRST# JTAG_TDO GPIO11 ACIN_BUF
TV6 @ AK29 AA7 DV1 2 1
GPU_NVJTAG_SEL JTAG_TRST# GPIO12 DGPU_AC_DETECT <58,59,85>
TV7 @ AJ29 AA4 VGA@ No connect to OVRM(Gen2 only)
NVJTAG_SEL GPIO13
AA6 RB751S40T1G_SOD523-2
GPIO14 GC6_FB_EN1V8
AF4 RV215 1 VGA@ 2 10K_0201_5%
GPIO15
AD2
GPIO16 NVVDD_PSI
AL3 ADC_IN
AD1 RV218 1 @ 2 10K_0201_5%
<35> ADC_IN_P GPIO17
AK3 ADC_IN#
AF3
<35> ADC_IN_N GPIO18
AC5 VRAM_VDD_CTL 1 2 10K_0201_5%
RV219 @
GPIO19
External current sense for power monitoring AC1
GPIO20 VRAM_VREF_CTL
AD3 RV290 1 @ 2 10K_0201_5%
GPIO21 GPIO22_ADC_MUX_SEL
AC2
GPIO22 GPIO22_ADC_MUX_SEL <35>
AA3
GPIO23
U4
GPIO24 FBVDDQ_PSI
Y7
GPU_JTAG_TRST# GPIO25
AF6 GPU_GPIO26 2 GN18S@ 1 0_0201_5% FBVDDQ_PSI <108>
RV94
GPU_NVJTAG_SEL GPIO26 GPIO26_FP_FUSE <36>
AD5
GPIO27
U3 RV95 2 GN20S@ 1 0_0402_5% To Rom ,FUSE IC
GPIO28 ROM_WP#_R <31>
V2
GPIO29
U2
GPIO30 +1.8VSDGPU_AON
V3
GPIO31
Y1 PU at PCH side
GPIO32
1
VGA@ VGA@ AA1

GPIO33 CLKREQ_GPU# <11>
2
RV270 RV271 V4
GPIO34
C 10K_0201_5% 10K_0201_5% Y4 RV98 VGA@ C
GPIO35
10K_0201_5%
2
@ VGA@
3
ALL_GPWRGD
D
5 G QV16A
S
PJT138KA_SOT363-6
1
0.1U_0201_10V6K
4
VGA@
CV261
2
VGA_CLKREQ#_R <27>
Pin Name Default Function
JTAG_TRST L JTAG module will drive signal.

GPU side need to pull low as default
2
NVJTAG_SEL L Test Mode --> Disable
G
1 6
D
H Test Mode --> Enable
QV16B
PJT138KA_SOT363-6
VGA@
B B
+1.8VSDGPU_AON +3VS
Change to pop due to GPAK OD pin 2021/9/17 UV21
VGA@
RV99 1 VGA@ 2 10K_0201_5% PLTRST_VGA#_1V8 0.1U_0201_10V6K 2 1 1 20
Intel /AMD naming CV262 VDD 1V8_MAIN_EN 1.8VSDGPU_MAIN_EN3V3 <36>
20200814
0.1U_0201_10V6K 2 1 CV263 - DGPU_PWR EN re-name to SOC_DGPU_PWR_EN GPIO4_EN 2 19
1V8_MAIN_EN_GPU PEGX_RST# PLTRST_VGA#_1V8 <27>
@
0.1U_0201_10V6K 2 1 CV264 VGA_OVERT# 3 18
<12> SOC_DGPU_PWR_EN DGPU_PWR_EN PEX_VDD_EN PEX_VDD_EN <36,110>
@
0.1U_0201_10V6K 2 1 CV265 GPIO4_EN GC6_FB_EN1V8 RV268 2 RS@ 1 0_0402_5% GC6_FB_EN1V8_R 4
@ 2 1 10K_0201_5% GC6_FB_EN_GPU 17
DVT RV269 @
FB_VDD_EN FBVDDQ_EN <36,108>
5
<110> PEX_VDD_PG PEX_VDD_PG
6 16
<12> GC6_FB_EN3V3 GC6_FB_EN 3V3_SYS_EN 3VSDGPU_EN <36>
<108> FBVDDQ_PG 7
FB_VDD_PG 15 ALL_GPWRGD
VGA_OVERT# 8 ALL_GPU_PWR_OK
OVERT#_GPU
20200814 14 GPU_OVERT# <59>
- DGPU_HOLD_RST# re-name to SOC_DGPU_HOLD_RST# OVERT#
9 13 1V8_AON_EN <36>
<12> SOC_DGPU_HOLD_RST# DGPU_HOLD_RST# 1V8_AON_EN
12
NVVDD_EN NVVDD1_EN <36,103>
10
<11,42,51,52,66,69> PLT_RST_R# PLT_RST#
20200814
- PLT_RST# re-name to PLT_RST_R# 11
GND
SLG4U43589VTR_STQFN20_3X2
@ SA0000DH100
UV21
A VGA@ A
S IC SLG4U44276VTR STQFN 20P LOGIC SOC

SA0000DZ000

Nv(7/10) MISC
5 4 3 2 1
5 4 3 2 1
Main Function:Nv - IFP ABCD
UV1F
UV1C
3/14 IFPAB 6/14 IFPE
DVI HDMI DP AF11

IFPE_RSET
SL/DL HDMI DP
IFPA_L3#
AL20
AG26 TXC/TXC AL21
IFPAB_RSET TXC/TXC IFPA_L3
D VGA@ AH8 D
IFPC_AUX_SDA#
VGA@ RV206 IFPC_AUX_SCL
AG8
RV205 TXD0/0 IFPA_L2#
AK21 1 2 AF9
1 2 AE11 AJ21 IFPE_PLLVDD
IFPAB_PLLVDD TXD0/0 IFPA_L2
10K_0201_5% TXC IFPE_L3# AL8
10K_0201_5% TXC IFPE_L3 AK8
TXD1/1 IFPA_L1# AJ23
TXD1/1 IFPA_L1
AK23
TXD0 IFPE_L2# AL9
TXD0 IFPE_L2 AK9
AL24
TXD2/2 IFPA_L0#
TXD2/2 IFPA_L0
AL23
TXD1 IFPE_L1# AJ11
IFPE_L1 AK11
IFPAB IFPA_AUX_SDA#
AG18
TXD1
IFPA_AUX_SCL AG17
TXD2 IFPE_L0# AL11
TXD2 IFPE_L0 AL12
TXC AK27 AE17

IFPB_L3# IFP_IOVDD
TXC AJ27 AE18
IFPB_L3 IFP_IOVDD
TXD0/3 AJ26
IFPB_L2#
AF17 TXD0/3 AK26
IFP_IOVDD IFPB_L2
AF18 GN20-S5-ES-A1_BGA771~D
IFP_IOVDD
AF20
IFP_IOVDD @
AF21 TXD1/4 AK24
IFP_IOVDD IFPB_L1#
TXD1/4 AJ24
IFPB_L1
TXD2/5 IFPB_L0# AL27

TXD2/5 IFPB_L0
AL26
C C
AG15
IFPB_AUX_SDA#
AG14
IFPB_AUX_SCL
@
UV1E
UV1D
5/14 IFPD
4/14 IFPC
AF12 HDMI DP
IFPCD_RSET
HDMI DP
IFPC_AUX_SDA#
AH9
IFPC_AUX_SDA# AG11 IFPC_AUX_SCL
AG9
IFPC_AUX_SCL AG12
B B
VGA@ AJ12
TXC IFPD_L3#
RV207 TXC
AJ18 TXC
AK12
IFPC_L3# IFPD_L3
1 2 AE9 TXC AK18
IFPCD_PLLVDD IFPC_L3
AK14
TXD0 IFPD_L2#
10K_0201_5% TXD0 AJ14
TXD0 AJ20 IFPD IFPD_L2
IFPC TXD0
IFPC_L2#
IFPC_L2
AK20
AJ15
TXD1 IFPD_L1#
AL17 TXD1 AK15
TXD1 IFPC_L1# IFPC_L1
TXD1 IFPC_L1
AL18
TXD2 IFPD_L0#
AL15
TXD2 IFPC_L0# AJ17 TXD2 AL14
IFPD_L0
TXD2 AK17
IFPC_L0
AG20 IFP_IOVDD
AE20 AG21
IFP_IOVDD IFP_IOVDD
AE21
IFP_IOVDD
GN20-S5-ES-A1_BGA771~D GN20-S5-ES-A1_BGA771~D
@ @
A A
Security Classification
2021/08/05
Compal Secret Data
2022/08/05 Title
Compal Electronics, Inc.
Nv(8/10) IFP ABCD
5 4 3 2 1
A B C D E
OVR-M GEN1 GEN2 NV suggest BS_IN3,4 need also connect with BS_IN2(CSSP_FBVDD)
No use SH_P/N need PU the same voltage as no use BS_IN

For OVRM Keep ON +3V_OVRM
1
+3V_OVRM +3VS
RV193
0_0402_5%
ON_GEN1@ Remove GEN2
0_0402_5%2 RS@ 1 RV178
2
NV Suggest DVT
1 uPI_GEN1@
CV272 ON_GEN1@ ON_GEN1@ RV265 2 1 0_0402_5%
CSSP_B+ 75K_0402_1%1 GEN1@ 2 RV101 PFM_CH1_BS_IN1 0.1U_0201_10V6K 2 1 100_0402_1%1 2 RV103 CSSP_B+
NV Suggest OVRM@ 0_0402_5% RV240 CSSP_B+ <103>
1
1 2 CV273 1
1000P_0402_50V7K 1 2 CV271 1 RV104 2 680P_0402_50V7K
1
ON_GEN1@ ON_GEN1@
2K_0402_5%
RV110
ON_GEN1@
2K_0402_5%
RV111
ON_GEN1@
2K_0402_5%
RV112
ON_GEN1@
2K_0402_5%
RV113
ON_GEN1@
GEN1@ 665_0402_1% ON_GEN1@
0_0402_5%2 1 RV105 CSSN_B+
CSSN_B+ <103>
CSSP_FBVDD 75K_0402_1%1 GEN1@ 2 RV106 PFM_CH1_BS_IN2
2
ON_GEN1@ ON_GEN1@ PFM_CH1_SH_IN_P3
1 2 49.9_0402_1% 1 2 RV109 CSSP_FBVDD PFM_CH1_SH_IN_N3
1000P_0402_50V7K 1 2 CV274 1 RV108 2 49.9_0402_1% RV241 CSSP_FBVDD <103> SNN_PFM_CH1_SH_IN_P4
ON_GEN1@ SNN_PFM_CH1_SH_IN_N4
1
1
GEN1@ 665_0402_1% CV275
1
RV114 .1U_0402_16V7K
0_0402_5% RV115 ON_GEN1@
OVRM@ 0_0402_5% 2 ON_GEN1@
UPI-Semi suggest pop CV274/CV271 when GEN2 OVRM@ 0_0402_5%2 1 RV116 CSSN_FBVDD
2
Keep NV suggest to unpop when GEN2. CSSN_FBVDD <103>
2
UV20
3 27
6 BS_IN1 VCC
PFM_CH1_BS_IN3 11 BS_IN2 2 PFM_CH1_SH_IN_P1
PFM_CH1_BS_IN4 14 BS_IN3 SH_IN_P1 1 PFM_CH1_SH_IN_N1
BS_IN4 SH_IN_N1 5 PFM_CH1_SH_IN_P2
SH_IN_P2 4 PFM_CH1_SH_IN_N2
PFM_FILTER_GND_FET SH_IN_N2 PFM_CH1_SH_IN_P3 ADC_IN_N <33>
Remove GEN2 9 12
GND_FET SH_IN_P3 13 PFM_CH1_SH_IN_N3
SH_IN_N3 15 SNN_PFM_CH1_SH_IN_P4 ADC_IN_P <33>
RV122 1 2 442_0402_1% ON_GEN1@ SH_O1 32 SH_IN_P4 16 SNN_PFM_CH1_SH_IN_N4 ON_OVRM@ ON_OVRM@
RV123 1 2 634_0402_1% ON_GEN1@ IMON1 7 SH_O1 SH_IN_N4 ADC_IN_P RV125 1 2 0_0201_5% CV276 1 2 47P_0402_50V8J
SH_O2 2
RV124 1 2 169_0402_1% @ SH_O3 10 20
RV126 1 2 169_0402_1% @ BG_REF_OUT 17 SH_O3 DIFF_OUT_P 19 @ CV308 ON_OVRM@ ON_OVRM@
SH_O4 DIFF_OUT_N ADC_IN_N 47P_0402_50V8J RV127 1 2 0_0201_5% CV277 1 2 47P_0402_50V8J
30 PFM_PF_BSOK_R 1
0.015U_0402_16V7K
0.015U_0402_16V7K
0.015U_0402_16V7K
0.015U_0402_16V7K
BS_OK
1 1 1 1 1 RS@ 2 PFM_ADC_MUX_SEL_R 29 8 IMON2 TH4
MUX_SEL NC 18 BV_REF
GEN1@
GEN1@
RV128 0_0201_5% TH3

NC 21
PVT ADSR0 Remove GEN2
CV278
CV279
CV280
CV281
@ @ TH2
PFM_ADC_FILTER_EN 28 NC 31 SYNC TH1
2 2 2 2 2 ENABLE NC ON_GEN1@ 237K_0402_1%
2
NV Suggest no use IMON PIN 23 PFM_BG_REF_OUT RV131 1 RS@ 2 0_0201_5% PFM_BG_REF_OUT_R 1 2 RV132 10K_0402_1% 1 OVRM@ 2 RV133
PFM_SKIP_R 25 BG_REF_OUT 24 PFM_BS_REF RV134 1 RS@ 2 0_0201_5% PFM_BS_REF_R
uPI PD GND SKIP BS_REF 22 PVT
ON NC Floating CM_REF_IN 365K_0402_1% 1 GEN1@ 2 RV135 681K_0402_1% 2 GEN1@ 1 RV136
PFM_ADC_FILTER_MODE 26 33
MODE_SEL GND PFM_CM_REF_IN RV194 1 RS@ 2 0_0402_5% PFM_CM_REF_IN_R
PVT
NCP45492XMNTWG_QFN32_4X4
<33> GPIO22_ADC_MUX_SEL @ Remove GEN2
SA0000CQX00 1 1
1000P_0402_50V7K
CV283
GEN1@
1000P_0402_50V7K
CV284
OVRM@
1
CV285
2 2 OVRM@ 1000P_0402_50V7K
+3V_OVRM
2
1
+3V_OVRM
RV141
10K_0201_5%
@
1
2
RV159
Remove GEN2 10K_0402_1%
PFM_ADC_FILTER_EN OVRM@
2
1
RV145 PFM_PF_BSOK_R
10K_0201_5%
OVRM@
2
3 3
+3V_OVRM
Remove GEN2
1
ZZZ X76GEN1ON@
RV151
BOM option
10K_0201_5%
@ ALT. GROUP PARTS OVRM ON HH5A4
ON_GEN1 OVRM@,GEN1@,ON_OVEM@,ON_GEN1@ X76954BOL01
2
ZZZ X76GEN1UPI@
PFM_ADC_FILTER_MODE ON_GEN2 OVRM@,GEN2@,ON_OVEM@,ON_GEN2@
ALT. GROUP PARTS OVRM UPI HH5A4
uPI_GEN1 OVRM@,GEN1@,uPI_GEN1@
1
X76954BOL02
RV156
10K_0201_5%
@
uPI_GEN2 OVRM@,GEN2@,uPI_GEN2@
Pin23 : I2C_CLK(PFM_BG_REF_OUT)
2
OVRM Chip selection GEN2 selection uPI Gen1 strap Pin24 : I2C_DATA(PFM_BS_REF)
RV104 uPI_GEN1@ RV110 uPI_GEN1@ RV122 uPI_GEN1@ RV240 uPI_GEN1@ RV241 uPI_GEN1@ CV273 uPI_GEN1@
499_0402_1% 0_0402_5% 332_0402_1% 0_0402_5% 49.9_0402_1% 680P_0402_50V7K

SD034499080 SD028000080 SD034332080 SD028000080 SD034499A80 SE074681K80
RV108 uPI_GEN1@ RV111 uPI_GEN1@ RV123 uPI_GEN1@ RV116 uPI_GEN1@ RV109 uPI_GEN1@ CV275 uPI_GEN1@
+3V_OVRM
499_0402_1% 0_0402_5% 475_0402_1% 0_0402_5% 49.9_0402_1% .1U_0402_16V7K Remove GEN2
SD034499080 SD028000080 SD034475080 SD028000080 SD034499A80 SE076104K80
1
RV112 uPI_GEN1@ RV132 uPI_GEN1@ RV103 uPI_GEN1@ RV105 uPI_GEN1@

RV152
1K_0402_1% UV20 uPI_GEN1@
4 4
ON_GEN1@ 0_0402_5% 316K_0402_1% 100_0402_1% 0_0402_5%
SD028000080 SD034316380 SD034100080 SD028000080
2
S IC US5650QQKI WQFN 32P POWER MONITOR

PFM_SKIP_R RV113 uPI_GEN1@ RV152 uPI_GEN1@
SA0000CMA00
UV20 ON_GEN1@
1
0_0402_5% 10K_0402_1% Follow NV CRB, OVRM/PWR IC use same I2C power rail.
RV199 SD028000080 SD034100280
30.1K_0402_1% S IC NCP45492XMNTWG QFN 32P MONITOR
@ SA0000CQX00
2
N18P(10/11)-G61A/N20P OVR-M
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HH5A4 MB LA-M211P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D E
5 4 3 2 1
Main Function: Nv - Sequence
+1.8VALW_PRIM
+1.8VSDGPU_AON DVT +1.8VSDGPU_MAIN
22U_0603_6.3V6M
RV208 1 RS@ 2 0_0805_5%
CV315
VGA@
+1.8V_AON/+3VSDGPU 20200902 Change Net form +1.8V_MAIN
2
+1.8VALW to +1.8VALW_PRIM
+1.8VALW_PRIM +1.8VSDGPU_MAIN
D 20200902 Change Net form D
+1.8VALW to +1.8VALW_PRIM +1.8VSDGPU_AON UV12
+1.8VALW_PRIM UV11 1
RV279 1 @ 2 1 14 RV209 1 @ 2 0_0603_5% 2 VIN1
VIN1 VOUT1 1 VIN2
0_0402_5% 2 13 VGA@ CV296
VIN1 VOUT1 1U_0201_6.3V6M 7 6
1V8_AON_EN_R VIN thermal VOUT
10U_0402_6.3V6M
RV278 1 @ 2 3 12 CV295 1 2 1
<33> 1V8_AON_EN +5VALW ON1 CT1 2
CV307
10U_0402_6.3V6M
0.1U_0201_10V6K
CV310
0_0402_5% 220P_0402_50V7K @ 3 1 1
+5VALW VBIAS
CV317
4 11
VBIAS GND RV210 1 @ 2 0_0402_5% MAIN_AON_EN 4 5
3VSDGPU_EN 2 <33> 1.8VSDGPU_MAIN_EN3V3 ON GND
5 10 CV318 1 2
<33> 3VSDGPU_EN ON2 CT2 +3VSDGPU 2 2
VGA@
0.1U_0201_10V6K
CV313
0.1U_0201_10V6K
CV314
220P_0402_50V7K @
+3VS 1V8_AON_EN
VGA@
VGA@
6 9 RV211 1 RS@ 2 0_0402_5% AOZ1334DI-01_DFN8-7_3X3
0.1U_0201_10V6K
1 VIN2 VOUT2 1 1
CV311 7 8 DVT VGA@
VIN2 VOUT2
SA000070V00
10U_0402_6.3V6M
VGA@
@ 15 1 @
2 GPAD 2 2
CV312
EM5209VF_DFN14_2X3
@
2
@
RV175 @ 20200902 Change Net form
1M_0402_5%
2 1 1V8_AON_EN +1.8VALW to +1.8VALW_PRIM
RV162 @
1M_0402_5%
2 1 3VSDGPU_EN
+1.8VSDGPU_AON
check NV +FUSE_SRC
RV173 2 GN20S@1 0_0402_5%

1
CV294
UV14
2.2U_0402_6.3V6M
GN18S@ 1
2 2 VIN1
VIN2 12mils
+5VALW 7 6
VIN thermal VOUT
1
3 1
VBIAS CV293 RV174
C 4 5 C
2.2U_0402_6.3V6M 2.21K_0402_1%
<33> GPIO26_FP_FUSE ON GND GN18S@ GN18S@
2
1
2
2
@ AOZ1334DI-01_DFN8-7_3X3
10K_0201_5%
RV172
CV292 GN18S@
0.1U_0201_10V6K SA000070V00
GN18S@ 2
1
GN20S GPUs do not need FP_FUSE circuit
B B
+3VSDGPU
+PEX_VDD
+FBVDDQ
2
+NVVDD1
2
+5VS @ VGA@
2
RV164 +5VS RV166 VGA@
2
1_0603_5% 20_0402_5% +5VS RV168 +5VS
2
@ 20_0402_5% VGA@
1
RV163 VGA@ RV170

1
2
100K_0402_5% RV165 VGA@ VGA@ 1_0603_5%
1
100K_0402_5% RV167 RV169
1
6
D 100K_0402_5% 100K_0402_5%
1
3VSDGPU_EN# 2 D
1
6
G PEX_VDD_EN# 2 D D
1
1
G FBVDDQ_EN# 2 NVVDD1_EN# 2
S G G
1
3
3
D QV2A S D D
1
3
3VSDGPU_EN 5 2N7002KDW_SOT363-6 D QV3A 5 S 5 S

<33,108> FBVDDQ_EN <33,103> NVVDD1_EN
1
G @ 5 2N7002KDW_SOT363-6 G QV4A G QV5A
<33,110> PEX_VDD_EN
G VGA@ 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
S S VGA@ S VGA@
4
4
QV2B S QV4B QV5B
4
2N7002KDW_SOT363-6 QV3B 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6

@ 2N7002KDW_SOT363-6 VGA@ VGA@
VGA@
A A

Nv(10/10) Sequence
5 4 3 2 1
1 2 3 4 5
A A
B B
Reserve page
C C
D D

Reserve
1A
1 2 3 4 5
A B C D E
LCD POWER CIRCUIT

+3VS
+3V_LCD I (Max) : 0.372 A(+3VS_EDP) 20200728
LCD enable signal +3VS
RDS(Typ) : 70 mohm - Remove 3S@ config
+3VALW 1 2 V drop : 0.026 V +LCDVDD +19VB +INVPWR_B+
Max: 222mA
2
RVE35 0_0805_5% UVE1 Inrush: 1.5A
1 2 5 1 W=60mils RVE1
RVE36 @ 0_0805_5% 1
IN OUT W=60mils LVE1 W=60mils 10K_0201_5%
0.1U_0201_10V6K
2 1 1 HCB2012KF-221T30_0805 @
4.7U_0402_6.3V6M
CVE13 GND 1 2
CVE11
CVE12
1
+3VALW
CVE15
1U_0201_6.3V6M LCDVDD_EN 4 3
2 EN OC
1000P_0402_50V7K
SM01000EJ00 3000ma 1 1
10P_0201_25V8
1
SY6288C20AAC_SOT23-5 2 2 CVE14 RVE3 1 RS@ 2 EDP_HPD_R
1 220ohm@100mhz <6> CPU_EDP_HPD 1
High active @ DCR 0.04 68P_0402_50V8J CVE22 0_0201_5%
@
EN_VL:1.1V @ @RF@
0.1U_0201_10V6K
2
1
2 2
1
VCC
SOC_ENVDD 1
CVE23
<6> SOC_ENVDD IN B ESD request 11/22
4 RVE2 ESD@
SUSP# 2 OUT Y 100K_0402_5% Note: Unmount LV5 when panel boost
GND
<11,16,38,58,69,78,85,89> SUSP# IN A RF request 08/06 2
circuit was use. (2S battery cell)
2
TD Used 680P
UVE3
3
NL17SZ08DFT2G_SC70-5
SA0000BJI00 PD 100K For Gitch by Intel
RVE4 1 RS@ 2 BKOFF#

<58> EC_BKOFF#
RVE37 1 @ 2 0_0201_5% 0_0201_5%
RVE5 1 2 10K_0201_5%
GLITCH@
DMIC From SoC PD 100K For Gitch by Intel
RVE6 1 RS@ 2 BKL_PWM_LCD To eDP Panel

DMIC_DATA 2 @ 1 DMIC_DATA_R
TO eDP cable <6> SOC_BKL_PWM
0_0201_5%
<56> DMIC_DATA
RVE10 0_0402_5%
1
PCH_DMIC_DATA 2 1 RVE8
<10> PCH_DMIC_DATA
RVE11 33_0402_5% 100K_0201_5%
@
PCH_DMIC_CLK 2 1
<10> PCH_DMIC_CLK
2
RVE12 33_0402_5%
DMIC_CLK 2 1 DMIC_CLK_R
<56> DMIC_CLK
LVE2 XEMC@ BLM15PX221SN1D_2P
SM01000Q500
Place closed to JEDP1
1
100_0402_5% 330P_0402_50V7K
RVE13
EMC@
change PN to SM01000Q500
2
Camera DVT
+3VS +LCDVDD
2
2
0.1U_0201_10V6K
USB20_N7 USB20_N7_CAMERA
CVE18
EMC@
1 RVE14 1 RS@ 2 0_0402_5% 1 1
10P_0201_25V8
.1U_0402_16V7K
<13> USB20_N7
1
CVE16 CVE17 @ CVE21
USB20_P7 RVE15 1 RS@ 2 0_0402_5% USB20_P7_CAMERA RF@
<13> USB20_P7
2
2 2 2
Follow Raptor
RF request 08/06
20200721 - For DMIC (CCD 8pin module) +DMIC_VCC
+INVPWR_B+
eDP Conn.
RVE7 1 @ 2 0_0402_5%
+3VALW CONN@
RVE9 1 RS@ 2 0_0402_5% W=60mils
+1.8VALW_PRIM
DVT 1
2 1 41
Change to 1.8V Level ,due to 3 2 G1 42
DATA/CLK change to 1.8v level port 2021/9/13 4 3 G2 43
5 4 G3 44
BKL_PWM_LCD 6 5 G4 45
+LCDVDD BKOFF# 7 6 G5 46
USB/I2C Touch Screen Co-Lay EDP_HPD_R 8 7 G6
9 8
+DMIC_VCC 10 9
Reserve for QHD Panel
W=60mils 11 10
+LCDVDD +TS_PWR 12 11
13 12
RVE33 1 QHD@ 2 0_0402_5% CPU_EDP_AUXN CVE9 1 2 0.1U_0201_10V6K CPU_EDP_AUXN_C 14 13
<6> CPU_EDP_AUXN CPU_EDP_AUXP CVE10 CPU_EDP_AUXP_C 14
1 2 0.1U_0201_10V6K 15
<6> CPU_EDP_AUXP 15
16
check USB TS power CPU_EDP_TXP0 CVE1 1 2 0.1U_0201_10V6K CPU_EDP_TXP0_C 17 16 eDP
<6> CPU_EDP_TXP0 CPU_EDP_TXN0 CVE2 1 2 0.1U_0201_10V6K CPU_EDP_TXN0_C 18 17 (4-Lane)
+5VS +3VS <6> CPU_EDP_TXN0 18
RVE16 1 @ 2 0_0402_5% 19
3 +3VS CPU_EDP_TXP1 CVE3 1 2 0.1U_0201_10V6K CPU_EDP_TXP1_C 20 19 3
Change to Place on I2C_TS_INT# PVT <6> CPU_EDP_TXP1 CPU_EDP_TXN1 CVE4 1 2 0.1U_0201_10V6K CPU_EDP_TXN1_C 21 20
UVE2
<6> CPU_EDP_TXN1 21
RVE17 1 I2CTS@ 2 0_0402_5% 5 1 22
IN OUT 100K_0402_5% 1 2 I2C_TS_INT# CPU_EDP_TXP2 CVE5 1 2 0.1U_0201_10V6K CPU_EDP_TXP2_C 23 22
<6> CPU_EDP_TXP2 23
10U_0402_6.3V6M
0.1U_0201_10V6K
RVE19 1USBTS@ 2 0_0402_5% 2 1 1 RVE18 CPU_EDP_TXN2 CVE6 1 2 0.1U_0201_10V6K CPU_EDP_TXN2_C 24

GND <6> CPU_EDP_TXN2 TS_I2C_INT#_R 24
TS@ 25
SOC_TS_RST# CPU_EDP_TXP3 CVE7 2 0.1U_0201_10V6K CPU_EDP_TXP3_C 25
CVE19
CVE20
4 3 1 I2CTS@ 2 100K_0402_5% 1 26
EN OC <6> CPU_EDP_TXP3 CPU_EDP_TXN3 CVE8 26
RVE20 1 2 0.1U_0201_10V6K CPU_EDP_TXN3_C 27
<6> CPU_EDP_TXN3 27
RVE21 1 @ 2 0_0201_5% SY6288C20AAC_SOT23-5 TS@ 2 2 SOC_TS_RST#_R 28
<9> SOC_TS_PWR_EN USB20_P8_I2C_5_SCL 28
TS@ 29
+TS_PWR USB20_N8_I2C_5_SDA 30 29
RVE22 1 @ 2 0_0201_5% 31 30
<59> EC_TS_PWR_EN 31
Touch 32
33 32
Screen 33
RVE31 1 RS@ 2 0_0201_5% TS_PANEL_OD_EN 34
<11,16,38,58,69,78,85,89> SUSP# 35 34
PVT +3VS 35
Change to SUSP# to enable TS PWR 10/5 RVE32 1 I2CTS@ 2 2.2_0201_1% TS_PANEL_OD_EN USB20_N7_CAMERA 36
<58> TS_EN USB20_P7_CAMERA 36
For 37
USB20_P8 RVE23 1 2 0_0402_5% USB20_P8_I2C_5_SCL RVE34 1 @ 2 0_0201_5% 38 37
<13> USB20_P8 <12> PANEL_OD_EN Camera 38
USBTS@ DMIC_CLK_R 39
USB20_N8 RVE24 1 2 0_0402_5% USB20_N8_I2C_5_SDA Reserve for QHD Panel DMIC_DATA_R 40 39
<13> USB20_N8 40
USBTS@
DMIC_DATA_R JEDP1
I2C_5_SCL RVE25 1 2 0_0201_5% STARC_107K40-000001-G2
<12> I2C_5_SCL +LCDVDD DMIC_CLK_R
I2CTS@ SP010014B10
I2C_5_SDA RVE26 1 2 0_0201_5%
<12> I2C_5_SDA
2
I2CTS@ 2
Reserve I2C Touch
RVE38
10K_0201_5%
@
SOC_TS_RST# RVE27 1 2 0_0201_5% SOC_TS_RST#_R XEMC@
<12> SOC_TS_RST#
1
I2CTS@ DVE7
TS_PANEL_OD_EN YSLC05CH_SOT23-3
I2C_TS_INT# RVE28 1 2 2.2_0201_1% TS_I2C_INT#_R
<12> I2C_TS_INT# SCA00004300
1
I2CTS@
2
4 4
RVE30 RVE29 RVE39
Reserve for EMC/ESD Suggestion 0_0201_5% 0_0201_5% 10K_0201_5%
USBTS@ USBTS@ RVE30 QHD@ RVE29 QHD@ @
1
0_0201_5% 0_0201_5%
Reserve for EMC/ESD Suggestion SD043000080 SD043000080

RSV
A B C D E
1 2 3 4 5
A A
B B
Reserve Page
C C
D D

1A
1 2 3 4 5
A B C D E
+1.2V_HDMI
+5VS W=40mils +HDMI_5V_OUT

CVH15 +5VALW HDMI_RT_R_CLKP HDMI_RT_CLKP
1U_0201_6.3V6M @
22P_0402_50V8J
UVH3
1
2 1 1
10U_0402_6.3V6M
10U_0402_6.3V6M
RVH9 LVH1
UVH2 4.99K_0402_1% 3 4 3
CVH17
+3VS 10 1 OUT
VDD VOUT 2 1 1 1
9 2 1
CVH18
CVH19
2
CVH16 8 VIN VOUT 3 2 1 IN CVH23
10U_0402_6.3V6M 7 VIN VOUT 4 2 0.1U_0201_10V6K
2 1 6 VIN ADJ/NC 5 2 2 HCM1012GH900BP_4P GND 2
EN PGOOD SM070003V00
1 1
1
11 HDMI_RT_R_CLKN HDMI_RT_CLKN AP2330W -7_SC59-3
PAD RVH10
RT9059GQW _W DFN10_3X3 10K_0402_1% 20191206 DVH1
SA000071S00 20191016 - Remove RY53/RY52/CY27 HDMI_RT_HPD 6 3 HDMI_CTRL_DAT
S IC RT9059GQW WDFN 10P LDO - Add for EMI test - LS15 change to pop (EMI@) I/O4 I/O2
2
+3VS 20191105 5 2
- DY1 DY2 DY3 for EE LL VDD GND
0.01U_0201_16V7
0.01U_0201_16V7
0.1U_0201_10V6K
+1.2V_HDMI +HDMI_5V_OUT
1 1 1 HDMI_CTRL_CLK 4 1
I/O3 I/O1
AZC099-04S.R7G_SOT23-6
CVH20
CVH21
@ESD@ SC300001G00
CVH22
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.01U_0201_16V7
0.01U_0201_16V7
0.01U_0201_16V7
2 2 2
1 1 1 1 1 1
DVH2 @ESD@
UVH1 HDMI_RT_CLKN HDMI_RT_CLKN
1 9
CVH9
CVH10
CVH11
CVH12
CVH13
CVH14
6 1
2 2 2 2 2 2 30 VDD12 VDD33 24 HDMI_RT_CLKP 2 8 HDMI_RT_CLKP
DC coupling enable; Internal pull up, 3.3V I/O. VDD12 VDD33
L: DC coupling input 11
43 VDDA12 HDMI_RT_TX_N0 4 7 HDMI_RT_TX_N0
H: Default,AC coupling input VDDRX12
46 23 HDMI_RT_R_TX_P2 RVH1 1 RS@ 2 0_0402_5% HDMI_RT_TX_P2
HDMI_DCIN_EN 15 VDDRX12 OUT_D2p 22 HDMI_RT_R_TX_N2 RVH2 1 RS@ 2 0_0402_5% HDMI_RT_TX_N2 HDMI_RT_TX_P0 5 6 HDMI_RT_TX_P0
18 VDDTX12 OUT_D2n
VDDTX12
1
37 20 HDMI_RT_R_TX_P1 RVH3 1 RS@ 2 0_0402_5% HDMI_RT_TX_P1

POWERSWITCH OUT_D1p 19 HDMI_RT_R_TX_N1 RVH4 1 RS@ 2 0_0402_5% HDMI_RT_TX_N1
RVH8 CVH1 1 2 0.1U_0201_10V6K HDMI_TX_P2 38 OUT_D1n 3
<6> SOC_DP2_P0 HDMI_TX_N2 IN_D2p HDMI_RT_R_TX_P0 HDMI_RT_TX_P0
2 4.7K_0402_5% CVH2 1 2 0.1U_0201_10V6K 39 17 RVH5 1 RS@ 2 0_0402_5% 2
<6> SOC_DP2_N0 IN_D2n OUT_D0p HDMI_RT_R_TX_N0 HDMI_RT_TX_N0
16 RVH6 1 RS@ 2 0_0402_5% TVW DF1004AD0_DFN9
2
CVH3 1 2 0.1U_0201_10V6K HDMI_TX_P1 41 OUT_D0n

<6> SOC_DP2_P1
CVH4 1 2 0.1U_0201_10V6K HDMI_TX_N1 42 IN_D1p 14 HDMI_RT_R_CLKP DVT SC300003Z00
<6> SOC_DP2_N1 IN_D1n OUT_CLKp HDMI_RT_R_CLKN
13
Receiver equalization setting(Internal 150K PD) CVH5 1 2 0.1U_0201_10V6K HDMI_TX_P0 44 OUT_CLKn Change to R-short 2021/9/28 DVH3 @ESD@
(*) L: programmable EQ for channel loss up to 5.3dB <6> SOC_DP2_P2 HDMI_TX_N0 IN_D0p SOC_DP2_CTRL_DATA_R RVH23 HDMI_RT_TX_N1 HDMI_RT_TX_N1
CVH6 1 2 0.1U_0201_10V6K 45 33 1 @ 2 0_0402_5% 1 9
( ) H: programmable EQ for channel loss up to 10dB <6> SOC_DP2_N2 IN_D0n SDA_SRC/AUXN SOC_DP2_CTRL_CLK_R SOC_DP2_CTRL_DATA <6>
34 RVH24 1 @ 2 0_0402_5%
( ) M: programmable EQ for channel loss up to 14dB HDMI_CLKP SCL_SRC/AUXP HDMI_CTRL_DAT SOC_DP2_CTRL_CLK <6> HDMI_RT_TX_P1 HDMI_RT_TX_P1
CVH7 1 2 0.1U_0201_10V6K 47 8 2 8
<6> SOC_DP2_P3 HDMI_CLKN IN_CLKp SDA_SNK HDMI_CTRL_CLK
CVH8 1 2 0.1U_0201_10V6K 48 7
+3VS <6> SOC_DP2_N3 IN_CLKn SCL_SNK HDMI_RT_TX_N2 HDMI_RT_TX_N2
4 7
DVT
HDMI_DCIN_EN 3 40 HDMI_HPD RVH22 1 RS@ 2 0_0402_5% HDMI_RT_TX_P2 5 6 HDMI_RT_TX_P2
DCIN_ENB HPD_SRC SOC_DP2_HPD <6>
1
HDMI_EQ 5 21 HDMI_RT_HPD
@ HDMI_I2C_ADDR 31 EQ HPD_SNK HPD_SNK internal PD 150K ohm
RVH11 I2C_ADDR
4.7K_0402_5% 10 3
25 RSV1 32 HDMI_ID
2
HDMI_EQ 26 NC HDMI_ID 9 TVW DF1004AD0_DFN9

RSV2 HDMI_CEC 12
Placed close to REXT pin. CEC_EN SC300003Z00
1
@ RVH7 1 2 4.99K_0402_1% 36 29 TP@ T327

RVH12 4 REXT CSCL 28 TP@
PDB CSDA T328 +HDMI_5V_OUT
4.7K_0402_5% RESET# 35
Enhance Vswing HDMI_PRE 27 RESETB
2
2 PRE 49
TESTMODEB EPAD HDMI_CTRL_DAT RVH17 1 2 2.2K_0402_5%
HDMI_CTRL_CLK RVH18 1 2 2.2K_0402_5%
I2C Slave Address selection; Internal pull down;3.3V I/O
3 L: Default, Slave address 0x10-0x2F. PS8409AQFN48GTR2-A0_QFN48_6X6 3
H: Alternative salve address 0x90-0x9F, 0xD0-0xDF. SA0000AC340
S IC PS8409AQFN48GTR2-A2 QFN48P REPEATER
+3VS
Change to SA0000AC340 2021/9/8
+HDMI_5V_OUT HDMI connector
1
@ JHDMI1
RVH13 HDMI_RT_HPD 19
4.7K_0402_5% +3VS 18 HP_DET
17 +5V
2
HDMI_I2C_ADDR HDMI_CTRL_DAT 16 DDC/CEC_GND

HDMI_CTRL_CLK 15 SDA
Output pre-emphasis setting;Internal pull-up 3.3V I/O 14 SCL
L: Pre-emphasis =2.5dB 13 Reserved
H: Default, No Pre-emphasis Pull-high on SOC side (+3VS) HDMI_RT_CLKN 12 CEC 20
11 CK- GND 21
HDMI_PRE HDMI_RT_CLKP 10 CK_shield GND 22
CK+ GND
5
HDMI_RT_TX_N0 9 23
D0- GND
1
8
G
SOC_DP2_CTRL_CLK 4 3 HDMI_CTRL_CLK HDMI_RT_TX_P0 7 D0_shield

HDMI_RT_TX_N1 6 D0+
S
@ RVH14 QVH2A
D1-
2
4.7K_0402_5% PJT138KA_SOT363-6 5
+3VS HDMI_RT_TX_P1 4 D1_shield
G
2
SOC_DP2_CTRL_DATA 1 6 HDMI_CTRL_DAT HDMI_RT_TX_N2 3 D1+

2 D2-
S
QVH2B
D2_shield
2
PJT138KA_SOT363-6 HDMI_RT_TX_P2 1
HDMI_ID enable ; Internal pull down;3.3V I/O RVH16 D2+
L: Default, HDMI ID enable add external DDC circuit From Vendor Request 2021/8/16 YUQIU_HD050-F19M0BR-B
4 H: HDMI ID disable 10K_0402_5% 4
DC23300YP00
1
+3VS RESET# CONN@

Change symbol 09/30 DVT
1
1
CVH24
@ 1U_0201_6.3V6M Security Classification Compal Secret Data Compal Electronics, Inc.
RVH15 2021/08/05 2022/08/05 Title
4.7K_0402_5% 2 Issued Date Deciphered Date
HDMI CONN.
2
HDMI_ID THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1A
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

DP CONN (TUSB546)
A B C D E
1 2 3 4 5
MB_USB3.1 TypeC Conn. (Port 0/ Re-Timer Master) +3VALW
+3VS_RETIMER
1U_0201_6.3V6M
+3VALW 1
CT1
UT1 1 TypeC@
1 CT2
@ 5 VOUT 4.7U_0402_6.3V6M
RT4 1 @ 2 10K_0201_5% SOC_DG_BB_FORCE_PWR_R 2 VIN
RT5 1 TypeC@ 2 10K_0201_5% 2 2
4 GND
DVT EN
RT6 1 TypeC@ 2 100_0201_1% DG0_TEST_PWR_GOOD
RT12 1 RS@ 2 0_0201_5% TBT_RETIMER_0_LS_EN_R 3
DG0_POC_GPIO5 <43> TBT_RETIMER_0_LS_EN /OC +3VS_RETIMER
RT7 1 TypeC@ 2 10K_0201_5%
RT13 1 @ 2 0_0201_5% High active SY6288C20AAC_SOT23-5
<12> SOC_SLP_DS0#
UT2A EN_VL:1.1V TypeC@ RT14 1 @ 2 10K_0201_5%
DVT
DG0_SPI_DI C6 C9 TBT_I2C_SCL RT8 1 RS@ 2 0_0201_5% +3VS_RETIMER_0 Tolerance (+ 5%/-7.5%):
A +3VS_RETIMER DG0_SPI_DO EE_DI I2C_SCL TBT_I2C_SDA I2C3_PD_R_CLK <43> A
B4 E7 RT9 1 RS@ 2 0_0201_5% Burnside Bridge power pins which connected to +3VS_RETIMER_0 should I (Max) : 0.37 A(+3V_PRIM)
FLASH
Change DG0_FLSH_SHARE_EN to PD PVT DG0_SPI_CS# B6 EE_DO I2C_SDA A10 TBT_I2C_INT# RT84 1 RS@ 2 0_0201_5%
I2C3_PD_R_DAT
I2C3_PD_R_INT#
<43>
<43>
I2C to PD,SOC
be 3.465v maximum and 3.07v minimum for normal operation. RDS(Typ) : 70 mohm
DG0_SPI_CLK_R 1 RS@ 2 DG0_SPI_CLK C7 EE_CS# I2C_INT B10 SOC_DG_BB_FORCE_PWR_R
Delete DG0_FLSH_MSTR_SLV 1/7 EE_CLK FORCE_PWR DG0_FLASH_BUSY# SOC_DG_BB_FORCE_PWR_R <12,43> +3VS_RETIMER_0 ripple: 40mVp-p V drop : 0.026 V
RT209 0_0201_5% A9
POC GPIO
RT11 1 @ 2 10K_0201_5% DG0_FLSH_SHARE_EN EMC Suggestion
DG0_JTAG_TDI
MISC & FLASH_BUSY#
POC_GPIO_5
POC_GPIO_6
B9
A8
DG0_POC_GPIO5
DG0_POC_GPIO6
TBT_RETIMER_RESET#_R
RT1 Change to @ 20201130 intel review
and remove connect to SOC GPIO
RT10 1 TypeC@ 2 10K_0201_5%
DG0_JTAG_TMS
DG0_JTAG_TCK
A3
C3
B5
TDI
TMS
DEBUG PERST#
SMBUS_SCL
B8
A7
B7
RT_SML0CLK
RT_SML0DATA
RT1 2 @ 1 0_0201_5%
RT299 1 VPRO@ 2 0_0201_5%
RT298 1 VPRO@ 2 0_0201_5%
PLT_RST_R# <11,33,51,52,66,69>
SOC_SML0CLK <9>
Reserved v-pro only
RT42 pop PH change to +3VS_Retimer 20201130 Intel review +3VS_RETIMER
JTAG
DG0_FLSH_MSTR_SLV DG0_JTAG_TDO TCK SMBUS_SDA DG0_FLSH_SHARE_EN SOC_SML0DATA <9> TBT_RETIMER_RESET#_R
RT15 1 @ 2 10K_0201_5% C5 A4 & PU at CPU side RT42 2 1 10K_0201_5%
RT348 1 @ 2 10K_0201_5% TDO POC_GPIO_10 A5 DG0_FLSH_MSTR_SLV RT43 2 @ 1 10K_0201_5%
RT17 1 @ 2 10K_0201_5% DG0_POC_GPIO12 POC_GPIO_11 A6 DG0_POC_GPIO12
RT349 1 @ 2 10K_0201_5% POC_GPIO_12 L3
1AN0_THERMDA M11 NC_L3
DG0_SPI_CLK_R T143 TP@ THERMDA
CT131 2 1 10P_0201_50V8J
M12
@ B2 TEST_EDM RT_SML0CLK RT94 2 1 100K_0201_5%
EMC Suggestion FUSE_VQPS_64 L11 DG0_RST# RT_SML0DATA RT95 2 1 100K_0201_5%
+3VALW RESET# DG0_RST# <43>
A11
A12 MONDC L9 DG0_XTAL_25M_XI
Follow E team design PD 100K
DEBUG
Main
RT19 1 TypeC@ 2 10K_0201_5% DG0_FLASH_BUSY# L12 NC_A12 XTAL_25_IN M9 DG0_XTAL_25M_XO
MONDC_SVR XTAL_25_OUT
Delete Port1 Share Rom Part 1/7 DG0_TEST_PWR_GOOD B3 L5 AN0_RSENSE
B11 TEST_PWR_GOOD
TEST_EN
RSENSE
RBIAS
L4 AN0_RBIAS 1 2 SMBUS:
RT21 TypeC@
A1 4.75K_0201_0.5%
No support Vpro
A2 ATEST_P
ATEST_N
Intel recommended PD 100K
DG1_RST#:
For PD based systems, DG1_RST# should be output from PD.
For TCPC based systems, DG1_RST# should be output from SOC/EC. BURNSIDE-BRIDGE_BGA105
DG1_BB_FORCE_PWR: @
Connect to EC/PCH for FW update NOTE:
'0' - by default Re-Timer with TBT , AC Caps should be use 0201/25V package.
'1' - for debug only Re-Timer without TBT , AC Caps can be use 0402/25V package.
DG1_FLASH_BUSY#: For non-PD support 25V rating is no must.
UT2D
If Flash sharing is being used, PU should be used.
If Flash sharing isn't being used, PD should be used.
DG1_FLSH_SHARE_EN: <6> TBT_0_TTX_DRX_P0 CT11

TypeC@
1 2 0.22U_0201_10V6M TBT_0_TTX_DRX_P0_C J1
TBT PORTS J12 TBT_0_TRX_RD_DTX_P0 RT27 1 TypeC@ 2 2.2_0201_1% TBT_0_TRX_R_DTX_P0 CT12 1 2 0.33U_0201_25V6K TypeC@
TBT_0_TRX_C_DTX_P0 <43>
'0' - Flash isn't shared. 1 Flash per Re-timer CT13 1 2 0.22U_0201_10V6M TBT_0_TTX_DRX_N0_C J2 ASSRXp1 BSSRXp1 J11 TBT_0_TRX_RD_DTX_N0 RT28 1 TypeC@ 2 2.2_0201_1% TBT_0_TRX_R_DTX_N0 CT14 1 2 0.33U_0201_25V6K TypeC@
<6> TBT_0_TTX_DRX_N0 ASSRXn1 BSSRXn1 TBT_0_TRX_C_DTX_N0 <43>
'1' - Flash is shared between 2 Re-timers TypeC@ TypeC@
Port B - TypeC Side

CT15 1 2 0.22U_0201_10V6M TBT_0_TRX_DTX_P0_C G1 G12 TBT_0_TTX_RD_DRX_P0 RT29 1 TypeC@ 2 2.2_0201_1% TBT_0_TTX_R_DRX_P0 CT16 1 2 0.22U_0201_25V6K TypeC@
Port A - Host Side

B DG1_FLSH_MSTR_SLV: <6> TBT_0_TRX_DTX_P0 ASSTXp1 BSSTXp1 TBT_0_TTX_C_DRX_P0 <43> B
CT17 1 2 0.22U_0201_10V6M TBT_0_TRX_DTX_N0_C G2 G11 TBT_0_TTX_RD_DRX_N0 RT30 1 TypeC@ 2 2.2_0201_1% TBT_0_TTX_R_DRX_N0 CT18 1 2 0.22U_0201_25V6K TypeC@
'0' - Set Re-timer to be Slave on shared flash SPI I/F. <6> TBT_0_TRX_DTX_N0 ASSTXn1 BSSTXn1 TBT_0_TTX_C_DRX_N0 <43>
'1' - Set Re-timer to be Master on shared flash SPI I/F TypeC@ TypeC@
CT3 1 2 0.22U_0201_10V6M TBT_0_TTX_DRX_P1_C C1 C12 TBT_0_TRX_RD_DTX_P1 RT23 1 TypeC@ 2 2.2_0201_1% TBT_0_TRX_R_DTX_P1 CT4 1 2 0.33U_0201_25V6K TypeC@
<6> TBT_0_TTX_DRX_P1 ASSRXp2 BSSRXp2 TBT_0_TRX_C_DTX_P1 <43>
<6> TBT_0_TTX_DRX_N1 CT5 1 2 0.22U_0201_10V6M TBT_0_TTX_DRX_N1_C C2 C11 TBT_0_TRX_RD_DTX_N1 RT24 1 TypeC@ 2 2.2_0201_1% TBT_0_TRX_R_DTX_N1 CT6 1 2 0.33U_0201_25V6K TypeC@
ASSRXn2 BSSRXn2 TBT_0_TRX_C_DTX_N1 <43>
TypeC@ TypeC@
CT7 1 2 0.22U_0201_10V6M TBT_0_TRX_DTX_P1_C E1 E12 TBT_0_TTX_RD_DRX_P1 RT25 1 TypeC@ 2 2.2_0201_1% TBT_0_TTX_R_DRX_P1 CT8 1 2 0.22U_0201_25V6K TypeC@
<6> TBT_0_TRX_DTX_P1 ASSTXp2 BSSTXp2 TBT_0_TTX_C_DRX_P1 <43>
CT9 1 2 0.22U_0201_10V6M TBT_0_TRX_DTX_N1_C E2 E11 TBT_0_TTX_RD_DRX_N1 RT26 1 TypeC@ 2 2.2_0201_1% TBT_0_TTX_R_DRX_N1 CT10 1 2 0.22U_0201_25V6K TypeC@
<6> TBT_0_TRX_DTX_N1 ASSTXn2 BSSTXn2 TBT_0_TTX_C_DRX_N1 <43>
+3VS TypeC@
M7 M10 TBT_0_SBU1 RT31 1 RS@ 2 0_0201_5% TBT_0_SBU1_R
DG0_POC_GPIO6 <6> TBT_0_LSX_TX PA_LSTX_SBU1 BSBU1 TBT_0_SBU1_R <43>
RT32 1 TypeC@ 2 10K_0201_5% L7 L10 TBT_0_SBU2 RT33 1 RS@ 2 0_0201_5% TBT_0_SBU2_R
220K_0201_5%
220K_0201_5%
220K_0201_5%
220K_0201_5%
220K_0201_5%
220K_0201_5%
220K_0201_5%
220K_0201_5%
<6> TBT_0_LSX_RX PA_LSRX_SBU2 BSBU2 TBT_0_SBU2_R <43>
2TypeC@ 1
2TypeC@ 1
2TypeC@ 1
2TypeC@ 1
2TypeC@ 1
2TypeC@ 1
2TypeC@ 1
2TypeC@ 1
RT34
RT35
RT36
RT37
RT38
RT39
RT40
RT41
L8 DVT
<6> TBT_0_DP_AUXP_R PA_AUX_P
M8
<6> TBT_0_DP_AUXN_R PA_AUX_N
TBT_0_TTX_R_DRX_P0 1 2 TBT_0_TTX_R_DRX_P1 1 2
1
1
DT1 BL_ESD@ DT2 BL_ESD@
RT44 RT45 BURNSIDE-BRIDGE_BGA105
1M_0201_5% @ @ 1M_0201_5% @
PESD5V0H1BSF_SOD962-2-2 PESD5V0H1BSF_SOD962-2-2
2
AC coupling caps and PU/PD on AUX lines are TBT_0_TTX_R_DRX_N0 1 2 TBT_0_TTX_R_DRX_N1 1 2

implemented inside Burnside Bridge DT3 BL_ESD@ DT4 BL_ESD@
UT2C
B1 F12
B12 VSS_ANA VSS_ANA G7 TBT_0_TRX_R_DTX_P0 1 2 TBT_0_TRX_R_DTX_P1 1 2
D1 VSS_ANA VSS_ANA H1 DT5 BL_ESD@ DT6 BL_ESD@
D2 VSS_ANA VSS_ANA H2
D11 VSS_ANA VSS_ANA H11
D12
F1
VSS_ANA
VSS_ANA GND VSS_ANA
VSS_ANA
H12
J9
F2 VSS_ANA VSS_ANA K1 TBT_0_TRX_R_DTX_N0 1 2 TBT_0_TRX_R_DTX_N1 1 2

F7 VSS_ANA VSS_ANA K2 DT7 BL_ESD@ DT8 BL_ESD@
20200811
F9 VSS_ANA VSS_ANA K11 - DT1~DT8 change to SC40000H800 for ESD
F11 VSS_ANA VSS_ANA K12
VSS_ANA VSS_ANA PESD5V0H1BSF_SOD962-2-2 PESD5V0H1BSF_SOD962-2-2
G5
VSS F5
VSS F3
VSS Follow Burmside Bridge Rev0.84
BURNSIDE-BRIDGE_BGA105
change J5 pin to NC
C
@ Power Supply Decoupling of Type-C Port0 C
+3VO_TBT_0_ANA UT2B +3VS_RETIMER +0.9VO_TBT_0_SVR_IND +0.9VO_TBT_0_SVR
+3VO_TBT_0_LC LT1 +0.9VO_TBT_0_LVR +0.9VO_TBT_0_LC

L2 E6 0.9V@850mA
VCC3P3_ANA VCC3P3_SX 1 2
+0.9VO_TBT_0_SVR E5 M4
VCC3P3_LC VCC3P3_SVR +3VS_RETIMER
2.2U_0201_6.3V6M
2.2U_0201_6.3V6M
2.2U_0201_6.3V6M
2.2U_0201_6.3V6M
2.2U_0201_6.3V6M
2.2U_0201_6.3V6M
10U_0402_6.3V6M
2.2U_0201_6.3V6M
2.2U_0201_6.3V6M
M5 0.68UH_DFE252012P-R68M-P2_3.5A_20%
VCC3P3_SVR
47U_0603_6.3V6M
CT235 TypeC@
47U_0603_6.3V6M
CT19 TypeC@
18P_0201_25V8J
F6 J5 TypeC@ 1 2 2 2 2 2 2 1 2 2
VCC0P9_SVR_ANA VCC3P3_SVR
1
+0.9VO_TBT_0_SVR_IND
C55
CT20 TypeC@
CT21 @
CT22 TypeC@
CT23 @
CT24 TypeC@
CT25 @
CT27 TypeC@
CT28 TypeC@
G6 J7
25M XTAL (Type-C Port0)
Pin F6
Pin G6
Pin E3
Pin G3
Pin E9
Pin G9
Pin L6
Pin J3
VCC0P9_SVR_ANA VCC3P3A
CT26TypeC@
Power
E3 L1
2
VCC0P9_SVR SVR_IND 2 1 1 1 1 1 1 2 1 1
TypeC@
G3 M1
VCC0P9_SVR SVR_IND
DG0_XTAL_25M_XI E9 M2
+0.9VO_TBT_0_LC G9 VCC0P9_SVR_PB_ANA SVR_VSS M3
VCC0P9_SVR_PB_ANA SVR_VSS
YT1 TypeC@ DG0_XTAL_25M_XO +0.9VO_TBT_0_LVR J3
25MHZ 10PF EXS00A-CG03482 VCC0P9_LC +3VO_TBT_0_LC +3VO_TBT_0_ANA
L6 +3VS_RETIMER
1 3 Must use Metal shielded crystal M6 VCC0P9_LVR J6 NC_J6
1 3 VCC0P9_LVR_SENSE NC_J6
2.2U_0201_6.3V6M
2.2U_0201_6.3V6M
for better noise immunity.
1
GND GND
18P_0201_25V8J
18P_0201_25V8J
Suggest adding GND shield Share Same GND plane 2 2
Pin E5
Pin L2
CT29 TypeC@
CT30 TypeC@
BURNSIDE-BRIDGE_BGA105 @ @
C56 TypeC@
C57 TypeC@
2 4 across Crystal and 18pF caps
2.2U_0201_6.3V6M
2.2U_0201_6.3V6M
1 1 for better RFI. RT363
and connect to M2 & M3
47U_0603_6.3V6M
47U_0603_6.3V6M
0_0201_5% 2 2
1
1 1
pins (SVR_VSS) of BB
CT560 TypeC@
CT31 TypeC@
CT32 TypeC@
CT33 TypeC@
UT2
Pin M4
Pin M4
Pin J5
Pin E6
2
2 2
2
BURNSIDE-BRIDGE_BGA105 1 1
TypeC@
SA0000CAH60
20200929A
- Pin "NC_J6" need NC (TBT SCH check list Rev1p1)
Add CT560 for intel review
(in parallel of CT31)1130
Remove RT60/CT35/CT530 intel review 20201130
+3VALW
JTAG (Type-C Port0) SPI ROM (Type-C Port0) +3VS_RETIMER
3.3V@50mA
1 TypeC@
+3VO_TBT_0_LC
2.2U_0201_6.3V6M
CT34
2.2U_0402_6.3V6M 2
CT36 TypeC@
Pin J7
Follow Burmside Bridge
D 2 All 0201 decoupling caps should be places Ref Schematic D
2
2
TypeC@ RT56
TypeC@ RT57
TypeC@ RT58
TypeC@ RT59
UT3
as close as possible to
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
DG0_SPI_CS# RT62 1 RS@ 2 0_0201_5% DG0_SPI_CS#_R 1 8 1

DG0_SPI_DO RS@ 2 0_0201_5% DG0_SPI_DO_R CS# VCC DG0_SPI_HOLD#
RT63 1
DVT DG0_SPI_WP#
2
3 DO(IO1) HOLD#(IO3)
7
6 DG0_SPI_CLK_R1 RT64 1 RS@ 2 0_0201_5% DG0_SPI_CLK_R the re-timer power pins Place holder for RC filter to reduce
ripple to VCC3v3A pin
4 WP#(IO2) CLK 5 DG0_SPI_DI_R RT65 1 RS@ 2 0_0201_5% DG0_SPI_DI
1
GND DI(IO0)
DVT
W25Q80DVSSIG_SO8
DG0_JTAG_TDI +3VALW
TypeC@
DG0_JTAG_TMS
DG0_JTAG_TCK
DG0_JTAG_TDO DG0_SPI_CS# RT52 1 TypeC@ 2 2.2K_0201_5%
DG0_SPI_DO RT53 1 TypeC@ 2 2.2K_0201_5%
remove connector 2/14 DG0_SPI_WP# RT54 1 TypeC@ 2 3.3K_0201_5% Security Classification Compal Secret Data Compal Electronics, Inc.
DG0_SPI_HOLD# RT55 1 TypeC@ 2 3.3K_0201_5% 2021/08/05 2022/08/05 Title
DG0_SPI_CLK_R1 1 XEMI@ 2
XEMI@
TBT_TYPE-C_Port0 (1/2)
2 1 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
RT214 33_0201_5% CT229 22P_0201_50V8J 1A
1 2 3 4 5
5 4 3 2 1
+20V_TBT_0_VBUS_R +20V_TBT_0_VBUS_R Slave Adderss setting +3V_TBTA_PDLDO

VBUS Discharge Local PWR Voltage Monitor VBUS Voltage/current Monitor +3V_TBTA_PDLDO +3VLP
1
+5V_IN_PWR
1
RT69 EC_PD_INT# RT1160 2 @ 1 10K_0201_5%
4.7K_0805_5% RT1166 PD@ @
82P_0402_50V8J
10U_0402_6.3V6M
0.1U_0201_25V6K
PD@ 200K_0402_1% Slave Addr Ra 5% Rb 5% RT22
BL_EMC@
BL_EMC@
BL_EMC@
RT1168 addr0:0xC4 NC 10K <0.2V 10K_0402_5% 1 1 1
CT52
CT53
CT54
200K_0402_1% PD@
2
VMON addr1:0xC6 75K 10K >=0.2V&&<0.6V ADDR_CFG Move SOC_PD_INT# to CPU side
addr2:0xC8 33K 10K >=0.6V&&<1.0V
2
1
1
D LOC_PWR_MON 2 2 2
VBUS_DSCHG 2 QT1 RT1167 PD@ addr3:0xCa 10K 10K >=1.0V RT1165 PD@
1
G L2N7002WT1G_SC-70-3 10K_0402_1% 10K_0402_1%
S PD@ RT1169 It's is used for SMBUS slave addr0/1/2/3 20200811
3
10K_0402_1% PD@ setting during power on initialization. RF BOM - Remove TYPEC_IN_STATUS# (RT1159)
2
2
Symbol use RTS5457U, Change to SA0000DUO10 for Aspire use EMC Suggestion
+20V_TBT_0_VBUS +20V_TBT_0_VBUS_R
UT14 SA0000DUO10 +TBT_0_PD_CC1
2
D RTS5452E-GR QFN 32P TYPE-C PD CTRL PD@ LT5 BL_EMC@ D
RT1170 POP: Disable Dead battery function PD@ CT37 5A_Z80_0805_2P
ADDR_CFG 20 19 RT1170 1 @ 2 0_0402_5% 220P_0201_25V7K 1 2
+3V_TBTA_PDLDO ADDR_CFG /MGPIO11 DB_DIS 1
LOC_PWR_MON 23 1 2
MGPIO2 RT3986 1 @ 2 4.7K_0201_5% LOC_PWR_MON/MGPIO10 LT6 BL_EMC@
+TBT_0_PD_CC1
1000P_0201_50V7K
CT132 BL_EMC@
CT221 BL_EMC@
MGPIO3 RT3987 1 @ 2 4.7K_0201_5% VMON 21 16 5A_Z80_0805_2P
VMON/MGPIO9 PD CU CC1 +TBT_0_PD_CC2
100P_0201_50V8J
100P_0201_50V8J
CT223 BL_EMC@
CT222 BL_EMC@
18
0.1U_0201_25V6K
MGPIO6 RT3988 1 @ 2 4.7K_0201_5% MGPIO8 22 CC2 +TBT_0_PD_CC2
IMON/MGPIO8 2 1 1 1 1
MGPIO7 RT3989 1 @ 2 4.7K_0201_5%
MGPIO8 RT3990 1 @ 2 4.7K_0402_5% PD@ CT38
220P_0201_25V7K
RT1183 0_0402_5%1 @ 2 PD_USB1_SRC_HI_ILIM_R_PD 8 10 MGPIO6 1 2 2 2 2
<44,58> PD_USB1_SRC_HI_ILIM SOC_DG_BB_FORCE_PWR_R_PD AUX_P/ MGPIO4 SBU1/MGPIO6
RT1185 0_0402_5%1 @ 2 9 11 MGPIO7
<12,42> SOC_DG_BB_FORCE_PWR_R AUX_N/ MGPIO5 AUX MUX SBU2/MGPIO7
MGPIO2 RT3994 1 @ 2 4.7K_0201_5% RT104 0_0201_5% 2 @ 1 PD_R_PROCHOT# 32
MGPIO3 RT3995 1 @ 2 4.7K_0201_5% <7,17> VCCIN_AUX_CORE_ALERT#_R HPD/GPIO3
need check TI (ref sch 330p)
MGPIO6 RT3996 1 @ 2 4.7K_0201_5%
MGPIO7 RT3997 1 @ 2 4.7K_0201_5%
MGPIO8 RT3998 1 @ 2 4.7K_0402_5% EC_I2C_3_SCL
MGPIO2 12 14 RT4002
H_DP/MGPIO2 USB2.0 SWITCH C_DP/MGPIO0 TYPE-C_20V_VIN_EN <83>
1
MGPIO3 13 15 VBUS_DSCHG EC_I2C_3_SDA 1 @ 2
H_DM/MGPIO3 C_DM/MGPIO1 RT1171 0_0402_5%
PD@ 100K_0402_5%
+3V_TBTA_PDLDO RT4003
EC_PD_INT# 1 @ 2
2
0_0402_5%
4.7K_0402_5% 2 PD@ 1 RT1149 EC_I2C_3_SCL I2C1(Slave) to EC (0x62) EC_I2C_3_SCL 3

EC BBR 4 I2C3_PD_R_CLK_R
EC_I2C_3_SDA <58> EC_I2C_3_SCL EC_I2C_3_SDA SMBUS1_SCL/GPIO5 I2C_M_SCL/GPIO13 I2C3_PD_R_DAT_R
4.7K_0402_5% 2 PD@ 1 RT1150 20200722 30 5 I2C3(Master) to BB (0x56)
10K_0201_5% 2 PD@ 1 RT1151 EC_PD_INT#
- Need confirm with EC
<58> EC_I2C_3_SDA
<58> EC_PD_INT#
EC_PD_INT# 31 SMBUS1_SDA/GPIO6
SMBUS1_INT/GPIO4
I2C_M_SDA/GPIO14
I2C_M_INT/GPIO8
29 I2C3_PD_R_INT#_R Reserve for debug use
4.7K_0402_5% 2 PD@ 1 RT1152 PD1_I2C_2_SCL DG0_RST#_R 7

PCH 1 PD1_I2C_2_SCL
4.7K_0402_5% 2 PD@ 1 RT1153 PD1_I2C_2_SDA EN_USB1_5V_OUT# 27 SMBUS2_SCL/GPIO9
SMBUS2_SDA/GPIO10
GPIOs I2C_S_SCL/GPIO11
I2C_S_SDA/GPIO12
2 PD1_I2C_2_SDA
I2C2(Slave) to PCH (0x38) Dead Battery circuit
10K_0201_5% 2 PD@ 1 RT1154 PD1_INT#_R <44> EN_USB1_5V_OUT# TBT_RETIMER_0_LS_EN 6 28 PD1_INT#_R
<42> TBT_RETIMER_0_LS_EN SMBUS2_INT/GPIO7 I2C_S_INT/GPIO21
For BBR leakage 2021/11/10 DT26
TypeC@ 2 1
4.7K_0402_5% 1 PD@ 2 RT96 I2C3_PD_R_CLK_R +5V_PD_VIN
4.7K_0402_5% 1 PD@ 2 RT97 I2C3_PD_R_DAT_R RB751S-40_SOD523-2 +5VLP PVT
10K_0201_5% 2 PD@ 1 RT98 I2C3_PD_R_INT#_R 24
REXT
Power RT1180
2 @ 1 RT105 DG0_RST#_R 1 RS@ 2 0_0402_5%
1
<42> DG0_RST# 0_0201_5% +5VALW
20200806 K
VCONN_IN
C RT1164 33 RT1178 C
- INT# pull up from 2.2k to 10k ohm
LDO_3V3
6.2K_0402_1% PD@ EPAD 1 @ 2 0_0402_5% +5V_IN_PWR
+5V_PD_VIN
5V_IN
DT23
2
2 1
+3V_TBTA_PDLDO DB@
17
25
26
+5VLP +5VALW +20V_TBT_0_VBUS_R +PWR_LDO RB751S-40_SOD523-2
UT7 DB@ DT15

0_0201_5% 2 RS@ 1 RT108 PD_R_PROCHOT# PVT 1 5 2 1
VCC OUT
10U_0603_25V6M
PVT RT300 1 RS@ 2 0_0402_5% 1 1 DB@
1
+5V_IN_PWR CT47 CT564 RT375 2 RB751S-40_SOD523-2
DG0_RST#_R GND
CT145
10K_0201_5% 2 PD@ 1 RT1161 0.1U_0201_10V6K 4.7U_0402_6.3V6M 47K_0402_5% DB@
RT1182 1 @ 2 0_0402_5% PD@ PD@ PD@ 3 4 DB_PWR_EN
2
100K_0201_5% 2 PD@ 1 RT1184 TBT_RETIMER_0_LS_EN 2 2 NC EN
1
2
CT46 1 1
10U_0402_6.3V6M PD@ CT535 CT534 RT9069-50GB_SOT23-5
0.1U_0201_10V6K 10U_0402_6.3V6M SA00008FS00
2 PD@ PD@ +3VS_RETIMER PVT 1 RS@ 2
+3VS_RETIMER 2 2 RT410 0_0402_5%
+3VALW
+3VS_RETIMER +5VALW RT400 1 2 75K_0201_5%
1
10K_0201_5% 2 @ 1 RT1131 DG0_RST#_R @ @ DB@
1
RT210 RT211 D
2.2K_0402_5% 2.2K_0402_5% RT401 1 2 2 QT18
2
75K_0201_5% DB@ G
G
L2N7002WT1G_SC-70-3
+3VS_RETIMER For BBR leakage 2021/11/17 PD@ QT17A S DB@
1
3
2
100K_0201_5%
G
1U_0201_6.3V6M
2N7002KDW_SOT363-6 @
SPOK_5V RT402
CT566
1 @ 2
DG0_RST# SOC_SML1DATA PD1_I2C_2_SDA I2C3_PD_R_DAT I2C3_PD_R_DAT_R <11,58,87> SPOK_5V
100K_0201_5% 2 TypeC@ 1 RT450 1 6 3 1 0_0201_5% RT403 DB@
S
<9> SOC_SML1DATA <42> I2C3_PD_R_DAT 2

D
DB@
D
5
QT13 5V_EN RT4004 1 @ 2

G
<87> 5V_EN
2
PD@ L2N7002WT1G_SC-70-3 1 RS@ 2 0_0201_5%
QT17B RT1187
2
G
2N7002KDW_SOT363-6 0_0402_5% PVT
SOC_SML1CLK 4 3 PD1_I2C_2_SCL @
S
<9> SOC_SML1CLK I2C3_PD_R_CLK I2C3_PD_R_CLK_R

D
I2C2(Slave) to PCH 3 1
<42> I2C3_PD_R_CLK
D
I2C3(Master) to BB QT14
L2N7002WT1G_SC-70-3 1 2 PVT
+3VALW +3VS_RETIMER RS@ RT1186
0_0402_5%
1
@ +5V_IN_PWR +3V_TBTA_PDLDO
2
DT10
G
PD@ RT212 +3VS_RETIMER BL_EMC@

2.2K_0402_5% TBT_0_SBU1_R_SW 1 1 10 9 TBT_0_SBU1_R_SW
SOC_PD_INT# 3 1 PD1_INT#_R
<11> SOC_PD_INT#
2
+TBT_0_PD_CC1_SW 2 2 +TBT_0_PD_CC1_SW
G
QT5 RT1179 1 2 0_0402_5% 9 8
S
2
B @ B
L2N7002WT1G_SC-70-3 I2C3_PD_R_INT# 3 1 I2C3_PD_R_INT#_R @ TBT_0_SBU2_R_SW 4 4 7 7 TBT_0_SBU2_R_SW
<42> I2C3_PD_R_INT#
D
QT15 Note: +TBT_0_PD_CC2_SW 5 5 6 6 +TBT_0_PD_CC2_SW
L2N7002WT1G_SC-70-3 1 2 1.If the 5V_IN power supply
RS@ RT1188 voltage is fixed 5V or 3 3
0_0402_5% variable
+5VALW PVT 8
CC/SBU OVP +5VALW from 3.3V to 5V. Remove the
0ohm resistor. AZ1045-04F_DFN2510P10E-10-9
2.If the 5V_IN power supply SC300001Y00
voltage is fixed 3.3V, stuff
the 0ohm resistor.
1
RT1174
1
@ 470_0201_5% RT80 +20V_TBT_0_VBUS

1
RT1175 NOVP@ 470_0201_5%

@ 470_0201_5% RT109
2
NOVP@ 470_0201_5%
W = 200 mils
5 2
2
1000P_0201_50V7K
0.01U_0402_25V7K
0.1U_0201_25V6K
2
BL_EMC@
BL_EMC@
BL_EMC@
NOVP@ DT13 0520 Remove EMI 0 ohm

G
1 1 1
2
5
CT61
PJT138KA_SOT363-6 QT10B CEST23NC24VU_SOT23-3

CT59
CT60
QT11A 2N7002KDW_SOT363-6 BL_EMC@ LT2 BL_EMC@

G
+TBT_0_PD_CC1 4 3 +TBT_0_PD_CC1_SW NOVP@ USB20_N2 1 2 USB20_N2_R

G
<13> USB20_N2 1 2
2
TBT_0_SBU1_R TBT_0_SBU1_R_SW 2 2 2
S
@ PJT138KA_SOT363-6 4 3 QT10A
S
1
D
QT11B 2N7002KDW_SOT363-6 JUSBC1

G
+TBT_0_PD_CC2 1 6 +TBT_0_PD_CC2_SW A1 B12 USB20_P2 4 3 USB20_P2_R

TBT_0_SBU2_R TBT_0_SBU2_R_SW GND GND <13> USB20_P2 4 3
1 6
S
@
S
TBT_0_TTX_C_DRX_P0 TBT_0_TRX_C_DTX_P0
D
A2 B11 TBT_0_TRX_C_DTX_P0 <42> DLM0NSN900HY2D_4P

<42> TBT_0_TTX_C_DRX_P0 TBT_0_TTX_C_DRX_N0 SSTXP1 SSRXP1 TBT_0_TRX_C_DTX_N0
A3 B10 TBT_0_TRX_C_DTX_N0 <42> SM070005U00
<42> TBT_0_TTX_C_DRX_N0 SSTXN1 SSRXN1
TypeC@ TypeC@
NOVP@ 0.1U_0201_25V6K 1 2 CT62 A4 B9 CT63 1 2 0.1U_0201_25V6K
+TBT_0_PD_CC1 0_0402_5% 2 1 RT76 +TBT_0_PD_CC1_SW VBUS VBUS
NOVP@ +TBT_0_PD_CC1_SW A5 B8 TBT_0_SBU2_R_SW
+TBT_0_PD_CC2 0_0402_5% 2 1 RT77 +TBT_0_PD_CC2_SW CC1 SBU2
1. non-OVP : Pop QT11 20200904 USB20_P2_R USB20_N2_R
2. OVP : UT5 or QT11 & RT76,RT77 - C62/C63/C64/C65 .33u change to .1u for COST . A6 B7 20200924A
USB20_N2_R A7 DP1 DN2 B6 USB20_P2_R
DN1 DP2 - DT11 USB2 P/N Swap
TBT_0_SBU1_R_SW +TBT_0_PD_CC2_SW DT11
A8 B5 BL_EMC@
SBU1 CC2 USB20_N2_R 1 1 USB20_N2_R
TypeC@ TypeC@ 10 9
0.1U_0201_25V6K 1 2 CT65 A9 B4 CT64 1 2 0.1U_0201_25V6K
VBUS VBUS USB20_P2_R 2 2 USB20_P2_R
9 8
UT5 OVP@ TBT_0_TRX_C_DTX_N1 A10 B3 TBT_0_TTX_C_DRX_N1
<42> TBT_0_TRX_C_DTX_N1 TBT_0_TRX_C_DTX_P1 SSRXN2 SSTXN2 TBT_0_TTX_C_DRX_P1 TBT_0_TTX_C_DRX_N1 <42>
<42> TBT_0_TRX_C_DTX_P1 A11 B2 4 4 7 7
TBT_0_SBU1_R TBT_0_SBU1_R_SW SSRXP2 SSTXP2 TBT_0_TTX_C_DRX_P1 <42>
15 1
System Side
Connector Side
TBT_0_SBU2_R 14 SBU1 C_SBU1 2 TBT_0_SBU2_R_SW A12 B1 5 5

SBU2 C_SBU2 GND GND 6 6
RT4000
A RPD_G11 RS@ A
7 2 0_0402_5% 1 3 3
+3V_TBTA_PDLDO +TBT_0_PD_CC1
+TBT_0_PD_CC2
12
11 CC1
CC2
RPD_G1
C_CC1
C_CC2
4
5
+TBT_0_PD_CC1_SW
+TBT_0_PD_CC2_SW
2
3
GND
GND
GND
Double 8
6 RPD_G21 RS@ 2 TBT_0_SBU1_R 4
0.14mA RPD_G2 RT4001
<42> TBT_0_SBU1_R TBT_0_SBU2_R 5 GND
<42> TBT_0_SBU2_R GND AZ1045-04F_DFN2510P10E-10-9
RT3999 1 OVP@ 2 100K_0402_1% 9 20 PVT 0_0402_5% 6
10 FLT D1 19 GND SC300001Y00
VPWR D2
1
3 17
VBIAS N.C. 16 RT81 RT82 LOTES_AUSB0605-P1
2 1 N.C.
OVP@ OVP@ 8 1M_0201_5% 1M_0201_5% CONN@ SP06000EPA0
CT66 CT67 13 GND TypeC@ TypeC@
1U_0201_6.3V6M 0.1U_0201_25V6K 18 GND 2021/07/15
- Update SYMBOL/Footprint
2
1 2 21 GND
THERMAL_PAD OVP for SBU and VBUS
TPD6S300RUKR_WQFN20_3X3
SA0000E3G10
S IC RT1738AGQW(2) WQFN 20P PROTECTOR
20200901
Compal Secret Data
2021/09/01 Title
Change to SA0000E3G10 due to TI shortage 2021/09/08
TBT_TYPE-C_Port0 (2/2)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L151P
5 4 3 2 1
5 4 3 2 1
MB_USB3.1 TypeC Conn. (Power Path)

- For Realtek 5452E
D D
+5VALW
Change to SGA0000F200
due to SGA00009M00 shortage
C 1 C
+
+3V_TBTA_PDLDO 150U_B2_6.3VM_R35M CT565 +20V_TBT_0_VBUS
SGA0000F200
TypeC@ 2
UT9 TypeC@
6 1
IN OUT
1
47P_0201_50V8J
0.1U_0201_25V6K
RT224 RT223
CT232 @RF@
CT233 @RF@
1 1
1
100K_0201_5% 100K_0201_5% PD_USB1_ILIM 5 2 TypeC@
TypeC@ TypeC@ SET GND CT230
10U_0603_25V6M
2
2
EN_USB1_5V_OUT 4 3 2 2
Initial High EN FLAG
H: Provider 5V OFF G518B1TP1U_TSOT23-6
L: Provider 5V ON S IC SY6861B1ABC SOT23 6P PW R SW
6
D SA0000BDN00 RF Suggestion
EN_USB1_5V_OUT# 2 QT16A
<43> EN_USB1_5V_OUT# G 2N7002KDW _SOT363-6 TypeC@ TypeC@
1
S RT228 RT227 Change to SA0000BDN00
1
4.02K_0402_1% 4.02K_0402_1% symbol use G518B 2021/09/08

TypeC@
2
Res setting follow PWR IC 2021/09/08
B 3 B
D
PD_USB1_SRC_HI_ILIM 5 QT16B
<43,58> PD_USB1_SRC_HI_ILIM G 2N7002KDW _SOT363-6
S
4
1
PD_USB1_SRC_HI_ILIM : TypeC@
RT231
H = 5V/3A 100K_0201_5%
L = 5V/1.5A @
I=21/RSET
2
A A

Reserve_TYPE-C
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve_TYPE-C
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve_TYPE-C
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve_TYPE-C
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve_TYPE-C
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve_TYPE-C
5 4 3 2 1
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

Reserve
A B C D E
A B C D E
LAN-RTL8111H W=60mil W=60mil

IDC=1200mA +LAN_VDD +3V_LAN
W=60mil
300mA 1.4A
+REGOUT RL3 1 RS@ 2 0_0603_5%
PVT modify
+3VALW +3V_LAN
RL11 RS@ 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0.1U_0201_10V6K
CL1
0.1U_0201_10V6K
CL19
0.1U_0201_10V6K
CL14
0.1U_0201_10V6K
CL13
0.1U_0201_10V6K
CL18
0.1U_0201_10V6K
CL12
1U_0201_6.3V6M
CL11
1U_0201_6.3V6M
CL10
4.7U_0402_6.3V6M
CL9
4.7U_0402_6.3V6M
C69
1U_0201_6.3V6M
CL16
0.1U_0201_10V6K
CL17
0.1U_0201_10V6K
CL15
0.1U_0201_10V6K
CL22
1 60mil 0_0805_5% 1
1 2
LAN@
LAN@
LAN@
LAN@
LAN@
LAN@
LAN@
LAN@
LAN@
LAN@
LAN@
UL2 60mil
5 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Using LDO mode
@
IN OUT
2
GND
4 3
@
EN OC
Place near Pin 3,8,22,30 Place near Pin 22 For surge improvement Place near Pin 11,32,23
2 2 SY6288C20AAC_SOT23-5
LAN@ LAN@ @ Place near Pin 11,32
CL20 CL21 Add 1 cap for downsize reserved
1U_0201_6.3V6M 1U_0201_6.3V6M LAN_PW R_EN
1 1 LAN_PW R_EN <59>
UL1
From EC
High active.
EN threshold voltage min:1.2V typ:1.6V max:2.0V reserve EC_PME# pull high 100K to +3VALW_EC
Current limit threshold 1.5~2.8A
LAN_MIDI0+ PCIE_CRX_C_DTX_P12
PCIe X1 +3V_LAN
1 17 LAN@ CL4 1 2 0.1U_0201_10V6K
LAN_MIDI0- MDIP0 HSOP PCIE_CRX_C_DTX_N12 PCIE_CRX_DTX_P12 <13>
2 18 LAN@ CL3 1 2 0.1U_0201_10V6K (link to PICe Port 12)
+LAN_VDD MDIN0 HSON PLT_RST_R# PCIE_CRX_DTX_N12 <13>
3 19
LAN_MIDI1+ AVDD10 PERSTB PLT_RST_R# <11,33,42,52,66,69>
4 20 ISOLATEB
MDIP1 ISOLATEB
1
LAN_MIDI1- 5 21 LAN_PME#
LAN_MIDI2+ MDIN1 LANWAKEB +LAN_VDD LAN_PME# <58>
6 22
LAN_MIDI2- 7 MDIP2 DVDD10 23 +3V_LAN RL12 LAN@
2 +LAN_VDD 8 MDIN2 VDDREG 24 +REGOUT 10K_0402_5% 2
LAN_MIDI3+ 9 AVDD10 REGOUT 25 1 TP@T329
2
LAN_MIDI3- 10 MDIP3 LED2 26 GPO 1 TP@T203
PU at PCH side +3V_LAN 11 MDIN3 LED1/GPIO 27 1 TP@T330 Reserve TP For Debug LAN_PME#
CLKREQ_LAN# 12 AVDD33 LED0 28 XTLI PVT modify
<11> CLKREQ_LAN# PCIE_CTX_C_DRX_P12 CLKREQB CKXTAL1 XTLO_R
PCIe X1 <13> PCIE_CTX_DRX_P12 0.1U_0201_10V6K LAN@ 1 2 CL7 13 29 LAN@ 1 RM129 2 XTLO 3/13 update Pin 28 to XTALIN
0.1U_0201_10V6K LAN@ 1 2 CL6 PCIE_CTX_C_DRX_N12 14 HSIP CKXTAL2 30 +LAN_VDD 470_0402_5%
<13> PCIE_CTX_DRX_N12 CLK_PCIE_LAN HSIN AVDD10 LAN_RST +3V_LAN
15 31 1 2
<11> CLK_PCIE_LAN CLK_PCIE_LAN# 16 REFCLK_P RSET 32 +3V_LAN 2.49K_0402_1% LAN@ RL6 +3VS
PU at PCH side PCIe CLK <11> CLK_PCIE_LAN# REFCLK_N AVDD33 33
GND
1
RL4 RL2
10K_0402_5% LAN@ 1K_0402_5%
@
LAN Connector
2
GPO ISOLATEB
RTL8111H-CG_QFN32_4X4 LAN@
2
SA000080P00 JRJ45
RL13
12 LAN@ 15K_0402_1%
RJ45_MIDI3- 8 GND
PR4- 11
1
RJ45_MIDI3+ 7 GND
PR4+
RJ45_MIDI1- 6
PR2-
RJ45_MIDI2- 5
PR3-
RJ45_MIDI2+ 4 LAN@
PR3+ YL1
RJ45_MIDI1+ 3 25MHZ_20PF_7R25000001
3 PR2+ 3
RJ45_MIDI0- 2 XTLI 1 3 XTLO MP modify
PR1- 10 1 3
RJ45_MIDI0+ 1 GND MP modify NC NC
PR1+ 1 1
TR1 9 LAN@
GND CL5 2 4 CL8
LAN_TERMAL 1 24 MCT1 LAN@ 33P_0402_50V8J 33P_0402_50V8J
LAN_MIDI0+ 2 TCT1 MCT1 23 RJ45_MIDI0+ SANTA_130460-3400 2 2
LAN_MIDI0- 3 TD1+ MX1+ 22 RJ45_MIDI0-
TD1- MX1- CONN@
SJ10000TO00
4
TCT2 MCT2
21 MCT2 DC23400F800
LAN_MIDI1+ 5 20 RJ45_MIDI1+
40mil LAN@ 12/21 change YL1 size to 20x16
TD2- MX2- RJ45_GND 1 2 LANGND
7 18 MCT3
LAN_MIDI2+ 8 TCT3 MCT3 17 RJ45_MIDI2+ C52
40mil 10P_0201_50V8J ESD
TD3- MX3- LANGND
1
10 15 MCT4 PLT_RST_R#
LAN_MIDI3+ 11 TCT4 MCT4 14 RJ45_MIDI3+ JUMP@
LAN_MIDI3- 12 TD4+ MX4+ 13 RJ45_MIDI3- J1 JP1
TD4- MX4- 1
JUMP_43X118 @EMC@
RL7
RL8
RL9
RL10
B88069X9231T203_4P5X3P2-2 CL2
100P_0201_50V8J
2
MHPC_NS892407 D8 2 @EMC@
1
2
2
2
2
LAN@ SP050006800 LAN_EMC@

LAN@
LAN@
LAN@
LAN@
C51 LAN@ AZ5125-02S.R7G_SOT23-3
1
.1U_0402_16V7K
2
Place close to TCT pin
1
1
1
1
75_0402_1%~D
75_0402_1%~D
75_0402_1%~D
75_0402_1%~D
4 4
RJ45_GND

LAN RTL8111H-CG
A B C D E
A B C D E
NGFF Wireless LAN / BT (Key E) [PCIE+USB/CNVi]

+3VALW +3VS_WLAN
+3VS_WLAN +3VS_WLAN
UW2 W=60mils
1 5 1 CW11,CW13,CW14 close to pin64,66 CW15/CW16/CW17 close to pin2,4 1
IN OUT
1 1 1 1 1 1
1
1 2 1 1 CW11 CW13 CW14 CW20 CW15 CW16 CW17 CW21
CW9 GND CW10 CW12 @ @ @RF@ @ @ @ @RF@
EC_WLAN_ON 4 3 4.7U_0402_6.3V6M
<58> EC_WLAN_ON
2
1U_0201_6.3V6M EN OC 4.7U_0402_6.3V6M 0.1U_0201_10V6K 2 2 2 2 4.7U_0402_6.3V6M 2 2
1
2 SY6288C20AAC_SOT23-5 2 2 0.1U_0201_10V6K 4.7U_0402_6.3V6M 10P_0201_25V8 0.1U_0201_10V6K 4.7U_0402_6.3V6M 10P_0201_25V8
@
RW21
100K_0402_5%
2
PD 100K For Gitch 20210524
Remark
* un use EMC (EM5203) for CNVi issue
** CNVi use ALW power rail / PCIE WLAN use VS rail UART_2_CRXD_R_DTXD RW24 1 UART@ 2 0_0402_5%
UART_2_CTXD_R_DRXD UART_2_CRXD_DTXD <12>
autodetct and change EN pin power domain by BIOS/EC RW25 1 UART@ 2 0_0402_5%
KEY E +3VS_WLAN
Co-layout with CNVi for UART Debug and BT signal
UART_2_CTXD_DRXD <12>
JNGFF1
1 2
3 GND_1 3.3VAUX_2 4 CNVi@
USB2 P10 <13> USB20_P10 USB_D+ 3.3VAUX_4
5 6 @ T144 1 RW26 2
(For Bluetooth) <13> USB20_N10 7 USB_D- LED1# 8 75K_0402_5%
CNV_CRX_DTX_N1 9 GND_7 PCM_CLK 10 CNV_RF_RESET#_R RW19 1 CNVi@ 2 33_0201_5% 1.8V
<14> CNV_CRX_DTX_N1 SDIO_CLK PCM_SYNC CNV_RF_RESET# <14>
CNV_CRX_DTX_P1 11 12
<14> CNV_CRX_DTX_P1 SDIO_CMD PCM_OUT
13 14 CLKREQ_CNV#_R RW1 1 CNVi@ 2 33_0201_5%
SDIO_DAT0 PCM_IN CLKREQ_CNV# <14>
CNV_CRX_DTX_N0 15 16
2 <14> CNV_CRX_DTX_N0 SDIO_DAT1 LED2# @ T70 2
CNVi Rx CNV_CRX_DTX_P0 17 18
<14> CNV_CRX_DTX_P0 SDIO_DAT2 GND_18
19 20
CLK_CNV_CRX_DTX_N 21 SDIO_DAT3 UART_WAKE 22 UART_2_CRXD_R_DTXD RW20 1 CNVi@ 2 39_0201_5%
<14> CLK_CNV_CRX_DTX_N CLK_CNV_CRX_DTX_P SDIO_WAKE UART_TX CNV_BRI_CRX_DTX <14>
23 DVT
<14> CLK_CNV_CRX_DTX_P SDIO_RST
24 UART_2_CTXD_R_DRXD RW3 1 CNVi@ 2 0_0402_5%
PH +3VS at SOC side, for win7 USB3 debug 1.8V UART X
UART_RX CNV_RGI_CRX_R_DTX CNV_RGI_CTX_DRX <14> CNV BT X
25 26 RW4 1 CNVi@ 2 39_0201_5%
PCIE_CTX_DRX_P9 CW18 GND_33 UART_RTS CNV_RGI_CRX_DTX <14>
1 2 0.1U_0201_10V6K PCIE_CTX_C_DRX_P9 27 28 CNV_BRI_CTX_R_DRX RW5 1 RS@ 2 0_0201_5% PVT CNV_BRI_CTX_DRX <14>
<13> PCIE_CTX_DRX_P9 PCIE_CTX_DRX_N9 CW19 PET_RX_P0 UART_CTS
1 2 0.1U_0201_10V6K PCIE_CTX_C_DRX_N9 29 30 E51TXD_P80DATA_R RW7 1 RS@ 2 0_0201_5%
<13> PCIE_CTX_DRX_N9 PET_RX_N0 CLink_RST E51TXD_P80DATA <58>
PCIe X1 31 32 E51RXD_P80CLK_R RW8 1 RS@ 2 0_0201_5%
GND_39 CLink_DATA E51RXD_P80CLK <58>
PCIE_CRX_DTX_P9 33 34
<13> PCIE_CRX_DTX_P9 PER_TX_P0 CLink_CLK
(Link to PICe Port 4) PCIE_CRX_DTX_N9 35 36
<13> PCIE_CRX_DTX_N9 PER_TX_N0 COEX3
37 38
CLK_PCIE_WLAN 39 GND_45 COEX2 40
<11> CLK_PCIE_WLAN CLK_PCIE_WLAN# REFCLK_P0 COEX1
PCIe CLK 41 42
<11> CLK_PCIE_WLAN# REFCLK_N0 SUSCLK(32KHz) WL_RST#_R
43 44 RW15 1 RS@ 2 0_0201_5% PLT_RST_R# PLT_RST_R# <11,33,42,51,66,69>
CLKREQ_PCIE#3 45 GND_51 PERST0# 46 BT_ON
(From PCH CLKOUT1) <11> CLKREQ_WLAN# CLKREQ0# W_DISABLE2# WL_OFF# BT_ON <10>
47 48 20200720-Remove BT_ON from EC
<58> WLAN_PME# PEWAKE0# W_DISABLE1# WL_OFF# <58>
49 50
CNV_CTX_DRX_N1 51 GND_57 I2C_DAT 52
<14> CNV_CTX_DRX_N1
<14> CNV_CTX_DRX_P1
CNV_CTX_DRX_P1 53 RSVD/PCIE_RX_P1 I2C_CLK 54 P80CLK and BT_ON enable seperate.
55 RSVD/PCIE_RX_N1 I2C_IRQ 56 REFCLK_CNV_R
GND_63 RSVD_64 @ T71
CNVi Tx CNV_CTX_DRX_N0 57 58
<14> CNV_CTX_DRX_N0 CNV_CTX_DRX_P0 RSVD/PCIE_TX_P1 RSVD_66
59 60
<14> CNV_CTX_DRX_P0 RSVD/PCIE_TX_N1 RSVD_68
61 62
CLK_CNV_CTX_DRX_N 63 GND_69 RSVD_70 64
<14> CLK_CNV_CTX_DRX_N CLK_CNV_CTX_DRX_P RSVD_71 3.3VAUX_72
65 66
<14> CLK_CNV_CTX_DRX_P RSVD_73 3.3VAUX_74
67
GND_75 68
3
GND1 Reserve for BT_ON OD pull high (1.0) 3
69 20200720 RM5 change to @ +3VS_WLAN
GND2
BELLW_80152-3221
CONN@ BT_ON RW28 1 @ 2 8.2K_0402_5%
SP070013E00
+3VS_WLAN
RW27 CLKREQ_CNV#_R RW29 1 2 10K_0402_5%
2 1 200K_0402_1% WLAN_PME#
E51TXD_P80DATA_R RW30 1 2 100K_0402_5%
remove Debug conn. due to placement
4 4

NGFF WL(KEY E) / WWAN(KRY B)
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
5 4 3 2 1
A B C D E
Int. Speaker Conn.

HD Audio Codec add 1 cap for MLCC downsize
+PVDD_HDA
SM01000EJ00 3000mA 220ohm@100mhz DCR 0.04 +5VS (output = 300 mA) +VDDA
40mil 40mil JPA1 40mil
LA1 2 1 1 2
+VDDA 1 2
HCB2012KF-221T30_0805 1 1 1
0.1U_0201_10V6K
CA2
0.1U_0201_10V6K
CA3
.1U_0402_16V7K
CA4
JUMP_43X79 4.75V
10U_0402_6.3V6M
10U_0402_6.3V6M
JUMP@
CA1
CA34
Remove RA3,RA4 2021/9/27 DVT JSPK1
2
2 2 @ +AVDD1_HDA 2
XEMC@ SPKL+ LA4 EMC@ 1 2 PBY160808T-121Y-N_2P SPK_L+ 1
GND GND
GND & GNDA moat SPKL- LA5 EMC@ 1 2 PBY160808T-121Y-N_2P SPK_L- 2 1
2 3
1 GND G1 1
EMI request for solve EMI noise, SM01000OW00. 4
G2
Place near Pin41 Place near Pin46
3
+VDDA CVILU_CI4202M2HR0-NH
add 1 cap for MLCC downsize CA35 1 2 10U_0402_6.3V6M add 1 cap for MLCC downsize CONN@ GND
GND 20mil XEMC@ SP02001CK00
CA5 1 2 10U_0402_6.3V6M RA1 1 RS@ 2 DA2
1 0_0603_5% TVNST52302AB0_SOT523-3
1
0.1U_0201_10V6K
CA8
Pin9 need to matching with SOC HDA CA6 1 2 0.1U_0201_10V6K CA9 CA36
1
interface.
10U_0402_6.3V6M
10U_0402_6.3V6M
2 RS@ 1 Place near Pin9 +3VS_DVDDIO GND
+3VS
2
RA2 0_0402_5% 2 @
+3VS_DVDD GND & GNDA moat
20mil GNDA
2 RS@ 1 Place near Pin26
+3VS
RA5 0_0402_5% +1.8VS Headphone Out
1
0.1U_0201_10V6K
CA11
CA37 CA10 +1.8VS_VDDA RA6 2 RS@ 1
1 0_0402_5%
1
+MIC2_VREFO
0.1U_0201_10V6K
CA12
CA13
10U_0402_6.3V6M
10U_0402_6.3V6M
2
2
2
DVT modify #575412 WHL DG p292_
10U_0402_6.3V6M
2
XEMC@ 2 @ add 2pF cap on HDA_SDO and HDA_RST# close to CPU
add 2pF cap on HDA_SDI close to codec
1 2 DMIC_CLK Place near Pin1 GND GNDA 11/26
CA32
1
10P_0201_50V8J HDA_SDIN0_AUDIO
41
46
26
40
1
9
UA1 Place near Pin40 RA19 RA20
Reserved for EMI 2.2K_0402_5% 2.2K_0402_5%
PVDD1
PVDD2
AVDD1
AVDD2
DVDD
DVDD-IO
add 1 cap for MLCC downsize
GND 1
CA31
2
@
LINE1-L 22 2P_0201_25V8B
LINE1-R 21 LINE1-L(PORT-C-L) 43 SPKL- 2 SLEEVE
LINE1-R(PORT-C-R) SPK-OUT-L- 42 SLEEVE <73>
SPKL+
24 SPK-OUT-L+ RING2
LINE2-L(PORT-E-L) RING2 <73>
23 45 SPKR+ GND
LINE2-R(PORT-E-R) SPK-OUT-R+ 44 SPKR+ <73>
SPKR-
SPK-OUT-R- SPKR- <73>
2 RING2 17 2
40mil SLEEVE 18 MIC2-L(PORT-F-L) /RING2
MIC2-R(PORT-F-R) /SLEEVE 32 HP_LEFT
Combo MIC HPOUT-L(PORT-I-L)
+MICBIAS 31 33 HP_RIGHT
+MICBIAS LINE1-VREFO-L HPOUT-R(PORT-I-R)
30
LINE1-VREFO-R 10 HDA_SYNC_R
DMIC_DATA 2 SYNC 6 HDA_BIT_CLK_R HDA_SYNC_R <10>
<38> DMIC_DATA DMIC_CLK GPIO0/DMIC-DATA BCLK HDA_BIT_CLK_R <10>
3
<38> DMIC_CLK GPIO1/DMIC-CLK 1 XEMC@ 2 1 2 CA15 XEMC@ GND
RA10 0_0402_5% 22P_0402_50V8J
EC_MUTE# 47 5 HDA_SDOUT_R
<58> EC_MUTE# HDA_RST#_R 2 PDB SDATA-OUT HDA_SDIN0_AUDIO HDA_SDOUT_R <10>
@ 1 11 8 1 RA33 2
Pin11,12 <10> HDA_RST#_R
0_0402_5% RA41 RESETB SDATA-IN 33_0402_5%
HDA_SDIN0 <10>
ALC255: RESETB, PCBEEP ALC255 48 CODEC_GPIO2 RA60 1 2 0_0201_5% DMIC_MUTE# Change to 51ohm 11/29
SPDIF-OUT/GPIO2 DMIC_MUTE# <58>
ALC256 : Floating ( I2C ) MONO_IN 12
10mil Close codec1
PCBEEP 16 PC_BEEP
HP_PLUG# RA13 2 200K_0402_1% SENSE_A 13 MONO-OUT
<73> HP_PLUG# SENSE A +MIC2_VREFO
+3VS RA14 2 1 100K_0402_1% 14 LINE1-L 1 2
SENSE B 29 10U_0402_6.3V6M 1 2 CA18 CA29 4.7U_0402_6.3V6M
MIC2-VREFO GND
1
ALC256 37
CA19 35 CBP 7 10U_0402_6.3V6M 1 2 CA20 HP_LEFT RA24 1 EMI@ 2 0_0603_5% HPOUT_L_1 R1 1 2 HPOUT_L_2
CBN LDO3-CAP GNDA HPOUT_L_2 <73>
2 1 2.2U_0402_6.3V6M 39 51_0603_1%
+1.8VS_VDDA
2
0_0402_5% RA43 LDO2-CAP 27 10U_0402_6.3V6M 1 2 CA21

LDO1-CAP GNDA PVT
2 @ 1 CPVDD 36
+3VS_DVDD CPVDD HP_RIGHT HPOUT_R_1 R2 1 HPOUT_R_2
0_0402_5% RA42 1 RA15 2 RA27 1 EMI@ 2 0_0603_5% 2
Pin20 28 CODEC_VREF 100K_0402_5% 10mil 51_0603_1%
HPOUT_R_2 <73>
ALC255 : 3.3V VREF
2.2U_0402_6.3V6M
ALC255 2 RS@ 1 20
+3VALW CPVREF
ALC256 : 3.3V or 5V
0.1U_0201_10V6K
CA23
RA16 0_0402_5% 15 1
JDREF
CA24
Power for combo jack depop 10U_0402_6.3V6M 1 2 CA22 19 34 CPVEE LINE1-R 1 2
GNDA MIC-CAP CPVEE CA30 4.7U_0402_6.3V6M
circuit at system shutdown mode 2 2
+MICBIAS DA5 C3 C4
2
1
4 @ 2 2 2 RA29 1 @EMC@ @EMC@
49 DVSS 25 CA26 4.7K_0402_5% 330P_0402_50V7K 330P_0402_50V7K
Pin4 Thermal PAD AVSS1 38 2.2U_0402_6.3V6M 1 1 1
ALC283 : DVSS
2
AVSS2
ALC255/256/233 : DC DET (For Japen customer only) ALC255-CG_MQFN48_6X6 Place near pin28 GNDA 3 2 RA32 1
SA000082700 4.7K_0402_5%
Pin36 @ GND BAT54A-7-F_SOT23-3
3 3
ALC255 : 3.3V GND SCS00007G00
GNDA
ALC256 : 1.8V Change to use SCS00007G00 , GNDA
SYMBOL:SCSBAT540A0 Due to load bom issue DVT
Pin15
RA21 CA27 ALC283 : Ref. Resistor for Jack Detect
DOS mode 22K_0402_5% .1U_0402_16V7K ALC255/256/233 : Jack Detect for SPDIF-OUT and SPK-OUT port
2 1 BEEP#_R 1 2 MONO_IN
<58> BEEP#
@
Pin16
RA22 CA33 ALC255:
2
MONO-OUT CODEC_GPIO2 2 0_0201_5% MUTE_LED# +3VS_DVDD

4.7K_0402_5%
OS mode 22K_0402_5% 1 .1U_0402_16V7K RA59 1 @

MUTE_LED# <58,63>
100P_0201_50V8J
CA28 XEMC@
2 1 1 2 PC_BEEP
<7> PCH_SPKR ALC256 : BEEP
RA23
1
2 ALC256
1
UA1 UA1
@ RA57
1
D @ 10K_0201_5%
GND & GNDA moat 2 QA12
2
1 2 RA51 G L2N7002WT1G_SC-70-3 CODEC_GPIO2
0_0402_5% DVT modify GND S SB000009Q80
1
RS@ S IC ALC256-CG MQFN 48P CODEC S IC ALC256M-CG MQFN 48P CODEC 0FA
1 2 RA52 256@ 256M@
0_0402_5% SA000080Q10 SA0000CCP10 RA58
RS@ 10K_0201_5%
1 2 RA53
2
0_0402_5%
RS@
1 2 RA54
0_0402_5% GND
RS@
1 2 RA55
0_0402_5%
RS@
1 2 RA56
0_0402_5% Mute LED circuit
4 RS@ 4
GND GNDA
Vendor suggest:
At least one Ground short close to codec.

HDA CODEC (ALC287)
1A
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Audio-Reserve
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
5 4 3 2 1
5 4 3 2 1
+1.8VALW_ESPI
near SOC SOC_RTCRST# <11>
1
+VTT_EC +1.05V_PROC D
1U_0201_6.3V6M
C63 1 2 0.1U_0201_10V6K EC_RST# 1
EC_CLR_CMOS
C87
2 QB1
G L2N7002WT1G_SC-70-3
1
R27 2 RS@ 1 0_0402_5% S
3
2 RB4
1 10K_0402_5%
Vendor suggest C54
2
+3VLP +3VLP_EC +3VLP_ECA 0.1U_0201_10V6K
+3VLP_EC R35 2
0_0603_5% L4 Vendor suggest
1 2 1 2
1 @ 2 LAN_PME# RS@ BLM15AX601SN1D _2P
D D
4.7U_0402_6.3V6M
RB6 47K_0402_5% SM01000KL00 10/21
0.1U_0201_10V6K
0.1U_0201_10V6K
EC_PME# PU +3V_LAN at LAN side remove ADP_EXIST
1 1 1 1 remove EN_PTM#
C62
C60
+3VLP_EC +1.8VALW_PRIM +1.8VALW_ESPI +VTT_EC remove AC_OFF
C59
C58
BT on need reserve EC path?
0.1U_0201_10V6K clubeman EC_VCCST_PG at pin21 but countryman need use FAN PWM
R32 1 2 2.2K_0402_5% EC_SMB_CK0 2 2 2 R28 2
USBKB_EN for perkey 5V use
R31 1 2 2.2K_0402_5% EC_SMB_DA0 0_0402_5%
1 2
RS@
ECAGND SPOK_5V_R RB73 1 RS@ 2 0_0402_5%
ECAGND <83> SPOK_5V <11,43,87>
111
117
124
DVT
22
33
96
67
UK5
9
ESPI Bus Pin : 1~14
VCC0
VCC_IO2
VCC_ESPI
VCC
VCC
VCC
AVCC
PECI_VTT
Power rail 1.8V
C86
XEMC@
2 1 2
XEMC@
R29
1 ESPI_CLK_R EMI TP_PWR_EN 1
eSPI & MISC
21
<63> TP_PWR_EN EC_WLAN_ON GA20/GPIO00 PWM0/GPIO0F EC_VCCST_PG_R <11>
22P_0402_50V8J 33_0402_5% 2 23
<52> EC_WLAN_ON EC_KBL_EN 3 ESPI_ALERT#/GPIO01 PWM1/GPIO10 26 FAN_PWM1 BEEP# <56> +3VS
<63> EC_KBL_EN GPIO02 PWM Output FANPWM0/GPIO12 FAN_PWM1 <77>
4 27 FAN_PWM2
<9> ESPI_CS# ESPI_CS# FANPWM1/GPIO13 FAN_PWM2 <77>
5
<9> ESPI_IO3_R ESPI_IO3
1
Reserved R3874,as Schematic checklist requirement, 7
<9> ESPI_IO2_R ESPI_IO2 BATT_TEMP
remove R33 (PD @ PCH side) 8 63 R80
<9> ESPI_IO1_R 10 ESPI_IO1 AD0/GPIO38 64 VRAM_TEMP BATT_TEMP <82,85>
<9> ESPI_IO0_R ESPI_IO0 AD1/GPIO39 VRAM_TEMP <83> 10K_0402_5%
65 @
ESPI_CLK_R AD2/GPIO3A AD_BID ADP_I <83,85>
12 AD Input 66
2
<9> ESPI_CLK_R EC_USB_EN 13 ESPICLK AD3/GPIO3B 75
<71,73> EC_USB_EN EC_RST# GPIO05 AD4/GPIO42 CHG_ILMSEL <71>
37 76 IDCHG
<77> EC_RST# CHG_EN 20 ECRST# AD5/GPIO43 IDCHG <85> DMIC_MUTE#
<71> CHG_EN CHG_CTL1 GPIO0E
38
<71> CHG_CTL1 ESPI_RST# GPIO1D
14
<9> ESPI_RST# ESPI_RST#/GPIO07 68 SPOK_5V_R Low -active need to pull-up
R34 1 @ 2 4.7K_0402_5% OPMODE DA0/GPIO3C 70 OPMODE +3VS
DA Output DA1/GPIO3D
KSI0 55 71 WLAN_PME#
KSI0/GPIO30 DA2/GPIO3E WL_OFF# WLAN_PME# <52> EC_CAM_DET
KSI1 56 72 R85 1 2 10K_0402_5%
KSI1/GPIO31 DA3/GPIO3F WL_OFF# <52>
KSI2 57
KSI3 58 KSI2/GPIO32 83 TS_EN EC_MUTE# R30 1 @ 2 10K_0402_5%
KSI3/GPIO33 SCL2/GPIO4A PD_USB1_SRC_HI_ILIM TS_EN <38> remove EC_SMB_CK2/DA2
KSI4 59 84
C
60 KSI4/GPIO34 SDA2/GPIO4B 85 EC_I2C_3_SCL PD_USB1_SRC_HI_ILIM <43,44> C
OPMODE (Internal Pull High) : KSI5 DVT
KSI5/GPIO35 SCL3/GPIO4C EC_I2C_3_SDA EC_I2C_3_SCL <43> SYS_PWROK_R
KSI6 61 86 RB11 1 RS@ 2 0_0402_5%
KSO[0..17] KSI6/GPIO36 SDA3/GPIO4D TP_CLK EC_I2C_3_SDA <43> 20200806 - I2C 3 for PD SYS_PWROK <11>
KSI7 62 87
Pull Up : Intel eSPI Master Attached Flash Sharing Topology <63> KSO[0..17] KSO0 39 KSI7/GPIO37
PS2 Interface
PSCLK3/GPIO4E 88 TP_DATA TP_CLK <63>
DVT
--> For KB9042 / KB9052 KSI[0..7] KSO0/GPIO20 PSDAT3/GPIO4F TP_DATA <63>
KSO1 40
<63> KSI[0..7] KSO2 41 KSO1/GPIO21
KSO3 42 KSO2/GPIO22 97 SOC_ENBKL
Pull Down : Intel Legacy Wire-OR share ROM. KSO3/GPIO23 SHICS#/GPIO60 EC_PD_INT# SOC_ENBKL <6> For Thermal Portect Shutdown
KSO4 43 98
--> For KB9022/9042 Use KSO5 44 KSO4/GPIO24 SHICLK/GPIO61 99 SLP_SUS# EC_PD_INT# <43>
KSO5/GPIO25 Int. K/B GPIO SHIDO/GPIO62 SLP_SUS# <11> Remove MAINPWON diode change to AND gate for 3V_EN 20210524
KSO6 45 109 VCIN0_PH
KSO7 46 KSO6/GPIO26 Matrix VCIN0/GPIO78 VCIN0_PH <83> +3VLP_EC
KSO7/GPIO27
remove TURBO_EN
KSO8 47
+3VLP_EC KSO9 48 KSO8/GPIO28 119 DMIC_MUTE#
49 KSO9/GPIO29 MISO_SHR_ROM/GPIO5B 120 ADP_DET DMIC_MUTE# <56>
KSO10
EC_SMB_CK1 KSO10/GPIO2A MOSI_SHR_ROM/GPIO5C EC_CLR_CMOS ADP_DET <83>
R67 1 2 2.2K_0402_5% KSO11 50 SPI ROM 126 CB2
R68 1 2 2.2K_0402_5% EC_SMB_DA1 KSO12 51 KSO11/GPIO2B SPICLK_SHR_ROM/GPIO58 128 EC_GPIO5A RB80 1 2 MUTE_LED# 2 1
KSO12/GPIO2C SPICS#_SHR_ROM/GPIO5A MUTE_LED# <56,63>
KSO13 52 0_0201_5%
KSO14 53 KSO13/GPIO2D 0.1U_0201_10V6K
KSO14/GPIO2E
Add VCIN1_BATT_DROP
5
KSO15 54 73 VCIN1_BATT_DROP
KSO15/GPIO2F AD6/GPIO40 SYS_PWROK_R VCIN1_BATT_DROP <83>
KSO16 81 74 3.3V
VCC
KSO17 82 KSO16/GPIO48 AD7/GPIO41 89 BATT_4S MAINPWON 1
KSO17/GPIO49 LOCK#/GPIO50 BATT_BLUE_LED# BATT_4S <85> IN B
90 4 3.3V
ESB_CLK EC_GPIO0B GPIO52 CAP_LED# BATT_BLUE_LED# <73> 3V_EN_R OUT Y 3V_EN <87>
RB75 1 @ 2 0_0201_5% 91 2
GND
<59> ESB_CLK CAPSLED#/GPIO53 CAP_LED# <63>
EC_SMB_CK0 77 GPIO 92 PWR_LED# 3.3V IN A
<82,85> EC_SMB_CK0 SCL0/GPIO44 WDT_LED/GPIO54 PWR_LED# <73>
2
EC_CAM_DET RB76 1 RS@ 2 0_0201_5% PVT EC_SMB_DA0 78 93 BATT_AMB_LED#
<59,63> EC_CAM_DET <82,85> EC_SMB_DA0 EC_SMB_CK1 SDA0/GPIO45 SCROLED#/GPIO55 BATT_AMB_LED# <73>
79 95 SYSON RB74 UB1
<33,66> EC_SMB_CK1 SYSON <16,66,89>
3
ESB_DAT RB77 1 @ 2 0_0201_5% EC_GPIO0C EC_SMB_DA1 80 SCL1_BT/GPIO46 GPIO56 121 VR_ON 100K_0402_5% NL17SZ08DFT2G_SC70-5
<59> ESB_DAT <33,66> EC_SMB_DA1 SPOK_3V SDA1_BT/GPIO47 GPIO57 PCH_DPWROK VR_ON <11,97>
15 SMBUS 127
DGPU_AC_DETECT RB78 1 <11,87,90> SPOK_3V AC_PRESENT SCL4/GPIO08 GPIO59 PCH_DPWROK <11>
<33,59,85> DGPU_AC_DETECT RS@ 2 0_0201_5% 19 SA0000BJI00
<11> AC_PRESENT
1
EC_GPIO0B 17 SDA4/GPIO0D
PVT
EC_GPIO0C 18 SCL5/GPIO0B 100 EC_RSMRST#
SDA5/GPIO0C FANFB2/GPIO63 3V_EN_R EC_RSMRST# <11>
101
FANFB3/GPIO64 102 VCIN1_ADP_PROCHOT
VCIN1/GPIO65 103 VCOUT1_PROCHOT# VCIN1_ADP_PROCHOT <83>
RB9 0_0402_5% GPIO
SPOK_3V 2 RS@ 1 VCOUT1/GPIO66 104 MAINPWON 3V_EN 1 2
CHARGE_ID 6 VCOUT0/GPIO67 105 EC_BKOFF# MAINPWON <77,83,87>
RB79 100K_0201_5%
SPOK_5V SPOK_3V_5V EC_MUTE# GPIO04 GPIO68 EC_TP_INT# EC_BKOFF# <38>
1 @ 2 0_0402_5% 16 106
<56> EC_MUTE# LAN_PME# OWM/GPIO0A GPIO69 EC_1.8V_EN EC_TP_INT# <7,63>
B RB10 25 107 B
<51> LAN_PME# FAN_SPEED1 28 PWM2/GPIO11 GPIO6A 108 TP_EN EC_1.8V_EN <90>
@ESD@
<77> FAN_SPEED1 FAN_SPEED2 FANFB0/GPIO14 GWG/GPIO6B TP_EN <63>
29 SYSON C88 1 2 0.1U_0201_10V6K
<77> FAN_SPEED2 E51TXD_P80DATA 30 FANFB1/GPIO15
<52> E51TXD_P80DATA TXD/GPIO16 GPIO
For abnormal shutdown E51RXD_P80CLK 31 110 ACIN
<52> E51RXD_P80CLK PCH_PWROK RXD/GPIO17 AC_IN/GPIO79 EC_ON ACIN <85>
32 112
<11> PCH_PWROK PWR_SUSP_LED# 34 POWER_FAIL1/GPIO18 GPXIOD02/GPIO7A 114 EC_ON <87>
DB2 11/10
<73> PWR_SUSP_LED# ON/OFFBTN# ON/OFFBTN# <63>
RB751V-40_SOD323-2 VCCIN_AUX_PCH_VR_PG change to VR_PWRGD 36 PWM3/GPIO19 GPIO7B 115 LID_SW#
VR_PWRGD <97> VR_PWRGD NUMLED#/GPIO1A GPIO GPXIOD04/GPIO7C LID_SW# <63,73>
SPOK_3V_5V 1 2 EC_RSMRST# 116 SUSP#
(check PRG155 should be reserve by default) GPIO7D SUSP# <11,16,38,69,78,85,89>
@ ACIN C82 1 2 100P_0201_50V8J
DB4 118 H_PECI_R 1 2
122 PECI/GPIO7F H_PECI <7> 1 2 4.7K_0402_5%
RB751V-40_SOD323-2 R26 43_0402_1% R61 @
PCH_PWROK <11> PBTN_OUT# XCLKI/GPIO5D
1 2 123
<71> CHG_CTL3 GPIO5E
125 ME_EN
FOR 9052 leakage issue GPIO7E ME_EN <10>
AGND
DB3
GND
GND
GND
GND
GND
RB751V-40_SOD323-2 +3VLP_EC
1 2 PCH_DPWROK
@ KB9052Q-D_LQFP128_14X14 LID_SW# RB5 1 2 100K_0402_5%
11
24
35
94
113
69
+3VLP_EC SA0000BCG50
S IC KB9052Q E LQFP 128P EC CONTROLLER +1.8VALW_PRIM
1 2 KSI0
20mil
ECAGND
Board ID RB15 470K_0402_5% Change to SA0000BCG50(KB9052Q-E) 1 2 BATT_TEMP

+3VLP_EC RB12 DVT@ C64 100P_0201_50V8J
1
12K +-5% 0402 SUSP# 1 2 PVT 1 2
SD034120280 RB16 100K_0402_5% L5 BLM15AX601SN1D _2P R83 2 RS@ 1 VCOUT1_PROCHOT#
2
RB12 A5DVT2@ RB12 A3DVT1@ SM01000KL00 10K_0402_5% RB14 0_0402_5%

RB13 15K +-5% 0402 160K +-5% 0402 CW3046@
100K_0402_1% SD034150280 SD034160380 CHARGE_ID
Ra
1 2
ECAGND
RB12 A5PVT@ RB12 A3PVT@ 2015/1/9 acer require:
1
AD_BID 20K +-5% 0402 200K +-5% 0402 R84

SD034200280 SD034200380 10K_0402_5%
reserved protact circuit when
1
1 SLGC55544@ adaptor 107% happen

EVT@ CB1
Rb RB12 0.1U_0201_10V6K 2
0_0402_5% @
2 RB12 A5MP1A@ RB12 A3MP1A@
2
A 27K +-5% 0402 240K +-1% 0402 RS@ A

SD034270280 SD000001B80 H_PROCHOT# 2 1 VR_HOT#
ESD <7,85> H_PROCHOT#

RB3 0_0402_5%
VR_HOT# <97>
SYS_PWROK_R PCH_PWROK VCOUT1_PROCHOT#

Analog Board ID definition,
Please see page 3. 2 1
C85 2
100P_0201_50V8J C61 C53
EMC@ 100P_0201_50V8J 100P_0201_50V8J
1
1
EMC@ 2 EMC@ Security Classification
2021/08/05
Compal Secret Data
2022/08/05 Title
EC_ENE KB9052Q
5 4 3 2 1
A B C D E
OMEN New ESB CLK&DAT for Extend I/O

*NMI_DBG#: is a debug pin for EC to
infrom BIOS after press hot key.
+3VLP_EC
1 1
1
KC3810@
RK20
47K_0402_1%
KC3810@
UK4
2
KC3810_RST# ESB_CLK 1 13 TEST_EN# - Keep NC

<58> ESB_CLK ESB_CLK TEST_EN#
2 <51> LAN_PW R_EN LAN_PW R_EN 2 14 EC_TS_PW R_EN
GPIO00 GPIO08/CAS_DAT EC_TS_PW R_EN <38>
KC3810@
CK16 KC3810_RST# 3 15 DVT
.1U_0402_16V7K RST# GPIO09
1 ESB_DAT 4 16
<58> ESB_DAT ESB_DAT GPIO0A
PM_SLP_S0# RB8 1 @ 2 0_0402_5% PM_SLP_S0#_R 5 17
<11,66> PM_SLP_S0# GPIO01 GPIO0B
<58,63> EC_CAM_DET 6 18
GPIO02 GPIO0C/PWM0
+3VLP_EC 7 19
<33,58,85> DGPU_AC_DETECT GPIO03 GPIO0D/PWM1
20200824
KC3810@ GPU_OVERT#_EC 8 20
GPIO04 GPIO0E/PWM2 - Change to 3Zone RGB
RK207 2 1 4.7K_0402_5% ESB_CLK
- Remove G & B enable
<95> VCCIN_AUX_VR_PG 9 21
RK208 2 1 4.7K_0402_5% ESB_DAT GPIO05 GPIO0F/PWM3
KC3810@ FP_PW R_EN 10 22
<66> FP_PW R_EN GPIO06 GPIO10/ESB_RUN#
11 23 BaseAddOpt Remove UK4.23 SX_EXIT_HOLDOFF# form GH67G 20210519
GPIO07/CAS_CLK GPIO11/BaseAddOpt
12 24
GND
GND VCC +3VLP_EC
2 2
0.1U_0201_10V6K
W=60mils
CK202
KC3810NF-A0_QFN24_4X4 1
25
SA00002AI00
KC3810@
+3VS
2
RB71 1 2 10K_0402_5% GPU_OVERT#
DVT
GPU_OVERT# RB18 1 RS@ 2 0_0402_5%
<33> GPU_OVERT#
THERMAL_ALERT# 1 @ 2 GPU_OVERT#_EC
<66> THERMAL_ALERT#
RB17 0_0402_5%
Need EC confirm
3 3
[ GPIO11/BaseAddOpt ] +3VLP_EC
If support second 3810,
please let one 3810 GPIO11 connect GND and
1
the other keep NC or initial High @
RK213
- High/NC: USR_EGPIOBaseSetting - 0x00 47K_0402_1%
- Low: USR_EGPIOBaseSetting - 0x08
2
BaseAddOpt
1
@
RK214
0_0402_5%
2
4 4

Reserve for KBC &SIO
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve for Secure & Reset IC
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve for SMB/I2C Block Diagrams
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve for LEDs Controller
5 4 3 2 1
KB Conn. 32pin CONN@
TP/B Conn. +3V_PTP
@ CK2
0.1U_0201_10V6K
+3V_PTP
+3VS JTP1
<58,59> EC_CAM_DET JKB1 RK11 2 1
EC_CAM_DET 32 34 +3VALW 0_0402_5% 1
MUTE_LED# 820_0402_5% 1 2 RE76 MUTE_LED#_R 31 32 G2 33 2 @ 1 TP_CLK 2 1
<56,58> MUTE_LED# 31 G1 2
CAP_LED# 820_0402_5% 1 2 RE77 CAP_LED#_R 30 TP_DATA 3
<58> CAP_LED#
29 30 EC PS2 4 3
4.7U_0402_6.3V6M
+5VS 29 4
KSO16 28 UK2 I2C_1_SDA_R 5
KSO17 27 28 5 1 I2C_1_SCL_R 6 5
KSO0 26 27 IN OUT PCH I2C EC_TP_INT# 7 6
26 1 <7,58> EC_TP_INT# 7
KSI[0..7] 25 2 TP_EN 8
CK5
KSO1 <58> TP_EN
<58> KSI[0..7] 25 GND 8
KSO2 24 1
KSO[0..17] KSO3 23 24 4 3
<58> KSO[0..17] 23 EN OC 2
KSO4 22 1 CK6 9
KSO5 21 22 CK4 SY6288C20AAC_SOT23-5 GND 10
21 680P_0402_50V7K GND
KSO6 20 ESD@ 2
KSO7 19 20 1U_0201_6.3V6M HEFEN_AFA02-S08FIA-2H
KSO8 18 19 2 CONN@
18 TP_PWR_EN <58>
KSO9 17 SP01002PE00
17
1
RK220 KSO10 16
ON/OFF BTN 100K_0402_5% KSO11 15 16 @
+3VLP 2 1 KSO12 14 15 RK218 TP_PWR_EN follow SYSON behavior
KSO13 13 14 100K_0402_5% +3V_PTP
KSO14 12 13
2
KSO15 11 12
11
2
KSI0 10 +3V_PTP +3V_PTP
ON/OFFBTN# KSI1 9 10
<58> ON/OFFBTN# 9
KSI2 8 RK1
KSI3 7 8 10K_0402_5%
7
1
SW 1 EVT@ KSI4 6 RK10 RK7
1
6
5
1 2 KSI5 5 2.2K_0402_5% 2.2K_0402_5% EC_TP_INT#
G
KSI6 4 5 QK1B
KSI7 3 4 2N7002KDW _SOT363-6
For EVT TEST 2 3
2
3 4 ON/OFFBTN# 1 2 3 4 I2C_1_SCL_R +3V_PTP
S
1 <12> I2C_1_SCL
D
ACES_51519-03201-001
SKRPABE010_4P SP01001RH00 1 2
1
SN10000CV00 RK9 @ 0_0402_5%
2
RK3 RK2
G
change PN to SN10000CV00 4.7K_0402_5% 4.7K_0402_5%
QK1A
2N7002KDW _SOT363-6
2
6 1 I2C_1_SDA_R
S
<12> I2C_1_SDA
D
TP_CLK
<58> TP_CLK TP_DATA
1 @ 2
<58> TP_DATA
KB BackLight RK8 0_0402_5%
Change to pop ESD request 10/8
+5VS +5VS_BL ACES_51522-00801-001

U9 DK4
5 1 8 TP_DATA 6 3 TP_EN
IN OUT 7 8 10 I/O4 I/O2
2 6 7 G2 9
0.1U_0201_10V6K
GND 5 6 G1
4 3 4 5 5 2
<58> EC_KBL_EN EN OC 4 +3V_PTP VDD GND
1 3
SY6288C20AAC_SOT23-5 2 3
2
C84
1
1 +5VS_BL ACES_51522-00801-001 TP_CLK 4 1 EC_TP_INT#
2 JBL1 I/O3 I/O1
CONN@ 8 AZC099-04S.R7G_SOT23-6
7 8 10 ESD@ SC300001G00
6 7 G2 9
5 6 G1
4 5
3 4
2 3
1 2
1
JBL2
CONN@
JBL2 for 17"
Battery LED
Hall sensor Move to SUB/B

+3VLP
+3VLP CONN@
JHS1
1
LID_SW # 2 1
1 <58,73> LID_SW# 2
3 5
CG2 4 3 GND 6
1 4 GND
0.1U_0201_10V6K
@ 2 CG3 JXT_FP202DH-004M10M
0.1U_0201_10V6K SP010022U00
@ESD@ 2 Security Classification Compal Secret Data Compal Electronics, Inc.
KB/TP/LED/LID
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
5 4 3 2 1
A B C D E
Close to Thermal SKIN

20200717 THERMAL SENSOR
- Remove G-Sensor 20200810
- Check address
+3VS +3VS +3VS
SMBUS ADDRESS
1001_0000b
TMS@
1
TMS@ UF3
RF9 RF26 TMS_SMB_CLK 1 5 TMS_SMB_DATA
RF10 10K_0402_5% SMBCLK SMBDATA
2.2K_0402_5%
5
TMS@ 2.2K_0402_5% TMS@ 2 +3VS
G
QF1B TMS@ GND
2
2N7002KDW_SOT363-6 THERMAL2_ALERT# 3 4
1 ALERT# +Vs 1
3 4 TMS_SMB_CLK
<33,58> EC_SMB_CK1 1
S
G753T11U_SOT23-5
2
TMS@ TMS@ CF22
G
QF1A SA00008CH00 0.1U_0201_10V6K
2N7002KDW_SOT363-6 2
6 1 TMS_SMB_DATA
<33,58> EC_SMB_DA1
S
D
Change to G753T11U
Close to SO-DIMM
+3VS
+3VS
1 SMBUS ADDRESS
20200928 TMS@ CF20
1001_1000b
1
0.1U_0201_10V6K TMS@
TMS@ UF2 RF24
2 1 8 TMS_SMB_CLK 10K_0402_5%
- Remove 3rd thermal sensor 2

VDD SCL
7 TMS_SMB_DATA
2
D+ SDA
3 6 THERMAL_ALERT#
D- ALERT# THERMAL_ALERT# <59>
1 TMS@ 2 TH_THERM# 4 5
+3VS T_CRIT# GND THERMAL2_ALERT#
RF23 10K_0402_5% RK209 1 @ 2 0_0402_5%
2 NCT7718W_MSOP8 2
SA000067P10 Change to SA000067P10 2021/09/08
S IC NCT7718W MSOP 8P THEMAL SENSOR AETD
TPM 2.0
Finger print
+FP_VCC
UK1
+3VALW add 1 cap for MLCC downsize +3VALW_TPM +3VS add 1 cap for MLCC downsize +3VS_TPM RK5 1 RS@ 2 0_0603_5% 5 1
+3VALW IN OUT
RK4 1 @ 2 0_0603_5% 1
+5VALW
1 TPM@ 2 1 TPM@ 2 2 FP@
RW18 0_0603_5% RW17 0_0603_5% GND CK1
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
0.1U_0201_10V6K
CW3 TPM@
0.1U_0201_10V6K
CW4 TPM@
0.1U_0201_10V6K
CW1 TPM@
0.1U_0201_10V6K
CW2 TPM@
4 3
CW7
TPM@ CW8
TPM@ CW6
TPM@ CW5
1 1 1 1 EN OC 4.7U_0402_6.3V6M
1
2
1 SY6288C20AAC_SOT23-5
TPM@
CK3 FP@
2
2 2 2 2 FP@ FP_PWREN RK221 1 @ 2 0_0201_5%

FP_PWR_EN <59>
1U_0201_6.3V6M
2 RK222 1 RS@ 2 0_0201_5% SYSON <16,58,89>
1
PVT Change to unpop ESD request 10/8
@ Due to no EC pin , change to SYSON enable
near pin1 near pin8,22 RK219
+3VALW_TPM 100K_0402_5%
SA0000AQ250, S IC NPCT750AABYX QFN 32P TPM (SPI interface) PD 100K For Gitch 20210524
2
RW6 1 TPM@ 2 10K_0402_5% TPM_PIRQ# DK1 @ESD@
UW1 6 3 USB20_N9_L
+FP_VCC I/O4 I/O2
1
VSB +3VALW_TPM
2 TPM@ 1 29
3 <11,59> PM_SLP_S0# SDA/GPIO0 3
RW16 0_0402_5% 30 8
SCL/GPIO1 VHIO +3VS_TPM
22 5 2
6 VHIO SM070005U00 VDD GND
GPIO3 2 RW31 1 @ 2 0_0201_5% DLM0NSN900HY2D_4P
SOC_SPI_0_D1_R TPM@ 1 RW9 2 56_0201_1% TPM_SPI_SO 24 NC 3 USB20_N9 2 1 USB20_N9_L
<9> SOC_SPI_0_D1_R SOC_SPI_0_D0_R TPM_SPI_SI MISO NC <13> USB20_N9 2 1 USB20_P9_L
TPM@ 1 RW10 2 56_0201_1% 21 5 4 1
<9> SOC_SPI_0_D0_R TPM_PIRQ# 2 RW13 1 TPM_PIRQ#_R 18 MOSI/GPIO7 NC 7 I/O3 I/O1
<6> TPM_PIRQ# TPM@
0_0402_5% PIRQ/GPIO2 NC 9 RW32 1 @ 2 0_0201_5% USB20_P9 3 4 USB20_P9_L AZC099-04S.R7G_SOT23-6
NC <13> USB20_P9 3 4
10
SOC_SPI_0_CLK_R TPM@ 1 RW12 2 56_0201_1% TPM_SPI_CLK 19 NC 11 LK1 FPEMC@
<9> SOC_SPI_0_CLK_R SOC_SPI_0_CS#2 TPM_SPI_CS#2 SCLK NC
TPM@ 2 RW11 1 0_0402_5% 20 12
<9> SOC_SPI_0_CS#2 PLT_RST_R# 2 RW14 1 0_0402_5% TPM_RST# 17 SCS/GPIO5 NC 14
TPM@
<11,33,42,51,52,69> PLT_RST_R# 27 PLTRST NC 15
13 NC NC 26
20200727 GPIO4 NC DVT:update JFP1 define
25 +FP_VCC
- RW9/RW10/RW12 change to 56ohm for 2 load topology NC 28
4 NC 31 PIN ETU801 FA577E-1200 Power Souce Check
@ T32 PP/GPIO6 NC 32 1 2 0_0201_5% SP01001AE00
NC
RW35 @
1 +FP_VCC(5V) +FP_VCC(3V) EGIS ETU801 +FP_VCC=5V ACES_51522-00801-001
GND
16
23
RW33 1 TPM@
RW34 1 TPM@
2 0_0201_5%
2 0_0201_5% 2 USBP D+ ELAN SA464K-2200 +FP_VCC=3.3V USB20_P9_L
8
7 8 10
GND 33 USB20_N9_L 6 7 G2 9
PGND 3 USBN D- 5 6 G1
NPCT750AAAYX_QFN32_5X5 4 5
4 GND GND 3 4
@ 3
2
5 NC NC 1 2
1
UW1 TPM@ 6 NC NC JFP1
CONN@
7 NC
8 NC SWAP FP conn. pin define 08/23
S IC NPCT750AADYX QFN 32P TPM FW 7.2.2.0

SA0000AQ2F0
4 4

TPM/FP/Sensor
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1A
A B C D E
A B C D E
1
+5VS_HDD FFC Type 1
100mils
10U_0402_6.3V6M
CO12
1
1
CONN@
HDD@ CO13 JHDD1
0.1U_0201_10V6K 14
2
2 @ +5VS +5VS_HDD 13 GND
GND
RO4 1 RS@ 2 0_0805_5% 12
11 12
DVT 11
10
RO25 1 RS@ 2 0_0201_5% G_INT2_R 9 10
8 9
7 8
Remove SATA Redriver due to length spec SATA_CRX_DTX_P0 CO14 2 HDD@
1 0.01U_0201_6.3V7K RDSATA_CRX_DTX_C_P0 6 7
<13> SATA_CRX_DTX_P0 SATA_CRX_DTX_N0 RDSATA_CRX_DTX_C_N0 6
CO15 2 HDD@
1 0.01U_0201_6.3V7K 5
<13> SATA_CRX_DTX_N0 4 5
SATA_CTX_DRX_N0 CO16 2 HDD@
1 0.01U_0201_6.3V7K RDSATA_CTX_DRX_C_N0 3 4
<13> SATA_CTX_DRX_N0 SATA_CTX_DRX_P0 RDSATA_CTX_DRX_C_P0 3
<13> SATA_CTX_DRX_P0 CO17 2 HDD@
1 0.01U_0201_6.3V7K 2
1 2
1
SWAP PIN 07/29 ACES_51625-01201-001
SP010028W00
2 2
3 3
4 4

HDD/ Re-Driver/ G-sensor
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
+3VS_SSD_1 +3VS_SSD1
20210517 Power source +3VALW
DVT +3VS_SSD1
> +3VS_SSD1 : JSSD1 @ UM2
2 2
> +3VS_SSD2 : JSSD2 CS98 2 1 1 14 +3VS_SSD_1 1 RS@ 2 CS103 CS104
0.1U_0201_10V6K 2 VIN1 VOUT1 13 RS21 0_0805_5%
VIN1 VOUT1 0.1U_0201_10V6K 0.1U_0201_10V6K
1 1
SUSP# RS22 1 RS@ 2 0_0201_5% +3V_NGFF_GATE1 3 12 1 2
<11,16,38,58,78,85,89> SUSP# ON1 CT1
DVT CS97 1000P_0402_50V7K
4 11
+5VALW VBIAS GND
+3VALW CS100 2 1 5 10 1 2 +3VS_SSD2
1U_0201_6.3V6M ON2 CT2 CS99 1000P_0402_50V7K
D 6 9 +3VS_SSD_2 1 RS@ 2 D
+3V_NGFF_GATE2 VIN2 VOUT2
1U_0201_6.3V6M
1U_0201_6.3V6M
2 2 RS24 1 RS@ 2 0_0201_5% 7 8 RS25 0_0805_5%
VIN2 VOUT2
CS101
CS102
DVT
@ 15 DVT +3VS_SSD_2 +3VS_SSD2
2 1 CS109 GPAD
1 1 EM5209VF_DFN14_2X3 2 2
0.1U_0201_10V6K
CS116 CS117
0.1U_0201_10V6K 0.1U_0201_10V6K
1 1
Place CS101 close UM2 pin 1&2
Place CS102 close UM2 pin 6&7
+3VS_SSD1
SSD (Gen4) JSSD1 1
10U_0402_6.3V6M
0.1U_0201_10V6K
1 2 1 2 1
(PCIE4 Port A)
15P_0201_25V8J
3 GND 3P3VAUX 4 + CS95 CS121
PCIE4_A_CRX_DTX_N3 5 GND 3P3VAUX 6 CS94 CS96 150U_B2_6.3VM_R35M @RF@
<13> PCIE4_A_CRX_DTX_N3 PCIE4_A_CRX_DTX_P3 7 PERn3 NC 8
<13> PCIE4_A_CRX_DTX_P3 PERp3 NC 2 1 2
SGA0000F200
2
20210517 Power source
9 10
PCIE4_A_CTX_DRX_N3 CS61 1 2 0.22U_0201_10V6K PCIE4_A_CTX_C_DRX_N3 11 GND DAS/DSS# 12
> +3VS_SSD1 : JSSD1
<13> PCIE4_A_CTX_DRX_N3 PCIE4_A_CTX_DRX_P3 CS62 1 2 0.22U_0201_10V6K PCIE4_A_CTX_C_DRX_P3 13 PETn3 3P3VAUX 14 > +3VS_SSD2 : JSSD2
<13> PCIE4_A_CTX_DRX_P3 PETp3 3P3VAUX
15 16
PCIE4_A_CRX_DTX_N2 17 GND 3P3VAUX 18 RF request 08/06
<13> PCIE4_A_CRX_DTX_N2 PCIE4_A_CRX_DTX_P2 PERn2 3P3VAUX
19 20
<13> PCIE4_A_CRX_DTX_P2 PERp2 NC
21 22 Change to SGA0000F200 due to SGA00009M00 shortage
PCIE4_A_CTX_DRX_N2 CS63 1 2 0.22U_0201_10V6K PCIE4_A_CTX_C_DRX_N2 23 GND NC 24
<13> PCIE4_A_CTX_DRX_N2 PCIE4_A_CTX_DRX_P2 CS64 PETn2 NC
1 2 0.22U_0201_10V6K PCIE4_A_CTX_C_DRX_P2 25 26
<13> PCIE4_A_CTX_DRX_P2 27 PETp2 NC 28
PCIE4_A_CRX_DTX_N1 29 GND NC 30
<13> PCIE4_A_CRX_DTX_N1 PCIE4_A_CRX_DTX_P1 PERn1 NC
31 32
C
<13> PCIE4_A_CRX_DTX_P1 33 PERp1 NC 34 C
<13> PCIE4_A_CTX_DRX_N1 PCIE4_A_CTX_DRX_P1 CS66 1 2 0.22U_0201_10V6K PCIE4_A_CTX_C_DRX_P1 37 PETn1 NC 38
<13> PCIE4_A_CTX_DRX_P1
39 PETp1 DEVSLP 40
20200813 Remove DEVSLP
PCIE4_A_CRX_DTX_N0 41 GND NC 42
<13> PCIE4_A_CRX_DTX_N0 PCIE4_A_CRX_DTX_P0 43 PERn0/SATA-B+ NC 44
<13> PCIE4_A_CRX_DTX_P0 PERp0/SATA-B- NC
45 46
<13> PCIE4_A_CTX_DRX_N0 PCIE4_A_CTX_DRX_P0 CS68 PETn0/SATA-A- NC
1 2 0.22U_0201_10V6K PCIE4_A_CTX_C_DRX_P0 49 50 PLT_RST_R# <11,33,42,51,52,66,69>
<13> PCIE4_A_CTX_DRX_P0 PETp0/SATA-A+ PERST# SSD1_CLKREQ#_R
51 52 RS23 1 RS@ 2 0_0201_5%
GND CLKREQ# CLKREQ_SSD1# <11>
53 54 DVT
<11> CLK_PCIE_SSD1# REFCLKN PEWake#
<11> CLK_PCIE_SSD1 55 56
57 REFCLKP NC 58
GND NC
Change to pop CS105 From ESD request
T217
59 60 SUSCLK_SSD1
20200813 SUSCLK Change to TP
ESD@
SSD1_DET# 61 NC SUSCLK(32kHz) 62 PLT_RST_R# CS105 2 1 100P_0402_50V8J
T216 @ PEDET(NC-PCIE/GND-SATA) 3P3VAUX
63 64 @
65 GND 3P3VAUX 66
67 GND 3P3VAUX
GND 68
Place close to JSSD pin 50
Remove-PEDET(NC-PCIE/GND-SATA) GND1 69 ESD request to reserve.
GND2
BELLW_80159-3221
CONN@
SP070018L00
+3VS_SSD2
SSD (Gen3)
(PCIE3 Port 5~8)
JSSD2 1
10U_0402_6.3V6M
0.1U_0201_10V6K
1 2 1 2 1
15P_0201_25V8J
3 GND 3P3VAUX 4 + CS108 CS122
B PCIE3_CRX_DTX_N8 5 GND 3P3VAUX 6 CS106 CS107 150U_B2_6.3VM_R35M @RF@ B
<13> PCIE3_CRX_DTX_N8 PCIE3_CRX_DTX_P8 PERn3 NC
7 8 SGA0000F200
<13> PCIE3_CRX_DTX_P8 PERp3 NC 2 1 2 2
9 10
PCIE3_CTX_DRX_N8 CS92 1 2 0.22U_0201_10V6K PCIE3_CTX_C_DRX_N8 11 GND DAS/DSS# 12
<13> PCIE3_CTX_DRX_N8 PCIE3_CTX_DRX_P8 CS93 PETn3 3P3VAUX
<13> PCIE3_CTX_DRX_P8 1 2 0.22U_0201_10V6K PCIE3_CTX_C_DRX_P8 13 14
15 PETp3 3P3VAUX 16
PCIE3_CRX_DTX_N7 17 GND 3P3VAUX 18 RF request 08/06
<13> PCIE3_CRX_DTX_N7 PCIE3_CRX_DTX_P7 PERn2 3P3VAUX
19 20
<13> PCIE3_CRX_DTX_P7 21 PERp2 NC 22 Change to SGA0000F200 due to SGA00009M00 shortage
PCIE3_CTX_DRX_N7 CS86 1 2 0.22U_0201_10V6K PCIE3_CTX_C_DRX_N7 23 GND NC 24
<13> PCIE3_CTX_DRX_N7 PCIE3_CTX_DRX_P7 CS88 PETn2 NC
1 2 0.22U_0201_10V6K PCIE3_CTX_C_DRX_P7 25 26
<13> PCIE3_CTX_DRX_P7 PETp2 NC
27 28
PCIE3_CRX_DTX_N6 29 GND NC 30
<13> PCIE3_CRX_DTX_N6 PCIE3_CRX_DTX_P6 31 PERn1 NC 32
<13> PCIE3_CRX_DTX_P6 PERp1 NC
33 34
PCIE3_CTX_DRX_N6 CS87 1 2 0.22U_0201_10V6K PCIE3_CTX_C_DRX_N6 35 GND NC 36
<13> PCIE3_CTX_DRX_N6 PCIE3_CTX_DRX_P6 CS90 PETn1 NC
<13> PCIE3_CTX_DRX_P6 1 2 0.22U_0201_10V6K PCIE3_CTX_C_DRX_P6 37 38 20200813 Remove DEVSLP
39 PETp1 DEVSLP 40
PCIE3_CRX_DTX_N5 41 GND NC 42
<13> PCIE3_CRX_DTX_N5 PCIE3_CRX_DTX_P5 PERn0/SATA-B+ NC
43 44
<13> PCIE3_CRX_DTX_P5 45 PERp0/SATA-B- NC 46
PCIE3_CTX_DRX_N5 CS89 1 2 0.22U_0201_10V6K PCIE3_CTX_C_DRX_N5 47 GND NC 48 @ESD@
<13> PCIE3_CTX_DRX_N5 PCIE3_CTX_DRX_P5 CS91 PETn0/SATA-A- NC
1 2 0.22U_0201_10V6K PCIE3_CTX_C_DRX_P5 49 50 PLT_RST_R# CS119 2 1 100P_0402_50V8J
<13> PCIE3_CTX_DRX_P5 PETp0/SATA-A+ PERST# SSD2_CLKREQ#_R PLT_RST_R# <11,33,42,51,52,66,69>
51 52 RS28 1 RS@ 2 0_0201_5%
GND CLKREQ# CLKREQ_SSD2# <11>
<11> CLK_PCIE_SSD2# 53 54
55 REFCLKN PEWake# 56
<11> CLK_PCIE_SSD2 REFCLKP NC DVT Place close to JSSD pin 50
57 58
GND NC
ESD request to reserve.
T219
59 60 SUSCLK_SSD2
20200813 SUSCLK Change to TP
61 NC SUSCLK(32kHz) 62
T224 @ PEDET(NC-PCIE/GND-SATA) 3P3VAUX
63 64 @
65 GND 3P3VAUX 66
67 GND 3P3VAUX
GND 68
A Remove-PEDET(NC-PCIE/GND-SATA) GND1 69
A
GND2
BELLW_80159-3221
CONN@
SP070018L00

SATA/PCIE-SSD
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

SATA/PCIE-SSD
5 4 3 2 1
1 2 3 4 5
MB_USB3 GEN1 Type-A Conn. 20210907

- Change PN to SC300001Y00 (GEN1)
ESD@ SC300001Y00
D1
USB3_CRX_DTX_N1 RS16 2 RS@ 1 0_0402_5% USB3_CRX_L_DTX_N1 USB3_CRX_L_DTX_N1 1 1 10 9 USB3_CRX_L_DTX_N1
<13> USB3_CRX_DTX_N1
USB3_CRX_DTX_P1 RS17 2 RS@ 1 0_0402_5% USB3_CRX_L_DTX_P1 USB3_CRX_L_DTX_P1 2 2 9 8 USB3_CRX_L_DTX_P1
<13> USB3_CRX_DTX_P1
USB3_CTX_L_DRX_N1 4 4 7 7 USB3_CTX_L_DRX_N1
+5VALW_USBB
USB3_CTX_L_DRX_P1 5 5 6 6 USB3_CTX_L_DRX_P1 20200819
USB3_CTX_DRX_N1 USB3_CTX_C_DRX_N1 USB3_CTX_L_DRX_N1
- Add for USB Power 1
CT561 1 2 0.1U_0201_10V6K RS30 2 RS@ 1 0_0402_5% 3 3
<13> USB3_CTX_DRX_N1 +
CT537
8 150U_B2_6.3VM_R35M
A USB3_CTX_DRX_P1 CT562 1 2 0.1U_0201_10V6K USB3_CTX_C_DRX_P1 RS31 2 RS@ 1 0_0402_5% USB3_CTX_L_DRX_P1 SGA0000F200 A
<13> USB3_CTX_DRX_P1 2
AZ1045-04F_DFN2510P10E-10-9
USB Host Charger Change to SGA0000F200 due to SGA00009M00 shortage
ESD@ +5VALW_USBB
D5
SC300001G00 JUSB1
+5VALW 6 3 U2DN1_R 1
I/O4 I/O2 U2DN1_R 2 VBUS
+5VALW_USBB U2DP1_R 3 D-
RS6 1 RS@ 2 0_1206_5% 4 D+
LT4 EMI@ +5VALW_USBB 5 2 USB3_CRX_L_DTX_N1 5 GND
U2DP1_R VDD GND USB3_CRX_L_DTX_P1 StdA-SSRX-
22U_0603_6.3V6M
.1U_0402_16V7K
1 1 U2DP1 4 3 6 10
4 3 StdA-SSRX+ GND 11
1
CS2
CS1
CHG@
7
@ RS5 USB3_CTX_L_DRX_N1 8 GND-DRAIN GND 12
RS@ U2DN1 1 2 U2DN1_R U2DP1_R 4 1 USB3_CTX_L_DRX_P1 9 StdA-SSTX- GND 13
0_1206_5%
2 2 1 2 I/O3 I/O1 StdA-SSTX+ GND
US1 SLGC55544@ DLM0NSN900HY2D_4P AZC099-04S.R7G_SOT23-6 ACON_TARAC-9V1391
2
+5VALW_CHG 1 12 +USB3VCCB_CHG SM070005U00
VIN VOUT CONN@
2 DC23300AG00
20200724 <13,71> USB20_N1 DM_OUT
- Change to USB OC1# for Reserved 3 FH51M symbol
<13,71> USB20_P1 DP_OUT
@ 10 U2DP1
USB_OC2# 2 RS7 1 0_0402_5% 13 DP_IN 11 U2DN1
<6> USB_OC2# FAULT# DM_IN
CHG_ILMSEL
0.1U_0201_10V6K
4
1 <58> CHG_ILMSEL ILIM_SEL Co-lay for Non-charger
CS3
@ CHG_EN 5 15
<58> CHG_EN EN ILIM_L +5VALW_USBA
16 +5VALW_USBB
2 ILIM_HI
1
CHG_CTL1 6
<58> CHG_CTL1 CHG_CTL2 CTL1
22.1K_0402_1%
39K_0402_1%
7 9
CHG_CTL3 CTL2 NC
RS9
RS8
8 14 1 NCHG@ 2
<58> CHG_CTL3 CTL3 GND 17 RS20 0_0805_5%
Thermal Pad CHG@ CHG@
2
1
+5VALW RT364 1 NCHG@ 2 0_0201_5% USB20_N1_R RT366 1 NCHG@ 2 0_0201_5% U2DN1

<13,71> USB20_N1
@ SLGC55544CVTR_TQFN16_3X3 RT365 1 NCHG@ 2 0_0201_5% USB20_P1_R RT367 1 NCHG@ 2 0_0201_5% U2DP1
B <13,71> USB20_P1 B
RS11
CHG@ 0_0402_5%
RS3 1 2 10K_0402_5% CHG_CTL2
2
0831 Reserve ILIM_L R as vendor recommend

RS4 1 @ 2 10K_0402_5% CHG_ILMSEL 20200721 ILM R vaule
- For SDP measure
Ios(mA)=50250/R(Kohm)
0911 Rerserve PU, vendor suggest to EC ILIM_Hi=2273mA
control if future need support SDP2 ILIM_L=1288mA(reserve)
US1
USB Host Charger Truth Table S IC CW3046AAAQ QFN 16P USB CHARGER
SA0000A7L00
CHG_EN CTL1 CTL2 CTL3 ILIM_SEL MODE Current Limit Note CW3046@
Setting
0 0 1 0 1 SDP1-OFF ILIM_H Port power off ZZZ ZZZ
1 0 1 0 1 SDP1 ILIM_H Data Lines Connected

ALT. GROUP PARTS USB CHARGER SLG HH5A4 ALT. GROUP PARTS USB CHARGER CW HH5A4
1 0 1 1 1 DCP ILIM_H Data Lines Disconnected X76954BOL11 X76954BOL12
Auto X76CHGSLG@ X76CHGCW@
1 1 1 1 1 CDP ILIM_H Data Lines Connected
20210907
+5VALW_USBA
+5VALW +5VALW_USBA
- Change PN to SC300001Y00 (GEN1)
20200819
UT4 80mil ESD@ SC300001Y00 - Add for USB Power 1
5 1 DT28
IN OUT USB3_CRX_L_DTX_N2 1 1 USB3_CRX_L_DTX_N2 +
C 20200825 10 9 CT536 C
- C25 pop (follow FH5AT) 2 150U_B2_6.3VM_R35M
GND USB3_CRX_DTX_N2 USB3_CRX_L_DTX_N2 USB3_CRX_L_DTX_P2 USB3_CRX_L_DTX_P2
47U_0805_6.3V6M
0.1U_0201_10V6K
1 1 RS13 2 RS@ 1 0_0402_5% 2 2 9 8 SGA0000F200

<13> USB3_CRX_DTX_N2
1
EC_USB_EN USB_OC1# 2
C26
C27
C25 4 3
EN OC USB3_CRX_DTX_P2 2 RS@ 1 0_0402_5% USB3_CRX_L_DTX_P2 USB3_CTX_L_DRX_N2 4 4 USB3_CTX_L_DRX_N2
1U_0201_6.3V6M
<13> USB3_CRX_DTX_P2
RS12 7 7
SY6288C20AAC_SOT23-5
2
2 I (Max) : 0.9 A(+5VALW_USBA) 2 USB3_CTX_L_DRX_P2 5 5 6 6 USB3_CTX_L_DRX_P2

RDS(Typ) : 70 mohm Change to SGA0000F200 due to SGA00009M00 shortage
USB3_CTX_DRX_N2 CT521 1 2 0.1U_0201_10V6K USB3_CTX_C_DRX_N2 RS32 2 RS@ 1 0_0402_5% USB3_CTX_L_DRX_N2 3 3
V drop : 0.063 V <13> USB3_CTX_DRX_N2
<58,73> EC_USB_EN EN: Active High 8
USB3_CTX_DRX_P2 CT520 1 2 0.1U_0201_10V6K USB3_CTX_C_DRX_P2 RS33 2 RS@ 1 0_0402_5% USB3_CTX_L_DRX_P2
<13> USB3_CTX_DRX_P2
1
AZ1045-04F_DFN2510P10E-10-9
@ USB_OC1# <6>
R75
100K_0402_5%
PD 100K For Gitch 20210524
2
ESD@ +5VALW_USBA
D6
SC300001G00
USB20_N5_R 6 3 JUSB2
I/O4 I/O2 1
USB20_N5_R 2 VBUS
L6 EMI@ USB20_P5_R 3 D-
USB20_P5 4 3 USB20_P5_R +5VALW_USBA 5 2 4 D+
<13> USB20_P5 4 3 VDD GND USB3_CRX_L_DTX_N2 GND
5
USB3_CRX_L_DTX_P2 6 StdA-SSRX- 10
USB20_N5 1 2 USB20_N5_R 7 StdA-SSRX+ GND 11
<13> USB20_N5 1 2 USB20_P5_R USB3_CTX_L_DRX_N2 GND-DRAIN GND
4 1 8 12
DLM0NSN900HY2D_4P I/O3 I/O1 USB3_CTX_L_DRX_P2 9 StdA-SSTX- GND 13
SM070005U00 AZC099-04S.R7G_SOT23-6 StdA-SSTX+ GND
ACON_TARAC-9V1391
CONN@
DC23300AG00
FH51M symbol
D D

USB2/USB3 TYPEA1&2
1A
1 2 3 4 5
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
5 4 3 2 1
A B C D E
IO/B CONN
1 1
CONN@
TW VM_FPC0518-40RC-TAGHT
42
41 GND2
LT3 EMI@ 40 GND1
USB20_P6 USB20_P6_R <56> HP_PLUG# 40
4 3 <56> RING2 39
<13> USB20_P6 4 3 39
<56> SLEEVE 38
37 38
<56> HPOUT_R_2 37
USB20_N6 1 2 USB20_N6_R 36
<13> USB20_N6 1 2 <56> HPOUT_L_2 36
35
DLM0NSN900HY2D_4P GNDA BATT_AMB_LED# 34 35
<58> BATT_AMB_LED# 34
SM070005U00 BATT_BLUE_LED# 33
<58> BATT_BLUE_LED# 33
PWR_SUSP_LED# 32
<58> PWR_SUSP_LED# 32
PWR_LED# 31
<58> PWR_LED# 31
+3VALW 30
29 30
28 29
+3VLP 28
2 EC_USB_EN 27 2
<58,71> EC_USB_EN 27
LID_SW # 26
<58,63> LID_SW # 26
25
USB3_CTX_DRX_P3 24 25
<13> USB3_CTX_DRX_P3 USB3_CTX_DRX_N3 24
23
<13> USB3_CTX_DRX_N3 23
22
USB3_CRX_DTX_P3 21 22
<13> USB3_CRX_DTX_P3 21
USB3_CRX_DTX_N3 20
<13> USB3_CRX_DTX_N3 20
19
USB20_N6_R 18 19
USB20_P6_R 17 18
16 17
15 16
14 15
13 14
SPKR- 12 13
<56> SPKR- 12
11
SPKR+ 10 11
<56> SPKR+ 10
9
+5VALW 8 9
7 8
6 7
5 6
4 5
100mils 2.5A 3 4
2 3
1 2
1
JIO1
3 3
SWAP pin define due to sub/b outline change 0810
4 4

IO/B_LAN E2600
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
5 4 3 2 1
FAN1 Conn Screw Hole Stand OFF
@ H1 @ H5 @ H7
Clips FD1
@ H10 @ H11 @ H12 @ H13 H_3P3 H_4P2 H_3P2 @
1
H_3P0-G H_2P1 H_3P1X2P1 H_3P0-G CLIP1
+5VS +VCC_FAN1 EMIST_SUL-12A2M_1P FIDUCIAL_C56M40
40mil
1
RF1 1 RS@ 2 0_0603_5% FD2
1
1 2
1
XEMC@ CF2 CF1 @ H2 @ H6 @ @
1
1000P_0402_50V7K 4.7U_0402_6.3V6M H_3P3 H_4P2 CLIP2
2 1 EMIST_SUL-12A2M_1P FIDUCIAL_C56M40
@ H15 @ H16
H_2P8X2P1 H_5P0X4P5 FD3
1
@ @
1
+3VS @ H3 CLIP3
H_3P3 EMIST_SUL-12A2M_1P FIDUCIAL_C56M40
1
FD4
RF2
1
10K_0402_5% +VCC_FAN1
40mil @ @
JFAN1
1
CLIP4
2
1 @ H4 EMIST_SUL-12A2M_1P FIDUCIAL_C56M40
FAN_SPEED1 2 1 H_3P3
<58> FAN_SPEED1 FAN_PWM1 3 2
<58> FAN_PWM1 4 3
1
1
4
1
5 @
CF3 6 GND
2 1000P_0402_50V7K GND
XEMC@ CVILU_CI4204M2HR0-NH
CONN@
SP020012X00
1
D@
2 QB2
G L2N7002WT1G_SC-70-3
S
3
Reserve for Factory 10/05
FAN2 Conn Reset Circuit

+3VLP 1 @ 2
MAINPWON <58,83,87>
R23 0_0402_5%
1 RS@ 2
EC_RST# <58>
2
+VCC_FAN2 R24 0_0402_5%
+5VS R25
40mil
10K_0402_5%
RF4 1 RS@ 2 0_0603_5%
1 2
6
Q2A D
XEMC@ CF5 CF6 BI_GATE# 2
1000P_0402_50V7K 4.7U_0402_6.3V6M BI_GATE PH to +RTCVCC at PWR G
2 1 2N7002KDW_SOT363-6
side S
1
1
3
Q2B D C40
BI_GATE 5 0.1U_0201_10V6K
<82> BI_GATE G 2
2N7002KDW_SOT363-6
S
4
+3VS
1
RF3
10K_0402_5% +VCC_FAN2
JFAN2
40mil Reset Button
2
1
FAN_SPEED2 2 1
<58> FAN_SPEED2 FAN_PWM2 2 SW3
3
<58> FAN_PWM2 3 BI_GATE 1 BI_GATE
1 4 2
4
5
CF4 6 GND
2 1000P_0402_50V7K GND 3 4
XEMC@ CVILU_CI4204M2HR0-NH
CONN@
SKRPABE010_4P
SP020012X00
SN10000CV00
change PN to SN10000CV00

FAN & Screw Hole
A B C D E
+3VALW
+3VS
+3VALW TO +3VS
1U_0201_6.3V6M
C81
1 I (Max) : 6.89 A(+3VS) JUMP@
RON(Max) : 21 mohm JPQ2
+3VS_LS 1 2
V drop : 0.145 V 1 2
2 JUMP_43X118
1 U8 1 1
0.1U_0201_10V6K
1 14
VIN1 VOUT1
C83
2 13
R60 1 RS@ 2 0_0201_5% EN_3VS VIN1 VOUT1
<11,16,38,58,69,85,89> SUSP# 3 12 1 2 2
EN1 SS1 C80
+5VALW 4 11 1000P_0201_50V7K
VBIAS GND
5 10 1 2
EN2 SS2 C79
6 9 1000P_0201_50V7K
7 VIN2 VOUT2 8
1 VIN2 VOUT2
C78 15
1U_0201_6.3V6M Thermal pad
2 EM5209VF_DFN14_2X3
I (Max) : 5.434 A(+5VS)

RON(Max) : 21 mohm
V drop : 0.114 V
2 2
+5VS
+5VALW
+5VALW TO +5VS C76 2 1 JUMP@

1U_0201_6.3V6M UM5 JPQ1
1 14 +5VS_LS 1 2
2 VIN1 VOUT1 13 1 2
SUSP# RS29 1 RS@ 2 0_0201_5% VIN1 VOUT1 JUMP_43X118 1
+5VALW EN_5VS 3 12 1 2
ON1 CT1 CS120 1000P_0402_50V7K C70
2 1 4 11 0.1U_0201_25V6K
CS112 1U_0201_6.3V6M VBIAS GND 2
SUSP# RS26 1 RS@ 2 0_0201_5% EN_1.8VS 5 10 1 2 +1.8VS
ON2 CT2 CS111 1000P_0402_50V7K
6 9 +1.8VS_R 1 RS@ 2
7 VIN2 VOUT2 8 RS27 0_0805_5%
+1.8VALW_PRIM VIN2 VOUT2
15 DVT
+1.8VALW TO +1.8VS GPAD +1.8VS
EM5209VF_DFN14_2X3
1U_0201_6.3V6M
CS113
1 2
CS118
0.1U_0201_10V6K
2 1
3 3
20200717
- Remove VGA Power sequence
4 4

DC Interface & Sequence Logic
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

XDP/CMC/APS Debug Conn
1A
5 4 3 2 1
5 4 3 2 1
CPU PN
UC1 UC1 UC1 UC1
QS P28W QS U15W Sus-QS UC1 I3-1215U UC1
MP
UC1
I3-1220P
S IC FJ8071504661126 QY4Y Q0 1G BGA S S IC FJ8071504661124 QY4W Q0 1G BGA S S IC FJ8071504787906 QYYD K0 1.7G BGA S S IC FJ8071504826607 Q0E8 R0 1.7G S
QY4Y@ QY4W @ QYYD@ Q0E8@ S IC FJ8071504827100 SRLFT R0 1.2G BGA 1744 ABO ! S IC FJ8071504827402 SRLFY R0 1.5G BGA 1744 ABO !
D
SA0000ERH10 SA0000ERL00 SA0000F4X10 SA0000FB530 S IC FJ8071504786604 Q07M L0 2.1G S 0FA SRLFT@ SRLFY@ D
Q07M@ SA0000FBR80 SA0000FE850
SA0000F9E60
UC1 UC1 UC1 UC1 UC1 UC1
I5-1235U
UC1
i5-1240P
S IC FJ8071504661121 QY4T Q0 1.2G BGA S S IC FJ8071504698605 QXZS J0 1G FCBGA S S IC FJ8071504786603 QYY9 K0 2.1G BGA S S IC FJ8071504826802 Q0EP R0 1.3G S S IC FJ8071504826802 SRLFQ R0 1.3G BGA 1744 ABO ! S IC FJ8071504787907 SRLD9 L0 1.7G BGA 1744 ABO !
QY4T@ QXZS@ QYY9@ Q0EP@ SRLFQ@ SRLD9@
SA0000EQC10 SA0000EL800 SA0000F4A10 SA0000FB720 S IC FJ8071504787907 Q07Q L0 1.7G S 0FA SA0000FB7A0 SA0000F9FB0
Q07Q@
SA0000F9F70 UC1 I7-1255U UC1
UC1 UC1 UC1 UC1
i7-1260P
S IC FJ8071504826607 SRLFP R0 1.7G BGA 1744 ABO ! S IC FJ8071504786607 SRLD6 L0 2.1G FCBGA 1744 ABO !
S IC FJ8071504661122 QY4U Q0 1.2G BGA S S IC FJ8071504698606 QXZT J0 1G FCBGA S S IC FJ8071504827402 Q0EU R0 1.5G BGA S S IC FJ8071504827100 Q0EV R0 1.2G BGA S SRLFP@ SRLD6@
QY4U@ QXZT@ Q0EU@ Q0EV@ SA0000FB5A0 SA0000FBV40
SA0000EQD10 SA0000EL920 SA0000FE800 SA0000FBR00
A5 X4E PN A3 X4E PN HDMI LOGO

ZZZ ZZZ
ZZZ ZZZ ZZZ
C C
X4EDIS@ X4EDISNFP@
X4EA3DIS@ X4EA3DISNFP@
SMT EMC DIS EE LAM211 HH5A4 PCBA EMC DIS W /O FP EE LAM211 HH5A4
X4EAUWBOL01 X4EAUWBOL04 SMT EMC DIS LAM211 HH5J4 SMT EMC DIS LAM211 HH5J4 HDMI LOGO 45@
X4EAUWBOL51 X4EAUWBOL56 RO0000003HM
ZZZ ZZZ
ZZZ ZZZ
X4EUMA@ X4EUMANFP@
X4EA3UMA@ X4EA3UMANFP@
SMT EMC UMA EE LAM211 HH5A4 PCBA EMC UMA W /O FP EE LAM211 HH5A4
X4EAUWBOL02 X4EAUWBOL03 SMT EMC UMA LAM211 HH5J4 SMT EMC UMA W /O FP LAM211 HH5J4
X4EAUWBOL52 X4EAUWBOL54
ZZZ ZZZ
X4EA3UMAS@ X4EA3UMASNFP@
SMT EMC UMA SLIM LAM211 HH5J4 SMT EMC UMA SLIM W /O FP LAM211 HH5J4
X4EAUWBOL53 X4EAUWBOL55
B
PCB PN B
ZZZ ZZZ ZZZ
PCB 3TY LA-M211P REV0 MB 1 S PCB HH5A4 LA-M211P LS-M211P PCB HH5A4 LA-M211P LS-M211P 1A
PCB@ DAZ10@ DAZ1A@
DA8001SW000 DAZ3TY00100 DAZ3TY00101
ZZZ ZZZ
PCB 3TY LA-M211P REV1 MB 1 PCB 3TY LA-M211P REV1A MB 1A

PCB10@ PCB1A@
DA8001SW010 DA8001SW01A
A A

Config
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
Size
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH514 MB LA-L972P
5 4 3 2 1
A B C D E
+19V_ADPIN 5A_Z120_25M_0805_2P
EMI@ PL101
+19V_ADPIN_P1
1 @ PJP101 1
1 1 2
1 2
2 3 1 2
3
@EMI@ PL102
1
4 5A_Z120_25M_0805_2P
G1
1
5 EMI@ PC104
G2 EMI@ PC105 PC102 1000P_0402_50V7K
2
ACES_30706-11702-001 1000P_0402_50V7K 100P_0201_50V8J
2
EMI@
ADAPDET
ADAPDET <85>
PR1853 100_0402_1%
MB:Battery Con Put TOP Side 1 2
EC_SMB_DA0 <58,85>
PR1854 100_0402_1%
2 1 2 2
EC_SMB_CK0 <58,85>
Battery Bot Side PR1855

200K_0402_1%
1 2
PIN1 GND @ PJP201 +3VLP
1
PIN2 GND 1 2 1 2
2 3 BATT_TEMP <58,85>
PIN3 SMD 3 4
EC_SMB_DA1-1
EC_SMB_CK1-1 PR1856 1K_0402_1%
PIN4 SMC 4 5
5 6
BATT_TS
BATT_B/I
PIN5 TEMP 6 7
7 8
PIN6 BI 8 9 +RTCVCC
PIN7 Batt+ GND 10
GND
PIN8 Batt+ CVILU_CI9908M2HR0-NH
1
PR212
100K_0402_5%
PQ201 Change to SB00000QO00,
SB501380010(BSS138LT1G Del)
2
1
D
<77> BI_GATE 2 PQ201
G LBSS139LT1G 1N SOT-23-3
+12.6V_BATT+ S
3
EMI@ PL201
2
3 FBMA-L11-201209-800LMA50T @ @0@ PR101 3
1 2 PR1857
change PL201, PL202 +12.6V_BATT 0_0402_5% 1 2
SM01000C000 to comm +3VLP +CHGRTC
1 2 0_0402_5%
part SM01000P200
1
EMI@ PL1803
FBMA-L11-201209-800LMA50T
1
EMI@ PC1853 PC1854

1000P_0402_50V7K 0.01U_0402_50V7K
2
EMI@
2013/06/07
Add for ENE9022 Battery Voltage drop detection.
Connect to ENE9022 pin64 AD1.
4 4

DCIN
A B C D E
A B C D E
PR1861 0.005_1206_1%
1 4
2 3
NON_PD@
+19V_ADPIN_P1
PD@
PQ204
AONR21357_DFN3X3-8-5-X
1
2 +19V_VIN
5 3
1
PD@ PD201
BZT52-B5V1S_SOD323-2
4
1 1
PD@ PQ206
2
1
D TP0610K
2 ideal_1
G
ADAPTERIN_IDEL_GATE
470K_0402_1%
ADAPTERIN_IDEL_E
PD@ PR223
2
PD@ PQ207B PD@ PQ207A
METR3906KW-G_SOT363-6 METR3906KW-G_SOT363-6
1
5 2
6
ADAPTERIN_IDEL_C
1ADAPTERIN_IDEL_B
+20V_TBT_0_VBUS_R +20V_TBT_0_VBUS_R_P1 +20V_TBT_0_VBUS_R_P2
PD@ PQ15 PD@ PQ14 PD@ PQ251
1
PD@
1
AONR21357_DFN3X3-8-5-X AONR21357_DFN3X3-8-5-X AONR21357_DFN3X3-8-5-X PD@ PR210 PR211
1 1 1 @ PJ2 47K_0402_1% PD@ 47K_0402_1%
2 2 2 +20V_VIN_TYPEC_0 1 2 PR222
5 3 3 5 5 3 1 2
+19V_VIN 470K_0402_1%
2
JUMP_43X118
2
4
4
1
PD@
499K_0402_1%
2200P_0402_25V7K
PQ253
1 +3VLP +19V_ADPIN_P1
1
D TP0610K
PD@ PR44
2 ideal_1
2 PD@ PC10 G 2
2
TYPE-CIN_IDEL_GATE
S
TYPE-CIN_IDEL_E 3
0.1U_0402_25V7K
1
1
PR217
PC202
100K_0402_1%
TYPE-C_20V_Gate
102K_0402_1%
100K_0402_1%
2
1
1
PR214
@OTP@ PR209
30.1K_0402_1%
1
PR213
2
@OTP@
PD@ PQ252B PD@ PQ252A
1
2
PD@ METR3906KW-G_SOT363-6 METR3906KW-G_SOT363-6 PU201
2
PR45
1
1 8 G718_TMSNS1
49.9K_0402_1% VCC TMSNS1
@OTP@ PR201 2 7 G718_RHYST1 @OTP@ 1 2
5 2 GND RHYST1
2
0_0402_5% PR206 16.2K_0402_1%

1 2MAINPWON_G718 3 6 G718_TMSNS2
TYPE-C_20V_Gate_R
MAINPWON
<58,77,87> MAINPWON OT1 TMSNS2
4 5 G718_RHYST2
1 2
TYPE-CIN_IDEL_B
<58> ADP_DET OT2 RHYST2
1
G718TM1U_SOT23-8 PR202 PR203
PH204
3
6
2M_0402_1%
Check barrel adapter exist or not. 4.99K_0402_1%
100K_0402_1%_NCP15WF104F03RC
TYPE-CIN_IDEL_C
2
@OTP@
1
D
(Common Part)
2 PD@ PQ16
<43> TYPE-C_20V_VIN_EN
G SL200002H00
2N7002KW_SOT323-3
S
3
1
PD@ PR252 PD@ PR251
47K_0402_1% PD@ PR253 47K_0402_1%
470K_0402_1%
2
2
When PR204=18.7K
For KB9022 Active Recovery
OTP
3 3
VCIN0_PH(V) 89'C, 1V 56'C, 2V
PH202(ohm) 8.0524K 26.11K
+3VLP_ECA
+3VLP_ECA
PR205
10K_0402_1%
1 2
1
ADP_I <58,85>
+19VB_5V PR207
1
16.5K_0402_1%
PR208
18.7K_0402_1%
2
VCIN1_ADP_PROCHOT <58>
2
<58> VRAM_TEMP
1
PR1858 VCIN0_PH <58>

750K_0402_1%
@0@ PR1859
2
1
PC203 must close to EC pin
1
1 2 PR204
VCIN1_BATT_DROP <58>
VGA@ PH203 @VGA@ PH202 10K_0402_1% PH201
2
@ PC201
2013/06/07 0_0402_5% 100K_0402_1%_NCP15WF104F03RC 100K_0402_1%_NCP15WF104F03RC 100K_0402_1%_NCP15WF104F03RC
2
1
Add for ENE9022 Battery Voltage drop detection. 0.1U_0402_25V6
1
2
PC204 PR1860
Connect to ENE9022 pin64 AD1. 0.1U_0402_25V6 150K_0402_1% PT202 @ PH201 is Common Part SL200002H00
1
PT201 @
ECAGND <58>
T202 T201 must close to PH201
VAL50/ZAL20 Battery is 3-cell NVDC design.
B+=9V
Change PR12=50k if Battery is 2-cell NVDC design ADP_I=20*I(adapter)*0.01
B+=6V I(adapter)=adapter(W)*130%/19
4 4

BATTERY CONN/OTP
D 1A
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
Size
5 4 3 2 1
A B C D E
PRB1 PQB2
1
D AON7506_DFN33-8-5
1M_0402_1%
2 1 2
PQB1 +19VB 1
G L2N7002SWT1G_SOT323-3 2 +12.6V_BATT_CHG
PRB2 S 5 3
3
2 1
+19V_P1 +19V_P2
PQB3 3M_0402_5% PQB4
4
EMB04N03H_EDFN5X6-8-5 AON7506_DFN33-8-5
1 1
PRB3
0.01_1206_1% EMI@ PLB1
+19V_CHG
1 2 2 1
HCB2012KF-121T50_0805
5 3 3 5 1 4 1 2
+19V_VIN
2 3
10U_0603_25V6M
PCB8 @ 10U_0603_25V6M
0.047U_0603_25V7M
4
10U_0603_25V6M
1000P_0402_50V7K
2200P_0402_50V7K
PCB2
1 2
1
PCB1
PCB3
PCB4
68P_0402_50V8J
0.1U_0402_25V6
0.1U_0402_25V6
ACFET MDU1512 SB00000SY00 ACP ACN
1
@EMI@ PCB5
EMI@ PCB6
PCB9
EMI@ PCB10
0.022U_0603_25V7K
Rds(on):4.2~5m Ohm
2
4.7_0603_1%
4.02K_0402_1%
2
10_0402_1%
Vgs=20V
1
PRB4
PCB12
2
PCB11
Vds=30V 0.1U_0402_25V6 PCB13
PRB5
PRB6
EMI@
2 1 1 2 1 2
ID= 24.2A (Ta=70C)
PCB7
1
0.01U_0402_50V7K
2
+19V_VIN ACDRV_CHGR_R 0.1U_0402_25V7K
PRB7
1
4.02K_0402_1% BATDRV_CHGR
PRB44 1 2 ACDRV_CHGR
1
10K_0402_50%_TPM0S103P130R
@ PRB8 PRB9 @
0_0402_5% 0_0402_5%
2
+19V_ADPIN_P1 2 1CMSRC_CHGR BATSRC_CHGR
PRB10
2
1
@0@ PRB21 4.02K_0402_1%
ACN_CHGR
ACP_CHGR
0_0402_5% PDB1 PRB12 @ PCB15
2016/03/13 SE158225K80 X1
1
499K_0402_1%
S SCH DIO BAS40CW SOT-323 10_1206_5% 1000P_0402_50V7K

2
down size SE00000WP00 S

PRB37
3 1 2
+19V_VIN 1 2 1
CER CAP 2.2U 25V K X5R 0603
1
2 ACDRV_CHGR PQB5
+19VB
PRB45 PCB16 1U_0603_25V6K +6V_CHG_REGN
2
422K_0402_1% 2 1 PCB18
2.2U_0603_16V6K
AON7506_DFN33-8-5
PUB1
2
<82> ADAPDET ACDET 1 2 Choke 4.7uH SH00000YC00 (Common Part)
ACDRV
ACP
ACN
28
VCC PRB14 (Size:6.6 x 7.3 x 3 mm)
2N7002KW_SOT323-3
2 2
CMSRC_CHGR 3 (DCR:28m~33m)
68.1K_0402_1%
24 0_0603_5%
CMSRC REGN
1
2DH_CHGR_R4
1
D PCB28 @ PCB19 1
PRB40
1
1
215K_0402_1%
PRB38
2200P_0402_50V7K 6 0.047U_0603_25V7M
PQB23
2 ACDET BST_CHGR1 2BST_CHGR_R 1

PRB31
G 25 2
11 BTST
<58,82> EC_SMB_DA0 +12.6V_BATT
2
SDA
S
2
3
2
1
UG_CHGR 0_0603_5%
3
12 26 PRB19
2
<58,82> EC_SMB_CK0 SCL HIDRV PLB2 0.01_1206_1%

1
@0@ ACPRN_CHGR 5 4.7UH_PCMB063T-4R7MS_8A_20%

@0@ PRB17 <58,83> ADP_I PCB20 PRB18 0_0402_5% ACOK 27 LX_CHGR 1 2 1 4
0_0402_5% 1 2 1 2 7 PHASE
IADP 2 3
1
LG_CHGR
4.7_1206_5%
100P_0201_50V8J IDCHG 8 23 PQB6
2
IDCHG LODRV
EMI@ PRB20
CPU_PMON
10U_0603_25V6M
10U_0603_25V6M
1 2 9
PMON
AON7506_DFN33-8-5
@ PCB21 10 22 PRB41 316K_0402_1% SRP SRN
1SNUB_CHGR2
/PROCHOT GND
1
PCB22
PCB23
100P_0201_50V8J 1 2
+3VLP 4
<58> IDCHG PRB24 143K_0402_1%
2
@0@ PRB42 0_0402_5% 13 21 ILIM_CHGR 1 2
GND ILIM
680P_0402_50V7K
1 2 PRB25
<7,58> H_PROCHOT# 14 10_0402_1%
3
2
1
NC SRP_CHGR
EMI@ PCB24
@ 20 1 2
PRB26 SRP
1 2 15 19 SRN_CHGR 1 2
20160601 colay BQ24781
2
/BATPRES SRN
PRB43
0_0402_5% 16 18 BATDRV_CHGR 10_0402_1% PCB25
/TB_STAT BATDRV 0.1U_0402_25V6
29 17 BATSRC_CHGR 1 2
PWPD BATSRC
CPU_PMON <58,82> BATT_TEMP
<97> CPU_PMON CHG_TB_STAT BQ24800RUYR_WQFN28_4X4
+6V_CHG_REGN
1
0.1U_0402_25V6
0.1U_0402_25V6
3.3*100/(316+100)=0.79 H/L Side AON7506 SB000010A00
@ PRB46 PCB35 @ PRB36
ICHG= 0.79 /(20*0.01)=3.95A Rds(on):13~15.8mohm
1
PCB26
PCB27
30.1K_0402_1% 100P_0201_50V8J 10K_0402_1%
2
1 2 Vgs=20V
3 3.3*78.7/(316+78.7)=0.66 Vds=30V 3
2
2
ICHG= 0.66 /(20*0.01)=3.28A ID= 10.5A (Ta=70C)
+6V_CHG_REGN +3VS
1
PRB32
10K_0402_1%
ACDET PRB34
1
For 4S per cell 4.35V battery 10K_0402_1%
2
1 2 ACPRN_CHGR @ PRB22 @ PRB23

<58> ACIN
10K_0402_1% 10K_0402_1%
1
4S_BATT@
PRB30 PRB35
2
2M_0402_1% DGPU_AC_DETECT <33,58,59>
12K_0402_1%
1 2
@ PQB21A
6
@4S_BATT@ D 2N7002KDW_SOT363-6
PRB16 2
0_0402_5% G
2
1
S
1
@ PQB26 @ PQB21B
1
3
4S_BATT@ RUM001L02_VMT3 D 2N7002KDW_SOT363-6
PQB25 H_PROCHOT# 2 ACIN 5
4S_BATT@ PRB27 LTC015EUBFS8TL_UMT3F G
100K_0402_1%
4 1 2 2 S 4
4
<58> BATT_4S
3
4S_BATT@
3
1
PQB22 D
2
<11,16,38,58,69,78,89> SUSP# G
S
L2N7002SWT1G_SOT323-3
3

charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
Custom
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
Size
5 4 3 2 1
A B C D E
+19VB
EMI@ PL311 @0@ PR303 PC301
FBMA-L11-201209-800LMA50T 0_0402_5% 0.1U_0402_25V7K
1 2 +19VB_3V BST_3V 1 2 1 2
2200P_0402_50V7K
PU301
1
SY8388BRHC_QFN16_2P5X2P5
EMI@ PC302
@EMI@ PC303
EMI@ PC304
Choke 1.5uH SH000016700 (common part)
10U_0603_25V6M
10U_0603_25V6M
0.1U_0402_25V6
0.1U_0402_25V6
1
1
@ PC305
PC306
(Size:6.8 x 6.47 x 3 mm)
IN3
IN2
IN1
BS
PL301
1.5UH_9A_20%_7X7X3_M (DCR:14m~15m Ohm)
2
LX_3V 5 17
LX EP LX_3V 1 2
+3VALWP
1 16 1
6 LX2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
+3VALWP
1
GND
15 @EMI@
@ PC307
PC308
PC309
@ PC310
PC311
PC312
LX1 PR304
2
7 4.7_1206_5%
PG
13V_SN
14
2
GND1
PR305
100K_0402_5% 8 13 +3VLP @EMI@
1
EN2 LDO PC314
2
680P_0402_50V7K
TEST
PC313
OUT
EN1
2
SPOK_3V 4.7U_0402_6.3V6M
FF
<11,58,90> SPOK_3V
2
ENLDO_3V5V
Iocp=10A
10
11
12
3.3V LDO 150mA~300mA
EN1 and EN2 dont't floating
<58> 3V_EN
PC315 PR306
1000P_0402_50V7K 1K_0402_5%
PR301 3V_FB 1 2 1 2 @ PJ302
499K_0402_1% +3VALWP 1 2 +3VALW
ENLDO_3V5V 1 2 1 2
ENLDO_3V5V +19VB JUMP_43X118
1
150K_0402_1%
PR302
2 2
PR503
100K_0402_5%
1 2
+3VLP
PR501 PC501
10_0603_1% 0.1U_0603_25V7K
BST_5V 1 2 BST_5V_R 1 2
<11,43,58> SPOK_5V
PU501 Choke 1.5uH SH000016700 (common part)

+19VB EMI@ PL511 +19VB_5V (Size:6.8 x 6.47 x 3 mm)
FBMA-L11-201209-800LMA50T 7 (DCR:14m~15m Ohm)
1 2 5 PGOOD
VIN 1 PL501
PC506 BOOT 1.5UH_9A_20%_7X7X3_M
2200P_0402_50V7K
0.1U_0402_25V6
0.1U_0402_25V6
2 1 VCC_5V 11
VCC 2 LX_5V 1 2
10U_0603_25V6M
10U_0603_25V6M
+5VALWP
1
LX
@EMI@ PC517
PC502
PC503
EMI@ PC504
@EMI@ PC505
2.2U_0402_6.3V6M 6 3
EN LX
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2
1
10
PR502
4.7_1206_5%
VOUT
EMI@
PC507
PC508
PC509
PC510
PC511
PC512
PC521
2
2
12 9
LDO5 FF @ @
2
8
AGND
15V_SN
4
5V_EN PGND
<43> 5V_EN
680P_0402_50V7K
Fsw : 750K Hz RT6258CGQUF_UQFN12_3X3
3 3
EMI@
PC513
Iocp(min)=9A
2
+5VLP
5V LDO 150mA
4.7U_0402_6.3V6M
PC514
1
2
PR506 PC515 @ PJ502

PR504 1K_0402_1% 1000P_0402_50V7K +5VALWP 1 2 +5VALW
2.2K_0402_5% 5V_FB 1 2 5V_FB_1 1 2 1 2
1 2 JUMP_43X118
<58> EC_ON
@0@ PR505
1 2
<58,77,83> MAINPWON
0_0402_5%
5V_EN
1M_0402_1%
1
1
PR507
PC516
4.7U_0402_6.3V6M
2
2
4 4

+3VALW/+5VALW
Custom 1A
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4
2016/11/03
Compal Secret Data
2017/06/14 Title
DDR4
Custom 1A
A B C D E
A B C D E
Module model information

TPS51486_V1.mdd
1 1
2.5x2x1.2
Rdc=190~220 mohm OCP > 1.05A
Idc=1.05A ; Isat=1.5A OVP = 120%
FSW = 580KHz
1 2SNUB_DDR_2.5V 1 2 PG=93%
EMI@ PRM19 EMI@ PCM20 +2.5VP

4.7_0805_5% 680P_0603_50V8J
SW_VPP_DDR 1 2
PLM1
+5VALW_DDR G6020MC1D@ PUM1 4.7UH_MLN-YT12N4R7M-M1L__1.9A_20%
22U_0603_6.3V6M
1
G6020MC1D_AQFN18_3X3
PCM1
2
1
2.2_0402_5%
PRM20
TPS51486A@
PUM1
TPS51486ARJER_VQFN18_3X3 OCP > 8.2A
PCM2
5x5x3 OVP = 120%
2
+5VALW +5VALW_DDR 2.2U_0402_10V6M
Rdc=11~12 mohm
1 2 13
VCC_5V SW_VPP
15 FSW = 600KHz
@ PJM2 Idc=8.5A ; Isat=14A PG=93%
JUMP_43X39 1 2 SNUB_DDR_1.2V 1 2
1 2 14 12 Ipeak=6.8A
1 2 PVIN_VPP VPPSNS PRM2 PCM4
5.1_0603_5% 0.1U_0402_25V6 EMI@ PRM1 EMI@ PCM3
18 BST_DDR
BST 1 2 BST_DDR_R 1 2 4.7_0805_5% 680P_0603_50V8J +1.2VP
10U_0402_10V6M
0.1U_0402_10V6K
7 PLM2
PVIN 17 LX_DDR
SW 3 2
1
1
PCM21
PCM5
+1.2VP
PRM18 4 1
1 5
@EMI@
2
2 VLDOIN VDDQSNS VDDQSNS_DDR 1 2
1
2
10U_0402_6.3V6M
2 2
+3VALW 8 VTT 0_0402_5% 0.68U_PCMC063TR68MN_15.5A_20%
PCM12
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PGOOD
+19VB +19VB_DDR
1
PVIN=4.5~24V 4
VTTSNS
1
2
PCM6
PCM7
PCM8
PCM9
PCM10
PCM11
6 VTTREF_DDR
VTTREF
2
PLM3 EMI@
0.47U_0402_6.3V6K
5A_Z80_0805_2P EN_DDR 11
0.6V:
SLP_S4 Current limit=1~1.7A
1
1 2 PRM3 16
PCM13
2
PGND_VPP 9
100K_0402_5% PGND
@EMI@
EMI@
EN_0.675VSP
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
10 3 +0.6VSP
VTT_CNTL AGND
2
1
2
0.1U_0402_25V6
1
1
PCM14
PCM15
PCM16
PCM17
10U_0603_6.3V6M
1
1
PCM18
PCM25
TPS51486A@ PRM22
2
1
0_0402_5%
PCM22
G6020MC1D@ PRM23
2
0_0402_5%
2
@0@ PRM5 0_0402_5%
1 2
<16,58,66> SYSON 1
@ PCM24
SLP_S4/VTT_CNTL High-level voltage>1.6V 0.1U_0402_10V7K 1
@ PJM4
2
+1.2VP +1.2V_VDDQ
2
SLP_S4/VTT_CNTL Low-level voltage<0.5V @0@

PRM10
1 2
JUMP_43X118
1 2
<8> SM_PG_CTRL
0_0402_5%
1 2
<11,16,38,58,69,78,85> SUSP# PRM21 PJM5 @
@ 0_0402_5% 1 2
1
@ PCM23 +0.6VSP 1 2 +0.6VS_VTT

JUMP_43X39
0.1U_0402_10V7K
2
3 3
@ PJM3
1 2
+2.5VP 1 2 +2.5V
JUMP_43X79
4 4

DDR4
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
Custom
A B C D E
A B C D E
PR1809
100K_0402_5%
2 1
+3VALW
Choke 1uH SH00000Z200 (Common Part)
+1.8V_PG <95> (Size:5.0 x 4.7 x 3 mm)
(DCR:13m~14m Ohm)
PL1802
+19VB 5A_Z80_0805_2P
PU1801
1 2 +19VB_1.8VALWP 2 9 @0@ PR1808 PC1810 @EMI@ PR1802 @EMI@ PC1806
IN PG 0_0402_5% 0.1U_0402_25V7K 4.7_1206_5% 680P_0402_50V7K
EMI@ 3 1 1.8VALWP_BST 1 2 1 2 1 2 1.8VALWP_SNB 1 2
10U_0603_25V6M
10U_0603_25V6M
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_50V7K
IN BS
1
@ PC1801
PC1802
4 6
EMI@ PC1816
EMI@ PC1815
@EMI@ PC1808
1 IN LX 1
2
5 19 PL1801
IN LX 1UH_6.6A_20%_5X5X3_M
1.8VALWP_LX
@0@ PR1811
1
0_0402_5%
2
7
GND LX
20 1 2
+1.8VALWP
330P_0402_50V7K
<58> EC_1.8V_EN 8 14 1.8VALWP_FB
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
GND FB
PC1803
1
1
18 17 1.8VALWP_LDO
(R1)
PC1805
PC1817
PR1801 GND VCC
@
PC1812
PC1813
PC1814
PC1804
1
1
1 2 11 10 PC1809
2
<11,58,87> SPOK_3V EN NC 2.2U_0402_6.3V6M PR1803
0_0402_5% 1.8VALWP_ILMT 13 12 20.5K_0402_1% @ @
2
ILMT NC
1
15 16
1K_0402_1%
+3VALW
2
BYP NC
1
PR1805
PR1810
1M_0402_1% @ PC1811 21
PAD
1
0.47U_0402_6.3V6K
2
Vout=0.6V* (1+Rup/Rdown)
2
1.8VALWP_LDO PC1807 SY8286RAC_QFN20_3X3
Vout=0.6V*(1+20.5/10)
2
1U_0402_6.3V6K FB = 0.6V =1.83V (x1.017)
1
@0@ PR1807 @ PJ1801

0_0402_5% JUMP_43X79
1
1 2
PR1804 +1.8VALWP 1 2 +1.8VALW_PRIM
2
1.8VALWP_ILMT 10K_0402_1%
(R2)
1
2
PR1806 8286RAC
10K_0402_5% Min Typ Max
ILMT='0' 6.5A 7.5A 8.5A
2
ILMT=Floating 9.5A 10.5A 11.5A

ILMT='1' 12.5A 13.5A 14.5A
2 2
+3VALW
1
PJ1851 @ @ PJ1852
1
JUMP_43X39 JUMP_43X39
3 3
1 2
+1.8VP_PROC 1 2 +1.8V_PROC
2
2
1
@ PC1852
@ PU1851
22U_0603_6.3V6M VIN_1.8VP_PROC 4 1
+1.8VP_PROC
2
VIN VOUT
2
PR1851 GND
@
1 2 EN_1.8VP_PROC 3 5
EN EP
1
<11> +1.8V_PROC_EN @ PC1851
0_0402_5%
1
AP7343D-18FS4-7B_X2-DFN1010-5 1U_0402_6.3V6K
@ PR1852 SA0000DGX00 2
1M_0402_5%
2
Main : SA0000DGX00
AP7343D-18FS4-7B
300mA
2nd : SA0000EA900
G9103-180N61U
200mA
4 4

1.5VS/2.5V
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
Size
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
Size
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
Size
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

HH514 MB LA-L972P
C 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1.0VS_VCCIO
5 4 3 2 1
5 4 3 2 1
Main Func = +VCCIN_AUX

Module model information +VCCIN_AUX ADL-P_45W
RT6543A_V1A.mdd for IC portion Vout 1.8V
IPL2(TDC) = 17A
RT6543A_V1B.mdd for SW portion Peak Current = 34.2A(ICCmax)
OCP: 51A
OVP: VID+0.36V (max 2V)
FSW= 600KHz
+19VB_CPU DC LL=2.0m ohm
AC LL=3.4m ohm
D D
2200P_0402_50V7K
0.1U_0402_25V7K
10U_0603_25V6M
10U_0603_25V6M
BST_AUX_R +19VB_CPU ADL-P_28W/15w
+VCCIN_AUX
1
PCA06
PCA21
EMI@ PCA11
EMI@ PCA28
1
1
PRA12
ICCMAX=51A
2
2.2_0603_5% PCA230 @0@
0.1U_0402_25V6 PRA13 0_0805_5% TDC=14A
2
OCP=41.6A
2
OCP is Lowside MOSFET Rdson sense
2
DC LL=2.0m ohm
BST_AUX
AC LL=3.4m ohm
0.1U_0402_25V6
1
226K x1.2
PCA231
261K x1.4 UG_AUX
2
PUA01
10
RT6543AGQW_WQFN20_3X3
Main: CYNTEC
PRA16
Package: 6.86x 6.47 x 3
BOOT
261K_0402_1%
Idc=38A, Isat=45A
2
1 2 CS_DSI_RT6543 1 20 VSYS_RT6543
CS_DIS VSYS PQA01 Rdc=0.90mohm +/-5%
+5VALW
G1
D1
AONY36352_DFN5X6D-8-7 SH00001EF00
@0@ PRA14 0_0603_5%
LX_AUX 7 PLA01
1 2 PVCC_RT6543 15 11 UG_AUX D2/S1 0.15UH_STPI0603-R15M-T4-TW_35A_20%
PVCC UGATE LX_AUX 1 4
+VCCIN_AUX
S2-3
S2-2
S2-1
2 1
G2
PCA232 1U_0402_6.3V6K 2 3
PRA15 5.1_0603_5% Place near to VR
1
1 2 VCC_RT6543 16 12 LX_AUX
3K_0402_1%
VCC PH
PRA17
1
2 1 LG_AUX
PCA233 1U_0402_6.3V6K PRA18 EMI@ PRA11
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
100K_0402_1% HBM 500V 4.7_1206_5%
High > 1V
2
1 2 4 13 LG_AUX <97> AUX_ISENP <97> AUX_ISENN
+3VALW
PCA30
PCA07
C PGOOD LGATE C
Low <0.4V
2
1ISENSEP_AUX_R
<59> VCCIN_AUX_VR_PG
@0@
PRA19
1
SNB_AUX
1 2 EN_RT6543 19 14 PRA20
<90> +1.8V_PG EN PGND
1
EMI@ PCA24 0_0402_1%
1
@ 390P_0402_50V7K
0_0402_1% PCA234 @0@ 0_0402_1%
3K_0402_1%
PRA21
2
0.1U_0402_25V6
2
17 2 ISENSEP_RT6543 1 2 ISENSEP_RT6543_R
PRA22
<11,17> VCCIN_AUX_CORE_VID1 VID1 ISENSEP
PRA24 PRA25
@0@ 0_0402_1%
PRA23
2
+3VALW 18 3 ISENSEN_RT6543 1 2 ISENSEN_RT6543_R
1 2 1 2
ISENSEN_RT6543_R
<11,17> VCCIN_AUX_CORE_VID0 VID0 ISENSEN
+VCCIN_AUX 953_0402_1% 1.54K_0402_1%
PCA235
1 2 PHA1
@ PRA26
PRA27 PRA28 ISENSEN_AUX_NTC
100K_0402_1% 0.1U_0402_25V6 1 2
1 2 FSWSEL_RT6543 9 8 VOUT_RT6543 1 2 2 1
+5VALW FSWSEL VOUT
10K_0402_1%_B25/50 3370K
1
ISENSEP_RT6543_R
@PRA29 0_0402_1% 100_0402_1%
B=3435(B25/85)
100K_0402_1% PCA236 @0@ PRA32 PCA237 @ PRA33
1
5 COMP_RT6543 1 2 1 2 1 2 1 2
COMP 10K_0402_1% 1.6K_0402_1% 1 2
2
PRA30 PRA31 2200P_0402_50V7K 390P_0402_50V7K

10K_0402_1% 10K_0402_1% PCA238
PCA239 27P_0402_50V8J PRA34 6.34K_0402_1% 0.1U_0402_25V6
2
VCCIN_AUX_CORE_VID1 FB_RT6543
6 1 2 1 2
VCCIN_AUX_CORE_VID0
5V: 800KHz FB
Float: 600KHz @0@

PRA38
GND: 400KHz
1
7 RGND_RT6543 1 2
RGND VSS_SENSE_VCCIN_AUX <17>
AGND
@ PRA36 @ PRA37
B 10K_0402_1% 10K_0402_1% 0_0402_1% B
1
VCC_SENSE_VCCIN_AUX <17>
PRA39
2
21
1
100_0402_1%
PCA240
2 @ PCA241 0.1U_0402_25V6
2
1 2
0.082U_0402_16V7K
330P_0402_50V7K
@ PCA242
2 1
VCCIN_AUX VID Follow Intel PDG Rev0.71 @PCA243
1 2
VID1 VID0 +VCCIN_AUX 0.01UF_0402_25V7K

Voltage
0 0 0
0 1 1.1
1 0 1.65
1 1 1.8
A A

5 4 3 2 1
5 4 3 2 1
D D
+VCCIN_AUX Output CAP :

330uF_2.5V*1
22uF_0603*18
CPU Primary Side CPU Secondary side

+VCCIN_AUX +VCCIN_AUX
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PCA214
PCA202
PCA210
PCA215
1
PCA201
PCA221
PCA218
PCA213
PCA224
PCA203
PCA219
PCA217
PCA209
PCA208
2
2
C C
22U_0603_6.3V6M
22U_0603_6.3V6M
330U_D2_2.5VY_R9M
1
PCA220
PCA204
1
+
PCA229
2
2
B B
A A

PWR_VCCIN_AUX DECOUPLING
5 4 3 2 1
5 4 3 2 1
ADL-P_45W
Main Func = CPU (IA/GT) Module model information
+VCC_CORE +VCC_GT +VCCIN_AUX
28W@ PRZ103 15W@ PRZ103
RT3624BE_V1A.mdd IC
VREF06_RT3624BE 44.2K_0402_1% 80.6K_0402_1% RT3624BE_V1B.mdd SW
ICCMAX=120A ICCMAX=55A ICCMAX=34.2A
+3VALW +1.05V_PROC
TDC=71A TDC=30A TDC=17A
80.6K_0402_1%
OCP=156A OCP=65A OCP=44.5A

332K_0402_1%
41.2K_0402_1%
38.3K_0402_1%
11.5K_0402_1%
11.5K_0402_1%
1
1
DC LL=2.3m ohm DC LL=3.2m ohm DC LL=2.0m ohm
PRZ103
PRZ104
PRZ105
PRZ106
PRZ107
PRZ108
1
AC LL=2.3m ohm AC LL=3.2m ohm AC LL=3.4m ohm
75_0402_1%
10K_0402_1%
PRZ132
@ PRZ131
2
2
45W@
2
VR_HOT# 1 2 VR_HOT#_RT3624BE
<58> VR_HOT#
D
@0@ PRZ133 0_0402_5% Switching Freqency= 600K Hz D
<58> VR_PWRGD
VR_PWRGD 1 2 VR_READY_RT3624BE ADL-P_28W
<98>
<98>
<98>
<98>
<99>
<99>
PWM1G
PWM2G
PWM3C
PWM4C
PWM2C
PWM1C
@0@ PRZ134 0_0402_5%
SET1_RT3624BE @ PRZ161
ICCMAX=109A ICCMAX=55A ICCMAX=32A
SET2_RT3624BE
100K_0402_5%
VCC_RT3624BE1 2
SET3_RT3624BE PRZ162
100K_0402_5%
DC LL=2.3m ohm DC LL=3.2m ohm
0_0402_5%
SET4_RT3624BE 1 2
DC LL=2.0m ohm
PHZ101 AC LL=2.3m ohm AC LL=3.2m ohm AC LL=3.4m ohm
PRZ167 0_0402_5%
100K_0402_1%_NCP15WF104F03-X PRZ101
Close IA phase1 MOSFET
PRZ163 0_0402_5%
1
TSEN_MAIN_RT3624BE_R 1 2 TSEN_MAIN_RT3624BE 2.2_0402_5% VREF06_RT3624BE = 0.6V
1
1 2
+5VALW
2 PRZ166 1
DRVEN_CPU <98,99>
1
1 2 PCZ101
Switching Freqency= 600K Hz
2
PRZ109 4.7U_0402_6.3V6M
PRZ168 0_0402_5%
2
2
110K_0402_1%
ADL-P_15W
0_0402_5%
1
PHZ102
PRZ164 0_0402_5%
100K_0402_1%_NCP15WF104F03-X PRZ160
45W_PHASE@
1
TSEN_AUXI_RT3624BE_R 1 2 TSEN_AUXI_RT3624BE 0_0402_5%
Close GT phase1 MOSFET
1
1 2 VR_ENABLE_RT3624BE @0@ PRZ314
1 2
<11,58> VR_ON
2
@ PCZ117 0_0402_5%
28W_PHASE@ PRZ165
28W@ PRZ111 PRZ110 15W@ PRZ111 2.2U_0402_6.3V6M
10K_0402_1%
7.5K_0402_1%
7.87K_0402_1%
32.4K_0402_1%
32.4K_0402_1%
2
1
7.5K_0402_1% 110K_0402_1% 25.5K_0402_1% 1 2

12.4K_0402_1%
PWM3_MAIN_RT3624BE 2
ICCMAX=80A ICCMAX=40A ICCMAX=32A
PRZ111
PRZ112
PRZ315
PRZ316
PRZ115
PRZ116
PRZ159
PWM4_MAIN_RT3624BE
PWM2_MAIN_RT3624BE
PWM1_MAIN_RT3624BE
PWM1_AUXI_RT3624BE
PWM2_AUXI_RT3624BE
2.2_0603_1%
1 2
DRVEN_RT3624BE
+19VB_CPU
2
SET2_RT3624BE_L 2
45W@
VCC_RT3624BE
PCZ116
SET1_RT3624BE_L
SET3_RT3624BE_L
SET4_RT3624BE_L
AU1_ANS_EN
1TSEN_MAIN_RT3624BE_L
1TSEN_AUXI_RT3624BE_L
28W@ PRZ118
4.3K_0402_1%
15W@ PRZ118
100_0402_1%
0.47U_0402_25V6K
1 2 VIN_RT3624BE DC LL=2.8m ohm DC LL=3.2m ohm DC LL=2.0m ohm
AC LL=2.8m ohm AC LL=3.2m ohm AC LL=3.4m ohm
PUZ101
RT3624BEGQW_WQFN52_6X6
53
52
51
50
49
48
47
46
45
44
43
42
41
40
PRZ172 PRZ171
Switching Freqency= 600K Hz
DRVEN_F
GND
VRON
VCC
ANS_EN
PWM3_MAIN
PWM4_MAIN
PWM2_MAIN
PWM1_MAIN
VIN/VSYS
PWM1_AUXI
PWM2_AUXI
DRVEN
DBLR_PS
C 887_0402_1% 887_0402_1% C
1
1 2 ISEN1PC_R 1 2 PRZ141 PRZ142

0_0402_1%
0_0402_1%
1K_0402_1%
100_0402_1%
432_0402_1%
3.16K_0402_1%
<98> ISEN1PC
2.61K_0402_1% 56.2K_0402_1%
PRZ118
PRZ119
PRZ120
PRZ121
PRZ122
PRZ123
1
ISEN3P_CORE_RT3624BE 1 39 AUX_ISENN IMON_AUX_RT3624BE 1 2IMON_AUX_RT3624BE_R 1 2
ISEN3P_MAIN ISENN_AUX VREF06_RT3624BE
1
PCZ118 @0@ PRZ170 ISEN1P_CORE_RT3624BE
ISEN3N_CORE_RT3624BE 2 38 ISENP_AUX_RT3624BE 1 2
2
0.1U_0402_25V6 2 0_0402_5% PRZ169 ISEN3N_MAIN ISENP_AUX

680_0402_1% ISEN4N_CORE_RT3624BE 3 37 ISEN1N_GT_RT3624BE @ PCZ107
2
45W@ PCZ119 1 2 ISEN1N_CORE_RT3624BE ISEN4N_MAIN ISEN1N_AUXI 0.1U_0402_6.3V7K @ PCZ111
<98> ISEN1NC ISEN4P_CORE_RT3624BE ISEN1P_GT_RT3624BE
0.1U_0402_25V6 4 36 0.1U_0402_6.3V7K
PRZ176 PRZ175 1 2 ISEN4P_MAIN ISEN1P_AUXI 1 2 PRZ150
887_0402_1% 887_0402_1% ISEN2P_CORE_RT3624BE 5 35 ISEN2P_GT_RT3624BE 100_0402_1%
1 2 ISEN2PC_R 1 2 ISEN2P_CORE_RT3624BE ISEN2P_MAIN ISEN2P_AUXI VSEN_AUXI_RT3624BE 1 2
<98> ISEN2PC ISEN2N_CORE_RT3624BE 6 34 ISEN2N_GT_RT3624BE PCZ112
+VCC_GT
ISEN2N_MAIN ISEN2N_AUXI
1
100P_0402_50V8J PCZ113 390P_0402_50V7K

1
PCZ120 @0@ PRZ174 ISEN1N_CORE_RT3624BE 7 33 FB_AUXI_RT3624BE COMP_AUXI_RT3624BE 1 2 1 2 @0@ PRZ149 0_0402_5%

ISEN1N_MAIN FB_AUXI
0.1U_0402_25V6 0_0402_5% PRZ173 ISEN1P_CORE_RT3624BE 8 32 COMP_AUXI_RT3624BE 1 2
VCC_SENSE_VCCIN_GT <16>
2
680_0402_1% ISEN1P_MAIN COMP_AUXI 1 2 1 2

2
PCZ121 1 2 ISEN2N_CORE_RT3624BE FB_MAIN_RT3624BE 9 31 VSEN_AUXI_RT3624BE @0@ PRZ153 0_0402_5%

<98> ISEN2NC FB_MAIN VSEN_AUXI
0.1U_0402_25V6 45W@ PRZ151 PRZ152 1 2
1 2 COMP_CORE_RT3624BE 10 30 RGND_AUXI_RT3624BE FB_AUXI_RT3624BE 18.7K_0402_1% 7.32K_0402_1%
VSS_SENSE_VCCIN_GT <16>
COMP_MAIN RGND_AUXI
DIS_IA_PH3@PRZ324 10K_0402_1% VSEN_MAIN_RT3624BE 11 29 CPU_PMON PRZ154 100_0402_1%
1 2 VSEN_MAIN PSYS RGND_AUXI_RT3624BE 1 2
28W_PHASE@ PRZ180 28W_PHASE@ PRZ179 +5VALW RGND_MAIN_RT3624BE 12 28 IMON_AUX_RT3624BE
887_0402_1% 887_0402_1% RGND_MAIN IMON_AUX 28W@ PRZ151 15W@ PRZ151
ISEN3PC_R ISEN3P_CORE_RT3624BE VREF_SPS_RT3624BE SET4_RT3624BE
TSEN_MAIN
IMON_MAIN
1 2 1 2 13 27 18.7K_0402_1% 26.1K_0402_1%
TSEN_AUXI
IMON_AUXI
VR_READY
<98> ISEN3PC VREF_SPS_RT3624BE VREF_SPS SET4
VR_HOT
1
VREF_SPS_RT3624BE = 1.3V
ALERT
1
VREF
VCLK
SET1
SET2
SET3
VDIO
28W_PHASE@ PCZ122 @0@ PRZ178 0_0402_5%
1
PCZ130
0.1U_0402_25V6 28W_PHASE@ PRZ177
2
680_0402_1% 0.22U_0402_10V6K
2
14
15
16
17
18
19
20
21
22
23
24
25
26
PCZ123 1 2 ISEN3N_CORE_RT3624BE PRZ189 PRZ190
<98> ISEN3NC
28W_PHASE@ 0.1U_0402_25V6 887_0402_1% 887_0402_1%
1 2 DIS_IA_PH3@ PRZ181 ISEN1P_GT_RT3624BE 1 2 ISEN1PG_R 1 2
ISEN1PG <99>
10K_0402_1%
disable phase3, ISEN3P/ISEN3N to 5V
1
1 2
+5VALW
1
VR_READY_RT3624BE
VCLK_RT3624BE
ALERT#_RT3624BE
VREF06_RT3624BE
@ PRZ188 PCZ126
SET1_RT3624BE
SET2_RT3624BE
SET3_RT3624BE
VDIO_RT3624BE
VR_HOT#_RT3624BE
TSEN_MAIN_RT3624BE
IMON_MAIN_RT3624BE
TSEN_AUXI_RT3624BE
DIS_IA_PH4@ PRZ325
IMON_GT_RT3624BE
10K_0402_1% PRZ187 3.74K_0402_1% 0.1U_0402_25V6
2
45W_PHASE@ PRZ185 45W_PHASE@ PRZ184 1 2 680_0402_1%
+5VALW
2
887_0402_1% 887_0402_1% ISEN1N_GT_RT3624BE 1 2 PCZ127
ISEN4PC_R ISEN4P_CORE_RT3624BE ISEN1NG <99>
1 2 1 2 0.1U_0402_25V6
<98> ISEN4PC
PRZ326 1 2
1
10K_0402_5%
Close CPU
1
45W_PHASE@ PCZ124 @0@ PRZ183 0_0402_5% 1 2

Vpsys max is 1.6V +5VALW 28W_PHASE@ PRZ193 28W_PHASE@ PRZ194
0.1U_0402_25V6 45W_PHASE@ PRZ182 DIS_GT_PH2@ 887_0402_1% 887_0402_1%
2
B 680_0402_1% ISEN2P_GT_RT3624BE 1 2 ISEN2PG_R 1 2 B

VREF06_RT3624BE ISEN2PG <99>
2
45W_PHASE@ PCZ125 1 2 ISEN4N_CORE_RT3624BE

<98> ISEN4NC
1
0.1U_0402_25V6
3.9_0402_1%
CPU_PMON <85>
1
1 2 DIS_IA_PH4@ PRZ186 @ PRZ192 28W_PHASE@ PCZ128
PRZ102
12.4K_0402_1%
10K_0402_1%
PRZ317
1 2 28W_PHASE@ PRZ191 3.74K_0402_1% 0.1U_0402_25V6
+5VALW disable phase4, ISEN4P/ISEN4N to 5V
2
680_0402_1%
2
ISEN2N_GT_RT3624BE 1 2 28W_PHASE@ PCZ129 ISEN2NG <99>
PSYS_RT3624BE_L 2
@ PCZ108 0.1U_0402_25V6
0.1U_0402_6.3V7K PRZ195 1 2
0.1U_0402_6.3V7K
PRZ144 1 2 10K_0402_5%
1
100_0402_1% VREF06_RT3624BE_R 1 2
@ PCZ103
+VCC_CORE 1 2 VSEN_MAIN_RT3624BE +5VALW
1
PCZ110 PCZ109 PCZ102 DIS_GT_PH2@
2
390P_0402_50V7K 82P_0402_50V8J
@0@ PRZ143 0_0402_5% 1 2 1 2 COMP_CORE_RT3624BE 0.47U_0402_6.3V6K
disable phase2, ISEN2P_GT/ISEN2N_GT to 5V.
2
1 2
<15> VCC_SENSE_VCCIN 1 2 1 2
1
@0@ PRZ147 0_0402_5%
AUX choke sense
0_0402_5%
1 2 15W@ PRZ146 28W@ PRZ146 PRZ146 45W@ PRZ145
PRZ124
<15> VSS_SENSE_VCCIN 11K_0402_1% 8.2K_0402_1% 8.2K_0402_1% 27K_0402_1% FB_MAIN_RT3624BE
PRZ148 45W@
100_0402_1% 28W@ PRZ137 15W@ PRZ137
2
1 2 RGND_MAIN_RT3624BE 100_0402_1% 11.3K_0402_1% 28W@ PRZ135 15W@ PRZ135 PRZ155 PRZ156
28W@ PRZ136 15W@ PRZ136 3.6K_0402_1% 1K_0402_1% 1.05K_0402_1% 1.05K_0402_1%
2.61K_0402_1% 7.5K_0402_1% 1 2 AUX_ISENP_R 1 2
4 phase is 27K AUX_ISENP <95>
Close IA phase1 choke
1
3 phase is 28.7K
28W@ PHZ103 15W@ PHZ103 PRZ157
2 phase is 45.3K 28W@ PRZ145 15W@ PRZ145 10K_0402_1%_TSM0A103F34D1RZ 100K_0402_1%_B25/50 4250K
28.7K_0402_1% 45.3K_0402_1% 45W@ PHZ103 45W@ PRZ135 1.54K_0402_1%
10K_0402_1%_TSM0A103F34D1RZ 3.3K_0402_1%
2
NTC1P_MAIN 45W@ PRZ137 1 2 IMON_MAIN_RT3624BE AUX_ISENN_R
182_0402_1% ISENP_AUX_RT3624BE
1
1 2NTC1N_MAIN 1 2 45W@ PRZ136 1 2
1
2.55K_0402_1% PCZ114 PHZ105
1 2 @ PCZ105 PRZ158
Close AUX choke
VREF06_RT3624BE
45W@ PRZ138 0.1U_0402_6.3V7K 0.1U_0402_10V7K 10K_0402_1%_TSM0A103F34D1RZ
Close GT phase1 choke
2
33_0402_1% 4.64K_0402_1%
2
NTC1P_GT 45W@ PRZ140 1 2 IMON_GT_RT3624BE
IA phase opction,
2
10.5K_0402_1%
AUX_ISENN_RR
Please confirm FAE if the choke is changed. 1 2 NTC1N_GT 1 2 45W@ PRZ139 1 2
PHZ104 100K_0402_1%_B25/50 4250K 5.9K_0402_1%
1 2 @ PCZ106
VREF06_RT3624BE
0.1U_0402_6.3V7K
28W@ PRZ140 15W@ PRZ140 28W@ PRZ139 15W@ PRZ139
GT phase opction, 10.5K_0402_1% 11.3K_0402_1% 5.9K_0402_1% 7.5K_0402_1% 28W@ PRZ138 15W@ PRZ138
4 Phase 3 Phase 2 Phase Please confirm FAE if the choke is changed. +1.05V_PROC 33_0402_1% 1K_0402_1%
1
PRZ196
A A
0_0201_5%
PRZ145 20K 28.7K 45.3K 2 Phase 1 Phase
2
AUX_ISENN
AUX_ISENN <95>
PCZ115
56_0402_1%
100_0402_1%
45.3_0402_1%
0.1U_0402_10V7K
0.1U_0402_10V7K
PRZ135 2.15K 3.6K 1K PRZ138 80.6 1K
1
1 2
PCZ104
PRZ127
PRZ126
PRZ125
Need confirm choke DCR of AUX to setting

2
@ PRZ128
PRZ136 2.2K 2.61K 7.5K PRZ139 6.65K 7.5K 0_0402_5%
1 2 VCLK_RT3624BE
<15> SOC_SVID_CLK
PRZ129
0_0402_5%
PRZ137 536 100 11.3 PRZ140 12K 11.3K 1 2 VDIO_RT3624BE Security Classification Compal Secret Data Compal Electronics, Inc.
<15> SOC_SVID_DAT
PRZ130
0_0402_5%
IA ISENxP/ISENxN NA IA ISEN3P/ISEN3N GT ISENxP/ISENxN 1 2 ALERT#_RT3624BE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
1A
to 5V IA ISEN4P/ISEN4N IA ISEN4P/ISEN4N to 5V NA GT ISEN2P/ISEN2N <15> SOC_SVID_ALERT# AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
5 4 3 2 1
5 4 3 2 1
Main Func = +VCC_CORE
D D
+19VB_CPU
+19VB
EMI@ PLZ11
5A_Z80_0805_2P
1 2
EMI@ PLZ12 +19VB_CPU

5A_Z80_0805_2P
33U_25V_M
33U_25V_M
1 2
33U_D1_25VM_R6M
1 1 1
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
0.1U_0402_25V7K
1
1
EMI@ PCZ22
EMI@ PCZ23
PCZ24
PCZ25
PCZ65
PCZ259
+ + +
PCZ26
PCZ27
PCZ258
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
2
PCZ28
PCZ29
2200P_0402_50V7K
0.1U_0402_25V7K
1
1
non_Slim@ 2
non_Slim@ 2 2
PCZ30
PCZ31
PCZ68
28W_PHASE@ PCZ260
2
2
A3_Slim@
28W_PHASE@
28W_PHASE@
28W_PHASE@
28W_PHASE_EMI@
28W_PHASE_EMI@
PCZ258 for thin type NB
28W_PHASE@ PRZ42 SH00001Z500

PRZ44 SH00001Z500 2.2_0603_5%
2.2_0603_5% BOOT3_VCC 1 2 7*7*3
BOOT1_VCC 1 2 7*7*3 0.15uH
1 2 DRVH1_VCC-1 0.15uH 1 2 DRVH3_VCC-1 RDC=0.85 +/-5%m ohm
RDC=0.85 +/-5%m ohm 28W_PHASE@ Idc=35A
1
PCZ69 PRZ113 0_0603_5% Idc=35A 28W_PHASE@ PCZ49 PRZ45 0_0603_5%
0.1U_0402_25V6 0.1U_0402_25V6 28W_PHASE@ Isat=50A
Isat=50A
2
PUZ2 PUZ4 28W_PHASE@
2
PQZ1 PLZ1 PQZ3 28W_PHASE@ PLZ3
G1
D1
G1
D1
4 3 DRVH1_VCC 0.15UH_MMD-06CZER15MER3L__35A_20% 4 3 DRVH3_VCC 0.15UH_MMD-06CZER15MER3L__35A_20%
BOOT UGATE AONY36352_DFN5X6D-8-7 BOOT UGATE AONY36352_DFN5X6D-8-7
C VSW1_VCC 1 4 VSW3_VCC 1 4 C
5 2 VSW1_VCC 7 +VCC_CORE 5 2 VSW3_VCC 7 +VCC_CORE
<97> PWM1C PWM PHASE D2/S1 2 3 <97> PWM3C @28W_PHASE@PRZ47 0_0402_5% PWM PHASE D2/S1 2 3
@0@ PRZ461 2 0_0402_5% DRON_1 1 6 1 2 DRON_3 1 6
S2-3
S2-2
S2-1
S2-3
S2-2
S2-1
<97..99> DRVEN_CPU EN PGND <97..99> DRVEN_CPU EN PGND
G2
G2
1 2 8 7 near choke 1 2 8 7 near choke
+5VALW +5VALW
1
VCC LGATE 9 @EMI@ VCC LGATE 9 @28W_PHASE_EMI@
3
PRZ201 1_0603_1% GND PRZ114 28W_PHASE@ PRZ321 1_0603_1% GND PRZ53
RT9610CGQW_WDFN8_2X2 DRVL1_VCC RT9610CGQW_WDFN8_2X2 DRVL3_VCC
4.7_1206_5% 4.7_1206_5%
1
1
PCZ234 28W_PHASE@ PCZ235
ISEN1NC <97> ISEN3NC <97>
2
2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
2
2
SNB1_VCC SNB3_VCC
1
@EMI@ @28W_PHASE_EMI@
ISEN1PC <97> ISEN3PC <97>
PCZ62 PCZ47
680P_0402_50V7K 680P_0402_50V7K
2
+19VB_CPU
+19VB_CPU
B B
PCZ236
PCZ237
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
0.1U_0402_25V7K
1
1
PCZ53
PCZ42
45W_PHASE@ PCZ263
45W_PHASE@ PCZ264
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
0.1U_0402_25V7K
1
1
PCZ43 EMI@
PCZ44 EMI@
2
PCZ45
PCZ46
PCZ261
PCZ262
45W_PHASE_EMI@
45W_PHASE_EMI@
45W_PHASE@
45W_PHASE@
2
SH00001Z500
45W_PHASE@ PRZ48
2.2_0603_5% 7*7*3
BOOT4_VCC 1 2 0.15uH
PRZ50 1 2 DRVH4_VCC-1 RDC=0.85 +/-5%m ohm
SH00001Z500
2.2_0603_5%
7*7*3 Idc=35A
1
1 2 45W_PHASE@ PCZ71 PRZ52 0_0603_5%
0.15uH 0.1U_0402_25V6 45W_PHASE@ 45W_PHASE@ Isat=50A
2
1 2 DRVH2_VCC-1 RDC=0.85 +/-5%m ohm PUZ5
2
1
PCZ66 Idc=35A PQZ4 45W_PHASE@ PLZ4
G1
D1
0.22U_0603_25V7K PRZ54 0_0603_5% 4 3 DRVH4_VCC AONY36352_DFN5X6D-8-7 0.15UH_MMD-06CZER15MER3L__35A_20%
Isat=50A
1
PUZ3 BOOT UGATE VSW4_VCC 1 4

+VCC_CORE
2
PQZ2 PLZ2 5 2 VSW4_VCC 7

G1
D1
4 3 DRVH2_VCC 0.15UH_MMD-06CZER15MER3L__35A_20% <97> PWM4C PWM PHASE D2/S1 2 3

BOOT UGATE AONY36352_DFN5X6D-8-7
VSW2_VCC 1 4 1
45W_PHASE@ PRZ117 2 0_0402_5% 1 6
+VCC_CORE
S2-3
S2-2
S2-1
5 2 VSW2_VCC 7 <97..99> DRVEN_CPU EN PGND
G2
<97> PWM2C PWM PHASE D2/S1 2 3 1 2 8 7
+5VALW VCC LGATE near choke
1
@0@ PRZ551 2 0_0402_5% DRON_2 1 6 9 @45W_PHASE_EMI@
S2-3
S2-2
S2-1
3
<97..99> DRVEN_CPU Not to change short pad EN PGND 45W_PHASE@ PRZ322 1_0603_1% GND PRZ56
G2
1 2 8 7 DRVL4_VCC
+5VALW VCC LGATE near choke RT9610CGQW_WDFN8_2X2 4.7_1206_5%
1
1
9 @EMI@ 45W_PHASE@
6
GND ISEN4NC <97>

PRZ320 1_0603_1% PRZ43 PCZ72
2
RT9610CGQW_WDFN8_2X2 DRVL2_VCC 2.2U_0402_6.3V6M
4.7_1206_5%
2
1
PCZ58 45W_PHASE@ SNB4_VCC

ISEN2NC <97>
2
1
2.2U_0402_6.3V6M @45W_PHASE_EMI@
2
SNB2_VCC ISEN4PC <97>

PCZ74
680P_0402_50V7K
2
1
@EMI@
ISEN2PC <97>
PCZ60
680P_0402_50V7K
2
A A

5 4 3 2 1
5 4 3 2 1
Main Func = +VCC_GT
D D
+19VB_CPU
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
0.1U_0402_25V7K
1
1
EMI@ PCG03
EMI@ PCG04
PCG219
PCG05
PCG06
2
2
PRG9 SH00001Z500
2.2_0603_5%
BOOT1_VCCGT 1 2 7*7*3
1 2 DRVH1_VCCGT-1 0.15uH
RDC=0.85 +/-5%m ohm
1
PCG13 PRG10 0_0603_5% Idc=35A
0.1U_0402_25V6
Isat=50A
2
PUG1
2
PQG1 PLG4
G1
D1
4 3 DRVH1_VCCGT AONY36352_DFN5X6D-8-7 0.15UH_MMD-06CZER15MER3L__35A_20%
BOOT UGATE VSW1_VCCGT 1 4
5 2 VSW1_VCCGT 7 +VCC_GT
<97> PWM1G PWM PHASE D2/S1 2 3
@0@ PRG031 2 0_0402_5% DRON_1A 1 6
S2-3
S2-2
S2-1
C <97..99> DRVEN_CPU EN PGND C
G2
1 2 8 7 near choke
+5VALW VCC LGATE
1
9 @EMI@
3
PRG14 1_0603_1% GND PRG02
RT9610CGQW_WDFN8_2X2 DRVL1_VCCGT
4.7_1206_5%
1
PCG15
ISEN1NG <97>
2
2.2U_0402_6.3V6M
2
SNB1_VCCGT
1
@EMI@
ISEN1PG <97>
PCG216
680P_0402_50V7K
2
+19VB_CPU
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
PCG20
PCG21
2200P_0402_50V7K
0.1U_0402_25V7K
1
1
PCG22
PCG23
28W_PHASE@ PCG221
2
2
28W_PHASE_EMI@
28W_PHASE@
28W_PHASE@
28W_PHASE_EMI@
SH00001Z500
28W_PHASE@ PRG12
7*7*3
2.2_0603_5% 0.15uH
BOOT2_VCCGT 1 2 RDC=0.85 +/-5%m ohm
1 2 DRVH2_VCCGT-1
B
Idc=35A B
Isat=50A
1
28W_PHASE@ PCG14 PRG13 0_0603_5%

0.1U_0402_25V6 28W_PHASE@ 28W_PHASE@
2
PUG2
2
PQG2 28W_PHASE@ PLG02

G1
D1
4 3 DRVH2_VCCGT AONY36352_DFN5X6D-8-7 0.15UH_MMD-06CZER15MER3L__35A_20%
BOOT UGATE VSW2_VCCGT 1 4
5 2 VSW2_VCCGT 7 +VCC_GT
<97> PWM2G PWM PHASE D2/S1 2 3
PRG07 1 2 0_0402_5% DRON_2A 1 6
S2-3
S2-2
S2-1
<97..99> DRVEN_CPU @28W_PHASE@ EN PGND
G2
1 2 8 7 near choke
+5VALW VCC LGATE
1
9 @28W_PHASE_EMI@
6
PRG15 1_0603_1% GND PRG01

28W_PHASE@ RT9610CGQW_WDFN8_2X2 DRVL2_VCCGT
4.7_1206_5%
1
PCG12 28W_PHASE@ ISEN2NG <97>
2
2.2U_0402_6.3V6M
2
SNB2_VCCGT
28W_PHASE@
1
@28W_PHASE_EMI@
ISEN2PG <97>
PCG218
2 680P_0402_50V7K
A A

5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
Size
5 4 3 2 1
4
3
2
1
A
A
220uF*1
330uF*2
+VCC_CORE
1uF_0201*9
2 1 2 1 2 1
2
1
+
22uF_0603*20
PCZ201 PCZ220 PCZ225 PCZ232

330U_D1_2VY_R9M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2
1
+
PCZ219 PCZ211 PCZ214
PCZ202 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
330U_D1_2VY_R9M 2 1 2 1 2 1

+VCC_CORE Output CAP :
2
1
+
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PCZ203 2 1 2 1 2 1
220U_D7_2VM_R4.5M
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
Main Func = +VCCIN DECOUPLING

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
B
B

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
PCZ269 PCZ231
22U_0603_6.3V6M 22U_0603_6.3V6M
C
C
+VCC_GT
Issued Date
330uF*2
2 1 2 1
2
1
+
PCG222 PCG213
PCG209 22U_0603_6.3V6M 22U_0603_6.3V6M
330U_D1_2VY_R9M 2 1 2 1
22uF_0603*13
PCG223 PCG205
2
1
+
22U_0603_6.3V6M 22U_0603_6.3V6M
PCG208 2 1 2 1
330U_D1_2VY_R9M
PCG224 PCG204
22U_0603_6.3V6M 22U_0603_6.3V6M
2020/02/27
+VCC_GT Output CAP :
2 1 2 1
PCG225 PCG202
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1
PCG203
22U_0603_6.3V6M
2 1
PCG201
22U_0603_6.3V6M
D
D
2 1
PCG207
22U_0603_6.3V6M
Compal Secret Data
2 1
Deciphered Date
PCG210
22U_0603_6.3V6M
2 1
PCG214
22U_0603_6.3V6M
2021/12/31
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Date:
Title
Document Number
Monday, April 18, 2022

E
E
Sheet
PWR_CPU Decoupling CAP
101
of
HH514 MB LA-L972P
122
Rev
1A
4
3
2
1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

HH514 MB LA-L972P
C 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1.0VS_VCCIO
5 4 3 2 1
5 4 3 2 1
unmount PRV5 for 2 phase select
R1, R2, R3, R4, R5, C are GPU_B+

based on VGA type to set. R2
NVVDD_PSI <33>
GN18S@
PRV2 +3VS
0_0402_5%
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
0.1U_0402_25V6
2200P_0402_50V7K
<33> NVVDD_VID
20.5K_0402_1% @VGA@ PRV3
PCV2
PCV3
PCV4
PCV5
PCV6
PCV7
1
1
D
2 1
R1 VGA_EN 2 1 D
R1 R2 NVVDD1_EN <33,36>
105
105
GN18S@
10K_0402_5%
.1U_0402_16V7K
2
2
105
105
GN20S@ PRV4 GN20S@ PRV2 PRV4 0_0402_5%
R3
PRV1
PRV9
VGA_EMI@
@VGA_EMI@
10K_0402_5%
2
1
6.19K_0402_1% 20.5K_0402_1% GN18S@ 6.19K_0402_1%
@VGA@ PRV7
PCV1
@VGA@
2 1 2 1
PRV6 VGA@ VGA@ VGA@ VGA@
R3 R4
2
4.32K_0402_1%
@VGA@
@VGA@
1
2
1
GN20S@ PRV6 GN20S@ PRV11
1
2.8K_0402_1% 13.7K_0402_1%
GN18S@
R4 PRV11 UG1_VGA
R5 C
1
16.5K_0402_1% GN18S@
Rdc=0.85 mohm , Isat=50A, Idc=35A
1 2
GN20S@ PRV14 GN20S@ PCV8 PCV8 @VGA@ PQV1
C PRV15
2
274_0402_1% 4700P_0402_50V7K 4700P_0402_50V7K AONY36352_DFN5X6D-8-7 SH00001Z500
2
GN18S@ BST1_VGA 1 2 BST1_VGA_R VGA@
G1
D1
PRV14 VGA@ PLV1
R5 309_0402_1% +NVVDD1
0_0603_5% 7 LX1_VGA 1 4
2
D2/S1
1
NVVDD_GND_SENSE_R VGA@ PCV10
2 3
UGATE1
BOOT1
VID
PSI
EN
S2-3
S2-2
S2-1
2
0.1U_0402_25V7K
G2
@VGA_EMI@
4.7_1206_5%
2
0.15UH_MMD-06CZER15MER3L__35A_20%
REFADJ 6 20 LX1_VGA
PRV16
6
3
REFADJ PHASE1
1SNUB_VGA1 1
REFIN_VGA 7 19 LG1_VGA @VGA@
REFIN LGATE1 PRV17
0_0402_5%
VREF_VGA 8 PUV1 18 PVCC_VGA 1 2
VREF PVCC +5VS
1
RT8816BGQW_WQFN20_3X3 VGA@
1
VGA@ PRV19 TON_VGA 9 17 LG2_VGA PCV11 @VGA_EMI@

PCV12 VGA@ 499K_0402_1% TON VGA@ LGATE2 4.7U_0402_6.3V6M PCV13
2
1U_0201_6.3V6M GPU_B+ 2 1 680P_0603_50V7K
GPU_B+
2
2
OCSET/SS
10 16 GPU_B+
RGND PHASE2
UGATE2
PGOOD
BOOT2
VSNS
GND
C C
VGA@ PRV20 LX2_VGA
100_0402_1%
21
11
12
13
14
15
1 2 1
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
0.1U_0402_25V6
2200P_0402_50V7K
PCV15
PCV19
PCV20
PCV16
PCV17
PCV18
1
1
VGA@ PCV14 + VGA@ PCV431
@VGA@ 33U_25V_M
@VGA@ PRV21 0.1U_0402_25V7K
PRV22
2
<32> VSS_SENSE_NVVDD1 NVVDD_GND_SENSE_R 2
105
105
105
105
1 2
VGA_EMI@
@VGA_EMI@
BST2_VGA 1 2 BST2_VGA_R
UG2_VGA
0_0402_5% VGA@ VGA@ VGA@ VGA@
1
@VGA@ PCV21
0_0603_5% VGA@ PQV2
2
@VGA@ 1000P_0402_50V7K UG2_VGA AONY36352_DFN5X6D-8-7
PRV23
2
G1
D1
<32> VCC_SENSE_NVVDD1 1 2 VGA@ PLV9
NVVDD_SENSE_R +NVVDD1
0_0402_5% VGA_CORE_PG LX2_VGA 7 LX2_VGA 1 4
D2/S1
@VGA_EMI@
4.7_1206_5%
2
VGA@ 100_0402_1% @VGA@ PRV27 2 3
S2-3
S2-2
S2-1
1 2 VGA@ PRV26
PRV25
G2
+NVVDD1 1 2 10K_0402_1% 0.15UH_MMD-06CZER15MER3L__35A_20%
PRV24 2 1 +1.8VSDGPU_AON
3
Rdc=0.85 mohm
1SNUB_VGA2 1
0_0402_5%
@VGA@ PRV28
LG2_VGA
GB3 -64 =>GN20S

10K_0402_1%
2 1 +3VS
GB3B-64 =>GN18S @VGA_EMI@

1
PCV23
1
VGA@ PRV30 680P_0603_50V7K
2
VGA@ 137K_0402_1%
PCV24
2
0.033U_0402_16V7K
2
B B
GPU_B+ FBVDD_B+
VGA_EMI@ PLV11 VGA@ PRV74 VGA@ PRV75
+19VB HCB2012KF-121T50_0805
1 2 1 4 1 4
VGA_EMI@ PLV12 2 3 2 3
HCB2012KF-121T50_0805
1 2
0.005_1206_1% 0.005_1206_1%
<35> CSSP_B+ <35> CSSN_B+<35> CSSP_FBVDD <35> CSSN_FBVDD
NVVDD OCP :111A
A A

PWR_VGA_UP9512P
5 4 3 2 1
1 2 3 4 5
A A
B B
Reserve Page
C C
D D

PWR_+NVVDD1
1A
1 2 3 4 5
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

PWR_+NVVDD1
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

PWR_+NVVDD1
1A
5 4 3 2 1
A
B
C
D
5
5
2 1 2 1
2 1
VGA@ PCV47 VGA@ PCV31
+NVVDD1
VGA@ PCV65 2 1 1U_0402_10V7 10U_0402_6.3V6M

4.7U_0402_6.3V6M 2 1 2 1
2 1 @VGA@ PCV55
0.1U_0402_25V6 VGA@ PCV48 VGA@ PCV32
+NVVDD1
VGA@ PCV66 2 1 1U_0402_10V7 10U_0402_6.3V6M
4.7U_0402_6.3V6M 2 1 2 1
2 1 @ESD_VGA@ PCV56
0.1U_0402_25V6 VGA@ PCV49 VGA@ PCV33
VGA@ PCV67 2 1 1U_0402_10V7 10U_0402_6.3V6M
4.7U_0402_6.3V6M 2 1 2 1
2 1 @ESD_VGA@ PCV58
0.1U_0402_25V6 VGA@ PCV50 VGA@ PCV34
VGA@ PCV69 1U_0402_10V7 10U_0402_6.3V6M
4.7U_0402_6.3V6M 2 1 2 1

1U_0402_10V7 10U_0402_6.3V6M
GB3- 64 package
2 1 2 1

1U_0402_10V6K 10U_0402_6.3V6M
Under GPU Core
2 1 2 1
4
4

1U_0402_10V6K 10U_0402_6.3V6M
2 1 2 1

1U_0402_10V6K 10U_0402_6.3V6M
2 1
VGA@ PCV39
10U_0402_6.3V6M
2 1
VGA@ PCV40
10U_0402_6.3V6M
2 1
VGA@ PCV41
10U_0402_6.3V6M
2 1
VGA@ PCV42
10U_0402_6.3V6M
2 1
1u*8
4.7u *4
330u*4
10u*25
VGA@ PCV68
22u* 15
10U_0402_6.3V6M
Near VGA
Under VGA
2 1
-----------------
VGA@ PCV64
10U_0402_6.3V6M
3
3
Issued Date
2 1 2 1
10U_0402_6.3V6M 22U_0603_6.3V6M
2 1 2 1
10U_0402_6.3V6M 22U_0603_6.3V6M
+NVVDD1

2 1 2 1
2019/08/30
10U_0402_6.3V6M 22U_0603_6.3V6M
2 1 2 1
10U_0402_6.3V6M 22U_0603_6.3V6M
PCV43 VGA@
330U_D1_2VY_R9M
2 1
2
1
+
2 1
10U_0402_6.3V6M
+NVVDD1
VGA@ PCV74 22U_0603_6.3V6M

2 1 VGA@ PCV81
2 1
2
1
+
10U_0402_6.3V6M
VGA@ PCV75 22U_0603_6.3V6M
2 1 VGA@ PCV82 PCV44 VGA@
330U_D1_2VY_R9M
Near GPU Core
10U_0402_6.3V6M 2 1
Compal Secret Data
Deciphered Date
VGA@ PCV76
2
1
+
2 1 22U_0603_6.3V6M
VGA@ PCV432
10U_0402_6.3V6M 2 1 PCV45 VGA@
2
2
VGA@ PCV77
330U_D1_2VY_R9M
2 1 22U_0603_6.3V6M
VGA@ PCV433
2
1
+
10U_0402_6.3V6M 2 1
VGA@ PCV78
2 1 22U_0603_6.3V6M PCV46 VGA@
VGA@ PCV434
330U_D1_2VY_R9M
2020/08/30
10U_0402_6.3V6M 2 1
VGA@ PCV79
2 1 22U_0603_6.3V6M
VGA@ PCV435
10U_0402_6.3V6M 2 1
VGA@ PCV80
22U_0603_6.3V6M
VGA@ PCV436
2 1
22U_0603_6.3V6M
VGA@ PCV437
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Title
Date:
2 1
22U_0603_6.3V6M
VGA@ PCV438
2 1
22U_0603_6.3V6M
VGA@ PCV439
Document Number
2 1
22U_0603_6.3V6M
VGA@ PCV440
Monday, April 18, 2022
2 1
1
1
@ESD_VGA@ PCV57
0.1U_0402_25V6
Sheet
HH514 MB LA-L972P
2 1
@ESD_VGA@ PCV59
107
PWR_VGA DECOUPLING
0.1U_0402_25V6
of
122
Rev
1A
A
B
C
D
5 4 3 2 1
@ PJW1
GN20S/N18S-G5
B+_+1.35VS_VGAP 1
1 2
2 FBVDD_B+ +1.35VSDGPU
TDC :9.6A
2200P_0402_50V7K
JUMP_43X79
VGA@ PRW1 Peak Current 11.7A
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
0.1U_0402_25V6
0.1U_0402_25V6
VGA_EMI@ PCW1
@VGA_EMI@ PCW2
VGA@ PRW28 1K_0402_1%
VGA_EMI@ PCW32
1
1
1 2 @VGA_EMI@ PCW62
PCW3
PCW4
PCW5
VGA@ PCW54
31.6K_0402_1% <33,36> FBVDDQ_EN
2 1
+3VALW
VGA@ PCW55 1 2
+1.8VALW_PRIM FBVDD_B+
2
0.1U_0402_25V6
1 2
VGA@
VGA@
VGA@
10U_0603_25V6M
@VGA@ PRW3 @VGA_EMI@ PCW63

0_0402_5%
D 1 2 1 2 D
<33> FBVDDQ_PSI +5VS FBVDD_B+
10U_0603_25V6M
1
VGA@ UG1_+1.35VS_VGAP
PRW6 SH00000PJ00
10K_0402_1%
7X7X3
VGA@ PRW4 Isat:11.3A /15A Idc=11.3A
2
2.2_0603_5% VGA@
PQW1
DCR:7.4~6.7A
2 1
2
AONY36352_DFN5X6D-8-7 VGA@ PLW1 1UH_11A_20%_7X7X3_M
BOOT1_+1..35VS_VGAP_R
G1
D1
SW1_+1.35VS_VGAP
+FBVDDQ
BOOT1_+1.35VS_VGAP
1 4
UG1_+1.35VS_VGAP
VID_+1.35VS_VGAP
PSI_+1.35VS_VGAP
EN_+1.35VS_VGAP
SW1_+1.35VS_VGAP 7 2 3
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
D2/S1
330U_D1_2VY_R9M
1
1
@0@ PRW9
S2-3
S2-2
S2-1
VGA_EMI@
@VGA@ PCW6
VGA@ PCW7
PCW8
VGA@ PCW10
@VGA@PCW11
VGA@PCW12
G2
1
VID_+1.35VS_VGAP 1 2 PRW8
2
VRAM_VDD_CTL <33> 4.7_1206_5% +
PCW61
6
2
1
0_0402_5%
VGA@
@VGA@
@VGA@ PCW15
SNB1_+1.35VS_VGAP
0.1U_0402_16V7K
PRW10 VGA@ 2
1
10K_0402_1% PUW1 VGA@
1
RT8816BGQW_WQFN20_3X3 PCW14 VGA@
2
0.22U_0603_25V7K
UGATE1
BOOT1
VID
PSI
EN
2
REFADJ_+1.35VS_VGAP 6 20 SW1_+1.35VS_VGAP
REFADJ PHASE1 LG1_+1.35VS_VGAP
1
REFIN_+1.35VS_VGAP 7 19 LG1_+1.35VS_VGAP VGA_EMI@ PCW16
REFIN LGATE1 VGA@ PRW11 AONY36352 5x6 DFN 680P_0402_50V7K
2.2_0603_5%
H/S Rds(on): 7.3 mohm(Typ), 9.1 mohm(Max)
2
VREF_+1.35VS_VGAP 8 18 PVCC_+1.35VS_VGAP 1 2
VREF PVCC +5VALW L/S Rds(on): 2 mohm(Typ), 2.5 mohm(Max)
VGA@ PRW12 VGA@ PRW13
2.2_0402_1% 499K_0402_1%
2 1 2 1 TON_+1.35VS_VGAP 9 17 VGA@ PCW17
B+_+1.35VS_VGAP TON LGATE2
1
2.2U_0402_6.3V6M
OCSET/SS
VGA@ RGND 10 16
PCW18
2
UGATE2
RGND PHASE2
PGOOD
BOOT2
C C
VSNS
2 1TON_+1.35VS_VGAP_R GND
0.1U_0402_25V6
21
11
12
13
14
15
Vsense_+1.35VS_VGAP
OCset_+1.35VS_VGAP
@VGA@
PRW14
1 2
<32> FBVDDQ_GND_SENSE
FBVDDQ_PG
0_0402_5%
@VGA@ PRW21
10_0402_1%
1 2
1
@VGA@ PCW60 VGA@

1000P_0402_50V7K PRW18
10K_0402_1%
2
1 2 +3VS
VGA@ PRW19
100_0402_1% FBVDDQ_PG <33>
1 2
+FBVDDQ
39K_0402_1%
1
PRW17
When PRW17=39K, Rocset for 15A

@VGA@
PRW20
FBVDD OCP :15A

2
1 2 VGA@
<32> FB_VDDQ_SENSE
0_0402_5%
B B
2
@VGA@ PCW27
1
0.1U_0402_25V6
VREF_+1.35VS_VGAP
VGA@ PCW20
0.1U_0402_25V6
VGA@ PRW22
4.53K_0402_1%
1
REF1
2
2
REFADJ
VGA@ PRW25
137K_0402_1%
REFADJ_+1.35VS_VGAP_R 1 2 REFADJ_+1.35VS_VGAP
VGA@ PRW23
VGA@ PCW21
2200P_0402_50V7K
1
1
7.87K_0402_1%
RBOOT
2
2
25w>TDP FBVDD=1.2V
REFIN_+1.35VS_VGAP 35W>=TDP>=25W FBVDD=1.25V(P0), 1.2V(P3~P8)
PRW24
PCW22
A A
2200P_0402_50V7K
20.5K_0402_1%
1
Vram voltage
REF2 When,VRAM_VDD_CTL=High
VGA@
VGA@
2
Vboot=1.253V (x1.010)
2
When,VRAM_VDD_CTL=Low
Vboot=1.203V (x1.013)
PWR_+1.5VRAM
1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. CML_H 82
5 4 3 2 1
5 4 3 2 1
D D
Reserve Page C
B B
A A
2016/11/03
Compal Secret Data
2017/06/14 Title
PIR
5 4 3 2 1
A B C D E
1 1
Module model information

SY8032_V2.mdd
@ PJE1
JUMP_43X79
1 2
+1.0VSDGPUP 1 2 +PEX_VDD
2 2
VIN_1.0VS
VGA@
PCE1
22U_0603_6.3V6M (Common Part)
VGA@
1 2 PUE1 SH00000YG00 4*4*2 GN20S@ PRE4
SY8032ABC_SOT23-6 12K_0402_1%
@ PJE2 PLE1 VGA@
JUMP_43X79 1UH_2.8A_30%_4X4X2_F
1 2 VIN_1.0VS 4 3 LX_1.0VS 1 2
+3VS 1 2 IN LX +1.0VSDGPUP
VGA@
5 2 PRE3
PG GND
1
<33> PEX_VDD_PG 1 2
+3VS
68P_0402_50V8J
6 1 @VGA_EMI@
PRE4
14K_0402_1%
22U_0603_6.3V6M
22U_0603_6.3V6M
FB EN
1
PRE2
PCE2
1
10K_0402_5% 4.7_0603_5%
PCE3
PCE4
VGA@ GN18S@
2
@VGA@ PRE6
2
0_0402_5%
Rup
SNUB_1.0VS
1 2 EN_1.0VS
VGA@
VGA@
<33,36> PEX_VDD_EN
FB_1.0VS
1
@VGA@ PRE7 VGA@

1
10K_0402_1% PRE1 @VGA@
1
1 2 1M_0402_1% PCE5 PCE6
+1.8VSDGPU_AON Function Field :
1
0.1U_0402_16V7K @VGA_EMI@ VGA@ PRE8
2
Rdown PWR.Plane.Regulator_1.05VDGPU - 43.7

2
680P_0402_50V7K 20.5K_0402_1%
Rest of support elements - 43.8
2
Note:
When design Vin=5V, please stuff snubber
to prevent Vin damage
3 3
Imax= 1.6 A, Ipeak= 1.9A

GN18S Vout=0.6V*(1+(14k/20.5k)=1.009V (1.01%)
Vout=0.6V* (1+Rup/Rdown)
GN20S 0.95V
GN18S 1V
4 4

1.05VSDGPU
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

+12V_FAN
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
Size
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
Size
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
Size
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
Size
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
Size
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
Size
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

Reserve
Size
5 4 3 2 1
5 4 3 2 1
Version change list Page 1 of 1 for

(P.I.R. List) PWR
Item Fixed Issue Reason for change PG# Modify List Date Phase
1. CPU 45W and CPU 28W

01 28W IMON and 1. CPU trancsient tuning for 45W and 28W 1.PRZ106 change to 38.3k /PRZ121 change to 432 ohm for GT frequency. 21/10/13 DVT
2. Lack of PCZ109, PCZ130, PCZ116 P.97
Iccmax change to 2.PRZ104 change to 332k for Core frequency
D right value 3.PRZ111 change to 7.5k/PRZ118 change to 4.3k for for ICC MAX GT=55A/Core=112A D
4.PRZ138 change to 33 ohm/ PRZ139 change to 5.9k/ PRZ140 change to 10.5k for GT=55A IMON
5.PRZ151 change to 18.7k for GT=55A_LL
6. PCZ118,PCZ119,PCZ120,PCZ121,PCZ122,PCZ123,PCZ126,PCZ127,PCZ128,PCZ129 change to SE00000G880
CPU 45W
1.PRZ106 change to 38.3k /PRZ121 change to 432 ohm for GT frequency.
2.PRZ104 change to 332k for Core frequency
3.PRZ118 change to 3.16k for for ICC MAX GT=55A
4.PRZ138 change to 33 ohm/ PRZ139 change to 5.9k/ PRZ140 change to 10.5k for GT=55A IMON
5.PRZ151 change to 18.7k for GT=55A_LL
6.PRZ137 change to 182 ohm for shortage of 187 ohm
7.add PRZ165 for PWM4 BOM control
8.PCZ118,PCZ119,PCZ120,PCZ121,PCZ122,PCZ123,PCZ124,PCZ125,PCZ126,PCZ127,PCZ128,PCZ129 change to SE00000G880
all
PCZ109 change to SE071820J80 S CER CAP 82P 50V J NPO 0402
PCZ130 change to SE095224K00 S CER CAP 0.22U 10V K X5R 0402
PCZ116 change to SE00000WA00 S CER CAP 0.47U 25V K X5R 0402
02 shortage of the
TPS51486 Lack of the TPS51486 DDR solution P.89 1. PUM1 DDR solution add G6020MC1D for 2nd source (X76 BOM) 21/10/13 DVT
C C
shortage of the 1. PRA16 change from 255k to 261k for shortage of 255k value.
03 resistor Lack of the PRA16 and PRA13 P.95 2. PRA13 change from 0 0805 1% to 0 ohm 0805 5% 21/10/13 DVT
04 Buyer suggest Cost saving for 1uF_0201 MLCC P.101 1.PCZ205,PCZ206,PCZ209,PCZ212,PCZ218,PCZ219,PCZ220,PCZ222,PCZ230 change from SE00001HM00 to SE00000UC00 21/10/13 DVT
Height limitation Change PCZ258 to A3 Slim type BOM

05 P.98 1. PCZ258 change to BOM control for A3 slim type NB 21/10/13 DVT
UMA EC code
06 limitation Pop on PR207 for EC issue P.83 1. PR207 change to pop on for SMT EC issue(VRAM temp trigger) at UMA SKU 21/10/28 DVT
B 07 VRAM voltage NV concern VRAM voltage by chip side P.97 1. PRW25 change to 137k ohm for VRAM voltage (P0:1.21V, P8:1.259V). NV recommended 21/10/28 DVT B
PCZ104,PCZ114,PCZ115 change to lower cost P.97

08 Cost saving part 1. PCZ104,PCZ114,PCZ115 change to "S CER CAP 0.1U 10V +-10% X7R 0402" SE102104K00 for lower cost action 21/10/28 DVT
1. PU501 change form SY8288C SA00008YM00 to RT6258C SA0000BYV01

PU501 5V IC is shortage for MP stage P87 2. Add PC521 22uF_0603
09 Lack of 5V IC 2022/3/14 Pre-MP
3. PC501 change to 0603 size
A A

PIR
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Version change list Page 1 of 1 for

(P.I.R. List) PWR
Item Fixed Issue Reason for change PG# Modify List Date Phase
D D
C C
B B
A A

PIR
Custom 0.1
5 4 3 2 1
5 4 3 2 1
HW Schematic chang list (P.I.R)

Item Page Date Rev. Reason for change Modify Item
1 10 9/13 0.2 DMIC Port error Change DMIC DAT/CLK To GPP_S2/S3
2 33 9/17 0.2 BOM error Pop RV99 Due to PLTRST_VGA#_1V8 output need pull-up
D D
3 56 9/27 0.2 From Factory request Remove RA3,RA4

4 52 9/28 0.2 Intel CNVi spec RW20 Change to 39ohm
5 40 9/30 0.2 ME Connector change Update HDMI symbol to YUQIU_HD050-F19M0BR-B
6 77 9/30 0.2 Screw hole change H7 Change to H_3P2
7 56 10/1 0.2 Reserve Mute LED circuit from Codec to KB Reserve Mute LED circuit
8 58 10/1 0.2 BOM Update Change R85 to pop
9 6 10/1 0.2 BOM Update ADD QS CPU PN
10 38 10/5 0.2 Change enable pin to power on TS PWR Add RVE31 for SUSP# to enable TS PWR
11 29 10/5 0.2 EMI test result update Add CV322 ,CV323 for EMI Request
12 11 10/5 0.2 Intel Debug port reserve add test point on GPP_E15/GPP_E16 (intel debug port)
13 8 10/7 0.2 ESD test result update POP CC5 due to ESD request
14 11 10/7 0.2 BOM Update UC5 Change to use SA0000BJI00
C
15 10/7 0.2 BOM Update Add SAMSUNG 16Gb VRAM part & VRAM Strap pin setting C
16 10/7 0.2 BOM reduce RC256, RO4,RS21,RS25,RS27,RV208 Change to r-short

17 10/7 0.2 BOM reduce RC1,RC2,RT31,RT33,RA24,RA27,RK5,R72,RC126,RC131,RC200 Change to r-short
18 10/7 0.2 BOM reduce RO25,RS22,RS23,RS24,RS28,RT12,RT62,RT63,RT64,RT65,RT8,RT9,RT84,RVE3,
RVE4 Change to r-short
19 10/7 0.2 BOM reduce R71,RB11,RB18,RB73,RC186,RC197,RV178,RV211,RV2,RV268,RVE14,RVE15,
RVH1,RVH2,RVH3,RVH4,RVH5,RVH6,RVH22 Change to r-short
20 66 10/8 0.2 ESD test result update DK1 Change to unpop , DK4 change to pop (ESD request)
21 12 10/8 0.2 BOM Update Pop RC484 for VGA Power up sequence
22 56 10/9 0.2 Vendor Suggest R1 , R2 Change to 49.9ohm (Vendor request)
23 38 10/18 0.3 Design reserve for QHD panel Add RVE32 for TS_EN, RVE34 / RVE33 Reserve for QHD PANEL
24 38 10/18 0.3 Design reserve for QHD panel Reserve PANEL_OD_EN for OHD PANEL
25 56 10/22 0.3 BOM Update Change codec PN to SA000080Q10
B B
26 69 10/22 0.3 ESD test result update Pop CS105 from ESD request
27 58 10/22 0.3 DVT BOM Update Update EC Board ID for A5DVT2@ , A3DVT1@
28 43 11/10 1.0 BOM Update Change UT14 PN to SA0000DUO10
29 11 11/10 1.0 Reserve for +LCDVDD sequence Add UVE3/RVE35,RVE36,RVE37 for LCDVDD enable
30 38 11/10 1.0 Change RVE18 to I2C_TS_INT# & Always Pop on (TS Sku & non-TS_Sku)
31 43 11/10 1.0 BBR re-timer leakage issue RT105 Change to 0 ohm(unpop) , Add DT26 for prevent leakage
32 11 11/10 1.0 EC autoload power up issue Add QC2 to EC_VCCST_PG_R prevnet EC autoload issue
33 38 11/10 1.0 Reserve RVE38,RVE39 for TS_PANEL_OD_EN PU/PD
BOM reduce RC143,RC150,RC191, RC34,RK222 , RT108 , RVE22 , RW5,RT1186,RT1187,RT1188,
34 11/14 1.0 RT4000,RT4001 Change to R-short
35 11 11/14 1.0 EC autoload power up issue Reserve QC3 for VR_ON & EC_VCCST_PG_R#
36 43 11/16 1.0 Intel PDG spec update add RC496 pull-down for PDG 1.5 Version
A 37 43 11/17 1.0 BBR re-timer leakage issue Add RT450 pull-up for DG0_RST# A
38 43 11/19 1.0 BOM Update RT1161 Change to 10k ohm

39 11/22 1.0 BOM reduce RV29 ,RV276,RT209,RV131,RV134,RT300 Change to R-short
40 38 11/22 1.0 ESD test result update Add CVE23 for ESD reqeust
HW-P.I.R page1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH5A4 M/B LA-M211P
5 4 3 2 1
5 4 3 2 1
HW Schematic chang list (P.I.R)

Item Page Date Rev. Reason for change Modify Item
41 10 11/22 1.0 Net name update TS_I2C_INT#_GND change to TS_I2C_INT#_R
42 56 11/23 1.0 Reserve for EMI test RA24,RA27 Change to 0ohm for EMI test
D D
43 58 11/23 1.0 BOM reduce RB76,RB78 Change to R-short

44 11/29 1.0 BOM update CS108,CS95,CT536,CT537,CT565 Change to SGA0000F200 , due to SGA00009M00 shortage
45 71 11/29 1.0 BOM update Add USB Charger X76 PN
46 58 11/29 1.0 BOM update UK5 change to SA0000BCG50(KB9052Q E)
47 27 11/29 1.0 BOM update Add GN18-S5 MP PN
48 56 11/29 1.0 BOM update R1,R2 Change to SD014510A80 (51ohm)
49 16 11/29 1.0 Intel spec update RC113 Change to 4.7k pull-down
50 16 12/2 1.0 BOM Reduce RC143,UC5 Change to unpop
51 43 12/2 1.0 BOM update RT450 Change to 100k pull-up
52 9 12/6 1.0 Reserve for BIOS strap pin RC481,RC492 Change to pull-down reserve
53 56 12/6 1.0 BOM update CA31 change to unpop due to PDG no require
54 12/20 1.0 BOM update Add GN20-S7 /4GB VRAM PN
C
55 1/14 1.0 BOM update Add MP CPU PN C
56 1/17 1A PWR update Combine PWR schematic

57 2/7 1A BOM update Update 1A DAZ & Board ID table
B B
A A

HW-P.I.R page2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH5A4 M/B LA-M211P
5 4 3 2 1

Compal LA-M211P HH5A4 R1a

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Compal LA-M211P HH5A4 R1a

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HH5A4 MB Schematic Document

Security Classification Compal Secret Data Compal Electronics, Inc.

Nvidia M.2 SSD PCIe 4.0

USB3.1 - JUSB 1 USB3.1 - JUSB 1 USB3.1 - JUSB 1

eSPI BUS Int.Keyboard 2

- GEN1 - GEN1 - GEN1

- USB2 Port 8 - USB2 Port 9 - USB2 Port 10 - PCH I2C1 P.63

Sub Board - PCIE4 Port12 - PCIE Port9 - PCIE Port5~8

IO/B (LS-M211P) PCIe Int. DMIC Audio Jack

4 Power On/Off CKT. HDD 4

Power Circuit DC/DC P.63

RC197 +3VALW_DSW CPU

UV12 +1.8VSDGPU_MAIN GPU

RS27 +1.8VS RA83 +1.8V_AUDIO CODEC

PU501 PJ502 +5VALW

U4 +5VS_BL JKBL1,2 KB Backlight

JIO1 +5VALW JIO1 IO Conn. +VCC_FAN1

PLV11, GPU_B+ GPU

Security Classification Compal Secret Data Compal Electronics, Inc.

[ HH5A4 -PWR Sequence_ADL-U ]

G3->S0 S0-> S0iX S0iX ->S0 S0->S5

SLP_SUS# 95.92ms 952.4us SLP_SUS#

EC_1V8EN 2.49ms 9.9ms

+1.05VO_VNNBYPASS 4us 10.90ms +1.05VO_VNNBYPASS

AC_PRESENT_R 29.44ms 10.ms AC_PRESENT_R

+2.5V 716us 50.98ms

CPU_C10_GATE# SLP_S3# 1.0ms 10us

+1.05V_VCCST Not used

VR_ON SLP_S3# 48.30ms 80.24us

Security Classification Compal Secret Data Compal Electronics, Inc.

TBT_0_LSX_RX EN26 GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD/BSSB_LS1_RX TCP3_TX_N0 BR1

Security Classification Compal Secret Data Compal Electronics, Inc.

RC460 RC461 RC462 SOC_XDP_TCK0 51_0201_5% 2 CMC@ 1 RC29

Refer to Boot Strap 0 (on GPP_C5) for the encoding.

HIGH: Top swap enable 1 = (Default) Normal

This strap should sample LOW. There should NOT be @

Security Classification Compal Secret Data Compal Electronics, Inc.

Follow Intel DDR4 NIL

0.1U_0201_10V6K 2 1 CC4 BG53

RC33 DT42 RSVD_10

A 4 DDR_DRAMRST# RC34 1 RS@ 2 DDR_DRAMRST#_R

DDR_PG_CTRL 1 2 ESD change to pop 10/07

2200P for power sequence tCPU19

Security Classification Compal Secret Data Compal Electronics, Inc.

1 SOC_SPI_0_CS#1 EG58 SPI0_MOSI GPP_C3/SML0CLK EF38 SOC_SML0DATA

SOC_GPP_E6 EH23 DP51 ESPI_IO0 RC54 1 2 33_0201_5% ESPI_IO0_R @RF@

SOC_GPP_E6 SOC_GPP_F13 ET33 GPP_F14/GSXDIN/THC1_SPI2_IO2 GPP_A5/ESPI_ALERT0# DP54

SOC_GPP_F16 EL33 SOC_SML0DATA 499_0201_1% 1 2 RC46

1 CL_DATA EF26 CL_CLK CC9

From EC MAF - Master Attached Flash

(For share ROM)

RC58 RC59 EC FW access through eSPI Bus

SOC_GPP_E12 SOC_GPP_F16 SOC_GPP_F15 SOC_GPP_F14 SOC_GPP_F13

RC61 RC62 RC63 RC481 RC492

Default pull-down 12/6

RC67 10K_0402_5% PCB_ID0

* SPI0 1 load topology: *** SPI0 3 load topology:

RC66 RC67 R2 is required 10 ohm for 1.8V and 3.3V.

Project Project_ID1 Project_ID0 PartNumber - Description RC68 1 RS@ 2 0_0402_5%

20200813 remove Memory Down Strap Topology BOM Config

Security Classification Compal Secret Data Compal Electronics, Inc.

100K_0201_5% 1 GLITCH@2 RC95 HDA_BIT_CLK PCH_DMIC_DATA CC18 @RF@1 2 22P_0201_25V8