1V 10-bit Successive Approximation ADC for Low Power Biomedical Applications

Hwang-Cherng Chow and Yi-Hung Chen

Department and Graduate Institute of Electronics Engineering

Chang Gung University
259 Wen-Hwa 1st Road, Kwei-Shan, Tao-Yuan 333, Taiwan, ROC
Email: hcchow@mail.cgu.edu.tw

Abstract-- A low power 1V 10-bit successive device threshold voltages. Although the used charge
approximation analog-to-digital converter (SA-ADC) is recycling and current driven bulk techniques are known in
presented for biomedical applications. In the DAC the literature, we demonstrate a new low voltage
capacitor arrays of this SA-ADC a charge-recycling application in this paper.
method for switching the capacitors is used. Besides, a 1V
rail-to-rail input comparator with both current driven bulk II. Conventional SA-ADC Design
technique and offset cancellation is proposed. The
complete 1V ADC implemented in TSMC 0.18um CMOS A. Conventional capacitor array switching method
process has a signal-to-noise ratio of 58.5dB and its
effective number of bits is 9.4 based on post-layout
simulations. The entire ADC power consumption is
32.6uW for normal signals and 29.5uW for ECG
applications.

I. Introduction Figure 1 Block diagram of both the comparator and DAC

In a biomedical signal processing system, an ADC is
an important circuit that successively converts biomedical
signals from analog into digital signals. Analyzing and
processing digital signals are dependent on specific
demands. However, the ADC operates continuously.
The typical relationship between the DAC and
comparator is shown in Figure 1. Figure 2 shows the
conventional DAC capacitor array. The algorithm is
described below [1].
VMID

Therefore, the power consumption is a very important

factor in the ADC circuit design. Moreover, the key
components of a successive approximation analog to C2 = 2C0 C1 = C0 C0
digital converter (SA-ADC) include a comparator and a
DAC.
S 2+ S sample S2 − S sample S1−
As the CMOS process advances, the allowed supply VREF
S1+ S0
+
S sample S0−

voltage VDD is continuously decreasing, but the threshold VIN

voltage VT of devices is not scaled proportionally. If the

supply voltage becomes less than about 1.5V, the
traditional complementary differential input pairs can not
support a rail-to-rail input range. Besides, the
conventional DAC switching method efficiently charges
the capacitor array. But, during the other half of bit
cycling it is highly inefficient since the stored charge into
the array will be discharged [1]. This leads to large energy
inefficiency.
In this paper, a 10-bit successive approximation
analog to digital converter suitable for biomedical
applications is presented for 1V low voltage operations. A
charge reuse DAC is implemented in the SA-ADC
through charge recycling technique [1] to save more
power. Besides, the 1V comparator supports a rail-to-rail
input range by current driven bulk technique to reduce
Figure 2 Conventional DAC capacitor array
The Ssample turns on at the sample phase, and the
entire capacitor array stores the voltage VMID-VIN. Then, at
time 0, S2+ is connected to VREF. The first DAC output voltage
Vx [1] is
Vx[1]= VMID-VIN+ VREF/2 (1)
If the capacitor array settles in time TP, the total energy
drawn from VREF is [1]
E0→ 1 = − V R E F ( Q C 2 ( T P ) − Q C 2 (0 + )) (2)
= - VREF (QC2(TP)- QC2(0+))
= - VREF2C0((VX[1]- VREF)- VX[0])
=C0V2REF
The output of the comparator (CMP)

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VIN < VREF/2 => CMP=1 (3)
VIN > VREF/2 => CMP=0
The output of CMP decides the switching of next
capacitors. If CMP is “0”, the second largest capacitor is
connected to VREF (turn on), raising the voltage at Vx. If
CMP is “1”, S2+ turns off and S1+ turns on. On the other
hand, C2 is switched to ground and C1 is connected to VREF.
The total energy drawn from VREF can be computed as
follows [1]:
When CMP=0
Vx[2]= VMID-VIN+ VREF 3/4
E 1 → 2 = (C0V2REF)/4
(5)
When CMP=1
Vx[2]= VMID-VIN+ VREF 1/4
2 voltage, we split the MSB capacitor into two capacitors of
E 1 → 2 = (C0V REF)5/4
(7)
The conventional method is switching down the
MSB capacitor and switching up the sub-MSB capacitor.
This method is the simplest one to change the DAC output
voltage, but the stored charge is then discharged right now
on CMP result of 1. The energy is wasted in this time
interval.
B. Conventional comparator
Figure 3 Complementary differential input pairs
Figure 3 shows conventional complementary differential
input pairs [2] that can achieve a rail-to-rail input. But, the
supply voltage is generally limited to about 1.5V. When
the supply voltage is below Vtn+|Vtp |+Vds,n+|Vds,p|,
there is a dead region at the middle of the supply voltage.
Therefore, the input common mode range will be limited
by both transistor threshold voltages and overdrive
voltages.
III. Proposed SA-ADC
In Figure 4, the complete architecture of the proposed
successive-approximation analog to digital converter is
shown. The converter consists of a DAC circuit, a
comparator, digital control logic, shift registers and a
successive approximation register.
Figure 4 Proposed SA-ADC architecture
(4)
A. Charge recycling
In this DAC design we make use of charge reuse [1].
Through charge recycling much of the energy can be
saved for a “high” of CMP’s value. To avoid charging any
(6) capacitor to VREF during decreasing the DAC output
the second largest capacitance, and switch down one of
them [1]. In this operation, the capacitor splitting
approach requires no energy spent in charging up a
capacitor from ground to VREF when the CMP result is
“1”and achieves the same energy when the CMP result is
“0”.
Figure 5 shows a 10-bit capacitor array using the
published splitting capacitor array method [1]. No extra
area is required to split the MSB capacitor. But this
switching method will require twice switches. Since
switches area are general small, so the side effect is
minimal.
Figure 5 10-bit splitting capacitor array
B. 1V rail-to-ail input comparator
In this SA-ADC, 1V comparator is required that
supports a rail to rail input common range. The threshold
voltage of an MOS transistor is given as a function of
bulk-source voltage VBS by
VT H = VT H 0 + γ ( 2φ F + V SB − 2 φ F ) (9)
where Vth0 : zero bias threshold voltage, γ: bulk effect
factor and φF : Fermi potential.
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 For typical p-channel transistors, 2φF = -0.7V, γ = -
0.5V(1/2), and Vth0 = -0.55V, and a bulk bias VBS is
normally larger than 0V, which increases the threshold
voltage. However, by biasing VBS less than 0V we can
actually decrease the threshold voltage.
To reduce the threshold voltage as much as possible,
we tend to bias the bulk bias | VBS | as high as possible.
There is a published method called the current driven bulk
(CDB) technique [3] to meet this circuit demand well, as
shown in Figure 6.

Figure 8 Whole core layout

A. Static characteristics
Figures 9 and 10 show simulation results of the
differential nonlinearity (DNL) and the integral
nonlinearity (INL), respectively, that are less than
0.25LSB and 0.45LSB at 1V supply voltage with 10-bit
resolution.
Figure 6 Current driven bulk technique
0.5
0.4
To change the voltage of bulk, the voltage of VBS 0.3

alters that is used to reduce the threshold voltage. Using 0.2

the current driven bulk technique the threshold voltage

0.1
0

can be reduced well under 0.3V in TSMC 0.18um CMOS -0.1

technology. If VDS(sat) = 0.1V is assumed and designed, a -0.2

-0.3
rail-to-rail input range operational amplifier can be -0.4

achieved for 1V operation. Figure 7 shows a modified -0.5

1 69 137 205 273 341 409 477 545 613 681 749 817 885 953 1021

single stage preamplifier with complementary input pairs.

Figure 9 Simulated ADC static characteristics DNL
0.6

0.4

0.2

-0.2

-0.4

-0.6
1 69 137 205 273 341 409 477 545 613 681 749 817 885 953 1021

Figure 10 Simulated ADC static characteristics INL

Figure 7 Single stage preamplifier with CDB
IV. Simulation Results and Comparison
The complete ADC is implemented in TSMC
0.18um mixed-signal CMOS process. Figure 8 is a
photograph of the whole core layout where the active area
2 Figure 12(b). The simulation results are satisfactory.
is about 0.87mm . The circuit performance is carried out
by HSPICE simulations.
B. Dynamic characteristics
Figure 11 shows a full-scale 300Hz sine wave
spectrum with simulation results at a sampling rate of 20
KS/sec. The signal to noise ratio (SNR) is 58.5dB, and the
equivalent effective number of bits is 9.4. Simulation
results of biomedical signal processing such as an ECG
application are shown in Figure 12. The used ECG signal
has a higher frequency of 100Hz to save CPU simulation
time. The recovered signal by an ideal DAC is shown in

198

Figure 11 Signal to noise ratio of proposed ADC
comparator with current driven bulk technique and offset
cancellation is implemented. The complete ADC has a
signal-to-noise ratio of 58.5dB and its effective number of
bits is 9.4 based on post-layout simulations. The
differential nonlinearity (DNL) and the integral
nonlinearity (INL) are, respectively, less than 0.25LSB
and 0.45LSB at 1V only supply voltage. The entire ADC
power consumption is 32.6uW for normal signals and
29.5uW with further 9.4% reduction for ECG applications.
Acknowledgements

This work was supported by the National Science Council

of Taiwan, the Republic of China under contract no.
NSC93-2220-E-182-002. The software and chip
fabrication support from the Chip Implementation Center
(a) is also acknowledged.

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Table 1 shows the comparison result with other 10-bit SA-ADC with New Self-timed Timing Control for
Biomedical Applications,” IEEE International Symposium on
existing low supply voltage ADC circuits. According to Circuits and Systems, Vol.1, May 2005, pp. 736-739
the comparison results, the power consumption is
efficiently reduced to 32.6uW through the charge Table 1 Performance comparison
recycling technique. As compared to our previous design [4] [5] [6] This
[6], the power saving is very significant. As for the input work
common range it can accept a rail to rail input at the 1V Process 1.2um 0.18um 0.18um 0.18um
supply voltage. This feature is important for biomedical Resolution 8bits 9bits 10bits 10bits
signal processing because the bio-signal is always first Supply 1V 1V 1.8V 1V
amplified by the instrumentation amplifier then to the voltage
ADC. As the magnitude swing of the amplified signal Input swing 850mV 0.5V Rail to Rail to
increases, the design of a high resolution ADC such as 10- Rail Rail
bits becomes feasible and easier. Sampling 50KS/s 150KS/s 70kS/s 40KS/s
rate
DNL 0.47LSB 0.7LSB 0.33LSB 0.25LSB
V. Conclusion INL 1.14LSB 0.75LSB 0.24LSB 0.45LSB
SNR 49.31dB 51.6dB 59.55dB 58.5dB
A low power 1V 10-bit successive approximation ENOB 7.9bits 8.27bits 9.6bits 9.4bits
analog-to-digital converter has been presented for Power 0.34mW 30uW 0.3mW 32.6uW
biomedical applications. A charge-recycling method for Core Area <1.8mm x < 1mm x < 850um
---
switching the capacitors in the DAC is used. By making 1.8mm 1mm x 850mm
use of charge reuse, the average switching energy can be
greatly reduced. Besides, a 1V rail-to-rail input

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