Time-Shifted CDS Enhancement of Comparator-Based

MDAC for Pipelined ADC Applications

Omid Rajaee, Nima Maghari and Un-Ku Moon
School of Electrical Engineering and Computer Science
Oregon State University, Corvallis, OR 97331

Abstract—A new comparator based MDAC is presented. This the Vcm, comparator detects zero crossing and turns off the
structure utilizes nonlinear charge transfer and time shifted current source. Moreover, a brief preset phase is necessary
CDS techniques to improve the performance of the comparator to ensure that the voltage Vx starts out below the Vcm.
based MDAC. Simulation results show that the proposed
MDAC can be utilized in pipeline ADCs to enhance accuracy C2
and speed.
Φ2
C1 P
E1 E1
I. INTRODUCTION E2
Vx Vo
Low intrinsic device gain in scaled CMOS technologies is Vcm Vcm
Vx
CL
one of the most challenging circuit design problems. E2 Vcm
Although cascoded and gain boosted amplifier stages are C2
straightforward solutions to increase amplifier gain, these
techniques reduce output voltage swing. Another method for Vo
achieving higher gain without reducing voltage swing is to C1 E1
Vo[n]
cascade several gain stages, which in turn causes stability Vx Vo
problems and increases the power consumption. Vcm Vcm
CL -Vcm
E2
Recently, comparator based switched capacitor circuits
(CBSC) were introduced as an alternative to the opamp
based designs to overcome some of these limitations [1]. Figure 1. The Conventional CBSC S/H Circuit
These circuits replace the opamp with comparator to
eliminate the need for high gain, high speed opamps, and In the opamp based circuits, the accuracy of the output
operate with low power consumption. voltage during the charge transfer phase depends on the
Comparator based technique provides a simple solution for accuracy of the virtual ground node. But in the CBSC
amplifier gain problem, but accuracy of this technique is circuit, an accurate virtual ground condition is only required
limited by the comparator and the current source. Delay of at the zero crossing instant.
comparator and finite output resistance of current sources In order to increase the accuracy of amplification/charge
will directly affect the accuracy of comparator based circuits. transfer phase and to maintain a fast charge transfer, charge
As a result, the accuracy degrades for high sampling rates. transfer phase is divided into two sub phases: coarse phase
In this paper, new techniques are proposed to increase the and fine phase. Coarse charge transfer phase is used to
sampling speed of comparator-based MDAC (multiplying
obtain quick, rough estimate of output and virtual ground
digital-to-analog converter) while maintaining the accuracy.
condition while fine transfer phase is utilized to obtain more
accurate virtual ground condition.
II. BASIC CBSC CIRCUITS
Fig. 1 shows the comparator based S/H [1] in the III. THE PROPOSED VOLTAGE CONTROLLED CHARGING
amplification/charge transfer phase. The comparator based TECHNIQUE
S/H is similar to the opamp based S/H except that opamp is
In the comparator based S/H (or MDAC), the charge
replaced with a comparator and a current source. Assuming
transfer error is a function of comparator delay and output
that Vx always starts below the virtual ground condition, the
current source turns on at the beginning of charge transfer current ( E= I o ∆t ), where a portion of this error term is
phase and charges up C1, C2 and CL. As soon as Vx reaches C

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nonlinearity and gain error caused by finite resistance of Since the differential pair used as voltage controlled current
current source. The rest of the error term is offset. source is similar to preamplifier of comparator, it can be
merged into the comparator design.
C E
t s a m p li n g ∼ V in = V in . (1)
Io ∆t

The speed of operation is proportional to the current

charging the capacitors (1), hence there is a tradeoff
between speed and accuracy. In the conventional CBSC
technique, accuracy issue is partially solved by utilizing an
extra fine correction phase, which in turn imposes longer
settling time and lower sampling speed. One interesting
feature of CBSC technique is that the linearity of current is
only important at virtual ground detection instant:
Io average ( I o ) I zero _ cross _ ins tan t + I zero _ det ect _ ins tan t
E = ∆t = ∆t =
C C
(2)
In order to achieve faster settling, variable current source can
be used. The idea is to charge the capacitor with current
proportional to the difference between Vx and Vref as shown
in Fig. 2(a). This can be done by using a voltage controlled
current source instead of the constant current source used in
the conventional CBSC circuit.
∆t
2C Figure 3. Merging Preamplifier of Comparator and VCCS
IV. THE PROPOSED TIME-SHIFTED COMPARATOR BASED
MDAC
Although error (voltage overshoot) is not significantly large
in this case, a correction phase is still needed to acquire high
accuracy.
There are two straight forward methods to cancel the
overshoot error: using a fine correction phase or correlated
double sampling technique. The main drawback of these
two methods is that one extra phase is needed for error
correction. However, in the pipeline ADCs, the need for
extra correction phase can be eliminated by utilizing time
shifted CDS technique. This has been demonstrated in a
opamp based pipelined ADC [2].

Figure 2. The Proposed Voltage Controlled Charging

Technique

Fig. 2(c) shows one possible implementation of the Voltage

controlled charging (VCC) technique. A differential pair is
used as a voltage controlled current source. When Vx is low
compared to reference voltage, all the tail current flows
through M3 and is mirrored at the output. When Vx Figure 4. Time Shifted CDS Pipeline ADC
approaches Vref, current flowing through M3 reaches its
minimum value which is considerably linear: Fig. 4 illustrates the principle of Time Shifted CDS
Technique. One path represents the predictive path which
I c = g m (Vref - Vx ) (3) only operates for the first few stages, and the other path
represents the main signal path that operate for all stages.

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The first few stages of the main signal path are very similar
to their corresponding stages in the predictive path, and they
share the same set of active elements. Both signal paths
process the same input signal from the first sample-and-hold
stage, but the main signal path is delayed by an additional
S/H following the first S/H. The input signal is first sampled
by the predictive pipeline and the difference between virtual
ground node (Vx) and reference voltage is stored on a
pipeline stage, the error voltage stored on Cf-p1 or Cf-p2 is
shifted by Vref -VR . Later in the correction phase, the SC
level shifter cancels the mentioned dc level shift.
Fig. 6 shows timing sequence and clock phases of the
proposed MDAC.
Φ1

capacitor. The stored error is used to correct the Φ2

corresponding stage in the main pipeline in the following
clock phase. As both signal paths share the same comparator Φ1a

and current sources, this operation is easily achieved with

Φ1b
added switches and capacitors. Fig. 4 shows timing diagram
of conventional CDS and time-shifted CDS. The entire Φ2a
timing of each time-shifted CDS stage is shifted one clock
phase ahead, and the sampling phase and the pre-amplifying Φ2b
phase share the same time slot. Moreover, the amplifying PS1 PA1 PS2 PA2 PS1 PA1 PS2
MA2 MS MA1 MS
phase and the pre-sampling phase can be merged into one MA2 MS MA1

clock phase since they are independent of each other.
Fig. 5 shows the proposed MDAC structure with time
shifted CDS comparator based sampling. The input/output
of main and predictive paths are shown in this figure.
PS2 = Predictive Sampling- input sampled on Cf-p2 and Cs-p
PS1 = Predictive Sampling- input sampled on Cf-p1 and Cs-p
MA1 = Main Path Amplifying , Error stored on Cf—1 used for correction
MA2 = Main Path Amplifying , Error stored on Cf—2 used for correction
PA2 = Predictive path amplifying - Cf-p2 and Cs-p are used
PA1 = Predictive path amplifying - Cf-p1 and Cs-p are used
MS = Main Path Sampling
Figure 6. Timing of the Proposed Structure

V. PROPERTIES OF THE PROPOSED TIME-SHIFTED

COMPARATOR BASED MDAC

A. Offset and Nonlinearity Errors

Two mechanisms generate offset and nonlinearity in the
comparator based circuits: output overshoot due to
comparator delay and voltage drop across the sampling
switches [1]. Since the current charging the sampling
capacitor is not constant, the output overshoot error of a
voltage controlled charging MDAC can be expressed as:
V
gm (Vx - Vref ) + 0
dV0 R
= (4)
dt C
2
gm +
2V0 (
R ) ∆t
Figure 5. The Proposed Time Shifted Comparator Based ∆E = (V0 − Vref + ) × (1- e 2C
) (5)
MDAC Rgm
In the proposed structure, predictive path contains three Where Vo is MDAC output voltage, R is current source
capacitors (Cf-p1, Cf-p2, and Cs-p) while the main path output resistance, C is total output capacitance, ∆t is
contains two sampling capacitors (Cf-m, and Cs-m). In each comparator delay and Vx is voltage at node x:
clock cycle, the error voltage is stored on one of the
predictive sampling capacitors (Cf-p1 or Cf-p2). The second Vx = 0.5(V0 + Vref ) (6)
operation is done by the main path while virtual ground of
2
the main path is shifted by the error voltage stored on the gm +
R ) ∆t
(
predictive sampling capacitor. Meanwhile, the predictive Although the output term (1- e 2 C ) in error expression
path samples the input (Vi-p) on the two other predictive
is small, further error suppression is necessary for higher
sampling capacitors.
accuracy. Thanks to the time-shifted CDS technique, the
Since the reference voltage of the MDAC, i.e. VR, can take
gain error is reduced to:
different values with respect to the output bits of the

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 2V0 (
gm
+
1
) ∆t frequencies, performance of both structures is comparable.
2
∆E = (V0 − Vref + ) × (1- e 2 C RC
) (7) But SFDR of the conventional CBSC MDAC degrades
Rgm rapidly at higher sampling frequencies while SFDR of the
The constant charging current passing through the finite proposed structure maintains accuracy.
resistance switches causes a voltage drop across each
switch, and it creates both offset and nonlinearity. Since the VII. CONCLUSIONS
output current is small at the virtual ground condition (3), New Techniques are proposed to improve the accuracy of
(Vref ≈ Vx) and the resistance of the switches can be made comparator based circuits at higher frequencies. Variable
small, the voltage drop across the switches do not current source was added to the output of the proposed
significantly contribute to offset or nonlinearity. MDAC to enhance speed and accuracy. Also time-shifted
CDS, which compensates for charge transfer errors without
B. Noise an extra clock phase, was successfully incorporated to the
A major limitation to the accuracy of the comparator based proposed MDAC design.
circuits is the noise added when input is sampled and
amplified. The comparator is the most critical part of the
noise performance of CBSC circuits. It can be shown that
the input referred noise of comparator is
1 (8)
vn2 = 4kTRn SFDR = 74 dB
2ti
where Rn is the input referred noise resistance and ti is the
integration time (delay) of comparator. Total noise in the
correlated double sampling architecture can be expressed as:
1 (9)
vn2 =| 1 − e − jw | 2 4 kTRn
2 ti

As shown by the frequency shaping in (9), flicker noise and

dc offset are suppressed in the CDS architecture. Compared Figure 7. PSD of the Proposed MDAC
to the conventional comparator based circuit, the total noise
power of the CDS architecture is increased by 3dB.

VI. SIMULATION RESULTS

The effectiveness of the proposed time-shifted CDS
enhanced comparator-based architecture is demonstrated in
simulation. The proposed MDAC was simulated using a
0.18µm CMOS technology models (1.8V supply voltage).
SFDR of the proposed MDAC is 74dB at 70 MHz sampling
rate. This initial set of simulation results are summarized in
Table I. Power spectrum of output residue of time shifted
MDAC is shown in Fig. 7. In this structure the overall
power consumption is dominated by the power dissipated in
charging the capacitors.
Figure 8. Comparing the Conventional and the Proposed
TABLE I. SIMULATION RESULTS MDAC

Time Shifted CDS References:

Sampling Speed 70 MHz
[1] Fiorenza, J. K.; Sepke, T.; Holloway, P.; Sodini, C. G.; Lee, H.-S
Power Consumption 1mW /stage, Pseudo (2mW) “Comparator-Based Switched-Capacitor Circuits for Scaled CMOS
Technologies”, IEEE J. Solid-State Circuits, Vol. 41, No. 12, pp.
SFDR 74 dB( Pseudo Differential)
2658-2668, Dec. 2006.
SNR 65 dB [2] J. Li and U. Moon, " A 1.8V 67mW 10b 100MS/s pipelined ADC
using time-shifted CDS technique," IEEE J. Solid-State Circuits, pp.
1468-1476, Sep. 2004.
Fig. 8 compares SFDR of the proposed structure with the
conventional comparator based MDAC. At low sampling

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