CSCE-312 - Summer 2020 - ​Sample​ Midterm Exam 

NAME: UIN:  

Note1: There are 4 questions in this part of the exam for a total of 40 points. 
Note2: These are the various options to write and submit the exam: 

1. Print on paper, hand write legibly, scan and submit in PDF format 
2. Use your favorite editor to type and draw and submit in PDF format. 
3. A combination of the two above, but be sure to submit in PDF format. 

Note2: Assume there is no restriction on the maximum number of inputs in logic gates. 
Note3: Assume binary numbers provided are unsigned unless specified otherwise 

   

 
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Q1A. [5 pts] ​You are tasked with the challenge of figuring out if a student is eligible to take an elective 
course. The conditions to be eligible to take an elective course is as follows: 

A. The student must have taken exactly two prerequisites courses from the following list of three 
courses: ​A, B, C​, and  
B. The student is not in minor classification.  

Write a Boolean logic expression for taking the elective course. You do not need to minimize the 
expression. Use the following symbols: ​M ​for Minor, A
​ , B, C​ for courses, and ​E f​ or Elective.  

   

 
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Q1B. [5 pts]​ Design a single-bit comparator with two single-bit inputs ​A ​and ​B​ and three single-bit 
outputs: ​GT (A > B), LT (A<B) and EQ (A==B).​ Complete the truth table for this single bit comparator 
and then write minimized logic equations for the three outputs. 

A  B  GT  EQ  LT 

         

         

         

         

Write the minimized logic equations below: 

GT = 

EQ =  

LT = 

 
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Q2. [10 pts]​ A chip with output X

​ ​ is expected to perform a different logic operation on inputs A
​ ​and ​B 
depending on its 2-bit input signal S
​ = {S​0​, S​1​}​. Suppose the following table shows the logic operation 
that needs to be performed based on the 2-bit input signal S
​ = {S​0​, S​1​}​ -  

 
Design combinational logic (chosen from logic gates, mux, dmux, etc.) to implement the above 
chip functionality as noted in the table: 

 
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Q3A. [5 pts] ​Below is a logic diagram of a latch designed using​ NAND gates​. Study the logic diagram 
carefully and then d
​ raw the waveform for output Q​ in response to waveforms for inputs S and R. You 
may assume arbitrary starting value of output Q and you may assume that gates and wires in the 
cross-coupled configuration have identical delays. 

   

 
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Q3B. [5 pts] C
​ ompare the behavior of D latch and D flip-flop devices by completing the timing diagram 
in the waveform below. Note that Q(latch) represents the output of a D-Latch and Q(FF) represents the 
output of a DFF. Assume that both Q(FF) and Q(Latch) start as logic 0. D is the data input and C is the 
clock input to the Latch and FF. 

   

 
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Q4A [5 pts].​ Assume you are given a 2-input 4-bit subtractor chip implemented with a 4-bit RCA and other 
combinational logic. However the problem is that this s​ ubtractor cannot be modified internally​ (i.e. it is a 
black-box). But you do have a 4
​ -bit incrementer chip​ in your lab. Using these and any other basic logic gates, 
show how you can i​ mplement a 4-bit adder to add two numbers A[3:0] and B[3:0].​ ​Assume the numbers are 
signed and that your subtractor is capable of handling inputs in 2’s complement format. Briefly describe your design 
approach, and then draw the circuit to match it. 

DESIGN APPROACH CIRCUIT 

     

   

 
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Question 4B​.​ [5 points]​ ​Design a 6-bit RCA (RCA6) using ONLY 4-bit RCA (RCA4)​ available as ​standard 
components​. A RCA4 module (​A[3:0], B[3:0], c ​as input pins, and​ S[3:0], co ​as output pins) is provided as a 
reference. Clearly label all the input pins (​A[5:0], B[5:0]​) and the output pins (​S[5:0], overflow​) in your RCA6 design. 

   

   

 
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ADD PAGES AS NEEDED 

 
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