07-EIec-A4, December 2016 Page 1 of 6

National Exams December 2016

07-EIec-A4, Digital Systems & Computers

3 hours duration

NOTES:

1. If doubt exists as to the interpretation of any question, the

candidate is urged to submit with the answer paper, a clear statement
of any assumptions made.

2. This is a Closed Book exam.

Candidates may use one of two calculators, the Casio or Sharp
approved models.

3. FIVE (5) questions constitute a complete exam.

Clearly indicate your choice of any five of the six questions given
otherwise the first five answers found will be considered your pick.

4. All questions are worth 12 points.

See below for a detailed breakdown of the marking.

Marking Scheme
1. (a) 3, (b) 3, (c) 3, (d) 3, total = 12
2. (a) 3, (b) 6, (c) 3, total = 12
3. (a) 6, (b) 6, total = 12
4. (a) 4, (b) 3, (c) 5, total = 12
5. (a) 5, (b) 7, total = 12
6. (a) 4, (b) 4, (c) 4, total = 12
The number beside each part above indicates the points that part is worth
07-Elec-A4, December 2016 Page 2 of 6

1.- Given the following function in product-of-sums (PoS) form:

f (A, B, C, D) = (13+C).(A+B+CHB+C+D)

(a) Prepare its truth table. [3 pts]

(b) Express f in canonical sum of products (SoP) form using the abbreviated notation
involving minterms, i.e., f (A, B, C, D) = Emi (...) [3 pts]

(c) Map the function f in a Karnaugh map (K-map) and find the minimized SoP form. [3 pts]

Note: Alternatively you can verify this result using Boolean algebra, a summary of
identities is provided in a table attached at the end.
(d) Is the expression found in part (c) hazard-free? If not, give the hazard-free SoP form. [3 pts]

2.- The following circuit contains two RS flip-flops.

(a) Write the logic expressions for RA, SA, RB and S13. [3 pts]

(b) Obtain the state transition table for the circuit. [6 pts]

(c) Sketch the state transition diagram for the circuit. [3 pts]

RA Q
>A
SAQ

RB
01k >B
SBQ

Note: Consult the flip-flop excitation table attached at the end as needed.
07-EIec-A4, December 2016 Page 3 of 6

3.- The following is a truth table of a 3-input, 4-output combinational circuit.

(a) Using K-maps obtain the simplified expressions for A, B, C and D. [6 pts]

(b) Implement using a PAL or PLA architecture. Justify your choice. [6 pts]

Inputs Outputs
X Y Z A B C D
0 0 0 0 1 1 0
0 0 1 1 0 0 0
0 1 0 0 0 1 1
0 1 1 1 1 1 1
1 0 0 1 0 1 1
1 0 1 0 1 0 1
1 1 0 0 1 1 0
1 1 1 1 1 0 1

4.- (a) A NOR gate can be used single-handedly to implement any of the three basic
logic gates. Show this by drawing the circuits for the AND, OR & NOT gates. [4 pts]

(b) A combinational circuit is formed by a combination of logic gates that

produce an immediate change in the output when inputs change. How is this
different in the case of sequential circuits? Explain. [3 pts]

(c) i. Draw the circuit of a synchronous counter.

ii. Draw the circuit of an asynchronous counter.
Clearly identify each of them and justify why one is synchronous and not the
other. [5 pts]
 Page 4 of 6
07-Elec-A4, December 2016

4Kbyte
5.- Two new external memory chips need to be added to a microprocessor system — a
$B800.
RAM that should begin at $8800, and a 2Kbyte EPROM that should begin at
in use
Regions $9800-$9FFF, $B600-$B7FF & $C000-$FFFF of the memory map are
already and conflict should be avoided.
(a) Fill in the blanks beside and inside the memory chips with the appropriate
numbers. The number on top of this symbol represents the number
of lines on that bus. [5 pts]

(b) E1 & E2 are the active-low chip select pins for the RAM & EPROM chips,
respectively. Find their Boolean expressions. Use the minimum number of
lines and gates possible. Use decoder outputs to minimize decoding logic.
Complete the connections in the figure below (adding logic gates where
needed) to create the address decoding specified. [7 pts]

Note: The `$' sign indicates the number following it is a hexadecimal number.

8 Data Bus (D -D )
16
Address Bus (A15- A0)

A -A0
D D

4K x 8
E-clock YO RAM
E3 D.Yi 3 begins at
e Y2 E1 $8800
C Y31
Y4
d
eimmo.00.

A15
• -2 Y5
\A14
Y6
\A13
Ao Y7 A -A0
HC138 D -D

2K x8
EPROM
begins at
B800
 Page 5 of 6
07-Elec-A4, December 2016

-anode seven-
6.- The figure below shows a circuit used to display two digits in two common
segment LED displays. The LED arrangem ent for each seven-s egment display is shown on
are used to control the two-
the right side. Parallel Port B lines PB7-PB0 of a microcontroller
e which
digit display. PB7 is used for digit selection, while PB6-PB0 are used to determin
transistor
segments are lit. Consider that inverters are open-collector TTL inverters and
saturation VcE value is approximately 0.3V.
[4 pts]
i. Provide the binary values needed in Port B lines to display:
(i) the number '3' in the 10's digit, and
(ii) the number '6' in the l's digit.

ii. From the programming point-of-view suggest the sequence of steps that will
[4 pts]
allow observing the number '36' lit on the 2-digit display. Explain.

iii. Find the value for the resistors R2 that will allow limiting the current through
each LED to 10mA. When turned on, consider the nominal voltage across a
LED is 2V. [4 pts]

Vsource = 5V

PB7
5.1K
VVV\-
10K

NT1
5.1K
vvvL
10K

T0 a
10 Digit 1' Digit
I g lb
.0 •

a
0 • •

a el ic
R
.2
PB6 NV\
R. 2
PB5 -1>c> VVV‘
• • •
• • •
• • •

PB0 to
 Page 6 of 6
07-Elec-A4, December 2016

Excitation Table

Q-4-- R S 3 K
Q
0 0 X 0 0 X
1 0 1 1 X 1 1
0
1 0 1 0 X 1 1
1 0 -x X 0 ,0
1

Bic Boolegn Identities

Comments •
Identity

A +0 = A Operations with 0 and 1

1.
A +1 1 Operations with 0 and I
2.
A+A= A Idompotent
3.
A -4-A=1 Complementarity
4.
with 0 andI
5. A • 0=0Operations
Operations with 0 and 1.
6. A • 1= A
A•A= A Idompotent
7.
AA0 Complementarity
8.
9. A =A Involution
A+ B= B+A Commutative
10.
11. A B= B A Commutative
A + (B + (A + B)+C=A+B+C Associative
12.
A•(B•C)=. (A• B)•C= A• B.0 Associative
13.
A • (B + C) = (A • B) + (A • C) Distributive
14.
A + (B • C) (A + BHA + C) Distributive
15.
A-F(A• B)= A Absorption
16.
17. A•(A+ B). A Absorption
18. (A•B)+(71•C)+(B•C)=(A•B)+(.71.-C) Consensus
19. A+ B+C+...=-A.4731.-C.... De Morgan
20. A•B•C•...=71.4-73÷-e+... De Morgan
21. (A + 7/3) • B = A • B Simplification
22. (A•713-)+ B = A + B Simplification
07-Elec-A4, May 2016 Page 1 of 6

National Exams May 2016

07-Elec-A4, Digital Systems & Computers

3 hours duration

NOTES:

1. If doubt exists as to the interpretation of any question, the

candidate is urged to submit with the answer paper, a clear statement
of any assumptions made.

2. This is a Closed Book exam.

Candidates may use one of two calculators, the Casio or Sharp
approved models.

3. FIVE (5) questions constitute a complete exam.

Clearly indicate your choice of any five of the six questions given
otherwise the first five answers found will be considered your pick.

4. All questions are worth 12 points.

See below for a detailed breakdown of the marking.

Marking Scheme
1. (a) 2, (b) 5, (c) 2, (d) 3, total = 12
2. (a) 3, (b) 6, (c) 3, total = 12
3. (a) 2, (b) 4, (c) 2, (d) 4, total = 12
4. (a) 4, (b) 5, (c) 3, total = 12
5. (a) 4, (b) 4, (c) 4, total = 12
6. (a) 4, (b) 8, total = 12
The number beside each part above indicates the points that part is worth
 07-Elec-A4, May 2016 Page 2 of 6

1.- Given the following function in sums-of-product (SoP) form:

f (A, B, , D) =

where mi represent the minterms involved in the SoP canonical form off.
(a) Prepare its truth table.
(b) Map the function f in a K-map and identify:
i. One implicant that is not a prime implicant,
ii. One prime implicant that is not essential, and
iii. All essential prime implicants.
In identifying each implicant above list all the minterms in each of them.
(c) Write the minimized SoP form for f.
(d) Is the minimized SoP expression found hazard-free?
Explain and if it is not provide the hazard-free SoP form for f

2.- The following circuit contains two JK flip-flops.

(a) Write the logic expressions for JA, KA, JB and KB. [3 pts]
(b) Obtain the state transition table for the circuit. [6 pts]
(c) Sketch the state transition diagram for the circuit. [3 pts]

CK
Note: Consult the flip-flop excitation table attached at the end as needed.
07-EIec-A4, May 2016 Page 3 of 6

3.- (a) Provide the state transition table for an asynchronous binary up-counter that will go
through the sequence 0000, 0001, 0010, ..., 1111, 0000, ....
(b) Build the asynchronous binary up-counter in (a) using T flip-flops.
(c) Provide the state transition table for a decade counter.
(d) Build an asynchronous decade binary up-counter using T flip-flops.

Hint: Try modifying the counter in (b) such that it turns into a decade counter.

4.- The figure below shows a memory cell A built using two cascaded inverters.
Data input D contains the value to be written to the memory cell. Control input W
(write) determines when the value of the memory cell is to be updated with the
value in D. Two tri-state gates (buffers) are used for this purpose.

cA/

1111/1.1•111

(a) Is the control input W (write) active-low or active-high?

Explain by describing how the value of the cell is (i) held and (ii) updated.
(b) Provide a truth table having A, D and W as inputs, and showing the values of
the 2 tri-state gate outputs Ti and T2 for each input combination.
(c) How long does W have to be active for the memory update to be successful?
Explain.
07-Elec-A4, May 2016 Page 4 of 6

5.- (a) Identify by marking with a X which of the following are the 4 essential components of a
computer system.
Mouse Busses (address, data, control)
Processor (CPU) Keyboard
Printer Display monitor
Hard drive I/0 ports
Memory

(b) Identify the main differences between a general purpose microprocessor and a
microcontroller.

(c) Identify which CPU register(s) is(are) typically associated with each of the following
- the address of the next instruction to be executed:
- the next available location at the top of the stack:
- pointing to an array or list of data values in memory:
- containing the information an assembly program uses at decision making points
(conditional branch statements):
07-Elec-A4, May 2016 Page 5 of 6

6.- Figure 6.1 below shows a circuit used to display six BCD digits in six common-cathode
seven-segment displays. The LED arrangement for each seven-segment display is shown in
parts 6.2 and 6.3 of the figure. A buffer chip is used to provide the current required to light
up the LEDs as determined by Port B pin values, i.e. it provides all six displays with a logic
`0' or a logic '1' as dictated by PB7-PB0, while adding the required driving capacity.
(a) Using a CPU accumulator register A with Idaa' (load accumulator A) and `staa' (store
accumulator A) instructions available, write a sequence of assembly instructions to display
the number '6' on the seven-segment display #0.
Port B and Port D are memory mapped with addresses $1004 and $1008, respectively.
(b) Describe a way through which we can observe not just one digit lit as in part (a) above but all
digits simultaneously showing '09.05.16' on the display arrangement shown in Figure 6.1.
Include the sequence of steps to accomplish this as well as the bit patterns needed for Port B.
No need to include assembly instructions in part (b) just the algorithmic sequence.

#5 #4 #0
100 C*2
WV
MA/

10052 .
Buffer Chip MA,

PB7 ,PB6 • • ,PBO common common common

cathode cathode cathode
R
PD5

R
Micro PD4 WV
Controller

PDO

Fig 6.1. Port B and Port D together drive six seven-segment displays

a b c d e f g
a

f
g

e
•h
d

Fig 6.2. Seven-segment

display common cathode
Fig 6.3. Common-cathode seven-segment display
07-Elec-A4, May 2016 Page 6 of 6

.Excitation Table

Q Q+ R S 3 K T ID
o o x o o x o
o 1 1 1 X 1 1
1 0 1 0 X 1 1 0 •
1 I o -x x 0 0 i

Eglis39olean, Identities,

Identkw Comas

1. A +0 = A Operations witli0 and 1

2. A +1=1 Operations with 0 and 1
3. A -4--A=A Idompotent
4. A+A=1 Complementarity
5. A• 0=0 Operations with 0 andI
6. A .1= A Operations with 0 and 1.
7. AA=A Idompotent'
8. A • A =0 Complementarity
9. A =A • Involution
10. A+B=B+A Commutative
I. A-13= B• A Commutative
12. A+(B+C)=(A+B)-i-C=A+B+C Associative
13. A-(B-C)=(A•B).C=A-B•C Associative
14. A• (B+C) = (A- B)÷(A.C) Distributive
15. A+(B-C)=(A+B)•(A-FC) Distributive
16. A-i-(A-B)=A Absorption
17, A•(A+B)=A Absorption
18. (A-B)÷(A.•0+(B.C)=(A-B)+(A-C) Consensus
19. A+13-i-C-1-...=A...T3:E'•... De Morgan
20. A-B-C•...= -A÷T3÷E-1-... De Morgan
21. (A 4- T3)• B= A. B Simplification
22. (A•ii)+B=A+B Simplification
 National Exams December 2015

07-Elec-A4, Digital Systems & Computers

3 hours duration

NOTES:

1. If doubt exists as to the interpretation of any question, the

candidate is urged to submit with the answer paper, a clear statement
of any assumptions made.

2. This is a Closed Book exam.

Candidates may use one of two calculators, the Casio or Sharp
approved models.

3. FIVE (5) questions constitute a complete exam.

You are required to answer questions 1, 2, 4 and 6.
You have a choice of answering question 3 or question 5.

4. Questions 1, 2, 4 and 6 are worth 12 points.

Questions 3 and 5 are worth 16 points.
For a detailed breakdown see marking scheme on next page.

Marking Scheme
1. (a) 3, (b) 3, (c) 3, (d) 3, total = 12
2. (a) 9, (b) 3, total = 12
3. (a) 2, (b) 3, (c) 5, (d) 3, (e) 3, total = 16
4. (a) 3, (b) 3, (c) 3, (d) 3, total = 12
5. (a) 6, (b) 6, (c) 4' , total — 16
6. (a) 3, (b) 3, (c) 3, (d) 3, total = 12
The number beside each part above indicates the points that part is worth

Page 1 of 8
07-Elec-A4, December 2015 Page 2 of 8

1.- Given the following function in sum of products form:

f (A, B, C) = ABC + BC + ABC

(a) Prepare its truth table. [3 pts]

(b) Express f in canonical product of sums form. [3 pts]

(c) Use Karnaugh maps (K-maps) to express f in minimized product of sums form. [3 pts]

(d) Synthesize a NOR-only circuit for f with a minimum number of gates. [3 pts]
07-Elec-A4, December 2015 Page 3 of 8

2.- A circuit is needed to start and stop counting clock pulses on command.
(a) Design a 3-bit synchronous counter that goes through the sequence 000, 001, 010,
011, 100, 101, 110, 111 and then repeats. Use positive-edge-triggered JK flip-
flops. Label the bits Qc, QB & QA where Qc is the most significant bit.
Draw the circuit implementing the counter. [9 pts]

(b) Modify the circuit so that it counts whenever an additional COUNT ENABLE
(CTE) input is HIGH, stops counting when CTE goes LOW and resumes counting
from where it stopped when CTE goes HIGH again. [3 pts]
07-Elec-A4, December 2015 Page 4 of 8

3.- The finite state machine (FSM) shown in the figure below is implemented with one toggle
(T) flip-flop and one D flip-flip. It has a single input I and a single output Z. The
combinational logic required is implemented by an 8:1 MUX, 1 NAND and 1 AND gates.
(a) Is this a Moore or a Mealy FSM? Justify. [2 pts]

(b) Write the logic expressions for TA, DB and Z. [3 pts]

(c) Obtain the state transition table including TA, DB, Q;1-4, +(g and the output Z. [5 pts]

(d) Draw the state transition diagram of the FSM including input I and output Z
values. [3 pts]

o -0

0-2
0 -3 IA
0-40
v—sK
A D a
6, So
C LP,

CLK cl) Cf.R.

JUL

(e) Assuming that the preset input PR is not asserted fill the timing diagram below
for QA, QB and Z. [3 pts]

Q3
0

zilftwavanwinvamus....

CLK
•0---'

1
CLR

0
07-Elec-A4, December 2015 Page 5 of 8

4.- The diagram below shows the use a D flip-flop governing two digital switches in order to
route line PD0 of the HC11 microcontroller unit (MCU) to one of two connectors: the HOST
computer I/O port or the MCU I/O port connector.
Digitals switches close when control input C is at a logic '1' and remain open when C is '0'.
HC11 address lines A15 - A13 are connected to the 3 address inputs of a 3:8 decoder as
shown in the figure, the most significant address input of the decoder is A2 and the least
significant is A0. Assume the decoder is enabled and towards the end of the execution of
each instruction cycle all its active-low outputs Y0 - V7 go back to their inactive logic '1'
state.
The least significant data bus line of the HC11 (Do) is connected to the flip-flop D input.
Knowing that instruction
ldaa #$xx means load HC11 CPU register accumulator A with hexadecimal value xx, and
staa $zzzz means store the value in accumulator A to address $zzzz,
which of the following set of instructions will direct HC11 line PD0 to the HOST computer
1/0 port, which to the MCU I/O port connector and which will not affect the current routing.
Mark your choice with an X and justify your selection in each case.
(a) ldaa #$10, staa $8000 [ ] HOST Comp 110 port, [ MCU 110 port, [ ] No Action
(b) ldaa #$29, staa $4000 [1HOST Comp IJO port, [ MCU I/O port, [ No Action
(c) ldaa #$B4, staa $5000 [ ] HOST Comp 110 port, [1MCU 110 port, [ No Action
(d) ldaa #$05, staa $2500 [ HOST Comp I/O port, [ 1 MCU I/0 port, [ No Action

YO -
Y1
3: 72
DECODER
Y4: -
HC11 A15... A2 Y5 -
HC11 A14 — At Y6
1-1C11 A13
HOST
, COMP
.1/0 PORT PD'o' •

Digital
Q Ck<--1 HC11
HC11 PD0 Switch 1
Data Bus
HC11
Line Do
Digital D
MCU
Switch 2
D flip-flop

> MCU
PDo 110
PORT
07-Elec-A4, December 2015 Page 6 of 8

5.- Provide this 8-bit CPU with a 64Kbyte memory space by making use of 16K x 4 memory
chips like the ones provided in the figure below.
(a) Fill in the blanks beside and inside the memory chips with the appropriate
numbers. The number on top of this symbol represents the number of
lines on that bus. The spaces besides the A's and the D's are to indicate which lines
of the address and data busses are connected to each chip, respectively. [6 pts]

(b) Complete the connections in the figure below adding logic gates where needed to
produce the chip select (CS) signals needed in the decoding logic. Explain the
reasons for the connections made, include expressions for the Boolean logic used. [6 pts]

(c) Provide the address range allocated to each of the chips used. [4 pts]

Note: R/W & clock signals are omitted for simplicity.

111.11.1.111

16 Address Bus (A15— Ao)

A A A -A A -A

16K x 8 16K x 8 16K x 8

D -D D -D D -D
8-bit CS CS CS
CPU
A -A A -A A -A

16K x 8 16K x 8 16K x 8

D -D D -D D -D
CS CS CS

8
Data Bus (D7 — Do)
07-Elec-A4, December 2015 Page 7 of 8

6.- (a) Identify the three basic logic gates.

Is it possible to realize any combinational logic function using just one type of gate?
Explain. [3 pts]

(b) What is the main difference between combinational and sequential circuits? [3 pts]

(c) What is a finite state machine (FSM)?

Is a counter a special case of FSM? Explain. [3 pts]

(d) Identify the difference between synchronous and asynchronous counters.

How would you identify one type or the other? [3 pts]
07-Elec-A4, December 2015 Page 8 of 8

Excitation Table

C.?. ., Q4- R S
0 0 X 0
0 1 •0 1 1 X 1 1
1 0 1 0 X 1 1 0
1 1 0 -x X 0 0 11

fiasic B °lean Identities

Identity fslinments

1. A -4-0=A Operations with:0 and 1.

2. A +1=1 Operations with 0 and I
3. A +A = A Idompotent
4. A + A =1 Complementarity
5. A • 0=0Operations.with 0 and I
6. A .1=A Operations with 0 and 1.
7. AA=A Idompote nt
8. A •A 0 Complementarity
9. A =A Involution
10. A-f B= B+A Commutative
11. A- .8= B• A Commutative
12. Al-(B+C)=(A+B)+C= A+ B+C Associative
13. A -(B- C).=. (A- B).C=A•B•C Associative
14. A•(B+C)=0- BH-(A-C) Distributive
15. A + (B. C) = (A + BHA + C) Distributive
16. A + (A • B) = A Absorption
17. AAA B) = A Absorption
18. (A- B)+(A•C)+(B-C)=(A-B)+(71.0 Consensus
19. A+B+C-4-....=A•713•Z7.... De Morgan
20. A • B • C = -4- A+ E De Morgan
21. (A +13). B = A • B Simplification
22. - ÷B=A-1-B
(A- M Simplification
 National Exams May 2015

07-Elec-A4, Digital Systems &Computers

3 hours duration

NOTES:

1. If doubt exists as to the interpretation of any question, the

candidate is urged to submit with the answer paper, a clear statement
of any assumptions made.

2. This is a Closed Book exam.

Candidates may use one of two calculators, the Casio or Sharp
approved models.

3. FIVE (5) questions constitute a complete exam.

Clearly indicate your choice of any five of the six questions given
otherwise the first five answers found will be considered your pick.

4. All questions are worth 12 points.

See below for a detailed breakdown of the marking.

Marking Scheme
1. (a) 2, (b) 2, (c) 2, (d) 3, (e) 3, total= 12
2. (a) 6, (b) 6, total = 12
3. (a) 4, (b) 4, (c) 4, total = 12
4. (a) 3, (b) 4, (c) 3, (d) 2, total= 12
5. (a) 6, (b) 6, total= 12
6. (a) 4, (b) 4, (c) 4, total= 12
The number beside each part above indicates the points that part is worth

Page 1 of 7
07-Elec-A4, May 2015 Page 2 of 7

1.- (a) Using only one NAND gate build a NOT gate. [2 pts]

(b) Using only NAND gates build atwo-input OR gate. [2 pts]

Draw circuits for the function g given by

(c) as written above using AND, OR &NOT gates (assume 2 & 3-input gates
are available). [2 pts]

(d) using NAND gates only (assume literal complements as well as 2 and 3-input
gates are available). [3 pts]

(e) using NOR gates only (assume literal complements as well as 2 and 3-input
gates are available). [3 pts]

Note: Do not use Boolean algebra or K-map to simplify g in parts (c)-(e) above.

2.- The function of any flip-flop type can be obtained by using another type of flip-flop with
suitable logic applied to the Tatter's inputs.
(a) Show how to implement a Tflip-flop using a RS flip-flop. [6 pts]

(b) Show how to implement a RS flip-flop using a Dflip-flop. [6 pts]

Include K-map work showing how to obtain the additional logic needed and
draw the logic circuit for each case including flip-flops and additional logic.

Note: Use flip-flop excitation table attached at the end as needed.

07-Elec-A4, May 2015 Page 3 of 7

3.- The logic box shown below performs the substraction of two 2-bit numbers Nt =AB
(minuend) & NZ = CD (subtrahend). The result (difference) is a three bit number D = XYZ.

A
~, X Nt ~ A 6

D Nz ~ .D-XY~

(a) Build the truth table for the functions X, Y & Z. [4 pts]
Note: Values of D result in 3-bit 2's complement.
(b) Use K-maps to minimize the functions X, Y & Z in sum of products form. [4 pts]

(c) You are given the half-subtractor (HS) and full-subtractor (FS) shown below.
Complete the diagram connections required to obtain the difference D = XYZ
of NI — N2 = AB — CD.
M - minuend, S -subtrahend, D;ff -difference, B;~ -borrow-in, Bo,,, -borrow-out [4 pts]

A M Dlf ,
HS X
B T
,
ou

' Y
C
M Dif '
' Z
S FS
D ~ '
Bin Bout '
07-Elec-A4, May 2015 Page 4 of 7

4.- The following circuit with input X and output Y uses one RS flip-flop and a Tflip-flop.

(a) Write the logic expressions for RA, SA, Ts and Y. [3 pts]

(b) Obtain the state transition table for the circuit.

Include A, B, X, RA, SA, TB, A+, B+,Yin this order. [4 pts]

(c) Sketch the state transition diagram for the circuit. [3 pts]

(d) Is this a Moore or a Mealy machine? Explain. [2 pts]

Note: Consult flip-flop excitation table attached at the end as needed.

07-Elec-A4, May 2015 Page 5 of 7

5.- (a) Describe the algorithm of a short assembly program, including any additional routines
needed, in charge of [h pts]
1. Reading ONE (1) character (char) received through an asynchronous serial port,
2. Converting that char received to lowercase if uppercase, or viceversa (assume the
char received is a letter), and
3. Transmitting the char obtained in Step 2 above through the asynchronous serial
port using interrupts.
You can use a subroutine called inchar starting at address FFCDnex. This subroutine
loops until a character is received by the input serial port then returns the ASCII
character in a CPU register called accumulator A (ACCA).
Assume the asynchronous serial port has been initialized already including a serial line
speed of 9600 baud.
Assume standard serial port registers: status (SR), control (CR), transmit data (TDR)
and receive data (RDR) are memory mapped and their addresses available.

(b) Both input and output serial channels support RS-2321evels, this is, the microprocessor
board receive data (RxD) line is coupled to the channel through RS-232 receivers and
the transmit data (TxD) line is coupled to the channel through RS-232 drivers.
Assume the character `U' is received by your program through the serial port.
Once your program runs sketch the time waveforms for:
(i) the serial bit stream on the TxD line in the board before the RS-232 drivers, and
(ii) the same serial bit stream in (i) above on the transmit line of the RS-232
cable connected to the board serial port connector.
Label each bit appropriately according to their position and role in the frame.
Include time scale values and voltage scale values for each case. [6 pts]
Assume CMOS logic levels are used within the microprocessor board.

ASCII value for `U' is 55hex

ASCII value for `u' is 75n~X

hex stands for hexadecimal

07-Elec-A4, May 2015 Page 6 of 7

6.- For microprocessors, such as Motorola's, that use big-endian order for storing multiple-byte
variables, describe the results of executing the following two assembly instructions by
answering parts (a)-(c) below.
(a) Fill the memory block below with the result of the instruction: [4 pts]

"Store the 16-bit number $lOB2 to address $ C109"

1-bvte locations
Low Memory

$C108
$C109
$C10A
High Memory

(b)The stack pointer register SP = $DFE8 before the following instruction is executed.
Fill the memory block below with the result of the instruction: [4 pts]

"Push the 16-bit number $2EA4 onto the stack"

1-hvte I~rati~ns
Low Memory

$DFE7
$DFE8 ~— SP (before PUSH)
$DFE9
High Memory

(c) What is the value of the stack pointer register SP after the PUSH? [4 pts]

Note: $XXXX = XXXXheX is a hexadecimal value

07-Elec-A4, May 2015 Page 7 of 7

+ R S J ~ `I' D
0 0 X 0 0 X 0 0
0 1 0 1 1 X 1 1
~ 0 1 0 X 1 ~ D
1 Z 0 - X X 0 0 1

1. A~+O ~ A Operations with 0 and 1

2. A+1=1 Operations with 0 and 1
3. A+A=A Idom~otent
4. A+A=1 Complementarily
5. A•0=0 Operations with d and 1
6. A•1=A Operations with 0 and 1.
7. A•A=A Idornpotent~
8. A•A=0 Complementarity
4. A=A Involution
10. A+B=B+A Commutative
11. A•B=B•A Commutative
12. A+(~+C}=(A+B}+C=A+B+C Associative
13. A•(B•G~=(A~B)•C=A•B•C Associative
Distributive
I~~stributive
Absorption
Absorption
I8. (A•B)+(A•C7+(B~G~-(A•B)-t-(A'G'E Consensus
19. A+B+C+...=A•B•C•... De Morgan
20. A•8•C•...=A+B+C+... De Morgan
Sim~lificatian
Simplification
 National Exams May 2013

07-Elec-A4, Digital Systems & Computers

3 hours duration

NOTES:

1. If doubt exists as to the interpretation of any question, the

candidate is urged to submit with the answer paper, a clear statement
of any assumptions made.

2. This is a Closed Book exam.

Candidates may use one of two calculators, the Casio or Sharp
approved models.

3. FIVE (5) questions constitute a complete exam.

Clearly indicate your choice of any five of the six questions given
otherwise the first five answers found will be considered your pick.

4. All questions are worth 12 points.

See below for a detailed breakdown of the marking.

Marking Scheme
1. (a) 2. (b) 2. (e) 2, (d) 3, (e) 3, total = 12

2. (a) 2. (b) 4, (e) 2, Cd) 4, total = 12

3. (a) 3, (b) 3. (e) 3, Cd) 3. total = 12
4. (a) 3, (b) 3, (c) 6, total = 12
5. Ca) 4, (b) 4. (e) 4, total = 12
6. (a) 2, (b) 3. (c) i. 3, (e) ii. 2, (e) iii. 2, total = 12
The number beside each part above indicates the points that part is worth
07-Elec-A4, May 2013 Page 2 of 5

1.- A combinational circuit taking a nonnegative three digit binary number ABC as input
decides whether it IS an even number or the two most significant digits A & B are equal
(indicating it with output E = I) and whether the sum of its two least significant digits B & C
is odd (indicating it with output 0 = I)".
(a) Provide the truth table for the circuit.
(b) Write output E in canonical sum-of-products (SoP) form.
(c) Write output 0 in canonical product-of-sums (PaS) form.
(d) Use Boolean identities to find the minimized SoP form [Dr output E.

(e) Use Boolean identities to find the minimized PaS form for output O.

Note: Please find a table with Boolean identities attached in the last page

2.- (a) Provide the stale transition table for an asynchronous binary up-counter that will go
through the sequence 0000.0001,0010, ..., 1111,0000, ....
(b) Build the asynchronous binary up-counter in (a) using T flip-flops.
(c) Provide the state transition table for a decade counter.
(d) Build an asynchronous decade binary up-counter using T flip-flops.
Hint: Try modifying the counter in (b) such that it turns into a decade counter.

3.- Use JK flip-flops to design a finite state machine (FSM) that works as a 2-bit binary
synchronous up-counter when its input X = 0 and as a 2-bit binary synchronous down-
counter when its input X = 1.
(a) Draw the state transition diagram.
(b) Build the state transition table. Include values of flip-flop inputs.
(c) Find minimized logic expressions for flip-flop inputs.
(d) Draw the resulting logic circuit that implements this FSM.

Note: Please find flip-flop excitation tables attached in the last page
07-Elec-A4, May 2013 Page 3 of 5

4.- (a) Where is the use of a parallel-to-serial shift register needed, in the receiving unit of a
serial communication port or in its transmitting unit? Explain.
(b) Where is the use of a serial-to-parallel shift register needed, in the receiving unit of a
serial communication port or in its transmitting unit? Explain.
(c) Draw the circuit for a 4-bit shift register using D flip-flops that can perform parallel-to-
serial conversion as well as serial-to-parallel conversion.
In your diagram, identify:
i) The serial input terminal,
ii) The serial output terminal,
iii) The parallel input terminals, and
iv) The parallel output terminals.

5.- For microprocessors, such as Motorola's, that use big-endian order for storing multiple-byte
variables
(a) Fill the memory block below with the result of the instruction:
"Store the 16-bit number $7AOl to address $C239"

1-byte locations
•• Low Memory
•
$C238
$C239
$C23A
••
• High Memory
(b) Let SP = $DC51. Fill the memory block below with the result of the instruction:
"Push the 16-bit number $7AOl onto the stack"

1-byte locations
• Low Memory
•
•
$DC50
$DC51 ...- SP (before PUSH)

$DC52
•
• High Memory
•
(c) What is the value of the stack pointer register SP after the PUSH?
~
07-Elec-A4, May 2013 Page 4 of 5

6.- (a) Mention two differences between the address bus and the data bus of a computer system
in tenus of the direction information can flow in them and the meaning of the information
each carries.

(b) A microprocessor system has an address bus with 20 lines, Aw~, and a data bus with 16
lines, DwDo. What is the memory space of the system (in KByte and MByte)? Justify.
Indicate the address range of the entire memory space providing the lowest and highest
addresses in hexadecimaL

(c) Provide the 16-bit CPU in the figure below with a 512KByte memory space by making
use of 64K X 16 memory chips like the ones provided in the figure below.
l. How many chips are needed?
Fill in the blanks beside and inside the memory chips with the appropriate numbers.
The number on top of this symbol ,/ represents the number of lines on that bus.
The spaces besides the A's and the D's indicate which set of lines of the address or
data bus is connected to each chip, respectively.
ii, Complete the connections in the figure below adding logic gates where needed to
produce the chip select (CS) signals needed (the decoding logic). Explain the reasons
for the connections made; include expressions for the Boolean logic used.
i. Provide the address range allocated to each chip in hexadecimal.
Note: RIW & clock signals are omitted for simplicity.

,..
20 Address Bus (A19- Ao)
- --
"' " "';L
'Y- A- -A - '+ A - -A - A - -A -

64K x 16 64K x 16 64K x 16

0- -0 - o -0 -
~
o- -0 - ~
~ -

is-en - CS es - cs
CPU

'+ A--A - '+ A - -A -

'-;L A -
-A -

64K x 16 64K x 16 64K x 16

o- -0 - ~ D- -0 - ~ o--0 - ~
- CS - cs -cs
H? / / /
,
07-Elec-A4, May 2013 Page 5 of 5

Excitation Table

Q 0+ R S J K T D
0 X 0 0 X 0 0 .
0
0 1 0 I 1 X 1 1
1 0 1 0 X 1 1 0
1 1 0 -X X 0 0 1

Basic Boolean Identities

Identity Comments

1. A+O;::;A Operations with' 0 and I

2. A+ [;::;1 Operations with 0 and 1
3. A+A=A . Idompoteut
4. A+A=1 Complementarity
5. A·O~O Operations with 0 and 1
6. A·l=A Operations with 0 and 1.
7. A·A=A Idempotent
8. A·A;::;O Complementarity
9. A=A Involution
Commutative
.
LO. A+B=B+A
II. A·B= B·A Commutative
12. A+ (B+C) = (A + B) + C;::; A+ B+ C Associative
13. A·(B· C)=(A· B)· C=A· B· C Associative
14. A·(B+C) = (A- B) +(A· C) Distributive
IS. A + (B· C) ;::;(A + B) . (A + C) Distributive
16. A+(A· B) = A Absorption
17. A·(A+B)=A Absorption
18. (A· B)+(A· C) +(B·C) =(A' B)+(A'C) Consensus
19. A+B+ C+ ... ;::;A·B·C· . De Morgan
20. A·B·C· ... ;::;A+ B+C+ . ~. De Margan
21. (A+ B)· B= A· B Simplification
22". (A, B)+ B =A+ B Simplification