4.

Pipeline Control

Gisselquist Daniel E. Gisselquist, Ph.D.

Technology, LLC
 Lesson Overview
Ź Lesson Overview Objectives
LED Walker
Diagrams ˝ State diagrams
Pipeline
Bus
˝ Pipeline control structures
Wishbone Bus ˝ Minimal peripherals
Simulation
Unused Logic ˝ Simulating Wishbone
Sim Exercise
˝ $past() operator
Past Operator
Formal Verification ˝ Verifying Wishbone
SymbiYosys Tasks
Exercise
Bonus
Conclusion

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 LED Walker
Lesson Overview Let’s make our LED’s walk on command
Ź LED Walker
Diagrams ˝ Bus requests
Pipeline
Bus
˝ State Diagram
Wishbone Bus
Simulation
Unused Logic
Sim Exercise
Past Operator
Formal Verification
SymbiYosys Tasks
Exercise
Bonus
Conclusion

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 Goal
Lesson Overview Let’s adjust our LED sequence to require a request
Ź LED Walker
Diagrams
Pipeline
i clk
Bus i request
Wishbone Bus
Simulation o busy
Unused Logic
Sim Exercise
o led[0]
Past Operator o led[1]
Formal Verification
SymbiYosys Tasks o led[2]
Exercise
Bonus
o led[3]
Conclusion o led[4]
o led[5]

˝ Our goal will be to create a design with these outputs

˝ If successful, you’ll see this in GTKwave

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 Goal
Lesson Overview We’ll add state ID’s to this diagram
Ź LED Walker
Diagrams
Pipeline
i clk
Bus i request
Wishbone Bus
Simulation o busy
Unused Logic
Sim Exercise
o led[0]
Past Operator o led[1]
Formal Verification
SymbiYosys Tasks o led[2]
Exercise
Bonus
o led[3]
Conclusion o led[4]
o led[5]
state 0 1 2 3 4 5 6 7 8 9 10 11 0

˝ Our goal will be to create a design with these outputs

˝ If successful, you’ll see this in GTKwave

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 State Transition
Lesson Overview The key to this design is the idle state
Ź LED Walker
Diagrams ˝ The design waits in state 0 for an i_request
Pipeline
Bus
˝ Only responds when it isn’t busy
Wishbone Bus
Simulation
i n i t i a l state = 0 ;
Unused Logic
Sim Exercise always @ ( posedge i_clk )
Past Operator i f ( ( i_request )&&(! o_busy ) )
Formal Verification
SymbiYosys Tasks
state <= 4 ’ h1 ;
Exercise e l s e i f ( state >= 4 ’ hB )
Bonus
state <= 4 ’ h0 ;
Conclusion
e l s e i f ( state != 0 )
state <= state + 1 ’ b1 ;

assign o_busy = ( state != 0 ) ;

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 State Transition Diagrams
Lesson Overview
LED Walker
Ź Diagrams
Pipeline ˝ States
Bus
Wishbone Bus – Shown as named bubbles
Simulation
Unused Logic – Moore FSM: states include outputs
Sim Exercise This FSM is a Moore FSM
Past Operator
Formal Verification
SymbiYosys Tasks
˝ Transitions
Exercise
Bonus
– Arrows between states
Conclusion – May contain transition criteria
– Mealy FSM: transitions include out-
puts

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 Outputs
Lesson Overview We can use a case statement for our outputs
LED Walker
Ź Diagrams always @ ( posedge i_clk )
Pipeline
Bus
case ( state )
Wishbone Bus 4 ’ h1 : o_led <= 6 ’ b00_0001 ;
Simulation 4 ’ h2 : o_led <= 6 ’ b00_0010 ;
Unused Logic
Sim Exercise 4 ’ h3 : o_led <= 6 ’ b00_0100 ;
Past Operator 4 ’ h4 : o_led <= 6 ’ b00_1000 ;
Formal Verification
SymbiYosys Tasks
4 ’ h5 : o_led <= 6 ’ b01_0000 ;
Exercise 4 ’ h6 : o_led <= 6 ’ b10_0000 ;
Bonus 4 ’ h7 : o_led <= 6 ’ b01_0000 ;
Conclusion
// . . .
4 ’ ha : o_led <= 6 ’ b00_0010 ;
4 ’ hb : o_led <= 6 ’ b00_0001 ;
d e f a u l t : o_led <= 6 ’ b00_0000 ;
endcase

Or can we? Does this work?

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 Pipeline Strategies
Lesson Overview Several approaches to pipeline logic
LED Walker
Diagrams 1. Apply the logic on every clock
Ź Pipeline
Bus
Wishbone Bus // From t h e PPS´ I I i m p l e m e n t a t i o n
Simulation always @ ( posedge i_clk )
Unused Logic
Sim Exercise
counter <= counter + INCREMENT ;
Past Operator
Formal Verification
SymbiYosys Tasks
Exercise
Bonus
Conclusion

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 Pipeline Strategies
Lesson Overview Several approaches to pipeline logic
LED Walker
Diagrams 1. Apply the logic on every clock
Ź Pipeline
2. Wait for a clock enable (CE) signal
Bus
Wishbone Bus
Simulation
// From t h e I n t e g e r C l o c k D i v i d e r
Unused Logic
Sim Exercise always @ ( posedge i_clk )
Past Operator i f ( stb ) // t h i s would be t h e CE s i g n a l
Formal Verification
SymbiYosys Tasks
begin
Exercise i f ( led_index >= 4 ’ d13 )
Bonus
led_index <= 0 ;
Conclusion
else
led_index <= led_index + 1 ’ b1 ;
end

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 Pipeline Strategies
Lesson Overview Several approaches to pipeline logic
LED Walker
Diagrams 1. Apply the logic on every clock
Ź Pipeline
2. Wait for a clock enable (CE) signal
Bus
Wishbone Bus 3. Move on a request, but only when not busy
Simulation
Unused Logic
Sim Exercise // Today ’ s l o g i c : Wait f o r t h e r e q u e s t
Past Operator
always @ ( posedge i_clk )
Formal Verification
SymbiYosys Tasks i f ( ( i_request )&&(! o_busy ) )
Exercise state <= 4 ’ h1 ;
Bonus
Conclusion
e l s e i f ( state >= 4 ’ hB )
state <= 4 ’ h0 ;
e l s e i f ( state != 0 )
state <= state + 1 ’ b1 ;

Above: A mix of pipeline and state machine logic

This is fairly common

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 Bus
Lesson Overview Interface standards simplify plugging things in
LED Walker
Diagrams
Pipeline
Ź Bus A bus interface can be standardized
Wishbone Bus
Simulation ˝ A master makes requests
Unused Logic
Sim Exercise
A slave responds
Past Operator ˝ Read request
Formal Verification
SymbiYosys Tasks
– Contains an address
Exercise
Bonus – Slave responds with a value
Conclusion
˝ Write request
– Contains an address
– Contains a value
– Slave responds with an acknowledgment

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 Bus Topology
Lesson Overview
LED Walker
Diagrams
Pipeline
Ź Bus
Wishbone Bus
Simulation
Unused Logic
Sim Exercise
Past Operator
Formal Verification
SymbiYosys Tasks
Exercise ˝ Every bus has a master
Bonus
˝ A Bus may have many slaves
Conclusion
Slaves are differentiated by their address
˝ All connected via an interconnect
˝ A slave on one bus may be a master on another

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 Many Bus Standards
Lesson Overview There are many bus standards
LED Walker
Diagrams
Pipeline
Ź Bus
Wishbone Bus
Simulation
Unused Logic
Sim Exercise
Past Operator
Formal Verification
SymbiYosys Tasks
Exercise
AXI Avalon Wishbone
Bonus
Conclusion I like Wishbone for its simplicity
˝ Only one request channel
AXI has three, Avalon has two
˝ Only the request channel can stall
˝ Acknowledgements are simple

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 Wishbone Bus
Lesson Overview I use Wishbone B4, pipelined mode exclusively
LED Walker
Diagrams
Pipeline
i clk
Bus i cyc
Ź Wishbone Bus
Simulation i stb
Unused Logic
Sim Exercise
i we
Past Operator i addr 0
Formal Verification
SymbiYosys Tasks i data S
Exercise
Bonus
o stall
Conclusion o ack
o data

˝ A request takes place any time (i_stb)&&(!o_stall)

Just like our (i_request)&&(!o_busy)
˝ The request details are found in i_we, i_addr, and i_data
˝ These wires are don’t care if i_stb isn’t true

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 Wishbone Bus
Lesson Overview I use Wishbone B4, pipelined mode exclusively
LED Walker
Diagrams
Pipeline
i clk
Bus i cyc
Ź Wishbone Bus
Simulation i stb
Unused Logic
Sim Exercise
i we
Past Operator i addr 0
Formal Verification
SymbiYosys Tasks i data S
Exercise
Bonus
o stall
Conclusion o ack
o data

˝ If i_we, this is a write request

˝ A write request writes i_data to address i_addr
˝ Read requests ignore i_data

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 Wishbone Bus
Lesson Overview I use Wishbone B4, pipelined mode exclusively
LED Walker
Diagrams
Pipeline
i clk
Bus i cyc
Ź Wishbone Bus
Simulation i stb
Unused Logic
Sim Exercise
i we
Past Operator i addr 0
Formal Verification
SymbiYosys Tasks i data S
Exercise
Bonus
o stall
Conclusion o ack
o data

˝ The response is signaled when o_ack is true

˝ If this was a read request, o_data would have the result

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 Wishbone Bus
Lesson Overview I use Wishbone B4, pipelined mode exclusively
LED Walker
Diagrams
Pipeline
i clk
Bus i cyc
Ź Wishbone Bus
Simulation i stb
Unused Logic
Sim Exercise
i we
Past Operator i addr 0
Formal Verification
SymbiYosys Tasks i data S
Exercise
Bonus
o stall
Conclusion o ack
o data

˝ i_cyc will be true from request to ack

˝ i_stb will never be true unless i_cyc

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 Wishbone Bus
Lesson Overview I use Wishbone B4, pipelined mode exclusively
LED Walker
Diagrams
Pipeline
i clk
Bus i cyc
Ź Wishbone Bus
Simulation i stb
Unused Logic
Sim Exercise
i we
Past Operator i addr 0
Formal Verification
SymbiYosys Tasks i data S
Exercise
Bonus
o stall
Conclusion o ack
o data

˝ A slave must respond to every request

˝ Multiple requests can be made before the slave responds
˝ This is controlled by the o_stall signal

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 Wishbone Bus
Lesson Overview Let’s Wishbone enable our core
LED Walker
Diagrams ˝ We’ll start the LED cycling on a write
Pipeline
Bus
˝ Writes will stall if the LED’s are busy
Ź Wishbone Bus ˝ Return our state on a read
Simulation
Unused Logic ˝ We’ll also acknowledge all requests immediately
Sim Exercise
Past Operator
Formal Verification
SymbiYosys Tasks
Exercise
Bonus
Conclusion

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 Wishbone Bus
Lesson Overview ˝ We’ll immediately acknowledge any transaction
LED Walker
Diagrams i n i t i a l o_ack = 1 ’ b0 ;
Pipeline
Bus
always @ ( posedge i_clk )
Ź Wishbone Bus o_ack <= ( i_stb )&&(! o_stall ) ;
Simulation
Unused Logic
Sim Exercise
˝ Stall if we’re busy and another cycle is requested
Past Operator
Formal Verification assign o_stall = ( busy)&&(i_we ) ;
SymbiYosys Tasks
Exercise
Bonus
˝ Return state upon any read
Conclusion
assign o_data = { 2 8 ’ h0 , state } ;

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 Simulation
Lesson Overview It helps to be able to communicate with your wishbone slave
LED Walker
Diagrams
during simulation
Pipeline
Bus
˝ Makes simulations easier
Wishbone Bus ˝ Transaction scripting makes more sense
Ź Simulation
Unused Logic ˝ Just need to implement two functions
Sim Exercise
Past Operator – One to read from the bus
Formal Verification
SymbiYosys Tasks unsigned wb read ( u n s i g n e d a );
Exercise
Bonus
Conclusion – One to write to the bus
void w b w r i t e ( u n s i g n e d a , u n s i g n e d v );

˝ We’ll come back later and create high-throughput versions of

these

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 Sim Read
Lesson Overview u n s i g n e d wb read ( u n s i g n e d a ) {
LED Walker
Diagrams
tb - > i c y c = tb - > i s t b = 1;
Pipeline tb - > i w e = 0;
Bus
tb - > i a d d r = a ;
Wishbone Bus
Ź Simulation
Unused Logic // Make the read request
Sim Exercise
Past Operator
w h i l e ( tb - > o s t a l l )
Formal Verification t i c k ( tb );
SymbiYosys Tasks t i c k ( tb );
Exercise
Bonus tb - > i s t b = 0;
Conclusion // Wait for the ACK
w h i l e (! tb - > o a c k )
t i c k ( tb );
// Idle the bus , and read the response
tb - > i c y c = 0;
r e t u r n tb - > o d a t a ;
}

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 Sim Write
Lesson Overview void wb write ( unsigned a, unsigned v) {
LED Walker
Diagrams
tb - > i c y c = tb - > i s t b = 1;
Pipeline tb - > i w e = 1;
Bus
tb - > i a d d r = a ;
Wishbone Bus
Ź Simulation tb - > i d a t a = v ;
Unused Logic // Make the write request
Sim Exercise
Past Operator
w h i l e ( tb - > o s t a l l )
Formal Verification t i c k ( tb );
SymbiYosys Tasks t i c k ( tb );
Exercise
Bonus tb - > i s t b = 0;
Conclusion // Wait for the acknowledgement
w h i l e (! tb - > o a c k )
t i c k ( tb );
// Idle the bus and return
tb - > i c y c = 0;

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 Run Twice
Lesson Overview This makes building the sim easy!
LED Walker
Diagrams ˝ Let’s tell our LED’s to cycle twice
Pipeline
Bus
Wishbone Bus i n t main ( i n t argc , c h a r ** a r g v ) {
Ź Simulation // Setup Verilator ( same as before )
Unused Logic
Sim Exercise
// Read from the current state
Past Operator p r i n t f ( " Initial state is : 0 x %02 x \ n " ,
Formal Verification
wb read (0));
SymbiYosys Tasks
Exercise f o r ( i n t c y c l e =0; c y c l e <2; c y c l e ++) {
Bonus // Wait five clocks
Conclusion
f o r ( i n t i =0; i <5; i ++)
t i c k ();

// Start the LEDs cycling

w b w r i t e (0 ,0);
t i c k ();
// ... ( next page )

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 Display State
Lesson Overview This makes building the sim easy!
LED Walker
Diagrams ˝ Here’s the other half
Pipeline
Bus
Wishbone Bus // ... ( last page )
Ź Simulation w h i l e (( s t a t e = wb read (0))!=0) {
Unused Logic
Sim Exercise
i f (( s t a t e != l a s t s t a t e )
Past Operator ||( tb - > o l e d != l a s t l e d )) {
Formal Verification
p r i n t f ( // something useful
SymbiYosys Tasks
Exercise );
Bonus } t i c k ();
Conclusion

last state = state ;

l a s t l e d = tb - > o l e d ;
}

The full example code is available on line

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 Unused Logic
Lesson Overview % verilator -- trace - Wall - cc reqwalker . v
LED Walker
Diagrams
% Warning - UNUSED : reqwalker . v :37:
Pipeline Signal is not used : i_cyc
Bus
% Warning - UNUSED : reqwalker . v :38:
Wishbone Bus
Simulation Signal is not used : i_addr
Ź Unused Logic % Warning - UNUSED : reqwalker . v :39:
Sim Exercise
Past Operator
Signal is not used : i_data
Formal Verification % Error : Exiting due to 3 warning ( s )
SymbiYosys Tasks % Error : Command Failed / usr / bin / verilator_bin
Exercise
Bonus -- trace - Wall - cc reqwalker . v
Conclusion %

What happened?

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 Unused Logic
Lesson Overview What happened?
LED Walker
Diagrams ˝ The -Wall flag to Verilator looks for all kinds things you
Pipeline
Bus
might not have meant
Wishbone Bus ˝ It turns warnings into errors
Simulation
Ź Unused Logic ˝ It found logic we weren’t using: i_cyc, i_addr, and i_data
Sim Exercise
Past Operator – These are standard bus interface wires
Formal Verification
SymbiYosys Tasks
– I often include them, even if not used, to keep the
Exercise interface standardized
Bonus
Conclusion ˝ So how do get our design to work?

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 Unused Logic
Lesson Overview Getting Verilator to ignore unused logic
LED Walker
Diagrams ˝ Use the // Verilator lint off UNUSED command
Pipeline
Bus // V e r i l a t o r l i n t o f f UNUSED
Wishbone Bus
Simulation
wire unused ;
Ź Unused Logic a s s i g n unused = &{ 1 ’ b0 , i_cyc , i_addr ,
Sim Exercise
Past Operator
i_data } ;
Formal Verification // V e r i l a t o r l i n t o n UNUSED
SymbiYosys Tasks
Exercise
Bonus
˝ Verilator will now no longer check if unused is used or not
Conclusion

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 Sim Exercise
Lesson Overview Build and run the demo
LED Walker
Diagrams ˝ Examine the trace
Pipeline
Bus
˝ Examine the output
Wishbone Bus
Simulation Does it work like you expected?
Unused Logic
Ź Sim Exercise
Past Operator
Formal Verification
SymbiYosys Tasks
Exercise
Bonus
Conclusion

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 Trace bias
Lesson Overview Look at the trace. Can you explain this?
LED Walker
Diagrams
Pipeline
Bus
Wishbone Bus
Simulation
Unused Logic
Ź Sim Exercise
Past Operator
Formal Verification
SymbiYosys Tasks
Exercise
Bonus
Conclusion Our inputs aren’t clock synchronous!
˝ Normally, all logic changes on the posedge of i_clk
˝ i_cyc, i_stb, i_we are changing before the clock

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 Trace bias
Lesson Overview This is a consequence of our trace() function
LED Walker
Diagrams ˝ We set our input values, i_cyc, etc before calling tick ()
Pipeline
Bus void tick ( void ) {
Wishbone Bus
Simulation
t i c k c o u n t ++;
Unused Logic
Ź Sim Exercise
tb - > e v a l (); // Adjusted inputs are
Past Operator
Formal Verification i f ( tfp ) // recorded here
SymbiYosys Tasks t f p - >dump( t i c k c o u n t * 10 - 2);
Exercise
Bonus
Conclusion tb - > i c l k = 1; // <--- posedge i_clk
tb - > e v a l (); // takes place here !
i f ( tfp )
t f p - >dump( t i c k c o u n t * 10);
// ...

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 Trace bias
Lesson Overview This is a consequence of our trace() function
LED Walker
Diagrams ˝ We set our input values, i_cyc, etc before calling tick ()
Pipeline
Bus void tick ( void ) {
Wishbone Bus
Simulation
t i c k c o u n t ++;
Unused Logic
Ź Sim Exercise
tb - > e v a l (); // Adjusted inputs are
Past Operator
Formal Verification i f ( tfp ) // recorded here
SymbiYosys Tasks t f p - >dump( t i c k c o u n t * 10 - 2);
Exercise
Bonus
Conclusion tb - > i c l k = 1; // <--- posedge i_clk
tb - > e v a l (); // takes place here !
i f ( tfp )
t f p - >dump( t i c k c o u n t * 10);
// ...

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 Trace bias
Lesson Overview This is a consequence of our trace() function
LED Walker
Diagrams ˝ We set our input values, i_cyc, etc before calling tick ()
Pipeline
Bus void tick ( void ) {
Wishbone Bus
Simulation
t i c k c o u n t ++;
Unused Logic
Ź Sim Exercise
tb - > e v a l (); // Adjusted inputs are
Past Operator
Formal Verification i f ( tfp ) // recorded here
SymbiYosys Tasks t f p - >dump( t i c k c o u n t * 10 - 2);
Exercise
Bonus
Conclusion ˝ The tfp->dump(tickcount*10 -2) dumps the state of
everything just before the positive edge of the clock
˝ This captures the changes made to i_cyc, i_stb, i_we, etc.,
in wb read() and wb write()
˝ The trace accurately reflected these changes taking place
before the clock edge

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 Trace bias
Lesson Overview This is a consequence of our trace() function
LED Walker
Diagrams ˝ We set our input values, i_cyc, etc before calling tick ()
Pipeline
Bus
˝ Had we done otherwise, combinatorial logic wouldn’t have
Wishbone Bus settled before posedge i_clk
Simulation
Unused Logic ˝ Worse, the trace wouldn’t make any sense
Ź Sim Exercise
˝ This way, things work. Logic matches the trace.
Past Operator
Formal Verification It just looks strange.
SymbiYosys Tasks
Exercise
Bonus
Conclusion

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 Simulation output
Lesson Overview Is this an output you expected?
LED Walker
Diagrams % ./ reqwalker
Pipeline
Bus
Initial state is : 0 x00
Wishbone Bus 10: State # 4 --O - - -
Simulation 12: State # 6 ----O -
Unused Logic
Ź Sim Exercise 14: State # 8 ----O -
Past Operator 16: State # 10 --O - - -
Formal Verification
SymbiYosys Tasks
27: State # 4 --O - - -
Exercise 29: State # 6 ----O -
Bonus 31: State # 8 ----O -
Conclusion
33: State # 10 --O - - -
%

Let’s look at the trace again!

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 Double ACKs
Lesson Overview Look at the trace. Can you explain this?
LED Walker
Diagrams
Pipeline
Bus
Wishbone Bus
Simulation
Unused Logic
Ź Sim Exercise
Past Operator
Formal Verification
SymbiYosys Tasks
Exercise
Bonus
Conclusion

˝ Why are we getting two acks in a row?

˝ We never created two adjacent requests!

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 Double ACKs
Lesson Overview Look at the trace. Can you explain this?
LED Walker
Diagrams
Pipeline
Bus
Wishbone Bus
Simulation
Unused Logic
Ź Sim Exercise
Past Operator
Formal Verification
SymbiYosys Tasks
Exercise
Bonus
Conclusion

˝ The stall line depends upon i_we

˝ Without a call to tb->eval(), it won’t update!

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 Double ACKs
Lesson Overview Remember how we defined o_stall?
LED Walker
Diagrams a s s i g n o_stall = ( busy)&&(i_we ) ;
Pipeline
Bus
Wishbone Bus
Simulation ˝ wb write() and wb read() both adjust i_we
Unused Logic ˝ . . . without calling Verilator to give it a chance to update
Ź Sim Exercise
Past Operator o_stall before referencing it!
Formal Verification
˝ o_stall is still updated before the clock, but not until after
SymbiYosys Tasks
Exercise we used it in wb write() and wb read()
Bonus
Conclusion
˝ We can fix this by calling tb->eval() to get Verilator to
adjust o_stall

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 Double ACKs
Lesson Overview Need to call tb->eval()
LED Walker
Diagrams ˝ o_stall depends upon a Verilator input, i_we
Pipeline
Bus – Fixing this requires an extra call to eval()
Wishbone Bus
Simulation – I don’t normally need to do this
Unused Logic
Ź Sim Exercise ˝ Both wb read() and wb write() need to be updated
Past Operator
Formal Verification
˝ Example update to wb read():
SymbiYosys Tasks
Exercise u n s i g n e d wb read ( u n s i g n e d a ) {
Bonus tb - > i c y c = tb - > i s t b = 1;
Conclusion
tb - > i w e = 0; tb - > e v a l ();
tb - > i a d d r = a ;
// Make the request
// ...
}

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 Exercise
Lesson Overview Rebuild and run again. Is this better?
LED Walker
Diagrams % ./ reqwalker
Pipeline
Bus
Initial state is : 0 x00
Wishbone Bus 9: State # 3 -O - - - -
Simulation 11: State # 5 ---O - -
Unused Logic
Ź Sim Exercise 13: State # 7 ----- O
Past Operator 15: State # 9 ---O - -
Formal Verification
SymbiYosys Tasks
17: State # 11 -O - - - -
Exercise 27: State # 3 -O - - - -
Bonus 29: State # 5 ---O - -
Conclusion
31: State # 7 ----- O
33: State # 9 ---O - -
35: State # 11 -O - - - -
%

But, why are we reading every other trace?

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 Exercise
Lesson Overview Look at the ACK’s
LED Walker
Diagrams
Pipeline
Bus
Wishbone Bus
Simulation
Unused Logic
Ź Sim Exercise
Past Operator
Formal Verification
SymbiYosys Tasks
Exercise
Bonus
Conclusion

˝ Pattern: i_stb, o_ack repeats

˝ Lesson: The clock ticks twice per read

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 Sim Exercise
Lesson Overview Here’s the full and final simulation
LED Walker
Diagrams
Pipeline
Bus
Wishbone Bus
Simulation
Unused Logic
Ź Sim Exercise
Past Operator
Formal Verification
SymbiYosys Tasks
Exercise
Bonus
Conclusion

Here you can see both LED walks, as expected

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 Formal past operator
Lesson Overview Pipeline logic needs to reason in passing time
LED Walker
Diagrams ˝ $past(X) returns the value of X one clock ago
Pipeline
Bus
˝ $past(X,N) returns the value of X N clocks ago
Wishbone Bus ˝ Both require a clock
Simulation
Unused Logic
always @ ( posedge i_clk )
Sim Exercise
Ź Past Operator i f ( $past ( C ) )
Formal Verification a s s e r t ( X == Y ) ;
SymbiYosys Tasks
Exercise
Bonus ˝ It’s illegal to use $past(X) without a clock
Conclusion
// T h i s i s an e r r o r : t h e r e ’ s no c l o c k
always @ ( ∗ )
i f ( $past ( C ) )
assert (X ) ;

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 Formal past operator
Lesson Overview $past(X) has one disadvantage
LED Walker
Diagrams ˝ On the initial clock, $past(X) is undefined
Pipeline
Bus – Assertions referencing $past(X) will always fail
Wishbone Bus
Simulation – Assumptions referencing $past(X) will always succeed
Unused Logic
Sim Exercise ˝ I guard against this with f_past_valid
Ź Past Operator
Formal Verification reg f_past_valid ;
SymbiYosys Tasks
Exercise
i n i t i a l f_past_valid = 0 ;
Bonus always @ ( posedge i_clk )
Conclusion f_past_valid = 1 ’ b1 ;

˝ To use, place f_past_valid in an if condition

always @ ( posedge i_clk )
i f ( ( f_past_valid)&&( $past ( some_condition ) ) )
a s s e r t ( this_must_then_be_true ) ;

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 Formal Verification
Lesson Overview What properties might we use?
LED Walker
Diagrams ˝ assume properties of the inputs
Pipeline
Bus
˝ assert properties of local states and outputs
Wishbone Bus
Simulation
Unused Logic
Sim Exercise
Past Operator
Formal
Ź Verification
SymbiYosys Tasks
Exercise
Bonus
Conclusion

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 Formal Verification
Lesson Overview What properties might we use?
LED Walker
Diagrams
Pipeline
i clk
Bus i stb
Wishbone Bus
Simulation busy
Unused Logic
Sim Exercise
o led[0]
Past Operator o led[1]
Formal
Ź Verification o led[2]
SymbiYosys Tasks
Exercise o led[3]
Bonus
Conclusion
o led[4]
o led[5]
state 0 1 2 3 4 5 6 7 8 9 10 11 0

The goal waveform diagram should give you an idea

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 Formal Verification
Lesson Overview What properties might we use?
LED Walker
Diagrams ˝ For our state machine
Pipeline
Bus always @ ( ∗ )
Wishbone Bus
Simulation
case ( state )
Unused Logic 4 ’ h0 : a s s e r t ( o_led == 0 ) ;
Sim Exercise
Past Operator
4 ’ h1 : a s s e r t ( o_led == 6 ’ h1 ) ;
Formal 4 ’ h2 : a s s e r t ( o_led == 6 ’ h2 ) ;
Ź Verification
//
SymbiYosys Tasks
Exercise 4 ’ hb : a s s e r t ( o_led == 6 ’ h1 ) ;
Bonus endcase
Conclusion

always @ ( ∗ )
a s s e r t ( busy != ( state == 0 ) ) ;

always @ ( ∗ )
a s s e r t ( state <= 4 ’ hb ) ;

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 Formal Verification
Lesson Overview What properties might we use?
LED Walker
Diagrams ˝ For our state machine, using $past(X)
Pipeline
Bus
˝ An accepted write should start our cycle
Wishbone Bus
Simulation always @ ( posedge i_clk )
Unused Logic i f ( ( f_past_valid)&&( $past ( i_stb ) )
Sim Exercise
Past Operator
&&($past ( i_we ))&&(! $past ( o_stall ) ) )
Formal begin
Ź Verification
SymbiYosys Tasks a s s e r t ( state == 1 ) ;
Exercise a s s e r t ( busy ) ;
Bonus
Conclusion
end

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 Formal Verification
Lesson Overview What properties might we use?
LED Walker
Diagrams ˝ During the cycle, the state should increment
Pipeline
Bus always @ ( posedge i_clk )
Wishbone Bus
Simulation
i f ( ( f_past_valid)&&( $past ( busy ) )
Unused Logic &&($past ( state < 4 ’ hb ) ) )
Sim Exercise
Past Operator
a s s e r t ( state == $past ( state ) + 1 ) ;
Formal
Ź Verification
SymbiYosys Tasks
Exercise
Bonus
Conclusion

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 Formal Verification
Lesson Overview What properties might we use?
LED Walker
Diagrams ˝ For our bus interface?
Pipeline
Bus // Bus s h o u l d be i d l e i n i t i a l l y
Wishbone Bus
Simulation
i n i t i a l assume ( ! i_cyc ) ;
Unused Logic
Sim Exercise
Past Operator
// i s t b i s o n l y a l l o w e d i f i c y c
Formal always @ ( ∗ )
Ź Verification
i f ( ! i_cyc )
SymbiYosys Tasks
Exercise assume ( ! i_stb ) ;
Bonus
Conclusion
// When i c y c g o e s h i g h , s o t o o d o e s i s t b
always @ ( posedge i_clk )
i f ( ( ! $past ( i_cyc ))&&( i_cyc ) )
assume ( i_stb ) ;

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 Formal Verification
Lesson Overview What properties might we use?
LED Walker
Diagrams ˝ For our bus interface?
Pipeline
Bus always @ ( posedge i_clk )
Wishbone Bus
Simulation
i f ( ( f_past_valid)&&( $past ( i_stb ) )
Unused Logic &&($past ( o_stall ) ) )
Sim Exercise
Past Operator
begin
Formal // R e q u e s t i s s t a l l e d
Ź Verification
// I t s h o u l d n ’ t c h a n ge
SymbiYosys Tasks
Exercise assume ( i_stb ) ;
Bonus assume ( i_we == $past ( i_we ) ) ;
Conclusion
assume ( i_addr == $past ( i_addr ) ) ;
i f ( i_we )
assume ( i_data == $past ( i_data ) ) ;
end

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 Formal Verification
Lesson Overview What properties might we use?
LED Walker
Diagrams ˝ For our bus interface?
Pipeline
Bus always @ ( posedge i_clk )
Wishbone Bus
Simulation
i f ( ( f_past_valid)&&( $past ( i_stb ) )
Unused Logic &&(! $past ( o_stall ) ) )
Sim Exercise
Past Operator
a s s e r t ( o_ack ) ;
Formal
Ź Verification
SymbiYosys Tasks
Exercise
Bonus
Conclusion

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 Cover Property
Lesson Overview You can also use $past with cover
LED Walker
Diagrams always @ ( posedge i_clk )
Pipeline
Bus
i f ( f_past_valid )
Wishbone Bus cover ( ( ! busy)&&( $past ( busy ) ) ) ;
Simulation
Unused Logic
Sim Exercise
Past Operator
Formal
Ź Verification
SymbiYosys Tasks
Exercise
Bonus
Conclusion

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 SymbiYosys Tasks
Lesson Overview Constantly editing our SymbiYosys file is getting old
LED Walker
Diagrams ˝ Running cover, then
Pipeline
Bus
˝ Editing our script, then
Wishbone Bus ˝ Running induction, then . . .
Simulation
Unused Logic ˝ Can we do this with one file?
Sim Exercise
Past Operator Yes, using SymbiYosys tasks!
Formal Verification

Ź
SymbiYosys
Tasks
˝ SymbiYosys allows us to define multiple different scripts
Exercise ˝ . . . all in the same file
Bonus
Conclusion ˝ It does this using tasks

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 SymbiYosys Tasks
Lesson Overview Let’s define two tasks
LED Walker
Diagrams ˝ cvr to run cover
Pipeline
Bus
˝ prf to run induction
Wishbone Bus
Simulation SymbiYosys lines prefixed by a task name are specific to that task
Unused Logic
Sim Exercise [ tasks ]
Past Operator
prf
Formal Verification
SymbiYosys cvr
Ź Tasks
Exercise
Bonus [ options ]
Conclusion
cvr : mode cover
prf : mode prove

The full reqwalker.sby file is with the course handouts

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 SymbiYosys Tasks
Lesson Overview We can now run a named task
LED Walker
Diagrams % sby -f reqwalker . sby prf
Pipeline
Bus
Wishbone Bus . . . or all tasks in sequence
Simulation
Unused Logic % sby -f reqwalker . sby
Sim Exercise
Past Operator
Formal Verification
SymbiYosys
Ź Tasks
Exercise
Bonus
Conclusion

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 SymbiYosys Tasks
Lesson Overview I use this often with the ZipCPU
LED Walker
Diagrams ˝ Using the yosys command hierarchy I can describe multiple
Pipeline
Bus
configurations to verify
Wishbone Bus
Simulation – With/Without the pipeline
Unused Logic
Sim Exercise
– With/Without the instruction cache
Past Operator – With/Without the data cache
Formal Verification
SymbiYosys . . . , etc.
Ź Tasks
Exercise ˝ SymbiYosys tasks are very useful!
Bonus
Conclusion

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 Exercise
Lesson Overview Your turn! Formally verify this design
LED Walker
Diagrams ˝ Build and create a SymbiYosys script
Pipeline
Bus
˝ Apply to the example design
Wishbone Bus ˝ Adjust the design until it passes
Simulation
Unused Logic
Sim Exercise
– Did you find any bugs?
Past Operator – Why weren’t these bugs caught in simulation?
Formal Verification
SymbiYosys Tasks
Ź Exercise
Bonus
Conclusion

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 Exercise
Lesson Overview Your turn to design
LED Walker
Diagrams ˝ Add the integer clock divider to this design
Pipeline
Bus (Otherwise you’d never see the LED’s change on real
Wishbone Bus
Simulation hardware)
Unused Logic
Sim Exercise ˝ Adjust both simulator and formal properties
Past Operator
Formal Verification
˝ Create a simulation trace
SymbiYosys Tasks ˝ Create a cover trace
Ź Exercise
Bonus Do they match?
Conclusion

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 Bonus
Lesson Overview Bonus: If you have hardware with more than one LED . . .
LED Walker
Diagrams ˝ Adjust the number of LED’s to match your hardware
Pipeline
Bus
˝ Create an i_btn input and connect it to a button
Wishbone Bus ˝ Replace the i_stb input with the logic below
Simulation
Unused Logic
reg stb ;
Sim Exercise
Past Operator i n i t i a l stb = 0 ;
Formal Verification always @ ( posedge i_clk )
SymbiYosys Tasks
Exercise
i f ( i_btn )
Ź Bonus stb <= 1 ’ b1 ;
Conclusion
e l s e i f ( ! busy )
stb <= 1 ’ b0 ;

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 Bonus
Lesson Overview Bonus: If you have hardware with more than one LED
LED Walker
Diagrams ˝ Adjust the number of LED’s to match your hardware
Pipeline
Bus
˝ Create an i_btn input and connect it to a button
Wishbone Bus ˝ Replace the i_stb input with the given logic
Simulation
Unused Logic ˝ Tie i_we high
Sim Exercise
Past Operator
˝ Ignore o_stall, i_cyc, etc.
Formal Verification You’ll need to adjust the formal properties
SymbiYosys Tasks
Exercise
You should still be able to simulate it
Ź Bonus ˝ Simulate this updated design
Conclusion
˝ Implement it on your hardware
– Did it do what you expected? Why or why not?
– Does the LED walk back and forth when you press the
button?
It should!
It might not work reliably . . . yet

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 Conclusion
Lesson Overview What did we learn this lesson?
LED Walker
Diagrams ˝ Pipeline handshaking, i_request && !o_busy
Pipeline
Bus
˝ State transition diagrams
Wishbone Bus ˝ Definition of a bus
Simulation
Unused Logic ˝ Logic involved in processing the wishbone bus
Sim Exercise
Past Operator
˝ How to make a wishbone slave
Formal Verification ˝ How to make wishbone bus calls from your Verilator C++
SymbiYosys Tasks
Exercise
driver
Bonus ˝ How to ignore unused logic in Verilator
Ź Conclusion
˝ Verilator requires a call to eval() for combinatorial logic to
settle
˝ The $past operator in formal verification
˝ SymbiYosys tasks

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